2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
135 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
136 module_param(ple_gap
, int, S_IRUGO
);
138 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
139 module_param(ple_window
, int, S_IRUGO
);
141 /* Default doubles per-vcpu window every exit. */
142 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
143 module_param(ple_window_grow
, int, S_IRUGO
);
145 /* Default resets per-vcpu window every exit to ple_window. */
146 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
147 module_param(ple_window_shrink
, int, S_IRUGO
);
149 /* Default is to compute the maximum so we can never overflow. */
150 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
151 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
152 module_param(ple_window_max
, int, S_IRUGO
);
154 extern const ulong vmx_return
;
156 #define NR_AUTOLOAD_MSRS 8
157 #define VMCS02_POOL_SIZE 1
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
174 struct list_head loaded_vmcss_on_cpu_link
;
177 struct shared_msr_entry
{
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
196 typedef u64 natural_width
;
197 struct __packed vmcs12
{
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
204 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding
[7]; /* room for future expansion */
210 u64 vm_exit_msr_store_addr
;
211 u64 vm_exit_msr_load_addr
;
212 u64 vm_entry_msr_load_addr
;
214 u64 virtual_apic_page_addr
;
215 u64 apic_access_addr
;
217 u64 guest_physical_address
;
218 u64 vmcs_link_pointer
;
219 u64 guest_ia32_debugctl
;
222 u64 guest_ia32_perf_global_ctrl
;
230 u64 host_ia32_perf_global_ctrl
;
231 u64 padding64
[8]; /* room for future expansion */
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
238 natural_width cr0_guest_host_mask
;
239 natural_width cr4_guest_host_mask
;
240 natural_width cr0_read_shadow
;
241 natural_width cr4_read_shadow
;
242 natural_width cr3_target_value0
;
243 natural_width cr3_target_value1
;
244 natural_width cr3_target_value2
;
245 natural_width cr3_target_value3
;
246 natural_width exit_qualification
;
247 natural_width guest_linear_address
;
248 natural_width guest_cr0
;
249 natural_width guest_cr3
;
250 natural_width guest_cr4
;
251 natural_width guest_es_base
;
252 natural_width guest_cs_base
;
253 natural_width guest_ss_base
;
254 natural_width guest_ds_base
;
255 natural_width guest_fs_base
;
256 natural_width guest_gs_base
;
257 natural_width guest_ldtr_base
;
258 natural_width guest_tr_base
;
259 natural_width guest_gdtr_base
;
260 natural_width guest_idtr_base
;
261 natural_width guest_dr7
;
262 natural_width guest_rsp
;
263 natural_width guest_rip
;
264 natural_width guest_rflags
;
265 natural_width guest_pending_dbg_exceptions
;
266 natural_width guest_sysenter_esp
;
267 natural_width guest_sysenter_eip
;
268 natural_width host_cr0
;
269 natural_width host_cr3
;
270 natural_width host_cr4
;
271 natural_width host_fs_base
;
272 natural_width host_gs_base
;
273 natural_width host_tr_base
;
274 natural_width host_gdtr_base
;
275 natural_width host_idtr_base
;
276 natural_width host_ia32_sysenter_esp
;
277 natural_width host_ia32_sysenter_eip
;
278 natural_width host_rsp
;
279 natural_width host_rip
;
280 natural_width paddingl
[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control
;
282 u32 cpu_based_vm_exec_control
;
283 u32 exception_bitmap
;
284 u32 page_fault_error_code_mask
;
285 u32 page_fault_error_code_match
;
286 u32 cr3_target_count
;
287 u32 vm_exit_controls
;
288 u32 vm_exit_msr_store_count
;
289 u32 vm_exit_msr_load_count
;
290 u32 vm_entry_controls
;
291 u32 vm_entry_msr_load_count
;
292 u32 vm_entry_intr_info_field
;
293 u32 vm_entry_exception_error_code
;
294 u32 vm_entry_instruction_len
;
296 u32 secondary_vm_exec_control
;
297 u32 vm_instruction_error
;
299 u32 vm_exit_intr_info
;
300 u32 vm_exit_intr_error_code
;
301 u32 idt_vectoring_info_field
;
302 u32 idt_vectoring_error_code
;
303 u32 vm_exit_instruction_len
;
304 u32 vmx_instruction_info
;
311 u32 guest_ldtr_limit
;
313 u32 guest_gdtr_limit
;
314 u32 guest_idtr_limit
;
315 u32 guest_es_ar_bytes
;
316 u32 guest_cs_ar_bytes
;
317 u32 guest_ss_ar_bytes
;
318 u32 guest_ds_ar_bytes
;
319 u32 guest_fs_ar_bytes
;
320 u32 guest_gs_ar_bytes
;
321 u32 guest_ldtr_ar_bytes
;
322 u32 guest_tr_ar_bytes
;
323 u32 guest_interruptibility_info
;
324 u32 guest_activity_state
;
325 u32 guest_sysenter_cs
;
326 u32 host_ia32_sysenter_cs
;
327 u32 vmx_preemption_timer_value
;
328 u32 padding32
[7]; /* room for future expansion */
329 u16 virtual_processor_id
;
330 u16 guest_es_selector
;
331 u16 guest_cs_selector
;
332 u16 guest_ss_selector
;
333 u16 guest_ds_selector
;
334 u16 guest_fs_selector
;
335 u16 guest_gs_selector
;
336 u16 guest_ldtr_selector
;
337 u16 guest_tr_selector
;
338 u16 host_es_selector
;
339 u16 host_cs_selector
;
340 u16 host_ss_selector
;
341 u16 host_ds_selector
;
342 u16 host_fs_selector
;
343 u16 host_gs_selector
;
344 u16 host_tr_selector
;
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
352 #define VMCS12_REVISION 0x11e57ed0
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
359 #define VMCS12_SIZE 0x1000
361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
363 struct list_head list
;
365 struct loaded_vmcs vmcs02
;
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
373 /* Has the level1 guest done vmxon? */
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
379 /* The host-usable pointer to the above */
380 struct page
*current_vmcs12_page
;
381 struct vmcs12
*current_vmcs12
;
382 struct vmcs
*current_shadow_vmcs
;
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
387 bool sync_shadow_vmcs
;
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool
;
392 u64 vmcs01_tsc_offset
;
393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending
;
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
399 struct page
*apic_access_page
;
400 struct page
*virtual_apic_page
;
401 u64 msr_ia32_feature_control
;
403 struct hrtimer preemption_timer
;
404 bool preemption_timer_expired
;
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
410 #define POSTED_INTR_ON 0
411 /* Posted-Interrupt Descriptor */
413 u32 pir
[8]; /* Posted interrupt requested */
414 u32 control
; /* bit 0 of control is outstanding notification bit */
418 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
420 return test_and_set_bit(POSTED_INTR_ON
,
421 (unsigned long *)&pi_desc
->control
);
424 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
426 return test_and_clear_bit(POSTED_INTR_ON
,
427 (unsigned long *)&pi_desc
->control
);
430 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
432 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
436 struct kvm_vcpu vcpu
;
437 unsigned long host_rsp
;
439 bool nmi_known_unmasked
;
441 u32 idt_vectoring_info
;
443 struct shared_msr_entry
*guest_msrs
;
446 unsigned long host_idt_base
;
448 u64 msr_host_kernel_gs_base
;
449 u64 msr_guest_kernel_gs_base
;
451 u32 vm_entry_controls_shadow
;
452 u32 vm_exit_controls_shadow
;
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
458 struct loaded_vmcs vmcs01
;
459 struct loaded_vmcs
*loaded_vmcs
;
460 bool __launched
; /* temporary, used in vmx_vcpu_run */
461 struct msr_autoload
{
463 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
464 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
468 u16 fs_sel
, gs_sel
, ldt_sel
;
472 int gs_ldt_reload_needed
;
473 int fs_reload_needed
;
474 u64 msr_host_bndcfgs
;
475 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
480 struct kvm_segment segs
[8];
483 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
484 struct kvm_save_segment
{
492 bool emulation_required
;
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked
;
497 s64 vnmi_blocked_time
;
502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc
;
505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested
;
508 /* Dynamic PLE window. */
510 bool ple_window_dirty
;
513 enum segment_cache_field
{
522 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
524 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
527 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
533 static unsigned long shadow_read_only_fields
[] = {
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
548 VM_EXIT_INSTRUCTION_LEN
,
549 IDT_VECTORING_INFO_FIELD
,
550 IDT_VECTORING_ERROR_CODE
,
551 VM_EXIT_INTR_ERROR_CODE
,
553 GUEST_LINEAR_ADDRESS
,
554 GUEST_PHYSICAL_ADDRESS
556 static int max_shadow_read_only_fields
=
557 ARRAY_SIZE(shadow_read_only_fields
);
559 static unsigned long shadow_read_write_fields
[] = {
566 GUEST_INTERRUPTIBILITY_INFO
,
579 CPU_BASED_VM_EXEC_CONTROL
,
580 VM_ENTRY_EXCEPTION_ERROR_CODE
,
581 VM_ENTRY_INTR_INFO_FIELD
,
582 VM_ENTRY_INSTRUCTION_LEN
,
583 VM_ENTRY_EXCEPTION_ERROR_CODE
,
589 static int max_shadow_read_write_fields
=
590 ARRAY_SIZE(shadow_read_write_fields
);
592 static const unsigned short vmcs_field_to_offset_table
[] = {
593 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
594 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
595 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
596 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
597 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
598 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
599 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
600 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
601 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
602 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
603 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
604 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
605 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
606 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
607 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
608 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
609 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
610 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
611 FIELD64(MSR_BITMAP
, msr_bitmap
),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
615 FIELD64(TSC_OFFSET
, tsc_offset
),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
617 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
618 FIELD64(EPT_POINTER
, ept_pointer
),
619 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
620 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
621 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
622 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
623 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
625 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
626 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
627 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
628 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
629 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
630 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
631 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
635 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
638 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
639 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
640 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
642 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
647 FIELD(TPR_THRESHOLD
, tpr_threshold
),
648 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
649 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
650 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
651 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
652 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
653 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
654 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
655 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
656 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
657 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
658 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
659 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
660 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
661 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
662 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
663 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
664 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
665 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
666 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
667 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
668 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
669 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
670 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
671 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
672 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
673 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
674 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
676 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
677 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
678 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
679 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
680 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
681 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
682 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
683 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
684 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
685 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
686 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
687 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
688 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
689 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
690 FIELD(GUEST_CR0
, guest_cr0
),
691 FIELD(GUEST_CR3
, guest_cr3
),
692 FIELD(GUEST_CR4
, guest_cr4
),
693 FIELD(GUEST_ES_BASE
, guest_es_base
),
694 FIELD(GUEST_CS_BASE
, guest_cs_base
),
695 FIELD(GUEST_SS_BASE
, guest_ss_base
),
696 FIELD(GUEST_DS_BASE
, guest_ds_base
),
697 FIELD(GUEST_FS_BASE
, guest_fs_base
),
698 FIELD(GUEST_GS_BASE
, guest_gs_base
),
699 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
700 FIELD(GUEST_TR_BASE
, guest_tr_base
),
701 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
702 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
703 FIELD(GUEST_DR7
, guest_dr7
),
704 FIELD(GUEST_RSP
, guest_rsp
),
705 FIELD(GUEST_RIP
, guest_rip
),
706 FIELD(GUEST_RFLAGS
, guest_rflags
),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
708 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
709 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
710 FIELD(HOST_CR0
, host_cr0
),
711 FIELD(HOST_CR3
, host_cr3
),
712 FIELD(HOST_CR4
, host_cr4
),
713 FIELD(HOST_FS_BASE
, host_fs_base
),
714 FIELD(HOST_GS_BASE
, host_gs_base
),
715 FIELD(HOST_TR_BASE
, host_tr_base
),
716 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
717 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
718 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
719 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
720 FIELD(HOST_RSP
, host_rsp
),
721 FIELD(HOST_RIP
, host_rip
),
724 static inline short vmcs_field_to_offset(unsigned long field
)
726 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
728 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
729 vmcs_field_to_offset_table
[field
] == 0)
732 return vmcs_field_to_offset_table
[field
];
735 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
737 return to_vmx(vcpu
)->nested
.current_vmcs12
;
740 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
742 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
743 if (is_error_page(page
))
749 static void nested_release_page(struct page
*page
)
751 kvm_release_page_dirty(page
);
754 static void nested_release_page_clean(struct page
*page
)
756 kvm_release_page_clean(page
);
759 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
760 static u64
construct_eptp(unsigned long root_hpa
);
761 static void kvm_cpu_vmxon(u64 addr
);
762 static void kvm_cpu_vmxoff(void);
763 static bool vmx_mpx_supported(void);
764 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
765 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
766 struct kvm_segment
*var
, int seg
);
767 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
768 struct kvm_segment
*var
, int seg
);
769 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
770 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
771 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
772 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
773 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
774 static int alloc_identity_pagetable(struct kvm
*kvm
);
776 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
777 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
779 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
780 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
782 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
783 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
785 static unsigned long *vmx_io_bitmap_a
;
786 static unsigned long *vmx_io_bitmap_b
;
787 static unsigned long *vmx_msr_bitmap_legacy
;
788 static unsigned long *vmx_msr_bitmap_longmode
;
789 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
790 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
791 static unsigned long *vmx_vmread_bitmap
;
792 static unsigned long *vmx_vmwrite_bitmap
;
794 static bool cpu_has_load_ia32_efer
;
795 static bool cpu_has_load_perf_global_ctrl
;
797 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
798 static DEFINE_SPINLOCK(vmx_vpid_lock
);
800 static struct vmcs_config
{
804 u32 pin_based_exec_ctrl
;
805 u32 cpu_based_exec_ctrl
;
806 u32 cpu_based_2nd_exec_ctrl
;
811 static struct vmx_capability
{
816 #define VMX_SEGMENT_FIELD(seg) \
817 [VCPU_SREG_##seg] = { \
818 .selector = GUEST_##seg##_SELECTOR, \
819 .base = GUEST_##seg##_BASE, \
820 .limit = GUEST_##seg##_LIMIT, \
821 .ar_bytes = GUEST_##seg##_AR_BYTES, \
824 static const struct kvm_vmx_segment_field
{
829 } kvm_vmx_segment_fields
[] = {
830 VMX_SEGMENT_FIELD(CS
),
831 VMX_SEGMENT_FIELD(DS
),
832 VMX_SEGMENT_FIELD(ES
),
833 VMX_SEGMENT_FIELD(FS
),
834 VMX_SEGMENT_FIELD(GS
),
835 VMX_SEGMENT_FIELD(SS
),
836 VMX_SEGMENT_FIELD(TR
),
837 VMX_SEGMENT_FIELD(LDTR
),
840 static u64 host_efer
;
842 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
845 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
846 * away by decrementing the array size.
848 static const u32 vmx_msr_index
[] = {
850 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
852 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
855 static inline bool is_page_fault(u32 intr_info
)
857 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
858 INTR_INFO_VALID_MASK
)) ==
859 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
862 static inline bool is_no_device(u32 intr_info
)
864 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
865 INTR_INFO_VALID_MASK
)) ==
866 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
869 static inline bool is_invalid_opcode(u32 intr_info
)
871 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
872 INTR_INFO_VALID_MASK
)) ==
873 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
876 static inline bool is_external_interrupt(u32 intr_info
)
878 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
879 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
882 static inline bool is_machine_check(u32 intr_info
)
884 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
885 INTR_INFO_VALID_MASK
)) ==
886 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
889 static inline bool cpu_has_vmx_msr_bitmap(void)
891 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
894 static inline bool cpu_has_vmx_tpr_shadow(void)
896 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
899 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
901 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
904 static inline bool cpu_has_secondary_exec_ctrls(void)
906 return vmcs_config
.cpu_based_exec_ctrl
&
907 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
910 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
912 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
913 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
916 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
918 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
919 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
922 static inline bool cpu_has_vmx_apic_register_virt(void)
924 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
925 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
928 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
930 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
931 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
934 static inline bool cpu_has_vmx_posted_intr(void)
936 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
939 static inline bool cpu_has_vmx_apicv(void)
941 return cpu_has_vmx_apic_register_virt() &&
942 cpu_has_vmx_virtual_intr_delivery() &&
943 cpu_has_vmx_posted_intr();
946 static inline bool cpu_has_vmx_flexpriority(void)
948 return cpu_has_vmx_tpr_shadow() &&
949 cpu_has_vmx_virtualize_apic_accesses();
952 static inline bool cpu_has_vmx_ept_execute_only(void)
954 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
957 static inline bool cpu_has_vmx_eptp_uncacheable(void)
959 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
962 static inline bool cpu_has_vmx_eptp_writeback(void)
964 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
967 static inline bool cpu_has_vmx_ept_2m_page(void)
969 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
972 static inline bool cpu_has_vmx_ept_1g_page(void)
974 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
977 static inline bool cpu_has_vmx_ept_4levels(void)
979 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
982 static inline bool cpu_has_vmx_ept_ad_bits(void)
984 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
987 static inline bool cpu_has_vmx_invept_context(void)
989 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
992 static inline bool cpu_has_vmx_invept_global(void)
994 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
997 static inline bool cpu_has_vmx_invvpid_single(void)
999 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1002 static inline bool cpu_has_vmx_invvpid_global(void)
1004 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1007 static inline bool cpu_has_vmx_ept(void)
1009 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1010 SECONDARY_EXEC_ENABLE_EPT
;
1013 static inline bool cpu_has_vmx_unrestricted_guest(void)
1015 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1016 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1019 static inline bool cpu_has_vmx_ple(void)
1021 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1022 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1025 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1027 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1030 static inline bool cpu_has_vmx_vpid(void)
1032 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1033 SECONDARY_EXEC_ENABLE_VPID
;
1036 static inline bool cpu_has_vmx_rdtscp(void)
1038 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1039 SECONDARY_EXEC_RDTSCP
;
1042 static inline bool cpu_has_vmx_invpcid(void)
1044 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1045 SECONDARY_EXEC_ENABLE_INVPCID
;
1048 static inline bool cpu_has_virtual_nmis(void)
1050 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1053 static inline bool cpu_has_vmx_wbinvd_exit(void)
1055 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1056 SECONDARY_EXEC_WBINVD_EXITING
;
1059 static inline bool cpu_has_vmx_shadow_vmcs(void)
1062 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1063 /* check if the cpu supports writing r/o exit information fields */
1064 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1067 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1068 SECONDARY_EXEC_SHADOW_VMCS
;
1071 static inline bool report_flexpriority(void)
1073 return flexpriority_enabled
;
1076 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1078 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1081 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1083 return (vmcs12
->cpu_based_vm_exec_control
&
1084 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1085 (vmcs12
->secondary_vm_exec_control
& bit
);
1088 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1090 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1093 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1095 return vmcs12
->pin_based_vm_exec_control
&
1096 PIN_BASED_VMX_PREEMPTION_TIMER
;
1099 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1101 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1104 static inline bool is_exception(u32 intr_info
)
1106 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1107 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1110 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1112 unsigned long exit_qualification
);
1113 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1114 struct vmcs12
*vmcs12
,
1115 u32 reason
, unsigned long qualification
);
1117 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1121 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1122 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1127 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1133 } operand
= { vpid
, 0, gva
};
1135 asm volatile (__ex(ASM_VMX_INVVPID
)
1136 /* CF==1 or ZF==1 --> rc = -1 */
1137 "; ja 1f ; ud2 ; 1:"
1138 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1141 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1145 } operand
= {eptp
, gpa
};
1147 asm volatile (__ex(ASM_VMX_INVEPT
)
1148 /* CF==1 or ZF==1 --> rc = -1 */
1149 "; ja 1f ; ud2 ; 1:\n"
1150 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1153 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1157 i
= __find_msr_index(vmx
, msr
);
1159 return &vmx
->guest_msrs
[i
];
1163 static void vmcs_clear(struct vmcs
*vmcs
)
1165 u64 phys_addr
= __pa(vmcs
);
1168 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1169 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1172 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1176 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1178 vmcs_clear(loaded_vmcs
->vmcs
);
1179 loaded_vmcs
->cpu
= -1;
1180 loaded_vmcs
->launched
= 0;
1183 static void vmcs_load(struct vmcs
*vmcs
)
1185 u64 phys_addr
= __pa(vmcs
);
1188 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1189 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1192 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1198 * This bitmap is used to indicate whether the vmclear
1199 * operation is enabled on all cpus. All disabled by
1202 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1204 static inline void crash_enable_local_vmclear(int cpu
)
1206 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1209 static inline void crash_disable_local_vmclear(int cpu
)
1211 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1214 static inline int crash_local_vmclear_enabled(int cpu
)
1216 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1219 static void crash_vmclear_local_loaded_vmcss(void)
1221 int cpu
= raw_smp_processor_id();
1222 struct loaded_vmcs
*v
;
1224 if (!crash_local_vmclear_enabled(cpu
))
1227 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1228 loaded_vmcss_on_cpu_link
)
1229 vmcs_clear(v
->vmcs
);
1232 static inline void crash_enable_local_vmclear(int cpu
) { }
1233 static inline void crash_disable_local_vmclear(int cpu
) { }
1234 #endif /* CONFIG_KEXEC */
1236 static void __loaded_vmcs_clear(void *arg
)
1238 struct loaded_vmcs
*loaded_vmcs
= arg
;
1239 int cpu
= raw_smp_processor_id();
1241 if (loaded_vmcs
->cpu
!= cpu
)
1242 return; /* vcpu migration can race with cpu offline */
1243 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1244 per_cpu(current_vmcs
, cpu
) = NULL
;
1245 crash_disable_local_vmclear(cpu
);
1246 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1249 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250 * is before setting loaded_vmcs->vcpu to -1 which is done in
1251 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252 * then adds the vmcs into percpu list before it is deleted.
1256 loaded_vmcs_init(loaded_vmcs
);
1257 crash_enable_local_vmclear(cpu
);
1260 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1262 int cpu
= loaded_vmcs
->cpu
;
1265 smp_call_function_single(cpu
,
1266 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1269 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1274 if (cpu_has_vmx_invvpid_single())
1275 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1278 static inline void vpid_sync_vcpu_global(void)
1280 if (cpu_has_vmx_invvpid_global())
1281 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1284 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1286 if (cpu_has_vmx_invvpid_single())
1287 vpid_sync_vcpu_single(vmx
);
1289 vpid_sync_vcpu_global();
1292 static inline void ept_sync_global(void)
1294 if (cpu_has_vmx_invept_global())
1295 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1298 static inline void ept_sync_context(u64 eptp
)
1301 if (cpu_has_vmx_invept_context())
1302 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1308 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1310 unsigned long value
;
1312 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1313 : "=a"(value
) : "d"(field
) : "cc");
1317 static __always_inline u16
vmcs_read16(unsigned long field
)
1319 return vmcs_readl(field
);
1322 static __always_inline u32
vmcs_read32(unsigned long field
)
1324 return vmcs_readl(field
);
1327 static __always_inline u64
vmcs_read64(unsigned long field
)
1329 #ifdef CONFIG_X86_64
1330 return vmcs_readl(field
);
1332 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1336 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1338 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1339 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1343 static void vmcs_writel(unsigned long field
, unsigned long value
)
1347 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1348 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1349 if (unlikely(error
))
1350 vmwrite_error(field
, value
);
1353 static void vmcs_write16(unsigned long field
, u16 value
)
1355 vmcs_writel(field
, value
);
1358 static void vmcs_write32(unsigned long field
, u32 value
)
1360 vmcs_writel(field
, value
);
1363 static void vmcs_write64(unsigned long field
, u64 value
)
1365 vmcs_writel(field
, value
);
1366 #ifndef CONFIG_X86_64
1368 vmcs_writel(field
+1, value
>> 32);
1372 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1374 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1377 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1379 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1382 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1384 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1385 vmx
->vm_entry_controls_shadow
= val
;
1388 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1390 if (vmx
->vm_entry_controls_shadow
!= val
)
1391 vm_entry_controls_init(vmx
, val
);
1394 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1396 return vmx
->vm_entry_controls_shadow
;
1400 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1402 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1405 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1407 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1410 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1412 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1413 vmx
->vm_exit_controls_shadow
= val
;
1416 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1418 if (vmx
->vm_exit_controls_shadow
!= val
)
1419 vm_exit_controls_init(vmx
, val
);
1422 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1424 return vmx
->vm_exit_controls_shadow
;
1428 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1430 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1433 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1435 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1438 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1440 vmx
->segment_cache
.bitmask
= 0;
1443 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1447 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1449 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1450 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1451 vmx
->segment_cache
.bitmask
= 0;
1453 ret
= vmx
->segment_cache
.bitmask
& mask
;
1454 vmx
->segment_cache
.bitmask
|= mask
;
1458 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1460 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1462 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1463 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1467 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1469 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1471 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1472 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1476 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1478 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1480 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1481 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1485 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1487 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1489 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1490 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1494 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1498 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1499 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1500 if ((vcpu
->guest_debug
&
1501 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1502 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1503 eb
|= 1u << BP_VECTOR
;
1504 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1507 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1508 if (vcpu
->fpu_active
)
1509 eb
&= ~(1u << NM_VECTOR
);
1511 /* When we are running a nested L2 guest and L1 specified for it a
1512 * certain exception bitmap, we must trap the same exceptions and pass
1513 * them to L1. When running L2, we will only handle the exceptions
1514 * specified above if L1 did not want them.
1516 if (is_guest_mode(vcpu
))
1517 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1519 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1522 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1523 unsigned long entry
, unsigned long exit
)
1525 vm_entry_controls_clearbit(vmx
, entry
);
1526 vm_exit_controls_clearbit(vmx
, exit
);
1529 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1532 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1536 if (cpu_has_load_ia32_efer
) {
1537 clear_atomic_switch_msr_special(vmx
,
1538 VM_ENTRY_LOAD_IA32_EFER
,
1539 VM_EXIT_LOAD_IA32_EFER
);
1543 case MSR_CORE_PERF_GLOBAL_CTRL
:
1544 if (cpu_has_load_perf_global_ctrl
) {
1545 clear_atomic_switch_msr_special(vmx
,
1546 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1547 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1553 for (i
= 0; i
< m
->nr
; ++i
)
1554 if (m
->guest
[i
].index
== msr
)
1560 m
->guest
[i
] = m
->guest
[m
->nr
];
1561 m
->host
[i
] = m
->host
[m
->nr
];
1562 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1563 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1566 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1567 unsigned long entry
, unsigned long exit
,
1568 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1569 u64 guest_val
, u64 host_val
)
1571 vmcs_write64(guest_val_vmcs
, guest_val
);
1572 vmcs_write64(host_val_vmcs
, host_val
);
1573 vm_entry_controls_setbit(vmx
, entry
);
1574 vm_exit_controls_setbit(vmx
, exit
);
1577 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1578 u64 guest_val
, u64 host_val
)
1581 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1585 if (cpu_has_load_ia32_efer
) {
1586 add_atomic_switch_msr_special(vmx
,
1587 VM_ENTRY_LOAD_IA32_EFER
,
1588 VM_EXIT_LOAD_IA32_EFER
,
1591 guest_val
, host_val
);
1595 case MSR_CORE_PERF_GLOBAL_CTRL
:
1596 if (cpu_has_load_perf_global_ctrl
) {
1597 add_atomic_switch_msr_special(vmx
,
1598 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1599 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1600 GUEST_IA32_PERF_GLOBAL_CTRL
,
1601 HOST_IA32_PERF_GLOBAL_CTRL
,
1602 guest_val
, host_val
);
1608 for (i
= 0; i
< m
->nr
; ++i
)
1609 if (m
->guest
[i
].index
== msr
)
1612 if (i
== NR_AUTOLOAD_MSRS
) {
1613 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1614 "Can't add msr %x\n", msr
);
1616 } else if (i
== m
->nr
) {
1618 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1619 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1622 m
->guest
[i
].index
= msr
;
1623 m
->guest
[i
].value
= guest_val
;
1624 m
->host
[i
].index
= msr
;
1625 m
->host
[i
].value
= host_val
;
1628 static void reload_tss(void)
1631 * VT restores TR but not its size. Useless.
1633 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1634 struct desc_struct
*descs
;
1636 descs
= (void *)gdt
->address
;
1637 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1641 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1646 guest_efer
= vmx
->vcpu
.arch
.efer
;
1649 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1652 ignore_bits
= EFER_NX
| EFER_SCE
;
1653 #ifdef CONFIG_X86_64
1654 ignore_bits
|= EFER_LMA
| EFER_LME
;
1655 /* SCE is meaningful only in long mode on Intel */
1656 if (guest_efer
& EFER_LMA
)
1657 ignore_bits
&= ~(u64
)EFER_SCE
;
1659 guest_efer
&= ~ignore_bits
;
1660 guest_efer
|= host_efer
& ignore_bits
;
1661 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1662 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1664 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1665 /* On ept, can't emulate nx, and must switch nx atomically */
1666 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1667 guest_efer
= vmx
->vcpu
.arch
.efer
;
1668 if (!(guest_efer
& EFER_LMA
))
1669 guest_efer
&= ~EFER_LME
;
1670 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1677 static unsigned long segment_base(u16 selector
)
1679 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1680 struct desc_struct
*d
;
1681 unsigned long table_base
;
1684 if (!(selector
& ~3))
1687 table_base
= gdt
->address
;
1689 if (selector
& 4) { /* from ldt */
1690 u16 ldt_selector
= kvm_read_ldt();
1692 if (!(ldt_selector
& ~3))
1695 table_base
= segment_base(ldt_selector
);
1697 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1698 v
= get_desc_base(d
);
1699 #ifdef CONFIG_X86_64
1700 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1701 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1706 static inline unsigned long kvm_read_tr_base(void)
1709 asm("str %0" : "=g"(tr
));
1710 return segment_base(tr
);
1713 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1715 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1718 if (vmx
->host_state
.loaded
)
1721 vmx
->host_state
.loaded
= 1;
1723 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1724 * allow segment selectors with cpl > 0 or ti == 1.
1726 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1727 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1728 savesegment(fs
, vmx
->host_state
.fs_sel
);
1729 if (!(vmx
->host_state
.fs_sel
& 7)) {
1730 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1731 vmx
->host_state
.fs_reload_needed
= 0;
1733 vmcs_write16(HOST_FS_SELECTOR
, 0);
1734 vmx
->host_state
.fs_reload_needed
= 1;
1736 savesegment(gs
, vmx
->host_state
.gs_sel
);
1737 if (!(vmx
->host_state
.gs_sel
& 7))
1738 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1740 vmcs_write16(HOST_GS_SELECTOR
, 0);
1741 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1744 #ifdef CONFIG_X86_64
1745 savesegment(ds
, vmx
->host_state
.ds_sel
);
1746 savesegment(es
, vmx
->host_state
.es_sel
);
1749 #ifdef CONFIG_X86_64
1750 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1751 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1753 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1754 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1757 #ifdef CONFIG_X86_64
1758 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1759 if (is_long_mode(&vmx
->vcpu
))
1760 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1762 if (boot_cpu_has(X86_FEATURE_MPX
))
1763 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1764 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1765 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1766 vmx
->guest_msrs
[i
].data
,
1767 vmx
->guest_msrs
[i
].mask
);
1770 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1772 if (!vmx
->host_state
.loaded
)
1775 ++vmx
->vcpu
.stat
.host_state_reload
;
1776 vmx
->host_state
.loaded
= 0;
1777 #ifdef CONFIG_X86_64
1778 if (is_long_mode(&vmx
->vcpu
))
1779 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1781 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1782 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1783 #ifdef CONFIG_X86_64
1784 load_gs_index(vmx
->host_state
.gs_sel
);
1786 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1789 if (vmx
->host_state
.fs_reload_needed
)
1790 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1791 #ifdef CONFIG_X86_64
1792 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1793 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1794 loadsegment(es
, vmx
->host_state
.es_sel
);
1798 #ifdef CONFIG_X86_64
1799 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1801 if (vmx
->host_state
.msr_host_bndcfgs
)
1802 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1804 * If the FPU is not active (through the host task or
1805 * the guest vcpu), then restore the cr0.TS bit.
1807 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1809 load_gdt(this_cpu_ptr(&host_gdt
));
1812 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1815 __vmx_load_host_state(vmx
);
1820 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1821 * vcpu mutex is already taken.
1823 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1825 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1826 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1829 kvm_cpu_vmxon(phys_addr
);
1830 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1831 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1833 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1834 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1835 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1838 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1839 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1840 unsigned long sysenter_esp
;
1842 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1843 local_irq_disable();
1844 crash_disable_local_vmclear(cpu
);
1847 * Read loaded_vmcs->cpu should be before fetching
1848 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1849 * See the comments in __loaded_vmcs_clear().
1853 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1854 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1855 crash_enable_local_vmclear(cpu
);
1859 * Linux uses per-cpu TSS and GDT, so set these when switching
1862 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1863 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1865 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1866 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1867 vmx
->loaded_vmcs
->cpu
= cpu
;
1871 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1873 __vmx_load_host_state(to_vmx(vcpu
));
1874 if (!vmm_exclusive
) {
1875 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1881 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1885 if (vcpu
->fpu_active
)
1887 vcpu
->fpu_active
= 1;
1888 cr0
= vmcs_readl(GUEST_CR0
);
1889 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1890 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1891 vmcs_writel(GUEST_CR0
, cr0
);
1892 update_exception_bitmap(vcpu
);
1893 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1894 if (is_guest_mode(vcpu
))
1895 vcpu
->arch
.cr0_guest_owned_bits
&=
1896 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1897 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1900 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1903 * Return the cr0 value that a nested guest would read. This is a combination
1904 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1905 * its hypervisor (cr0_read_shadow).
1907 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1909 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1910 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1912 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1914 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1915 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1918 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1920 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1921 * set this *before* calling this function.
1923 vmx_decache_cr0_guest_bits(vcpu
);
1924 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1925 update_exception_bitmap(vcpu
);
1926 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1927 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1928 if (is_guest_mode(vcpu
)) {
1930 * L1's specified read shadow might not contain the TS bit,
1931 * so now that we turned on shadowing of this bit, we need to
1932 * set this bit of the shadow. Like in nested_vmx_run we need
1933 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1934 * up-to-date here because we just decached cr0.TS (and we'll
1935 * only update vmcs12->guest_cr0 on nested exit).
1937 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1938 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1939 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1940 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1942 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1945 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1947 unsigned long rflags
, save_rflags
;
1949 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1950 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1951 rflags
= vmcs_readl(GUEST_RFLAGS
);
1952 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1953 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1954 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1955 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1957 to_vmx(vcpu
)->rflags
= rflags
;
1959 return to_vmx(vcpu
)->rflags
;
1962 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1964 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1965 to_vmx(vcpu
)->rflags
= rflags
;
1966 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1967 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1968 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1970 vmcs_writel(GUEST_RFLAGS
, rflags
);
1973 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1975 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1978 if (interruptibility
& GUEST_INTR_STATE_STI
)
1979 ret
|= KVM_X86_SHADOW_INT_STI
;
1980 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1981 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1986 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1988 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1989 u32 interruptibility
= interruptibility_old
;
1991 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1993 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1994 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1995 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1996 interruptibility
|= GUEST_INTR_STATE_STI
;
1998 if ((interruptibility
!= interruptibility_old
))
1999 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2002 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2006 rip
= kvm_rip_read(vcpu
);
2007 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2008 kvm_rip_write(vcpu
, rip
);
2010 /* skipping an emulated instruction also counts */
2011 vmx_set_interrupt_shadow(vcpu
, 0);
2015 * KVM wants to inject page-faults which it got to the guest. This function
2016 * checks whether in a nested guest, we need to inject them to L1 or L2.
2018 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2020 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2022 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2025 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2026 vmcs_read32(VM_EXIT_INTR_INFO
),
2027 vmcs_readl(EXIT_QUALIFICATION
));
2031 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2032 bool has_error_code
, u32 error_code
,
2035 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2036 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2038 if (!reinject
&& is_guest_mode(vcpu
) &&
2039 nested_vmx_check_exception(vcpu
, nr
))
2042 if (has_error_code
) {
2043 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2044 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2047 if (vmx
->rmode
.vm86_active
) {
2049 if (kvm_exception_is_soft(nr
))
2050 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2051 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2052 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2056 if (kvm_exception_is_soft(nr
)) {
2057 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2058 vmx
->vcpu
.arch
.event_exit_inst_len
);
2059 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2061 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2066 static bool vmx_rdtscp_supported(void)
2068 return cpu_has_vmx_rdtscp();
2071 static bool vmx_invpcid_supported(void)
2073 return cpu_has_vmx_invpcid() && enable_ept
;
2077 * Swap MSR entry in host/guest MSR entry array.
2079 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2081 struct shared_msr_entry tmp
;
2083 tmp
= vmx
->guest_msrs
[to
];
2084 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2085 vmx
->guest_msrs
[from
] = tmp
;
2088 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2090 unsigned long *msr_bitmap
;
2092 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2093 if (is_long_mode(vcpu
))
2094 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2096 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2098 if (is_long_mode(vcpu
))
2099 msr_bitmap
= vmx_msr_bitmap_longmode
;
2101 msr_bitmap
= vmx_msr_bitmap_legacy
;
2104 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2108 * Set up the vmcs to automatically save and restore system
2109 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2110 * mode, as fiddling with msrs is very expensive.
2112 static void setup_msrs(struct vcpu_vmx
*vmx
)
2114 int save_nmsrs
, index
;
2117 #ifdef CONFIG_X86_64
2118 if (is_long_mode(&vmx
->vcpu
)) {
2119 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2121 move_msr_up(vmx
, index
, save_nmsrs
++);
2122 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2124 move_msr_up(vmx
, index
, save_nmsrs
++);
2125 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2127 move_msr_up(vmx
, index
, save_nmsrs
++);
2128 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2129 if (index
>= 0 && vmx
->rdtscp_enabled
)
2130 move_msr_up(vmx
, index
, save_nmsrs
++);
2132 * MSR_STAR is only needed on long mode guests, and only
2133 * if efer.sce is enabled.
2135 index
= __find_msr_index(vmx
, MSR_STAR
);
2136 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2137 move_msr_up(vmx
, index
, save_nmsrs
++);
2140 index
= __find_msr_index(vmx
, MSR_EFER
);
2141 if (index
>= 0 && update_transition_efer(vmx
, index
))
2142 move_msr_up(vmx
, index
, save_nmsrs
++);
2144 vmx
->save_nmsrs
= save_nmsrs
;
2146 if (cpu_has_vmx_msr_bitmap())
2147 vmx_set_msr_bitmap(&vmx
->vcpu
);
2151 * reads and returns guest's timestamp counter "register"
2152 * guest_tsc = host_tsc + tsc_offset -- 21.3
2154 static u64
guest_read_tsc(void)
2156 u64 host_tsc
, tsc_offset
;
2159 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2160 return host_tsc
+ tsc_offset
;
2164 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2165 * counter, even if a nested guest (L2) is currently running.
2167 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2171 tsc_offset
= is_guest_mode(vcpu
) ?
2172 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2173 vmcs_read64(TSC_OFFSET
);
2174 return host_tsc
+ tsc_offset
;
2178 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2179 * software catchup for faster rates on slower CPUs.
2181 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2186 if (user_tsc_khz
> tsc_khz
) {
2187 vcpu
->arch
.tsc_catchup
= 1;
2188 vcpu
->arch
.tsc_always_catchup
= 1;
2190 WARN(1, "user requested TSC rate below hardware speed\n");
2193 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2195 return vmcs_read64(TSC_OFFSET
);
2199 * writes 'offset' into guest's timestamp counter offset register
2201 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2203 if (is_guest_mode(vcpu
)) {
2205 * We're here if L1 chose not to trap WRMSR to TSC. According
2206 * to the spec, this should set L1's TSC; The offset that L1
2207 * set for L2 remains unchanged, and still needs to be added
2208 * to the newly set TSC to get L2's TSC.
2210 struct vmcs12
*vmcs12
;
2211 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2212 /* recalculate vmcs02.TSC_OFFSET: */
2213 vmcs12
= get_vmcs12(vcpu
);
2214 vmcs_write64(TSC_OFFSET
, offset
+
2215 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2216 vmcs12
->tsc_offset
: 0));
2218 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2219 vmcs_read64(TSC_OFFSET
), offset
);
2220 vmcs_write64(TSC_OFFSET
, offset
);
2224 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2226 u64 offset
= vmcs_read64(TSC_OFFSET
);
2228 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2229 if (is_guest_mode(vcpu
)) {
2230 /* Even when running L2, the adjustment needs to apply to L1 */
2231 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2233 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2234 offset
+ adjustment
);
2237 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2239 return target_tsc
- native_read_tsc();
2242 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2244 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2245 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2249 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2250 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2251 * all guests if the "nested" module option is off, and can also be disabled
2252 * for a single guest by disabling its VMX cpuid bit.
2254 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2256 return nested
&& guest_cpuid_has_vmx(vcpu
);
2260 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2261 * returned for the various VMX controls MSRs when nested VMX is enabled.
2262 * The same values should also be used to verify that vmcs12 control fields are
2263 * valid during nested entry from L1 to L2.
2264 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2265 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2266 * bit in the high half is on if the corresponding bit in the control field
2267 * may be on. See also vmx_control_verify().
2268 * TODO: allow these variables to be modified (downgraded) by module options
2271 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2272 static u32 nested_vmx_true_procbased_ctls_low
;
2273 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2274 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2275 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2276 static u32 nested_vmx_true_exit_ctls_low
;
2277 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2278 static u32 nested_vmx_true_entry_ctls_low
;
2279 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2280 static u32 nested_vmx_ept_caps
;
2281 static __init
void nested_vmx_setup_ctls_msrs(void)
2284 * Note that as a general rule, the high half of the MSRs (bits in
2285 * the control fields which may be 1) should be initialized by the
2286 * intersection of the underlying hardware's MSR (i.e., features which
2287 * can be supported) and the list of features we want to expose -
2288 * because they are known to be properly supported in our code.
2289 * Also, usually, the low half of the MSRs (bits which must be 1) can
2290 * be set to 0, meaning that L1 may turn off any of these bits. The
2291 * reason is that if one of these bits is necessary, it will appear
2292 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2293 * fields of vmcs01 and vmcs02, will turn these bits off - and
2294 * nested_vmx_exit_handled() will not pass related exits to L1.
2295 * These rules have exceptions below.
2298 /* pin-based controls */
2299 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2300 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2301 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2302 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2303 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2304 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2305 PIN_BASED_VMX_PREEMPTION_TIMER
;
2308 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2309 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2310 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2312 nested_vmx_exit_ctls_high
&=
2313 #ifdef CONFIG_X86_64
2314 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2316 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2317 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2318 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2319 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2321 if (vmx_mpx_supported())
2322 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2324 /* We support free control of debug control saving. */
2325 nested_vmx_true_exit_ctls_low
= nested_vmx_exit_ctls_low
&
2326 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2328 /* entry controls */
2329 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2330 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2331 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2332 nested_vmx_entry_ctls_high
&=
2333 #ifdef CONFIG_X86_64
2334 VM_ENTRY_IA32E_MODE
|
2336 VM_ENTRY_LOAD_IA32_PAT
;
2337 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2338 VM_ENTRY_LOAD_IA32_EFER
);
2339 if (vmx_mpx_supported())
2340 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2342 /* We support free control of debug control loading. */
2343 nested_vmx_true_entry_ctls_low
= nested_vmx_entry_ctls_low
&
2344 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2346 /* cpu-based controls */
2347 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2348 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2349 nested_vmx_procbased_ctls_low
= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2350 nested_vmx_procbased_ctls_high
&=
2351 CPU_BASED_VIRTUAL_INTR_PENDING
|
2352 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2353 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2354 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2355 CPU_BASED_CR3_STORE_EXITING
|
2356 #ifdef CONFIG_X86_64
2357 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2359 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2360 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2361 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2362 CPU_BASED_PAUSE_EXITING
| CPU_BASED_TPR_SHADOW
|
2363 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2365 * We can allow some features even when not supported by the
2366 * hardware. For example, L1 can specify an MSR bitmap - and we
2367 * can use it to avoid exits to L1 - even when L0 runs L2
2368 * without MSR bitmaps.
2370 nested_vmx_procbased_ctls_high
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2371 CPU_BASED_USE_MSR_BITMAPS
;
2373 /* We support free control of CR3 access interception. */
2374 nested_vmx_true_procbased_ctls_low
= nested_vmx_procbased_ctls_low
&
2375 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2377 /* secondary cpu-based controls */
2378 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2379 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2380 nested_vmx_secondary_ctls_low
= 0;
2381 nested_vmx_secondary_ctls_high
&=
2382 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2383 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2384 SECONDARY_EXEC_WBINVD_EXITING
;
2387 /* nested EPT: emulate EPT also to L1 */
2388 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2389 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2390 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2392 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2394 * For nested guests, we don't do anything specific
2395 * for single context invalidation. Hence, only advertise
2396 * support for global context invalidation.
2398 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2400 nested_vmx_ept_caps
= 0;
2402 /* miscellaneous data */
2403 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2404 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2405 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2406 VMX_MISC_ACTIVITY_HLT
;
2407 nested_vmx_misc_high
= 0;
2410 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2413 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2415 return ((control
& high
) | low
) == control
;
2418 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2420 return low
| ((u64
)high
<< 32);
2423 /* Returns 0 on success, non-0 otherwise. */
2424 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2426 switch (msr_index
) {
2427 case MSR_IA32_VMX_BASIC
:
2429 * This MSR reports some information about VMX support. We
2430 * should return information about the VMX we emulate for the
2431 * guest, and the VMCS structure we give it - not about the
2432 * VMX support of the underlying hardware.
2434 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2435 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2436 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2438 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2439 case MSR_IA32_VMX_PINBASED_CTLS
:
2440 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2441 nested_vmx_pinbased_ctls_high
);
2443 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2444 *pdata
= vmx_control_msr(nested_vmx_true_procbased_ctls_low
,
2445 nested_vmx_procbased_ctls_high
);
2447 case MSR_IA32_VMX_PROCBASED_CTLS
:
2448 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2449 nested_vmx_procbased_ctls_high
);
2451 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2452 *pdata
= vmx_control_msr(nested_vmx_true_exit_ctls_low
,
2453 nested_vmx_exit_ctls_high
);
2455 case MSR_IA32_VMX_EXIT_CTLS
:
2456 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2457 nested_vmx_exit_ctls_high
);
2459 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2460 *pdata
= vmx_control_msr(nested_vmx_true_entry_ctls_low
,
2461 nested_vmx_entry_ctls_high
);
2463 case MSR_IA32_VMX_ENTRY_CTLS
:
2464 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2465 nested_vmx_entry_ctls_high
);
2467 case MSR_IA32_VMX_MISC
:
2468 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2469 nested_vmx_misc_high
);
2472 * These MSRs specify bits which the guest must keep fixed (on or off)
2473 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2474 * We picked the standard core2 setting.
2476 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2477 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2478 case MSR_IA32_VMX_CR0_FIXED0
:
2479 *pdata
= VMXON_CR0_ALWAYSON
;
2481 case MSR_IA32_VMX_CR0_FIXED1
:
2484 case MSR_IA32_VMX_CR4_FIXED0
:
2485 *pdata
= VMXON_CR4_ALWAYSON
;
2487 case MSR_IA32_VMX_CR4_FIXED1
:
2490 case MSR_IA32_VMX_VMCS_ENUM
:
2491 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2493 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2494 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2495 nested_vmx_secondary_ctls_high
);
2497 case MSR_IA32_VMX_EPT_VPID_CAP
:
2498 /* Currently, no nested vpid support */
2499 *pdata
= nested_vmx_ept_caps
;
2509 * Reads an msr value (of 'msr_index') into 'pdata'.
2510 * Returns 0 on success, non-0 otherwise.
2511 * Assumes vcpu_load() was already called.
2513 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2516 struct shared_msr_entry
*msr
;
2519 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2523 switch (msr_index
) {
2524 #ifdef CONFIG_X86_64
2526 data
= vmcs_readl(GUEST_FS_BASE
);
2529 data
= vmcs_readl(GUEST_GS_BASE
);
2531 case MSR_KERNEL_GS_BASE
:
2532 vmx_load_host_state(to_vmx(vcpu
));
2533 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2537 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2539 data
= guest_read_tsc();
2541 case MSR_IA32_SYSENTER_CS
:
2542 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2544 case MSR_IA32_SYSENTER_EIP
:
2545 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2547 case MSR_IA32_SYSENTER_ESP
:
2548 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2550 case MSR_IA32_BNDCFGS
:
2551 if (!vmx_mpx_supported())
2553 data
= vmcs_read64(GUEST_BNDCFGS
);
2555 case MSR_IA32_FEATURE_CONTROL
:
2556 if (!nested_vmx_allowed(vcpu
))
2558 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2560 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2561 if (!nested_vmx_allowed(vcpu
))
2563 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2565 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2567 /* Otherwise falls through */
2569 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2574 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2581 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2584 * Writes msr value into into the appropriate "register".
2585 * Returns 0 on success, non-0 otherwise.
2586 * Assumes vcpu_load() was already called.
2588 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2591 struct shared_msr_entry
*msr
;
2593 u32 msr_index
= msr_info
->index
;
2594 u64 data
= msr_info
->data
;
2596 switch (msr_index
) {
2598 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2600 #ifdef CONFIG_X86_64
2602 vmx_segment_cache_clear(vmx
);
2603 vmcs_writel(GUEST_FS_BASE
, data
);
2606 vmx_segment_cache_clear(vmx
);
2607 vmcs_writel(GUEST_GS_BASE
, data
);
2609 case MSR_KERNEL_GS_BASE
:
2610 vmx_load_host_state(vmx
);
2611 vmx
->msr_guest_kernel_gs_base
= data
;
2614 case MSR_IA32_SYSENTER_CS
:
2615 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2617 case MSR_IA32_SYSENTER_EIP
:
2618 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2620 case MSR_IA32_SYSENTER_ESP
:
2621 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2623 case MSR_IA32_BNDCFGS
:
2624 if (!vmx_mpx_supported())
2626 vmcs_write64(GUEST_BNDCFGS
, data
);
2629 kvm_write_tsc(vcpu
, msr_info
);
2631 case MSR_IA32_CR_PAT
:
2632 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2633 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2635 vmcs_write64(GUEST_IA32_PAT
, data
);
2636 vcpu
->arch
.pat
= data
;
2639 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2641 case MSR_IA32_TSC_ADJUST
:
2642 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2644 case MSR_IA32_FEATURE_CONTROL
:
2645 if (!nested_vmx_allowed(vcpu
) ||
2646 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2647 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2649 vmx
->nested
.msr_ia32_feature_control
= data
;
2650 if (msr_info
->host_initiated
&& data
== 0)
2651 vmx_leave_nested(vcpu
);
2653 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2654 return 1; /* they are read-only */
2656 if (!vmx
->rdtscp_enabled
)
2658 /* Check reserved bit, higher 32 bits should be zero */
2659 if ((data
>> 32) != 0)
2661 /* Otherwise falls through */
2663 msr
= find_msr_entry(vmx
, msr_index
);
2665 u64 old_msr_data
= msr
->data
;
2667 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2669 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2673 msr
->data
= old_msr_data
;
2677 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2683 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2685 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2688 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2691 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2693 case VCPU_EXREG_PDPTR
:
2695 ept_save_pdptrs(vcpu
);
2702 static __init
int cpu_has_kvm_support(void)
2704 return cpu_has_vmx();
2707 static __init
int vmx_disabled_by_bios(void)
2711 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2712 if (msr
& FEATURE_CONTROL_LOCKED
) {
2713 /* launched w/ TXT and VMX disabled */
2714 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2717 /* launched w/o TXT and VMX only enabled w/ TXT */
2718 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2719 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2720 && !tboot_enabled()) {
2721 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2722 "activate TXT before enabling KVM\n");
2725 /* launched w/o TXT and VMX disabled */
2726 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2727 && !tboot_enabled())
2734 static void kvm_cpu_vmxon(u64 addr
)
2736 asm volatile (ASM_VMX_VMXON_RAX
2737 : : "a"(&addr
), "m"(addr
)
2741 static int hardware_enable(void)
2743 int cpu
= raw_smp_processor_id();
2744 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2747 if (read_cr4() & X86_CR4_VMXE
)
2750 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2753 * Now we can enable the vmclear operation in kdump
2754 * since the loaded_vmcss_on_cpu list on this cpu
2755 * has been initialized.
2757 * Though the cpu is not in VMX operation now, there
2758 * is no problem to enable the vmclear operation
2759 * for the loaded_vmcss_on_cpu list is empty!
2761 crash_enable_local_vmclear(cpu
);
2763 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2765 test_bits
= FEATURE_CONTROL_LOCKED
;
2766 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2767 if (tboot_enabled())
2768 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2770 if ((old
& test_bits
) != test_bits
) {
2771 /* enable and lock */
2772 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2774 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2776 if (vmm_exclusive
) {
2777 kvm_cpu_vmxon(phys_addr
);
2781 native_store_gdt(this_cpu_ptr(&host_gdt
));
2786 static void vmclear_local_loaded_vmcss(void)
2788 int cpu
= raw_smp_processor_id();
2789 struct loaded_vmcs
*v
, *n
;
2791 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2792 loaded_vmcss_on_cpu_link
)
2793 __loaded_vmcs_clear(v
);
2797 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2800 static void kvm_cpu_vmxoff(void)
2802 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2805 static void hardware_disable(void)
2807 if (vmm_exclusive
) {
2808 vmclear_local_loaded_vmcss();
2811 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2814 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2815 u32 msr
, u32
*result
)
2817 u32 vmx_msr_low
, vmx_msr_high
;
2818 u32 ctl
= ctl_min
| ctl_opt
;
2820 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2822 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2823 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2825 /* Ensure minimum (required) set of control bits are supported. */
2833 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2835 u32 vmx_msr_low
, vmx_msr_high
;
2837 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2838 return vmx_msr_high
& ctl
;
2841 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2843 u32 vmx_msr_low
, vmx_msr_high
;
2844 u32 min
, opt
, min2
, opt2
;
2845 u32 _pin_based_exec_control
= 0;
2846 u32 _cpu_based_exec_control
= 0;
2847 u32 _cpu_based_2nd_exec_control
= 0;
2848 u32 _vmexit_control
= 0;
2849 u32 _vmentry_control
= 0;
2851 min
= CPU_BASED_HLT_EXITING
|
2852 #ifdef CONFIG_X86_64
2853 CPU_BASED_CR8_LOAD_EXITING
|
2854 CPU_BASED_CR8_STORE_EXITING
|
2856 CPU_BASED_CR3_LOAD_EXITING
|
2857 CPU_BASED_CR3_STORE_EXITING
|
2858 CPU_BASED_USE_IO_BITMAPS
|
2859 CPU_BASED_MOV_DR_EXITING
|
2860 CPU_BASED_USE_TSC_OFFSETING
|
2861 CPU_BASED_MWAIT_EXITING
|
2862 CPU_BASED_MONITOR_EXITING
|
2863 CPU_BASED_INVLPG_EXITING
|
2864 CPU_BASED_RDPMC_EXITING
;
2866 opt
= CPU_BASED_TPR_SHADOW
|
2867 CPU_BASED_USE_MSR_BITMAPS
|
2868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2869 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2870 &_cpu_based_exec_control
) < 0)
2872 #ifdef CONFIG_X86_64
2873 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2874 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2875 ~CPU_BASED_CR8_STORE_EXITING
;
2877 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2879 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2880 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2881 SECONDARY_EXEC_WBINVD_EXITING
|
2882 SECONDARY_EXEC_ENABLE_VPID
|
2883 SECONDARY_EXEC_ENABLE_EPT
|
2884 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2885 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2886 SECONDARY_EXEC_RDTSCP
|
2887 SECONDARY_EXEC_ENABLE_INVPCID
|
2888 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2889 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2890 SECONDARY_EXEC_SHADOW_VMCS
;
2891 if (adjust_vmx_controls(min2
, opt2
,
2892 MSR_IA32_VMX_PROCBASED_CTLS2
,
2893 &_cpu_based_2nd_exec_control
) < 0)
2896 #ifndef CONFIG_X86_64
2897 if (!(_cpu_based_2nd_exec_control
&
2898 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2899 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2902 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2903 _cpu_based_2nd_exec_control
&= ~(
2904 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2905 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2906 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2908 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2909 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2911 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2912 CPU_BASED_CR3_STORE_EXITING
|
2913 CPU_BASED_INVLPG_EXITING
);
2914 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2915 vmx_capability
.ept
, vmx_capability
.vpid
);
2918 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2919 #ifdef CONFIG_X86_64
2920 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2922 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2923 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2924 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2925 &_vmexit_control
) < 0)
2928 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2929 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2930 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2931 &_pin_based_exec_control
) < 0)
2934 if (!(_cpu_based_2nd_exec_control
&
2935 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2936 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2937 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2939 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2940 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2941 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2942 &_vmentry_control
) < 0)
2945 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2947 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2948 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2951 #ifdef CONFIG_X86_64
2952 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2953 if (vmx_msr_high
& (1u<<16))
2957 /* Require Write-Back (WB) memory type for VMCS accesses. */
2958 if (((vmx_msr_high
>> 18) & 15) != 6)
2961 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2962 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2963 vmcs_conf
->revision_id
= vmx_msr_low
;
2965 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2966 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2967 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2968 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2969 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2971 cpu_has_load_ia32_efer
=
2972 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2973 VM_ENTRY_LOAD_IA32_EFER
)
2974 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2975 VM_EXIT_LOAD_IA32_EFER
);
2977 cpu_has_load_perf_global_ctrl
=
2978 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2979 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2980 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2981 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2984 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2985 * but due to arrata below it can't be used. Workaround is to use
2986 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2988 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2993 * BC86,AAY89,BD102 (model 44)
2997 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2998 switch (boot_cpu_data
.x86_model
) {
3004 cpu_has_load_perf_global_ctrl
= false;
3005 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3006 "does not work properly. Using workaround\n");
3016 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3018 int node
= cpu_to_node(cpu
);
3022 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3025 vmcs
= page_address(pages
);
3026 memset(vmcs
, 0, vmcs_config
.size
);
3027 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3031 static struct vmcs
*alloc_vmcs(void)
3033 return alloc_vmcs_cpu(raw_smp_processor_id());
3036 static void free_vmcs(struct vmcs
*vmcs
)
3038 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3042 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3044 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3046 if (!loaded_vmcs
->vmcs
)
3048 loaded_vmcs_clear(loaded_vmcs
);
3049 free_vmcs(loaded_vmcs
->vmcs
);
3050 loaded_vmcs
->vmcs
= NULL
;
3053 static void free_kvm_area(void)
3057 for_each_possible_cpu(cpu
) {
3058 free_vmcs(per_cpu(vmxarea
, cpu
));
3059 per_cpu(vmxarea
, cpu
) = NULL
;
3063 static void init_vmcs_shadow_fields(void)
3067 /* No checks for read only fields yet */
3069 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3070 switch (shadow_read_write_fields
[i
]) {
3072 if (!vmx_mpx_supported())
3080 shadow_read_write_fields
[j
] =
3081 shadow_read_write_fields
[i
];
3084 max_shadow_read_write_fields
= j
;
3086 /* shadowed fields guest access without vmexit */
3087 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3088 clear_bit(shadow_read_write_fields
[i
],
3089 vmx_vmwrite_bitmap
);
3090 clear_bit(shadow_read_write_fields
[i
],
3093 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3094 clear_bit(shadow_read_only_fields
[i
],
3098 static __init
int alloc_kvm_area(void)
3102 for_each_possible_cpu(cpu
) {
3105 vmcs
= alloc_vmcs_cpu(cpu
);
3111 per_cpu(vmxarea
, cpu
) = vmcs
;
3116 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3118 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3121 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3122 struct kvm_segment
*save
)
3124 if (!emulate_invalid_guest_state
) {
3126 * CS and SS RPL should be equal during guest entry according
3127 * to VMX spec, but in reality it is not always so. Since vcpu
3128 * is in the middle of the transition from real mode to
3129 * protected mode it is safe to assume that RPL 0 is a good
3132 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3133 save
->selector
&= ~SELECTOR_RPL_MASK
;
3134 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3137 vmx_set_segment(vcpu
, save
, seg
);
3140 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3142 unsigned long flags
;
3143 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3146 * Update real mode segment cache. It may be not up-to-date if sement
3147 * register was written while vcpu was in a guest mode.
3149 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3150 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3151 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3152 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3153 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3154 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3156 vmx
->rmode
.vm86_active
= 0;
3158 vmx_segment_cache_clear(vmx
);
3160 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3162 flags
= vmcs_readl(GUEST_RFLAGS
);
3163 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3164 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3165 vmcs_writel(GUEST_RFLAGS
, flags
);
3167 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3168 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3170 update_exception_bitmap(vcpu
);
3172 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3173 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3174 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3175 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3176 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3177 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3180 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3182 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3183 struct kvm_segment var
= *save
;
3186 if (seg
== VCPU_SREG_CS
)
3189 if (!emulate_invalid_guest_state
) {
3190 var
.selector
= var
.base
>> 4;
3191 var
.base
= var
.base
& 0xffff0;
3201 if (save
->base
& 0xf)
3202 printk_once(KERN_WARNING
"kvm: segment base is not "
3203 "paragraph aligned when entering "
3204 "protected mode (seg=%d)", seg
);
3207 vmcs_write16(sf
->selector
, var
.selector
);
3208 vmcs_write32(sf
->base
, var
.base
);
3209 vmcs_write32(sf
->limit
, var
.limit
);
3210 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3213 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3215 unsigned long flags
;
3216 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3218 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3219 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3220 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3221 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3222 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3223 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3224 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3226 vmx
->rmode
.vm86_active
= 1;
3229 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3230 * vcpu. Warn the user that an update is overdue.
3232 if (!vcpu
->kvm
->arch
.tss_addr
)
3233 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3234 "called before entering vcpu\n");
3236 vmx_segment_cache_clear(vmx
);
3238 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3239 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3240 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3242 flags
= vmcs_readl(GUEST_RFLAGS
);
3243 vmx
->rmode
.save_rflags
= flags
;
3245 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3247 vmcs_writel(GUEST_RFLAGS
, flags
);
3248 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3249 update_exception_bitmap(vcpu
);
3251 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3252 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3253 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3254 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3255 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3256 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3258 kvm_mmu_reset_context(vcpu
);
3261 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3263 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3264 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3270 * Force kernel_gs_base reloading before EFER changes, as control
3271 * of this msr depends on is_long_mode().
3273 vmx_load_host_state(to_vmx(vcpu
));
3274 vcpu
->arch
.efer
= efer
;
3275 if (efer
& EFER_LMA
) {
3276 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3279 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3281 msr
->data
= efer
& ~EFER_LME
;
3286 #ifdef CONFIG_X86_64
3288 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3292 vmx_segment_cache_clear(to_vmx(vcpu
));
3294 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3295 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3296 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3298 vmcs_write32(GUEST_TR_AR_BYTES
,
3299 (guest_tr_ar
& ~AR_TYPE_MASK
)
3300 | AR_TYPE_BUSY_64_TSS
);
3302 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3305 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3307 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3308 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3313 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3315 vpid_sync_context(to_vmx(vcpu
));
3317 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3319 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3323 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3325 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3327 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3328 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3331 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3333 if (enable_ept
&& is_paging(vcpu
))
3334 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3335 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3338 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3340 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3342 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3343 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3346 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3348 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3350 if (!test_bit(VCPU_EXREG_PDPTR
,
3351 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3354 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3355 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3356 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3357 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3358 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3362 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3364 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3366 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3367 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3368 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3369 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3370 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3373 __set_bit(VCPU_EXREG_PDPTR
,
3374 (unsigned long *)&vcpu
->arch
.regs_avail
);
3375 __set_bit(VCPU_EXREG_PDPTR
,
3376 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3379 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3381 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3383 struct kvm_vcpu
*vcpu
)
3385 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3386 vmx_decache_cr3(vcpu
);
3387 if (!(cr0
& X86_CR0_PG
)) {
3388 /* From paging/starting to nonpaging */
3389 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3390 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3391 (CPU_BASED_CR3_LOAD_EXITING
|
3392 CPU_BASED_CR3_STORE_EXITING
));
3393 vcpu
->arch
.cr0
= cr0
;
3394 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3395 } else if (!is_paging(vcpu
)) {
3396 /* From nonpaging to paging */
3397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3398 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3399 ~(CPU_BASED_CR3_LOAD_EXITING
|
3400 CPU_BASED_CR3_STORE_EXITING
));
3401 vcpu
->arch
.cr0
= cr0
;
3402 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3405 if (!(cr0
& X86_CR0_WP
))
3406 *hw_cr0
&= ~X86_CR0_WP
;
3409 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3411 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3412 unsigned long hw_cr0
;
3414 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3415 if (enable_unrestricted_guest
)
3416 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3418 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3420 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3423 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3427 #ifdef CONFIG_X86_64
3428 if (vcpu
->arch
.efer
& EFER_LME
) {
3429 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3431 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3437 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3439 if (!vcpu
->fpu_active
)
3440 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3442 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3443 vmcs_writel(GUEST_CR0
, hw_cr0
);
3444 vcpu
->arch
.cr0
= cr0
;
3446 /* depends on vcpu->arch.cr0 to be set to a new value */
3447 vmx
->emulation_required
= emulation_required(vcpu
);
3450 static u64
construct_eptp(unsigned long root_hpa
)
3454 /* TODO write the value reading from MSR */
3455 eptp
= VMX_EPT_DEFAULT_MT
|
3456 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3457 if (enable_ept_ad_bits
)
3458 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3459 eptp
|= (root_hpa
& PAGE_MASK
);
3464 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3466 unsigned long guest_cr3
;
3471 eptp
= construct_eptp(cr3
);
3472 vmcs_write64(EPT_POINTER
, eptp
);
3473 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3474 guest_cr3
= kvm_read_cr3(vcpu
);
3476 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3477 ept_load_pdptrs(vcpu
);
3480 vmx_flush_tlb(vcpu
);
3481 vmcs_writel(GUEST_CR3
, guest_cr3
);
3484 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3486 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3487 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3489 if (cr4
& X86_CR4_VMXE
) {
3491 * To use VMXON (and later other VMX instructions), a guest
3492 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3493 * So basically the check on whether to allow nested VMX
3496 if (!nested_vmx_allowed(vcpu
))
3499 if (to_vmx(vcpu
)->nested
.vmxon
&&
3500 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3503 vcpu
->arch
.cr4
= cr4
;
3505 if (!is_paging(vcpu
)) {
3506 hw_cr4
&= ~X86_CR4_PAE
;
3507 hw_cr4
|= X86_CR4_PSE
;
3509 * SMEP/SMAP is disabled if CPU is in non-paging mode
3510 * in hardware. However KVM always uses paging mode to
3511 * emulate guest non-paging mode with TDP.
3512 * To emulate this behavior, SMEP/SMAP needs to be
3513 * manually disabled when guest switches to non-paging
3516 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3517 } else if (!(cr4
& X86_CR4_PAE
)) {
3518 hw_cr4
&= ~X86_CR4_PAE
;
3522 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3523 vmcs_writel(GUEST_CR4
, hw_cr4
);
3527 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3528 struct kvm_segment
*var
, int seg
)
3530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3533 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3534 *var
= vmx
->rmode
.segs
[seg
];
3535 if (seg
== VCPU_SREG_TR
3536 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3538 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3539 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3542 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3543 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3544 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3545 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3546 var
->unusable
= (ar
>> 16) & 1;
3547 var
->type
= ar
& 15;
3548 var
->s
= (ar
>> 4) & 1;
3549 var
->dpl
= (ar
>> 5) & 3;
3551 * Some userspaces do not preserve unusable property. Since usable
3552 * segment has to be present according to VMX spec we can use present
3553 * property to amend userspace bug by making unusable segment always
3554 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3555 * segment as unusable.
3557 var
->present
= !var
->unusable
;
3558 var
->avl
= (ar
>> 12) & 1;
3559 var
->l
= (ar
>> 13) & 1;
3560 var
->db
= (ar
>> 14) & 1;
3561 var
->g
= (ar
>> 15) & 1;
3564 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3566 struct kvm_segment s
;
3568 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3569 vmx_get_segment(vcpu
, &s
, seg
);
3572 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3575 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3577 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3579 if (unlikely(vmx
->rmode
.vm86_active
))
3582 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3587 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3591 if (var
->unusable
|| !var
->present
)
3594 ar
= var
->type
& 15;
3595 ar
|= (var
->s
& 1) << 4;
3596 ar
|= (var
->dpl
& 3) << 5;
3597 ar
|= (var
->present
& 1) << 7;
3598 ar
|= (var
->avl
& 1) << 12;
3599 ar
|= (var
->l
& 1) << 13;
3600 ar
|= (var
->db
& 1) << 14;
3601 ar
|= (var
->g
& 1) << 15;
3607 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3608 struct kvm_segment
*var
, int seg
)
3610 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3611 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3613 vmx_segment_cache_clear(vmx
);
3615 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3616 vmx
->rmode
.segs
[seg
] = *var
;
3617 if (seg
== VCPU_SREG_TR
)
3618 vmcs_write16(sf
->selector
, var
->selector
);
3620 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3624 vmcs_writel(sf
->base
, var
->base
);
3625 vmcs_write32(sf
->limit
, var
->limit
);
3626 vmcs_write16(sf
->selector
, var
->selector
);
3629 * Fix the "Accessed" bit in AR field of segment registers for older
3631 * IA32 arch specifies that at the time of processor reset the
3632 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3633 * is setting it to 0 in the userland code. This causes invalid guest
3634 * state vmexit when "unrestricted guest" mode is turned on.
3635 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3636 * tree. Newer qemu binaries with that qemu fix would not need this
3639 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3640 var
->type
|= 0x1; /* Accessed */
3642 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3645 vmx
->emulation_required
= emulation_required(vcpu
);
3648 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3650 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3652 *db
= (ar
>> 14) & 1;
3653 *l
= (ar
>> 13) & 1;
3656 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3658 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3659 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3662 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3664 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3665 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3668 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3670 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3671 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3674 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3676 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3677 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3680 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3682 struct kvm_segment var
;
3685 vmx_get_segment(vcpu
, &var
, seg
);
3687 if (seg
== VCPU_SREG_CS
)
3689 ar
= vmx_segment_access_rights(&var
);
3691 if (var
.base
!= (var
.selector
<< 4))
3693 if (var
.limit
!= 0xffff)
3701 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3703 struct kvm_segment cs
;
3704 unsigned int cs_rpl
;
3706 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3707 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3711 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3715 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3716 if (cs
.dpl
> cs_rpl
)
3719 if (cs
.dpl
!= cs_rpl
)
3725 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3729 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3731 struct kvm_segment ss
;
3732 unsigned int ss_rpl
;
3734 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3735 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3739 if (ss
.type
!= 3 && ss
.type
!= 7)
3743 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3751 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3753 struct kvm_segment var
;
3756 vmx_get_segment(vcpu
, &var
, seg
);
3757 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3765 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3766 if (var
.dpl
< rpl
) /* DPL < RPL */
3770 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3776 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3778 struct kvm_segment tr
;
3780 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3784 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3786 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3794 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3796 struct kvm_segment ldtr
;
3798 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3802 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3812 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3814 struct kvm_segment cs
, ss
;
3816 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3817 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3819 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3820 (ss
.selector
& SELECTOR_RPL_MASK
));
3824 * Check if guest state is valid. Returns true if valid, false if
3826 * We assume that registers are always usable
3828 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3830 if (enable_unrestricted_guest
)
3833 /* real mode guest state checks */
3834 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3835 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3837 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3839 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3841 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3843 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3845 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3848 /* protected mode guest state checks */
3849 if (!cs_ss_rpl_check(vcpu
))
3851 if (!code_segment_valid(vcpu
))
3853 if (!stack_segment_valid(vcpu
))
3855 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3857 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3859 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3861 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3863 if (!tr_valid(vcpu
))
3865 if (!ldtr_valid(vcpu
))
3869 * - Add checks on RIP
3870 * - Add checks on RFLAGS
3876 static int init_rmode_tss(struct kvm
*kvm
)
3882 idx
= srcu_read_lock(&kvm
->srcu
);
3883 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3884 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3887 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3888 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3889 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3892 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3895 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3899 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3900 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3903 srcu_read_unlock(&kvm
->srcu
, idx
);
3907 static int init_rmode_identity_map(struct kvm
*kvm
)
3910 pfn_t identity_map_pfn
;
3916 /* Protect kvm->arch.ept_identity_pagetable_done. */
3917 mutex_lock(&kvm
->slots_lock
);
3919 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3922 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3924 r
= alloc_identity_pagetable(kvm
);
3928 idx
= srcu_read_lock(&kvm
->srcu
);
3929 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3932 /* Set up identity-mapping pagetable for EPT in real mode */
3933 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3934 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3935 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3936 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3937 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3941 kvm
->arch
.ept_identity_pagetable_done
= true;
3944 srcu_read_unlock(&kvm
->srcu
, idx
);
3947 mutex_unlock(&kvm
->slots_lock
);
3951 static void seg_setup(int seg
)
3953 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3956 vmcs_write16(sf
->selector
, 0);
3957 vmcs_writel(sf
->base
, 0);
3958 vmcs_write32(sf
->limit
, 0xffff);
3960 if (seg
== VCPU_SREG_CS
)
3961 ar
|= 0x08; /* code segment */
3963 vmcs_write32(sf
->ar_bytes
, ar
);
3966 static int alloc_apic_access_page(struct kvm
*kvm
)
3969 struct kvm_userspace_memory_region kvm_userspace_mem
;
3972 mutex_lock(&kvm
->slots_lock
);
3973 if (kvm
->arch
.apic_access_page_done
)
3975 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3976 kvm_userspace_mem
.flags
= 0;
3977 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
3978 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3979 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3983 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
3984 if (is_error_page(page
)) {
3990 * Do not pin the page in memory, so that memory hot-unplug
3991 * is able to migrate it.
3994 kvm
->arch
.apic_access_page_done
= true;
3996 mutex_unlock(&kvm
->slots_lock
);
4000 static int alloc_identity_pagetable(struct kvm
*kvm
)
4002 /* Called with kvm->slots_lock held. */
4004 struct kvm_userspace_memory_region kvm_userspace_mem
;
4007 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4009 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4010 kvm_userspace_mem
.flags
= 0;
4011 kvm_userspace_mem
.guest_phys_addr
=
4012 kvm
->arch
.ept_identity_map_addr
;
4013 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4014 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4019 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4026 spin_lock(&vmx_vpid_lock
);
4027 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4028 if (vpid
< VMX_NR_VPIDS
) {
4030 __set_bit(vpid
, vmx_vpid_bitmap
);
4032 spin_unlock(&vmx_vpid_lock
);
4035 static void free_vpid(struct vcpu_vmx
*vmx
)
4039 spin_lock(&vmx_vpid_lock
);
4041 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4042 spin_unlock(&vmx_vpid_lock
);
4045 #define MSR_TYPE_R 1
4046 #define MSR_TYPE_W 2
4047 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4050 int f
= sizeof(unsigned long);
4052 if (!cpu_has_vmx_msr_bitmap())
4056 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4057 * have the write-low and read-high bitmap offsets the wrong way round.
4058 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4060 if (msr
<= 0x1fff) {
4061 if (type
& MSR_TYPE_R
)
4063 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4065 if (type
& MSR_TYPE_W
)
4067 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4069 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4071 if (type
& MSR_TYPE_R
)
4073 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4075 if (type
& MSR_TYPE_W
)
4077 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4082 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4085 int f
= sizeof(unsigned long);
4087 if (!cpu_has_vmx_msr_bitmap())
4091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4092 * have the write-low and read-high bitmap offsets the wrong way round.
4093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4095 if (msr
<= 0x1fff) {
4096 if (type
& MSR_TYPE_R
)
4098 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4100 if (type
& MSR_TYPE_W
)
4102 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4104 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4106 if (type
& MSR_TYPE_R
)
4108 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4110 if (type
& MSR_TYPE_W
)
4112 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4117 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4120 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4121 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4122 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4123 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4126 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4128 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4130 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4134 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4138 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4142 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4144 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4146 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4150 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4152 return enable_apicv
&& irqchip_in_kernel(kvm
);
4156 * Send interrupt to vcpu via posted interrupt way.
4157 * 1. If target vcpu is running(non-root mode), send posted interrupt
4158 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4159 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4160 * interrupt from PIR in next vmentry.
4162 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4167 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4170 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4171 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4173 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4174 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4175 POSTED_INTR_VECTOR
);
4178 kvm_vcpu_kick(vcpu
);
4181 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4183 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4185 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4188 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4191 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4197 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4198 * will not change in the lifetime of the guest.
4199 * Note that host-state that does change is set elsewhere. E.g., host-state
4200 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4202 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4209 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4210 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4212 /* Save the most likely value for this task's CR4 in the VMCS. */
4214 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4215 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4217 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4218 #ifdef CONFIG_X86_64
4220 * Load null selectors, so we can avoid reloading them in
4221 * __vmx_load_host_state(), in case userspace uses the null selectors
4222 * too (the expected case).
4224 vmcs_write16(HOST_DS_SELECTOR
, 0);
4225 vmcs_write16(HOST_ES_SELECTOR
, 0);
4227 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4228 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4230 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4231 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4233 native_store_idt(&dt
);
4234 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4235 vmx
->host_idt_base
= dt
.address
;
4237 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4239 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4240 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4241 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4242 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4244 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4245 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4246 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4250 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4252 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4254 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4255 if (is_guest_mode(&vmx
->vcpu
))
4256 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4257 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4258 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4261 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4263 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4265 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4266 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4267 return pin_based_exec_ctrl
;
4270 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4272 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4274 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4275 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4277 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4278 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4279 #ifdef CONFIG_X86_64
4280 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4281 CPU_BASED_CR8_LOAD_EXITING
;
4285 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4286 CPU_BASED_CR3_LOAD_EXITING
|
4287 CPU_BASED_INVLPG_EXITING
;
4288 return exec_control
;
4291 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4293 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4294 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4295 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4297 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4299 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4300 enable_unrestricted_guest
= 0;
4301 /* Enable INVPCID for non-ept guests may cause performance regression. */
4302 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4304 if (!enable_unrestricted_guest
)
4305 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4307 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4308 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4309 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4310 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4311 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4312 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4314 We can NOT enable shadow_vmcs here because we don't have yet
4317 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4318 return exec_control
;
4321 static void ept_set_mmio_spte_mask(void)
4324 * EPT Misconfigurations can be generated if the value of bits 2:0
4325 * of an EPT paging-structure entry is 110b (write/execute).
4326 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4329 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4333 * Sets up the vmcs for emulated real mode.
4335 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4337 #ifdef CONFIG_X86_64
4343 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4344 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4346 if (enable_shadow_vmcs
) {
4347 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4348 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4350 if (cpu_has_vmx_msr_bitmap())
4351 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4353 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4356 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4358 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4360 if (cpu_has_secondary_exec_ctrls()) {
4361 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4362 vmx_secondary_exec_control(vmx
));
4365 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4366 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4367 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4368 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4369 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4371 vmcs_write16(GUEST_INTR_STATUS
, 0);
4373 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4374 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4378 vmcs_write32(PLE_GAP
, ple_gap
);
4379 vmx
->ple_window
= ple_window
;
4380 vmx
->ple_window_dirty
= true;
4383 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4384 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4385 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4387 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4388 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4389 vmx_set_constant_host_state(vmx
);
4390 #ifdef CONFIG_X86_64
4391 rdmsrl(MSR_FS_BASE
, a
);
4392 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4393 rdmsrl(MSR_GS_BASE
, a
);
4394 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4396 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4397 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4400 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4401 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4402 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4403 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4404 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4406 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4407 u32 msr_low
, msr_high
;
4409 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4410 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4411 /* Write the default value follow host pat */
4412 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4413 /* Keep arch.pat sync with GUEST_IA32_PAT */
4414 vmx
->vcpu
.arch
.pat
= host_pat
;
4417 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4418 u32 index
= vmx_msr_index
[i
];
4419 u32 data_low
, data_high
;
4422 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4424 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4426 vmx
->guest_msrs
[j
].index
= i
;
4427 vmx
->guest_msrs
[j
].data
= 0;
4428 vmx
->guest_msrs
[j
].mask
= -1ull;
4433 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4435 /* 22.2.1, 20.8.1 */
4436 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4438 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4439 set_cr4_guest_host_mask(vmx
);
4444 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4447 struct msr_data apic_base_msr
;
4449 vmx
->rmode
.vm86_active
= 0;
4451 vmx
->soft_vnmi_blocked
= 0;
4453 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4454 kvm_set_cr8(&vmx
->vcpu
, 0);
4455 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
;
4456 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4457 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4458 apic_base_msr
.host_initiated
= true;
4459 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4461 vmx_segment_cache_clear(vmx
);
4463 seg_setup(VCPU_SREG_CS
);
4464 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4465 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4467 seg_setup(VCPU_SREG_DS
);
4468 seg_setup(VCPU_SREG_ES
);
4469 seg_setup(VCPU_SREG_FS
);
4470 seg_setup(VCPU_SREG_GS
);
4471 seg_setup(VCPU_SREG_SS
);
4473 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4474 vmcs_writel(GUEST_TR_BASE
, 0);
4475 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4476 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4478 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4479 vmcs_writel(GUEST_LDTR_BASE
, 0);
4480 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4481 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4483 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4484 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4485 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4487 vmcs_writel(GUEST_RFLAGS
, 0x02);
4488 kvm_rip_write(vcpu
, 0xfff0);
4490 vmcs_writel(GUEST_GDTR_BASE
, 0);
4491 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4493 vmcs_writel(GUEST_IDTR_BASE
, 0);
4494 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4496 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4497 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4498 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4500 /* Special registers */
4501 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4505 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4507 if (cpu_has_vmx_tpr_shadow()) {
4508 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4509 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4510 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4511 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4512 vmcs_write32(TPR_THRESHOLD
, 0);
4515 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4517 if (vmx_vm_has_apicv(vcpu
->kvm
))
4518 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4521 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4523 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4524 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4525 vmx_set_cr4(&vmx
->vcpu
, 0);
4526 vmx_set_efer(&vmx
->vcpu
, 0);
4527 vmx_fpu_activate(&vmx
->vcpu
);
4528 update_exception_bitmap(&vmx
->vcpu
);
4530 vpid_sync_context(vmx
);
4534 * In nested virtualization, check if L1 asked to exit on external interrupts.
4535 * For most existing hypervisors, this will always return true.
4537 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4539 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4540 PIN_BASED_EXT_INTR_MASK
;
4544 * In nested virtualization, check if L1 has set
4545 * VM_EXIT_ACK_INTR_ON_EXIT
4547 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4549 return get_vmcs12(vcpu
)->vm_exit_controls
&
4550 VM_EXIT_ACK_INTR_ON_EXIT
;
4553 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4555 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4556 PIN_BASED_NMI_EXITING
;
4559 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4561 u32 cpu_based_vm_exec_control
;
4563 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4564 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4568 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4570 u32 cpu_based_vm_exec_control
;
4572 if (!cpu_has_virtual_nmis() ||
4573 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4574 enable_irq_window(vcpu
);
4578 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4579 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4580 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4583 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4585 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4587 int irq
= vcpu
->arch
.interrupt
.nr
;
4589 trace_kvm_inj_virq(irq
);
4591 ++vcpu
->stat
.irq_injections
;
4592 if (vmx
->rmode
.vm86_active
) {
4594 if (vcpu
->arch
.interrupt
.soft
)
4595 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4596 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4597 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4600 intr
= irq
| INTR_INFO_VALID_MASK
;
4601 if (vcpu
->arch
.interrupt
.soft
) {
4602 intr
|= INTR_TYPE_SOFT_INTR
;
4603 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4604 vmx
->vcpu
.arch
.event_exit_inst_len
);
4606 intr
|= INTR_TYPE_EXT_INTR
;
4607 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4610 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4612 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4614 if (is_guest_mode(vcpu
))
4617 if (!cpu_has_virtual_nmis()) {
4619 * Tracking the NMI-blocked state in software is built upon
4620 * finding the next open IRQ window. This, in turn, depends on
4621 * well-behaving guests: They have to keep IRQs disabled at
4622 * least as long as the NMI handler runs. Otherwise we may
4623 * cause NMI nesting, maybe breaking the guest. But as this is
4624 * highly unlikely, we can live with the residual risk.
4626 vmx
->soft_vnmi_blocked
= 1;
4627 vmx
->vnmi_blocked_time
= 0;
4630 ++vcpu
->stat
.nmi_injections
;
4631 vmx
->nmi_known_unmasked
= false;
4632 if (vmx
->rmode
.vm86_active
) {
4633 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4634 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4637 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4638 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4641 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4643 if (!cpu_has_virtual_nmis())
4644 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4645 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4647 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4650 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4652 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4654 if (!cpu_has_virtual_nmis()) {
4655 if (vmx
->soft_vnmi_blocked
!= masked
) {
4656 vmx
->soft_vnmi_blocked
= masked
;
4657 vmx
->vnmi_blocked_time
= 0;
4660 vmx
->nmi_known_unmasked
= !masked
;
4662 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4663 GUEST_INTR_STATE_NMI
);
4665 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4666 GUEST_INTR_STATE_NMI
);
4670 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4672 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4675 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4678 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4679 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4680 | GUEST_INTR_STATE_NMI
));
4683 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4685 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4686 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4687 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4688 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4691 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4694 struct kvm_userspace_memory_region tss_mem
= {
4695 .slot
= TSS_PRIVATE_MEMSLOT
,
4696 .guest_phys_addr
= addr
,
4697 .memory_size
= PAGE_SIZE
* 3,
4701 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4704 kvm
->arch
.tss_addr
= addr
;
4705 return init_rmode_tss(kvm
);
4708 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4713 * Update instruction length as we may reinject the exception
4714 * from user space while in guest debugging mode.
4716 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4717 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4718 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4722 if (vcpu
->guest_debug
&
4723 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4740 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4741 int vec
, u32 err_code
)
4744 * Instruction with address size override prefix opcode 0x67
4745 * Cause the #SS fault with 0 error code in VM86 mode.
4747 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4748 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4749 if (vcpu
->arch
.halt_request
) {
4750 vcpu
->arch
.halt_request
= 0;
4751 return kvm_emulate_halt(vcpu
);
4759 * Forward all other exceptions that are valid in real mode.
4760 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4761 * the required debugging infrastructure rework.
4763 kvm_queue_exception(vcpu
, vec
);
4768 * Trigger machine check on the host. We assume all the MSRs are already set up
4769 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4770 * We pass a fake environment to the machine check handler because we want
4771 * the guest to be always treated like user space, no matter what context
4772 * it used internally.
4774 static void kvm_machine_check(void)
4776 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4777 struct pt_regs regs
= {
4778 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4779 .flags
= X86_EFLAGS_IF
,
4782 do_machine_check(®s
, 0);
4786 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4788 /* already handled by vcpu_run */
4792 static int handle_exception(struct kvm_vcpu
*vcpu
)
4794 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4795 struct kvm_run
*kvm_run
= vcpu
->run
;
4796 u32 intr_info
, ex_no
, error_code
;
4797 unsigned long cr2
, rip
, dr6
;
4799 enum emulation_result er
;
4801 vect_info
= vmx
->idt_vectoring_info
;
4802 intr_info
= vmx
->exit_intr_info
;
4804 if (is_machine_check(intr_info
))
4805 return handle_machine_check(vcpu
);
4807 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4808 return 1; /* already handled by vmx_vcpu_run() */
4810 if (is_no_device(intr_info
)) {
4811 vmx_fpu_activate(vcpu
);
4815 if (is_invalid_opcode(intr_info
)) {
4816 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4817 if (er
!= EMULATE_DONE
)
4818 kvm_queue_exception(vcpu
, UD_VECTOR
);
4823 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4824 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4827 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4828 * MMIO, it is better to report an internal error.
4829 * See the comments in vmx_handle_exit.
4831 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4832 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4833 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4834 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4835 vcpu
->run
->internal
.ndata
= 2;
4836 vcpu
->run
->internal
.data
[0] = vect_info
;
4837 vcpu
->run
->internal
.data
[1] = intr_info
;
4841 if (is_page_fault(intr_info
)) {
4842 /* EPT won't cause page fault directly */
4844 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4845 trace_kvm_page_fault(cr2
, error_code
);
4847 if (kvm_event_needs_reinjection(vcpu
))
4848 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4849 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4852 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4854 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4855 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4859 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4860 if (!(vcpu
->guest_debug
&
4861 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4862 vcpu
->arch
.dr6
&= ~15;
4863 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
4864 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
4865 skip_emulated_instruction(vcpu
);
4867 kvm_queue_exception(vcpu
, DB_VECTOR
);
4870 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4871 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4875 * Update instruction length as we may reinject #BP from
4876 * user space while in guest debugging mode. Reading it for
4877 * #DB as well causes no harm, it is not used in that case.
4879 vmx
->vcpu
.arch
.event_exit_inst_len
=
4880 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4881 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4882 rip
= kvm_rip_read(vcpu
);
4883 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4884 kvm_run
->debug
.arch
.exception
= ex_no
;
4887 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4888 kvm_run
->ex
.exception
= ex_no
;
4889 kvm_run
->ex
.error_code
= error_code
;
4895 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4897 ++vcpu
->stat
.irq_exits
;
4901 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4903 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4907 static int handle_io(struct kvm_vcpu
*vcpu
)
4909 unsigned long exit_qualification
;
4910 int size
, in
, string
;
4913 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4914 string
= (exit_qualification
& 16) != 0;
4915 in
= (exit_qualification
& 8) != 0;
4917 ++vcpu
->stat
.io_exits
;
4920 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4922 port
= exit_qualification
>> 16;
4923 size
= (exit_qualification
& 7) + 1;
4924 skip_emulated_instruction(vcpu
);
4926 return kvm_fast_pio_out(vcpu
, size
, port
);
4930 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4933 * Patch in the VMCALL instruction:
4935 hypercall
[0] = 0x0f;
4936 hypercall
[1] = 0x01;
4937 hypercall
[2] = 0xc1;
4940 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4942 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4944 if (nested_vmx_secondary_ctls_high
&
4945 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4946 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4947 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4948 return (val
& always_on
) == always_on
;
4951 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4952 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4954 if (is_guest_mode(vcpu
)) {
4955 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4956 unsigned long orig_val
= val
;
4959 * We get here when L2 changed cr0 in a way that did not change
4960 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4961 * but did change L0 shadowed bits. So we first calculate the
4962 * effective cr0 value that L1 would like to write into the
4963 * hardware. It consists of the L2-owned bits from the new
4964 * value combined with the L1-owned bits from L1's guest_cr0.
4966 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4967 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4969 if (!nested_cr0_valid(vmcs12
, val
))
4972 if (kvm_set_cr0(vcpu
, val
))
4974 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4977 if (to_vmx(vcpu
)->nested
.vmxon
&&
4978 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4980 return kvm_set_cr0(vcpu
, val
);
4984 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4986 if (is_guest_mode(vcpu
)) {
4987 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4988 unsigned long orig_val
= val
;
4990 /* analogously to handle_set_cr0 */
4991 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4992 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4993 if (kvm_set_cr4(vcpu
, val
))
4995 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4998 return kvm_set_cr4(vcpu
, val
);
5001 /* called to set cr0 as approriate for clts instruction exit. */
5002 static void handle_clts(struct kvm_vcpu
*vcpu
)
5004 if (is_guest_mode(vcpu
)) {
5006 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5007 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5008 * just pretend it's off (also in arch.cr0 for fpu_activate).
5010 vmcs_writel(CR0_READ_SHADOW
,
5011 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5012 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5014 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5017 static int handle_cr(struct kvm_vcpu
*vcpu
)
5019 unsigned long exit_qualification
, val
;
5024 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5025 cr
= exit_qualification
& 15;
5026 reg
= (exit_qualification
>> 8) & 15;
5027 switch ((exit_qualification
>> 4) & 3) {
5028 case 0: /* mov to cr */
5029 val
= kvm_register_readl(vcpu
, reg
);
5030 trace_kvm_cr_write(cr
, val
);
5033 err
= handle_set_cr0(vcpu
, val
);
5034 kvm_complete_insn_gp(vcpu
, err
);
5037 err
= kvm_set_cr3(vcpu
, val
);
5038 kvm_complete_insn_gp(vcpu
, err
);
5041 err
= handle_set_cr4(vcpu
, val
);
5042 kvm_complete_insn_gp(vcpu
, err
);
5045 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5047 err
= kvm_set_cr8(vcpu
, cr8
);
5048 kvm_complete_insn_gp(vcpu
, err
);
5049 if (irqchip_in_kernel(vcpu
->kvm
))
5051 if (cr8_prev
<= cr8
)
5053 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5060 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5061 skip_emulated_instruction(vcpu
);
5062 vmx_fpu_activate(vcpu
);
5064 case 1: /*mov from cr*/
5067 val
= kvm_read_cr3(vcpu
);
5068 kvm_register_write(vcpu
, reg
, val
);
5069 trace_kvm_cr_read(cr
, val
);
5070 skip_emulated_instruction(vcpu
);
5073 val
= kvm_get_cr8(vcpu
);
5074 kvm_register_write(vcpu
, reg
, val
);
5075 trace_kvm_cr_read(cr
, val
);
5076 skip_emulated_instruction(vcpu
);
5081 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5082 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5083 kvm_lmsw(vcpu
, val
);
5085 skip_emulated_instruction(vcpu
);
5090 vcpu
->run
->exit_reason
= 0;
5091 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5092 (int)(exit_qualification
>> 4) & 3, cr
);
5096 static int handle_dr(struct kvm_vcpu
*vcpu
)
5098 unsigned long exit_qualification
;
5101 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5102 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5104 /* First, if DR does not exist, trigger UD */
5105 if (!kvm_require_dr(vcpu
, dr
))
5108 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5109 if (!kvm_require_cpl(vcpu
, 0))
5111 dr7
= vmcs_readl(GUEST_DR7
);
5114 * As the vm-exit takes precedence over the debug trap, we
5115 * need to emulate the latter, either for the host or the
5116 * guest debugging itself.
5118 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5119 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5120 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5121 vcpu
->run
->debug
.arch
.pc
=
5122 vmcs_readl(GUEST_CS_BASE
) +
5123 vmcs_readl(GUEST_RIP
);
5124 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5125 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5128 vcpu
->arch
.dr6
&= ~15;
5129 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5130 kvm_queue_exception(vcpu
, DB_VECTOR
);
5135 if (vcpu
->guest_debug
== 0) {
5136 u32 cpu_based_vm_exec_control
;
5138 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5139 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5143 * No more DR vmexits; force a reload of the debug registers
5144 * and reenter on this instruction. The next vmexit will
5145 * retrieve the full state of the debug registers.
5147 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5151 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5152 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5155 if (kvm_get_dr(vcpu
, dr
, &val
))
5157 kvm_register_write(vcpu
, reg
, val
);
5159 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5162 skip_emulated_instruction(vcpu
);
5166 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5168 return vcpu
->arch
.dr6
;
5171 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5175 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5177 u32 cpu_based_vm_exec_control
;
5179 get_debugreg(vcpu
->arch
.db
[0], 0);
5180 get_debugreg(vcpu
->arch
.db
[1], 1);
5181 get_debugreg(vcpu
->arch
.db
[2], 2);
5182 get_debugreg(vcpu
->arch
.db
[3], 3);
5183 get_debugreg(vcpu
->arch
.dr6
, 6);
5184 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5186 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5188 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5189 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5190 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5193 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5195 vmcs_writel(GUEST_DR7
, val
);
5198 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5200 kvm_emulate_cpuid(vcpu
);
5204 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5206 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5209 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5210 trace_kvm_msr_read_ex(ecx
);
5211 kvm_inject_gp(vcpu
, 0);
5215 trace_kvm_msr_read(ecx
, data
);
5217 /* FIXME: handling of bits 32:63 of rax, rdx */
5218 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5219 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5220 skip_emulated_instruction(vcpu
);
5224 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5226 struct msr_data msr
;
5227 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5228 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5229 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5233 msr
.host_initiated
= false;
5234 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5235 trace_kvm_msr_write_ex(ecx
, data
);
5236 kvm_inject_gp(vcpu
, 0);
5240 trace_kvm_msr_write(ecx
, data
);
5241 skip_emulated_instruction(vcpu
);
5245 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5247 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5251 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5253 u32 cpu_based_vm_exec_control
;
5255 /* clear pending irq */
5256 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5257 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5258 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5260 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5262 ++vcpu
->stat
.irq_window_exits
;
5265 * If the user space waits to inject interrupts, exit as soon as
5268 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5269 vcpu
->run
->request_interrupt_window
&&
5270 !kvm_cpu_has_interrupt(vcpu
)) {
5271 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5277 static int handle_halt(struct kvm_vcpu
*vcpu
)
5279 skip_emulated_instruction(vcpu
);
5280 return kvm_emulate_halt(vcpu
);
5283 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5285 skip_emulated_instruction(vcpu
);
5286 kvm_emulate_hypercall(vcpu
);
5290 static int handle_invd(struct kvm_vcpu
*vcpu
)
5292 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5295 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5297 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5299 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5300 skip_emulated_instruction(vcpu
);
5304 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5308 err
= kvm_rdpmc(vcpu
);
5309 kvm_complete_insn_gp(vcpu
, err
);
5314 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5316 skip_emulated_instruction(vcpu
);
5317 kvm_emulate_wbinvd(vcpu
);
5321 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5323 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5324 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5326 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5327 skip_emulated_instruction(vcpu
);
5331 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5333 if (likely(fasteoi
)) {
5334 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5335 int access_type
, offset
;
5337 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5338 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5340 * Sane guest uses MOV to write EOI, with written value
5341 * not cared. So make a short-circuit here by avoiding
5342 * heavy instruction emulation.
5344 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5345 (offset
== APIC_EOI
)) {
5346 kvm_lapic_set_eoi(vcpu
);
5347 skip_emulated_instruction(vcpu
);
5351 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5354 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5356 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5357 int vector
= exit_qualification
& 0xff;
5359 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5360 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5364 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5366 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5367 u32 offset
= exit_qualification
& 0xfff;
5369 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5370 kvm_apic_write_nodecode(vcpu
, offset
);
5374 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5376 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5377 unsigned long exit_qualification
;
5378 bool has_error_code
= false;
5381 int reason
, type
, idt_v
, idt_index
;
5383 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5384 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5385 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5387 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5389 reason
= (u32
)exit_qualification
>> 30;
5390 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5392 case INTR_TYPE_NMI_INTR
:
5393 vcpu
->arch
.nmi_injected
= false;
5394 vmx_set_nmi_mask(vcpu
, true);
5396 case INTR_TYPE_EXT_INTR
:
5397 case INTR_TYPE_SOFT_INTR
:
5398 kvm_clear_interrupt_queue(vcpu
);
5400 case INTR_TYPE_HARD_EXCEPTION
:
5401 if (vmx
->idt_vectoring_info
&
5402 VECTORING_INFO_DELIVER_CODE_MASK
) {
5403 has_error_code
= true;
5405 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5408 case INTR_TYPE_SOFT_EXCEPTION
:
5409 kvm_clear_exception_queue(vcpu
);
5415 tss_selector
= exit_qualification
;
5417 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5418 type
!= INTR_TYPE_EXT_INTR
&&
5419 type
!= INTR_TYPE_NMI_INTR
))
5420 skip_emulated_instruction(vcpu
);
5422 if (kvm_task_switch(vcpu
, tss_selector
,
5423 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5424 has_error_code
, error_code
) == EMULATE_FAIL
) {
5425 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5426 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5427 vcpu
->run
->internal
.ndata
= 0;
5431 /* clear all local breakpoint enable flags */
5432 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x155);
5435 * TODO: What about debug traps on tss switch?
5436 * Are we supposed to inject them and update dr6?
5442 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5444 unsigned long exit_qualification
;
5449 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5451 gla_validity
= (exit_qualification
>> 7) & 0x3;
5452 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5453 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5454 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5455 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5456 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5457 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5458 (long unsigned int)exit_qualification
);
5459 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5460 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5465 * EPT violation happened while executing iret from NMI,
5466 * "blocked by NMI" bit has to be set before next VM entry.
5467 * There are errata that may cause this bit to not be set:
5470 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5471 cpu_has_virtual_nmis() &&
5472 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5473 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5475 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5476 trace_kvm_page_fault(gpa
, exit_qualification
);
5478 /* It is a write fault? */
5479 error_code
= exit_qualification
& (1U << 1);
5480 /* It is a fetch fault? */
5481 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5482 /* ept page table is present? */
5483 error_code
|= (exit_qualification
>> 3) & 0x1;
5485 vcpu
->arch
.exit_qualification
= exit_qualification
;
5487 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5490 static u64
ept_rsvd_mask(u64 spte
, int level
)
5495 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5496 mask
|= (1ULL << i
);
5499 /* bits 7:3 reserved */
5501 else if (spte
& (1ULL << 7))
5503 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5504 * level == 1 if the hypervisor is using the ignored bit 7.
5506 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5508 /* bits 6:3 reserved */
5514 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5517 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5519 /* 010b (write-only) */
5520 WARN_ON((spte
& 0x7) == 0x2);
5522 /* 110b (write/execute) */
5523 WARN_ON((spte
& 0x7) == 0x6);
5525 /* 100b (execute-only) and value not supported by logical processor */
5526 if (!cpu_has_vmx_ept_execute_only())
5527 WARN_ON((spte
& 0x7) == 0x4);
5531 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5533 if (rsvd_bits
!= 0) {
5534 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5535 __func__
, rsvd_bits
);
5539 /* bits 5:3 are _not_ reserved for large page or leaf page */
5540 if ((rsvd_bits
& 0x38) == 0) {
5541 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5543 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5544 ept_mem_type
== 7) {
5545 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5546 __func__
, ept_mem_type
);
5553 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5556 int nr_sptes
, i
, ret
;
5559 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5560 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5561 skip_emulated_instruction(vcpu
);
5565 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5566 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5567 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5570 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5571 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5573 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5576 /* It is the real ept misconfig */
5577 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5578 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5580 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5582 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5583 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5585 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5586 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5591 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5593 u32 cpu_based_vm_exec_control
;
5595 /* clear pending NMI */
5596 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5597 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5598 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5599 ++vcpu
->stat
.nmi_window_exits
;
5600 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5605 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5608 enum emulation_result err
= EMULATE_DONE
;
5611 bool intr_window_requested
;
5612 unsigned count
= 130;
5614 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5615 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5617 while (vmx
->emulation_required
&& count
-- != 0) {
5618 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5619 return handle_interrupt_window(&vmx
->vcpu
);
5621 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5624 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5626 if (err
== EMULATE_USER_EXIT
) {
5627 ++vcpu
->stat
.mmio_exits
;
5632 if (err
!= EMULATE_DONE
) {
5633 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5634 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5635 vcpu
->run
->internal
.ndata
= 0;
5639 if (vcpu
->arch
.halt_request
) {
5640 vcpu
->arch
.halt_request
= 0;
5641 ret
= kvm_emulate_halt(vcpu
);
5645 if (signal_pending(current
))
5655 static int __grow_ple_window(int val
)
5657 if (ple_window_grow
< 1)
5660 val
= min(val
, ple_window_actual_max
);
5662 if (ple_window_grow
< ple_window
)
5663 val
*= ple_window_grow
;
5665 val
+= ple_window_grow
;
5670 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5675 if (modifier
< ple_window
)
5680 return max(val
, minimum
);
5683 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5685 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5686 int old
= vmx
->ple_window
;
5688 vmx
->ple_window
= __grow_ple_window(old
);
5690 if (vmx
->ple_window
!= old
)
5691 vmx
->ple_window_dirty
= true;
5693 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5696 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5698 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5699 int old
= vmx
->ple_window
;
5701 vmx
->ple_window
= __shrink_ple_window(old
,
5702 ple_window_shrink
, ple_window
);
5704 if (vmx
->ple_window
!= old
)
5705 vmx
->ple_window_dirty
= true;
5707 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5711 * ple_window_actual_max is computed to be one grow_ple_window() below
5712 * ple_window_max. (See __grow_ple_window for the reason.)
5713 * This prevents overflows, because ple_window_max is int.
5714 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5716 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5718 static void update_ple_window_actual_max(void)
5720 ple_window_actual_max
=
5721 __shrink_ple_window(max(ple_window_max
, ple_window
),
5722 ple_window_grow
, INT_MIN
);
5725 static __init
int hardware_setup(void)
5727 int r
= -ENOMEM
, i
, msr
;
5729 rdmsrl_safe(MSR_EFER
, &host_efer
);
5731 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
5732 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5734 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5735 if (!vmx_io_bitmap_a
)
5738 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5739 if (!vmx_io_bitmap_b
)
5742 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5743 if (!vmx_msr_bitmap_legacy
)
5746 vmx_msr_bitmap_legacy_x2apic
=
5747 (unsigned long *)__get_free_page(GFP_KERNEL
);
5748 if (!vmx_msr_bitmap_legacy_x2apic
)
5751 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5752 if (!vmx_msr_bitmap_longmode
)
5755 vmx_msr_bitmap_longmode_x2apic
=
5756 (unsigned long *)__get_free_page(GFP_KERNEL
);
5757 if (!vmx_msr_bitmap_longmode_x2apic
)
5759 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5760 if (!vmx_vmread_bitmap
)
5763 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5764 if (!vmx_vmwrite_bitmap
)
5767 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
5768 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
5771 * Allow direct access to the PC debug port (it is often used for I/O
5772 * delays, but the vmexits simply slow things down).
5774 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
5775 clear_bit(0x80, vmx_io_bitmap_a
);
5777 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
5779 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
5780 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
5782 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
5783 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
5784 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
5785 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
5786 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
5787 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
5788 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
5790 memcpy(vmx_msr_bitmap_legacy_x2apic
,
5791 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
5792 memcpy(vmx_msr_bitmap_longmode_x2apic
,
5793 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
5796 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
5797 vmx_disable_intercept_msr_read_x2apic(msr
);
5799 /* According SDM, in x2apic mode, the whole id reg is used.
5800 * But in KVM, it only use the highest eight bits. Need to
5802 vmx_enable_intercept_msr_read_x2apic(0x802);
5804 vmx_enable_intercept_msr_read_x2apic(0x839);
5806 vmx_disable_intercept_msr_write_x2apic(0x808);
5808 vmx_disable_intercept_msr_write_x2apic(0x80b);
5810 vmx_disable_intercept_msr_write_x2apic(0x83f);
5814 kvm_mmu_set_mask_ptes(0ull,
5815 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
5816 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
5817 0ull, VMX_EPT_EXECUTABLE_MASK
);
5818 ept_set_mmio_spte_mask();
5823 update_ple_window_actual_max();
5825 if (setup_vmcs_config(&vmcs_config
) < 0) {
5830 if (boot_cpu_has(X86_FEATURE_NX
))
5831 kvm_enable_efer_bits(EFER_NX
);
5833 if (!cpu_has_vmx_vpid())
5835 if (!cpu_has_vmx_shadow_vmcs())
5836 enable_shadow_vmcs
= 0;
5837 if (enable_shadow_vmcs
)
5838 init_vmcs_shadow_fields();
5840 if (!cpu_has_vmx_ept() ||
5841 !cpu_has_vmx_ept_4levels()) {
5843 enable_unrestricted_guest
= 0;
5844 enable_ept_ad_bits
= 0;
5847 if (!cpu_has_vmx_ept_ad_bits())
5848 enable_ept_ad_bits
= 0;
5850 if (!cpu_has_vmx_unrestricted_guest())
5851 enable_unrestricted_guest
= 0;
5853 if (!cpu_has_vmx_flexpriority()) {
5854 flexpriority_enabled
= 0;
5857 * set_apic_access_page_addr() is used to reload apic access
5858 * page upon invalidation. No need to do anything if the
5859 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5861 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
5864 if (!cpu_has_vmx_tpr_shadow())
5865 kvm_x86_ops
->update_cr8_intercept
= NULL
;
5867 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
5868 kvm_disable_largepages();
5870 if (!cpu_has_vmx_ple())
5873 if (!cpu_has_vmx_apicv())
5877 kvm_x86_ops
->update_cr8_intercept
= NULL
;
5879 kvm_x86_ops
->hwapic_irr_update
= NULL
;
5880 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
5881 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
5885 nested_vmx_setup_ctls_msrs();
5887 return alloc_kvm_area();
5890 free_page((unsigned long)vmx_vmwrite_bitmap
);
5892 free_page((unsigned long)vmx_vmread_bitmap
);
5894 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
5896 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5898 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
5900 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5902 free_page((unsigned long)vmx_io_bitmap_b
);
5904 free_page((unsigned long)vmx_io_bitmap_a
);
5909 static __exit
void hardware_unsetup(void)
5911 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
5912 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
5913 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5914 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5915 free_page((unsigned long)vmx_io_bitmap_b
);
5916 free_page((unsigned long)vmx_io_bitmap_a
);
5917 free_page((unsigned long)vmx_vmwrite_bitmap
);
5918 free_page((unsigned long)vmx_vmread_bitmap
);
5924 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5925 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5927 static int handle_pause(struct kvm_vcpu
*vcpu
)
5930 grow_ple_window(vcpu
);
5932 skip_emulated_instruction(vcpu
);
5933 kvm_vcpu_on_spin(vcpu
);
5938 static int handle_nop(struct kvm_vcpu
*vcpu
)
5940 skip_emulated_instruction(vcpu
);
5944 static int handle_mwait(struct kvm_vcpu
*vcpu
)
5946 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
5947 return handle_nop(vcpu
);
5950 static int handle_monitor(struct kvm_vcpu
*vcpu
)
5952 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
5953 return handle_nop(vcpu
);
5957 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5958 * We could reuse a single VMCS for all the L2 guests, but we also want the
5959 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5960 * allows keeping them loaded on the processor, and in the future will allow
5961 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5962 * every entry if they never change.
5963 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5964 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5966 * The following functions allocate and free a vmcs02 in this pool.
5969 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5970 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5972 struct vmcs02_list
*item
;
5973 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5974 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5975 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5976 return &item
->vmcs02
;
5979 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5980 /* Recycle the least recently used VMCS. */
5981 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5982 struct vmcs02_list
, list
);
5983 item
->vmptr
= vmx
->nested
.current_vmptr
;
5984 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5985 return &item
->vmcs02
;
5988 /* Create a new VMCS */
5989 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5992 item
->vmcs02
.vmcs
= alloc_vmcs();
5993 if (!item
->vmcs02
.vmcs
) {
5997 loaded_vmcs_init(&item
->vmcs02
);
5998 item
->vmptr
= vmx
->nested
.current_vmptr
;
5999 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6000 vmx
->nested
.vmcs02_num
++;
6001 return &item
->vmcs02
;
6004 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6005 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6007 struct vmcs02_list
*item
;
6008 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6009 if (item
->vmptr
== vmptr
) {
6010 free_loaded_vmcs(&item
->vmcs02
);
6011 list_del(&item
->list
);
6013 vmx
->nested
.vmcs02_num
--;
6019 * Free all VMCSs saved for this vcpu, except the one pointed by
6020 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6021 * must be &vmx->vmcs01.
6023 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6025 struct vmcs02_list
*item
, *n
;
6027 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6028 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6030 * Something will leak if the above WARN triggers. Better than
6033 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6036 free_loaded_vmcs(&item
->vmcs02
);
6037 list_del(&item
->list
);
6039 vmx
->nested
.vmcs02_num
--;
6044 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6045 * set the success or error code of an emulated VMX instruction, as specified
6046 * by Vol 2B, VMX Instruction Reference, "Conventions".
6048 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6050 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6051 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6052 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6055 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6057 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6058 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6059 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6063 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6064 u32 vm_instruction_error
)
6066 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6068 * failValid writes the error number to the current VMCS, which
6069 * can't be done there isn't a current VMCS.
6071 nested_vmx_failInvalid(vcpu
);
6074 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6075 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6076 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6078 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6080 * We don't need to force a shadow sync because
6081 * VM_INSTRUCTION_ERROR is not shadowed
6085 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6087 struct vcpu_vmx
*vmx
=
6088 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6090 vmx
->nested
.preemption_timer_expired
= true;
6091 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6092 kvm_vcpu_kick(&vmx
->vcpu
);
6094 return HRTIMER_NORESTART
;
6098 * Decode the memory-address operand of a vmx instruction, as recorded on an
6099 * exit caused by such an instruction (run by a guest hypervisor).
6100 * On success, returns 0. When the operand is invalid, returns 1 and throws
6103 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6104 unsigned long exit_qualification
,
6105 u32 vmx_instruction_info
, gva_t
*ret
)
6108 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6109 * Execution", on an exit, vmx_instruction_info holds most of the
6110 * addressing components of the operand. Only the displacement part
6111 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6112 * For how an actual address is calculated from all these components,
6113 * refer to Vol. 1, "Operand Addressing".
6115 int scaling
= vmx_instruction_info
& 3;
6116 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6117 bool is_reg
= vmx_instruction_info
& (1u << 10);
6118 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6119 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6120 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6121 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6122 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6125 kvm_queue_exception(vcpu
, UD_VECTOR
);
6129 /* Addr = segment_base + offset */
6130 /* offset = base + [index * scale] + displacement */
6131 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
6133 *ret
+= kvm_register_read(vcpu
, base_reg
);
6135 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6136 *ret
+= exit_qualification
; /* holds the displacement */
6138 if (addr_size
== 1) /* 32 bit */
6142 * TODO: throw #GP (and return 1) in various cases that the VM*
6143 * instructions require it - e.g., offset beyond segment limit,
6144 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6145 * address, and so on. Currently these are not checked.
6151 * This function performs the various checks including
6152 * - if it's 4KB aligned
6153 * - No bits beyond the physical address width are set
6154 * - Returns 0 on success or else 1
6155 * (Intel SDM Section 30.3)
6157 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6162 struct x86_exception e
;
6164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6165 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6167 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6168 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6171 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6172 sizeof(vmptr
), &e
)) {
6173 kvm_inject_page_fault(vcpu
, &e
);
6177 switch (exit_reason
) {
6178 case EXIT_REASON_VMON
:
6181 * The first 4 bytes of VMXON region contain the supported
6182 * VMCS revision identifier
6184 * Note - IA32_VMX_BASIC[48] will never be 1
6185 * for the nested case;
6186 * which replaces physical address width with 32
6189 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6190 nested_vmx_failInvalid(vcpu
);
6191 skip_emulated_instruction(vcpu
);
6195 page
= nested_get_page(vcpu
, vmptr
);
6197 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6198 nested_vmx_failInvalid(vcpu
);
6200 skip_emulated_instruction(vcpu
);
6204 vmx
->nested
.vmxon_ptr
= vmptr
;
6206 case EXIT_REASON_VMCLEAR
:
6207 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6208 nested_vmx_failValid(vcpu
,
6209 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6210 skip_emulated_instruction(vcpu
);
6214 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6215 nested_vmx_failValid(vcpu
,
6216 VMXERR_VMCLEAR_VMXON_POINTER
);
6217 skip_emulated_instruction(vcpu
);
6221 case EXIT_REASON_VMPTRLD
:
6222 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6223 nested_vmx_failValid(vcpu
,
6224 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6225 skip_emulated_instruction(vcpu
);
6229 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6230 nested_vmx_failValid(vcpu
,
6231 VMXERR_VMCLEAR_VMXON_POINTER
);
6232 skip_emulated_instruction(vcpu
);
6237 return 1; /* shouldn't happen */
6246 * Emulate the VMXON instruction.
6247 * Currently, we just remember that VMX is active, and do not save or even
6248 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6249 * do not currently need to store anything in that guest-allocated memory
6250 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6251 * argument is different from the VMXON pointer (which the spec says they do).
6253 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6255 struct kvm_segment cs
;
6256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6257 struct vmcs
*shadow_vmcs
;
6258 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6259 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6261 /* The Intel VMX Instruction Reference lists a bunch of bits that
6262 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6263 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6264 * Otherwise, we should fail with #UD. We test these now:
6266 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6267 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6268 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6269 kvm_queue_exception(vcpu
, UD_VECTOR
);
6273 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6274 if (is_long_mode(vcpu
) && !cs
.l
) {
6275 kvm_queue_exception(vcpu
, UD_VECTOR
);
6279 if (vmx_get_cpl(vcpu
)) {
6280 kvm_inject_gp(vcpu
, 0);
6284 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6287 if (vmx
->nested
.vmxon
) {
6288 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6289 skip_emulated_instruction(vcpu
);
6293 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6294 != VMXON_NEEDED_FEATURES
) {
6295 kvm_inject_gp(vcpu
, 0);
6299 if (enable_shadow_vmcs
) {
6300 shadow_vmcs
= alloc_vmcs();
6303 /* mark vmcs as shadow */
6304 shadow_vmcs
->revision_id
|= (1u << 31);
6305 /* init shadow vmcs */
6306 vmcs_clear(shadow_vmcs
);
6307 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6310 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6311 vmx
->nested
.vmcs02_num
= 0;
6313 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6315 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6317 vmx
->nested
.vmxon
= true;
6319 skip_emulated_instruction(vcpu
);
6320 nested_vmx_succeed(vcpu
);
6325 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6326 * for running VMX instructions (except VMXON, whose prerequisites are
6327 * slightly different). It also specifies what exception to inject otherwise.
6329 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6331 struct kvm_segment cs
;
6332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6334 if (!vmx
->nested
.vmxon
) {
6335 kvm_queue_exception(vcpu
, UD_VECTOR
);
6339 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6340 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6341 (is_long_mode(vcpu
) && !cs
.l
)) {
6342 kvm_queue_exception(vcpu
, UD_VECTOR
);
6346 if (vmx_get_cpl(vcpu
)) {
6347 kvm_inject_gp(vcpu
, 0);
6354 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6357 if (vmx
->nested
.current_vmptr
== -1ull)
6360 /* current_vmptr and current_vmcs12 are always set/reset together */
6361 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6364 if (enable_shadow_vmcs
) {
6365 /* copy to memory all shadowed fields in case
6366 they were modified */
6367 copy_shadow_to_vmcs12(vmx
);
6368 vmx
->nested
.sync_shadow_vmcs
= false;
6369 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6370 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6371 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6372 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6374 kunmap(vmx
->nested
.current_vmcs12_page
);
6375 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6376 vmx
->nested
.current_vmptr
= -1ull;
6377 vmx
->nested
.current_vmcs12
= NULL
;
6381 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6382 * just stops using VMX.
6384 static void free_nested(struct vcpu_vmx
*vmx
)
6386 if (!vmx
->nested
.vmxon
)
6389 vmx
->nested
.vmxon
= false;
6390 nested_release_vmcs12(vmx
);
6391 if (enable_shadow_vmcs
)
6392 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6393 /* Unpin physical memory we referred to in current vmcs02 */
6394 if (vmx
->nested
.apic_access_page
) {
6395 nested_release_page(vmx
->nested
.apic_access_page
);
6396 vmx
->nested
.apic_access_page
= NULL
;
6398 if (vmx
->nested
.virtual_apic_page
) {
6399 nested_release_page(vmx
->nested
.virtual_apic_page
);
6400 vmx
->nested
.virtual_apic_page
= NULL
;
6403 nested_free_all_saved_vmcss(vmx
);
6406 /* Emulate the VMXOFF instruction */
6407 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6409 if (!nested_vmx_check_permission(vcpu
))
6411 free_nested(to_vmx(vcpu
));
6412 skip_emulated_instruction(vcpu
);
6413 nested_vmx_succeed(vcpu
);
6417 /* Emulate the VMCLEAR instruction */
6418 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6420 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6422 struct vmcs12
*vmcs12
;
6425 if (!nested_vmx_check_permission(vcpu
))
6428 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6431 if (vmptr
== vmx
->nested
.current_vmptr
)
6432 nested_release_vmcs12(vmx
);
6434 page
= nested_get_page(vcpu
, vmptr
);
6437 * For accurate processor emulation, VMCLEAR beyond available
6438 * physical memory should do nothing at all. However, it is
6439 * possible that a nested vmx bug, not a guest hypervisor bug,
6440 * resulted in this case, so let's shut down before doing any
6443 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6446 vmcs12
= kmap(page
);
6447 vmcs12
->launch_state
= 0;
6449 nested_release_page(page
);
6451 nested_free_vmcs02(vmx
, vmptr
);
6453 skip_emulated_instruction(vcpu
);
6454 nested_vmx_succeed(vcpu
);
6458 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6460 /* Emulate the VMLAUNCH instruction */
6461 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6463 return nested_vmx_run(vcpu
, true);
6466 /* Emulate the VMRESUME instruction */
6467 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6470 return nested_vmx_run(vcpu
, false);
6473 enum vmcs_field_type
{
6474 VMCS_FIELD_TYPE_U16
= 0,
6475 VMCS_FIELD_TYPE_U64
= 1,
6476 VMCS_FIELD_TYPE_U32
= 2,
6477 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6480 static inline int vmcs_field_type(unsigned long field
)
6482 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6483 return VMCS_FIELD_TYPE_U32
;
6484 return (field
>> 13) & 0x3 ;
6487 static inline int vmcs_field_readonly(unsigned long field
)
6489 return (((field
>> 10) & 0x3) == 1);
6493 * Read a vmcs12 field. Since these can have varying lengths and we return
6494 * one type, we chose the biggest type (u64) and zero-extend the return value
6495 * to that size. Note that the caller, handle_vmread, might need to use only
6496 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6497 * 64-bit fields are to be returned).
6499 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6500 unsigned long field
, u64
*ret
)
6502 short offset
= vmcs_field_to_offset(field
);
6508 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6510 switch (vmcs_field_type(field
)) {
6511 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6512 *ret
= *((natural_width
*)p
);
6514 case VMCS_FIELD_TYPE_U16
:
6517 case VMCS_FIELD_TYPE_U32
:
6520 case VMCS_FIELD_TYPE_U64
:
6530 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6531 unsigned long field
, u64 field_value
){
6532 short offset
= vmcs_field_to_offset(field
);
6533 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6537 switch (vmcs_field_type(field
)) {
6538 case VMCS_FIELD_TYPE_U16
:
6539 *(u16
*)p
= field_value
;
6541 case VMCS_FIELD_TYPE_U32
:
6542 *(u32
*)p
= field_value
;
6544 case VMCS_FIELD_TYPE_U64
:
6545 *(u64
*)p
= field_value
;
6547 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6548 *(natural_width
*)p
= field_value
;
6557 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6560 unsigned long field
;
6562 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6563 const unsigned long *fields
= shadow_read_write_fields
;
6564 const int num_fields
= max_shadow_read_write_fields
;
6568 vmcs_load(shadow_vmcs
);
6570 for (i
= 0; i
< num_fields
; i
++) {
6572 switch (vmcs_field_type(field
)) {
6573 case VMCS_FIELD_TYPE_U16
:
6574 field_value
= vmcs_read16(field
);
6576 case VMCS_FIELD_TYPE_U32
:
6577 field_value
= vmcs_read32(field
);
6579 case VMCS_FIELD_TYPE_U64
:
6580 field_value
= vmcs_read64(field
);
6582 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6583 field_value
= vmcs_readl(field
);
6589 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6592 vmcs_clear(shadow_vmcs
);
6593 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6598 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6600 const unsigned long *fields
[] = {
6601 shadow_read_write_fields
,
6602 shadow_read_only_fields
6604 const int max_fields
[] = {
6605 max_shadow_read_write_fields
,
6606 max_shadow_read_only_fields
6609 unsigned long field
;
6610 u64 field_value
= 0;
6611 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6613 vmcs_load(shadow_vmcs
);
6615 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6616 for (i
= 0; i
< max_fields
[q
]; i
++) {
6617 field
= fields
[q
][i
];
6618 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6620 switch (vmcs_field_type(field
)) {
6621 case VMCS_FIELD_TYPE_U16
:
6622 vmcs_write16(field
, (u16
)field_value
);
6624 case VMCS_FIELD_TYPE_U32
:
6625 vmcs_write32(field
, (u32
)field_value
);
6627 case VMCS_FIELD_TYPE_U64
:
6628 vmcs_write64(field
, (u64
)field_value
);
6630 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6631 vmcs_writel(field
, (long)field_value
);
6640 vmcs_clear(shadow_vmcs
);
6641 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6645 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6646 * used before) all generate the same failure when it is missing.
6648 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6651 if (vmx
->nested
.current_vmptr
== -1ull) {
6652 nested_vmx_failInvalid(vcpu
);
6653 skip_emulated_instruction(vcpu
);
6659 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6661 unsigned long field
;
6663 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6664 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6667 if (!nested_vmx_check_permission(vcpu
) ||
6668 !nested_vmx_check_vmcs12(vcpu
))
6671 /* Decode instruction info and find the field to read */
6672 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6673 /* Read the field, zero-extended to a u64 field_value */
6674 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
6675 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6676 skip_emulated_instruction(vcpu
);
6680 * Now copy part of this value to register or memory, as requested.
6681 * Note that the number of bits actually copied is 32 or 64 depending
6682 * on the guest's mode (32 or 64 bit), not on the given field's length.
6684 if (vmx_instruction_info
& (1u << 10)) {
6685 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6688 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6689 vmx_instruction_info
, &gva
))
6691 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6692 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6693 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6696 nested_vmx_succeed(vcpu
);
6697 skip_emulated_instruction(vcpu
);
6702 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6704 unsigned long field
;
6706 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6707 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6708 /* The value to write might be 32 or 64 bits, depending on L1's long
6709 * mode, and eventually we need to write that into a field of several
6710 * possible lengths. The code below first zero-extends the value to 64
6711 * bit (field_value), and then copies only the approriate number of
6712 * bits into the vmcs12 field.
6714 u64 field_value
= 0;
6715 struct x86_exception e
;
6717 if (!nested_vmx_check_permission(vcpu
) ||
6718 !nested_vmx_check_vmcs12(vcpu
))
6721 if (vmx_instruction_info
& (1u << 10))
6722 field_value
= kvm_register_readl(vcpu
,
6723 (((vmx_instruction_info
) >> 3) & 0xf));
6725 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6726 vmx_instruction_info
, &gva
))
6728 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6729 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
6730 kvm_inject_page_fault(vcpu
, &e
);
6736 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6737 if (vmcs_field_readonly(field
)) {
6738 nested_vmx_failValid(vcpu
,
6739 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6740 skip_emulated_instruction(vcpu
);
6744 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
6745 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6746 skip_emulated_instruction(vcpu
);
6750 nested_vmx_succeed(vcpu
);
6751 skip_emulated_instruction(vcpu
);
6755 /* Emulate the VMPTRLD instruction */
6756 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6758 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6762 if (!nested_vmx_check_permission(vcpu
))
6765 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6768 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6769 struct vmcs12
*new_vmcs12
;
6771 page
= nested_get_page(vcpu
, vmptr
);
6773 nested_vmx_failInvalid(vcpu
);
6774 skip_emulated_instruction(vcpu
);
6777 new_vmcs12
= kmap(page
);
6778 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6780 nested_release_page_clean(page
);
6781 nested_vmx_failValid(vcpu
,
6782 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6783 skip_emulated_instruction(vcpu
);
6787 nested_release_vmcs12(vmx
);
6788 vmx
->nested
.current_vmptr
= vmptr
;
6789 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6790 vmx
->nested
.current_vmcs12_page
= page
;
6791 if (enable_shadow_vmcs
) {
6792 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6793 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6794 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6795 vmcs_write64(VMCS_LINK_POINTER
,
6796 __pa(vmx
->nested
.current_shadow_vmcs
));
6797 vmx
->nested
.sync_shadow_vmcs
= true;
6801 nested_vmx_succeed(vcpu
);
6802 skip_emulated_instruction(vcpu
);
6806 /* Emulate the VMPTRST instruction */
6807 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6809 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6810 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6812 struct x86_exception e
;
6814 if (!nested_vmx_check_permission(vcpu
))
6817 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6818 vmx_instruction_info
, &vmcs_gva
))
6820 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6821 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6822 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6824 kvm_inject_page_fault(vcpu
, &e
);
6827 nested_vmx_succeed(vcpu
);
6828 skip_emulated_instruction(vcpu
);
6832 /* Emulate the INVEPT instruction */
6833 static int handle_invept(struct kvm_vcpu
*vcpu
)
6835 u32 vmx_instruction_info
, types
;
6838 struct x86_exception e
;
6843 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6844 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6845 kvm_queue_exception(vcpu
, UD_VECTOR
);
6849 if (!nested_vmx_check_permission(vcpu
))
6852 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6853 kvm_queue_exception(vcpu
, UD_VECTOR
);
6857 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6858 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6860 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6862 if (!(types
& (1UL << type
))) {
6863 nested_vmx_failValid(vcpu
,
6864 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6868 /* According to the Intel VMX instruction reference, the memory
6869 * operand is read even if it isn't needed (e.g., for type==global)
6871 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6872 vmx_instruction_info
, &gva
))
6874 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6875 sizeof(operand
), &e
)) {
6876 kvm_inject_page_fault(vcpu
, &e
);
6881 case VMX_EPT_EXTENT_GLOBAL
:
6882 kvm_mmu_sync_roots(vcpu
);
6883 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
6884 nested_vmx_succeed(vcpu
);
6887 /* Trap single context invalidation invept calls */
6892 skip_emulated_instruction(vcpu
);
6896 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
6898 kvm_queue_exception(vcpu
, UD_VECTOR
);
6903 * The exit handlers return 1 if the exit was handled fully and guest execution
6904 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6905 * to be done to userspace and return 0.
6907 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6908 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6909 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6910 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6911 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6912 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6913 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6914 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6915 [EXIT_REASON_CPUID
] = handle_cpuid
,
6916 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6917 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6918 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6919 [EXIT_REASON_HLT
] = handle_halt
,
6920 [EXIT_REASON_INVD
] = handle_invd
,
6921 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6922 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6923 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6924 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6925 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6926 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6927 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6928 [EXIT_REASON_VMREAD
] = handle_vmread
,
6929 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6930 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6931 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6932 [EXIT_REASON_VMON
] = handle_vmon
,
6933 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6934 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6935 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6936 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6937 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6938 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6939 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6940 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6941 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6942 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6943 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6944 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
6945 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
6946 [EXIT_REASON_INVEPT
] = handle_invept
,
6947 [EXIT_REASON_INVVPID
] = handle_invvpid
,
6950 static const int kvm_vmx_max_exit_handlers
=
6951 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6953 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6954 struct vmcs12
*vmcs12
)
6956 unsigned long exit_qualification
;
6957 gpa_t bitmap
, last_bitmap
;
6962 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6963 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6965 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6967 port
= exit_qualification
>> 16;
6968 size
= (exit_qualification
& 7) + 1;
6970 last_bitmap
= (gpa_t
)-1;
6975 bitmap
= vmcs12
->io_bitmap_a
;
6976 else if (port
< 0x10000)
6977 bitmap
= vmcs12
->io_bitmap_b
;
6980 bitmap
+= (port
& 0x7fff) / 8;
6982 if (last_bitmap
!= bitmap
)
6983 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6985 if (b
& (1 << (port
& 7)))
6990 last_bitmap
= bitmap
;
6997 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6998 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6999 * disinterest in the current event (read or write a specific MSR) by using an
7000 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7002 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7003 struct vmcs12
*vmcs12
, u32 exit_reason
)
7005 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7008 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7012 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7013 * for the four combinations of read/write and low/high MSR numbers.
7014 * First we need to figure out which of the four to use:
7016 bitmap
= vmcs12
->msr_bitmap
;
7017 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7019 if (msr_index
>= 0xc0000000) {
7020 msr_index
-= 0xc0000000;
7024 /* Then read the msr_index'th bit from this bitmap: */
7025 if (msr_index
< 1024*8) {
7027 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
7029 return 1 & (b
>> (msr_index
& 7));
7031 return 1; /* let L1 handle the wrong parameter */
7035 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7036 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7037 * intercept (via guest_host_mask etc.) the current event.
7039 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7040 struct vmcs12
*vmcs12
)
7042 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7043 int cr
= exit_qualification
& 15;
7044 int reg
= (exit_qualification
>> 8) & 15;
7045 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7047 switch ((exit_qualification
>> 4) & 3) {
7048 case 0: /* mov to cr */
7051 if (vmcs12
->cr0_guest_host_mask
&
7052 (val
^ vmcs12
->cr0_read_shadow
))
7056 if ((vmcs12
->cr3_target_count
>= 1 &&
7057 vmcs12
->cr3_target_value0
== val
) ||
7058 (vmcs12
->cr3_target_count
>= 2 &&
7059 vmcs12
->cr3_target_value1
== val
) ||
7060 (vmcs12
->cr3_target_count
>= 3 &&
7061 vmcs12
->cr3_target_value2
== val
) ||
7062 (vmcs12
->cr3_target_count
>= 4 &&
7063 vmcs12
->cr3_target_value3
== val
))
7065 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7069 if (vmcs12
->cr4_guest_host_mask
&
7070 (vmcs12
->cr4_read_shadow
^ val
))
7074 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7080 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7081 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7084 case 1: /* mov from cr */
7087 if (vmcs12
->cpu_based_vm_exec_control
&
7088 CPU_BASED_CR3_STORE_EXITING
)
7092 if (vmcs12
->cpu_based_vm_exec_control
&
7093 CPU_BASED_CR8_STORE_EXITING
)
7100 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7101 * cr0. Other attempted changes are ignored, with no exit.
7103 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7104 (val
^ vmcs12
->cr0_read_shadow
))
7106 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7107 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7116 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7117 * should handle it ourselves in L0 (and then continue L2). Only call this
7118 * when in is_guest_mode (L2).
7120 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7122 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7123 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7124 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7125 u32 exit_reason
= vmx
->exit_reason
;
7127 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7128 vmcs_readl(EXIT_QUALIFICATION
),
7129 vmx
->idt_vectoring_info
,
7131 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7134 if (vmx
->nested
.nested_run_pending
)
7137 if (unlikely(vmx
->fail
)) {
7138 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7139 vmcs_read32(VM_INSTRUCTION_ERROR
));
7143 switch (exit_reason
) {
7144 case EXIT_REASON_EXCEPTION_NMI
:
7145 if (!is_exception(intr_info
))
7147 else if (is_page_fault(intr_info
))
7149 else if (is_no_device(intr_info
) &&
7150 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7152 return vmcs12
->exception_bitmap
&
7153 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7154 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7156 case EXIT_REASON_TRIPLE_FAULT
:
7158 case EXIT_REASON_PENDING_INTERRUPT
:
7159 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7160 case EXIT_REASON_NMI_WINDOW
:
7161 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7162 case EXIT_REASON_TASK_SWITCH
:
7164 case EXIT_REASON_CPUID
:
7165 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7168 case EXIT_REASON_HLT
:
7169 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7170 case EXIT_REASON_INVD
:
7172 case EXIT_REASON_INVLPG
:
7173 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7174 case EXIT_REASON_RDPMC
:
7175 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7176 case EXIT_REASON_RDTSC
:
7177 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7178 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7179 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7180 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7181 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7182 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7183 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7185 * VMX instructions trap unconditionally. This allows L1 to
7186 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7189 case EXIT_REASON_CR_ACCESS
:
7190 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7191 case EXIT_REASON_DR_ACCESS
:
7192 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7193 case EXIT_REASON_IO_INSTRUCTION
:
7194 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7195 case EXIT_REASON_MSR_READ
:
7196 case EXIT_REASON_MSR_WRITE
:
7197 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7198 case EXIT_REASON_INVALID_STATE
:
7200 case EXIT_REASON_MWAIT_INSTRUCTION
:
7201 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7202 case EXIT_REASON_MONITOR_INSTRUCTION
:
7203 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7204 case EXIT_REASON_PAUSE_INSTRUCTION
:
7205 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7206 nested_cpu_has2(vmcs12
,
7207 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7208 case EXIT_REASON_MCE_DURING_VMENTRY
:
7210 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7211 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7212 case EXIT_REASON_APIC_ACCESS
:
7213 return nested_cpu_has2(vmcs12
,
7214 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7215 case EXIT_REASON_EPT_VIOLATION
:
7217 * L0 always deals with the EPT violation. If nested EPT is
7218 * used, and the nested mmu code discovers that the address is
7219 * missing in the guest EPT table (EPT12), the EPT violation
7220 * will be injected with nested_ept_inject_page_fault()
7223 case EXIT_REASON_EPT_MISCONFIG
:
7225 * L2 never uses directly L1's EPT, but rather L0's own EPT
7226 * table (shadow on EPT) or a merged EPT table that L0 built
7227 * (EPT on EPT). So any problems with the structure of the
7228 * table is L0's fault.
7231 case EXIT_REASON_WBINVD
:
7232 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7233 case EXIT_REASON_XSETBV
:
7240 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7242 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7243 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7247 * The guest has exited. See if we can fix it or if we need userspace
7250 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7252 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7253 u32 exit_reason
= vmx
->exit_reason
;
7254 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7256 /* If guest state is invalid, start emulating */
7257 if (vmx
->emulation_required
)
7258 return handle_invalid_guest_state(vcpu
);
7260 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7261 nested_vmx_vmexit(vcpu
, exit_reason
,
7262 vmcs_read32(VM_EXIT_INTR_INFO
),
7263 vmcs_readl(EXIT_QUALIFICATION
));
7267 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7268 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7269 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7274 if (unlikely(vmx
->fail
)) {
7275 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7276 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7277 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7283 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7284 * delivery event since it indicates guest is accessing MMIO.
7285 * The vm-exit can be triggered again after return to guest that
7286 * will cause infinite loop.
7288 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7289 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7290 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7291 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7292 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7293 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7294 vcpu
->run
->internal
.ndata
= 2;
7295 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7296 vcpu
->run
->internal
.data
[1] = exit_reason
;
7300 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7301 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7302 get_vmcs12(vcpu
))))) {
7303 if (vmx_interrupt_allowed(vcpu
)) {
7304 vmx
->soft_vnmi_blocked
= 0;
7305 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7306 vcpu
->arch
.nmi_pending
) {
7308 * This CPU don't support us in finding the end of an
7309 * NMI-blocked window if the guest runs with IRQs
7310 * disabled. So we pull the trigger after 1 s of
7311 * futile waiting, but inform the user about this.
7313 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7314 "state on VCPU %d after 1 s timeout\n",
7315 __func__
, vcpu
->vcpu_id
);
7316 vmx
->soft_vnmi_blocked
= 0;
7320 if (exit_reason
< kvm_vmx_max_exit_handlers
7321 && kvm_vmx_exit_handlers
[exit_reason
])
7322 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7324 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7325 kvm_queue_exception(vcpu
, UD_VECTOR
);
7330 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7332 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7334 if (is_guest_mode(vcpu
) &&
7335 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7338 if (irr
== -1 || tpr
< irr
) {
7339 vmcs_write32(TPR_THRESHOLD
, 0);
7343 vmcs_write32(TPR_THRESHOLD
, irr
);
7346 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7348 u32 sec_exec_control
;
7351 * There is not point to enable virtualize x2apic without enable
7354 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7355 !vmx_vm_has_apicv(vcpu
->kvm
))
7358 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7361 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7364 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7365 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7367 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7368 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7370 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7372 vmx_set_msr_bitmap(vcpu
);
7375 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
7377 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7380 * Currently we do not handle the nested case where L2 has an
7381 * APIC access page of its own; that page is still pinned.
7382 * Hence, we skip the case where the VCPU is in guest mode _and_
7383 * L1 prepared an APIC access page for L2.
7385 * For the case where L1 and L2 share the same APIC access page
7386 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7387 * in the vmcs12), this function will only update either the vmcs01
7388 * or the vmcs02. If the former, the vmcs02 will be updated by
7389 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7390 * the next L2->L1 exit.
7392 if (!is_guest_mode(vcpu
) ||
7393 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
7394 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
7395 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
7398 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7403 if (!vmx_vm_has_apicv(kvm
))
7409 status
= vmcs_read16(GUEST_INTR_STATUS
);
7414 vmcs_write16(GUEST_INTR_STATUS
, status
);
7418 static void vmx_set_rvi(int vector
)
7426 status
= vmcs_read16(GUEST_INTR_STATUS
);
7427 old
= (u8
)status
& 0xff;
7428 if ((u8
)vector
!= old
) {
7430 status
|= (u8
)vector
;
7431 vmcs_write16(GUEST_INTR_STATUS
, status
);
7435 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7437 if (!is_guest_mode(vcpu
)) {
7438 vmx_set_rvi(max_irr
);
7446 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7449 if (nested_exit_on_intr(vcpu
))
7453 * Else, fall back to pre-APICv interrupt injection since L2
7454 * is run without virtual interrupt delivery.
7456 if (!kvm_event_needs_reinjection(vcpu
) &&
7457 vmx_interrupt_allowed(vcpu
)) {
7458 kvm_queue_interrupt(vcpu
, max_irr
, false);
7459 vmx_inject_irq(vcpu
);
7463 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7465 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7468 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7469 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7470 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7471 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7474 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7478 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7479 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7482 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7483 exit_intr_info
= vmx
->exit_intr_info
;
7485 /* Handle machine checks before interrupts are enabled */
7486 if (is_machine_check(exit_intr_info
))
7487 kvm_machine_check();
7489 /* We need to handle NMIs before interrupts are enabled */
7490 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7491 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7492 kvm_before_handle_nmi(&vmx
->vcpu
);
7494 kvm_after_handle_nmi(&vmx
->vcpu
);
7498 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7500 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7503 * If external interrupt exists, IF bit is set in rflags/eflags on the
7504 * interrupt stack frame, and interrupt will be enabled on a return
7505 * from interrupt handler.
7507 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7508 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7509 unsigned int vector
;
7510 unsigned long entry
;
7512 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7513 #ifdef CONFIG_X86_64
7517 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7518 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7519 entry
= gate_offset(*desc
);
7521 #ifdef CONFIG_X86_64
7522 "mov %%" _ASM_SP
", %[sp]\n\t"
7523 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7528 "orl $0x200, (%%" _ASM_SP
")\n\t"
7529 __ASM_SIZE(push
) " $%c[cs]\n\t"
7530 "call *%[entry]\n\t"
7532 #ifdef CONFIG_X86_64
7537 [ss
]"i"(__KERNEL_DS
),
7538 [cs
]"i"(__KERNEL_CS
)
7544 static bool vmx_mpx_supported(void)
7546 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7547 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7550 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7555 bool idtv_info_valid
;
7557 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7559 if (cpu_has_virtual_nmis()) {
7560 if (vmx
->nmi_known_unmasked
)
7563 * Can't use vmx->exit_intr_info since we're not sure what
7564 * the exit reason is.
7566 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7567 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7568 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7570 * SDM 3: 27.7.1.2 (September 2008)
7571 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7572 * a guest IRET fault.
7573 * SDM 3: 23.2.2 (September 2008)
7574 * Bit 12 is undefined in any of the following cases:
7575 * If the VM exit sets the valid bit in the IDT-vectoring
7576 * information field.
7577 * If the VM exit is due to a double fault.
7579 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7580 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7581 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7582 GUEST_INTR_STATE_NMI
);
7584 vmx
->nmi_known_unmasked
=
7585 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7586 & GUEST_INTR_STATE_NMI
);
7587 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7588 vmx
->vnmi_blocked_time
+=
7589 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7592 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7593 u32 idt_vectoring_info
,
7594 int instr_len_field
,
7595 int error_code_field
)
7599 bool idtv_info_valid
;
7601 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7603 vcpu
->arch
.nmi_injected
= false;
7604 kvm_clear_exception_queue(vcpu
);
7605 kvm_clear_interrupt_queue(vcpu
);
7607 if (!idtv_info_valid
)
7610 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7612 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7613 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7616 case INTR_TYPE_NMI_INTR
:
7617 vcpu
->arch
.nmi_injected
= true;
7619 * SDM 3: 27.7.1.2 (September 2008)
7620 * Clear bit "block by NMI" before VM entry if a NMI
7623 vmx_set_nmi_mask(vcpu
, false);
7625 case INTR_TYPE_SOFT_EXCEPTION
:
7626 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7628 case INTR_TYPE_HARD_EXCEPTION
:
7629 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7630 u32 err
= vmcs_read32(error_code_field
);
7631 kvm_requeue_exception_e(vcpu
, vector
, err
);
7633 kvm_requeue_exception(vcpu
, vector
);
7635 case INTR_TYPE_SOFT_INTR
:
7636 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7638 case INTR_TYPE_EXT_INTR
:
7639 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7646 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7648 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7649 VM_EXIT_INSTRUCTION_LEN
,
7650 IDT_VECTORING_ERROR_CODE
);
7653 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7655 __vmx_complete_interrupts(vcpu
,
7656 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7657 VM_ENTRY_INSTRUCTION_LEN
,
7658 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7660 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7663 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7666 struct perf_guest_switch_msr
*msrs
;
7668 msrs
= perf_guest_get_msrs(&nr_msrs
);
7673 for (i
= 0; i
< nr_msrs
; i
++)
7674 if (msrs
[i
].host
== msrs
[i
].guest
)
7675 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7677 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7681 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7683 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7684 unsigned long debugctlmsr
, cr4
;
7686 /* Record the guest's net vcpu time for enforced NMI injections. */
7687 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7688 vmx
->entry_time
= ktime_get();
7690 /* Don't enter VMX if guest state is invalid, let the exit handler
7691 start emulation until we arrive back to a valid state */
7692 if (vmx
->emulation_required
)
7695 if (vmx
->ple_window_dirty
) {
7696 vmx
->ple_window_dirty
= false;
7697 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
7700 if (vmx
->nested
.sync_shadow_vmcs
) {
7701 copy_vmcs12_to_shadow(vmx
);
7702 vmx
->nested
.sync_shadow_vmcs
= false;
7705 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7706 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7707 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7708 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7711 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
7712 vmcs_writel(HOST_CR4
, cr4
);
7713 vmx
->host_state
.vmcs_host_cr4
= cr4
;
7716 /* When single-stepping over STI and MOV SS, we must clear the
7717 * corresponding interruptibility bits in the guest state. Otherwise
7718 * vmentry fails as it then expects bit 14 (BS) in pending debug
7719 * exceptions being set, but that's not correct for the guest debugging
7721 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7722 vmx_set_interrupt_shadow(vcpu
, 0);
7724 atomic_switch_perf_msrs(vmx
);
7725 debugctlmsr
= get_debugctlmsr();
7727 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7729 /* Store host registers */
7730 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7731 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7732 "push %%" _ASM_CX
" \n\t"
7733 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7735 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7736 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7738 /* Reload cr2 if changed */
7739 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7740 "mov %%cr2, %%" _ASM_DX
" \n\t"
7741 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7743 "mov %%" _ASM_AX
", %%cr2 \n\t"
7745 /* Check if vmlaunch of vmresume is needed */
7746 "cmpl $0, %c[launched](%0) \n\t"
7747 /* Load guest registers. Don't clobber flags. */
7748 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7749 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7750 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7751 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7752 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7753 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7754 #ifdef CONFIG_X86_64
7755 "mov %c[r8](%0), %%r8 \n\t"
7756 "mov %c[r9](%0), %%r9 \n\t"
7757 "mov %c[r10](%0), %%r10 \n\t"
7758 "mov %c[r11](%0), %%r11 \n\t"
7759 "mov %c[r12](%0), %%r12 \n\t"
7760 "mov %c[r13](%0), %%r13 \n\t"
7761 "mov %c[r14](%0), %%r14 \n\t"
7762 "mov %c[r15](%0), %%r15 \n\t"
7764 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7766 /* Enter guest mode */
7768 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7770 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7772 /* Save guest registers, load host registers, keep flags */
7773 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7775 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7776 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7777 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7778 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7779 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7780 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7781 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7782 #ifdef CONFIG_X86_64
7783 "mov %%r8, %c[r8](%0) \n\t"
7784 "mov %%r9, %c[r9](%0) \n\t"
7785 "mov %%r10, %c[r10](%0) \n\t"
7786 "mov %%r11, %c[r11](%0) \n\t"
7787 "mov %%r12, %c[r12](%0) \n\t"
7788 "mov %%r13, %c[r13](%0) \n\t"
7789 "mov %%r14, %c[r14](%0) \n\t"
7790 "mov %%r15, %c[r15](%0) \n\t"
7792 "mov %%cr2, %%" _ASM_AX
" \n\t"
7793 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7795 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7796 "setbe %c[fail](%0) \n\t"
7797 ".pushsection .rodata \n\t"
7798 ".global vmx_return \n\t"
7799 "vmx_return: " _ASM_PTR
" 2b \n\t"
7801 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7802 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7803 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7804 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7805 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7806 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7807 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7808 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7809 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7810 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7811 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7812 #ifdef CONFIG_X86_64
7813 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7814 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7815 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7816 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7817 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7818 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7819 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7820 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7822 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7823 [wordsize
]"i"(sizeof(ulong
))
7825 #ifdef CONFIG_X86_64
7826 , "rax", "rbx", "rdi", "rsi"
7827 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7829 , "eax", "ebx", "edi", "esi"
7833 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7835 update_debugctlmsr(debugctlmsr
);
7837 #ifndef CONFIG_X86_64
7839 * The sysexit path does not restore ds/es, so we must set them to
7840 * a reasonable value ourselves.
7842 * We can't defer this to vmx_load_host_state() since that function
7843 * may be executed in interrupt context, which saves and restore segments
7844 * around it, nullifying its effect.
7846 loadsegment(ds
, __USER_DS
);
7847 loadsegment(es
, __USER_DS
);
7850 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7851 | (1 << VCPU_EXREG_RFLAGS
)
7852 | (1 << VCPU_EXREG_PDPTR
)
7853 | (1 << VCPU_EXREG_SEGMENTS
)
7854 | (1 << VCPU_EXREG_CR3
));
7855 vcpu
->arch
.regs_dirty
= 0;
7857 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7859 vmx
->loaded_vmcs
->launched
= 1;
7861 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7862 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7865 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7866 * we did not inject a still-pending event to L1 now because of
7867 * nested_run_pending, we need to re-enable this bit.
7869 if (vmx
->nested
.nested_run_pending
)
7870 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7872 vmx
->nested
.nested_run_pending
= 0;
7874 vmx_complete_atomic_exit(vmx
);
7875 vmx_recover_nmi_blocking(vmx
);
7876 vmx_complete_interrupts(vmx
);
7879 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
7881 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7884 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
7888 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7890 vmx_vcpu_load(vcpu
, cpu
);
7895 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7897 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7900 leave_guest_mode(vcpu
);
7901 vmx_load_vmcs01(vcpu
);
7903 free_loaded_vmcs(vmx
->loaded_vmcs
);
7904 kfree(vmx
->guest_msrs
);
7905 kvm_vcpu_uninit(vcpu
);
7906 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7909 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7912 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7916 return ERR_PTR(-ENOMEM
);
7920 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7924 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7925 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
7929 if (!vmx
->guest_msrs
) {
7933 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7934 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7935 if (!vmx
->loaded_vmcs
->vmcs
)
7938 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7939 loaded_vmcs_init(vmx
->loaded_vmcs
);
7944 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7945 vmx
->vcpu
.cpu
= cpu
;
7946 err
= vmx_vcpu_setup(vmx
);
7947 vmx_vcpu_put(&vmx
->vcpu
);
7951 if (vm_need_virtualize_apic_accesses(kvm
)) {
7952 err
= alloc_apic_access_page(kvm
);
7958 if (!kvm
->arch
.ept_identity_map_addr
)
7959 kvm
->arch
.ept_identity_map_addr
=
7960 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7961 err
= init_rmode_identity_map(kvm
);
7966 vmx
->nested
.current_vmptr
= -1ull;
7967 vmx
->nested
.current_vmcs12
= NULL
;
7972 free_loaded_vmcs(vmx
->loaded_vmcs
);
7974 kfree(vmx
->guest_msrs
);
7976 kvm_vcpu_uninit(&vmx
->vcpu
);
7979 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7980 return ERR_PTR(err
);
7983 static void __init
vmx_check_processor_compat(void *rtn
)
7985 struct vmcs_config vmcs_conf
;
7988 if (setup_vmcs_config(&vmcs_conf
) < 0)
7990 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7991 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7992 smp_processor_id());
7997 static int get_ept_level(void)
7999 return VMX_EPT_DEFAULT_GAW
+ 1;
8002 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8006 /* For VT-d and EPT combination
8007 * 1. MMIO: always map as UC
8009 * a. VT-d without snooping control feature: can't guarantee the
8010 * result, try to trust guest.
8011 * b. VT-d with snooping control feature: snooping control feature of
8012 * VT-d engine can guarantee the cache correctness. Just set it
8013 * to WB to keep consistent with host. So the same as item 3.
8014 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8015 * consistent with host MTRR
8018 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
8019 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
8020 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
8021 VMX_EPT_MT_EPTE_SHIFT
;
8023 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
8029 static int vmx_get_lpage_level(void)
8031 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8032 return PT_DIRECTORY_LEVEL
;
8034 /* For shadow and EPT supported 1GB page */
8035 return PT_PDPE_LEVEL
;
8038 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8040 struct kvm_cpuid_entry2
*best
;
8041 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8044 vmx
->rdtscp_enabled
= false;
8045 if (vmx_rdtscp_supported()) {
8046 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8047 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
8048 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
8049 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
8050 vmx
->rdtscp_enabled
= true;
8052 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8053 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8059 /* Exposing INVPCID only when PCID is exposed */
8060 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8061 if (vmx_invpcid_supported() &&
8062 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
8063 guest_cpuid_has_pcid(vcpu
)) {
8064 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8065 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
8066 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8069 if (cpu_has_secondary_exec_ctrls()) {
8070 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8071 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8072 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8076 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8080 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8082 if (func
== 1 && nested
)
8083 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8086 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8087 struct x86_exception
*fault
)
8089 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8092 if (fault
->error_code
& PFERR_RSVD_MASK
)
8093 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8095 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8096 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8097 vmcs12
->guest_physical_address
= fault
->address
;
8100 /* Callbacks for nested_ept_init_mmu_context: */
8102 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8104 /* return the page table to be shadowed - in our case, EPT12 */
8105 return get_vmcs12(vcpu
)->ept_pointer
;
8108 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8110 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
8111 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
8113 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8114 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8115 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8117 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8120 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8122 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8125 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8126 struct x86_exception
*fault
)
8128 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8130 WARN_ON(!is_guest_mode(vcpu
));
8132 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8133 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
8134 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8135 vmcs_read32(VM_EXIT_INTR_INFO
),
8136 vmcs_readl(EXIT_QUALIFICATION
));
8138 kvm_inject_page_fault(vcpu
, fault
);
8141 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8142 struct vmcs12
*vmcs12
)
8144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8146 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8147 /* TODO: Also verify bits beyond physical address width are 0 */
8148 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
))
8152 * Translate L1 physical address to host physical
8153 * address for vmcs02. Keep the page pinned, so this
8154 * physical address remains valid. We keep a reference
8155 * to it so we can release it later.
8157 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8158 nested_release_page(vmx
->nested
.apic_access_page
);
8159 vmx
->nested
.apic_access_page
=
8160 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8163 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8164 /* TODO: Also verify bits beyond physical address width are 0 */
8165 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
))
8168 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8169 nested_release_page(vmx
->nested
.virtual_apic_page
);
8170 vmx
->nested
.virtual_apic_page
=
8171 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8174 * Failing the vm entry is _not_ what the processor does
8175 * but it's basically the only possibility we have.
8176 * We could still enter the guest if CR8 load exits are
8177 * enabled, CR8 store exits are enabled, and virtualize APIC
8178 * access is disabled; in this case the processor would never
8179 * use the TPR shadow and we could simply clear the bit from
8180 * the execution control. But such a configuration is useless,
8181 * so let's keep the code simple.
8183 if (!vmx
->nested
.virtual_apic_page
)
8190 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8192 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8195 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8198 /* Make sure short timeouts reliably trigger an immediate vmexit.
8199 * hrtimer_start does not guarantee this. */
8200 if (preemption_timeout
<= 1) {
8201 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8205 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8206 preemption_timeout
*= 1000000;
8207 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8208 hrtimer_start(&vmx
->nested
.preemption_timer
,
8209 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8213 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8214 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8215 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8216 * guest in a way that will both be appropriate to L1's requests, and our
8217 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8218 * function also has additional necessary side-effects, like setting various
8219 * vcpu->arch fields.
8221 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8223 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8226 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
8227 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
8228 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
8229 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
8230 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
8231 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
8232 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
8233 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
8234 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
8235 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
8236 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
8237 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
8238 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
8239 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
8240 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
8241 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
8242 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
8243 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
8244 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
8245 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
8246 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
8247 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
8248 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
8249 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
8250 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
8251 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
8252 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
8253 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
8254 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
8255 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
8256 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
8257 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
8258 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
8259 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
8260 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
8261 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
8263 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
8264 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
8265 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
8267 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
8268 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
8270 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
8271 vmcs12
->vm_entry_intr_info_field
);
8272 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
8273 vmcs12
->vm_entry_exception_error_code
);
8274 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
8275 vmcs12
->vm_entry_instruction_len
);
8276 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
8277 vmcs12
->guest_interruptibility_info
);
8278 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
8279 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
8280 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
8281 vmcs12
->guest_pending_dbg_exceptions
);
8282 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
8283 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
8285 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
8287 exec_control
= vmcs12
->pin_based_vm_exec_control
;
8288 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
8289 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
8290 PIN_BASED_POSTED_INTR
);
8291 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
8293 vmx
->nested
.preemption_timer_expired
= false;
8294 if (nested_cpu_has_preemption_timer(vmcs12
))
8295 vmx_start_preemption_timer(vcpu
);
8298 * Whether page-faults are trapped is determined by a combination of
8299 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8300 * If enable_ept, L0 doesn't care about page faults and we should
8301 * set all of these to L1's desires. However, if !enable_ept, L0 does
8302 * care about (at least some) page faults, and because it is not easy
8303 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8304 * to exit on each and every L2 page fault. This is done by setting
8305 * MASK=MATCH=0 and (see below) EB.PF=1.
8306 * Note that below we don't need special code to set EB.PF beyond the
8307 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8308 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8309 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8311 * A problem with this approach (when !enable_ept) is that L1 may be
8312 * injected with more page faults than it asked for. This could have
8313 * caused problems, but in practice existing hypervisors don't care.
8314 * To fix this, we will need to emulate the PFEC checking (on the L1
8315 * page tables), using walk_addr(), when injecting PFs to L1.
8317 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
8318 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
8319 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
8320 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
8322 if (cpu_has_secondary_exec_ctrls()) {
8323 exec_control
= vmx_secondary_exec_control(vmx
);
8324 if (!vmx
->rdtscp_enabled
)
8325 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8326 /* Take the following fields only from vmcs12 */
8327 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
8328 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
8329 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
8330 if (nested_cpu_has(vmcs12
,
8331 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
8332 exec_control
|= vmcs12
->secondary_vm_exec_control
;
8334 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
8336 * If translation failed, no matter: This feature asks
8337 * to exit when accessing the given address, and if it
8338 * can never be accessed, this feature won't do
8341 if (!vmx
->nested
.apic_access_page
)
8343 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8345 vmcs_write64(APIC_ACCESS_ADDR
,
8346 page_to_phys(vmx
->nested
.apic_access_page
));
8347 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
8349 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8350 kvm_vcpu_reload_apic_access_page(vcpu
);
8353 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
8358 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8359 * Some constant fields are set here by vmx_set_constant_host_state().
8360 * Other fields are different per CPU, and will be set later when
8361 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8363 vmx_set_constant_host_state(vmx
);
8366 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8367 * entry, but only if the current (host) sp changed from the value
8368 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8369 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8370 * here we just force the write to happen on entry.
8374 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
8375 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
8376 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
8377 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
8378 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
8380 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
8381 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
8382 page_to_phys(vmx
->nested
.virtual_apic_page
));
8383 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
8387 * Merging of IO and MSR bitmaps not currently supported.
8388 * Rather, exit every time.
8390 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
8391 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
8392 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
8394 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
8396 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8397 * bitwise-or of what L1 wants to trap for L2, and what we want to
8398 * trap. Note that CR0.TS also needs updating - we do this later.
8400 update_exception_bitmap(vcpu
);
8401 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
8402 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8404 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8405 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8406 * bits are further modified by vmx_set_efer() below.
8408 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
8410 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8411 * emulated by vmx_set_efer(), below.
8413 vm_entry_controls_init(vmx
,
8414 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
8415 ~VM_ENTRY_IA32E_MODE
) |
8416 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
8418 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
8419 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
8420 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
8421 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
8422 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
8425 set_cr4_guest_host_mask(vmx
);
8427 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
8428 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
8430 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
8431 vmcs_write64(TSC_OFFSET
,
8432 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
8434 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8438 * Trivially support vpid by letting L2s share their parent
8439 * L1's vpid. TODO: move to a more elaborate solution, giving
8440 * each L2 its own vpid and exposing the vpid feature to L1.
8442 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
8443 vmx_flush_tlb(vcpu
);
8446 if (nested_cpu_has_ept(vmcs12
)) {
8447 kvm_mmu_unload(vcpu
);
8448 nested_ept_init_mmu_context(vcpu
);
8451 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
8452 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
8453 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
8454 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8456 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8457 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8458 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8461 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8462 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8463 * The CR0_READ_SHADOW is what L2 should have expected to read given
8464 * the specifications by L1; It's not enough to take
8465 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8466 * have more bits than L1 expected.
8468 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
8469 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
8471 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
8472 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
8474 /* shadow page tables on either EPT or shadow page tables */
8475 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
8476 kvm_mmu_reset_context(vcpu
);
8479 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
8482 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8485 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
8486 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
8487 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
8488 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
8491 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
8492 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
8496 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8497 * for running an L2 nested guest.
8499 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
8501 struct vmcs12
*vmcs12
;
8502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8504 struct loaded_vmcs
*vmcs02
;
8507 if (!nested_vmx_check_permission(vcpu
) ||
8508 !nested_vmx_check_vmcs12(vcpu
))
8511 skip_emulated_instruction(vcpu
);
8512 vmcs12
= get_vmcs12(vcpu
);
8514 if (enable_shadow_vmcs
)
8515 copy_shadow_to_vmcs12(vmx
);
8518 * The nested entry process starts with enforcing various prerequisites
8519 * on vmcs12 as required by the Intel SDM, and act appropriately when
8520 * they fail: As the SDM explains, some conditions should cause the
8521 * instruction to fail, while others will cause the instruction to seem
8522 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8523 * To speed up the normal (success) code path, we should avoid checking
8524 * for misconfigurations which will anyway be caught by the processor
8525 * when using the merged vmcs02.
8527 if (vmcs12
->launch_state
== launch
) {
8528 nested_vmx_failValid(vcpu
,
8529 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8530 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
8534 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
8535 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
8536 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8540 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
8541 !PAGE_ALIGNED(vmcs12
->msr_bitmap
)) {
8542 /*TODO: Also verify bits beyond physical address width are 0*/
8543 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8547 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
8548 /*TODO: Also verify bits beyond physical address width are 0*/
8549 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8553 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8554 vmcs12
->vm_exit_msr_load_count
> 0 ||
8555 vmcs12
->vm_exit_msr_store_count
> 0) {
8556 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8558 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8562 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8563 nested_vmx_true_procbased_ctls_low
,
8564 nested_vmx_procbased_ctls_high
) ||
8565 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8566 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8567 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8568 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8569 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8570 nested_vmx_true_exit_ctls_low
,
8571 nested_vmx_exit_ctls_high
) ||
8572 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8573 nested_vmx_true_entry_ctls_low
,
8574 nested_vmx_entry_ctls_high
))
8576 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8580 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8581 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8582 nested_vmx_failValid(vcpu
,
8583 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8587 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8588 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8589 nested_vmx_entry_failure(vcpu
, vmcs12
,
8590 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8593 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8594 nested_vmx_entry_failure(vcpu
, vmcs12
,
8595 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8600 * If the load IA32_EFER VM-entry control is 1, the following checks
8601 * are performed on the field for the IA32_EFER MSR:
8602 * - Bits reserved in the IA32_EFER MSR must be 0.
8603 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8604 * the IA-32e mode guest VM-exit control. It must also be identical
8605 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8608 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8609 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8610 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8611 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8612 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8613 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8614 nested_vmx_entry_failure(vcpu
, vmcs12
,
8615 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8621 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8622 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8623 * the values of the LMA and LME bits in the field must each be that of
8624 * the host address-space size VM-exit control.
8626 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8627 ia32e
= (vmcs12
->vm_exit_controls
&
8628 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8629 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8630 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8631 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8632 nested_vmx_entry_failure(vcpu
, vmcs12
,
8633 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8639 * We're finally done with prerequisite checking, and can start with
8643 vmcs02
= nested_get_current_vmcs02(vmx
);
8647 enter_guest_mode(vcpu
);
8649 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8651 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
8652 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8655 vmx
->loaded_vmcs
= vmcs02
;
8657 vmx_vcpu_load(vcpu
, cpu
);
8661 vmx_segment_cache_clear(vmx
);
8663 vmcs12
->launch_state
= 1;
8665 prepare_vmcs02(vcpu
, vmcs12
);
8667 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8668 return kvm_emulate_halt(vcpu
);
8670 vmx
->nested
.nested_run_pending
= 1;
8673 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8674 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8675 * returned as far as L1 is concerned. It will only return (and set
8676 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8682 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8683 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8684 * This function returns the new value we should put in vmcs12.guest_cr0.
8685 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8686 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8687 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8688 * didn't trap the bit, because if L1 did, so would L0).
8689 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8690 * been modified by L2, and L1 knows it. So just leave the old value of
8691 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8692 * isn't relevant, because if L0 traps this bit it can set it to anything.
8693 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8694 * changed these bits, and therefore they need to be updated, but L0
8695 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8696 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8698 static inline unsigned long
8699 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8702 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8703 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8704 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8705 vcpu
->arch
.cr0_guest_owned_bits
));
8708 static inline unsigned long
8709 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8712 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8713 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8714 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8715 vcpu
->arch
.cr4_guest_owned_bits
));
8718 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8719 struct vmcs12
*vmcs12
)
8724 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8725 nr
= vcpu
->arch
.exception
.nr
;
8726 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8728 if (kvm_exception_is_soft(nr
)) {
8729 vmcs12
->vm_exit_instruction_len
=
8730 vcpu
->arch
.event_exit_inst_len
;
8731 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8733 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8735 if (vcpu
->arch
.exception
.has_error_code
) {
8736 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8737 vmcs12
->idt_vectoring_error_code
=
8738 vcpu
->arch
.exception
.error_code
;
8741 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8742 } else if (vcpu
->arch
.nmi_injected
) {
8743 vmcs12
->idt_vectoring_info_field
=
8744 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8745 } else if (vcpu
->arch
.interrupt
.pending
) {
8746 nr
= vcpu
->arch
.interrupt
.nr
;
8747 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8749 if (vcpu
->arch
.interrupt
.soft
) {
8750 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8751 vmcs12
->vm_entry_instruction_len
=
8752 vcpu
->arch
.event_exit_inst_len
;
8754 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8756 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8760 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8764 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8765 vmx
->nested
.preemption_timer_expired
) {
8766 if (vmx
->nested
.nested_run_pending
)
8768 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8772 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8773 if (vmx
->nested
.nested_run_pending
||
8774 vcpu
->arch
.interrupt
.pending
)
8776 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8777 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8778 INTR_INFO_VALID_MASK
, 0);
8780 * The NMI-triggered VM exit counts as injection:
8781 * clear this one and block further NMIs.
8783 vcpu
->arch
.nmi_pending
= 0;
8784 vmx_set_nmi_mask(vcpu
, true);
8788 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8789 nested_exit_on_intr(vcpu
)) {
8790 if (vmx
->nested
.nested_run_pending
)
8792 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8798 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8801 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8804 if (ktime_to_ns(remaining
) <= 0)
8807 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8808 do_div(value
, 1000000);
8809 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8813 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8814 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8815 * and this function updates it to reflect the changes to the guest state while
8816 * L2 was running (and perhaps made some exits which were handled directly by L0
8817 * without going back to L1), and to reflect the exit reason.
8818 * Note that we do not have to copy here all VMCS fields, just those that
8819 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8820 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8821 * which already writes to vmcs12 directly.
8823 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8824 u32 exit_reason
, u32 exit_intr_info
,
8825 unsigned long exit_qualification
)
8827 /* update guest state fields: */
8828 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8829 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8831 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8832 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8833 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8835 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8836 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8837 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8838 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8839 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8840 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8841 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8842 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8843 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8844 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8845 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8846 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8847 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8848 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8849 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8850 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8851 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8852 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8853 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8854 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8855 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8856 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8857 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8858 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8859 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8860 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8861 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8862 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8863 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8864 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8865 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8866 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8867 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8868 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8869 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8870 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8872 vmcs12
->guest_interruptibility_info
=
8873 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8874 vmcs12
->guest_pending_dbg_exceptions
=
8875 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8876 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8877 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8879 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8881 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8882 if (vmcs12
->vm_exit_controls
&
8883 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8884 vmcs12
->vmx_preemption_timer_value
=
8885 vmx_get_preemption_timer_value(vcpu
);
8886 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8890 * In some cases (usually, nested EPT), L2 is allowed to change its
8891 * own CR3 without exiting. If it has changed it, we must keep it.
8892 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8893 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8895 * Additionally, restore L2's PDPTR to vmcs12.
8898 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8899 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8900 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8901 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8902 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8905 vmcs12
->vm_entry_controls
=
8906 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8907 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8909 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
8910 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8911 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8914 /* TODO: These cannot have changed unless we have MSR bitmaps and
8915 * the relevant bit asks not to trap the change */
8916 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8917 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8918 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8919 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8920 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8921 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8922 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8923 if (vmx_mpx_supported())
8924 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8926 /* update exit information fields: */
8928 vmcs12
->vm_exit_reason
= exit_reason
;
8929 vmcs12
->exit_qualification
= exit_qualification
;
8931 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8932 if ((vmcs12
->vm_exit_intr_info
&
8933 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8934 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8935 vmcs12
->vm_exit_intr_error_code
=
8936 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8937 vmcs12
->idt_vectoring_info_field
= 0;
8938 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8939 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8941 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8942 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8943 * instead of reading the real value. */
8944 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8947 * Transfer the event that L0 or L1 may wanted to inject into
8948 * L2 to IDT_VECTORING_INFO_FIELD.
8950 vmcs12_save_pending_event(vcpu
, vmcs12
);
8954 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8955 * preserved above and would only end up incorrectly in L1.
8957 vcpu
->arch
.nmi_injected
= false;
8958 kvm_clear_exception_queue(vcpu
);
8959 kvm_clear_interrupt_queue(vcpu
);
8963 * A part of what we need to when the nested L2 guest exits and we want to
8964 * run its L1 parent, is to reset L1's guest state to the host state specified
8966 * This function is to be called not only on normal nested exit, but also on
8967 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8968 * Failures During or After Loading Guest State").
8969 * This function should be called when the active VMCS is L1's (vmcs01).
8971 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8972 struct vmcs12
*vmcs12
)
8974 struct kvm_segment seg
;
8976 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8977 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8978 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8979 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8981 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8982 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8984 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8985 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8986 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8988 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8989 * actually changed, because it depends on the current state of
8990 * fpu_active (which may have changed).
8991 * Note that vmx_set_cr0 refers to efer set above.
8993 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8995 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8996 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8997 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8999 update_exception_bitmap(vcpu
);
9000 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
9001 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9004 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9005 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9007 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
9008 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
9010 nested_ept_uninit_mmu_context(vcpu
);
9012 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
9013 kvm_mmu_reset_context(vcpu
);
9016 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
9020 * Trivially support vpid by letting L2s share their parent
9021 * L1's vpid. TODO: move to a more elaborate solution, giving
9022 * each L2 its own vpid and exposing the vpid feature to L1.
9024 vmx_flush_tlb(vcpu
);
9028 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
9029 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
9030 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
9031 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
9032 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
9034 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9035 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
9036 vmcs_write64(GUEST_BNDCFGS
, 0);
9038 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
9039 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
9040 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
9042 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
9043 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
9044 vmcs12
->host_ia32_perf_global_ctrl
);
9046 /* Set L1 segment info according to Intel SDM
9047 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9048 seg
= (struct kvm_segment
) {
9050 .limit
= 0xFFFFFFFF,
9051 .selector
= vmcs12
->host_cs_selector
,
9057 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
9061 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
9062 seg
= (struct kvm_segment
) {
9064 .limit
= 0xFFFFFFFF,
9071 seg
.selector
= vmcs12
->host_ds_selector
;
9072 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
9073 seg
.selector
= vmcs12
->host_es_selector
;
9074 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
9075 seg
.selector
= vmcs12
->host_ss_selector
;
9076 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
9077 seg
.selector
= vmcs12
->host_fs_selector
;
9078 seg
.base
= vmcs12
->host_fs_base
;
9079 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
9080 seg
.selector
= vmcs12
->host_gs_selector
;
9081 seg
.base
= vmcs12
->host_gs_base
;
9082 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
9083 seg
= (struct kvm_segment
) {
9084 .base
= vmcs12
->host_tr_base
,
9086 .selector
= vmcs12
->host_tr_selector
,
9090 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
9092 kvm_set_dr(vcpu
, 7, 0x400);
9093 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
9097 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9098 * and modify vmcs12 to make it see what it would expect to see there if
9099 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9101 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
9103 unsigned long exit_qualification
)
9105 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9106 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9108 /* trying to cancel vmlaunch/vmresume is a bug */
9109 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
9111 leave_guest_mode(vcpu
);
9112 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
9113 exit_qualification
);
9115 vmx_load_vmcs01(vcpu
);
9117 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
9118 && nested_exit_intr_ack_set(vcpu
)) {
9119 int irq
= kvm_cpu_get_interrupt(vcpu
);
9121 vmcs12
->vm_exit_intr_info
= irq
|
9122 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
9125 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
9126 vmcs12
->exit_qualification
,
9127 vmcs12
->idt_vectoring_info_field
,
9128 vmcs12
->vm_exit_intr_info
,
9129 vmcs12
->vm_exit_intr_error_code
,
9132 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
9133 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
9134 vmx_segment_cache_clear(vmx
);
9136 /* if no vmcs02 cache requested, remove the one we used */
9137 if (VMCS02_POOL_SIZE
== 0)
9138 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
9140 load_vmcs12_host_state(vcpu
, vmcs12
);
9142 /* Update TSC_OFFSET if TSC was changed while L2 ran */
9143 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9145 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9148 /* Unpin physical memory we referred to in vmcs02 */
9149 if (vmx
->nested
.apic_access_page
) {
9150 nested_release_page(vmx
->nested
.apic_access_page
);
9151 vmx
->nested
.apic_access_page
= NULL
;
9153 if (vmx
->nested
.virtual_apic_page
) {
9154 nested_release_page(vmx
->nested
.virtual_apic_page
);
9155 vmx
->nested
.virtual_apic_page
= NULL
;
9159 * We are now running in L2, mmu_notifier will force to reload the
9160 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9162 kvm_vcpu_reload_apic_access_page(vcpu
);
9165 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9166 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9167 * success or failure flag accordingly.
9169 if (unlikely(vmx
->fail
)) {
9171 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
9173 nested_vmx_succeed(vcpu
);
9174 if (enable_shadow_vmcs
)
9175 vmx
->nested
.sync_shadow_vmcs
= true;
9177 /* in case we halted in L2 */
9178 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
9182 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9184 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
9186 if (is_guest_mode(vcpu
))
9187 nested_vmx_vmexit(vcpu
, -1, 0, 0);
9188 free_nested(to_vmx(vcpu
));
9192 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9193 * 23.7 "VM-entry failures during or after loading guest state" (this also
9194 * lists the acceptable exit-reason and exit-qualification parameters).
9195 * It should only be called before L2 actually succeeded to run, and when
9196 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9198 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
9199 struct vmcs12
*vmcs12
,
9200 u32 reason
, unsigned long qualification
)
9202 load_vmcs12_host_state(vcpu
, vmcs12
);
9203 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
9204 vmcs12
->exit_qualification
= qualification
;
9205 nested_vmx_succeed(vcpu
);
9206 if (enable_shadow_vmcs
)
9207 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
9210 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
9211 struct x86_instruction_info
*info
,
9212 enum x86_intercept_stage stage
)
9214 return X86EMUL_CONTINUE
;
9217 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
9220 shrink_ple_window(vcpu
);
9223 static struct kvm_x86_ops vmx_x86_ops
= {
9224 .cpu_has_kvm_support
= cpu_has_kvm_support
,
9225 .disabled_by_bios
= vmx_disabled_by_bios
,
9226 .hardware_setup
= hardware_setup
,
9227 .hardware_unsetup
= hardware_unsetup
,
9228 .check_processor_compatibility
= vmx_check_processor_compat
,
9229 .hardware_enable
= hardware_enable
,
9230 .hardware_disable
= hardware_disable
,
9231 .cpu_has_accelerated_tpr
= report_flexpriority
,
9233 .vcpu_create
= vmx_create_vcpu
,
9234 .vcpu_free
= vmx_free_vcpu
,
9235 .vcpu_reset
= vmx_vcpu_reset
,
9237 .prepare_guest_switch
= vmx_save_host_state
,
9238 .vcpu_load
= vmx_vcpu_load
,
9239 .vcpu_put
= vmx_vcpu_put
,
9241 .update_db_bp_intercept
= update_exception_bitmap
,
9242 .get_msr
= vmx_get_msr
,
9243 .set_msr
= vmx_set_msr
,
9244 .get_segment_base
= vmx_get_segment_base
,
9245 .get_segment
= vmx_get_segment
,
9246 .set_segment
= vmx_set_segment
,
9247 .get_cpl
= vmx_get_cpl
,
9248 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
9249 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
9250 .decache_cr3
= vmx_decache_cr3
,
9251 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
9252 .set_cr0
= vmx_set_cr0
,
9253 .set_cr3
= vmx_set_cr3
,
9254 .set_cr4
= vmx_set_cr4
,
9255 .set_efer
= vmx_set_efer
,
9256 .get_idt
= vmx_get_idt
,
9257 .set_idt
= vmx_set_idt
,
9258 .get_gdt
= vmx_get_gdt
,
9259 .set_gdt
= vmx_set_gdt
,
9260 .get_dr6
= vmx_get_dr6
,
9261 .set_dr6
= vmx_set_dr6
,
9262 .set_dr7
= vmx_set_dr7
,
9263 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
9264 .cache_reg
= vmx_cache_reg
,
9265 .get_rflags
= vmx_get_rflags
,
9266 .set_rflags
= vmx_set_rflags
,
9267 .fpu_deactivate
= vmx_fpu_deactivate
,
9269 .tlb_flush
= vmx_flush_tlb
,
9271 .run
= vmx_vcpu_run
,
9272 .handle_exit
= vmx_handle_exit
,
9273 .skip_emulated_instruction
= skip_emulated_instruction
,
9274 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
9275 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
9276 .patch_hypercall
= vmx_patch_hypercall
,
9277 .set_irq
= vmx_inject_irq
,
9278 .set_nmi
= vmx_inject_nmi
,
9279 .queue_exception
= vmx_queue_exception
,
9280 .cancel_injection
= vmx_cancel_injection
,
9281 .interrupt_allowed
= vmx_interrupt_allowed
,
9282 .nmi_allowed
= vmx_nmi_allowed
,
9283 .get_nmi_mask
= vmx_get_nmi_mask
,
9284 .set_nmi_mask
= vmx_set_nmi_mask
,
9285 .enable_nmi_window
= enable_nmi_window
,
9286 .enable_irq_window
= enable_irq_window
,
9287 .update_cr8_intercept
= update_cr8_intercept
,
9288 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
9289 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
9290 .vm_has_apicv
= vmx_vm_has_apicv
,
9291 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
9292 .hwapic_irr_update
= vmx_hwapic_irr_update
,
9293 .hwapic_isr_update
= vmx_hwapic_isr_update
,
9294 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
9295 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
9297 .set_tss_addr
= vmx_set_tss_addr
,
9298 .get_tdp_level
= get_ept_level
,
9299 .get_mt_mask
= vmx_get_mt_mask
,
9301 .get_exit_info
= vmx_get_exit_info
,
9303 .get_lpage_level
= vmx_get_lpage_level
,
9305 .cpuid_update
= vmx_cpuid_update
,
9307 .rdtscp_supported
= vmx_rdtscp_supported
,
9308 .invpcid_supported
= vmx_invpcid_supported
,
9310 .set_supported_cpuid
= vmx_set_supported_cpuid
,
9312 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
9314 .set_tsc_khz
= vmx_set_tsc_khz
,
9315 .read_tsc_offset
= vmx_read_tsc_offset
,
9316 .write_tsc_offset
= vmx_write_tsc_offset
,
9317 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
9318 .compute_tsc_offset
= vmx_compute_tsc_offset
,
9319 .read_l1_tsc
= vmx_read_l1_tsc
,
9321 .set_tdp_cr3
= vmx_set_cr3
,
9323 .check_intercept
= vmx_check_intercept
,
9324 .handle_external_intr
= vmx_handle_external_intr
,
9325 .mpx_supported
= vmx_mpx_supported
,
9327 .check_nested_events
= vmx_check_nested_events
,
9329 .sched_in
= vmx_sched_in
,
9332 static int __init
vmx_init(void)
9334 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
9335 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
9340 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
9341 crash_vmclear_local_loaded_vmcss
);
9347 static void __exit
vmx_exit(void)
9350 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
9357 module_init(vmx_init
)
9358 module_exit(vmx_exit
)