2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
135 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
136 module_param(ple_gap
, int, S_IRUGO
);
138 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
139 module_param(ple_window
, int, S_IRUGO
);
141 /* Default doubles per-vcpu window every exit. */
142 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
143 module_param(ple_window_grow
, int, S_IRUGO
);
145 /* Default resets per-vcpu window every exit to ple_window. */
146 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
147 module_param(ple_window_shrink
, int, S_IRUGO
);
149 /* Default is to compute the maximum so we can never overflow. */
150 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
151 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
152 module_param(ple_window_max
, int, S_IRUGO
);
154 extern const ulong vmx_return
;
156 #define NR_AUTOLOAD_MSRS 8
157 #define VMCS02_POOL_SIZE 1
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
174 struct list_head loaded_vmcss_on_cpu_link
;
177 struct shared_msr_entry
{
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
196 typedef u64 natural_width
;
197 struct __packed vmcs12
{
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
204 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding
[7]; /* room for future expansion */
210 u64 vm_exit_msr_store_addr
;
211 u64 vm_exit_msr_load_addr
;
212 u64 vm_entry_msr_load_addr
;
214 u64 virtual_apic_page_addr
;
215 u64 apic_access_addr
;
217 u64 guest_physical_address
;
218 u64 vmcs_link_pointer
;
219 u64 guest_ia32_debugctl
;
222 u64 guest_ia32_perf_global_ctrl
;
230 u64 host_ia32_perf_global_ctrl
;
231 u64 padding64
[8]; /* room for future expansion */
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
238 natural_width cr0_guest_host_mask
;
239 natural_width cr4_guest_host_mask
;
240 natural_width cr0_read_shadow
;
241 natural_width cr4_read_shadow
;
242 natural_width cr3_target_value0
;
243 natural_width cr3_target_value1
;
244 natural_width cr3_target_value2
;
245 natural_width cr3_target_value3
;
246 natural_width exit_qualification
;
247 natural_width guest_linear_address
;
248 natural_width guest_cr0
;
249 natural_width guest_cr3
;
250 natural_width guest_cr4
;
251 natural_width guest_es_base
;
252 natural_width guest_cs_base
;
253 natural_width guest_ss_base
;
254 natural_width guest_ds_base
;
255 natural_width guest_fs_base
;
256 natural_width guest_gs_base
;
257 natural_width guest_ldtr_base
;
258 natural_width guest_tr_base
;
259 natural_width guest_gdtr_base
;
260 natural_width guest_idtr_base
;
261 natural_width guest_dr7
;
262 natural_width guest_rsp
;
263 natural_width guest_rip
;
264 natural_width guest_rflags
;
265 natural_width guest_pending_dbg_exceptions
;
266 natural_width guest_sysenter_esp
;
267 natural_width guest_sysenter_eip
;
268 natural_width host_cr0
;
269 natural_width host_cr3
;
270 natural_width host_cr4
;
271 natural_width host_fs_base
;
272 natural_width host_gs_base
;
273 natural_width host_tr_base
;
274 natural_width host_gdtr_base
;
275 natural_width host_idtr_base
;
276 natural_width host_ia32_sysenter_esp
;
277 natural_width host_ia32_sysenter_eip
;
278 natural_width host_rsp
;
279 natural_width host_rip
;
280 natural_width paddingl
[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control
;
282 u32 cpu_based_vm_exec_control
;
283 u32 exception_bitmap
;
284 u32 page_fault_error_code_mask
;
285 u32 page_fault_error_code_match
;
286 u32 cr3_target_count
;
287 u32 vm_exit_controls
;
288 u32 vm_exit_msr_store_count
;
289 u32 vm_exit_msr_load_count
;
290 u32 vm_entry_controls
;
291 u32 vm_entry_msr_load_count
;
292 u32 vm_entry_intr_info_field
;
293 u32 vm_entry_exception_error_code
;
294 u32 vm_entry_instruction_len
;
296 u32 secondary_vm_exec_control
;
297 u32 vm_instruction_error
;
299 u32 vm_exit_intr_info
;
300 u32 vm_exit_intr_error_code
;
301 u32 idt_vectoring_info_field
;
302 u32 idt_vectoring_error_code
;
303 u32 vm_exit_instruction_len
;
304 u32 vmx_instruction_info
;
311 u32 guest_ldtr_limit
;
313 u32 guest_gdtr_limit
;
314 u32 guest_idtr_limit
;
315 u32 guest_es_ar_bytes
;
316 u32 guest_cs_ar_bytes
;
317 u32 guest_ss_ar_bytes
;
318 u32 guest_ds_ar_bytes
;
319 u32 guest_fs_ar_bytes
;
320 u32 guest_gs_ar_bytes
;
321 u32 guest_ldtr_ar_bytes
;
322 u32 guest_tr_ar_bytes
;
323 u32 guest_interruptibility_info
;
324 u32 guest_activity_state
;
325 u32 guest_sysenter_cs
;
326 u32 host_ia32_sysenter_cs
;
327 u32 vmx_preemption_timer_value
;
328 u32 padding32
[7]; /* room for future expansion */
329 u16 virtual_processor_id
;
330 u16 guest_es_selector
;
331 u16 guest_cs_selector
;
332 u16 guest_ss_selector
;
333 u16 guest_ds_selector
;
334 u16 guest_fs_selector
;
335 u16 guest_gs_selector
;
336 u16 guest_ldtr_selector
;
337 u16 guest_tr_selector
;
338 u16 host_es_selector
;
339 u16 host_cs_selector
;
340 u16 host_ss_selector
;
341 u16 host_ds_selector
;
342 u16 host_fs_selector
;
343 u16 host_gs_selector
;
344 u16 host_tr_selector
;
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
352 #define VMCS12_REVISION 0x11e57ed0
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
359 #define VMCS12_SIZE 0x1000
361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
363 struct list_head list
;
365 struct loaded_vmcs vmcs02
;
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
373 /* Has the level1 guest done vmxon? */
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
379 /* The host-usable pointer to the above */
380 struct page
*current_vmcs12_page
;
381 struct vmcs12
*current_vmcs12
;
382 struct vmcs
*current_shadow_vmcs
;
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
387 bool sync_shadow_vmcs
;
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool
;
392 u64 vmcs01_tsc_offset
;
393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending
;
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
399 struct page
*apic_access_page
;
400 struct page
*virtual_apic_page
;
401 u64 msr_ia32_feature_control
;
403 struct hrtimer preemption_timer
;
404 bool preemption_timer_expired
;
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
410 #define POSTED_INTR_ON 0
411 /* Posted-Interrupt Descriptor */
413 u32 pir
[8]; /* Posted interrupt requested */
414 u32 control
; /* bit 0 of control is outstanding notification bit */
418 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
420 return test_and_set_bit(POSTED_INTR_ON
,
421 (unsigned long *)&pi_desc
->control
);
424 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
426 return test_and_clear_bit(POSTED_INTR_ON
,
427 (unsigned long *)&pi_desc
->control
);
430 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
432 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
436 struct kvm_vcpu vcpu
;
437 unsigned long host_rsp
;
439 bool nmi_known_unmasked
;
441 u32 idt_vectoring_info
;
443 struct shared_msr_entry
*guest_msrs
;
446 unsigned long host_idt_base
;
448 u64 msr_host_kernel_gs_base
;
449 u64 msr_guest_kernel_gs_base
;
451 u32 vm_entry_controls_shadow
;
452 u32 vm_exit_controls_shadow
;
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
458 struct loaded_vmcs vmcs01
;
459 struct loaded_vmcs
*loaded_vmcs
;
460 bool __launched
; /* temporary, used in vmx_vcpu_run */
461 struct msr_autoload
{
463 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
464 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
468 u16 fs_sel
, gs_sel
, ldt_sel
;
472 int gs_ldt_reload_needed
;
473 int fs_reload_needed
;
474 u64 msr_host_bndcfgs
;
475 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
480 struct kvm_segment segs
[8];
483 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
484 struct kvm_save_segment
{
492 bool emulation_required
;
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked
;
497 s64 vnmi_blocked_time
;
502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc
;
505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested
;
508 /* Dynamic PLE window. */
510 bool ple_window_dirty
;
513 enum segment_cache_field
{
522 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
524 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
527 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
533 static unsigned long shadow_read_only_fields
[] = {
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
548 VM_EXIT_INSTRUCTION_LEN
,
549 IDT_VECTORING_INFO_FIELD
,
550 IDT_VECTORING_ERROR_CODE
,
551 VM_EXIT_INTR_ERROR_CODE
,
553 GUEST_LINEAR_ADDRESS
,
554 GUEST_PHYSICAL_ADDRESS
556 static int max_shadow_read_only_fields
=
557 ARRAY_SIZE(shadow_read_only_fields
);
559 static unsigned long shadow_read_write_fields
[] = {
566 GUEST_INTERRUPTIBILITY_INFO
,
579 CPU_BASED_VM_EXEC_CONTROL
,
580 VM_ENTRY_EXCEPTION_ERROR_CODE
,
581 VM_ENTRY_INTR_INFO_FIELD
,
582 VM_ENTRY_INSTRUCTION_LEN
,
583 VM_ENTRY_EXCEPTION_ERROR_CODE
,
589 static int max_shadow_read_write_fields
=
590 ARRAY_SIZE(shadow_read_write_fields
);
592 static const unsigned short vmcs_field_to_offset_table
[] = {
593 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
594 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
595 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
596 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
597 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
598 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
599 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
600 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
601 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
602 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
603 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
604 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
605 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
606 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
607 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
608 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
609 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
610 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
611 FIELD64(MSR_BITMAP
, msr_bitmap
),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
615 FIELD64(TSC_OFFSET
, tsc_offset
),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
617 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
618 FIELD64(EPT_POINTER
, ept_pointer
),
619 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
620 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
621 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
622 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
623 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
625 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
626 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
627 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
628 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
629 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
630 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
631 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
635 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
638 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
639 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
640 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
642 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
647 FIELD(TPR_THRESHOLD
, tpr_threshold
),
648 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
649 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
650 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
651 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
652 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
653 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
654 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
655 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
656 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
657 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
658 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
659 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
660 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
661 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
662 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
663 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
664 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
665 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
666 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
667 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
668 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
669 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
670 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
671 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
672 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
673 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
674 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
676 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
677 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
678 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
679 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
680 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
681 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
682 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
683 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
684 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
685 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
686 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
687 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
688 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
689 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
690 FIELD(GUEST_CR0
, guest_cr0
),
691 FIELD(GUEST_CR3
, guest_cr3
),
692 FIELD(GUEST_CR4
, guest_cr4
),
693 FIELD(GUEST_ES_BASE
, guest_es_base
),
694 FIELD(GUEST_CS_BASE
, guest_cs_base
),
695 FIELD(GUEST_SS_BASE
, guest_ss_base
),
696 FIELD(GUEST_DS_BASE
, guest_ds_base
),
697 FIELD(GUEST_FS_BASE
, guest_fs_base
),
698 FIELD(GUEST_GS_BASE
, guest_gs_base
),
699 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
700 FIELD(GUEST_TR_BASE
, guest_tr_base
),
701 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
702 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
703 FIELD(GUEST_DR7
, guest_dr7
),
704 FIELD(GUEST_RSP
, guest_rsp
),
705 FIELD(GUEST_RIP
, guest_rip
),
706 FIELD(GUEST_RFLAGS
, guest_rflags
),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
708 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
709 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
710 FIELD(HOST_CR0
, host_cr0
),
711 FIELD(HOST_CR3
, host_cr3
),
712 FIELD(HOST_CR4
, host_cr4
),
713 FIELD(HOST_FS_BASE
, host_fs_base
),
714 FIELD(HOST_GS_BASE
, host_gs_base
),
715 FIELD(HOST_TR_BASE
, host_tr_base
),
716 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
717 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
718 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
719 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
720 FIELD(HOST_RSP
, host_rsp
),
721 FIELD(HOST_RIP
, host_rip
),
723 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
725 static inline short vmcs_field_to_offset(unsigned long field
)
727 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
729 return vmcs_field_to_offset_table
[field
];
732 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
734 return to_vmx(vcpu
)->nested
.current_vmcs12
;
737 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
739 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
740 if (is_error_page(page
))
746 static void nested_release_page(struct page
*page
)
748 kvm_release_page_dirty(page
);
751 static void nested_release_page_clean(struct page
*page
)
753 kvm_release_page_clean(page
);
756 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
757 static u64
construct_eptp(unsigned long root_hpa
);
758 static void kvm_cpu_vmxon(u64 addr
);
759 static void kvm_cpu_vmxoff(void);
760 static bool vmx_mpx_supported(void);
761 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
762 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
763 struct kvm_segment
*var
, int seg
);
764 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
765 struct kvm_segment
*var
, int seg
);
766 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
767 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
768 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
769 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
770 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
771 static int alloc_identity_pagetable(struct kvm
*kvm
);
773 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
774 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
776 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
777 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
779 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
780 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
782 static unsigned long *vmx_io_bitmap_a
;
783 static unsigned long *vmx_io_bitmap_b
;
784 static unsigned long *vmx_msr_bitmap_legacy
;
785 static unsigned long *vmx_msr_bitmap_longmode
;
786 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
787 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
788 static unsigned long *vmx_vmread_bitmap
;
789 static unsigned long *vmx_vmwrite_bitmap
;
791 static bool cpu_has_load_ia32_efer
;
792 static bool cpu_has_load_perf_global_ctrl
;
794 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
795 static DEFINE_SPINLOCK(vmx_vpid_lock
);
797 static struct vmcs_config
{
801 u32 pin_based_exec_ctrl
;
802 u32 cpu_based_exec_ctrl
;
803 u32 cpu_based_2nd_exec_ctrl
;
808 static struct vmx_capability
{
813 #define VMX_SEGMENT_FIELD(seg) \
814 [VCPU_SREG_##seg] = { \
815 .selector = GUEST_##seg##_SELECTOR, \
816 .base = GUEST_##seg##_BASE, \
817 .limit = GUEST_##seg##_LIMIT, \
818 .ar_bytes = GUEST_##seg##_AR_BYTES, \
821 static const struct kvm_vmx_segment_field
{
826 } kvm_vmx_segment_fields
[] = {
827 VMX_SEGMENT_FIELD(CS
),
828 VMX_SEGMENT_FIELD(DS
),
829 VMX_SEGMENT_FIELD(ES
),
830 VMX_SEGMENT_FIELD(FS
),
831 VMX_SEGMENT_FIELD(GS
),
832 VMX_SEGMENT_FIELD(SS
),
833 VMX_SEGMENT_FIELD(TR
),
834 VMX_SEGMENT_FIELD(LDTR
),
837 static u64 host_efer
;
839 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
842 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
843 * away by decrementing the array size.
845 static const u32 vmx_msr_index
[] = {
847 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
849 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
852 static inline bool is_page_fault(u32 intr_info
)
854 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
855 INTR_INFO_VALID_MASK
)) ==
856 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
859 static inline bool is_no_device(u32 intr_info
)
861 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
862 INTR_INFO_VALID_MASK
)) ==
863 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
866 static inline bool is_invalid_opcode(u32 intr_info
)
868 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
869 INTR_INFO_VALID_MASK
)) ==
870 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
873 static inline bool is_external_interrupt(u32 intr_info
)
875 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
876 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
879 static inline bool is_machine_check(u32 intr_info
)
881 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
882 INTR_INFO_VALID_MASK
)) ==
883 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
886 static inline bool cpu_has_vmx_msr_bitmap(void)
888 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
891 static inline bool cpu_has_vmx_tpr_shadow(void)
893 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
896 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
898 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
901 static inline bool cpu_has_secondary_exec_ctrls(void)
903 return vmcs_config
.cpu_based_exec_ctrl
&
904 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
907 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
909 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
910 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
913 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
915 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
916 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
919 static inline bool cpu_has_vmx_apic_register_virt(void)
921 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
922 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
925 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
927 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
928 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
931 static inline bool cpu_has_vmx_posted_intr(void)
933 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
936 static inline bool cpu_has_vmx_apicv(void)
938 return cpu_has_vmx_apic_register_virt() &&
939 cpu_has_vmx_virtual_intr_delivery() &&
940 cpu_has_vmx_posted_intr();
943 static inline bool cpu_has_vmx_flexpriority(void)
945 return cpu_has_vmx_tpr_shadow() &&
946 cpu_has_vmx_virtualize_apic_accesses();
949 static inline bool cpu_has_vmx_ept_execute_only(void)
951 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
954 static inline bool cpu_has_vmx_eptp_uncacheable(void)
956 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
959 static inline bool cpu_has_vmx_eptp_writeback(void)
961 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
964 static inline bool cpu_has_vmx_ept_2m_page(void)
966 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
969 static inline bool cpu_has_vmx_ept_1g_page(void)
971 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
974 static inline bool cpu_has_vmx_ept_4levels(void)
976 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
979 static inline bool cpu_has_vmx_ept_ad_bits(void)
981 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
984 static inline bool cpu_has_vmx_invept_context(void)
986 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
989 static inline bool cpu_has_vmx_invept_global(void)
991 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
994 static inline bool cpu_has_vmx_invvpid_single(void)
996 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
999 static inline bool cpu_has_vmx_invvpid_global(void)
1001 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1004 static inline bool cpu_has_vmx_ept(void)
1006 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1007 SECONDARY_EXEC_ENABLE_EPT
;
1010 static inline bool cpu_has_vmx_unrestricted_guest(void)
1012 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1013 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1016 static inline bool cpu_has_vmx_ple(void)
1018 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1019 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1022 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1024 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1027 static inline bool cpu_has_vmx_vpid(void)
1029 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1030 SECONDARY_EXEC_ENABLE_VPID
;
1033 static inline bool cpu_has_vmx_rdtscp(void)
1035 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1036 SECONDARY_EXEC_RDTSCP
;
1039 static inline bool cpu_has_vmx_invpcid(void)
1041 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1042 SECONDARY_EXEC_ENABLE_INVPCID
;
1045 static inline bool cpu_has_virtual_nmis(void)
1047 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1050 static inline bool cpu_has_vmx_wbinvd_exit(void)
1052 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1053 SECONDARY_EXEC_WBINVD_EXITING
;
1056 static inline bool cpu_has_vmx_shadow_vmcs(void)
1059 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1060 /* check if the cpu supports writing r/o exit information fields */
1061 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1064 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1065 SECONDARY_EXEC_SHADOW_VMCS
;
1068 static inline bool report_flexpriority(void)
1070 return flexpriority_enabled
;
1073 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1075 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1078 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1080 return (vmcs12
->cpu_based_vm_exec_control
&
1081 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1082 (vmcs12
->secondary_vm_exec_control
& bit
);
1085 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1087 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1090 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1092 return vmcs12
->pin_based_vm_exec_control
&
1093 PIN_BASED_VMX_PREEMPTION_TIMER
;
1096 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1098 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1101 static inline bool is_exception(u32 intr_info
)
1103 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1104 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1107 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1109 unsigned long exit_qualification
);
1110 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1111 struct vmcs12
*vmcs12
,
1112 u32 reason
, unsigned long qualification
);
1114 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1118 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1119 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1124 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1130 } operand
= { vpid
, 0, gva
};
1132 asm volatile (__ex(ASM_VMX_INVVPID
)
1133 /* CF==1 or ZF==1 --> rc = -1 */
1134 "; ja 1f ; ud2 ; 1:"
1135 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1138 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1142 } operand
= {eptp
, gpa
};
1144 asm volatile (__ex(ASM_VMX_INVEPT
)
1145 /* CF==1 or ZF==1 --> rc = -1 */
1146 "; ja 1f ; ud2 ; 1:\n"
1147 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1150 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1154 i
= __find_msr_index(vmx
, msr
);
1156 return &vmx
->guest_msrs
[i
];
1160 static void vmcs_clear(struct vmcs
*vmcs
)
1162 u64 phys_addr
= __pa(vmcs
);
1165 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1166 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1169 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1173 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1175 vmcs_clear(loaded_vmcs
->vmcs
);
1176 loaded_vmcs
->cpu
= -1;
1177 loaded_vmcs
->launched
= 0;
1180 static void vmcs_load(struct vmcs
*vmcs
)
1182 u64 phys_addr
= __pa(vmcs
);
1185 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1186 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1189 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1195 * This bitmap is used to indicate whether the vmclear
1196 * operation is enabled on all cpus. All disabled by
1199 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1201 static inline void crash_enable_local_vmclear(int cpu
)
1203 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1206 static inline void crash_disable_local_vmclear(int cpu
)
1208 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1211 static inline int crash_local_vmclear_enabled(int cpu
)
1213 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1216 static void crash_vmclear_local_loaded_vmcss(void)
1218 int cpu
= raw_smp_processor_id();
1219 struct loaded_vmcs
*v
;
1221 if (!crash_local_vmclear_enabled(cpu
))
1224 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1225 loaded_vmcss_on_cpu_link
)
1226 vmcs_clear(v
->vmcs
);
1229 static inline void crash_enable_local_vmclear(int cpu
) { }
1230 static inline void crash_disable_local_vmclear(int cpu
) { }
1231 #endif /* CONFIG_KEXEC */
1233 static void __loaded_vmcs_clear(void *arg
)
1235 struct loaded_vmcs
*loaded_vmcs
= arg
;
1236 int cpu
= raw_smp_processor_id();
1238 if (loaded_vmcs
->cpu
!= cpu
)
1239 return; /* vcpu migration can race with cpu offline */
1240 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1241 per_cpu(current_vmcs
, cpu
) = NULL
;
1242 crash_disable_local_vmclear(cpu
);
1243 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1246 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1247 * is before setting loaded_vmcs->vcpu to -1 which is done in
1248 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1249 * then adds the vmcs into percpu list before it is deleted.
1253 loaded_vmcs_init(loaded_vmcs
);
1254 crash_enable_local_vmclear(cpu
);
1257 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1259 int cpu
= loaded_vmcs
->cpu
;
1262 smp_call_function_single(cpu
,
1263 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1266 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1271 if (cpu_has_vmx_invvpid_single())
1272 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1275 static inline void vpid_sync_vcpu_global(void)
1277 if (cpu_has_vmx_invvpid_global())
1278 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1281 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1283 if (cpu_has_vmx_invvpid_single())
1284 vpid_sync_vcpu_single(vmx
);
1286 vpid_sync_vcpu_global();
1289 static inline void ept_sync_global(void)
1291 if (cpu_has_vmx_invept_global())
1292 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1295 static inline void ept_sync_context(u64 eptp
)
1298 if (cpu_has_vmx_invept_context())
1299 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1305 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1307 unsigned long value
;
1309 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1310 : "=a"(value
) : "d"(field
) : "cc");
1314 static __always_inline u16
vmcs_read16(unsigned long field
)
1316 return vmcs_readl(field
);
1319 static __always_inline u32
vmcs_read32(unsigned long field
)
1321 return vmcs_readl(field
);
1324 static __always_inline u64
vmcs_read64(unsigned long field
)
1326 #ifdef CONFIG_X86_64
1327 return vmcs_readl(field
);
1329 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1333 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1335 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1336 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1340 static void vmcs_writel(unsigned long field
, unsigned long value
)
1344 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1345 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1346 if (unlikely(error
))
1347 vmwrite_error(field
, value
);
1350 static void vmcs_write16(unsigned long field
, u16 value
)
1352 vmcs_writel(field
, value
);
1355 static void vmcs_write32(unsigned long field
, u32 value
)
1357 vmcs_writel(field
, value
);
1360 static void vmcs_write64(unsigned long field
, u64 value
)
1362 vmcs_writel(field
, value
);
1363 #ifndef CONFIG_X86_64
1365 vmcs_writel(field
+1, value
>> 32);
1369 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1371 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1374 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1376 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1379 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1381 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1382 vmx
->vm_entry_controls_shadow
= val
;
1385 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1387 if (vmx
->vm_entry_controls_shadow
!= val
)
1388 vm_entry_controls_init(vmx
, val
);
1391 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1393 return vmx
->vm_entry_controls_shadow
;
1397 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1399 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1402 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1404 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1407 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1409 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1410 vmx
->vm_exit_controls_shadow
= val
;
1413 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1415 if (vmx
->vm_exit_controls_shadow
!= val
)
1416 vm_exit_controls_init(vmx
, val
);
1419 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1421 return vmx
->vm_exit_controls_shadow
;
1425 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1427 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1430 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1432 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1435 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1437 vmx
->segment_cache
.bitmask
= 0;
1440 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1444 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1446 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1447 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1448 vmx
->segment_cache
.bitmask
= 0;
1450 ret
= vmx
->segment_cache
.bitmask
& mask
;
1451 vmx
->segment_cache
.bitmask
|= mask
;
1455 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1457 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1459 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1460 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1464 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1466 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1468 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1469 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1473 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1475 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1477 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1478 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1482 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1484 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1486 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1487 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1491 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1495 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1496 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1497 if ((vcpu
->guest_debug
&
1498 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1499 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1500 eb
|= 1u << BP_VECTOR
;
1501 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1504 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1505 if (vcpu
->fpu_active
)
1506 eb
&= ~(1u << NM_VECTOR
);
1508 /* When we are running a nested L2 guest and L1 specified for it a
1509 * certain exception bitmap, we must trap the same exceptions and pass
1510 * them to L1. When running L2, we will only handle the exceptions
1511 * specified above if L1 did not want them.
1513 if (is_guest_mode(vcpu
))
1514 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1516 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1519 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1520 unsigned long entry
, unsigned long exit
)
1522 vm_entry_controls_clearbit(vmx
, entry
);
1523 vm_exit_controls_clearbit(vmx
, exit
);
1526 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1529 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1533 if (cpu_has_load_ia32_efer
) {
1534 clear_atomic_switch_msr_special(vmx
,
1535 VM_ENTRY_LOAD_IA32_EFER
,
1536 VM_EXIT_LOAD_IA32_EFER
);
1540 case MSR_CORE_PERF_GLOBAL_CTRL
:
1541 if (cpu_has_load_perf_global_ctrl
) {
1542 clear_atomic_switch_msr_special(vmx
,
1543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1544 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1550 for (i
= 0; i
< m
->nr
; ++i
)
1551 if (m
->guest
[i
].index
== msr
)
1557 m
->guest
[i
] = m
->guest
[m
->nr
];
1558 m
->host
[i
] = m
->host
[m
->nr
];
1559 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1560 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1563 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1564 unsigned long entry
, unsigned long exit
,
1565 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1566 u64 guest_val
, u64 host_val
)
1568 vmcs_write64(guest_val_vmcs
, guest_val
);
1569 vmcs_write64(host_val_vmcs
, host_val
);
1570 vm_entry_controls_setbit(vmx
, entry
);
1571 vm_exit_controls_setbit(vmx
, exit
);
1574 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1575 u64 guest_val
, u64 host_val
)
1578 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1582 if (cpu_has_load_ia32_efer
) {
1583 add_atomic_switch_msr_special(vmx
,
1584 VM_ENTRY_LOAD_IA32_EFER
,
1585 VM_EXIT_LOAD_IA32_EFER
,
1588 guest_val
, host_val
);
1592 case MSR_CORE_PERF_GLOBAL_CTRL
:
1593 if (cpu_has_load_perf_global_ctrl
) {
1594 add_atomic_switch_msr_special(vmx
,
1595 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1596 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1597 GUEST_IA32_PERF_GLOBAL_CTRL
,
1598 HOST_IA32_PERF_GLOBAL_CTRL
,
1599 guest_val
, host_val
);
1605 for (i
= 0; i
< m
->nr
; ++i
)
1606 if (m
->guest
[i
].index
== msr
)
1609 if (i
== NR_AUTOLOAD_MSRS
) {
1610 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1611 "Can't add msr %x\n", msr
);
1613 } else if (i
== m
->nr
) {
1615 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1616 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1619 m
->guest
[i
].index
= msr
;
1620 m
->guest
[i
].value
= guest_val
;
1621 m
->host
[i
].index
= msr
;
1622 m
->host
[i
].value
= host_val
;
1625 static void reload_tss(void)
1628 * VT restores TR but not its size. Useless.
1630 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1631 struct desc_struct
*descs
;
1633 descs
= (void *)gdt
->address
;
1634 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1638 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1643 guest_efer
= vmx
->vcpu
.arch
.efer
;
1646 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1649 ignore_bits
= EFER_NX
| EFER_SCE
;
1650 #ifdef CONFIG_X86_64
1651 ignore_bits
|= EFER_LMA
| EFER_LME
;
1652 /* SCE is meaningful only in long mode on Intel */
1653 if (guest_efer
& EFER_LMA
)
1654 ignore_bits
&= ~(u64
)EFER_SCE
;
1656 guest_efer
&= ~ignore_bits
;
1657 guest_efer
|= host_efer
& ignore_bits
;
1658 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1659 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1661 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1662 /* On ept, can't emulate nx, and must switch nx atomically */
1663 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1664 guest_efer
= vmx
->vcpu
.arch
.efer
;
1665 if (!(guest_efer
& EFER_LMA
))
1666 guest_efer
&= ~EFER_LME
;
1667 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1674 static unsigned long segment_base(u16 selector
)
1676 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1677 struct desc_struct
*d
;
1678 unsigned long table_base
;
1681 if (!(selector
& ~3))
1684 table_base
= gdt
->address
;
1686 if (selector
& 4) { /* from ldt */
1687 u16 ldt_selector
= kvm_read_ldt();
1689 if (!(ldt_selector
& ~3))
1692 table_base
= segment_base(ldt_selector
);
1694 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1695 v
= get_desc_base(d
);
1696 #ifdef CONFIG_X86_64
1697 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1698 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1703 static inline unsigned long kvm_read_tr_base(void)
1706 asm("str %0" : "=g"(tr
));
1707 return segment_base(tr
);
1710 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1712 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1715 if (vmx
->host_state
.loaded
)
1718 vmx
->host_state
.loaded
= 1;
1720 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1721 * allow segment selectors with cpl > 0 or ti == 1.
1723 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1724 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1725 savesegment(fs
, vmx
->host_state
.fs_sel
);
1726 if (!(vmx
->host_state
.fs_sel
& 7)) {
1727 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1728 vmx
->host_state
.fs_reload_needed
= 0;
1730 vmcs_write16(HOST_FS_SELECTOR
, 0);
1731 vmx
->host_state
.fs_reload_needed
= 1;
1733 savesegment(gs
, vmx
->host_state
.gs_sel
);
1734 if (!(vmx
->host_state
.gs_sel
& 7))
1735 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1737 vmcs_write16(HOST_GS_SELECTOR
, 0);
1738 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1741 #ifdef CONFIG_X86_64
1742 savesegment(ds
, vmx
->host_state
.ds_sel
);
1743 savesegment(es
, vmx
->host_state
.es_sel
);
1746 #ifdef CONFIG_X86_64
1747 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1748 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1750 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1751 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1754 #ifdef CONFIG_X86_64
1755 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1756 if (is_long_mode(&vmx
->vcpu
))
1757 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1759 if (boot_cpu_has(X86_FEATURE_MPX
))
1760 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1761 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1762 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1763 vmx
->guest_msrs
[i
].data
,
1764 vmx
->guest_msrs
[i
].mask
);
1767 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1769 if (!vmx
->host_state
.loaded
)
1772 ++vmx
->vcpu
.stat
.host_state_reload
;
1773 vmx
->host_state
.loaded
= 0;
1774 #ifdef CONFIG_X86_64
1775 if (is_long_mode(&vmx
->vcpu
))
1776 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1778 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1779 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1780 #ifdef CONFIG_X86_64
1781 load_gs_index(vmx
->host_state
.gs_sel
);
1783 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1786 if (vmx
->host_state
.fs_reload_needed
)
1787 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1788 #ifdef CONFIG_X86_64
1789 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1790 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1791 loadsegment(es
, vmx
->host_state
.es_sel
);
1795 #ifdef CONFIG_X86_64
1796 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1798 if (vmx
->host_state
.msr_host_bndcfgs
)
1799 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1801 * If the FPU is not active (through the host task or
1802 * the guest vcpu), then restore the cr0.TS bit.
1804 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1806 load_gdt(this_cpu_ptr(&host_gdt
));
1809 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1812 __vmx_load_host_state(vmx
);
1817 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1818 * vcpu mutex is already taken.
1820 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1822 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1823 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1826 kvm_cpu_vmxon(phys_addr
);
1827 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1828 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1830 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1831 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1832 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1835 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1836 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1837 unsigned long sysenter_esp
;
1839 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1840 local_irq_disable();
1841 crash_disable_local_vmclear(cpu
);
1844 * Read loaded_vmcs->cpu should be before fetching
1845 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1846 * See the comments in __loaded_vmcs_clear().
1850 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1851 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1852 crash_enable_local_vmclear(cpu
);
1856 * Linux uses per-cpu TSS and GDT, so set these when switching
1859 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1860 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1862 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1863 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1864 vmx
->loaded_vmcs
->cpu
= cpu
;
1868 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1870 __vmx_load_host_state(to_vmx(vcpu
));
1871 if (!vmm_exclusive
) {
1872 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1878 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1882 if (vcpu
->fpu_active
)
1884 vcpu
->fpu_active
= 1;
1885 cr0
= vmcs_readl(GUEST_CR0
);
1886 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1887 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1888 vmcs_writel(GUEST_CR0
, cr0
);
1889 update_exception_bitmap(vcpu
);
1890 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1891 if (is_guest_mode(vcpu
))
1892 vcpu
->arch
.cr0_guest_owned_bits
&=
1893 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1894 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1897 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1900 * Return the cr0 value that a nested guest would read. This is a combination
1901 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1902 * its hypervisor (cr0_read_shadow).
1904 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1906 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1907 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1909 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1911 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1912 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1915 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1917 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1918 * set this *before* calling this function.
1920 vmx_decache_cr0_guest_bits(vcpu
);
1921 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1922 update_exception_bitmap(vcpu
);
1923 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1924 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1925 if (is_guest_mode(vcpu
)) {
1927 * L1's specified read shadow might not contain the TS bit,
1928 * so now that we turned on shadowing of this bit, we need to
1929 * set this bit of the shadow. Like in nested_vmx_run we need
1930 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1931 * up-to-date here because we just decached cr0.TS (and we'll
1932 * only update vmcs12->guest_cr0 on nested exit).
1934 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1935 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1936 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1937 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1939 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1942 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1944 unsigned long rflags
, save_rflags
;
1946 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1947 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1948 rflags
= vmcs_readl(GUEST_RFLAGS
);
1949 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1950 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1951 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1952 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1954 to_vmx(vcpu
)->rflags
= rflags
;
1956 return to_vmx(vcpu
)->rflags
;
1959 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1961 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1962 to_vmx(vcpu
)->rflags
= rflags
;
1963 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1964 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1965 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1967 vmcs_writel(GUEST_RFLAGS
, rflags
);
1970 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1972 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1975 if (interruptibility
& GUEST_INTR_STATE_STI
)
1976 ret
|= KVM_X86_SHADOW_INT_STI
;
1977 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1978 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1983 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1985 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1986 u32 interruptibility
= interruptibility_old
;
1988 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1990 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1991 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1992 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1993 interruptibility
|= GUEST_INTR_STATE_STI
;
1995 if ((interruptibility
!= interruptibility_old
))
1996 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1999 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2003 rip
= kvm_rip_read(vcpu
);
2004 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2005 kvm_rip_write(vcpu
, rip
);
2007 /* skipping an emulated instruction also counts */
2008 vmx_set_interrupt_shadow(vcpu
, 0);
2012 * KVM wants to inject page-faults which it got to the guest. This function
2013 * checks whether in a nested guest, we need to inject them to L1 or L2.
2015 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2017 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2019 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2022 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2023 vmcs_read32(VM_EXIT_INTR_INFO
),
2024 vmcs_readl(EXIT_QUALIFICATION
));
2028 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2029 bool has_error_code
, u32 error_code
,
2032 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2033 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2035 if (!reinject
&& is_guest_mode(vcpu
) &&
2036 nested_vmx_check_exception(vcpu
, nr
))
2039 if (has_error_code
) {
2040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2041 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2044 if (vmx
->rmode
.vm86_active
) {
2046 if (kvm_exception_is_soft(nr
))
2047 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2048 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2049 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2053 if (kvm_exception_is_soft(nr
)) {
2054 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2055 vmx
->vcpu
.arch
.event_exit_inst_len
);
2056 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2058 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2060 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2063 static bool vmx_rdtscp_supported(void)
2065 return cpu_has_vmx_rdtscp();
2068 static bool vmx_invpcid_supported(void)
2070 return cpu_has_vmx_invpcid() && enable_ept
;
2074 * Swap MSR entry in host/guest MSR entry array.
2076 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2078 struct shared_msr_entry tmp
;
2080 tmp
= vmx
->guest_msrs
[to
];
2081 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2082 vmx
->guest_msrs
[from
] = tmp
;
2085 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2087 unsigned long *msr_bitmap
;
2089 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2090 if (is_long_mode(vcpu
))
2091 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2093 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2095 if (is_long_mode(vcpu
))
2096 msr_bitmap
= vmx_msr_bitmap_longmode
;
2098 msr_bitmap
= vmx_msr_bitmap_legacy
;
2101 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2105 * Set up the vmcs to automatically save and restore system
2106 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2107 * mode, as fiddling with msrs is very expensive.
2109 static void setup_msrs(struct vcpu_vmx
*vmx
)
2111 int save_nmsrs
, index
;
2114 #ifdef CONFIG_X86_64
2115 if (is_long_mode(&vmx
->vcpu
)) {
2116 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2118 move_msr_up(vmx
, index
, save_nmsrs
++);
2119 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2121 move_msr_up(vmx
, index
, save_nmsrs
++);
2122 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2124 move_msr_up(vmx
, index
, save_nmsrs
++);
2125 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2126 if (index
>= 0 && vmx
->rdtscp_enabled
)
2127 move_msr_up(vmx
, index
, save_nmsrs
++);
2129 * MSR_STAR is only needed on long mode guests, and only
2130 * if efer.sce is enabled.
2132 index
= __find_msr_index(vmx
, MSR_STAR
);
2133 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2134 move_msr_up(vmx
, index
, save_nmsrs
++);
2137 index
= __find_msr_index(vmx
, MSR_EFER
);
2138 if (index
>= 0 && update_transition_efer(vmx
, index
))
2139 move_msr_up(vmx
, index
, save_nmsrs
++);
2141 vmx
->save_nmsrs
= save_nmsrs
;
2143 if (cpu_has_vmx_msr_bitmap())
2144 vmx_set_msr_bitmap(&vmx
->vcpu
);
2148 * reads and returns guest's timestamp counter "register"
2149 * guest_tsc = host_tsc + tsc_offset -- 21.3
2151 static u64
guest_read_tsc(void)
2153 u64 host_tsc
, tsc_offset
;
2156 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2157 return host_tsc
+ tsc_offset
;
2161 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2162 * counter, even if a nested guest (L2) is currently running.
2164 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2168 tsc_offset
= is_guest_mode(vcpu
) ?
2169 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2170 vmcs_read64(TSC_OFFSET
);
2171 return host_tsc
+ tsc_offset
;
2175 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2176 * software catchup for faster rates on slower CPUs.
2178 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2183 if (user_tsc_khz
> tsc_khz
) {
2184 vcpu
->arch
.tsc_catchup
= 1;
2185 vcpu
->arch
.tsc_always_catchup
= 1;
2187 WARN(1, "user requested TSC rate below hardware speed\n");
2190 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2192 return vmcs_read64(TSC_OFFSET
);
2196 * writes 'offset' into guest's timestamp counter offset register
2198 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2200 if (is_guest_mode(vcpu
)) {
2202 * We're here if L1 chose not to trap WRMSR to TSC. According
2203 * to the spec, this should set L1's TSC; The offset that L1
2204 * set for L2 remains unchanged, and still needs to be added
2205 * to the newly set TSC to get L2's TSC.
2207 struct vmcs12
*vmcs12
;
2208 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2209 /* recalculate vmcs02.TSC_OFFSET: */
2210 vmcs12
= get_vmcs12(vcpu
);
2211 vmcs_write64(TSC_OFFSET
, offset
+
2212 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2213 vmcs12
->tsc_offset
: 0));
2215 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2216 vmcs_read64(TSC_OFFSET
), offset
);
2217 vmcs_write64(TSC_OFFSET
, offset
);
2221 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2223 u64 offset
= vmcs_read64(TSC_OFFSET
);
2225 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2226 if (is_guest_mode(vcpu
)) {
2227 /* Even when running L2, the adjustment needs to apply to L1 */
2228 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2230 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2231 offset
+ adjustment
);
2234 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2236 return target_tsc
- native_read_tsc();
2239 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2241 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2242 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2246 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2247 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2248 * all guests if the "nested" module option is off, and can also be disabled
2249 * for a single guest by disabling its VMX cpuid bit.
2251 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2253 return nested
&& guest_cpuid_has_vmx(vcpu
);
2257 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2258 * returned for the various VMX controls MSRs when nested VMX is enabled.
2259 * The same values should also be used to verify that vmcs12 control fields are
2260 * valid during nested entry from L1 to L2.
2261 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2262 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2263 * bit in the high half is on if the corresponding bit in the control field
2264 * may be on. See also vmx_control_verify().
2265 * TODO: allow these variables to be modified (downgraded) by module options
2268 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2269 static u32 nested_vmx_true_procbased_ctls_low
;
2270 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2271 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2272 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2273 static u32 nested_vmx_true_exit_ctls_low
;
2274 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2275 static u32 nested_vmx_true_entry_ctls_low
;
2276 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2277 static u32 nested_vmx_ept_caps
;
2278 static __init
void nested_vmx_setup_ctls_msrs(void)
2281 * Note that as a general rule, the high half of the MSRs (bits in
2282 * the control fields which may be 1) should be initialized by the
2283 * intersection of the underlying hardware's MSR (i.e., features which
2284 * can be supported) and the list of features we want to expose -
2285 * because they are known to be properly supported in our code.
2286 * Also, usually, the low half of the MSRs (bits which must be 1) can
2287 * be set to 0, meaning that L1 may turn off any of these bits. The
2288 * reason is that if one of these bits is necessary, it will appear
2289 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2290 * fields of vmcs01 and vmcs02, will turn these bits off - and
2291 * nested_vmx_exit_handled() will not pass related exits to L1.
2292 * These rules have exceptions below.
2295 /* pin-based controls */
2296 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2297 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2298 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2299 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2300 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2301 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2302 PIN_BASED_VMX_PREEMPTION_TIMER
;
2305 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2306 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2307 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2309 nested_vmx_exit_ctls_high
&=
2310 #ifdef CONFIG_X86_64
2311 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2313 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2314 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2315 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2316 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2318 if (vmx_mpx_supported())
2319 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2321 /* We support free control of debug control saving. */
2322 nested_vmx_true_exit_ctls_low
= nested_vmx_exit_ctls_low
&
2323 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2325 /* entry controls */
2326 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2327 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2328 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2329 nested_vmx_entry_ctls_high
&=
2330 #ifdef CONFIG_X86_64
2331 VM_ENTRY_IA32E_MODE
|
2333 VM_ENTRY_LOAD_IA32_PAT
;
2334 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2335 VM_ENTRY_LOAD_IA32_EFER
);
2336 if (vmx_mpx_supported())
2337 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2339 /* We support free control of debug control loading. */
2340 nested_vmx_true_entry_ctls_low
= nested_vmx_entry_ctls_low
&
2341 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2343 /* cpu-based controls */
2344 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2345 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2346 nested_vmx_procbased_ctls_low
= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2347 nested_vmx_procbased_ctls_high
&=
2348 CPU_BASED_VIRTUAL_INTR_PENDING
|
2349 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2350 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2351 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2352 CPU_BASED_CR3_STORE_EXITING
|
2353 #ifdef CONFIG_X86_64
2354 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2356 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2357 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2358 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2359 CPU_BASED_PAUSE_EXITING
| CPU_BASED_TPR_SHADOW
|
2360 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2362 * We can allow some features even when not supported by the
2363 * hardware. For example, L1 can specify an MSR bitmap - and we
2364 * can use it to avoid exits to L1 - even when L0 runs L2
2365 * without MSR bitmaps.
2367 nested_vmx_procbased_ctls_high
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2368 CPU_BASED_USE_MSR_BITMAPS
;
2370 /* We support free control of CR3 access interception. */
2371 nested_vmx_true_procbased_ctls_low
= nested_vmx_procbased_ctls_low
&
2372 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2374 /* secondary cpu-based controls */
2375 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2376 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2377 nested_vmx_secondary_ctls_low
= 0;
2378 nested_vmx_secondary_ctls_high
&=
2379 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2380 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2381 SECONDARY_EXEC_WBINVD_EXITING
;
2384 /* nested EPT: emulate EPT also to L1 */
2385 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2386 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2387 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2389 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2391 * For nested guests, we don't do anything specific
2392 * for single context invalidation. Hence, only advertise
2393 * support for global context invalidation.
2395 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2397 nested_vmx_ept_caps
= 0;
2399 /* miscellaneous data */
2400 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2401 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2402 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2403 VMX_MISC_ACTIVITY_HLT
;
2404 nested_vmx_misc_high
= 0;
2407 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2410 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2412 return ((control
& high
) | low
) == control
;
2415 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2417 return low
| ((u64
)high
<< 32);
2420 /* Returns 0 on success, non-0 otherwise. */
2421 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2423 switch (msr_index
) {
2424 case MSR_IA32_VMX_BASIC
:
2426 * This MSR reports some information about VMX support. We
2427 * should return information about the VMX we emulate for the
2428 * guest, and the VMCS structure we give it - not about the
2429 * VMX support of the underlying hardware.
2431 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2432 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2433 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2435 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2436 case MSR_IA32_VMX_PINBASED_CTLS
:
2437 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2438 nested_vmx_pinbased_ctls_high
);
2440 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2441 *pdata
= vmx_control_msr(nested_vmx_true_procbased_ctls_low
,
2442 nested_vmx_procbased_ctls_high
);
2444 case MSR_IA32_VMX_PROCBASED_CTLS
:
2445 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2446 nested_vmx_procbased_ctls_high
);
2448 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2449 *pdata
= vmx_control_msr(nested_vmx_true_exit_ctls_low
,
2450 nested_vmx_exit_ctls_high
);
2452 case MSR_IA32_VMX_EXIT_CTLS
:
2453 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2454 nested_vmx_exit_ctls_high
);
2456 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2457 *pdata
= vmx_control_msr(nested_vmx_true_entry_ctls_low
,
2458 nested_vmx_entry_ctls_high
);
2460 case MSR_IA32_VMX_ENTRY_CTLS
:
2461 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2462 nested_vmx_entry_ctls_high
);
2464 case MSR_IA32_VMX_MISC
:
2465 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2466 nested_vmx_misc_high
);
2469 * These MSRs specify bits which the guest must keep fixed (on or off)
2470 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2471 * We picked the standard core2 setting.
2473 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2474 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2475 case MSR_IA32_VMX_CR0_FIXED0
:
2476 *pdata
= VMXON_CR0_ALWAYSON
;
2478 case MSR_IA32_VMX_CR0_FIXED1
:
2481 case MSR_IA32_VMX_CR4_FIXED0
:
2482 *pdata
= VMXON_CR4_ALWAYSON
;
2484 case MSR_IA32_VMX_CR4_FIXED1
:
2487 case MSR_IA32_VMX_VMCS_ENUM
:
2488 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2490 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2491 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2492 nested_vmx_secondary_ctls_high
);
2494 case MSR_IA32_VMX_EPT_VPID_CAP
:
2495 /* Currently, no nested vpid support */
2496 *pdata
= nested_vmx_ept_caps
;
2506 * Reads an msr value (of 'msr_index') into 'pdata'.
2507 * Returns 0 on success, non-0 otherwise.
2508 * Assumes vcpu_load() was already called.
2510 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2513 struct shared_msr_entry
*msr
;
2516 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2520 switch (msr_index
) {
2521 #ifdef CONFIG_X86_64
2523 data
= vmcs_readl(GUEST_FS_BASE
);
2526 data
= vmcs_readl(GUEST_GS_BASE
);
2528 case MSR_KERNEL_GS_BASE
:
2529 vmx_load_host_state(to_vmx(vcpu
));
2530 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2534 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2536 data
= guest_read_tsc();
2538 case MSR_IA32_SYSENTER_CS
:
2539 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2541 case MSR_IA32_SYSENTER_EIP
:
2542 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2544 case MSR_IA32_SYSENTER_ESP
:
2545 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2547 case MSR_IA32_BNDCFGS
:
2548 if (!vmx_mpx_supported())
2550 data
= vmcs_read64(GUEST_BNDCFGS
);
2552 case MSR_IA32_FEATURE_CONTROL
:
2553 if (!nested_vmx_allowed(vcpu
))
2555 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2557 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2558 if (!nested_vmx_allowed(vcpu
))
2560 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2562 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2564 /* Otherwise falls through */
2566 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2571 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2578 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2581 * Writes msr value into into the appropriate "register".
2582 * Returns 0 on success, non-0 otherwise.
2583 * Assumes vcpu_load() was already called.
2585 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2588 struct shared_msr_entry
*msr
;
2590 u32 msr_index
= msr_info
->index
;
2591 u64 data
= msr_info
->data
;
2593 switch (msr_index
) {
2595 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2597 #ifdef CONFIG_X86_64
2599 vmx_segment_cache_clear(vmx
);
2600 vmcs_writel(GUEST_FS_BASE
, data
);
2603 vmx_segment_cache_clear(vmx
);
2604 vmcs_writel(GUEST_GS_BASE
, data
);
2606 case MSR_KERNEL_GS_BASE
:
2607 vmx_load_host_state(vmx
);
2608 vmx
->msr_guest_kernel_gs_base
= data
;
2611 case MSR_IA32_SYSENTER_CS
:
2612 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2614 case MSR_IA32_SYSENTER_EIP
:
2615 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2617 case MSR_IA32_SYSENTER_ESP
:
2618 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2620 case MSR_IA32_BNDCFGS
:
2621 if (!vmx_mpx_supported())
2623 vmcs_write64(GUEST_BNDCFGS
, data
);
2626 kvm_write_tsc(vcpu
, msr_info
);
2628 case MSR_IA32_CR_PAT
:
2629 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2630 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2632 vmcs_write64(GUEST_IA32_PAT
, data
);
2633 vcpu
->arch
.pat
= data
;
2636 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2638 case MSR_IA32_TSC_ADJUST
:
2639 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2641 case MSR_IA32_FEATURE_CONTROL
:
2642 if (!nested_vmx_allowed(vcpu
) ||
2643 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2644 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2646 vmx
->nested
.msr_ia32_feature_control
= data
;
2647 if (msr_info
->host_initiated
&& data
== 0)
2648 vmx_leave_nested(vcpu
);
2650 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2651 return 1; /* they are read-only */
2653 if (!vmx
->rdtscp_enabled
)
2655 /* Check reserved bit, higher 32 bits should be zero */
2656 if ((data
>> 32) != 0)
2658 /* Otherwise falls through */
2660 msr
= find_msr_entry(vmx
, msr_index
);
2662 u64 old_msr_data
= msr
->data
;
2664 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2666 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2670 msr
->data
= old_msr_data
;
2674 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2680 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2682 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2685 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2688 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2690 case VCPU_EXREG_PDPTR
:
2692 ept_save_pdptrs(vcpu
);
2699 static __init
int cpu_has_kvm_support(void)
2701 return cpu_has_vmx();
2704 static __init
int vmx_disabled_by_bios(void)
2708 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2709 if (msr
& FEATURE_CONTROL_LOCKED
) {
2710 /* launched w/ TXT and VMX disabled */
2711 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2714 /* launched w/o TXT and VMX only enabled w/ TXT */
2715 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2716 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2717 && !tboot_enabled()) {
2718 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2719 "activate TXT before enabling KVM\n");
2722 /* launched w/o TXT and VMX disabled */
2723 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2724 && !tboot_enabled())
2731 static void kvm_cpu_vmxon(u64 addr
)
2733 asm volatile (ASM_VMX_VMXON_RAX
2734 : : "a"(&addr
), "m"(addr
)
2738 static int hardware_enable(void)
2740 int cpu
= raw_smp_processor_id();
2741 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2744 if (read_cr4() & X86_CR4_VMXE
)
2747 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2750 * Now we can enable the vmclear operation in kdump
2751 * since the loaded_vmcss_on_cpu list on this cpu
2752 * has been initialized.
2754 * Though the cpu is not in VMX operation now, there
2755 * is no problem to enable the vmclear operation
2756 * for the loaded_vmcss_on_cpu list is empty!
2758 crash_enable_local_vmclear(cpu
);
2760 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2762 test_bits
= FEATURE_CONTROL_LOCKED
;
2763 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2764 if (tboot_enabled())
2765 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2767 if ((old
& test_bits
) != test_bits
) {
2768 /* enable and lock */
2769 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2771 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2773 if (vmm_exclusive
) {
2774 kvm_cpu_vmxon(phys_addr
);
2778 native_store_gdt(this_cpu_ptr(&host_gdt
));
2783 static void vmclear_local_loaded_vmcss(void)
2785 int cpu
= raw_smp_processor_id();
2786 struct loaded_vmcs
*v
, *n
;
2788 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2789 loaded_vmcss_on_cpu_link
)
2790 __loaded_vmcs_clear(v
);
2794 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2797 static void kvm_cpu_vmxoff(void)
2799 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2802 static void hardware_disable(void)
2804 if (vmm_exclusive
) {
2805 vmclear_local_loaded_vmcss();
2808 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2811 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2812 u32 msr
, u32
*result
)
2814 u32 vmx_msr_low
, vmx_msr_high
;
2815 u32 ctl
= ctl_min
| ctl_opt
;
2817 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2819 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2820 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2822 /* Ensure minimum (required) set of control bits are supported. */
2830 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2832 u32 vmx_msr_low
, vmx_msr_high
;
2834 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2835 return vmx_msr_high
& ctl
;
2838 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2840 u32 vmx_msr_low
, vmx_msr_high
;
2841 u32 min
, opt
, min2
, opt2
;
2842 u32 _pin_based_exec_control
= 0;
2843 u32 _cpu_based_exec_control
= 0;
2844 u32 _cpu_based_2nd_exec_control
= 0;
2845 u32 _vmexit_control
= 0;
2846 u32 _vmentry_control
= 0;
2848 min
= CPU_BASED_HLT_EXITING
|
2849 #ifdef CONFIG_X86_64
2850 CPU_BASED_CR8_LOAD_EXITING
|
2851 CPU_BASED_CR8_STORE_EXITING
|
2853 CPU_BASED_CR3_LOAD_EXITING
|
2854 CPU_BASED_CR3_STORE_EXITING
|
2855 CPU_BASED_USE_IO_BITMAPS
|
2856 CPU_BASED_MOV_DR_EXITING
|
2857 CPU_BASED_USE_TSC_OFFSETING
|
2858 CPU_BASED_MWAIT_EXITING
|
2859 CPU_BASED_MONITOR_EXITING
|
2860 CPU_BASED_INVLPG_EXITING
|
2861 CPU_BASED_RDPMC_EXITING
;
2863 opt
= CPU_BASED_TPR_SHADOW
|
2864 CPU_BASED_USE_MSR_BITMAPS
|
2865 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2866 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2867 &_cpu_based_exec_control
) < 0)
2869 #ifdef CONFIG_X86_64
2870 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2871 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2872 ~CPU_BASED_CR8_STORE_EXITING
;
2874 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2876 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2877 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2878 SECONDARY_EXEC_WBINVD_EXITING
|
2879 SECONDARY_EXEC_ENABLE_VPID
|
2880 SECONDARY_EXEC_ENABLE_EPT
|
2881 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2882 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2883 SECONDARY_EXEC_RDTSCP
|
2884 SECONDARY_EXEC_ENABLE_INVPCID
|
2885 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2887 SECONDARY_EXEC_SHADOW_VMCS
;
2888 if (adjust_vmx_controls(min2
, opt2
,
2889 MSR_IA32_VMX_PROCBASED_CTLS2
,
2890 &_cpu_based_2nd_exec_control
) < 0)
2893 #ifndef CONFIG_X86_64
2894 if (!(_cpu_based_2nd_exec_control
&
2895 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2896 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2899 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2900 _cpu_based_2nd_exec_control
&= ~(
2901 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2902 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2903 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2905 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2906 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2908 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2909 CPU_BASED_CR3_STORE_EXITING
|
2910 CPU_BASED_INVLPG_EXITING
);
2911 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2912 vmx_capability
.ept
, vmx_capability
.vpid
);
2915 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2916 #ifdef CONFIG_X86_64
2917 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2919 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2920 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2921 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2922 &_vmexit_control
) < 0)
2925 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2926 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2927 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2928 &_pin_based_exec_control
) < 0)
2931 if (!(_cpu_based_2nd_exec_control
&
2932 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2933 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2934 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2936 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2937 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2938 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2939 &_vmentry_control
) < 0)
2942 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2944 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2945 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2948 #ifdef CONFIG_X86_64
2949 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2950 if (vmx_msr_high
& (1u<<16))
2954 /* Require Write-Back (WB) memory type for VMCS accesses. */
2955 if (((vmx_msr_high
>> 18) & 15) != 6)
2958 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2959 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2960 vmcs_conf
->revision_id
= vmx_msr_low
;
2962 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2963 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2964 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2965 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2966 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2968 cpu_has_load_ia32_efer
=
2969 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2970 VM_ENTRY_LOAD_IA32_EFER
)
2971 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2972 VM_EXIT_LOAD_IA32_EFER
);
2974 cpu_has_load_perf_global_ctrl
=
2975 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2976 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2977 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2978 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2981 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2982 * but due to arrata below it can't be used. Workaround is to use
2983 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2985 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2990 * BC86,AAY89,BD102 (model 44)
2994 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2995 switch (boot_cpu_data
.x86_model
) {
3001 cpu_has_load_perf_global_ctrl
= false;
3002 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3003 "does not work properly. Using workaround\n");
3013 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3015 int node
= cpu_to_node(cpu
);
3019 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3022 vmcs
= page_address(pages
);
3023 memset(vmcs
, 0, vmcs_config
.size
);
3024 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3028 static struct vmcs
*alloc_vmcs(void)
3030 return alloc_vmcs_cpu(raw_smp_processor_id());
3033 static void free_vmcs(struct vmcs
*vmcs
)
3035 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3039 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3041 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3043 if (!loaded_vmcs
->vmcs
)
3045 loaded_vmcs_clear(loaded_vmcs
);
3046 free_vmcs(loaded_vmcs
->vmcs
);
3047 loaded_vmcs
->vmcs
= NULL
;
3050 static void free_kvm_area(void)
3054 for_each_possible_cpu(cpu
) {
3055 free_vmcs(per_cpu(vmxarea
, cpu
));
3056 per_cpu(vmxarea
, cpu
) = NULL
;
3060 static void init_vmcs_shadow_fields(void)
3064 /* No checks for read only fields yet */
3066 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3067 switch (shadow_read_write_fields
[i
]) {
3069 if (!vmx_mpx_supported())
3077 shadow_read_write_fields
[j
] =
3078 shadow_read_write_fields
[i
];
3081 max_shadow_read_write_fields
= j
;
3083 /* shadowed fields guest access without vmexit */
3084 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3085 clear_bit(shadow_read_write_fields
[i
],
3086 vmx_vmwrite_bitmap
);
3087 clear_bit(shadow_read_write_fields
[i
],
3090 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3091 clear_bit(shadow_read_only_fields
[i
],
3095 static __init
int alloc_kvm_area(void)
3099 for_each_possible_cpu(cpu
) {
3102 vmcs
= alloc_vmcs_cpu(cpu
);
3108 per_cpu(vmxarea
, cpu
) = vmcs
;
3113 static __init
int hardware_setup(void)
3115 if (setup_vmcs_config(&vmcs_config
) < 0)
3118 if (boot_cpu_has(X86_FEATURE_NX
))
3119 kvm_enable_efer_bits(EFER_NX
);
3121 if (!cpu_has_vmx_vpid())
3123 if (!cpu_has_vmx_shadow_vmcs())
3124 enable_shadow_vmcs
= 0;
3125 if (enable_shadow_vmcs
)
3126 init_vmcs_shadow_fields();
3128 if (!cpu_has_vmx_ept() ||
3129 !cpu_has_vmx_ept_4levels()) {
3131 enable_unrestricted_guest
= 0;
3132 enable_ept_ad_bits
= 0;
3135 if (!cpu_has_vmx_ept_ad_bits())
3136 enable_ept_ad_bits
= 0;
3138 if (!cpu_has_vmx_unrestricted_guest())
3139 enable_unrestricted_guest
= 0;
3141 if (!cpu_has_vmx_flexpriority()) {
3142 flexpriority_enabled
= 0;
3145 * set_apic_access_page_addr() is used to reload apic access
3146 * page upon invalidation. No need to do anything if the
3147 * processor does not have the APIC_ACCESS_ADDR VMCS field.
3149 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
3152 if (!cpu_has_vmx_tpr_shadow())
3153 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3155 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3156 kvm_disable_largepages();
3158 if (!cpu_has_vmx_ple())
3161 if (!cpu_has_vmx_apicv())
3165 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3167 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3168 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3169 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3173 nested_vmx_setup_ctls_msrs();
3175 return alloc_kvm_area();
3178 static __exit
void hardware_unsetup(void)
3183 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3185 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3188 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3189 struct kvm_segment
*save
)
3191 if (!emulate_invalid_guest_state
) {
3193 * CS and SS RPL should be equal during guest entry according
3194 * to VMX spec, but in reality it is not always so. Since vcpu
3195 * is in the middle of the transition from real mode to
3196 * protected mode it is safe to assume that RPL 0 is a good
3199 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3200 save
->selector
&= ~SELECTOR_RPL_MASK
;
3201 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3204 vmx_set_segment(vcpu
, save
, seg
);
3207 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3209 unsigned long flags
;
3210 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3213 * Update real mode segment cache. It may be not up-to-date if sement
3214 * register was written while vcpu was in a guest mode.
3216 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3217 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3218 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3219 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3220 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3221 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3223 vmx
->rmode
.vm86_active
= 0;
3225 vmx_segment_cache_clear(vmx
);
3227 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3229 flags
= vmcs_readl(GUEST_RFLAGS
);
3230 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3231 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3232 vmcs_writel(GUEST_RFLAGS
, flags
);
3234 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3235 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3237 update_exception_bitmap(vcpu
);
3239 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3240 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3241 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3242 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3243 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3244 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3247 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3249 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3250 struct kvm_segment var
= *save
;
3253 if (seg
== VCPU_SREG_CS
)
3256 if (!emulate_invalid_guest_state
) {
3257 var
.selector
= var
.base
>> 4;
3258 var
.base
= var
.base
& 0xffff0;
3268 if (save
->base
& 0xf)
3269 printk_once(KERN_WARNING
"kvm: segment base is not "
3270 "paragraph aligned when entering "
3271 "protected mode (seg=%d)", seg
);
3274 vmcs_write16(sf
->selector
, var
.selector
);
3275 vmcs_write32(sf
->base
, var
.base
);
3276 vmcs_write32(sf
->limit
, var
.limit
);
3277 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3280 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3282 unsigned long flags
;
3283 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3285 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3286 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3287 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3288 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3289 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3290 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3291 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3293 vmx
->rmode
.vm86_active
= 1;
3296 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3297 * vcpu. Warn the user that an update is overdue.
3299 if (!vcpu
->kvm
->arch
.tss_addr
)
3300 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3301 "called before entering vcpu\n");
3303 vmx_segment_cache_clear(vmx
);
3305 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3306 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3307 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3309 flags
= vmcs_readl(GUEST_RFLAGS
);
3310 vmx
->rmode
.save_rflags
= flags
;
3312 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3314 vmcs_writel(GUEST_RFLAGS
, flags
);
3315 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3316 update_exception_bitmap(vcpu
);
3318 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3319 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3320 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3321 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3322 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3323 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3325 kvm_mmu_reset_context(vcpu
);
3328 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3330 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3331 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3337 * Force kernel_gs_base reloading before EFER changes, as control
3338 * of this msr depends on is_long_mode().
3340 vmx_load_host_state(to_vmx(vcpu
));
3341 vcpu
->arch
.efer
= efer
;
3342 if (efer
& EFER_LMA
) {
3343 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3346 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3348 msr
->data
= efer
& ~EFER_LME
;
3353 #ifdef CONFIG_X86_64
3355 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3359 vmx_segment_cache_clear(to_vmx(vcpu
));
3361 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3362 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3363 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3365 vmcs_write32(GUEST_TR_AR_BYTES
,
3366 (guest_tr_ar
& ~AR_TYPE_MASK
)
3367 | AR_TYPE_BUSY_64_TSS
);
3369 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3372 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3374 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3375 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3380 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3382 vpid_sync_context(to_vmx(vcpu
));
3384 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3386 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3390 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3392 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3394 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3395 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3398 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3400 if (enable_ept
&& is_paging(vcpu
))
3401 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3402 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3405 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3407 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3409 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3410 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3413 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3415 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3417 if (!test_bit(VCPU_EXREG_PDPTR
,
3418 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3421 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3422 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3423 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3424 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3425 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3429 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3431 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3433 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3434 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3435 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3436 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3437 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3440 __set_bit(VCPU_EXREG_PDPTR
,
3441 (unsigned long *)&vcpu
->arch
.regs_avail
);
3442 __set_bit(VCPU_EXREG_PDPTR
,
3443 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3446 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3448 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3450 struct kvm_vcpu
*vcpu
)
3452 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3453 vmx_decache_cr3(vcpu
);
3454 if (!(cr0
& X86_CR0_PG
)) {
3455 /* From paging/starting to nonpaging */
3456 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3457 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3458 (CPU_BASED_CR3_LOAD_EXITING
|
3459 CPU_BASED_CR3_STORE_EXITING
));
3460 vcpu
->arch
.cr0
= cr0
;
3461 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3462 } else if (!is_paging(vcpu
)) {
3463 /* From nonpaging to paging */
3464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3465 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3466 ~(CPU_BASED_CR3_LOAD_EXITING
|
3467 CPU_BASED_CR3_STORE_EXITING
));
3468 vcpu
->arch
.cr0
= cr0
;
3469 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3472 if (!(cr0
& X86_CR0_WP
))
3473 *hw_cr0
&= ~X86_CR0_WP
;
3476 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3478 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3479 unsigned long hw_cr0
;
3481 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3482 if (enable_unrestricted_guest
)
3483 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3485 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3487 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3490 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3494 #ifdef CONFIG_X86_64
3495 if (vcpu
->arch
.efer
& EFER_LME
) {
3496 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3498 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3504 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3506 if (!vcpu
->fpu_active
)
3507 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3509 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3510 vmcs_writel(GUEST_CR0
, hw_cr0
);
3511 vcpu
->arch
.cr0
= cr0
;
3513 /* depends on vcpu->arch.cr0 to be set to a new value */
3514 vmx
->emulation_required
= emulation_required(vcpu
);
3517 static u64
construct_eptp(unsigned long root_hpa
)
3521 /* TODO write the value reading from MSR */
3522 eptp
= VMX_EPT_DEFAULT_MT
|
3523 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3524 if (enable_ept_ad_bits
)
3525 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3526 eptp
|= (root_hpa
& PAGE_MASK
);
3531 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3533 unsigned long guest_cr3
;
3538 eptp
= construct_eptp(cr3
);
3539 vmcs_write64(EPT_POINTER
, eptp
);
3540 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3541 guest_cr3
= kvm_read_cr3(vcpu
);
3543 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3544 ept_load_pdptrs(vcpu
);
3547 vmx_flush_tlb(vcpu
);
3548 vmcs_writel(GUEST_CR3
, guest_cr3
);
3551 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3553 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3554 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3556 if (cr4
& X86_CR4_VMXE
) {
3558 * To use VMXON (and later other VMX instructions), a guest
3559 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3560 * So basically the check on whether to allow nested VMX
3563 if (!nested_vmx_allowed(vcpu
))
3566 if (to_vmx(vcpu
)->nested
.vmxon
&&
3567 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3570 vcpu
->arch
.cr4
= cr4
;
3572 if (!is_paging(vcpu
)) {
3573 hw_cr4
&= ~X86_CR4_PAE
;
3574 hw_cr4
|= X86_CR4_PSE
;
3576 * SMEP/SMAP is disabled if CPU is in non-paging mode
3577 * in hardware. However KVM always uses paging mode to
3578 * emulate guest non-paging mode with TDP.
3579 * To emulate this behavior, SMEP/SMAP needs to be
3580 * manually disabled when guest switches to non-paging
3583 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3584 } else if (!(cr4
& X86_CR4_PAE
)) {
3585 hw_cr4
&= ~X86_CR4_PAE
;
3589 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3590 vmcs_writel(GUEST_CR4
, hw_cr4
);
3594 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3595 struct kvm_segment
*var
, int seg
)
3597 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3600 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3601 *var
= vmx
->rmode
.segs
[seg
];
3602 if (seg
== VCPU_SREG_TR
3603 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3605 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3606 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3609 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3610 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3611 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3612 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3613 var
->unusable
= (ar
>> 16) & 1;
3614 var
->type
= ar
& 15;
3615 var
->s
= (ar
>> 4) & 1;
3616 var
->dpl
= (ar
>> 5) & 3;
3618 * Some userspaces do not preserve unusable property. Since usable
3619 * segment has to be present according to VMX spec we can use present
3620 * property to amend userspace bug by making unusable segment always
3621 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3622 * segment as unusable.
3624 var
->present
= !var
->unusable
;
3625 var
->avl
= (ar
>> 12) & 1;
3626 var
->l
= (ar
>> 13) & 1;
3627 var
->db
= (ar
>> 14) & 1;
3628 var
->g
= (ar
>> 15) & 1;
3631 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3633 struct kvm_segment s
;
3635 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3636 vmx_get_segment(vcpu
, &s
, seg
);
3639 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3642 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3644 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3646 if (unlikely(vmx
->rmode
.vm86_active
))
3649 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3654 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3658 if (var
->unusable
|| !var
->present
)
3661 ar
= var
->type
& 15;
3662 ar
|= (var
->s
& 1) << 4;
3663 ar
|= (var
->dpl
& 3) << 5;
3664 ar
|= (var
->present
& 1) << 7;
3665 ar
|= (var
->avl
& 1) << 12;
3666 ar
|= (var
->l
& 1) << 13;
3667 ar
|= (var
->db
& 1) << 14;
3668 ar
|= (var
->g
& 1) << 15;
3674 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3675 struct kvm_segment
*var
, int seg
)
3677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3678 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3680 vmx_segment_cache_clear(vmx
);
3682 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3683 vmx
->rmode
.segs
[seg
] = *var
;
3684 if (seg
== VCPU_SREG_TR
)
3685 vmcs_write16(sf
->selector
, var
->selector
);
3687 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3691 vmcs_writel(sf
->base
, var
->base
);
3692 vmcs_write32(sf
->limit
, var
->limit
);
3693 vmcs_write16(sf
->selector
, var
->selector
);
3696 * Fix the "Accessed" bit in AR field of segment registers for older
3698 * IA32 arch specifies that at the time of processor reset the
3699 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3700 * is setting it to 0 in the userland code. This causes invalid guest
3701 * state vmexit when "unrestricted guest" mode is turned on.
3702 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3703 * tree. Newer qemu binaries with that qemu fix would not need this
3706 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3707 var
->type
|= 0x1; /* Accessed */
3709 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3712 vmx
->emulation_required
= emulation_required(vcpu
);
3715 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3717 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3719 *db
= (ar
>> 14) & 1;
3720 *l
= (ar
>> 13) & 1;
3723 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3725 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3726 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3729 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3731 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3732 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3735 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3737 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3738 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3741 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3743 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3744 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3747 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3749 struct kvm_segment var
;
3752 vmx_get_segment(vcpu
, &var
, seg
);
3754 if (seg
== VCPU_SREG_CS
)
3756 ar
= vmx_segment_access_rights(&var
);
3758 if (var
.base
!= (var
.selector
<< 4))
3760 if (var
.limit
!= 0xffff)
3768 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3770 struct kvm_segment cs
;
3771 unsigned int cs_rpl
;
3773 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3774 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3778 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3782 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3783 if (cs
.dpl
> cs_rpl
)
3786 if (cs
.dpl
!= cs_rpl
)
3792 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3796 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3798 struct kvm_segment ss
;
3799 unsigned int ss_rpl
;
3801 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3802 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3806 if (ss
.type
!= 3 && ss
.type
!= 7)
3810 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3818 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3820 struct kvm_segment var
;
3823 vmx_get_segment(vcpu
, &var
, seg
);
3824 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3832 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3833 if (var
.dpl
< rpl
) /* DPL < RPL */
3837 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3843 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3845 struct kvm_segment tr
;
3847 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3851 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3853 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3861 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3863 struct kvm_segment ldtr
;
3865 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3869 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3879 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3881 struct kvm_segment cs
, ss
;
3883 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3884 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3886 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3887 (ss
.selector
& SELECTOR_RPL_MASK
));
3891 * Check if guest state is valid. Returns true if valid, false if
3893 * We assume that registers are always usable
3895 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3897 if (enable_unrestricted_guest
)
3900 /* real mode guest state checks */
3901 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3902 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3904 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3906 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3908 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3910 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3912 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3915 /* protected mode guest state checks */
3916 if (!cs_ss_rpl_check(vcpu
))
3918 if (!code_segment_valid(vcpu
))
3920 if (!stack_segment_valid(vcpu
))
3922 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3924 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3926 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3928 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3930 if (!tr_valid(vcpu
))
3932 if (!ldtr_valid(vcpu
))
3936 * - Add checks on RIP
3937 * - Add checks on RFLAGS
3943 static int init_rmode_tss(struct kvm
*kvm
)
3949 idx
= srcu_read_lock(&kvm
->srcu
);
3950 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3951 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3954 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3955 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3956 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3959 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3962 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3966 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3967 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3970 srcu_read_unlock(&kvm
->srcu
, idx
);
3974 static int init_rmode_identity_map(struct kvm
*kvm
)
3977 pfn_t identity_map_pfn
;
3983 /* Protect kvm->arch.ept_identity_pagetable_done. */
3984 mutex_lock(&kvm
->slots_lock
);
3986 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3989 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3991 r
= alloc_identity_pagetable(kvm
);
3995 idx
= srcu_read_lock(&kvm
->srcu
);
3996 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3999 /* Set up identity-mapping pagetable for EPT in real mode */
4000 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4001 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4002 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4003 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4004 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4008 kvm
->arch
.ept_identity_pagetable_done
= true;
4011 srcu_read_unlock(&kvm
->srcu
, idx
);
4014 mutex_unlock(&kvm
->slots_lock
);
4018 static void seg_setup(int seg
)
4020 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4023 vmcs_write16(sf
->selector
, 0);
4024 vmcs_writel(sf
->base
, 0);
4025 vmcs_write32(sf
->limit
, 0xffff);
4027 if (seg
== VCPU_SREG_CS
)
4028 ar
|= 0x08; /* code segment */
4030 vmcs_write32(sf
->ar_bytes
, ar
);
4033 static int alloc_apic_access_page(struct kvm
*kvm
)
4036 struct kvm_userspace_memory_region kvm_userspace_mem
;
4039 mutex_lock(&kvm
->slots_lock
);
4040 if (kvm
->arch
.apic_access_page_done
)
4042 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4043 kvm_userspace_mem
.flags
= 0;
4044 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
4045 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4046 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4050 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4051 if (is_error_page(page
)) {
4057 * Do not pin the page in memory, so that memory hot-unplug
4058 * is able to migrate it.
4061 kvm
->arch
.apic_access_page_done
= true;
4063 mutex_unlock(&kvm
->slots_lock
);
4067 static int alloc_identity_pagetable(struct kvm
*kvm
)
4069 /* Called with kvm->slots_lock held. */
4071 struct kvm_userspace_memory_region kvm_userspace_mem
;
4074 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4076 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4077 kvm_userspace_mem
.flags
= 0;
4078 kvm_userspace_mem
.guest_phys_addr
=
4079 kvm
->arch
.ept_identity_map_addr
;
4080 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4081 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4086 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4093 spin_lock(&vmx_vpid_lock
);
4094 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4095 if (vpid
< VMX_NR_VPIDS
) {
4097 __set_bit(vpid
, vmx_vpid_bitmap
);
4099 spin_unlock(&vmx_vpid_lock
);
4102 static void free_vpid(struct vcpu_vmx
*vmx
)
4106 spin_lock(&vmx_vpid_lock
);
4108 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4109 spin_unlock(&vmx_vpid_lock
);
4112 #define MSR_TYPE_R 1
4113 #define MSR_TYPE_W 2
4114 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4117 int f
= sizeof(unsigned long);
4119 if (!cpu_has_vmx_msr_bitmap())
4123 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4124 * have the write-low and read-high bitmap offsets the wrong way round.
4125 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4127 if (msr
<= 0x1fff) {
4128 if (type
& MSR_TYPE_R
)
4130 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4132 if (type
& MSR_TYPE_W
)
4134 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4136 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4138 if (type
& MSR_TYPE_R
)
4140 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4142 if (type
& MSR_TYPE_W
)
4144 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4149 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4152 int f
= sizeof(unsigned long);
4154 if (!cpu_has_vmx_msr_bitmap())
4158 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4159 * have the write-low and read-high bitmap offsets the wrong way round.
4160 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4162 if (msr
<= 0x1fff) {
4163 if (type
& MSR_TYPE_R
)
4165 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4167 if (type
& MSR_TYPE_W
)
4169 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4171 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4173 if (type
& MSR_TYPE_R
)
4175 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4177 if (type
& MSR_TYPE_W
)
4179 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4184 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4187 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4188 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4189 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4190 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4193 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4195 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4197 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4201 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4203 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4205 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4209 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4211 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4213 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4217 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4219 return enable_apicv
&& irqchip_in_kernel(kvm
);
4223 * Send interrupt to vcpu via posted interrupt way.
4224 * 1. If target vcpu is running(non-root mode), send posted interrupt
4225 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4226 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4227 * interrupt from PIR in next vmentry.
4229 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4231 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4234 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4237 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4238 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4240 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4241 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4242 POSTED_INTR_VECTOR
);
4245 kvm_vcpu_kick(vcpu
);
4248 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4250 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4252 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4255 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4258 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4264 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4265 * will not change in the lifetime of the guest.
4266 * Note that host-state that does change is set elsewhere. E.g., host-state
4267 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4269 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4276 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4277 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4279 /* Save the most likely value for this task's CR4 in the VMCS. */
4281 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4282 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4284 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4285 #ifdef CONFIG_X86_64
4287 * Load null selectors, so we can avoid reloading them in
4288 * __vmx_load_host_state(), in case userspace uses the null selectors
4289 * too (the expected case).
4291 vmcs_write16(HOST_DS_SELECTOR
, 0);
4292 vmcs_write16(HOST_ES_SELECTOR
, 0);
4294 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4295 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4297 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4298 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4300 native_store_idt(&dt
);
4301 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4302 vmx
->host_idt_base
= dt
.address
;
4304 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4306 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4307 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4308 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4309 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4311 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4312 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4313 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4317 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4319 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4321 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4322 if (is_guest_mode(&vmx
->vcpu
))
4323 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4324 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4325 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4328 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4330 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4332 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4333 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4334 return pin_based_exec_ctrl
;
4337 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4339 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4341 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4342 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4344 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4345 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4346 #ifdef CONFIG_X86_64
4347 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4348 CPU_BASED_CR8_LOAD_EXITING
;
4352 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4353 CPU_BASED_CR3_LOAD_EXITING
|
4354 CPU_BASED_INVLPG_EXITING
;
4355 return exec_control
;
4358 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4360 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4361 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4362 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4364 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4366 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4367 enable_unrestricted_guest
= 0;
4368 /* Enable INVPCID for non-ept guests may cause performance regression. */
4369 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4371 if (!enable_unrestricted_guest
)
4372 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4374 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4375 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4376 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4377 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4378 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4379 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4381 We can NOT enable shadow_vmcs here because we don't have yet
4384 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4385 return exec_control
;
4388 static void ept_set_mmio_spte_mask(void)
4391 * EPT Misconfigurations can be generated if the value of bits 2:0
4392 * of an EPT paging-structure entry is 110b (write/execute).
4393 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4396 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4400 * Sets up the vmcs for emulated real mode.
4402 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4404 #ifdef CONFIG_X86_64
4410 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4411 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4413 if (enable_shadow_vmcs
) {
4414 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4415 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4417 if (cpu_has_vmx_msr_bitmap())
4418 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4420 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4423 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4425 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4427 if (cpu_has_secondary_exec_ctrls()) {
4428 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4429 vmx_secondary_exec_control(vmx
));
4432 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4433 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4434 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4435 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4436 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4438 vmcs_write16(GUEST_INTR_STATUS
, 0);
4440 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4441 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4445 vmcs_write32(PLE_GAP
, ple_gap
);
4446 vmx
->ple_window
= ple_window
;
4447 vmx
->ple_window_dirty
= true;
4450 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4451 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4452 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4454 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4455 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4456 vmx_set_constant_host_state(vmx
);
4457 #ifdef CONFIG_X86_64
4458 rdmsrl(MSR_FS_BASE
, a
);
4459 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4460 rdmsrl(MSR_GS_BASE
, a
);
4461 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4463 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4464 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4467 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4468 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4469 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4470 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4471 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4473 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4474 u32 msr_low
, msr_high
;
4476 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4477 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4478 /* Write the default value follow host pat */
4479 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4480 /* Keep arch.pat sync with GUEST_IA32_PAT */
4481 vmx
->vcpu
.arch
.pat
= host_pat
;
4484 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4485 u32 index
= vmx_msr_index
[i
];
4486 u32 data_low
, data_high
;
4489 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4491 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4493 vmx
->guest_msrs
[j
].index
= i
;
4494 vmx
->guest_msrs
[j
].data
= 0;
4495 vmx
->guest_msrs
[j
].mask
= -1ull;
4500 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4502 /* 22.2.1, 20.8.1 */
4503 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4505 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4506 set_cr4_guest_host_mask(vmx
);
4511 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4513 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4514 struct msr_data apic_base_msr
;
4516 vmx
->rmode
.vm86_active
= 0;
4518 vmx
->soft_vnmi_blocked
= 0;
4520 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4521 kvm_set_cr8(&vmx
->vcpu
, 0);
4522 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
;
4523 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4524 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4525 apic_base_msr
.host_initiated
= true;
4526 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4528 vmx_segment_cache_clear(vmx
);
4530 seg_setup(VCPU_SREG_CS
);
4531 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4532 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4534 seg_setup(VCPU_SREG_DS
);
4535 seg_setup(VCPU_SREG_ES
);
4536 seg_setup(VCPU_SREG_FS
);
4537 seg_setup(VCPU_SREG_GS
);
4538 seg_setup(VCPU_SREG_SS
);
4540 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4541 vmcs_writel(GUEST_TR_BASE
, 0);
4542 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4543 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4545 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4546 vmcs_writel(GUEST_LDTR_BASE
, 0);
4547 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4548 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4550 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4551 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4552 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4554 vmcs_writel(GUEST_RFLAGS
, 0x02);
4555 kvm_rip_write(vcpu
, 0xfff0);
4557 vmcs_writel(GUEST_GDTR_BASE
, 0);
4558 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4560 vmcs_writel(GUEST_IDTR_BASE
, 0);
4561 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4563 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4564 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4565 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4567 /* Special registers */
4568 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4572 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4574 if (cpu_has_vmx_tpr_shadow()) {
4575 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4576 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4577 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4578 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4579 vmcs_write32(TPR_THRESHOLD
, 0);
4582 kvm_vcpu_reload_apic_access_page(vcpu
);
4584 if (vmx_vm_has_apicv(vcpu
->kvm
))
4585 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4588 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4590 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4591 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4592 vmx_set_cr4(&vmx
->vcpu
, 0);
4593 vmx_set_efer(&vmx
->vcpu
, 0);
4594 vmx_fpu_activate(&vmx
->vcpu
);
4595 update_exception_bitmap(&vmx
->vcpu
);
4597 vpid_sync_context(vmx
);
4601 * In nested virtualization, check if L1 asked to exit on external interrupts.
4602 * For most existing hypervisors, this will always return true.
4604 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4606 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4607 PIN_BASED_EXT_INTR_MASK
;
4611 * In nested virtualization, check if L1 has set
4612 * VM_EXIT_ACK_INTR_ON_EXIT
4614 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4616 return get_vmcs12(vcpu
)->vm_exit_controls
&
4617 VM_EXIT_ACK_INTR_ON_EXIT
;
4620 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4622 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4623 PIN_BASED_NMI_EXITING
;
4626 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4628 u32 cpu_based_vm_exec_control
;
4630 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4631 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4632 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4635 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4637 u32 cpu_based_vm_exec_control
;
4639 if (!cpu_has_virtual_nmis() ||
4640 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4641 enable_irq_window(vcpu
);
4645 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4646 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4650 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4652 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4654 int irq
= vcpu
->arch
.interrupt
.nr
;
4656 trace_kvm_inj_virq(irq
);
4658 ++vcpu
->stat
.irq_injections
;
4659 if (vmx
->rmode
.vm86_active
) {
4661 if (vcpu
->arch
.interrupt
.soft
)
4662 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4663 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4664 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4667 intr
= irq
| INTR_INFO_VALID_MASK
;
4668 if (vcpu
->arch
.interrupt
.soft
) {
4669 intr
|= INTR_TYPE_SOFT_INTR
;
4670 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4671 vmx
->vcpu
.arch
.event_exit_inst_len
);
4673 intr
|= INTR_TYPE_EXT_INTR
;
4674 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4677 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4679 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4681 if (is_guest_mode(vcpu
))
4684 if (!cpu_has_virtual_nmis()) {
4686 * Tracking the NMI-blocked state in software is built upon
4687 * finding the next open IRQ window. This, in turn, depends on
4688 * well-behaving guests: They have to keep IRQs disabled at
4689 * least as long as the NMI handler runs. Otherwise we may
4690 * cause NMI nesting, maybe breaking the guest. But as this is
4691 * highly unlikely, we can live with the residual risk.
4693 vmx
->soft_vnmi_blocked
= 1;
4694 vmx
->vnmi_blocked_time
= 0;
4697 ++vcpu
->stat
.nmi_injections
;
4698 vmx
->nmi_known_unmasked
= false;
4699 if (vmx
->rmode
.vm86_active
) {
4700 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4701 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4704 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4705 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4708 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4710 if (!cpu_has_virtual_nmis())
4711 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4712 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4714 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4717 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4719 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4721 if (!cpu_has_virtual_nmis()) {
4722 if (vmx
->soft_vnmi_blocked
!= masked
) {
4723 vmx
->soft_vnmi_blocked
= masked
;
4724 vmx
->vnmi_blocked_time
= 0;
4727 vmx
->nmi_known_unmasked
= !masked
;
4729 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4730 GUEST_INTR_STATE_NMI
);
4732 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4733 GUEST_INTR_STATE_NMI
);
4737 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4739 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4742 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4745 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4746 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4747 | GUEST_INTR_STATE_NMI
));
4750 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4752 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4753 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4754 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4755 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4758 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4761 struct kvm_userspace_memory_region tss_mem
= {
4762 .slot
= TSS_PRIVATE_MEMSLOT
,
4763 .guest_phys_addr
= addr
,
4764 .memory_size
= PAGE_SIZE
* 3,
4768 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4771 kvm
->arch
.tss_addr
= addr
;
4772 return init_rmode_tss(kvm
);
4775 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4780 * Update instruction length as we may reinject the exception
4781 * from user space while in guest debugging mode.
4783 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4784 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4785 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4789 if (vcpu
->guest_debug
&
4790 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4807 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4808 int vec
, u32 err_code
)
4811 * Instruction with address size override prefix opcode 0x67
4812 * Cause the #SS fault with 0 error code in VM86 mode.
4814 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4815 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4816 if (vcpu
->arch
.halt_request
) {
4817 vcpu
->arch
.halt_request
= 0;
4818 return kvm_emulate_halt(vcpu
);
4826 * Forward all other exceptions that are valid in real mode.
4827 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4828 * the required debugging infrastructure rework.
4830 kvm_queue_exception(vcpu
, vec
);
4835 * Trigger machine check on the host. We assume all the MSRs are already set up
4836 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4837 * We pass a fake environment to the machine check handler because we want
4838 * the guest to be always treated like user space, no matter what context
4839 * it used internally.
4841 static void kvm_machine_check(void)
4843 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4844 struct pt_regs regs
= {
4845 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4846 .flags
= X86_EFLAGS_IF
,
4849 do_machine_check(®s
, 0);
4853 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4855 /* already handled by vcpu_run */
4859 static int handle_exception(struct kvm_vcpu
*vcpu
)
4861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4862 struct kvm_run
*kvm_run
= vcpu
->run
;
4863 u32 intr_info
, ex_no
, error_code
;
4864 unsigned long cr2
, rip
, dr6
;
4866 enum emulation_result er
;
4868 vect_info
= vmx
->idt_vectoring_info
;
4869 intr_info
= vmx
->exit_intr_info
;
4871 if (is_machine_check(intr_info
))
4872 return handle_machine_check(vcpu
);
4874 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4875 return 1; /* already handled by vmx_vcpu_run() */
4877 if (is_no_device(intr_info
)) {
4878 vmx_fpu_activate(vcpu
);
4882 if (is_invalid_opcode(intr_info
)) {
4883 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4884 if (er
!= EMULATE_DONE
)
4885 kvm_queue_exception(vcpu
, UD_VECTOR
);
4890 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4891 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4894 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4895 * MMIO, it is better to report an internal error.
4896 * See the comments in vmx_handle_exit.
4898 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4899 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4900 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4901 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4902 vcpu
->run
->internal
.ndata
= 2;
4903 vcpu
->run
->internal
.data
[0] = vect_info
;
4904 vcpu
->run
->internal
.data
[1] = intr_info
;
4908 if (is_page_fault(intr_info
)) {
4909 /* EPT won't cause page fault directly */
4911 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4912 trace_kvm_page_fault(cr2
, error_code
);
4914 if (kvm_event_needs_reinjection(vcpu
))
4915 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4916 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4919 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4921 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4922 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4926 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4927 if (!(vcpu
->guest_debug
&
4928 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4929 vcpu
->arch
.dr6
&= ~15;
4930 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
4931 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
4932 skip_emulated_instruction(vcpu
);
4934 kvm_queue_exception(vcpu
, DB_VECTOR
);
4937 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4938 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4942 * Update instruction length as we may reinject #BP from
4943 * user space while in guest debugging mode. Reading it for
4944 * #DB as well causes no harm, it is not used in that case.
4946 vmx
->vcpu
.arch
.event_exit_inst_len
=
4947 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4948 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4949 rip
= kvm_rip_read(vcpu
);
4950 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4951 kvm_run
->debug
.arch
.exception
= ex_no
;
4954 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4955 kvm_run
->ex
.exception
= ex_no
;
4956 kvm_run
->ex
.error_code
= error_code
;
4962 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4964 ++vcpu
->stat
.irq_exits
;
4968 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4970 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4974 static int handle_io(struct kvm_vcpu
*vcpu
)
4976 unsigned long exit_qualification
;
4977 int size
, in
, string
;
4980 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4981 string
= (exit_qualification
& 16) != 0;
4982 in
= (exit_qualification
& 8) != 0;
4984 ++vcpu
->stat
.io_exits
;
4987 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4989 port
= exit_qualification
>> 16;
4990 size
= (exit_qualification
& 7) + 1;
4991 skip_emulated_instruction(vcpu
);
4993 return kvm_fast_pio_out(vcpu
, size
, port
);
4997 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5000 * Patch in the VMCALL instruction:
5002 hypercall
[0] = 0x0f;
5003 hypercall
[1] = 0x01;
5004 hypercall
[2] = 0xc1;
5007 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
5009 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5011 if (nested_vmx_secondary_ctls_high
&
5012 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5013 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5014 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5015 return (val
& always_on
) == always_on
;
5018 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5019 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5021 if (is_guest_mode(vcpu
)) {
5022 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5023 unsigned long orig_val
= val
;
5026 * We get here when L2 changed cr0 in a way that did not change
5027 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5028 * but did change L0 shadowed bits. So we first calculate the
5029 * effective cr0 value that L1 would like to write into the
5030 * hardware. It consists of the L2-owned bits from the new
5031 * value combined with the L1-owned bits from L1's guest_cr0.
5033 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5034 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5036 if (!nested_cr0_valid(vmcs12
, val
))
5039 if (kvm_set_cr0(vcpu
, val
))
5041 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5044 if (to_vmx(vcpu
)->nested
.vmxon
&&
5045 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5047 return kvm_set_cr0(vcpu
, val
);
5051 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5053 if (is_guest_mode(vcpu
)) {
5054 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5055 unsigned long orig_val
= val
;
5057 /* analogously to handle_set_cr0 */
5058 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5059 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5060 if (kvm_set_cr4(vcpu
, val
))
5062 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5065 return kvm_set_cr4(vcpu
, val
);
5068 /* called to set cr0 as approriate for clts instruction exit. */
5069 static void handle_clts(struct kvm_vcpu
*vcpu
)
5071 if (is_guest_mode(vcpu
)) {
5073 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5074 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5075 * just pretend it's off (also in arch.cr0 for fpu_activate).
5077 vmcs_writel(CR0_READ_SHADOW
,
5078 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5079 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5081 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5084 static int handle_cr(struct kvm_vcpu
*vcpu
)
5086 unsigned long exit_qualification
, val
;
5091 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5092 cr
= exit_qualification
& 15;
5093 reg
= (exit_qualification
>> 8) & 15;
5094 switch ((exit_qualification
>> 4) & 3) {
5095 case 0: /* mov to cr */
5096 val
= kvm_register_readl(vcpu
, reg
);
5097 trace_kvm_cr_write(cr
, val
);
5100 err
= handle_set_cr0(vcpu
, val
);
5101 kvm_complete_insn_gp(vcpu
, err
);
5104 err
= kvm_set_cr3(vcpu
, val
);
5105 kvm_complete_insn_gp(vcpu
, err
);
5108 err
= handle_set_cr4(vcpu
, val
);
5109 kvm_complete_insn_gp(vcpu
, err
);
5112 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5114 err
= kvm_set_cr8(vcpu
, cr8
);
5115 kvm_complete_insn_gp(vcpu
, err
);
5116 if (irqchip_in_kernel(vcpu
->kvm
))
5118 if (cr8_prev
<= cr8
)
5120 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5127 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5128 skip_emulated_instruction(vcpu
);
5129 vmx_fpu_activate(vcpu
);
5131 case 1: /*mov from cr*/
5134 val
= kvm_read_cr3(vcpu
);
5135 kvm_register_write(vcpu
, reg
, val
);
5136 trace_kvm_cr_read(cr
, val
);
5137 skip_emulated_instruction(vcpu
);
5140 val
= kvm_get_cr8(vcpu
);
5141 kvm_register_write(vcpu
, reg
, val
);
5142 trace_kvm_cr_read(cr
, val
);
5143 skip_emulated_instruction(vcpu
);
5148 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5149 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5150 kvm_lmsw(vcpu
, val
);
5152 skip_emulated_instruction(vcpu
);
5157 vcpu
->run
->exit_reason
= 0;
5158 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5159 (int)(exit_qualification
>> 4) & 3, cr
);
5163 static int handle_dr(struct kvm_vcpu
*vcpu
)
5165 unsigned long exit_qualification
;
5168 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5169 if (!kvm_require_cpl(vcpu
, 0))
5171 dr
= vmcs_readl(GUEST_DR7
);
5174 * As the vm-exit takes precedence over the debug trap, we
5175 * need to emulate the latter, either for the host or the
5176 * guest debugging itself.
5178 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5179 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5180 vcpu
->run
->debug
.arch
.dr7
= dr
;
5181 vcpu
->run
->debug
.arch
.pc
=
5182 vmcs_readl(GUEST_CS_BASE
) +
5183 vmcs_readl(GUEST_RIP
);
5184 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5185 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5188 vcpu
->arch
.dr7
&= ~DR7_GD
;
5189 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5190 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5191 kvm_queue_exception(vcpu
, DB_VECTOR
);
5196 if (vcpu
->guest_debug
== 0) {
5197 u32 cpu_based_vm_exec_control
;
5199 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5200 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5201 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5204 * No more DR vmexits; force a reload of the debug registers
5205 * and reenter on this instruction. The next vmexit will
5206 * retrieve the full state of the debug registers.
5208 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5212 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5213 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5214 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5215 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5218 if (kvm_get_dr(vcpu
, dr
, &val
))
5220 kvm_register_write(vcpu
, reg
, val
);
5222 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5225 skip_emulated_instruction(vcpu
);
5229 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5231 return vcpu
->arch
.dr6
;
5234 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5238 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5240 u32 cpu_based_vm_exec_control
;
5242 get_debugreg(vcpu
->arch
.db
[0], 0);
5243 get_debugreg(vcpu
->arch
.db
[1], 1);
5244 get_debugreg(vcpu
->arch
.db
[2], 2);
5245 get_debugreg(vcpu
->arch
.db
[3], 3);
5246 get_debugreg(vcpu
->arch
.dr6
, 6);
5247 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5249 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5251 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5252 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5253 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5256 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5258 vmcs_writel(GUEST_DR7
, val
);
5261 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5263 kvm_emulate_cpuid(vcpu
);
5267 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5269 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5272 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5273 trace_kvm_msr_read_ex(ecx
);
5274 kvm_inject_gp(vcpu
, 0);
5278 trace_kvm_msr_read(ecx
, data
);
5280 /* FIXME: handling of bits 32:63 of rax, rdx */
5281 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5282 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5283 skip_emulated_instruction(vcpu
);
5287 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5289 struct msr_data msr
;
5290 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5291 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5292 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5296 msr
.host_initiated
= false;
5297 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5298 trace_kvm_msr_write_ex(ecx
, data
);
5299 kvm_inject_gp(vcpu
, 0);
5303 trace_kvm_msr_write(ecx
, data
);
5304 skip_emulated_instruction(vcpu
);
5308 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5310 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5314 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5316 u32 cpu_based_vm_exec_control
;
5318 /* clear pending irq */
5319 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5320 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5321 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5323 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5325 ++vcpu
->stat
.irq_window_exits
;
5328 * If the user space waits to inject interrupts, exit as soon as
5331 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5332 vcpu
->run
->request_interrupt_window
&&
5333 !kvm_cpu_has_interrupt(vcpu
)) {
5334 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5340 static int handle_halt(struct kvm_vcpu
*vcpu
)
5342 skip_emulated_instruction(vcpu
);
5343 return kvm_emulate_halt(vcpu
);
5346 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5348 skip_emulated_instruction(vcpu
);
5349 kvm_emulate_hypercall(vcpu
);
5353 static int handle_invd(struct kvm_vcpu
*vcpu
)
5355 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5358 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5360 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5362 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5363 skip_emulated_instruction(vcpu
);
5367 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5371 err
= kvm_rdpmc(vcpu
);
5372 kvm_complete_insn_gp(vcpu
, err
);
5377 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5379 skip_emulated_instruction(vcpu
);
5380 kvm_emulate_wbinvd(vcpu
);
5384 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5386 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5387 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5389 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5390 skip_emulated_instruction(vcpu
);
5394 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5396 if (likely(fasteoi
)) {
5397 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5398 int access_type
, offset
;
5400 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5401 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5403 * Sane guest uses MOV to write EOI, with written value
5404 * not cared. So make a short-circuit here by avoiding
5405 * heavy instruction emulation.
5407 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5408 (offset
== APIC_EOI
)) {
5409 kvm_lapic_set_eoi(vcpu
);
5410 skip_emulated_instruction(vcpu
);
5414 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5417 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5419 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5420 int vector
= exit_qualification
& 0xff;
5422 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5423 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5427 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5429 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5430 u32 offset
= exit_qualification
& 0xfff;
5432 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5433 kvm_apic_write_nodecode(vcpu
, offset
);
5437 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5439 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5440 unsigned long exit_qualification
;
5441 bool has_error_code
= false;
5444 int reason
, type
, idt_v
, idt_index
;
5446 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5447 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5448 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5450 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5452 reason
= (u32
)exit_qualification
>> 30;
5453 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5455 case INTR_TYPE_NMI_INTR
:
5456 vcpu
->arch
.nmi_injected
= false;
5457 vmx_set_nmi_mask(vcpu
, true);
5459 case INTR_TYPE_EXT_INTR
:
5460 case INTR_TYPE_SOFT_INTR
:
5461 kvm_clear_interrupt_queue(vcpu
);
5463 case INTR_TYPE_HARD_EXCEPTION
:
5464 if (vmx
->idt_vectoring_info
&
5465 VECTORING_INFO_DELIVER_CODE_MASK
) {
5466 has_error_code
= true;
5468 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5471 case INTR_TYPE_SOFT_EXCEPTION
:
5472 kvm_clear_exception_queue(vcpu
);
5478 tss_selector
= exit_qualification
;
5480 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5481 type
!= INTR_TYPE_EXT_INTR
&&
5482 type
!= INTR_TYPE_NMI_INTR
))
5483 skip_emulated_instruction(vcpu
);
5485 if (kvm_task_switch(vcpu
, tss_selector
,
5486 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5487 has_error_code
, error_code
) == EMULATE_FAIL
) {
5488 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5489 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5490 vcpu
->run
->internal
.ndata
= 0;
5494 /* clear all local breakpoint enable flags */
5495 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x55);
5498 * TODO: What about debug traps on tss switch?
5499 * Are we supposed to inject them and update dr6?
5505 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5507 unsigned long exit_qualification
;
5512 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5514 gla_validity
= (exit_qualification
>> 7) & 0x3;
5515 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5516 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5517 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5518 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5519 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5520 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5521 (long unsigned int)exit_qualification
);
5522 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5523 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5528 * EPT violation happened while executing iret from NMI,
5529 * "blocked by NMI" bit has to be set before next VM entry.
5530 * There are errata that may cause this bit to not be set:
5533 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5534 cpu_has_virtual_nmis() &&
5535 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5536 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5538 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5539 trace_kvm_page_fault(gpa
, exit_qualification
);
5541 /* It is a write fault? */
5542 error_code
= exit_qualification
& (1U << 1);
5543 /* It is a fetch fault? */
5544 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5545 /* ept page table is present? */
5546 error_code
|= (exit_qualification
>> 3) & 0x1;
5548 vcpu
->arch
.exit_qualification
= exit_qualification
;
5550 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5553 static u64
ept_rsvd_mask(u64 spte
, int level
)
5558 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5559 mask
|= (1ULL << i
);
5562 /* bits 7:3 reserved */
5564 else if (spte
& (1ULL << 7))
5566 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5567 * level == 1 if the hypervisor is using the ignored bit 7.
5569 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5571 /* bits 6:3 reserved */
5577 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5580 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5582 /* 010b (write-only) */
5583 WARN_ON((spte
& 0x7) == 0x2);
5585 /* 110b (write/execute) */
5586 WARN_ON((spte
& 0x7) == 0x6);
5588 /* 100b (execute-only) and value not supported by logical processor */
5589 if (!cpu_has_vmx_ept_execute_only())
5590 WARN_ON((spte
& 0x7) == 0x4);
5594 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5596 if (rsvd_bits
!= 0) {
5597 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5598 __func__
, rsvd_bits
);
5602 /* bits 5:3 are _not_ reserved for large page or leaf page */
5603 if ((rsvd_bits
& 0x38) == 0) {
5604 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5606 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5607 ept_mem_type
== 7) {
5608 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5609 __func__
, ept_mem_type
);
5616 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5619 int nr_sptes
, i
, ret
;
5622 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5623 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5624 skip_emulated_instruction(vcpu
);
5628 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5629 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5630 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5633 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5634 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5636 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5639 /* It is the real ept misconfig */
5640 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5641 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5643 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5645 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5646 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5648 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5649 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5654 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5656 u32 cpu_based_vm_exec_control
;
5658 /* clear pending NMI */
5659 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5660 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5661 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5662 ++vcpu
->stat
.nmi_window_exits
;
5663 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5668 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5670 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5671 enum emulation_result err
= EMULATE_DONE
;
5674 bool intr_window_requested
;
5675 unsigned count
= 130;
5677 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5678 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5680 while (vmx
->emulation_required
&& count
-- != 0) {
5681 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5682 return handle_interrupt_window(&vmx
->vcpu
);
5684 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5687 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5689 if (err
== EMULATE_USER_EXIT
) {
5690 ++vcpu
->stat
.mmio_exits
;
5695 if (err
!= EMULATE_DONE
) {
5696 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5697 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5698 vcpu
->run
->internal
.ndata
= 0;
5702 if (vcpu
->arch
.halt_request
) {
5703 vcpu
->arch
.halt_request
= 0;
5704 ret
= kvm_emulate_halt(vcpu
);
5708 if (signal_pending(current
))
5718 static int __grow_ple_window(int val
)
5720 if (ple_window_grow
< 1)
5723 val
= min(val
, ple_window_actual_max
);
5725 if (ple_window_grow
< ple_window
)
5726 val
*= ple_window_grow
;
5728 val
+= ple_window_grow
;
5733 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5738 if (modifier
< ple_window
)
5743 return max(val
, minimum
);
5746 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5748 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5749 int old
= vmx
->ple_window
;
5751 vmx
->ple_window
= __grow_ple_window(old
);
5753 if (vmx
->ple_window
!= old
)
5754 vmx
->ple_window_dirty
= true;
5756 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5759 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5761 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5762 int old
= vmx
->ple_window
;
5764 vmx
->ple_window
= __shrink_ple_window(old
,
5765 ple_window_shrink
, ple_window
);
5767 if (vmx
->ple_window
!= old
)
5768 vmx
->ple_window_dirty
= true;
5770 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5774 * ple_window_actual_max is computed to be one grow_ple_window() below
5775 * ple_window_max. (See __grow_ple_window for the reason.)
5776 * This prevents overflows, because ple_window_max is int.
5777 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5779 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5781 static void update_ple_window_actual_max(void)
5783 ple_window_actual_max
=
5784 __shrink_ple_window(max(ple_window_max
, ple_window
),
5785 ple_window_grow
, INT_MIN
);
5789 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5790 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5792 static int handle_pause(struct kvm_vcpu
*vcpu
)
5795 grow_ple_window(vcpu
);
5797 skip_emulated_instruction(vcpu
);
5798 kvm_vcpu_on_spin(vcpu
);
5803 static int handle_nop(struct kvm_vcpu
*vcpu
)
5805 skip_emulated_instruction(vcpu
);
5809 static int handle_mwait(struct kvm_vcpu
*vcpu
)
5811 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
5812 return handle_nop(vcpu
);
5815 static int handle_monitor(struct kvm_vcpu
*vcpu
)
5817 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
5818 return handle_nop(vcpu
);
5822 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5823 * We could reuse a single VMCS for all the L2 guests, but we also want the
5824 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5825 * allows keeping them loaded on the processor, and in the future will allow
5826 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5827 * every entry if they never change.
5828 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5829 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5831 * The following functions allocate and free a vmcs02 in this pool.
5834 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5835 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5837 struct vmcs02_list
*item
;
5838 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5839 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5840 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5841 return &item
->vmcs02
;
5844 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5845 /* Recycle the least recently used VMCS. */
5846 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5847 struct vmcs02_list
, list
);
5848 item
->vmptr
= vmx
->nested
.current_vmptr
;
5849 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5850 return &item
->vmcs02
;
5853 /* Create a new VMCS */
5854 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5857 item
->vmcs02
.vmcs
= alloc_vmcs();
5858 if (!item
->vmcs02
.vmcs
) {
5862 loaded_vmcs_init(&item
->vmcs02
);
5863 item
->vmptr
= vmx
->nested
.current_vmptr
;
5864 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5865 vmx
->nested
.vmcs02_num
++;
5866 return &item
->vmcs02
;
5869 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5870 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5872 struct vmcs02_list
*item
;
5873 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5874 if (item
->vmptr
== vmptr
) {
5875 free_loaded_vmcs(&item
->vmcs02
);
5876 list_del(&item
->list
);
5878 vmx
->nested
.vmcs02_num
--;
5884 * Free all VMCSs saved for this vcpu, except the one pointed by
5885 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5886 * must be &vmx->vmcs01.
5888 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5890 struct vmcs02_list
*item
, *n
;
5892 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
5893 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5895 * Something will leak if the above WARN triggers. Better than
5898 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
5901 free_loaded_vmcs(&item
->vmcs02
);
5902 list_del(&item
->list
);
5904 vmx
->nested
.vmcs02_num
--;
5909 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5910 * set the success or error code of an emulated VMX instruction, as specified
5911 * by Vol 2B, VMX Instruction Reference, "Conventions".
5913 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5915 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5916 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5917 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5920 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5922 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5923 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5924 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5928 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5929 u32 vm_instruction_error
)
5931 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5933 * failValid writes the error number to the current VMCS, which
5934 * can't be done there isn't a current VMCS.
5936 nested_vmx_failInvalid(vcpu
);
5939 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5940 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5941 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5943 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5945 * We don't need to force a shadow sync because
5946 * VM_INSTRUCTION_ERROR is not shadowed
5950 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
5952 struct vcpu_vmx
*vmx
=
5953 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
5955 vmx
->nested
.preemption_timer_expired
= true;
5956 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5957 kvm_vcpu_kick(&vmx
->vcpu
);
5959 return HRTIMER_NORESTART
;
5963 * Decode the memory-address operand of a vmx instruction, as recorded on an
5964 * exit caused by such an instruction (run by a guest hypervisor).
5965 * On success, returns 0. When the operand is invalid, returns 1 and throws
5968 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5969 unsigned long exit_qualification
,
5970 u32 vmx_instruction_info
, gva_t
*ret
)
5973 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5974 * Execution", on an exit, vmx_instruction_info holds most of the
5975 * addressing components of the operand. Only the displacement part
5976 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5977 * For how an actual address is calculated from all these components,
5978 * refer to Vol. 1, "Operand Addressing".
5980 int scaling
= vmx_instruction_info
& 3;
5981 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5982 bool is_reg
= vmx_instruction_info
& (1u << 10);
5983 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5984 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5985 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5986 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5987 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5990 kvm_queue_exception(vcpu
, UD_VECTOR
);
5994 /* Addr = segment_base + offset */
5995 /* offset = base + [index * scale] + displacement */
5996 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5998 *ret
+= kvm_register_read(vcpu
, base_reg
);
6000 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6001 *ret
+= exit_qualification
; /* holds the displacement */
6003 if (addr_size
== 1) /* 32 bit */
6007 * TODO: throw #GP (and return 1) in various cases that the VM*
6008 * instructions require it - e.g., offset beyond segment limit,
6009 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6010 * address, and so on. Currently these are not checked.
6016 * This function performs the various checks including
6017 * - if it's 4KB aligned
6018 * - No bits beyond the physical address width are set
6019 * - Returns 0 on success or else 1
6020 * (Intel SDM Section 30.3)
6022 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6027 struct x86_exception e
;
6029 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6030 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6032 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6033 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6036 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6037 sizeof(vmptr
), &e
)) {
6038 kvm_inject_page_fault(vcpu
, &e
);
6042 switch (exit_reason
) {
6043 case EXIT_REASON_VMON
:
6046 * The first 4 bytes of VMXON region contain the supported
6047 * VMCS revision identifier
6049 * Note - IA32_VMX_BASIC[48] will never be 1
6050 * for the nested case;
6051 * which replaces physical address width with 32
6054 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6055 nested_vmx_failInvalid(vcpu
);
6056 skip_emulated_instruction(vcpu
);
6060 page
= nested_get_page(vcpu
, vmptr
);
6062 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6063 nested_vmx_failInvalid(vcpu
);
6065 skip_emulated_instruction(vcpu
);
6069 vmx
->nested
.vmxon_ptr
= vmptr
;
6071 case EXIT_REASON_VMCLEAR
:
6072 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6073 nested_vmx_failValid(vcpu
,
6074 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6075 skip_emulated_instruction(vcpu
);
6079 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6080 nested_vmx_failValid(vcpu
,
6081 VMXERR_VMCLEAR_VMXON_POINTER
);
6082 skip_emulated_instruction(vcpu
);
6086 case EXIT_REASON_VMPTRLD
:
6087 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6088 nested_vmx_failValid(vcpu
,
6089 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6090 skip_emulated_instruction(vcpu
);
6094 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6095 nested_vmx_failValid(vcpu
,
6096 VMXERR_VMCLEAR_VMXON_POINTER
);
6097 skip_emulated_instruction(vcpu
);
6102 return 1; /* shouldn't happen */
6111 * Emulate the VMXON instruction.
6112 * Currently, we just remember that VMX is active, and do not save or even
6113 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6114 * do not currently need to store anything in that guest-allocated memory
6115 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6116 * argument is different from the VMXON pointer (which the spec says they do).
6118 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6120 struct kvm_segment cs
;
6121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6122 struct vmcs
*shadow_vmcs
;
6123 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6124 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6126 /* The Intel VMX Instruction Reference lists a bunch of bits that
6127 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6128 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6129 * Otherwise, we should fail with #UD. We test these now:
6131 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6132 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6133 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6134 kvm_queue_exception(vcpu
, UD_VECTOR
);
6138 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6139 if (is_long_mode(vcpu
) && !cs
.l
) {
6140 kvm_queue_exception(vcpu
, UD_VECTOR
);
6144 if (vmx_get_cpl(vcpu
)) {
6145 kvm_inject_gp(vcpu
, 0);
6149 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6152 if (vmx
->nested
.vmxon
) {
6153 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6154 skip_emulated_instruction(vcpu
);
6158 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6159 != VMXON_NEEDED_FEATURES
) {
6160 kvm_inject_gp(vcpu
, 0);
6164 if (enable_shadow_vmcs
) {
6165 shadow_vmcs
= alloc_vmcs();
6168 /* mark vmcs as shadow */
6169 shadow_vmcs
->revision_id
|= (1u << 31);
6170 /* init shadow vmcs */
6171 vmcs_clear(shadow_vmcs
);
6172 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6175 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6176 vmx
->nested
.vmcs02_num
= 0;
6178 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6180 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6182 vmx
->nested
.vmxon
= true;
6184 skip_emulated_instruction(vcpu
);
6185 nested_vmx_succeed(vcpu
);
6190 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6191 * for running VMX instructions (except VMXON, whose prerequisites are
6192 * slightly different). It also specifies what exception to inject otherwise.
6194 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6196 struct kvm_segment cs
;
6197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6199 if (!vmx
->nested
.vmxon
) {
6200 kvm_queue_exception(vcpu
, UD_VECTOR
);
6204 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6205 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6206 (is_long_mode(vcpu
) && !cs
.l
)) {
6207 kvm_queue_exception(vcpu
, UD_VECTOR
);
6211 if (vmx_get_cpl(vcpu
)) {
6212 kvm_inject_gp(vcpu
, 0);
6219 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6222 if (vmx
->nested
.current_vmptr
== -1ull)
6225 /* current_vmptr and current_vmcs12 are always set/reset together */
6226 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6229 if (enable_shadow_vmcs
) {
6230 /* copy to memory all shadowed fields in case
6231 they were modified */
6232 copy_shadow_to_vmcs12(vmx
);
6233 vmx
->nested
.sync_shadow_vmcs
= false;
6234 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6235 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6236 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6237 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6239 kunmap(vmx
->nested
.current_vmcs12_page
);
6240 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6241 vmx
->nested
.current_vmptr
= -1ull;
6242 vmx
->nested
.current_vmcs12
= NULL
;
6246 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6247 * just stops using VMX.
6249 static void free_nested(struct vcpu_vmx
*vmx
)
6251 if (!vmx
->nested
.vmxon
)
6254 vmx
->nested
.vmxon
= false;
6255 nested_release_vmcs12(vmx
);
6256 if (enable_shadow_vmcs
)
6257 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6258 /* Unpin physical memory we referred to in current vmcs02 */
6259 if (vmx
->nested
.apic_access_page
) {
6260 nested_release_page(vmx
->nested
.apic_access_page
);
6261 vmx
->nested
.apic_access_page
= NULL
;
6263 if (vmx
->nested
.virtual_apic_page
) {
6264 nested_release_page(vmx
->nested
.virtual_apic_page
);
6265 vmx
->nested
.virtual_apic_page
= NULL
;
6268 nested_free_all_saved_vmcss(vmx
);
6271 /* Emulate the VMXOFF instruction */
6272 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6274 if (!nested_vmx_check_permission(vcpu
))
6276 free_nested(to_vmx(vcpu
));
6277 skip_emulated_instruction(vcpu
);
6278 nested_vmx_succeed(vcpu
);
6282 /* Emulate the VMCLEAR instruction */
6283 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6287 struct vmcs12
*vmcs12
;
6290 if (!nested_vmx_check_permission(vcpu
))
6293 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6296 if (vmptr
== vmx
->nested
.current_vmptr
)
6297 nested_release_vmcs12(vmx
);
6299 page
= nested_get_page(vcpu
, vmptr
);
6302 * For accurate processor emulation, VMCLEAR beyond available
6303 * physical memory should do nothing at all. However, it is
6304 * possible that a nested vmx bug, not a guest hypervisor bug,
6305 * resulted in this case, so let's shut down before doing any
6308 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6311 vmcs12
= kmap(page
);
6312 vmcs12
->launch_state
= 0;
6314 nested_release_page(page
);
6316 nested_free_vmcs02(vmx
, vmptr
);
6318 skip_emulated_instruction(vcpu
);
6319 nested_vmx_succeed(vcpu
);
6323 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6325 /* Emulate the VMLAUNCH instruction */
6326 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6328 return nested_vmx_run(vcpu
, true);
6331 /* Emulate the VMRESUME instruction */
6332 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6335 return nested_vmx_run(vcpu
, false);
6338 enum vmcs_field_type
{
6339 VMCS_FIELD_TYPE_U16
= 0,
6340 VMCS_FIELD_TYPE_U64
= 1,
6341 VMCS_FIELD_TYPE_U32
= 2,
6342 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6345 static inline int vmcs_field_type(unsigned long field
)
6347 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6348 return VMCS_FIELD_TYPE_U32
;
6349 return (field
>> 13) & 0x3 ;
6352 static inline int vmcs_field_readonly(unsigned long field
)
6354 return (((field
>> 10) & 0x3) == 1);
6358 * Read a vmcs12 field. Since these can have varying lengths and we return
6359 * one type, we chose the biggest type (u64) and zero-extend the return value
6360 * to that size. Note that the caller, handle_vmread, might need to use only
6361 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6362 * 64-bit fields are to be returned).
6364 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6365 unsigned long field
, u64
*ret
)
6367 short offset
= vmcs_field_to_offset(field
);
6373 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6375 switch (vmcs_field_type(field
)) {
6376 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6377 *ret
= *((natural_width
*)p
);
6379 case VMCS_FIELD_TYPE_U16
:
6382 case VMCS_FIELD_TYPE_U32
:
6385 case VMCS_FIELD_TYPE_U64
:
6389 return 0; /* can never happen. */
6394 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6395 unsigned long field
, u64 field_value
){
6396 short offset
= vmcs_field_to_offset(field
);
6397 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6401 switch (vmcs_field_type(field
)) {
6402 case VMCS_FIELD_TYPE_U16
:
6403 *(u16
*)p
= field_value
;
6405 case VMCS_FIELD_TYPE_U32
:
6406 *(u32
*)p
= field_value
;
6408 case VMCS_FIELD_TYPE_U64
:
6409 *(u64
*)p
= field_value
;
6411 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6412 *(natural_width
*)p
= field_value
;
6415 return false; /* can never happen. */
6420 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6423 unsigned long field
;
6425 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6426 const unsigned long *fields
= shadow_read_write_fields
;
6427 const int num_fields
= max_shadow_read_write_fields
;
6429 vmcs_load(shadow_vmcs
);
6431 for (i
= 0; i
< num_fields
; i
++) {
6433 switch (vmcs_field_type(field
)) {
6434 case VMCS_FIELD_TYPE_U16
:
6435 field_value
= vmcs_read16(field
);
6437 case VMCS_FIELD_TYPE_U32
:
6438 field_value
= vmcs_read32(field
);
6440 case VMCS_FIELD_TYPE_U64
:
6441 field_value
= vmcs_read64(field
);
6443 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6444 field_value
= vmcs_readl(field
);
6447 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6450 vmcs_clear(shadow_vmcs
);
6451 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6454 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6456 const unsigned long *fields
[] = {
6457 shadow_read_write_fields
,
6458 shadow_read_only_fields
6460 const int max_fields
[] = {
6461 max_shadow_read_write_fields
,
6462 max_shadow_read_only_fields
6465 unsigned long field
;
6466 u64 field_value
= 0;
6467 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6469 vmcs_load(shadow_vmcs
);
6471 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6472 for (i
= 0; i
< max_fields
[q
]; i
++) {
6473 field
= fields
[q
][i
];
6474 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6476 switch (vmcs_field_type(field
)) {
6477 case VMCS_FIELD_TYPE_U16
:
6478 vmcs_write16(field
, (u16
)field_value
);
6480 case VMCS_FIELD_TYPE_U32
:
6481 vmcs_write32(field
, (u32
)field_value
);
6483 case VMCS_FIELD_TYPE_U64
:
6484 vmcs_write64(field
, (u64
)field_value
);
6486 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6487 vmcs_writel(field
, (long)field_value
);
6493 vmcs_clear(shadow_vmcs
);
6494 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6498 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6499 * used before) all generate the same failure when it is missing.
6501 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6503 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6504 if (vmx
->nested
.current_vmptr
== -1ull) {
6505 nested_vmx_failInvalid(vcpu
);
6506 skip_emulated_instruction(vcpu
);
6512 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6514 unsigned long field
;
6516 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6517 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6520 if (!nested_vmx_check_permission(vcpu
) ||
6521 !nested_vmx_check_vmcs12(vcpu
))
6524 /* Decode instruction info and find the field to read */
6525 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6526 /* Read the field, zero-extended to a u64 field_value */
6527 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6528 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6529 skip_emulated_instruction(vcpu
);
6533 * Now copy part of this value to register or memory, as requested.
6534 * Note that the number of bits actually copied is 32 or 64 depending
6535 * on the guest's mode (32 or 64 bit), not on the given field's length.
6537 if (vmx_instruction_info
& (1u << 10)) {
6538 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6541 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6542 vmx_instruction_info
, &gva
))
6544 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6545 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6546 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6549 nested_vmx_succeed(vcpu
);
6550 skip_emulated_instruction(vcpu
);
6555 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6557 unsigned long field
;
6559 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6560 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6561 /* The value to write might be 32 or 64 bits, depending on L1's long
6562 * mode, and eventually we need to write that into a field of several
6563 * possible lengths. The code below first zero-extends the value to 64
6564 * bit (field_value), and then copies only the approriate number of
6565 * bits into the vmcs12 field.
6567 u64 field_value
= 0;
6568 struct x86_exception e
;
6570 if (!nested_vmx_check_permission(vcpu
) ||
6571 !nested_vmx_check_vmcs12(vcpu
))
6574 if (vmx_instruction_info
& (1u << 10))
6575 field_value
= kvm_register_readl(vcpu
,
6576 (((vmx_instruction_info
) >> 3) & 0xf));
6578 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6579 vmx_instruction_info
, &gva
))
6581 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6582 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
6583 kvm_inject_page_fault(vcpu
, &e
);
6589 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6590 if (vmcs_field_readonly(field
)) {
6591 nested_vmx_failValid(vcpu
,
6592 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6593 skip_emulated_instruction(vcpu
);
6597 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6598 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6599 skip_emulated_instruction(vcpu
);
6603 nested_vmx_succeed(vcpu
);
6604 skip_emulated_instruction(vcpu
);
6608 /* Emulate the VMPTRLD instruction */
6609 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6611 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6615 if (!nested_vmx_check_permission(vcpu
))
6618 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6621 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6622 struct vmcs12
*new_vmcs12
;
6624 page
= nested_get_page(vcpu
, vmptr
);
6626 nested_vmx_failInvalid(vcpu
);
6627 skip_emulated_instruction(vcpu
);
6630 new_vmcs12
= kmap(page
);
6631 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6633 nested_release_page_clean(page
);
6634 nested_vmx_failValid(vcpu
,
6635 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6636 skip_emulated_instruction(vcpu
);
6640 nested_release_vmcs12(vmx
);
6641 vmx
->nested
.current_vmptr
= vmptr
;
6642 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6643 vmx
->nested
.current_vmcs12_page
= page
;
6644 if (enable_shadow_vmcs
) {
6645 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6646 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6647 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6648 vmcs_write64(VMCS_LINK_POINTER
,
6649 __pa(vmx
->nested
.current_shadow_vmcs
));
6650 vmx
->nested
.sync_shadow_vmcs
= true;
6654 nested_vmx_succeed(vcpu
);
6655 skip_emulated_instruction(vcpu
);
6659 /* Emulate the VMPTRST instruction */
6660 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6662 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6663 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6665 struct x86_exception e
;
6667 if (!nested_vmx_check_permission(vcpu
))
6670 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6671 vmx_instruction_info
, &vmcs_gva
))
6673 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6674 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6675 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6677 kvm_inject_page_fault(vcpu
, &e
);
6680 nested_vmx_succeed(vcpu
);
6681 skip_emulated_instruction(vcpu
);
6685 /* Emulate the INVEPT instruction */
6686 static int handle_invept(struct kvm_vcpu
*vcpu
)
6688 u32 vmx_instruction_info
, types
;
6691 struct x86_exception e
;
6696 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6697 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6698 kvm_queue_exception(vcpu
, UD_VECTOR
);
6702 if (!nested_vmx_check_permission(vcpu
))
6705 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6706 kvm_queue_exception(vcpu
, UD_VECTOR
);
6710 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6711 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6713 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6715 if (!(types
& (1UL << type
))) {
6716 nested_vmx_failValid(vcpu
,
6717 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6721 /* According to the Intel VMX instruction reference, the memory
6722 * operand is read even if it isn't needed (e.g., for type==global)
6724 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6725 vmx_instruction_info
, &gva
))
6727 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6728 sizeof(operand
), &e
)) {
6729 kvm_inject_page_fault(vcpu
, &e
);
6734 case VMX_EPT_EXTENT_GLOBAL
:
6735 kvm_mmu_sync_roots(vcpu
);
6736 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
6737 nested_vmx_succeed(vcpu
);
6740 /* Trap single context invalidation invept calls */
6745 skip_emulated_instruction(vcpu
);
6749 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
6751 kvm_queue_exception(vcpu
, UD_VECTOR
);
6756 * The exit handlers return 1 if the exit was handled fully and guest execution
6757 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6758 * to be done to userspace and return 0.
6760 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6761 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6762 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6763 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6764 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6765 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6766 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6767 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6768 [EXIT_REASON_CPUID
] = handle_cpuid
,
6769 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6770 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6771 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6772 [EXIT_REASON_HLT
] = handle_halt
,
6773 [EXIT_REASON_INVD
] = handle_invd
,
6774 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6775 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6776 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6777 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6778 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6779 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6780 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6781 [EXIT_REASON_VMREAD
] = handle_vmread
,
6782 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6783 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6784 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6785 [EXIT_REASON_VMON
] = handle_vmon
,
6786 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6787 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6788 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6789 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6790 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6791 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6792 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6793 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6794 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6795 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6796 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6797 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
6798 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
6799 [EXIT_REASON_INVEPT
] = handle_invept
,
6800 [EXIT_REASON_INVVPID
] = handle_invvpid
,
6803 static const int kvm_vmx_max_exit_handlers
=
6804 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6806 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6807 struct vmcs12
*vmcs12
)
6809 unsigned long exit_qualification
;
6810 gpa_t bitmap
, last_bitmap
;
6815 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6816 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6818 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6820 port
= exit_qualification
>> 16;
6821 size
= (exit_qualification
& 7) + 1;
6823 last_bitmap
= (gpa_t
)-1;
6828 bitmap
= vmcs12
->io_bitmap_a
;
6829 else if (port
< 0x10000)
6830 bitmap
= vmcs12
->io_bitmap_b
;
6833 bitmap
+= (port
& 0x7fff) / 8;
6835 if (last_bitmap
!= bitmap
)
6836 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6838 if (b
& (1 << (port
& 7)))
6843 last_bitmap
= bitmap
;
6850 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6851 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6852 * disinterest in the current event (read or write a specific MSR) by using an
6853 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6855 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6856 struct vmcs12
*vmcs12
, u32 exit_reason
)
6858 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6861 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6865 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6866 * for the four combinations of read/write and low/high MSR numbers.
6867 * First we need to figure out which of the four to use:
6869 bitmap
= vmcs12
->msr_bitmap
;
6870 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6872 if (msr_index
>= 0xc0000000) {
6873 msr_index
-= 0xc0000000;
6877 /* Then read the msr_index'th bit from this bitmap: */
6878 if (msr_index
< 1024*8) {
6880 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6882 return 1 & (b
>> (msr_index
& 7));
6884 return 1; /* let L1 handle the wrong parameter */
6888 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6889 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6890 * intercept (via guest_host_mask etc.) the current event.
6892 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6893 struct vmcs12
*vmcs12
)
6895 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6896 int cr
= exit_qualification
& 15;
6897 int reg
= (exit_qualification
>> 8) & 15;
6898 unsigned long val
= kvm_register_readl(vcpu
, reg
);
6900 switch ((exit_qualification
>> 4) & 3) {
6901 case 0: /* mov to cr */
6904 if (vmcs12
->cr0_guest_host_mask
&
6905 (val
^ vmcs12
->cr0_read_shadow
))
6909 if ((vmcs12
->cr3_target_count
>= 1 &&
6910 vmcs12
->cr3_target_value0
== val
) ||
6911 (vmcs12
->cr3_target_count
>= 2 &&
6912 vmcs12
->cr3_target_value1
== val
) ||
6913 (vmcs12
->cr3_target_count
>= 3 &&
6914 vmcs12
->cr3_target_value2
== val
) ||
6915 (vmcs12
->cr3_target_count
>= 4 &&
6916 vmcs12
->cr3_target_value3
== val
))
6918 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6922 if (vmcs12
->cr4_guest_host_mask
&
6923 (vmcs12
->cr4_read_shadow
^ val
))
6927 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6933 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6934 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6937 case 1: /* mov from cr */
6940 if (vmcs12
->cpu_based_vm_exec_control
&
6941 CPU_BASED_CR3_STORE_EXITING
)
6945 if (vmcs12
->cpu_based_vm_exec_control
&
6946 CPU_BASED_CR8_STORE_EXITING
)
6953 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6954 * cr0. Other attempted changes are ignored, with no exit.
6956 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6957 (val
^ vmcs12
->cr0_read_shadow
))
6959 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6960 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6969 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6970 * should handle it ourselves in L0 (and then continue L2). Only call this
6971 * when in is_guest_mode (L2).
6973 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6975 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6976 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6977 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6978 u32 exit_reason
= vmx
->exit_reason
;
6980 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6981 vmcs_readl(EXIT_QUALIFICATION
),
6982 vmx
->idt_vectoring_info
,
6984 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6987 if (vmx
->nested
.nested_run_pending
)
6990 if (unlikely(vmx
->fail
)) {
6991 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6992 vmcs_read32(VM_INSTRUCTION_ERROR
));
6996 switch (exit_reason
) {
6997 case EXIT_REASON_EXCEPTION_NMI
:
6998 if (!is_exception(intr_info
))
7000 else if (is_page_fault(intr_info
))
7002 else if (is_no_device(intr_info
) &&
7003 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7005 return vmcs12
->exception_bitmap
&
7006 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7007 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7009 case EXIT_REASON_TRIPLE_FAULT
:
7011 case EXIT_REASON_PENDING_INTERRUPT
:
7012 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7013 case EXIT_REASON_NMI_WINDOW
:
7014 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7015 case EXIT_REASON_TASK_SWITCH
:
7017 case EXIT_REASON_CPUID
:
7018 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7021 case EXIT_REASON_HLT
:
7022 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7023 case EXIT_REASON_INVD
:
7025 case EXIT_REASON_INVLPG
:
7026 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7027 case EXIT_REASON_RDPMC
:
7028 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7029 case EXIT_REASON_RDTSC
:
7030 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7031 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7032 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7033 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7034 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7035 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7036 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7038 * VMX instructions trap unconditionally. This allows L1 to
7039 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7042 case EXIT_REASON_CR_ACCESS
:
7043 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7044 case EXIT_REASON_DR_ACCESS
:
7045 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7046 case EXIT_REASON_IO_INSTRUCTION
:
7047 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7048 case EXIT_REASON_MSR_READ
:
7049 case EXIT_REASON_MSR_WRITE
:
7050 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7051 case EXIT_REASON_INVALID_STATE
:
7053 case EXIT_REASON_MWAIT_INSTRUCTION
:
7054 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7055 case EXIT_REASON_MONITOR_INSTRUCTION
:
7056 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7057 case EXIT_REASON_PAUSE_INSTRUCTION
:
7058 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7059 nested_cpu_has2(vmcs12
,
7060 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7061 case EXIT_REASON_MCE_DURING_VMENTRY
:
7063 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7064 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7065 case EXIT_REASON_APIC_ACCESS
:
7066 return nested_cpu_has2(vmcs12
,
7067 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7068 case EXIT_REASON_EPT_VIOLATION
:
7070 * L0 always deals with the EPT violation. If nested EPT is
7071 * used, and the nested mmu code discovers that the address is
7072 * missing in the guest EPT table (EPT12), the EPT violation
7073 * will be injected with nested_ept_inject_page_fault()
7076 case EXIT_REASON_EPT_MISCONFIG
:
7078 * L2 never uses directly L1's EPT, but rather L0's own EPT
7079 * table (shadow on EPT) or a merged EPT table that L0 built
7080 * (EPT on EPT). So any problems with the structure of the
7081 * table is L0's fault.
7084 case EXIT_REASON_WBINVD
:
7085 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7086 case EXIT_REASON_XSETBV
:
7093 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7095 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7096 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7100 * The guest has exited. See if we can fix it or if we need userspace
7103 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7105 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7106 u32 exit_reason
= vmx
->exit_reason
;
7107 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7109 /* If guest state is invalid, start emulating */
7110 if (vmx
->emulation_required
)
7111 return handle_invalid_guest_state(vcpu
);
7113 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7114 nested_vmx_vmexit(vcpu
, exit_reason
,
7115 vmcs_read32(VM_EXIT_INTR_INFO
),
7116 vmcs_readl(EXIT_QUALIFICATION
));
7120 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7121 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7122 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7127 if (unlikely(vmx
->fail
)) {
7128 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7129 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7130 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7136 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7137 * delivery event since it indicates guest is accessing MMIO.
7138 * The vm-exit can be triggered again after return to guest that
7139 * will cause infinite loop.
7141 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7142 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7143 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7144 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7145 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7146 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7147 vcpu
->run
->internal
.ndata
= 2;
7148 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7149 vcpu
->run
->internal
.data
[1] = exit_reason
;
7153 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7154 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7155 get_vmcs12(vcpu
))))) {
7156 if (vmx_interrupt_allowed(vcpu
)) {
7157 vmx
->soft_vnmi_blocked
= 0;
7158 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7159 vcpu
->arch
.nmi_pending
) {
7161 * This CPU don't support us in finding the end of an
7162 * NMI-blocked window if the guest runs with IRQs
7163 * disabled. So we pull the trigger after 1 s of
7164 * futile waiting, but inform the user about this.
7166 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7167 "state on VCPU %d after 1 s timeout\n",
7168 __func__
, vcpu
->vcpu_id
);
7169 vmx
->soft_vnmi_blocked
= 0;
7173 if (exit_reason
< kvm_vmx_max_exit_handlers
7174 && kvm_vmx_exit_handlers
[exit_reason
])
7175 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7177 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7178 kvm_queue_exception(vcpu
, UD_VECTOR
);
7183 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7185 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7187 if (is_guest_mode(vcpu
) &&
7188 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7191 if (irr
== -1 || tpr
< irr
) {
7192 vmcs_write32(TPR_THRESHOLD
, 0);
7196 vmcs_write32(TPR_THRESHOLD
, irr
);
7199 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7201 u32 sec_exec_control
;
7204 * There is not point to enable virtualize x2apic without enable
7207 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7208 !vmx_vm_has_apicv(vcpu
->kvm
))
7211 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7214 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7217 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7218 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7220 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7221 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7223 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7225 vmx_set_msr_bitmap(vcpu
);
7228 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
7230 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7233 * Currently we do not handle the nested case where L2 has an
7234 * APIC access page of its own; that page is still pinned.
7235 * Hence, we skip the case where the VCPU is in guest mode _and_
7236 * L1 prepared an APIC access page for L2.
7238 * For the case where L1 and L2 share the same APIC access page
7239 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7240 * in the vmcs12), this function will only update either the vmcs01
7241 * or the vmcs02. If the former, the vmcs02 will be updated by
7242 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7243 * the next L2->L1 exit.
7245 if (!is_guest_mode(vcpu
) ||
7246 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
7247 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
7248 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
7251 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7256 if (!vmx_vm_has_apicv(kvm
))
7262 status
= vmcs_read16(GUEST_INTR_STATUS
);
7267 vmcs_write16(GUEST_INTR_STATUS
, status
);
7271 static void vmx_set_rvi(int vector
)
7276 status
= vmcs_read16(GUEST_INTR_STATUS
);
7277 old
= (u8
)status
& 0xff;
7278 if ((u8
)vector
!= old
) {
7280 status
|= (u8
)vector
;
7281 vmcs_write16(GUEST_INTR_STATUS
, status
);
7285 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7291 * If a vmexit is needed, vmx_check_nested_events handles it.
7293 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
7296 if (!is_guest_mode(vcpu
)) {
7297 vmx_set_rvi(max_irr
);
7302 * Fall back to pre-APICv interrupt injection since L2
7303 * is run without virtual interrupt delivery.
7305 if (!kvm_event_needs_reinjection(vcpu
) &&
7306 vmx_interrupt_allowed(vcpu
)) {
7307 kvm_queue_interrupt(vcpu
, max_irr
, false);
7308 vmx_inject_irq(vcpu
);
7312 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7314 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7317 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7318 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7319 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7320 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7323 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7327 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7328 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7331 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7332 exit_intr_info
= vmx
->exit_intr_info
;
7334 /* Handle machine checks before interrupts are enabled */
7335 if (is_machine_check(exit_intr_info
))
7336 kvm_machine_check();
7338 /* We need to handle NMIs before interrupts are enabled */
7339 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7340 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7341 kvm_before_handle_nmi(&vmx
->vcpu
);
7343 kvm_after_handle_nmi(&vmx
->vcpu
);
7347 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7349 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7352 * If external interrupt exists, IF bit is set in rflags/eflags on the
7353 * interrupt stack frame, and interrupt will be enabled on a return
7354 * from interrupt handler.
7356 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7357 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7358 unsigned int vector
;
7359 unsigned long entry
;
7361 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7362 #ifdef CONFIG_X86_64
7366 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7367 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7368 entry
= gate_offset(*desc
);
7370 #ifdef CONFIG_X86_64
7371 "mov %%" _ASM_SP
", %[sp]\n\t"
7372 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7377 "orl $0x200, (%%" _ASM_SP
")\n\t"
7378 __ASM_SIZE(push
) " $%c[cs]\n\t"
7379 "call *%[entry]\n\t"
7381 #ifdef CONFIG_X86_64
7386 [ss
]"i"(__KERNEL_DS
),
7387 [cs
]"i"(__KERNEL_CS
)
7393 static bool vmx_mpx_supported(void)
7395 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7396 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7399 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7404 bool idtv_info_valid
;
7406 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7408 if (cpu_has_virtual_nmis()) {
7409 if (vmx
->nmi_known_unmasked
)
7412 * Can't use vmx->exit_intr_info since we're not sure what
7413 * the exit reason is.
7415 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7416 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7417 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7419 * SDM 3: 27.7.1.2 (September 2008)
7420 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7421 * a guest IRET fault.
7422 * SDM 3: 23.2.2 (September 2008)
7423 * Bit 12 is undefined in any of the following cases:
7424 * If the VM exit sets the valid bit in the IDT-vectoring
7425 * information field.
7426 * If the VM exit is due to a double fault.
7428 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7429 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7430 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7431 GUEST_INTR_STATE_NMI
);
7433 vmx
->nmi_known_unmasked
=
7434 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7435 & GUEST_INTR_STATE_NMI
);
7436 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7437 vmx
->vnmi_blocked_time
+=
7438 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7441 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7442 u32 idt_vectoring_info
,
7443 int instr_len_field
,
7444 int error_code_field
)
7448 bool idtv_info_valid
;
7450 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7452 vcpu
->arch
.nmi_injected
= false;
7453 kvm_clear_exception_queue(vcpu
);
7454 kvm_clear_interrupt_queue(vcpu
);
7456 if (!idtv_info_valid
)
7459 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7461 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7462 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7465 case INTR_TYPE_NMI_INTR
:
7466 vcpu
->arch
.nmi_injected
= true;
7468 * SDM 3: 27.7.1.2 (September 2008)
7469 * Clear bit "block by NMI" before VM entry if a NMI
7472 vmx_set_nmi_mask(vcpu
, false);
7474 case INTR_TYPE_SOFT_EXCEPTION
:
7475 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7477 case INTR_TYPE_HARD_EXCEPTION
:
7478 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7479 u32 err
= vmcs_read32(error_code_field
);
7480 kvm_requeue_exception_e(vcpu
, vector
, err
);
7482 kvm_requeue_exception(vcpu
, vector
);
7484 case INTR_TYPE_SOFT_INTR
:
7485 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7487 case INTR_TYPE_EXT_INTR
:
7488 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7495 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7497 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7498 VM_EXIT_INSTRUCTION_LEN
,
7499 IDT_VECTORING_ERROR_CODE
);
7502 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7504 __vmx_complete_interrupts(vcpu
,
7505 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7506 VM_ENTRY_INSTRUCTION_LEN
,
7507 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7509 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7512 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7515 struct perf_guest_switch_msr
*msrs
;
7517 msrs
= perf_guest_get_msrs(&nr_msrs
);
7522 for (i
= 0; i
< nr_msrs
; i
++)
7523 if (msrs
[i
].host
== msrs
[i
].guest
)
7524 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7526 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7530 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7532 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7533 unsigned long debugctlmsr
, cr4
;
7535 /* Record the guest's net vcpu time for enforced NMI injections. */
7536 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7537 vmx
->entry_time
= ktime_get();
7539 /* Don't enter VMX if guest state is invalid, let the exit handler
7540 start emulation until we arrive back to a valid state */
7541 if (vmx
->emulation_required
)
7544 if (vmx
->ple_window_dirty
) {
7545 vmx
->ple_window_dirty
= false;
7546 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
7549 if (vmx
->nested
.sync_shadow_vmcs
) {
7550 copy_vmcs12_to_shadow(vmx
);
7551 vmx
->nested
.sync_shadow_vmcs
= false;
7554 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7555 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7556 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7557 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7560 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
7561 vmcs_writel(HOST_CR4
, cr4
);
7562 vmx
->host_state
.vmcs_host_cr4
= cr4
;
7565 /* When single-stepping over STI and MOV SS, we must clear the
7566 * corresponding interruptibility bits in the guest state. Otherwise
7567 * vmentry fails as it then expects bit 14 (BS) in pending debug
7568 * exceptions being set, but that's not correct for the guest debugging
7570 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7571 vmx_set_interrupt_shadow(vcpu
, 0);
7573 atomic_switch_perf_msrs(vmx
);
7574 debugctlmsr
= get_debugctlmsr();
7576 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7578 /* Store host registers */
7579 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7580 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7581 "push %%" _ASM_CX
" \n\t"
7582 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7584 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7585 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7587 /* Reload cr2 if changed */
7588 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7589 "mov %%cr2, %%" _ASM_DX
" \n\t"
7590 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7592 "mov %%" _ASM_AX
", %%cr2 \n\t"
7594 /* Check if vmlaunch of vmresume is needed */
7595 "cmpl $0, %c[launched](%0) \n\t"
7596 /* Load guest registers. Don't clobber flags. */
7597 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7598 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7599 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7600 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7601 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7602 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7603 #ifdef CONFIG_X86_64
7604 "mov %c[r8](%0), %%r8 \n\t"
7605 "mov %c[r9](%0), %%r9 \n\t"
7606 "mov %c[r10](%0), %%r10 \n\t"
7607 "mov %c[r11](%0), %%r11 \n\t"
7608 "mov %c[r12](%0), %%r12 \n\t"
7609 "mov %c[r13](%0), %%r13 \n\t"
7610 "mov %c[r14](%0), %%r14 \n\t"
7611 "mov %c[r15](%0), %%r15 \n\t"
7613 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7615 /* Enter guest mode */
7617 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7619 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7621 /* Save guest registers, load host registers, keep flags */
7622 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7624 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7625 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7626 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7627 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7628 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7629 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7630 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7631 #ifdef CONFIG_X86_64
7632 "mov %%r8, %c[r8](%0) \n\t"
7633 "mov %%r9, %c[r9](%0) \n\t"
7634 "mov %%r10, %c[r10](%0) \n\t"
7635 "mov %%r11, %c[r11](%0) \n\t"
7636 "mov %%r12, %c[r12](%0) \n\t"
7637 "mov %%r13, %c[r13](%0) \n\t"
7638 "mov %%r14, %c[r14](%0) \n\t"
7639 "mov %%r15, %c[r15](%0) \n\t"
7641 "mov %%cr2, %%" _ASM_AX
" \n\t"
7642 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7644 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7645 "setbe %c[fail](%0) \n\t"
7646 ".pushsection .rodata \n\t"
7647 ".global vmx_return \n\t"
7648 "vmx_return: " _ASM_PTR
" 2b \n\t"
7650 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7651 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7652 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7653 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7654 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7655 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7656 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7657 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7658 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7659 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7660 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7661 #ifdef CONFIG_X86_64
7662 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7663 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7664 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7665 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7666 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7667 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7668 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7669 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7671 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7672 [wordsize
]"i"(sizeof(ulong
))
7674 #ifdef CONFIG_X86_64
7675 , "rax", "rbx", "rdi", "rsi"
7676 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7678 , "eax", "ebx", "edi", "esi"
7682 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7684 update_debugctlmsr(debugctlmsr
);
7686 #ifndef CONFIG_X86_64
7688 * The sysexit path does not restore ds/es, so we must set them to
7689 * a reasonable value ourselves.
7691 * We can't defer this to vmx_load_host_state() since that function
7692 * may be executed in interrupt context, which saves and restore segments
7693 * around it, nullifying its effect.
7695 loadsegment(ds
, __USER_DS
);
7696 loadsegment(es
, __USER_DS
);
7699 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7700 | (1 << VCPU_EXREG_RFLAGS
)
7701 | (1 << VCPU_EXREG_PDPTR
)
7702 | (1 << VCPU_EXREG_SEGMENTS
)
7703 | (1 << VCPU_EXREG_CR3
));
7704 vcpu
->arch
.regs_dirty
= 0;
7706 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7708 vmx
->loaded_vmcs
->launched
= 1;
7710 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7711 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7714 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7715 * we did not inject a still-pending event to L1 now because of
7716 * nested_run_pending, we need to re-enable this bit.
7718 if (vmx
->nested
.nested_run_pending
)
7719 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7721 vmx
->nested
.nested_run_pending
= 0;
7723 vmx_complete_atomic_exit(vmx
);
7724 vmx_recover_nmi_blocking(vmx
);
7725 vmx_complete_interrupts(vmx
);
7728 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
7730 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7733 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
7737 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7739 vmx_vcpu_load(vcpu
, cpu
);
7744 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7749 leave_guest_mode(vcpu
);
7750 vmx_load_vmcs01(vcpu
);
7752 free_loaded_vmcs(vmx
->loaded_vmcs
);
7753 kfree(vmx
->guest_msrs
);
7754 kvm_vcpu_uninit(vcpu
);
7755 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7758 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7761 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7765 return ERR_PTR(-ENOMEM
);
7769 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7773 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7774 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
7778 if (!vmx
->guest_msrs
) {
7782 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7783 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7784 if (!vmx
->loaded_vmcs
->vmcs
)
7787 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7788 loaded_vmcs_init(vmx
->loaded_vmcs
);
7793 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7794 vmx
->vcpu
.cpu
= cpu
;
7795 err
= vmx_vcpu_setup(vmx
);
7796 vmx_vcpu_put(&vmx
->vcpu
);
7800 if (vm_need_virtualize_apic_accesses(kvm
)) {
7801 err
= alloc_apic_access_page(kvm
);
7807 if (!kvm
->arch
.ept_identity_map_addr
)
7808 kvm
->arch
.ept_identity_map_addr
=
7809 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7810 err
= init_rmode_identity_map(kvm
);
7815 vmx
->nested
.current_vmptr
= -1ull;
7816 vmx
->nested
.current_vmcs12
= NULL
;
7821 free_loaded_vmcs(vmx
->loaded_vmcs
);
7823 kfree(vmx
->guest_msrs
);
7825 kvm_vcpu_uninit(&vmx
->vcpu
);
7828 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7829 return ERR_PTR(err
);
7832 static void __init
vmx_check_processor_compat(void *rtn
)
7834 struct vmcs_config vmcs_conf
;
7837 if (setup_vmcs_config(&vmcs_conf
) < 0)
7839 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7840 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7841 smp_processor_id());
7846 static int get_ept_level(void)
7848 return VMX_EPT_DEFAULT_GAW
+ 1;
7851 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7855 /* For VT-d and EPT combination
7856 * 1. MMIO: always map as UC
7858 * a. VT-d without snooping control feature: can't guarantee the
7859 * result, try to trust guest.
7860 * b. VT-d with snooping control feature: snooping control feature of
7861 * VT-d engine can guarantee the cache correctness. Just set it
7862 * to WB to keep consistent with host. So the same as item 3.
7863 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7864 * consistent with host MTRR
7867 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7868 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7869 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7870 VMX_EPT_MT_EPTE_SHIFT
;
7872 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7878 static int vmx_get_lpage_level(void)
7880 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7881 return PT_DIRECTORY_LEVEL
;
7883 /* For shadow and EPT supported 1GB page */
7884 return PT_PDPE_LEVEL
;
7887 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7889 struct kvm_cpuid_entry2
*best
;
7890 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7893 vmx
->rdtscp_enabled
= false;
7894 if (vmx_rdtscp_supported()) {
7895 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7896 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7897 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7898 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7899 vmx
->rdtscp_enabled
= true;
7901 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7902 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7908 /* Exposing INVPCID only when PCID is exposed */
7909 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7910 if (vmx_invpcid_supported() &&
7911 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7912 guest_cpuid_has_pcid(vcpu
)) {
7913 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7914 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7915 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7918 if (cpu_has_secondary_exec_ctrls()) {
7919 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7920 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7921 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7925 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7929 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7931 if (func
== 1 && nested
)
7932 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7935 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7936 struct x86_exception
*fault
)
7938 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7941 if (fault
->error_code
& PFERR_RSVD_MASK
)
7942 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7944 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7945 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7946 vmcs12
->guest_physical_address
= fault
->address
;
7949 /* Callbacks for nested_ept_init_mmu_context: */
7951 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7953 /* return the page table to be shadowed - in our case, EPT12 */
7954 return get_vmcs12(vcpu
)->ept_pointer
;
7957 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7959 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7960 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7962 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7963 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7964 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7966 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7969 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7971 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7974 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7975 struct x86_exception
*fault
)
7977 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7979 WARN_ON(!is_guest_mode(vcpu
));
7981 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7982 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7983 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7984 vmcs_read32(VM_EXIT_INTR_INFO
),
7985 vmcs_readl(EXIT_QUALIFICATION
));
7987 kvm_inject_page_fault(vcpu
, fault
);
7990 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
7991 struct vmcs12
*vmcs12
)
7993 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7995 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
7996 /* TODO: Also verify bits beyond physical address width are 0 */
7997 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
))
8001 * Translate L1 physical address to host physical
8002 * address for vmcs02. Keep the page pinned, so this
8003 * physical address remains valid. We keep a reference
8004 * to it so we can release it later.
8006 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8007 nested_release_page(vmx
->nested
.apic_access_page
);
8008 vmx
->nested
.apic_access_page
=
8009 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8012 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8013 /* TODO: Also verify bits beyond physical address width are 0 */
8014 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
))
8017 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8018 nested_release_page(vmx
->nested
.virtual_apic_page
);
8019 vmx
->nested
.virtual_apic_page
=
8020 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8023 * Failing the vm entry is _not_ what the processor does
8024 * but it's basically the only possibility we have.
8025 * We could still enter the guest if CR8 load exits are
8026 * enabled, CR8 store exits are enabled, and virtualize APIC
8027 * access is disabled; in this case the processor would never
8028 * use the TPR shadow and we could simply clear the bit from
8029 * the execution control. But such a configuration is useless,
8030 * so let's keep the code simple.
8032 if (!vmx
->nested
.virtual_apic_page
)
8039 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8041 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8042 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8044 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8047 /* Make sure short timeouts reliably trigger an immediate vmexit.
8048 * hrtimer_start does not guarantee this. */
8049 if (preemption_timeout
<= 1) {
8050 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8054 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8055 preemption_timeout
*= 1000000;
8056 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8057 hrtimer_start(&vmx
->nested
.preemption_timer
,
8058 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8062 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8063 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8064 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8065 * guest in a way that will both be appropriate to L1's requests, and our
8066 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8067 * function also has additional necessary side-effects, like setting various
8068 * vcpu->arch fields.
8070 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8072 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8075 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
8076 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
8077 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
8078 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
8079 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
8080 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
8081 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
8082 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
8083 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
8084 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
8085 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
8086 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
8087 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
8088 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
8089 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
8090 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
8091 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
8092 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
8093 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
8094 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
8095 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
8096 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
8097 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
8098 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
8099 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
8100 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
8101 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
8102 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
8103 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
8104 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
8105 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
8106 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
8107 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
8108 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
8109 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
8110 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
8112 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
8113 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
8114 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
8116 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
8117 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
8119 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
8120 vmcs12
->vm_entry_intr_info_field
);
8121 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
8122 vmcs12
->vm_entry_exception_error_code
);
8123 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
8124 vmcs12
->vm_entry_instruction_len
);
8125 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
8126 vmcs12
->guest_interruptibility_info
);
8127 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
8128 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
8129 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
8130 vmcs12
->guest_pending_dbg_exceptions
);
8131 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
8132 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
8134 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
8136 exec_control
= vmcs12
->pin_based_vm_exec_control
;
8137 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
8138 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
8139 PIN_BASED_POSTED_INTR
);
8140 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
8142 vmx
->nested
.preemption_timer_expired
= false;
8143 if (nested_cpu_has_preemption_timer(vmcs12
))
8144 vmx_start_preemption_timer(vcpu
);
8147 * Whether page-faults are trapped is determined by a combination of
8148 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8149 * If enable_ept, L0 doesn't care about page faults and we should
8150 * set all of these to L1's desires. However, if !enable_ept, L0 does
8151 * care about (at least some) page faults, and because it is not easy
8152 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8153 * to exit on each and every L2 page fault. This is done by setting
8154 * MASK=MATCH=0 and (see below) EB.PF=1.
8155 * Note that below we don't need special code to set EB.PF beyond the
8156 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8157 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8158 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8160 * A problem with this approach (when !enable_ept) is that L1 may be
8161 * injected with more page faults than it asked for. This could have
8162 * caused problems, but in practice existing hypervisors don't care.
8163 * To fix this, we will need to emulate the PFEC checking (on the L1
8164 * page tables), using walk_addr(), when injecting PFs to L1.
8166 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
8167 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
8168 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
8169 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
8171 if (cpu_has_secondary_exec_ctrls()) {
8172 exec_control
= vmx_secondary_exec_control(vmx
);
8173 if (!vmx
->rdtscp_enabled
)
8174 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8175 /* Take the following fields only from vmcs12 */
8176 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
8177 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
8178 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
8179 if (nested_cpu_has(vmcs12
,
8180 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
8181 exec_control
|= vmcs12
->secondary_vm_exec_control
;
8183 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
8185 * If translation failed, no matter: This feature asks
8186 * to exit when accessing the given address, and if it
8187 * can never be accessed, this feature won't do
8190 if (!vmx
->nested
.apic_access_page
)
8192 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8194 vmcs_write64(APIC_ACCESS_ADDR
,
8195 page_to_phys(vmx
->nested
.apic_access_page
));
8196 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
8198 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8199 kvm_vcpu_reload_apic_access_page(vcpu
);
8202 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
8207 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8208 * Some constant fields are set here by vmx_set_constant_host_state().
8209 * Other fields are different per CPU, and will be set later when
8210 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8212 vmx_set_constant_host_state(vmx
);
8215 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8216 * entry, but only if the current (host) sp changed from the value
8217 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8218 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8219 * here we just force the write to happen on entry.
8223 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
8224 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
8225 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
8226 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
8227 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
8229 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
8230 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
8231 page_to_phys(vmx
->nested
.virtual_apic_page
));
8232 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
8236 * Merging of IO and MSR bitmaps not currently supported.
8237 * Rather, exit every time.
8239 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
8240 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
8241 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
8243 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
8245 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8246 * bitwise-or of what L1 wants to trap for L2, and what we want to
8247 * trap. Note that CR0.TS also needs updating - we do this later.
8249 update_exception_bitmap(vcpu
);
8250 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
8251 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8253 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8254 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8255 * bits are further modified by vmx_set_efer() below.
8257 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
8259 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8260 * emulated by vmx_set_efer(), below.
8262 vm_entry_controls_init(vmx
,
8263 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
8264 ~VM_ENTRY_IA32E_MODE
) |
8265 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
8267 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
8268 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
8269 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
8270 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
8271 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
8274 set_cr4_guest_host_mask(vmx
);
8276 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
8277 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
8279 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
8280 vmcs_write64(TSC_OFFSET
,
8281 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
8283 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8287 * Trivially support vpid by letting L2s share their parent
8288 * L1's vpid. TODO: move to a more elaborate solution, giving
8289 * each L2 its own vpid and exposing the vpid feature to L1.
8291 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
8292 vmx_flush_tlb(vcpu
);
8295 if (nested_cpu_has_ept(vmcs12
)) {
8296 kvm_mmu_unload(vcpu
);
8297 nested_ept_init_mmu_context(vcpu
);
8300 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
8301 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
8302 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
8303 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8305 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8306 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8307 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8310 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8311 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8312 * The CR0_READ_SHADOW is what L2 should have expected to read given
8313 * the specifications by L1; It's not enough to take
8314 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8315 * have more bits than L1 expected.
8317 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
8318 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
8320 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
8321 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
8323 /* shadow page tables on either EPT or shadow page tables */
8324 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
8325 kvm_mmu_reset_context(vcpu
);
8328 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
8331 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8334 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
8335 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
8336 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
8337 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
8340 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
8341 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
8345 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8346 * for running an L2 nested guest.
8348 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
8350 struct vmcs12
*vmcs12
;
8351 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8353 struct loaded_vmcs
*vmcs02
;
8356 if (!nested_vmx_check_permission(vcpu
) ||
8357 !nested_vmx_check_vmcs12(vcpu
))
8360 skip_emulated_instruction(vcpu
);
8361 vmcs12
= get_vmcs12(vcpu
);
8363 if (enable_shadow_vmcs
)
8364 copy_shadow_to_vmcs12(vmx
);
8367 * The nested entry process starts with enforcing various prerequisites
8368 * on vmcs12 as required by the Intel SDM, and act appropriately when
8369 * they fail: As the SDM explains, some conditions should cause the
8370 * instruction to fail, while others will cause the instruction to seem
8371 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8372 * To speed up the normal (success) code path, we should avoid checking
8373 * for misconfigurations which will anyway be caught by the processor
8374 * when using the merged vmcs02.
8376 if (vmcs12
->launch_state
== launch
) {
8377 nested_vmx_failValid(vcpu
,
8378 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8379 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
8383 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
8384 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
8385 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8389 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
8390 !PAGE_ALIGNED(vmcs12
->msr_bitmap
)) {
8391 /*TODO: Also verify bits beyond physical address width are 0*/
8392 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8396 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
8397 /*TODO: Also verify bits beyond physical address width are 0*/
8398 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8402 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8403 vmcs12
->vm_exit_msr_load_count
> 0 ||
8404 vmcs12
->vm_exit_msr_store_count
> 0) {
8405 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8407 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8411 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8412 nested_vmx_true_procbased_ctls_low
,
8413 nested_vmx_procbased_ctls_high
) ||
8414 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8415 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8416 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8417 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8418 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8419 nested_vmx_true_exit_ctls_low
,
8420 nested_vmx_exit_ctls_high
) ||
8421 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8422 nested_vmx_true_entry_ctls_low
,
8423 nested_vmx_entry_ctls_high
))
8425 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8429 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8430 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8431 nested_vmx_failValid(vcpu
,
8432 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8436 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8437 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8438 nested_vmx_entry_failure(vcpu
, vmcs12
,
8439 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8442 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8443 nested_vmx_entry_failure(vcpu
, vmcs12
,
8444 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8449 * If the load IA32_EFER VM-entry control is 1, the following checks
8450 * are performed on the field for the IA32_EFER MSR:
8451 * - Bits reserved in the IA32_EFER MSR must be 0.
8452 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8453 * the IA-32e mode guest VM-exit control. It must also be identical
8454 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8457 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8458 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8459 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8460 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8461 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8462 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8463 nested_vmx_entry_failure(vcpu
, vmcs12
,
8464 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8470 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8471 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8472 * the values of the LMA and LME bits in the field must each be that of
8473 * the host address-space size VM-exit control.
8475 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8476 ia32e
= (vmcs12
->vm_exit_controls
&
8477 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8478 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8479 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8480 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8481 nested_vmx_entry_failure(vcpu
, vmcs12
,
8482 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8488 * We're finally done with prerequisite checking, and can start with
8492 vmcs02
= nested_get_current_vmcs02(vmx
);
8496 enter_guest_mode(vcpu
);
8498 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8500 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
8501 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8504 vmx
->loaded_vmcs
= vmcs02
;
8506 vmx_vcpu_load(vcpu
, cpu
);
8510 vmx_segment_cache_clear(vmx
);
8512 vmcs12
->launch_state
= 1;
8514 prepare_vmcs02(vcpu
, vmcs12
);
8516 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8517 return kvm_emulate_halt(vcpu
);
8519 vmx
->nested
.nested_run_pending
= 1;
8522 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8523 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8524 * returned as far as L1 is concerned. It will only return (and set
8525 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8531 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8532 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8533 * This function returns the new value we should put in vmcs12.guest_cr0.
8534 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8535 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8536 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8537 * didn't trap the bit, because if L1 did, so would L0).
8538 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8539 * been modified by L2, and L1 knows it. So just leave the old value of
8540 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8541 * isn't relevant, because if L0 traps this bit it can set it to anything.
8542 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8543 * changed these bits, and therefore they need to be updated, but L0
8544 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8545 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8547 static inline unsigned long
8548 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8551 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8552 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8553 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8554 vcpu
->arch
.cr0_guest_owned_bits
));
8557 static inline unsigned long
8558 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8561 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8562 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8563 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8564 vcpu
->arch
.cr4_guest_owned_bits
));
8567 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8568 struct vmcs12
*vmcs12
)
8573 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8574 nr
= vcpu
->arch
.exception
.nr
;
8575 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8577 if (kvm_exception_is_soft(nr
)) {
8578 vmcs12
->vm_exit_instruction_len
=
8579 vcpu
->arch
.event_exit_inst_len
;
8580 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8582 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8584 if (vcpu
->arch
.exception
.has_error_code
) {
8585 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8586 vmcs12
->idt_vectoring_error_code
=
8587 vcpu
->arch
.exception
.error_code
;
8590 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8591 } else if (vcpu
->arch
.nmi_injected
) {
8592 vmcs12
->idt_vectoring_info_field
=
8593 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8594 } else if (vcpu
->arch
.interrupt
.pending
) {
8595 nr
= vcpu
->arch
.interrupt
.nr
;
8596 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8598 if (vcpu
->arch
.interrupt
.soft
) {
8599 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8600 vmcs12
->vm_entry_instruction_len
=
8601 vcpu
->arch
.event_exit_inst_len
;
8603 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8605 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8609 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8611 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8613 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8614 vmx
->nested
.preemption_timer_expired
) {
8615 if (vmx
->nested
.nested_run_pending
)
8617 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8621 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8622 if (vmx
->nested
.nested_run_pending
||
8623 vcpu
->arch
.interrupt
.pending
)
8625 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8626 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8627 INTR_INFO_VALID_MASK
, 0);
8629 * The NMI-triggered VM exit counts as injection:
8630 * clear this one and block further NMIs.
8632 vcpu
->arch
.nmi_pending
= 0;
8633 vmx_set_nmi_mask(vcpu
, true);
8637 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8638 nested_exit_on_intr(vcpu
)) {
8639 if (vmx
->nested
.nested_run_pending
)
8641 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8647 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8650 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8653 if (ktime_to_ns(remaining
) <= 0)
8656 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8657 do_div(value
, 1000000);
8658 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8662 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8663 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8664 * and this function updates it to reflect the changes to the guest state while
8665 * L2 was running (and perhaps made some exits which were handled directly by L0
8666 * without going back to L1), and to reflect the exit reason.
8667 * Note that we do not have to copy here all VMCS fields, just those that
8668 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8669 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8670 * which already writes to vmcs12 directly.
8672 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8673 u32 exit_reason
, u32 exit_intr_info
,
8674 unsigned long exit_qualification
)
8676 /* update guest state fields: */
8677 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8678 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8680 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8681 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8682 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8684 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8685 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8686 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8687 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8688 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8689 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8690 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8691 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8692 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8693 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8694 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8695 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8696 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8697 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8698 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8699 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8700 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8701 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8702 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8703 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8704 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8705 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8706 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8707 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8708 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8709 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8710 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8711 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8712 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8713 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8714 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8715 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8716 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8717 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8718 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8719 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8721 vmcs12
->guest_interruptibility_info
=
8722 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8723 vmcs12
->guest_pending_dbg_exceptions
=
8724 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8725 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8726 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8728 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8730 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8731 if (vmcs12
->vm_exit_controls
&
8732 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8733 vmcs12
->vmx_preemption_timer_value
=
8734 vmx_get_preemption_timer_value(vcpu
);
8735 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8739 * In some cases (usually, nested EPT), L2 is allowed to change its
8740 * own CR3 without exiting. If it has changed it, we must keep it.
8741 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8742 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8744 * Additionally, restore L2's PDPTR to vmcs12.
8747 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8748 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8749 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8750 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8751 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8754 vmcs12
->vm_entry_controls
=
8755 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8756 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8758 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
8759 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8760 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8763 /* TODO: These cannot have changed unless we have MSR bitmaps and
8764 * the relevant bit asks not to trap the change */
8765 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8766 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8767 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8768 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8769 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8770 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8771 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8772 if (vmx_mpx_supported())
8773 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8775 /* update exit information fields: */
8777 vmcs12
->vm_exit_reason
= exit_reason
;
8778 vmcs12
->exit_qualification
= exit_qualification
;
8780 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8781 if ((vmcs12
->vm_exit_intr_info
&
8782 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8783 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8784 vmcs12
->vm_exit_intr_error_code
=
8785 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8786 vmcs12
->idt_vectoring_info_field
= 0;
8787 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8788 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8790 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8791 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8792 * instead of reading the real value. */
8793 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8796 * Transfer the event that L0 or L1 may wanted to inject into
8797 * L2 to IDT_VECTORING_INFO_FIELD.
8799 vmcs12_save_pending_event(vcpu
, vmcs12
);
8803 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8804 * preserved above and would only end up incorrectly in L1.
8806 vcpu
->arch
.nmi_injected
= false;
8807 kvm_clear_exception_queue(vcpu
);
8808 kvm_clear_interrupt_queue(vcpu
);
8812 * A part of what we need to when the nested L2 guest exits and we want to
8813 * run its L1 parent, is to reset L1's guest state to the host state specified
8815 * This function is to be called not only on normal nested exit, but also on
8816 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8817 * Failures During or After Loading Guest State").
8818 * This function should be called when the active VMCS is L1's (vmcs01).
8820 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8821 struct vmcs12
*vmcs12
)
8823 struct kvm_segment seg
;
8825 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8826 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8827 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8828 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8830 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8831 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8833 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8834 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8835 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8837 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8838 * actually changed, because it depends on the current state of
8839 * fpu_active (which may have changed).
8840 * Note that vmx_set_cr0 refers to efer set above.
8842 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8844 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8845 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8846 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8848 update_exception_bitmap(vcpu
);
8849 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8850 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8853 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8854 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8856 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8857 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8859 nested_ept_uninit_mmu_context(vcpu
);
8861 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8862 kvm_mmu_reset_context(vcpu
);
8865 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8869 * Trivially support vpid by letting L2s share their parent
8870 * L1's vpid. TODO: move to a more elaborate solution, giving
8871 * each L2 its own vpid and exposing the vpid feature to L1.
8873 vmx_flush_tlb(vcpu
);
8877 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8878 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8879 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8880 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8881 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8883 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8884 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
8885 vmcs_write64(GUEST_BNDCFGS
, 0);
8887 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8888 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8889 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8891 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8892 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8893 vmcs12
->host_ia32_perf_global_ctrl
);
8895 /* Set L1 segment info according to Intel SDM
8896 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8897 seg
= (struct kvm_segment
) {
8899 .limit
= 0xFFFFFFFF,
8900 .selector
= vmcs12
->host_cs_selector
,
8906 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8910 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8911 seg
= (struct kvm_segment
) {
8913 .limit
= 0xFFFFFFFF,
8920 seg
.selector
= vmcs12
->host_ds_selector
;
8921 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8922 seg
.selector
= vmcs12
->host_es_selector
;
8923 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8924 seg
.selector
= vmcs12
->host_ss_selector
;
8925 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8926 seg
.selector
= vmcs12
->host_fs_selector
;
8927 seg
.base
= vmcs12
->host_fs_base
;
8928 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8929 seg
.selector
= vmcs12
->host_gs_selector
;
8930 seg
.base
= vmcs12
->host_gs_base
;
8931 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8932 seg
= (struct kvm_segment
) {
8933 .base
= vmcs12
->host_tr_base
,
8935 .selector
= vmcs12
->host_tr_selector
,
8939 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8941 kvm_set_dr(vcpu
, 7, 0x400);
8942 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8946 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8947 * and modify vmcs12 to make it see what it would expect to see there if
8948 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8950 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8952 unsigned long exit_qualification
)
8954 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8955 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8957 /* trying to cancel vmlaunch/vmresume is a bug */
8958 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8960 leave_guest_mode(vcpu
);
8961 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8962 exit_qualification
);
8964 vmx_load_vmcs01(vcpu
);
8966 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
8967 && nested_exit_intr_ack_set(vcpu
)) {
8968 int irq
= kvm_cpu_get_interrupt(vcpu
);
8970 vmcs12
->vm_exit_intr_info
= irq
|
8971 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
8974 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8975 vmcs12
->exit_qualification
,
8976 vmcs12
->idt_vectoring_info_field
,
8977 vmcs12
->vm_exit_intr_info
,
8978 vmcs12
->vm_exit_intr_error_code
,
8981 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8982 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8983 vmx_segment_cache_clear(vmx
);
8985 /* if no vmcs02 cache requested, remove the one we used */
8986 if (VMCS02_POOL_SIZE
== 0)
8987 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8989 load_vmcs12_host_state(vcpu
, vmcs12
);
8991 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8992 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8994 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8997 /* Unpin physical memory we referred to in vmcs02 */
8998 if (vmx
->nested
.apic_access_page
) {
8999 nested_release_page(vmx
->nested
.apic_access_page
);
9000 vmx
->nested
.apic_access_page
= NULL
;
9002 if (vmx
->nested
.virtual_apic_page
) {
9003 nested_release_page(vmx
->nested
.virtual_apic_page
);
9004 vmx
->nested
.virtual_apic_page
= NULL
;
9008 * We are now running in L2, mmu_notifier will force to reload the
9009 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9011 kvm_vcpu_reload_apic_access_page(vcpu
);
9014 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9015 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9016 * success or failure flag accordingly.
9018 if (unlikely(vmx
->fail
)) {
9020 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
9022 nested_vmx_succeed(vcpu
);
9023 if (enable_shadow_vmcs
)
9024 vmx
->nested
.sync_shadow_vmcs
= true;
9026 /* in case we halted in L2 */
9027 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
9031 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9033 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
9035 if (is_guest_mode(vcpu
))
9036 nested_vmx_vmexit(vcpu
, -1, 0, 0);
9037 free_nested(to_vmx(vcpu
));
9041 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9042 * 23.7 "VM-entry failures during or after loading guest state" (this also
9043 * lists the acceptable exit-reason and exit-qualification parameters).
9044 * It should only be called before L2 actually succeeded to run, and when
9045 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9047 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
9048 struct vmcs12
*vmcs12
,
9049 u32 reason
, unsigned long qualification
)
9051 load_vmcs12_host_state(vcpu
, vmcs12
);
9052 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
9053 vmcs12
->exit_qualification
= qualification
;
9054 nested_vmx_succeed(vcpu
);
9055 if (enable_shadow_vmcs
)
9056 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
9059 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
9060 struct x86_instruction_info
*info
,
9061 enum x86_intercept_stage stage
)
9063 return X86EMUL_CONTINUE
;
9066 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
9069 shrink_ple_window(vcpu
);
9072 static struct kvm_x86_ops vmx_x86_ops
= {
9073 .cpu_has_kvm_support
= cpu_has_kvm_support
,
9074 .disabled_by_bios
= vmx_disabled_by_bios
,
9075 .hardware_setup
= hardware_setup
,
9076 .hardware_unsetup
= hardware_unsetup
,
9077 .check_processor_compatibility
= vmx_check_processor_compat
,
9078 .hardware_enable
= hardware_enable
,
9079 .hardware_disable
= hardware_disable
,
9080 .cpu_has_accelerated_tpr
= report_flexpriority
,
9082 .vcpu_create
= vmx_create_vcpu
,
9083 .vcpu_free
= vmx_free_vcpu
,
9084 .vcpu_reset
= vmx_vcpu_reset
,
9086 .prepare_guest_switch
= vmx_save_host_state
,
9087 .vcpu_load
= vmx_vcpu_load
,
9088 .vcpu_put
= vmx_vcpu_put
,
9090 .update_db_bp_intercept
= update_exception_bitmap
,
9091 .get_msr
= vmx_get_msr
,
9092 .set_msr
= vmx_set_msr
,
9093 .get_segment_base
= vmx_get_segment_base
,
9094 .get_segment
= vmx_get_segment
,
9095 .set_segment
= vmx_set_segment
,
9096 .get_cpl
= vmx_get_cpl
,
9097 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
9098 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
9099 .decache_cr3
= vmx_decache_cr3
,
9100 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
9101 .set_cr0
= vmx_set_cr0
,
9102 .set_cr3
= vmx_set_cr3
,
9103 .set_cr4
= vmx_set_cr4
,
9104 .set_efer
= vmx_set_efer
,
9105 .get_idt
= vmx_get_idt
,
9106 .set_idt
= vmx_set_idt
,
9107 .get_gdt
= vmx_get_gdt
,
9108 .set_gdt
= vmx_set_gdt
,
9109 .get_dr6
= vmx_get_dr6
,
9110 .set_dr6
= vmx_set_dr6
,
9111 .set_dr7
= vmx_set_dr7
,
9112 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
9113 .cache_reg
= vmx_cache_reg
,
9114 .get_rflags
= vmx_get_rflags
,
9115 .set_rflags
= vmx_set_rflags
,
9116 .fpu_deactivate
= vmx_fpu_deactivate
,
9118 .tlb_flush
= vmx_flush_tlb
,
9120 .run
= vmx_vcpu_run
,
9121 .handle_exit
= vmx_handle_exit
,
9122 .skip_emulated_instruction
= skip_emulated_instruction
,
9123 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
9124 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
9125 .patch_hypercall
= vmx_patch_hypercall
,
9126 .set_irq
= vmx_inject_irq
,
9127 .set_nmi
= vmx_inject_nmi
,
9128 .queue_exception
= vmx_queue_exception
,
9129 .cancel_injection
= vmx_cancel_injection
,
9130 .interrupt_allowed
= vmx_interrupt_allowed
,
9131 .nmi_allowed
= vmx_nmi_allowed
,
9132 .get_nmi_mask
= vmx_get_nmi_mask
,
9133 .set_nmi_mask
= vmx_set_nmi_mask
,
9134 .enable_nmi_window
= enable_nmi_window
,
9135 .enable_irq_window
= enable_irq_window
,
9136 .update_cr8_intercept
= update_cr8_intercept
,
9137 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
9138 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
9139 .vm_has_apicv
= vmx_vm_has_apicv
,
9140 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
9141 .hwapic_irr_update
= vmx_hwapic_irr_update
,
9142 .hwapic_isr_update
= vmx_hwapic_isr_update
,
9143 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
9144 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
9146 .set_tss_addr
= vmx_set_tss_addr
,
9147 .get_tdp_level
= get_ept_level
,
9148 .get_mt_mask
= vmx_get_mt_mask
,
9150 .get_exit_info
= vmx_get_exit_info
,
9152 .get_lpage_level
= vmx_get_lpage_level
,
9154 .cpuid_update
= vmx_cpuid_update
,
9156 .rdtscp_supported
= vmx_rdtscp_supported
,
9157 .invpcid_supported
= vmx_invpcid_supported
,
9159 .set_supported_cpuid
= vmx_set_supported_cpuid
,
9161 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
9163 .set_tsc_khz
= vmx_set_tsc_khz
,
9164 .read_tsc_offset
= vmx_read_tsc_offset
,
9165 .write_tsc_offset
= vmx_write_tsc_offset
,
9166 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
9167 .compute_tsc_offset
= vmx_compute_tsc_offset
,
9168 .read_l1_tsc
= vmx_read_l1_tsc
,
9170 .set_tdp_cr3
= vmx_set_cr3
,
9172 .check_intercept
= vmx_check_intercept
,
9173 .handle_external_intr
= vmx_handle_external_intr
,
9174 .mpx_supported
= vmx_mpx_supported
,
9176 .check_nested_events
= vmx_check_nested_events
,
9178 .sched_in
= vmx_sched_in
,
9181 static int __init
vmx_init(void)
9185 rdmsrl_safe(MSR_EFER
, &host_efer
);
9187 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
9188 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
9190 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9191 if (!vmx_io_bitmap_a
)
9196 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9197 if (!vmx_io_bitmap_b
)
9200 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9201 if (!vmx_msr_bitmap_legacy
)
9204 vmx_msr_bitmap_legacy_x2apic
=
9205 (unsigned long *)__get_free_page(GFP_KERNEL
);
9206 if (!vmx_msr_bitmap_legacy_x2apic
)
9209 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9210 if (!vmx_msr_bitmap_longmode
)
9213 vmx_msr_bitmap_longmode_x2apic
=
9214 (unsigned long *)__get_free_page(GFP_KERNEL
);
9215 if (!vmx_msr_bitmap_longmode_x2apic
)
9217 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9218 if (!vmx_vmread_bitmap
)
9221 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9222 if (!vmx_vmwrite_bitmap
)
9225 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
9226 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
9229 * Allow direct access to the PC debug port (it is often used for I/O
9230 * delays, but the vmexits simply slow things down).
9232 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
9233 clear_bit(0x80, vmx_io_bitmap_a
);
9235 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
9237 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
9238 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
9240 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
9242 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
9243 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
9248 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
9249 crash_vmclear_local_loaded_vmcss
);
9252 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
9253 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
9254 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
9255 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
9256 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
9257 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
9258 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
9260 memcpy(vmx_msr_bitmap_legacy_x2apic
,
9261 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
9262 memcpy(vmx_msr_bitmap_longmode_x2apic
,
9263 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
9266 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9267 vmx_disable_intercept_msr_read_x2apic(msr
);
9269 /* According SDM, in x2apic mode, the whole id reg is used.
9270 * But in KVM, it only use the highest eight bits. Need to
9272 vmx_enable_intercept_msr_read_x2apic(0x802);
9274 vmx_enable_intercept_msr_read_x2apic(0x839);
9276 vmx_disable_intercept_msr_write_x2apic(0x808);
9278 vmx_disable_intercept_msr_write_x2apic(0x80b);
9280 vmx_disable_intercept_msr_write_x2apic(0x83f);
9284 kvm_mmu_set_mask_ptes(0ull,
9285 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
9286 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
9287 0ull, VMX_EPT_EXECUTABLE_MASK
);
9288 ept_set_mmio_spte_mask();
9293 update_ple_window_actual_max();
9298 free_page((unsigned long)vmx_vmwrite_bitmap
);
9300 free_page((unsigned long)vmx_vmread_bitmap
);
9302 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9304 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9306 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9308 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9310 free_page((unsigned long)vmx_io_bitmap_b
);
9312 free_page((unsigned long)vmx_io_bitmap_a
);
9316 static void __exit
vmx_exit(void)
9318 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9319 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9320 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9321 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9322 free_page((unsigned long)vmx_io_bitmap_b
);
9323 free_page((unsigned long)vmx_io_bitmap_a
);
9324 free_page((unsigned long)vmx_vmwrite_bitmap
);
9325 free_page((unsigned long)vmx_vmread_bitmap
);
9328 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
9335 module_init(vmx_init
)
9336 module_exit(vmx_exit
)