2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
36 static int bypass_guest_pf
= 1;
37 module_param(bypass_guest_pf
, bool, 0);
39 static int enable_vpid
= 1;
40 module_param(enable_vpid
, bool, 0);
52 u32 idt_vectoring_info
;
53 struct kvm_msr_entry
*guest_msrs
;
54 struct kvm_msr_entry
*host_msrs
;
59 int msr_offset_kernel_gs_base
;
64 u16 fs_sel
, gs_sel
, ldt_sel
;
65 int gs_ldt_reload_needed
;
67 int guest_efer_loaded
;
79 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
81 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
84 static int init_rmode_tss(struct kvm
*kvm
);
86 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
87 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
89 static struct page
*vmx_io_bitmap_a
;
90 static struct page
*vmx_io_bitmap_b
;
92 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
93 static DEFINE_SPINLOCK(vmx_vpid_lock
);
95 static struct vmcs_config
{
99 u32 pin_based_exec_ctrl
;
100 u32 cpu_based_exec_ctrl
;
101 u32 cpu_based_2nd_exec_ctrl
;
106 #define VMX_SEGMENT_FIELD(seg) \
107 [VCPU_SREG_##seg] = { \
108 .selector = GUEST_##seg##_SELECTOR, \
109 .base = GUEST_##seg##_BASE, \
110 .limit = GUEST_##seg##_LIMIT, \
111 .ar_bytes = GUEST_##seg##_AR_BYTES, \
114 static struct kvm_vmx_segment_field
{
119 } kvm_vmx_segment_fields
[] = {
120 VMX_SEGMENT_FIELD(CS
),
121 VMX_SEGMENT_FIELD(DS
),
122 VMX_SEGMENT_FIELD(ES
),
123 VMX_SEGMENT_FIELD(FS
),
124 VMX_SEGMENT_FIELD(GS
),
125 VMX_SEGMENT_FIELD(SS
),
126 VMX_SEGMENT_FIELD(TR
),
127 VMX_SEGMENT_FIELD(LDTR
),
131 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
132 * away by decrementing the array size.
134 static const u32 vmx_msr_index
[] = {
136 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
138 MSR_EFER
, MSR_K6_STAR
,
140 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
142 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
146 for (i
= 0; i
< n
; ++i
)
147 wrmsrl(e
[i
].index
, e
[i
].data
);
150 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
154 for (i
= 0; i
< n
; ++i
)
155 rdmsrl(e
[i
].index
, e
[i
].data
);
158 static inline int is_page_fault(u32 intr_info
)
160 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
161 INTR_INFO_VALID_MASK
)) ==
162 (INTR_TYPE_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
165 static inline int is_no_device(u32 intr_info
)
167 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
168 INTR_INFO_VALID_MASK
)) ==
169 (INTR_TYPE_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
172 static inline int is_invalid_opcode(u32 intr_info
)
174 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
175 INTR_INFO_VALID_MASK
)) ==
176 (INTR_TYPE_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
179 static inline int is_external_interrupt(u32 intr_info
)
181 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
182 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
185 static inline int cpu_has_vmx_tpr_shadow(void)
187 return (vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
);
190 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
192 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
)));
195 static inline int cpu_has_secondary_exec_ctrls(void)
197 return (vmcs_config
.cpu_based_exec_ctrl
&
198 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
);
201 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
203 return (vmcs_config
.cpu_based_2nd_exec_ctrl
&
204 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
207 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
209 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
210 (irqchip_in_kernel(kvm
)));
213 static inline int cpu_has_vmx_vpid(void)
215 return (vmcs_config
.cpu_based_2nd_exec_ctrl
&
216 SECONDARY_EXEC_ENABLE_VPID
);
219 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
223 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
224 if (vmx
->guest_msrs
[i
].index
== msr
)
229 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
235 } operand
= { vpid
, 0, gva
};
237 asm volatile (ASM_VMX_INVVPID
238 /* CF==1 or ZF==1 --> rc = -1 */
240 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
243 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
247 i
= __find_msr_index(vmx
, msr
);
249 return &vmx
->guest_msrs
[i
];
253 static void vmcs_clear(struct vmcs
*vmcs
)
255 u64 phys_addr
= __pa(vmcs
);
258 asm volatile (ASM_VMX_VMCLEAR_RAX
"; setna %0"
259 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
262 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
266 static void __vcpu_clear(void *arg
)
268 struct vcpu_vmx
*vmx
= arg
;
269 int cpu
= raw_smp_processor_id();
271 if (vmx
->vcpu
.cpu
== cpu
)
272 vmcs_clear(vmx
->vmcs
);
273 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
274 per_cpu(current_vmcs
, cpu
) = NULL
;
275 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
278 static void vcpu_clear(struct vcpu_vmx
*vmx
)
280 if (vmx
->vcpu
.cpu
== -1)
282 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 0, 1);
286 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
291 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
294 static unsigned long vmcs_readl(unsigned long field
)
298 asm volatile (ASM_VMX_VMREAD_RDX_RAX
299 : "=a"(value
) : "d"(field
) : "cc");
303 static u16
vmcs_read16(unsigned long field
)
305 return vmcs_readl(field
);
308 static u32
vmcs_read32(unsigned long field
)
310 return vmcs_readl(field
);
313 static u64
vmcs_read64(unsigned long field
)
316 return vmcs_readl(field
);
318 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
322 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
324 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
325 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
329 static void vmcs_writel(unsigned long field
, unsigned long value
)
333 asm volatile (ASM_VMX_VMWRITE_RAX_RDX
"; setna %0"
334 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
336 vmwrite_error(field
, value
);
339 static void vmcs_write16(unsigned long field
, u16 value
)
341 vmcs_writel(field
, value
);
344 static void vmcs_write32(unsigned long field
, u32 value
)
346 vmcs_writel(field
, value
);
349 static void vmcs_write64(unsigned long field
, u64 value
)
352 vmcs_writel(field
, value
);
354 vmcs_writel(field
, value
);
356 vmcs_writel(field
+1, value
>> 32);
360 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
362 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
365 static void vmcs_set_bits(unsigned long field
, u32 mask
)
367 vmcs_writel(field
, vmcs_readl(field
) | mask
);
370 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
374 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
);
375 if (!vcpu
->fpu_active
)
376 eb
|= 1u << NM_VECTOR
;
377 if (vcpu
->guest_debug
.enabled
)
379 if (vcpu
->arch
.rmode
.active
)
381 vmcs_write32(EXCEPTION_BITMAP
, eb
);
384 static void reload_tss(void)
387 * VT restores TR but not its size. Useless.
389 struct descriptor_table gdt
;
390 struct desc_struct
*descs
;
393 descs
= (void *)gdt
.base
;
394 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
398 static void load_transition_efer(struct vcpu_vmx
*vmx
)
400 int efer_offset
= vmx
->msr_offset_efer
;
401 u64 host_efer
= vmx
->host_msrs
[efer_offset
].data
;
402 u64 guest_efer
= vmx
->guest_msrs
[efer_offset
].data
;
408 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
411 ignore_bits
= EFER_NX
| EFER_SCE
;
413 ignore_bits
|= EFER_LMA
| EFER_LME
;
414 /* SCE is meaningful only in long mode on Intel */
415 if (guest_efer
& EFER_LMA
)
416 ignore_bits
&= ~(u64
)EFER_SCE
;
418 if ((guest_efer
& ~ignore_bits
) == (host_efer
& ~ignore_bits
))
421 vmx
->host_state
.guest_efer_loaded
= 1;
422 guest_efer
&= ~ignore_bits
;
423 guest_efer
|= host_efer
& ignore_bits
;
424 wrmsrl(MSR_EFER
, guest_efer
);
425 vmx
->vcpu
.stat
.efer_reload
++;
428 static void reload_host_efer(struct vcpu_vmx
*vmx
)
430 if (vmx
->host_state
.guest_efer_loaded
) {
431 vmx
->host_state
.guest_efer_loaded
= 0;
432 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
436 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
438 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
440 if (vmx
->host_state
.loaded
)
443 vmx
->host_state
.loaded
= 1;
445 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
446 * allow segment selectors with cpl > 0 or ti == 1.
448 vmx
->host_state
.ldt_sel
= read_ldt();
449 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
450 vmx
->host_state
.fs_sel
= read_fs();
451 if (!(vmx
->host_state
.fs_sel
& 7)) {
452 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
453 vmx
->host_state
.fs_reload_needed
= 0;
455 vmcs_write16(HOST_FS_SELECTOR
, 0);
456 vmx
->host_state
.fs_reload_needed
= 1;
458 vmx
->host_state
.gs_sel
= read_gs();
459 if (!(vmx
->host_state
.gs_sel
& 7))
460 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
462 vmcs_write16(HOST_GS_SELECTOR
, 0);
463 vmx
->host_state
.gs_ldt_reload_needed
= 1;
467 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
468 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
470 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
471 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
475 if (is_long_mode(&vmx
->vcpu
))
476 save_msrs(vmx
->host_msrs
+
477 vmx
->msr_offset_kernel_gs_base
, 1);
480 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
481 load_transition_efer(vmx
);
484 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
488 if (!vmx
->host_state
.loaded
)
491 ++vmx
->vcpu
.stat
.host_state_reload
;
492 vmx
->host_state
.loaded
= 0;
493 if (vmx
->host_state
.fs_reload_needed
)
494 load_fs(vmx
->host_state
.fs_sel
);
495 if (vmx
->host_state
.gs_ldt_reload_needed
) {
496 load_ldt(vmx
->host_state
.ldt_sel
);
498 * If we have to reload gs, we must take care to
499 * preserve our gs base.
501 local_irq_save(flags
);
502 load_gs(vmx
->host_state
.gs_sel
);
504 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
506 local_irq_restore(flags
);
509 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
510 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
511 reload_host_efer(vmx
);
515 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
516 * vcpu mutex is already taken.
518 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
520 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
521 u64 phys_addr
= __pa(vmx
->vmcs
);
524 if (vcpu
->cpu
!= cpu
) {
526 kvm_migrate_apic_timer(vcpu
);
527 vpid_sync_vcpu_all(vmx
);
530 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
533 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
534 asm volatile (ASM_VMX_VMPTRLD_RAX
"; setna %0"
535 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
538 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
539 vmx
->vmcs
, phys_addr
);
542 if (vcpu
->cpu
!= cpu
) {
543 struct descriptor_table dt
;
544 unsigned long sysenter_esp
;
548 * Linux uses per-cpu TSS and GDT, so set these when switching
551 vmcs_writel(HOST_TR_BASE
, read_tr_base()); /* 22.2.4 */
553 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
555 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
556 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
559 * Make sure the time stamp counter is monotonous.
562 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
563 vmcs_write64(TSC_OFFSET
, vmcs_read64(TSC_OFFSET
) + delta
);
567 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
569 vmx_load_host_state(to_vmx(vcpu
));
572 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
574 if (vcpu
->fpu_active
)
576 vcpu
->fpu_active
= 1;
577 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
578 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
579 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
580 update_exception_bitmap(vcpu
);
583 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
585 if (!vcpu
->fpu_active
)
587 vcpu
->fpu_active
= 0;
588 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
589 update_exception_bitmap(vcpu
);
592 static void vmx_vcpu_decache(struct kvm_vcpu
*vcpu
)
594 vcpu_clear(to_vmx(vcpu
));
597 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
599 return vmcs_readl(GUEST_RFLAGS
);
602 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
604 if (vcpu
->arch
.rmode
.active
)
605 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
606 vmcs_writel(GUEST_RFLAGS
, rflags
);
609 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
612 u32 interruptibility
;
614 rip
= vmcs_readl(GUEST_RIP
);
615 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
616 vmcs_writel(GUEST_RIP
, rip
);
619 * We emulated an instruction, so temporary interrupt blocking
620 * should be removed, if set.
622 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
623 if (interruptibility
& 3)
624 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
625 interruptibility
& ~3);
626 vcpu
->arch
.interrupt_window_open
= 1;
629 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
630 bool has_error_code
, u32 error_code
)
632 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
633 nr
| INTR_TYPE_EXCEPTION
634 | (has_error_code
? INTR_INFO_DELIVER_CODE_MASK
: 0)
635 | INTR_INFO_VALID_MASK
);
637 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
640 static bool vmx_exception_injected(struct kvm_vcpu
*vcpu
)
642 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
644 return !(vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
648 * Swap MSR entry in host/guest MSR entry array.
651 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
653 struct kvm_msr_entry tmp
;
655 tmp
= vmx
->guest_msrs
[to
];
656 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
657 vmx
->guest_msrs
[from
] = tmp
;
658 tmp
= vmx
->host_msrs
[to
];
659 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
660 vmx
->host_msrs
[from
] = tmp
;
665 * Set up the vmcs to automatically save and restore system
666 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
667 * mode, as fiddling with msrs is very expensive.
669 static void setup_msrs(struct vcpu_vmx
*vmx
)
673 vmx_load_host_state(vmx
);
676 if (is_long_mode(&vmx
->vcpu
)) {
679 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
681 move_msr_up(vmx
, index
, save_nmsrs
++);
682 index
= __find_msr_index(vmx
, MSR_LSTAR
);
684 move_msr_up(vmx
, index
, save_nmsrs
++);
685 index
= __find_msr_index(vmx
, MSR_CSTAR
);
687 move_msr_up(vmx
, index
, save_nmsrs
++);
688 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
690 move_msr_up(vmx
, index
, save_nmsrs
++);
692 * MSR_K6_STAR is only needed on long mode guests, and only
693 * if efer.sce is enabled.
695 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
696 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
697 move_msr_up(vmx
, index
, save_nmsrs
++);
700 vmx
->save_nmsrs
= save_nmsrs
;
703 vmx
->msr_offset_kernel_gs_base
=
704 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
706 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
710 * reads and returns guest's timestamp counter "register"
711 * guest_tsc = host_tsc + tsc_offset -- 21.3
713 static u64
guest_read_tsc(void)
715 u64 host_tsc
, tsc_offset
;
718 tsc_offset
= vmcs_read64(TSC_OFFSET
);
719 return host_tsc
+ tsc_offset
;
723 * writes 'guest_tsc' into guest's timestamp counter "register"
724 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
726 static void guest_write_tsc(u64 guest_tsc
)
731 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
735 * Reads an msr value (of 'msr_index') into 'pdata'.
736 * Returns 0 on success, non-0 otherwise.
737 * Assumes vcpu_load() was already called.
739 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
742 struct kvm_msr_entry
*msr
;
745 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
752 data
= vmcs_readl(GUEST_FS_BASE
);
755 data
= vmcs_readl(GUEST_GS_BASE
);
758 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
760 case MSR_IA32_TIME_STAMP_COUNTER
:
761 data
= guest_read_tsc();
763 case MSR_IA32_SYSENTER_CS
:
764 data
= vmcs_read32(GUEST_SYSENTER_CS
);
766 case MSR_IA32_SYSENTER_EIP
:
767 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
769 case MSR_IA32_SYSENTER_ESP
:
770 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
773 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
778 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
786 * Writes msr value into into the appropriate "register".
787 * Returns 0 on success, non-0 otherwise.
788 * Assumes vcpu_load() was already called.
790 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
792 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
793 struct kvm_msr_entry
*msr
;
799 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
800 if (vmx
->host_state
.loaded
) {
801 reload_host_efer(vmx
);
802 load_transition_efer(vmx
);
806 vmcs_writel(GUEST_FS_BASE
, data
);
809 vmcs_writel(GUEST_GS_BASE
, data
);
812 case MSR_IA32_SYSENTER_CS
:
813 vmcs_write32(GUEST_SYSENTER_CS
, data
);
815 case MSR_IA32_SYSENTER_EIP
:
816 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
818 case MSR_IA32_SYSENTER_ESP
:
819 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
821 case MSR_IA32_TIME_STAMP_COUNTER
:
822 guest_write_tsc(data
);
825 msr
= find_msr_entry(vmx
, msr_index
);
828 if (vmx
->host_state
.loaded
)
829 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
832 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
839 * Sync the rsp and rip registers into the vcpu structure. This allows
840 * registers to be accessed by indexing vcpu->arch.regs.
842 static void vcpu_load_rsp_rip(struct kvm_vcpu
*vcpu
)
844 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
845 vcpu
->arch
.rip
= vmcs_readl(GUEST_RIP
);
849 * Syncs rsp and rip back into the vmcs. Should be called after possible
852 static void vcpu_put_rsp_rip(struct kvm_vcpu
*vcpu
)
854 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
855 vmcs_writel(GUEST_RIP
, vcpu
->arch
.rip
);
858 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_debug_guest
*dbg
)
860 unsigned long dr7
= 0x400;
863 old_singlestep
= vcpu
->guest_debug
.singlestep
;
865 vcpu
->guest_debug
.enabled
= dbg
->enabled
;
866 if (vcpu
->guest_debug
.enabled
) {
869 dr7
|= 0x200; /* exact */
870 for (i
= 0; i
< 4; ++i
) {
871 if (!dbg
->breakpoints
[i
].enabled
)
873 vcpu
->guest_debug
.bp
[i
] = dbg
->breakpoints
[i
].address
;
874 dr7
|= 2 << (i
*2); /* global enable */
875 dr7
|= 0 << (i
*4+16); /* execution breakpoint */
878 vcpu
->guest_debug
.singlestep
= dbg
->singlestep
;
880 vcpu
->guest_debug
.singlestep
= 0;
882 if (old_singlestep
&& !vcpu
->guest_debug
.singlestep
) {
885 flags
= vmcs_readl(GUEST_RFLAGS
);
886 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
887 vmcs_writel(GUEST_RFLAGS
, flags
);
890 update_exception_bitmap(vcpu
);
891 vmcs_writel(GUEST_DR7
, dr7
);
896 static int vmx_get_irq(struct kvm_vcpu
*vcpu
)
898 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
901 idtv_info_field
= vmx
->idt_vectoring_info
;
902 if (idtv_info_field
& INTR_INFO_VALID_MASK
) {
903 if (is_external_interrupt(idtv_info_field
))
904 return idtv_info_field
& VECTORING_INFO_VECTOR_MASK
;
906 printk(KERN_DEBUG
"pending exception: not handled yet\n");
911 static __init
int cpu_has_kvm_support(void)
913 unsigned long ecx
= cpuid_ecx(1);
914 return test_bit(5, &ecx
); /* CPUID.1:ECX.VMX[bit 5] -> VT */
917 static __init
int vmx_disabled_by_bios(void)
921 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
922 return (msr
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
923 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
924 == MSR_IA32_FEATURE_CONTROL_LOCKED
;
925 /* locked but not enabled */
928 static void hardware_enable(void *garbage
)
930 int cpu
= raw_smp_processor_id();
931 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
934 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
935 if ((old
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
936 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
937 != (MSR_IA32_FEATURE_CONTROL_LOCKED
|
938 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
939 /* enable and lock */
940 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
941 MSR_IA32_FEATURE_CONTROL_LOCKED
|
942 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
);
943 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
944 asm volatile (ASM_VMX_VMXON_RAX
: : "a"(&phys_addr
), "m"(phys_addr
)
948 static void hardware_disable(void *garbage
)
950 asm volatile (ASM_VMX_VMXOFF
: : : "cc");
953 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
954 u32 msr
, u32
*result
)
956 u32 vmx_msr_low
, vmx_msr_high
;
957 u32 ctl
= ctl_min
| ctl_opt
;
959 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
961 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
962 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
964 /* Ensure minimum (required) set of control bits are supported. */
972 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
974 u32 vmx_msr_low
, vmx_msr_high
;
976 u32 _pin_based_exec_control
= 0;
977 u32 _cpu_based_exec_control
= 0;
978 u32 _cpu_based_2nd_exec_control
= 0;
979 u32 _vmexit_control
= 0;
980 u32 _vmentry_control
= 0;
982 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
984 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
985 &_pin_based_exec_control
) < 0)
988 min
= CPU_BASED_HLT_EXITING
|
990 CPU_BASED_CR8_LOAD_EXITING
|
991 CPU_BASED_CR8_STORE_EXITING
|
993 CPU_BASED_USE_IO_BITMAPS
|
994 CPU_BASED_MOV_DR_EXITING
|
995 CPU_BASED_USE_TSC_OFFSETING
;
996 opt
= CPU_BASED_TPR_SHADOW
|
997 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
998 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
999 &_cpu_based_exec_control
) < 0)
1001 #ifdef CONFIG_X86_64
1002 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1003 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1004 ~CPU_BASED_CR8_STORE_EXITING
;
1006 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1008 opt
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1009 SECONDARY_EXEC_WBINVD_EXITING
|
1010 SECONDARY_EXEC_ENABLE_VPID
;
1011 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS2
,
1012 &_cpu_based_2nd_exec_control
) < 0)
1015 #ifndef CONFIG_X86_64
1016 if (!(_cpu_based_2nd_exec_control
&
1017 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1018 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1022 #ifdef CONFIG_X86_64
1023 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1026 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1027 &_vmexit_control
) < 0)
1031 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1032 &_vmentry_control
) < 0)
1035 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1037 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1038 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1041 #ifdef CONFIG_X86_64
1042 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1043 if (vmx_msr_high
& (1u<<16))
1047 /* Require Write-Back (WB) memory type for VMCS accesses. */
1048 if (((vmx_msr_high
>> 18) & 15) != 6)
1051 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1052 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1053 vmcs_conf
->revision_id
= vmx_msr_low
;
1055 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1056 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1057 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1058 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1059 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1064 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1066 int node
= cpu_to_node(cpu
);
1070 pages
= alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1073 vmcs
= page_address(pages
);
1074 memset(vmcs
, 0, vmcs_config
.size
);
1075 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1079 static struct vmcs
*alloc_vmcs(void)
1081 return alloc_vmcs_cpu(raw_smp_processor_id());
1084 static void free_vmcs(struct vmcs
*vmcs
)
1086 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1089 static void free_kvm_area(void)
1093 for_each_online_cpu(cpu
)
1094 free_vmcs(per_cpu(vmxarea
, cpu
));
1097 static __init
int alloc_kvm_area(void)
1101 for_each_online_cpu(cpu
) {
1104 vmcs
= alloc_vmcs_cpu(cpu
);
1110 per_cpu(vmxarea
, cpu
) = vmcs
;
1115 static __init
int hardware_setup(void)
1117 if (setup_vmcs_config(&vmcs_config
) < 0)
1120 if (boot_cpu_has(X86_FEATURE_NX
))
1121 kvm_enable_efer_bits(EFER_NX
);
1123 return alloc_kvm_area();
1126 static __exit
void hardware_unsetup(void)
1131 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1133 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1135 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1136 vmcs_write16(sf
->selector
, save
->selector
);
1137 vmcs_writel(sf
->base
, save
->base
);
1138 vmcs_write32(sf
->limit
, save
->limit
);
1139 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1141 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1143 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1147 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1149 unsigned long flags
;
1151 vcpu
->arch
.rmode
.active
= 0;
1153 vmcs_writel(GUEST_TR_BASE
, vcpu
->arch
.rmode
.tr
.base
);
1154 vmcs_write32(GUEST_TR_LIMIT
, vcpu
->arch
.rmode
.tr
.limit
);
1155 vmcs_write32(GUEST_TR_AR_BYTES
, vcpu
->arch
.rmode
.tr
.ar
);
1157 flags
= vmcs_readl(GUEST_RFLAGS
);
1158 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1159 flags
|= (vcpu
->arch
.rmode
.save_iopl
<< IOPL_SHIFT
);
1160 vmcs_writel(GUEST_RFLAGS
, flags
);
1162 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1163 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1165 update_exception_bitmap(vcpu
);
1167 fix_pmode_dataseg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1168 fix_pmode_dataseg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1169 fix_pmode_dataseg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1170 fix_pmode_dataseg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1172 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1173 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1175 vmcs_write16(GUEST_CS_SELECTOR
,
1176 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1177 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1180 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1182 if (!kvm
->arch
.tss_addr
) {
1183 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+
1184 kvm
->memslots
[0].npages
- 3;
1185 return base_gfn
<< PAGE_SHIFT
;
1187 return kvm
->arch
.tss_addr
;
1190 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1192 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1194 save
->selector
= vmcs_read16(sf
->selector
);
1195 save
->base
= vmcs_readl(sf
->base
);
1196 save
->limit
= vmcs_read32(sf
->limit
);
1197 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1198 vmcs_write16(sf
->selector
, save
->base
>> 4);
1199 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1200 vmcs_write32(sf
->limit
, 0xffff);
1201 vmcs_write32(sf
->ar_bytes
, 0xf3);
1204 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1206 unsigned long flags
;
1208 vcpu
->arch
.rmode
.active
= 1;
1210 vcpu
->arch
.rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1211 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1213 vcpu
->arch
.rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1214 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1216 vcpu
->arch
.rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1217 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1219 flags
= vmcs_readl(GUEST_RFLAGS
);
1220 vcpu
->arch
.rmode
.save_iopl
1221 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1223 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1225 vmcs_writel(GUEST_RFLAGS
, flags
);
1226 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1227 update_exception_bitmap(vcpu
);
1229 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1230 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1231 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1233 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1234 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1235 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1236 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1237 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1239 fix_rmode_seg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1240 fix_rmode_seg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1241 fix_rmode_seg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1242 fix_rmode_seg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1244 kvm_mmu_reset_context(vcpu
);
1245 init_rmode_tss(vcpu
->kvm
);
1248 #ifdef CONFIG_X86_64
1250 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1254 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1255 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1256 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1258 vmcs_write32(GUEST_TR_AR_BYTES
,
1259 (guest_tr_ar
& ~AR_TYPE_MASK
)
1260 | AR_TYPE_BUSY_64_TSS
);
1263 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1265 find_msr_entry(to_vmx(vcpu
), MSR_EFER
)->data
|= EFER_LMA
| EFER_LME
;
1266 vmcs_write32(VM_ENTRY_CONTROLS
,
1267 vmcs_read32(VM_ENTRY_CONTROLS
)
1268 | VM_ENTRY_IA32E_MODE
);
1271 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1273 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1275 vmcs_write32(VM_ENTRY_CONTROLS
,
1276 vmcs_read32(VM_ENTRY_CONTROLS
)
1277 & ~VM_ENTRY_IA32E_MODE
);
1282 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1284 vpid_sync_vcpu_all(to_vmx(vcpu
));
1287 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1289 vcpu
->arch
.cr4
&= KVM_GUEST_CR4_MASK
;
1290 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1293 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1295 vmx_fpu_deactivate(vcpu
);
1297 if (vcpu
->arch
.rmode
.active
&& (cr0
& X86_CR0_PE
))
1300 if (!vcpu
->arch
.rmode
.active
&& !(cr0
& X86_CR0_PE
))
1303 #ifdef CONFIG_X86_64
1304 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1305 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1307 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1312 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1313 vmcs_writel(GUEST_CR0
,
1314 (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
);
1315 vcpu
->arch
.cr0
= cr0
;
1317 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1318 vmx_fpu_activate(vcpu
);
1321 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1323 vmx_flush_tlb(vcpu
);
1324 vmcs_writel(GUEST_CR3
, cr3
);
1325 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1326 vmx_fpu_deactivate(vcpu
);
1329 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1331 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1332 vmcs_writel(GUEST_CR4
, cr4
| (vcpu
->arch
.rmode
.active
?
1333 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
));
1334 vcpu
->arch
.cr4
= cr4
;
1337 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1339 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1340 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1342 vcpu
->arch
.shadow_efer
= efer
;
1345 if (efer
& EFER_LMA
) {
1346 vmcs_write32(VM_ENTRY_CONTROLS
,
1347 vmcs_read32(VM_ENTRY_CONTROLS
) |
1348 VM_ENTRY_IA32E_MODE
);
1352 vmcs_write32(VM_ENTRY_CONTROLS
,
1353 vmcs_read32(VM_ENTRY_CONTROLS
) &
1354 ~VM_ENTRY_IA32E_MODE
);
1356 msr
->data
= efer
& ~EFER_LME
;
1361 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1363 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1365 return vmcs_readl(sf
->base
);
1368 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1369 struct kvm_segment
*var
, int seg
)
1371 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1374 var
->base
= vmcs_readl(sf
->base
);
1375 var
->limit
= vmcs_read32(sf
->limit
);
1376 var
->selector
= vmcs_read16(sf
->selector
);
1377 ar
= vmcs_read32(sf
->ar_bytes
);
1378 if (ar
& AR_UNUSABLE_MASK
)
1380 var
->type
= ar
& 15;
1381 var
->s
= (ar
>> 4) & 1;
1382 var
->dpl
= (ar
>> 5) & 3;
1383 var
->present
= (ar
>> 7) & 1;
1384 var
->avl
= (ar
>> 12) & 1;
1385 var
->l
= (ar
>> 13) & 1;
1386 var
->db
= (ar
>> 14) & 1;
1387 var
->g
= (ar
>> 15) & 1;
1388 var
->unusable
= (ar
>> 16) & 1;
1391 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1398 ar
= var
->type
& 15;
1399 ar
|= (var
->s
& 1) << 4;
1400 ar
|= (var
->dpl
& 3) << 5;
1401 ar
|= (var
->present
& 1) << 7;
1402 ar
|= (var
->avl
& 1) << 12;
1403 ar
|= (var
->l
& 1) << 13;
1404 ar
|= (var
->db
& 1) << 14;
1405 ar
|= (var
->g
& 1) << 15;
1407 if (ar
== 0) /* a 0 value means unusable */
1408 ar
= AR_UNUSABLE_MASK
;
1413 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1414 struct kvm_segment
*var
, int seg
)
1416 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1419 if (vcpu
->arch
.rmode
.active
&& seg
== VCPU_SREG_TR
) {
1420 vcpu
->arch
.rmode
.tr
.selector
= var
->selector
;
1421 vcpu
->arch
.rmode
.tr
.base
= var
->base
;
1422 vcpu
->arch
.rmode
.tr
.limit
= var
->limit
;
1423 vcpu
->arch
.rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1426 vmcs_writel(sf
->base
, var
->base
);
1427 vmcs_write32(sf
->limit
, var
->limit
);
1428 vmcs_write16(sf
->selector
, var
->selector
);
1429 if (vcpu
->arch
.rmode
.active
&& var
->s
) {
1431 * Hack real-mode segments into vm86 compatibility.
1433 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1434 vmcs_writel(sf
->base
, 0xf0000);
1437 ar
= vmx_segment_access_rights(var
);
1438 vmcs_write32(sf
->ar_bytes
, ar
);
1441 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1443 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1445 *db
= (ar
>> 14) & 1;
1446 *l
= (ar
>> 13) & 1;
1449 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1451 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1452 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1455 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1457 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1458 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1461 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1463 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1464 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1467 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1469 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1470 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1473 static int init_rmode_tss(struct kvm
*kvm
)
1475 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
1480 down_read(&kvm
->slots_lock
);
1481 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1484 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
1485 r
= kvm_write_guest_page(kvm
, fn
++, &data
, 0x66, sizeof(u16
));
1488 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
1491 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1495 r
= kvm_write_guest_page(kvm
, fn
, &data
,
1496 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
1503 up_read(&kvm
->slots_lock
);
1507 static void seg_setup(int seg
)
1509 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1511 vmcs_write16(sf
->selector
, 0);
1512 vmcs_writel(sf
->base
, 0);
1513 vmcs_write32(sf
->limit
, 0xffff);
1514 vmcs_write32(sf
->ar_bytes
, 0x93);
1517 static int alloc_apic_access_page(struct kvm
*kvm
)
1519 struct kvm_userspace_memory_region kvm_userspace_mem
;
1522 down_write(&kvm
->slots_lock
);
1523 if (kvm
->arch
.apic_access_page
)
1525 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
1526 kvm_userspace_mem
.flags
= 0;
1527 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
1528 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
1529 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
1533 down_read(¤t
->mm
->mmap_sem
);
1534 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
1535 up_read(¤t
->mm
->mmap_sem
);
1537 up_write(&kvm
->slots_lock
);
1541 static void allocate_vpid(struct vcpu_vmx
*vmx
)
1546 if (!enable_vpid
|| !cpu_has_vmx_vpid())
1548 spin_lock(&vmx_vpid_lock
);
1549 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
1550 if (vpid
< VMX_NR_VPIDS
) {
1552 __set_bit(vpid
, vmx_vpid_bitmap
);
1554 spin_unlock(&vmx_vpid_lock
);
1558 * Sets up the vmcs for emulated real mode.
1560 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
1562 u32 host_sysenter_cs
;
1565 struct descriptor_table dt
;
1567 unsigned long kvm_vmx_return
;
1571 vmcs_write64(IO_BITMAP_A
, page_to_phys(vmx_io_bitmap_a
));
1572 vmcs_write64(IO_BITMAP_B
, page_to_phys(vmx_io_bitmap_b
));
1574 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
1577 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
1578 vmcs_config
.pin_based_exec_ctrl
);
1580 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
1581 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
1582 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1583 #ifdef CONFIG_X86_64
1584 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
1585 CPU_BASED_CR8_LOAD_EXITING
;
1588 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
1590 if (cpu_has_secondary_exec_ctrls()) {
1591 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
1592 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
1594 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1596 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
1597 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
1600 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
1601 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
1602 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
1604 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
1605 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
1606 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1608 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
1609 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1610 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1611 vmcs_write16(HOST_FS_SELECTOR
, read_fs()); /* 22.2.4 */
1612 vmcs_write16(HOST_GS_SELECTOR
, read_gs()); /* 22.2.4 */
1613 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1614 #ifdef CONFIG_X86_64
1615 rdmsrl(MSR_FS_BASE
, a
);
1616 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
1617 rdmsrl(MSR_GS_BASE
, a
);
1618 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
1620 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
1621 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
1624 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
1627 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
1629 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
1630 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
1631 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
1632 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
1635 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
1636 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
1637 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
1638 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
1639 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
1640 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
1642 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
1643 u32 index
= vmx_msr_index
[i
];
1644 u32 data_low
, data_high
;
1648 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
1650 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
1652 data
= data_low
| ((u64
)data_high
<< 32);
1653 vmx
->host_msrs
[j
].index
= index
;
1654 vmx
->host_msrs
[j
].reserved
= 0;
1655 vmx
->host_msrs
[j
].data
= data
;
1656 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
1660 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
1662 /* 22.2.1, 20.8.1 */
1663 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
1665 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
1666 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
1672 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
1674 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1678 if (!init_rmode_tss(vmx
->vcpu
.kvm
)) {
1683 vmx
->vcpu
.arch
.rmode
.active
= 0;
1685 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
1686 set_cr8(&vmx
->vcpu
, 0);
1687 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1688 if (vmx
->vcpu
.vcpu_id
== 0)
1689 msr
|= MSR_IA32_APICBASE_BSP
;
1690 kvm_set_apic_base(&vmx
->vcpu
, msr
);
1692 fx_init(&vmx
->vcpu
);
1695 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1696 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1698 if (vmx
->vcpu
.vcpu_id
== 0) {
1699 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
1700 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
1702 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
1703 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
1705 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1706 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1708 seg_setup(VCPU_SREG_DS
);
1709 seg_setup(VCPU_SREG_ES
);
1710 seg_setup(VCPU_SREG_FS
);
1711 seg_setup(VCPU_SREG_GS
);
1712 seg_setup(VCPU_SREG_SS
);
1714 vmcs_write16(GUEST_TR_SELECTOR
, 0);
1715 vmcs_writel(GUEST_TR_BASE
, 0);
1716 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
1717 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1719 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
1720 vmcs_writel(GUEST_LDTR_BASE
, 0);
1721 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
1722 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
1724 vmcs_write32(GUEST_SYSENTER_CS
, 0);
1725 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
1726 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
1728 vmcs_writel(GUEST_RFLAGS
, 0x02);
1729 if (vmx
->vcpu
.vcpu_id
== 0)
1730 vmcs_writel(GUEST_RIP
, 0xfff0);
1732 vmcs_writel(GUEST_RIP
, 0);
1733 vmcs_writel(GUEST_RSP
, 0);
1735 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1736 vmcs_writel(GUEST_DR7
, 0x400);
1738 vmcs_writel(GUEST_GDTR_BASE
, 0);
1739 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
1741 vmcs_writel(GUEST_IDTR_BASE
, 0);
1742 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
1744 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
1745 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
1746 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
1750 /* Special registers */
1751 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
1755 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
1757 if (cpu_has_vmx_tpr_shadow()) {
1758 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
1759 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
1760 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
1761 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
1762 vmcs_write32(TPR_THRESHOLD
, 0);
1765 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
1766 vmcs_write64(APIC_ACCESS_ADDR
,
1767 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
1770 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
1772 vmx
->vcpu
.arch
.cr0
= 0x60000010;
1773 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
1774 vmx_set_cr4(&vmx
->vcpu
, 0);
1775 vmx_set_efer(&vmx
->vcpu
, 0);
1776 vmx_fpu_activate(&vmx
->vcpu
);
1777 update_exception_bitmap(&vmx
->vcpu
);
1779 vpid_sync_vcpu_all(vmx
);
1787 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
, int irq
)
1789 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1791 if (vcpu
->arch
.rmode
.active
) {
1792 vmx
->rmode
.irq
.pending
= true;
1793 vmx
->rmode
.irq
.vector
= irq
;
1794 vmx
->rmode
.irq
.rip
= vmcs_readl(GUEST_RIP
);
1795 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
1796 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
1797 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
1798 vmcs_writel(GUEST_RIP
, vmx
->rmode
.irq
.rip
- 1);
1801 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
1802 irq
| INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1805 static void kvm_do_inject_irq(struct kvm_vcpu
*vcpu
)
1807 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
1808 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
1809 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
1811 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
1812 if (!vcpu
->arch
.irq_pending
[word_index
])
1813 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
1814 vmx_inject_irq(vcpu
, irq
);
1818 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
1819 struct kvm_run
*kvm_run
)
1821 u32 cpu_based_vm_exec_control
;
1823 vcpu
->arch
.interrupt_window_open
=
1824 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
1825 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0);
1827 if (vcpu
->arch
.interrupt_window_open
&&
1828 vcpu
->arch
.irq_summary
&&
1829 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
) & INTR_INFO_VALID_MASK
))
1831 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1833 kvm_do_inject_irq(vcpu
);
1835 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
1836 if (!vcpu
->arch
.interrupt_window_open
&&
1837 (vcpu
->arch
.irq_summary
|| kvm_run
->request_interrupt_window
))
1839 * Interrupts blocked. Wait for unblock.
1841 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
1843 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
1844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
1847 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
1850 struct kvm_userspace_memory_region tss_mem
= {
1852 .guest_phys_addr
= addr
,
1853 .memory_size
= PAGE_SIZE
* 3,
1857 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
1860 kvm
->arch
.tss_addr
= addr
;
1864 static void kvm_guest_debug_pre(struct kvm_vcpu
*vcpu
)
1866 struct kvm_guest_debug
*dbg
= &vcpu
->guest_debug
;
1868 set_debugreg(dbg
->bp
[0], 0);
1869 set_debugreg(dbg
->bp
[1], 1);
1870 set_debugreg(dbg
->bp
[2], 2);
1871 set_debugreg(dbg
->bp
[3], 3);
1873 if (dbg
->singlestep
) {
1874 unsigned long flags
;
1876 flags
= vmcs_readl(GUEST_RFLAGS
);
1877 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1878 vmcs_writel(GUEST_RFLAGS
, flags
);
1882 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
1883 int vec
, u32 err_code
)
1885 if (!vcpu
->arch
.rmode
.active
)
1889 * Instruction with address size override prefix opcode 0x67
1890 * Cause the #SS fault with 0 error code in VM86 mode.
1892 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
1893 if (emulate_instruction(vcpu
, NULL
, 0, 0, 0) == EMULATE_DONE
)
1898 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1900 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1901 u32 intr_info
, error_code
;
1902 unsigned long cr2
, rip
;
1904 enum emulation_result er
;
1906 vect_info
= vmx
->idt_vectoring_info
;
1907 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
1909 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
1910 !is_page_fault(intr_info
))
1911 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
1912 "intr info 0x%x\n", __FUNCTION__
, vect_info
, intr_info
);
1914 if (!irqchip_in_kernel(vcpu
->kvm
) && is_external_interrupt(vect_info
)) {
1915 int irq
= vect_info
& VECTORING_INFO_VECTOR_MASK
;
1916 set_bit(irq
, vcpu
->arch
.irq_pending
);
1917 set_bit(irq
/ BITS_PER_LONG
, &vcpu
->arch
.irq_summary
);
1920 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == 0x200) /* nmi */
1921 return 1; /* already handled by vmx_vcpu_run() */
1923 if (is_no_device(intr_info
)) {
1924 vmx_fpu_activate(vcpu
);
1928 if (is_invalid_opcode(intr_info
)) {
1929 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1930 if (er
!= EMULATE_DONE
)
1931 kvm_queue_exception(vcpu
, UD_VECTOR
);
1936 rip
= vmcs_readl(GUEST_RIP
);
1937 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
1938 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
1939 if (is_page_fault(intr_info
)) {
1940 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
1941 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
1944 if (vcpu
->arch
.rmode
.active
&&
1945 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
1947 if (vcpu
->arch
.halt_request
) {
1948 vcpu
->arch
.halt_request
= 0;
1949 return kvm_emulate_halt(vcpu
);
1954 if ((intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
)) ==
1955 (INTR_TYPE_EXCEPTION
| 1)) {
1956 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1959 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
1960 kvm_run
->ex
.exception
= intr_info
& INTR_INFO_VECTOR_MASK
;
1961 kvm_run
->ex
.error_code
= error_code
;
1965 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
1966 struct kvm_run
*kvm_run
)
1968 ++vcpu
->stat
.irq_exits
;
1972 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1974 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1978 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1980 unsigned long exit_qualification
;
1981 int size
, down
, in
, string
, rep
;
1984 ++vcpu
->stat
.io_exits
;
1985 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
1986 string
= (exit_qualification
& 16) != 0;
1989 if (emulate_instruction(vcpu
,
1990 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1995 size
= (exit_qualification
& 7) + 1;
1996 in
= (exit_qualification
& 8) != 0;
1997 down
= (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_DF
) != 0;
1998 rep
= (exit_qualification
& 32) != 0;
1999 port
= exit_qualification
>> 16;
2001 return kvm_emulate_pio(vcpu
, kvm_run
, in
, size
, port
);
2005 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2008 * Patch in the VMCALL instruction:
2010 hypercall
[0] = 0x0f;
2011 hypercall
[1] = 0x01;
2012 hypercall
[2] = 0xc1;
2015 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2017 unsigned long exit_qualification
;
2021 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2022 cr
= exit_qualification
& 15;
2023 reg
= (exit_qualification
>> 8) & 15;
2024 switch ((exit_qualification
>> 4) & 3) {
2025 case 0: /* mov to cr */
2028 vcpu_load_rsp_rip(vcpu
);
2029 set_cr0(vcpu
, vcpu
->arch
.regs
[reg
]);
2030 skip_emulated_instruction(vcpu
);
2033 vcpu_load_rsp_rip(vcpu
);
2034 set_cr3(vcpu
, vcpu
->arch
.regs
[reg
]);
2035 skip_emulated_instruction(vcpu
);
2038 vcpu_load_rsp_rip(vcpu
);
2039 set_cr4(vcpu
, vcpu
->arch
.regs
[reg
]);
2040 skip_emulated_instruction(vcpu
);
2043 vcpu_load_rsp_rip(vcpu
);
2044 set_cr8(vcpu
, vcpu
->arch
.regs
[reg
]);
2045 skip_emulated_instruction(vcpu
);
2046 if (irqchip_in_kernel(vcpu
->kvm
))
2048 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2053 vcpu_load_rsp_rip(vcpu
);
2054 vmx_fpu_deactivate(vcpu
);
2055 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2056 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2057 vmx_fpu_activate(vcpu
);
2058 skip_emulated_instruction(vcpu
);
2060 case 1: /*mov from cr*/
2063 vcpu_load_rsp_rip(vcpu
);
2064 vcpu
->arch
.regs
[reg
] = vcpu
->arch
.cr3
;
2065 vcpu_put_rsp_rip(vcpu
);
2066 skip_emulated_instruction(vcpu
);
2069 vcpu_load_rsp_rip(vcpu
);
2070 vcpu
->arch
.regs
[reg
] = get_cr8(vcpu
);
2071 vcpu_put_rsp_rip(vcpu
);
2072 skip_emulated_instruction(vcpu
);
2077 lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
2079 skip_emulated_instruction(vcpu
);
2084 kvm_run
->exit_reason
= 0;
2085 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
2086 (int)(exit_qualification
>> 4) & 3, cr
);
2090 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2092 unsigned long exit_qualification
;
2097 * FIXME: this code assumes the host is debugging the guest.
2098 * need to deal with guest debugging itself too.
2100 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2101 dr
= exit_qualification
& 7;
2102 reg
= (exit_qualification
>> 8) & 15;
2103 vcpu_load_rsp_rip(vcpu
);
2104 if (exit_qualification
& 16) {
2116 vcpu
->arch
.regs
[reg
] = val
;
2120 vcpu_put_rsp_rip(vcpu
);
2121 skip_emulated_instruction(vcpu
);
2125 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2127 kvm_emulate_cpuid(vcpu
);
2131 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2133 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2136 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
2137 kvm_inject_gp(vcpu
, 0);
2141 /* FIXME: handling of bits 32:63 of rax, rdx */
2142 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
2143 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
2144 skip_emulated_instruction(vcpu
);
2148 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2150 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2151 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
2152 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2154 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
2155 kvm_inject_gp(vcpu
, 0);
2159 skip_emulated_instruction(vcpu
);
2163 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
,
2164 struct kvm_run
*kvm_run
)
2169 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
2170 struct kvm_run
*kvm_run
)
2172 u32 cpu_based_vm_exec_control
;
2174 /* clear pending irq */
2175 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2176 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
2177 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2179 * If the user space waits to inject interrupts, exit as soon as
2182 if (kvm_run
->request_interrupt_window
&&
2183 !vcpu
->arch
.irq_summary
) {
2184 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2185 ++vcpu
->stat
.irq_window_exits
;
2191 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2193 skip_emulated_instruction(vcpu
);
2194 return kvm_emulate_halt(vcpu
);
2197 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2199 skip_emulated_instruction(vcpu
);
2200 kvm_emulate_hypercall(vcpu
);
2204 static int handle_wbinvd(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2206 skip_emulated_instruction(vcpu
);
2207 /* TODO: Add support for VT-d/pass-through device */
2211 static int handle_apic_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2213 u64 exit_qualification
;
2214 enum emulation_result er
;
2215 unsigned long offset
;
2217 exit_qualification
= vmcs_read64(EXIT_QUALIFICATION
);
2218 offset
= exit_qualification
& 0xffful
;
2220 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
2222 if (er
!= EMULATE_DONE
) {
2224 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2232 * The exit handlers return 1 if the exit was handled fully and guest execution
2233 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2234 * to be done to userspace and return 0.
2236 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
2237 struct kvm_run
*kvm_run
) = {
2238 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
2239 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
2240 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
2241 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
2242 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
2243 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
2244 [EXIT_REASON_CPUID
] = handle_cpuid
,
2245 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
2246 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
2247 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
2248 [EXIT_REASON_HLT
] = handle_halt
,
2249 [EXIT_REASON_VMCALL
] = handle_vmcall
,
2250 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
2251 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
2252 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
2255 static const int kvm_vmx_max_exit_handlers
=
2256 ARRAY_SIZE(kvm_vmx_exit_handlers
);
2259 * The guest has exited. See if we can fix it or if we need userspace
2262 static int kvm_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2264 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
2265 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2266 u32 vectoring_info
= vmx
->idt_vectoring_info
;
2268 if (unlikely(vmx
->fail
)) {
2269 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2270 kvm_run
->fail_entry
.hardware_entry_failure_reason
2271 = vmcs_read32(VM_INSTRUCTION_ERROR
);
2275 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
2276 exit_reason
!= EXIT_REASON_EXCEPTION_NMI
)
2277 printk(KERN_WARNING
"%s: unexpected, valid vectoring info and "
2278 "exit reason is 0x%x\n", __FUNCTION__
, exit_reason
);
2279 if (exit_reason
< kvm_vmx_max_exit_handlers
2280 && kvm_vmx_exit_handlers
[exit_reason
])
2281 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
2283 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2284 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
2289 static void update_tpr_threshold(struct kvm_vcpu
*vcpu
)
2293 if (!vm_need_tpr_shadow(vcpu
->kvm
))
2296 if (!kvm_lapic_enabled(vcpu
) ||
2297 ((max_irr
= kvm_lapic_find_highest_irr(vcpu
)) == -1)) {
2298 vmcs_write32(TPR_THRESHOLD
, 0);
2302 tpr
= (kvm_lapic_get_cr8(vcpu
) & 0x0f) << 4;
2303 vmcs_write32(TPR_THRESHOLD
, (max_irr
> tpr
) ? tpr
>> 4 : max_irr
>> 4);
2306 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2308 u32 cpu_based_vm_exec_control
;
2310 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2311 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2312 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2315 static void vmx_intr_assist(struct kvm_vcpu
*vcpu
)
2317 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2318 u32 idtv_info_field
, intr_info_field
;
2319 int has_ext_irq
, interrupt_window_open
;
2322 update_tpr_threshold(vcpu
);
2324 has_ext_irq
= kvm_cpu_has_interrupt(vcpu
);
2325 intr_info_field
= vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
);
2326 idtv_info_field
= vmx
->idt_vectoring_info
;
2327 if (intr_info_field
& INTR_INFO_VALID_MASK
) {
2328 if (idtv_info_field
& INTR_INFO_VALID_MASK
) {
2329 /* TODO: fault when IDT_Vectoring */
2330 if (printk_ratelimit())
2331 printk(KERN_ERR
"Fault when IDT_Vectoring\n");
2334 enable_irq_window(vcpu
);
2337 if (unlikely(idtv_info_field
& INTR_INFO_VALID_MASK
)) {
2338 if ((idtv_info_field
& VECTORING_INFO_TYPE_MASK
)
2339 == INTR_TYPE_EXT_INTR
2340 && vcpu
->arch
.rmode
.active
) {
2341 u8 vect
= idtv_info_field
& VECTORING_INFO_VECTOR_MASK
;
2343 vmx_inject_irq(vcpu
, vect
);
2344 if (unlikely(has_ext_irq
))
2345 enable_irq_window(vcpu
);
2349 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, idtv_info_field
);
2350 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2351 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
2353 if (unlikely(idtv_info_field
& INTR_INFO_DELIVER_CODE_MASK
))
2354 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
2355 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
2356 if (unlikely(has_ext_irq
))
2357 enable_irq_window(vcpu
);
2362 interrupt_window_open
=
2363 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2364 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0);
2365 if (interrupt_window_open
) {
2366 vector
= kvm_cpu_get_interrupt(vcpu
);
2367 vmx_inject_irq(vcpu
, vector
);
2368 kvm_timer_intr_post(vcpu
, vector
);
2370 enable_irq_window(vcpu
);
2374 * Failure to inject an interrupt should give us the information
2375 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2376 * when fetching the interrupt redirection bitmap in the real-mode
2377 * tss, this doesn't happen. So we do it ourselves.
2379 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
2381 vmx
->rmode
.irq
.pending
= 0;
2382 if (vmcs_readl(GUEST_RIP
) + 1 != vmx
->rmode
.irq
.rip
)
2384 vmcs_writel(GUEST_RIP
, vmx
->rmode
.irq
.rip
);
2385 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
2386 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
2387 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
2390 vmx
->idt_vectoring_info
=
2391 VECTORING_INFO_VALID_MASK
2392 | INTR_TYPE_EXT_INTR
2393 | vmx
->rmode
.irq
.vector
;
2396 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2402 * Loading guest fpu may have cleared host cr0.ts
2404 vmcs_writel(HOST_CR0
, read_cr0());
2407 /* Store host registers */
2408 #ifdef CONFIG_X86_64
2409 "push %%rdx; push %%rbp;"
2412 "push %%edx; push %%ebp;"
2415 ASM_VMX_VMWRITE_RSP_RDX
"\n\t"
2416 /* Check if vmlaunch of vmresume is needed */
2417 "cmpl $0, %c[launched](%0) \n\t"
2418 /* Load guest registers. Don't clobber flags. */
2419 #ifdef CONFIG_X86_64
2420 "mov %c[cr2](%0), %%rax \n\t"
2421 "mov %%rax, %%cr2 \n\t"
2422 "mov %c[rax](%0), %%rax \n\t"
2423 "mov %c[rbx](%0), %%rbx \n\t"
2424 "mov %c[rdx](%0), %%rdx \n\t"
2425 "mov %c[rsi](%0), %%rsi \n\t"
2426 "mov %c[rdi](%0), %%rdi \n\t"
2427 "mov %c[rbp](%0), %%rbp \n\t"
2428 "mov %c[r8](%0), %%r8 \n\t"
2429 "mov %c[r9](%0), %%r9 \n\t"
2430 "mov %c[r10](%0), %%r10 \n\t"
2431 "mov %c[r11](%0), %%r11 \n\t"
2432 "mov %c[r12](%0), %%r12 \n\t"
2433 "mov %c[r13](%0), %%r13 \n\t"
2434 "mov %c[r14](%0), %%r14 \n\t"
2435 "mov %c[r15](%0), %%r15 \n\t"
2436 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2438 "mov %c[cr2](%0), %%eax \n\t"
2439 "mov %%eax, %%cr2 \n\t"
2440 "mov %c[rax](%0), %%eax \n\t"
2441 "mov %c[rbx](%0), %%ebx \n\t"
2442 "mov %c[rdx](%0), %%edx \n\t"
2443 "mov %c[rsi](%0), %%esi \n\t"
2444 "mov %c[rdi](%0), %%edi \n\t"
2445 "mov %c[rbp](%0), %%ebp \n\t"
2446 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2448 /* Enter guest mode */
2449 "jne .Llaunched \n\t"
2450 ASM_VMX_VMLAUNCH
"\n\t"
2451 "jmp .Lkvm_vmx_return \n\t"
2452 ".Llaunched: " ASM_VMX_VMRESUME
"\n\t"
2453 ".Lkvm_vmx_return: "
2454 /* Save guest registers, load host registers, keep flags */
2455 #ifdef CONFIG_X86_64
2456 "xchg %0, (%%rsp) \n\t"
2457 "mov %%rax, %c[rax](%0) \n\t"
2458 "mov %%rbx, %c[rbx](%0) \n\t"
2459 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2460 "mov %%rdx, %c[rdx](%0) \n\t"
2461 "mov %%rsi, %c[rsi](%0) \n\t"
2462 "mov %%rdi, %c[rdi](%0) \n\t"
2463 "mov %%rbp, %c[rbp](%0) \n\t"
2464 "mov %%r8, %c[r8](%0) \n\t"
2465 "mov %%r9, %c[r9](%0) \n\t"
2466 "mov %%r10, %c[r10](%0) \n\t"
2467 "mov %%r11, %c[r11](%0) \n\t"
2468 "mov %%r12, %c[r12](%0) \n\t"
2469 "mov %%r13, %c[r13](%0) \n\t"
2470 "mov %%r14, %c[r14](%0) \n\t"
2471 "mov %%r15, %c[r15](%0) \n\t"
2472 "mov %%cr2, %%rax \n\t"
2473 "mov %%rax, %c[cr2](%0) \n\t"
2475 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
2477 "xchg %0, (%%esp) \n\t"
2478 "mov %%eax, %c[rax](%0) \n\t"
2479 "mov %%ebx, %c[rbx](%0) \n\t"
2480 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2481 "mov %%edx, %c[rdx](%0) \n\t"
2482 "mov %%esi, %c[rsi](%0) \n\t"
2483 "mov %%edi, %c[rdi](%0) \n\t"
2484 "mov %%ebp, %c[rbp](%0) \n\t"
2485 "mov %%cr2, %%eax \n\t"
2486 "mov %%eax, %c[cr2](%0) \n\t"
2488 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2490 "setbe %c[fail](%0) \n\t"
2491 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
2492 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
2493 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
2494 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
2495 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2496 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2497 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2498 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2499 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2500 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
2501 #ifdef CONFIG_X86_64
2502 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2503 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2504 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2505 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2506 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2507 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2508 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2509 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
2511 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
2513 #ifdef CONFIG_X86_64
2514 , "rbx", "rdi", "rsi"
2515 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2517 , "ebx", "edi", "rsi"
2521 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
2522 if (vmx
->rmode
.irq
.pending
)
2523 fixup_rmode_irq(vmx
);
2525 vcpu
->arch
.interrupt_window_open
=
2526 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0;
2528 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
2531 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2533 /* We need to handle NMIs before interrupts are enabled */
2534 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == 0x200) /* nmi */
2538 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
2540 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2543 on_each_cpu(__vcpu_clear
, vmx
, 0, 1);
2544 free_vmcs(vmx
->vmcs
);
2549 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
2551 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2553 spin_lock(&vmx_vpid_lock
);
2555 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2556 spin_unlock(&vmx_vpid_lock
);
2557 vmx_free_vmcs(vcpu
);
2558 kfree(vmx
->host_msrs
);
2559 kfree(vmx
->guest_msrs
);
2560 kvm_vcpu_uninit(vcpu
);
2561 kmem_cache_free(kvm_vcpu_cache
, vmx
);
2564 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2567 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2571 return ERR_PTR(-ENOMEM
);
2575 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
2579 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2580 if (!vmx
->guest_msrs
) {
2585 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2586 if (!vmx
->host_msrs
)
2587 goto free_guest_msrs
;
2589 vmx
->vmcs
= alloc_vmcs();
2593 vmcs_clear(vmx
->vmcs
);
2596 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
2597 err
= vmx_vcpu_setup(vmx
);
2598 vmx_vcpu_put(&vmx
->vcpu
);
2602 if (vm_need_virtualize_apic_accesses(kvm
))
2603 if (alloc_apic_access_page(kvm
) != 0)
2609 free_vmcs(vmx
->vmcs
);
2611 kfree(vmx
->host_msrs
);
2613 kfree(vmx
->guest_msrs
);
2615 kvm_vcpu_uninit(&vmx
->vcpu
);
2617 kmem_cache_free(kvm_vcpu_cache
, vmx
);
2618 return ERR_PTR(err
);
2621 static void __init
vmx_check_processor_compat(void *rtn
)
2623 struct vmcs_config vmcs_conf
;
2626 if (setup_vmcs_config(&vmcs_conf
) < 0)
2628 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
2629 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
2630 smp_processor_id());
2635 static struct kvm_x86_ops vmx_x86_ops
= {
2636 .cpu_has_kvm_support
= cpu_has_kvm_support
,
2637 .disabled_by_bios
= vmx_disabled_by_bios
,
2638 .hardware_setup
= hardware_setup
,
2639 .hardware_unsetup
= hardware_unsetup
,
2640 .check_processor_compatibility
= vmx_check_processor_compat
,
2641 .hardware_enable
= hardware_enable
,
2642 .hardware_disable
= hardware_disable
,
2643 .cpu_has_accelerated_tpr
= cpu_has_vmx_virtualize_apic_accesses
,
2645 .vcpu_create
= vmx_create_vcpu
,
2646 .vcpu_free
= vmx_free_vcpu
,
2647 .vcpu_reset
= vmx_vcpu_reset
,
2649 .prepare_guest_switch
= vmx_save_host_state
,
2650 .vcpu_load
= vmx_vcpu_load
,
2651 .vcpu_put
= vmx_vcpu_put
,
2652 .vcpu_decache
= vmx_vcpu_decache
,
2654 .set_guest_debug
= set_guest_debug
,
2655 .guest_debug_pre
= kvm_guest_debug_pre
,
2656 .get_msr
= vmx_get_msr
,
2657 .set_msr
= vmx_set_msr
,
2658 .get_segment_base
= vmx_get_segment_base
,
2659 .get_segment
= vmx_get_segment
,
2660 .set_segment
= vmx_set_segment
,
2661 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
2662 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
2663 .set_cr0
= vmx_set_cr0
,
2664 .set_cr3
= vmx_set_cr3
,
2665 .set_cr4
= vmx_set_cr4
,
2666 .set_efer
= vmx_set_efer
,
2667 .get_idt
= vmx_get_idt
,
2668 .set_idt
= vmx_set_idt
,
2669 .get_gdt
= vmx_get_gdt
,
2670 .set_gdt
= vmx_set_gdt
,
2671 .cache_regs
= vcpu_load_rsp_rip
,
2672 .decache_regs
= vcpu_put_rsp_rip
,
2673 .get_rflags
= vmx_get_rflags
,
2674 .set_rflags
= vmx_set_rflags
,
2676 .tlb_flush
= vmx_flush_tlb
,
2678 .run
= vmx_vcpu_run
,
2679 .handle_exit
= kvm_handle_exit
,
2680 .skip_emulated_instruction
= skip_emulated_instruction
,
2681 .patch_hypercall
= vmx_patch_hypercall
,
2682 .get_irq
= vmx_get_irq
,
2683 .set_irq
= vmx_inject_irq
,
2684 .queue_exception
= vmx_queue_exception
,
2685 .exception_injected
= vmx_exception_injected
,
2686 .inject_pending_irq
= vmx_intr_assist
,
2687 .inject_pending_vectors
= do_interrupt_requests
,
2689 .set_tss_addr
= vmx_set_tss_addr
,
2692 static int __init
vmx_init(void)
2697 vmx_io_bitmap_a
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2698 if (!vmx_io_bitmap_a
)
2701 vmx_io_bitmap_b
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2702 if (!vmx_io_bitmap_b
) {
2708 * Allow direct access to the PC debug port (it is often used for I/O
2709 * delays, but the vmexits simply slow things down).
2711 iova
= kmap(vmx_io_bitmap_a
);
2712 memset(iova
, 0xff, PAGE_SIZE
);
2713 clear_bit(0x80, iova
);
2714 kunmap(vmx_io_bitmap_a
);
2716 iova
= kmap(vmx_io_bitmap_b
);
2717 memset(iova
, 0xff, PAGE_SIZE
);
2718 kunmap(vmx_io_bitmap_b
);
2720 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
2722 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
2726 if (bypass_guest_pf
)
2727 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
2732 __free_page(vmx_io_bitmap_b
);
2734 __free_page(vmx_io_bitmap_a
);
2738 static void __exit
vmx_exit(void)
2740 __free_page(vmx_io_bitmap_b
);
2741 __free_page(vmx_io_bitmap_a
);
2746 module_init(vmx_init
)
2747 module_exit(vmx_exit
)