2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id vmx_cpu_id
[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
59 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
61 static bool __read_mostly enable_vpid
= 1;
62 module_param_named(vpid
, enable_vpid
, bool, 0444);
64 static bool __read_mostly flexpriority_enabled
= 1;
65 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
67 static bool __read_mostly enable_ept
= 1;
68 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
70 static bool __read_mostly enable_unrestricted_guest
= 1;
71 module_param_named(unrestricted_guest
,
72 enable_unrestricted_guest
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept_ad_bits
= 1;
75 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
77 static bool __read_mostly emulate_invalid_guest_state
= 0;
78 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
80 static bool __read_mostly vmm_exclusive
= 1;
81 module_param(vmm_exclusive
, bool, S_IRUGO
);
83 static bool __read_mostly fasteoi
= 1;
84 module_param(fasteoi
, bool, S_IRUGO
);
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
91 static bool __read_mostly nested
= 0;
92 module_param(nested
, bool, S_IRUGO
);
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
125 module_param(ple_gap
, int, S_IRUGO
);
127 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
128 module_param(ple_window
, int, S_IRUGO
);
130 #define NR_AUTOLOAD_MSRS 8
131 #define VMCS02_POOL_SIZE 1
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
148 struct list_head loaded_vmcss_on_cpu_link
;
151 struct shared_msr_entry
{
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 typedef u64 natural_width
;
171 struct __packed vmcs12
{
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
178 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding
[7]; /* room for future expansion */
184 u64 vm_exit_msr_store_addr
;
185 u64 vm_exit_msr_load_addr
;
186 u64 vm_entry_msr_load_addr
;
188 u64 virtual_apic_page_addr
;
189 u64 apic_access_addr
;
191 u64 guest_physical_address
;
192 u64 vmcs_link_pointer
;
193 u64 guest_ia32_debugctl
;
196 u64 guest_ia32_perf_global_ctrl
;
203 u64 host_ia32_perf_global_ctrl
;
204 u64 padding64
[8]; /* room for future expansion */
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
211 natural_width cr0_guest_host_mask
;
212 natural_width cr4_guest_host_mask
;
213 natural_width cr0_read_shadow
;
214 natural_width cr4_read_shadow
;
215 natural_width cr3_target_value0
;
216 natural_width cr3_target_value1
;
217 natural_width cr3_target_value2
;
218 natural_width cr3_target_value3
;
219 natural_width exit_qualification
;
220 natural_width guest_linear_address
;
221 natural_width guest_cr0
;
222 natural_width guest_cr3
;
223 natural_width guest_cr4
;
224 natural_width guest_es_base
;
225 natural_width guest_cs_base
;
226 natural_width guest_ss_base
;
227 natural_width guest_ds_base
;
228 natural_width guest_fs_base
;
229 natural_width guest_gs_base
;
230 natural_width guest_ldtr_base
;
231 natural_width guest_tr_base
;
232 natural_width guest_gdtr_base
;
233 natural_width guest_idtr_base
;
234 natural_width guest_dr7
;
235 natural_width guest_rsp
;
236 natural_width guest_rip
;
237 natural_width guest_rflags
;
238 natural_width guest_pending_dbg_exceptions
;
239 natural_width guest_sysenter_esp
;
240 natural_width guest_sysenter_eip
;
241 natural_width host_cr0
;
242 natural_width host_cr3
;
243 natural_width host_cr4
;
244 natural_width host_fs_base
;
245 natural_width host_gs_base
;
246 natural_width host_tr_base
;
247 natural_width host_gdtr_base
;
248 natural_width host_idtr_base
;
249 natural_width host_ia32_sysenter_esp
;
250 natural_width host_ia32_sysenter_eip
;
251 natural_width host_rsp
;
252 natural_width host_rip
;
253 natural_width paddingl
[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control
;
255 u32 cpu_based_vm_exec_control
;
256 u32 exception_bitmap
;
257 u32 page_fault_error_code_mask
;
258 u32 page_fault_error_code_match
;
259 u32 cr3_target_count
;
260 u32 vm_exit_controls
;
261 u32 vm_exit_msr_store_count
;
262 u32 vm_exit_msr_load_count
;
263 u32 vm_entry_controls
;
264 u32 vm_entry_msr_load_count
;
265 u32 vm_entry_intr_info_field
;
266 u32 vm_entry_exception_error_code
;
267 u32 vm_entry_instruction_len
;
269 u32 secondary_vm_exec_control
;
270 u32 vm_instruction_error
;
272 u32 vm_exit_intr_info
;
273 u32 vm_exit_intr_error_code
;
274 u32 idt_vectoring_info_field
;
275 u32 idt_vectoring_error_code
;
276 u32 vm_exit_instruction_len
;
277 u32 vmx_instruction_info
;
284 u32 guest_ldtr_limit
;
286 u32 guest_gdtr_limit
;
287 u32 guest_idtr_limit
;
288 u32 guest_es_ar_bytes
;
289 u32 guest_cs_ar_bytes
;
290 u32 guest_ss_ar_bytes
;
291 u32 guest_ds_ar_bytes
;
292 u32 guest_fs_ar_bytes
;
293 u32 guest_gs_ar_bytes
;
294 u32 guest_ldtr_ar_bytes
;
295 u32 guest_tr_ar_bytes
;
296 u32 guest_interruptibility_info
;
297 u32 guest_activity_state
;
298 u32 guest_sysenter_cs
;
299 u32 host_ia32_sysenter_cs
;
300 u32 padding32
[8]; /* room for future expansion */
301 u16 virtual_processor_id
;
302 u16 guest_es_selector
;
303 u16 guest_cs_selector
;
304 u16 guest_ss_selector
;
305 u16 guest_ds_selector
;
306 u16 guest_fs_selector
;
307 u16 guest_gs_selector
;
308 u16 guest_ldtr_selector
;
309 u16 guest_tr_selector
;
310 u16 host_es_selector
;
311 u16 host_cs_selector
;
312 u16 host_ss_selector
;
313 u16 host_ds_selector
;
314 u16 host_fs_selector
;
315 u16 host_gs_selector
;
316 u16 host_tr_selector
;
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 #define VMCS12_REVISION 0x11e57ed0
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
331 #define VMCS12_SIZE 0x1000
333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
335 struct list_head list
;
337 struct loaded_vmcs vmcs02
;
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 /* Has the level1 guest done vmxon? */
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 /* The host-usable pointer to the above */
351 struct page
*current_vmcs12_page
;
352 struct vmcs12
*current_vmcs12
;
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool
;
357 u64 vmcs01_tsc_offset
;
358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending
;
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
364 struct page
*apic_access_page
;
368 struct kvm_vcpu vcpu
;
369 unsigned long host_rsp
;
372 bool nmi_known_unmasked
;
374 u32 idt_vectoring_info
;
376 struct shared_msr_entry
*guest_msrs
;
380 u64 msr_host_kernel_gs_base
;
381 u64 msr_guest_kernel_gs_base
;
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
388 struct loaded_vmcs vmcs01
;
389 struct loaded_vmcs
*loaded_vmcs
;
390 bool __launched
; /* temporary, used in vmx_vcpu_run */
391 struct msr_autoload
{
393 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
394 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
398 u16 fs_sel
, gs_sel
, ldt_sel
;
402 int gs_ldt_reload_needed
;
403 int fs_reload_needed
;
408 struct kvm_save_segment
{
413 } tr
, es
, ds
, fs
, gs
;
416 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg
[8];
420 bool emulation_required
;
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked
;
425 s64 vnmi_blocked_time
;
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested
;
434 enum segment_cache_field
{
443 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
445 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
453 static unsigned short vmcs_field_to_offset_table
[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
455 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
456 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
457 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
458 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
459 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
460 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
461 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
462 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
463 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
464 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
465 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
466 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
467 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
468 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
469 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
470 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
471 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
472 FIELD64(MSR_BITMAP
, msr_bitmap
),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
476 FIELD64(TSC_OFFSET
, tsc_offset
),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
478 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
479 FIELD64(EPT_POINTER
, ept_pointer
),
480 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
481 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
482 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
483 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
484 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
486 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
487 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
488 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
489 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
490 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
491 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
495 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
498 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
499 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
500 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
502 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
507 FIELD(TPR_THRESHOLD
, tpr_threshold
),
508 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
509 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
510 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
511 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
512 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
513 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
514 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
515 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
516 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
517 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
518 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
519 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
520 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
521 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
522 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
523 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
524 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
525 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
526 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
527 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
528 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
529 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
530 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
531 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
532 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
533 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
534 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
536 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
537 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
538 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
539 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
540 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
541 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
542 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
543 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
544 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
545 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
546 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
547 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
548 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
549 FIELD(GUEST_CR0
, guest_cr0
),
550 FIELD(GUEST_CR3
, guest_cr3
),
551 FIELD(GUEST_CR4
, guest_cr4
),
552 FIELD(GUEST_ES_BASE
, guest_es_base
),
553 FIELD(GUEST_CS_BASE
, guest_cs_base
),
554 FIELD(GUEST_SS_BASE
, guest_ss_base
),
555 FIELD(GUEST_DS_BASE
, guest_ds_base
),
556 FIELD(GUEST_FS_BASE
, guest_fs_base
),
557 FIELD(GUEST_GS_BASE
, guest_gs_base
),
558 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
559 FIELD(GUEST_TR_BASE
, guest_tr_base
),
560 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
561 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
562 FIELD(GUEST_DR7
, guest_dr7
),
563 FIELD(GUEST_RSP
, guest_rsp
),
564 FIELD(GUEST_RIP
, guest_rip
),
565 FIELD(GUEST_RFLAGS
, guest_rflags
),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
567 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
568 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
569 FIELD(HOST_CR0
, host_cr0
),
570 FIELD(HOST_CR3
, host_cr3
),
571 FIELD(HOST_CR4
, host_cr4
),
572 FIELD(HOST_FS_BASE
, host_fs_base
),
573 FIELD(HOST_GS_BASE
, host_gs_base
),
574 FIELD(HOST_TR_BASE
, host_tr_base
),
575 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
576 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
577 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
578 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
579 FIELD(HOST_RSP
, host_rsp
),
580 FIELD(HOST_RIP
, host_rip
),
582 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
584 static inline short vmcs_field_to_offset(unsigned long field
)
586 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
588 return vmcs_field_to_offset_table
[field
];
591 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
593 return to_vmx(vcpu
)->nested
.current_vmcs12
;
596 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
598 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
599 if (is_error_page(page
)) {
600 kvm_release_page_clean(page
);
606 static void nested_release_page(struct page
*page
)
608 kvm_release_page_dirty(page
);
611 static void nested_release_page_clean(struct page
*page
)
613 kvm_release_page_clean(page
);
616 static u64
construct_eptp(unsigned long root_hpa
);
617 static void kvm_cpu_vmxon(u64 addr
);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
620 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
622 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
623 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
625 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
626 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
628 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
629 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
631 static unsigned long *vmx_io_bitmap_a
;
632 static unsigned long *vmx_io_bitmap_b
;
633 static unsigned long *vmx_msr_bitmap_legacy
;
634 static unsigned long *vmx_msr_bitmap_longmode
;
636 static bool cpu_has_load_ia32_efer
;
637 static bool cpu_has_load_perf_global_ctrl
;
639 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
640 static DEFINE_SPINLOCK(vmx_vpid_lock
);
642 static struct vmcs_config
{
646 u32 pin_based_exec_ctrl
;
647 u32 cpu_based_exec_ctrl
;
648 u32 cpu_based_2nd_exec_ctrl
;
653 static struct vmx_capability
{
658 #define VMX_SEGMENT_FIELD(seg) \
659 [VCPU_SREG_##seg] = { \
660 .selector = GUEST_##seg##_SELECTOR, \
661 .base = GUEST_##seg##_BASE, \
662 .limit = GUEST_##seg##_LIMIT, \
663 .ar_bytes = GUEST_##seg##_AR_BYTES, \
666 static struct kvm_vmx_segment_field
{
671 } kvm_vmx_segment_fields
[] = {
672 VMX_SEGMENT_FIELD(CS
),
673 VMX_SEGMENT_FIELD(DS
),
674 VMX_SEGMENT_FIELD(ES
),
675 VMX_SEGMENT_FIELD(FS
),
676 VMX_SEGMENT_FIELD(GS
),
677 VMX_SEGMENT_FIELD(SS
),
678 VMX_SEGMENT_FIELD(TR
),
679 VMX_SEGMENT_FIELD(LDTR
),
682 static u64 host_efer
;
684 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
687 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
688 * away by decrementing the array size.
690 static const u32 vmx_msr_index
[] = {
692 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
694 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
696 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
698 static inline bool is_page_fault(u32 intr_info
)
700 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
701 INTR_INFO_VALID_MASK
)) ==
702 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
705 static inline bool is_no_device(u32 intr_info
)
707 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
708 INTR_INFO_VALID_MASK
)) ==
709 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
712 static inline bool is_invalid_opcode(u32 intr_info
)
714 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
715 INTR_INFO_VALID_MASK
)) ==
716 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
719 static inline bool is_external_interrupt(u32 intr_info
)
721 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
722 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
725 static inline bool is_machine_check(u32 intr_info
)
727 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
728 INTR_INFO_VALID_MASK
)) ==
729 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
732 static inline bool cpu_has_vmx_msr_bitmap(void)
734 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
737 static inline bool cpu_has_vmx_tpr_shadow(void)
739 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
742 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
744 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
747 static inline bool cpu_has_secondary_exec_ctrls(void)
749 return vmcs_config
.cpu_based_exec_ctrl
&
750 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
753 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
755 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
756 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
759 static inline bool cpu_has_vmx_flexpriority(void)
761 return cpu_has_vmx_tpr_shadow() &&
762 cpu_has_vmx_virtualize_apic_accesses();
765 static inline bool cpu_has_vmx_ept_execute_only(void)
767 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
770 static inline bool cpu_has_vmx_eptp_uncacheable(void)
772 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
775 static inline bool cpu_has_vmx_eptp_writeback(void)
777 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
780 static inline bool cpu_has_vmx_ept_2m_page(void)
782 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
785 static inline bool cpu_has_vmx_ept_1g_page(void)
787 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
790 static inline bool cpu_has_vmx_ept_4levels(void)
792 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
795 static inline bool cpu_has_vmx_ept_ad_bits(void)
797 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
800 static inline bool cpu_has_vmx_invept_individual_addr(void)
802 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
805 static inline bool cpu_has_vmx_invept_context(void)
807 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
810 static inline bool cpu_has_vmx_invept_global(void)
812 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
815 static inline bool cpu_has_vmx_invvpid_single(void)
817 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
820 static inline bool cpu_has_vmx_invvpid_global(void)
822 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
825 static inline bool cpu_has_vmx_ept(void)
827 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
828 SECONDARY_EXEC_ENABLE_EPT
;
831 static inline bool cpu_has_vmx_unrestricted_guest(void)
833 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
834 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
837 static inline bool cpu_has_vmx_ple(void)
839 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
840 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
843 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
845 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
848 static inline bool cpu_has_vmx_vpid(void)
850 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
851 SECONDARY_EXEC_ENABLE_VPID
;
854 static inline bool cpu_has_vmx_rdtscp(void)
856 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
857 SECONDARY_EXEC_RDTSCP
;
860 static inline bool cpu_has_virtual_nmis(void)
862 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
865 static inline bool cpu_has_vmx_wbinvd_exit(void)
867 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
868 SECONDARY_EXEC_WBINVD_EXITING
;
871 static inline bool report_flexpriority(void)
873 return flexpriority_enabled
;
876 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
878 return vmcs12
->cpu_based_vm_exec_control
& bit
;
881 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
883 return (vmcs12
->cpu_based_vm_exec_control
&
884 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
885 (vmcs12
->secondary_vm_exec_control
& bit
);
888 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
889 struct kvm_vcpu
*vcpu
)
891 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
894 static inline bool is_exception(u32 intr_info
)
896 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
897 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
900 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
901 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
902 struct vmcs12
*vmcs12
,
903 u32 reason
, unsigned long qualification
);
905 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
909 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
910 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
915 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
921 } operand
= { vpid
, 0, gva
};
923 asm volatile (__ex(ASM_VMX_INVVPID
)
924 /* CF==1 or ZF==1 --> rc = -1 */
926 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
929 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
933 } operand
= {eptp
, gpa
};
935 asm volatile (__ex(ASM_VMX_INVEPT
)
936 /* CF==1 or ZF==1 --> rc = -1 */
937 "; ja 1f ; ud2 ; 1:\n"
938 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
941 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
945 i
= __find_msr_index(vmx
, msr
);
947 return &vmx
->guest_msrs
[i
];
951 static void vmcs_clear(struct vmcs
*vmcs
)
953 u64 phys_addr
= __pa(vmcs
);
956 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
957 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
960 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
964 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
966 vmcs_clear(loaded_vmcs
->vmcs
);
967 loaded_vmcs
->cpu
= -1;
968 loaded_vmcs
->launched
= 0;
971 static void vmcs_load(struct vmcs
*vmcs
)
973 u64 phys_addr
= __pa(vmcs
);
976 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
977 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
980 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
984 static void __loaded_vmcs_clear(void *arg
)
986 struct loaded_vmcs
*loaded_vmcs
= arg
;
987 int cpu
= raw_smp_processor_id();
989 if (loaded_vmcs
->cpu
!= cpu
)
990 return; /* vcpu migration can race with cpu offline */
991 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
992 per_cpu(current_vmcs
, cpu
) = NULL
;
993 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
994 loaded_vmcs_init(loaded_vmcs
);
997 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
999 if (loaded_vmcs
->cpu
!= -1)
1000 smp_call_function_single(
1001 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
1004 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1009 if (cpu_has_vmx_invvpid_single())
1010 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1013 static inline void vpid_sync_vcpu_global(void)
1015 if (cpu_has_vmx_invvpid_global())
1016 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1019 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1021 if (cpu_has_vmx_invvpid_single())
1022 vpid_sync_vcpu_single(vmx
);
1024 vpid_sync_vcpu_global();
1027 static inline void ept_sync_global(void)
1029 if (cpu_has_vmx_invept_global())
1030 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1033 static inline void ept_sync_context(u64 eptp
)
1036 if (cpu_has_vmx_invept_context())
1037 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1043 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
1046 if (cpu_has_vmx_invept_individual_addr())
1047 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
1050 ept_sync_context(eptp
);
1054 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1056 unsigned long value
;
1058 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1059 : "=a"(value
) : "d"(field
) : "cc");
1063 static __always_inline u16
vmcs_read16(unsigned long field
)
1065 return vmcs_readl(field
);
1068 static __always_inline u32
vmcs_read32(unsigned long field
)
1070 return vmcs_readl(field
);
1073 static __always_inline u64
vmcs_read64(unsigned long field
)
1075 #ifdef CONFIG_X86_64
1076 return vmcs_readl(field
);
1078 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1082 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1084 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1085 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1089 static void vmcs_writel(unsigned long field
, unsigned long value
)
1093 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1094 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1095 if (unlikely(error
))
1096 vmwrite_error(field
, value
);
1099 static void vmcs_write16(unsigned long field
, u16 value
)
1101 vmcs_writel(field
, value
);
1104 static void vmcs_write32(unsigned long field
, u32 value
)
1106 vmcs_writel(field
, value
);
1109 static void vmcs_write64(unsigned long field
, u64 value
)
1111 vmcs_writel(field
, value
);
1112 #ifndef CONFIG_X86_64
1114 vmcs_writel(field
+1, value
>> 32);
1118 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1120 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1123 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1125 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1128 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1130 vmx
->segment_cache
.bitmask
= 0;
1133 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1137 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1139 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1140 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1141 vmx
->segment_cache
.bitmask
= 0;
1143 ret
= vmx
->segment_cache
.bitmask
& mask
;
1144 vmx
->segment_cache
.bitmask
|= mask
;
1148 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1150 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1152 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1153 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1157 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1159 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1161 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1162 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1166 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1168 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1170 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1171 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1175 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1177 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1179 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1180 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1184 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1188 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1189 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1190 if ((vcpu
->guest_debug
&
1191 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1192 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1193 eb
|= 1u << BP_VECTOR
;
1194 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1197 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1198 if (vcpu
->fpu_active
)
1199 eb
&= ~(1u << NM_VECTOR
);
1201 /* When we are running a nested L2 guest and L1 specified for it a
1202 * certain exception bitmap, we must trap the same exceptions and pass
1203 * them to L1. When running L2, we will only handle the exceptions
1204 * specified above if L1 did not want them.
1206 if (is_guest_mode(vcpu
))
1207 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1209 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1212 static void clear_atomic_switch_msr_special(unsigned long entry
,
1215 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1216 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1219 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1222 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1226 if (cpu_has_load_ia32_efer
) {
1227 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1228 VM_EXIT_LOAD_IA32_EFER
);
1232 case MSR_CORE_PERF_GLOBAL_CTRL
:
1233 if (cpu_has_load_perf_global_ctrl
) {
1234 clear_atomic_switch_msr_special(
1235 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1236 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1242 for (i
= 0; i
< m
->nr
; ++i
)
1243 if (m
->guest
[i
].index
== msr
)
1249 m
->guest
[i
] = m
->guest
[m
->nr
];
1250 m
->host
[i
] = m
->host
[m
->nr
];
1251 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1252 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1255 static void add_atomic_switch_msr_special(unsigned long entry
,
1256 unsigned long exit
, unsigned long guest_val_vmcs
,
1257 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1259 vmcs_write64(guest_val_vmcs
, guest_val
);
1260 vmcs_write64(host_val_vmcs
, host_val
);
1261 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1262 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1265 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1266 u64 guest_val
, u64 host_val
)
1269 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1273 if (cpu_has_load_ia32_efer
) {
1274 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1275 VM_EXIT_LOAD_IA32_EFER
,
1278 guest_val
, host_val
);
1282 case MSR_CORE_PERF_GLOBAL_CTRL
:
1283 if (cpu_has_load_perf_global_ctrl
) {
1284 add_atomic_switch_msr_special(
1285 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1286 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1287 GUEST_IA32_PERF_GLOBAL_CTRL
,
1288 HOST_IA32_PERF_GLOBAL_CTRL
,
1289 guest_val
, host_val
);
1295 for (i
= 0; i
< m
->nr
; ++i
)
1296 if (m
->guest
[i
].index
== msr
)
1299 if (i
== NR_AUTOLOAD_MSRS
) {
1300 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1301 "Can't add msr %x\n", msr
);
1303 } else if (i
== m
->nr
) {
1305 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1306 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1309 m
->guest
[i
].index
= msr
;
1310 m
->guest
[i
].value
= guest_val
;
1311 m
->host
[i
].index
= msr
;
1312 m
->host
[i
].value
= host_val
;
1315 static void reload_tss(void)
1318 * VT restores TR but not its size. Useless.
1320 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1321 struct desc_struct
*descs
;
1323 descs
= (void *)gdt
->address
;
1324 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1328 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1333 guest_efer
= vmx
->vcpu
.arch
.efer
;
1336 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1339 ignore_bits
= EFER_NX
| EFER_SCE
;
1340 #ifdef CONFIG_X86_64
1341 ignore_bits
|= EFER_LMA
| EFER_LME
;
1342 /* SCE is meaningful only in long mode on Intel */
1343 if (guest_efer
& EFER_LMA
)
1344 ignore_bits
&= ~(u64
)EFER_SCE
;
1346 guest_efer
&= ~ignore_bits
;
1347 guest_efer
|= host_efer
& ignore_bits
;
1348 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1349 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1351 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1352 /* On ept, can't emulate nx, and must switch nx atomically */
1353 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1354 guest_efer
= vmx
->vcpu
.arch
.efer
;
1355 if (!(guest_efer
& EFER_LMA
))
1356 guest_efer
&= ~EFER_LME
;
1357 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1364 static unsigned long segment_base(u16 selector
)
1366 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1367 struct desc_struct
*d
;
1368 unsigned long table_base
;
1371 if (!(selector
& ~3))
1374 table_base
= gdt
->address
;
1376 if (selector
& 4) { /* from ldt */
1377 u16 ldt_selector
= kvm_read_ldt();
1379 if (!(ldt_selector
& ~3))
1382 table_base
= segment_base(ldt_selector
);
1384 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1385 v
= get_desc_base(d
);
1386 #ifdef CONFIG_X86_64
1387 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1388 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1393 static inline unsigned long kvm_read_tr_base(void)
1396 asm("str %0" : "=g"(tr
));
1397 return segment_base(tr
);
1400 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1402 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1405 if (vmx
->host_state
.loaded
)
1408 vmx
->host_state
.loaded
= 1;
1410 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1411 * allow segment selectors with cpl > 0 or ti == 1.
1413 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1414 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1415 savesegment(fs
, vmx
->host_state
.fs_sel
);
1416 if (!(vmx
->host_state
.fs_sel
& 7)) {
1417 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1418 vmx
->host_state
.fs_reload_needed
= 0;
1420 vmcs_write16(HOST_FS_SELECTOR
, 0);
1421 vmx
->host_state
.fs_reload_needed
= 1;
1423 savesegment(gs
, vmx
->host_state
.gs_sel
);
1424 if (!(vmx
->host_state
.gs_sel
& 7))
1425 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1427 vmcs_write16(HOST_GS_SELECTOR
, 0);
1428 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1431 #ifdef CONFIG_X86_64
1432 savesegment(ds
, vmx
->host_state
.ds_sel
);
1433 savesegment(es
, vmx
->host_state
.es_sel
);
1436 #ifdef CONFIG_X86_64
1437 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1438 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1440 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1441 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1444 #ifdef CONFIG_X86_64
1445 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1446 if (is_long_mode(&vmx
->vcpu
))
1447 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1449 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1450 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1451 vmx
->guest_msrs
[i
].data
,
1452 vmx
->guest_msrs
[i
].mask
);
1455 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1457 if (!vmx
->host_state
.loaded
)
1460 ++vmx
->vcpu
.stat
.host_state_reload
;
1461 vmx
->host_state
.loaded
= 0;
1462 #ifdef CONFIG_X86_64
1463 if (is_long_mode(&vmx
->vcpu
))
1464 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1466 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1467 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1468 #ifdef CONFIG_X86_64
1469 load_gs_index(vmx
->host_state
.gs_sel
);
1471 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1474 if (vmx
->host_state
.fs_reload_needed
)
1475 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1476 #ifdef CONFIG_X86_64
1477 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1478 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1479 loadsegment(es
, vmx
->host_state
.es_sel
);
1483 * The sysexit path does not restore ds/es, so we must set them to
1484 * a reasonable value ourselves.
1486 loadsegment(ds
, __USER_DS
);
1487 loadsegment(es
, __USER_DS
);
1490 #ifdef CONFIG_X86_64
1491 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1495 load_gdt(&__get_cpu_var(host_gdt
));
1498 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1501 __vmx_load_host_state(vmx
);
1506 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1507 * vcpu mutex is already taken.
1509 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1511 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1512 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1515 kvm_cpu_vmxon(phys_addr
);
1516 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1517 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1519 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1520 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1521 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1524 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1525 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1526 unsigned long sysenter_esp
;
1528 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1529 local_irq_disable();
1530 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1531 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1535 * Linux uses per-cpu TSS and GDT, so set these when switching
1538 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1539 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1541 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1542 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1543 vmx
->loaded_vmcs
->cpu
= cpu
;
1547 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1549 __vmx_load_host_state(to_vmx(vcpu
));
1550 if (!vmm_exclusive
) {
1551 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1557 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1561 if (vcpu
->fpu_active
)
1563 vcpu
->fpu_active
= 1;
1564 cr0
= vmcs_readl(GUEST_CR0
);
1565 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1566 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1567 vmcs_writel(GUEST_CR0
, cr0
);
1568 update_exception_bitmap(vcpu
);
1569 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1570 if (is_guest_mode(vcpu
))
1571 vcpu
->arch
.cr0_guest_owned_bits
&=
1572 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1573 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1576 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1579 * Return the cr0 value that a nested guest would read. This is a combination
1580 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1581 * its hypervisor (cr0_read_shadow).
1583 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1585 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1586 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1588 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1590 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1591 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1594 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1596 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1597 * set this *before* calling this function.
1599 vmx_decache_cr0_guest_bits(vcpu
);
1600 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1601 update_exception_bitmap(vcpu
);
1602 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1603 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1604 if (is_guest_mode(vcpu
)) {
1606 * L1's specified read shadow might not contain the TS bit,
1607 * so now that we turned on shadowing of this bit, we need to
1608 * set this bit of the shadow. Like in nested_vmx_run we need
1609 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1610 * up-to-date here because we just decached cr0.TS (and we'll
1611 * only update vmcs12->guest_cr0 on nested exit).
1613 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1614 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1615 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1616 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1618 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1621 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1623 unsigned long rflags
, save_rflags
;
1625 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1626 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1627 rflags
= vmcs_readl(GUEST_RFLAGS
);
1628 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1629 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1630 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1631 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1633 to_vmx(vcpu
)->rflags
= rflags
;
1635 return to_vmx(vcpu
)->rflags
;
1638 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1640 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1641 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1642 to_vmx(vcpu
)->rflags
= rflags
;
1643 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1644 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1645 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1647 vmcs_writel(GUEST_RFLAGS
, rflags
);
1650 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1652 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1655 if (interruptibility
& GUEST_INTR_STATE_STI
)
1656 ret
|= KVM_X86_SHADOW_INT_STI
;
1657 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1658 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1663 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1665 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1666 u32 interruptibility
= interruptibility_old
;
1668 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1670 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1671 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1672 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1673 interruptibility
|= GUEST_INTR_STATE_STI
;
1675 if ((interruptibility
!= interruptibility_old
))
1676 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1679 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1683 rip
= kvm_rip_read(vcpu
);
1684 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1685 kvm_rip_write(vcpu
, rip
);
1687 /* skipping an emulated instruction also counts */
1688 vmx_set_interrupt_shadow(vcpu
, 0);
1692 * KVM wants to inject page-faults which it got to the guest. This function
1693 * checks whether in a nested guest, we need to inject them to L1 or L2.
1694 * This function assumes it is called with the exit reason in vmcs02 being
1695 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1698 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1700 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1702 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1703 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1706 nested_vmx_vmexit(vcpu
);
1710 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1711 bool has_error_code
, u32 error_code
,
1714 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1715 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1717 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1718 nested_pf_handled(vcpu
))
1721 if (has_error_code
) {
1722 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1723 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1726 if (vmx
->rmode
.vm86_active
) {
1728 if (kvm_exception_is_soft(nr
))
1729 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1730 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1731 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1735 if (kvm_exception_is_soft(nr
)) {
1736 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1737 vmx
->vcpu
.arch
.event_exit_inst_len
);
1738 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1740 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1742 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1745 static bool vmx_rdtscp_supported(void)
1747 return cpu_has_vmx_rdtscp();
1751 * Swap MSR entry in host/guest MSR entry array.
1753 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1755 struct shared_msr_entry tmp
;
1757 tmp
= vmx
->guest_msrs
[to
];
1758 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1759 vmx
->guest_msrs
[from
] = tmp
;
1763 * Set up the vmcs to automatically save and restore system
1764 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1765 * mode, as fiddling with msrs is very expensive.
1767 static void setup_msrs(struct vcpu_vmx
*vmx
)
1769 int save_nmsrs
, index
;
1770 unsigned long *msr_bitmap
;
1773 #ifdef CONFIG_X86_64
1774 if (is_long_mode(&vmx
->vcpu
)) {
1775 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1777 move_msr_up(vmx
, index
, save_nmsrs
++);
1778 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1780 move_msr_up(vmx
, index
, save_nmsrs
++);
1781 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1783 move_msr_up(vmx
, index
, save_nmsrs
++);
1784 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1785 if (index
>= 0 && vmx
->rdtscp_enabled
)
1786 move_msr_up(vmx
, index
, save_nmsrs
++);
1788 * MSR_STAR is only needed on long mode guests, and only
1789 * if efer.sce is enabled.
1791 index
= __find_msr_index(vmx
, MSR_STAR
);
1792 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1793 move_msr_up(vmx
, index
, save_nmsrs
++);
1796 index
= __find_msr_index(vmx
, MSR_EFER
);
1797 if (index
>= 0 && update_transition_efer(vmx
, index
))
1798 move_msr_up(vmx
, index
, save_nmsrs
++);
1800 vmx
->save_nmsrs
= save_nmsrs
;
1802 if (cpu_has_vmx_msr_bitmap()) {
1803 if (is_long_mode(&vmx
->vcpu
))
1804 msr_bitmap
= vmx_msr_bitmap_longmode
;
1806 msr_bitmap
= vmx_msr_bitmap_legacy
;
1808 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1813 * reads and returns guest's timestamp counter "register"
1814 * guest_tsc = host_tsc + tsc_offset -- 21.3
1816 static u64
guest_read_tsc(void)
1818 u64 host_tsc
, tsc_offset
;
1821 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1822 return host_tsc
+ tsc_offset
;
1826 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1827 * counter, even if a nested guest (L2) is currently running.
1829 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
)
1831 u64 host_tsc
, tsc_offset
;
1834 tsc_offset
= is_guest_mode(vcpu
) ?
1835 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1836 vmcs_read64(TSC_OFFSET
);
1837 return host_tsc
+ tsc_offset
;
1841 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1842 * software catchup for faster rates on slower CPUs.
1844 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1849 if (user_tsc_khz
> tsc_khz
) {
1850 vcpu
->arch
.tsc_catchup
= 1;
1851 vcpu
->arch
.tsc_always_catchup
= 1;
1853 WARN(1, "user requested TSC rate below hardware speed\n");
1857 * writes 'offset' into guest's timestamp counter offset register
1859 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1861 if (is_guest_mode(vcpu
)) {
1863 * We're here if L1 chose not to trap WRMSR to TSC. According
1864 * to the spec, this should set L1's TSC; The offset that L1
1865 * set for L2 remains unchanged, and still needs to be added
1866 * to the newly set TSC to get L2's TSC.
1868 struct vmcs12
*vmcs12
;
1869 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1870 /* recalculate vmcs02.TSC_OFFSET: */
1871 vmcs12
= get_vmcs12(vcpu
);
1872 vmcs_write64(TSC_OFFSET
, offset
+
1873 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1874 vmcs12
->tsc_offset
: 0));
1876 vmcs_write64(TSC_OFFSET
, offset
);
1880 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1882 u64 offset
= vmcs_read64(TSC_OFFSET
);
1883 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1884 if (is_guest_mode(vcpu
)) {
1885 /* Even when running L2, the adjustment needs to apply to L1 */
1886 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1890 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1892 return target_tsc
- native_read_tsc();
1895 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1897 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1898 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1902 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1903 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1904 * all guests if the "nested" module option is off, and can also be disabled
1905 * for a single guest by disabling its VMX cpuid bit.
1907 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1909 return nested
&& guest_cpuid_has_vmx(vcpu
);
1913 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1914 * returned for the various VMX controls MSRs when nested VMX is enabled.
1915 * The same values should also be used to verify that vmcs12 control fields are
1916 * valid during nested entry from L1 to L2.
1917 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1918 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1919 * bit in the high half is on if the corresponding bit in the control field
1920 * may be on. See also vmx_control_verify().
1921 * TODO: allow these variables to be modified (downgraded) by module options
1924 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1925 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1926 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1927 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1928 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1929 static __init
void nested_vmx_setup_ctls_msrs(void)
1932 * Note that as a general rule, the high half of the MSRs (bits in
1933 * the control fields which may be 1) should be initialized by the
1934 * intersection of the underlying hardware's MSR (i.e., features which
1935 * can be supported) and the list of features we want to expose -
1936 * because they are known to be properly supported in our code.
1937 * Also, usually, the low half of the MSRs (bits which must be 1) can
1938 * be set to 0, meaning that L1 may turn off any of these bits. The
1939 * reason is that if one of these bits is necessary, it will appear
1940 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1941 * fields of vmcs01 and vmcs02, will turn these bits off - and
1942 * nested_vmx_exit_handled() will not pass related exits to L1.
1943 * These rules have exceptions below.
1946 /* pin-based controls */
1948 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1949 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1951 nested_vmx_pinbased_ctls_low
= 0x16 ;
1952 nested_vmx_pinbased_ctls_high
= 0x16 |
1953 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1954 PIN_BASED_VIRTUAL_NMIS
;
1957 nested_vmx_exit_ctls_low
= 0;
1958 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1959 #ifdef CONFIG_X86_64
1960 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1962 nested_vmx_exit_ctls_high
= 0;
1965 /* entry controls */
1966 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1967 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1968 nested_vmx_entry_ctls_low
= 0;
1969 nested_vmx_entry_ctls_high
&=
1970 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1972 /* cpu-based controls */
1973 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1974 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1975 nested_vmx_procbased_ctls_low
= 0;
1976 nested_vmx_procbased_ctls_high
&=
1977 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1978 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1979 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1980 CPU_BASED_CR3_STORE_EXITING
|
1981 #ifdef CONFIG_X86_64
1982 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1984 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1985 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1986 CPU_BASED_RDPMC_EXITING
|
1987 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1989 * We can allow some features even when not supported by the
1990 * hardware. For example, L1 can specify an MSR bitmap - and we
1991 * can use it to avoid exits to L1 - even when L0 runs L2
1992 * without MSR bitmaps.
1994 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
1996 /* secondary cpu-based controls */
1997 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1998 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
1999 nested_vmx_secondary_ctls_low
= 0;
2000 nested_vmx_secondary_ctls_high
&=
2001 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2004 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2007 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2009 return ((control
& high
) | low
) == control
;
2012 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2014 return low
| ((u64
)high
<< 32);
2018 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2019 * also let it use VMX-specific MSRs.
2020 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2021 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2022 * like all other MSRs).
2024 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2026 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2027 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2029 * According to the spec, processors which do not support VMX
2030 * should throw a #GP(0) when VMX capability MSRs are read.
2032 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2036 switch (msr_index
) {
2037 case MSR_IA32_FEATURE_CONTROL
:
2040 case MSR_IA32_VMX_BASIC
:
2042 * This MSR reports some information about VMX support. We
2043 * should return information about the VMX we emulate for the
2044 * guest, and the VMCS structure we give it - not about the
2045 * VMX support of the underlying hardware.
2047 *pdata
= VMCS12_REVISION
|
2048 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2049 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2051 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2052 case MSR_IA32_VMX_PINBASED_CTLS
:
2053 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2054 nested_vmx_pinbased_ctls_high
);
2056 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2057 case MSR_IA32_VMX_PROCBASED_CTLS
:
2058 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2059 nested_vmx_procbased_ctls_high
);
2061 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2062 case MSR_IA32_VMX_EXIT_CTLS
:
2063 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2064 nested_vmx_exit_ctls_high
);
2066 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2067 case MSR_IA32_VMX_ENTRY_CTLS
:
2068 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2069 nested_vmx_entry_ctls_high
);
2071 case MSR_IA32_VMX_MISC
:
2075 * These MSRs specify bits which the guest must keep fixed (on or off)
2076 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2077 * We picked the standard core2 setting.
2079 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2080 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2081 case MSR_IA32_VMX_CR0_FIXED0
:
2082 *pdata
= VMXON_CR0_ALWAYSON
;
2084 case MSR_IA32_VMX_CR0_FIXED1
:
2087 case MSR_IA32_VMX_CR4_FIXED0
:
2088 *pdata
= VMXON_CR4_ALWAYSON
;
2090 case MSR_IA32_VMX_CR4_FIXED1
:
2093 case MSR_IA32_VMX_VMCS_ENUM
:
2096 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2097 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2098 nested_vmx_secondary_ctls_high
);
2100 case MSR_IA32_VMX_EPT_VPID_CAP
:
2101 /* Currently, no nested ept or nested vpid */
2111 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2113 if (!nested_vmx_allowed(vcpu
))
2116 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2117 /* TODO: the right thing. */
2120 * No need to treat VMX capability MSRs specially: If we don't handle
2121 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2127 * Reads an msr value (of 'msr_index') into 'pdata'.
2128 * Returns 0 on success, non-0 otherwise.
2129 * Assumes vcpu_load() was already called.
2131 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2134 struct shared_msr_entry
*msr
;
2137 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2141 switch (msr_index
) {
2142 #ifdef CONFIG_X86_64
2144 data
= vmcs_readl(GUEST_FS_BASE
);
2147 data
= vmcs_readl(GUEST_GS_BASE
);
2149 case MSR_KERNEL_GS_BASE
:
2150 vmx_load_host_state(to_vmx(vcpu
));
2151 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2155 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2157 data
= guest_read_tsc();
2159 case MSR_IA32_SYSENTER_CS
:
2160 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2162 case MSR_IA32_SYSENTER_EIP
:
2163 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2165 case MSR_IA32_SYSENTER_ESP
:
2166 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2169 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2171 /* Otherwise falls through */
2173 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2175 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2180 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2188 * Writes msr value into into the appropriate "register".
2189 * Returns 0 on success, non-0 otherwise.
2190 * Assumes vcpu_load() was already called.
2192 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2194 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2195 struct shared_msr_entry
*msr
;
2198 switch (msr_index
) {
2200 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2202 #ifdef CONFIG_X86_64
2204 vmx_segment_cache_clear(vmx
);
2205 vmcs_writel(GUEST_FS_BASE
, data
);
2208 vmx_segment_cache_clear(vmx
);
2209 vmcs_writel(GUEST_GS_BASE
, data
);
2211 case MSR_KERNEL_GS_BASE
:
2212 vmx_load_host_state(vmx
);
2213 vmx
->msr_guest_kernel_gs_base
= data
;
2216 case MSR_IA32_SYSENTER_CS
:
2217 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2219 case MSR_IA32_SYSENTER_EIP
:
2220 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2222 case MSR_IA32_SYSENTER_ESP
:
2223 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2226 kvm_write_tsc(vcpu
, data
);
2228 case MSR_IA32_CR_PAT
:
2229 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2230 vmcs_write64(GUEST_IA32_PAT
, data
);
2231 vcpu
->arch
.pat
= data
;
2234 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2237 if (!vmx
->rdtscp_enabled
)
2239 /* Check reserved bit, higher 32 bits should be zero */
2240 if ((data
>> 32) != 0)
2242 /* Otherwise falls through */
2244 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2246 msr
= find_msr_entry(vmx
, msr_index
);
2249 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2251 kvm_set_shared_msr(msr
->index
, msr
->data
,
2257 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2263 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2265 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2268 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2271 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2273 case VCPU_EXREG_PDPTR
:
2275 ept_save_pdptrs(vcpu
);
2282 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
2284 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
2285 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
2287 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2289 update_exception_bitmap(vcpu
);
2292 static __init
int cpu_has_kvm_support(void)
2294 return cpu_has_vmx();
2297 static __init
int vmx_disabled_by_bios(void)
2301 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2302 if (msr
& FEATURE_CONTROL_LOCKED
) {
2303 /* launched w/ TXT and VMX disabled */
2304 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2307 /* launched w/o TXT and VMX only enabled w/ TXT */
2308 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2309 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2310 && !tboot_enabled()) {
2311 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2312 "activate TXT before enabling KVM\n");
2315 /* launched w/o TXT and VMX disabled */
2316 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2317 && !tboot_enabled())
2324 static void kvm_cpu_vmxon(u64 addr
)
2326 asm volatile (ASM_VMX_VMXON_RAX
2327 : : "a"(&addr
), "m"(addr
)
2331 static int hardware_enable(void *garbage
)
2333 int cpu
= raw_smp_processor_id();
2334 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2337 if (read_cr4() & X86_CR4_VMXE
)
2340 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2341 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2343 test_bits
= FEATURE_CONTROL_LOCKED
;
2344 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2345 if (tboot_enabled())
2346 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2348 if ((old
& test_bits
) != test_bits
) {
2349 /* enable and lock */
2350 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2352 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2354 if (vmm_exclusive
) {
2355 kvm_cpu_vmxon(phys_addr
);
2359 store_gdt(&__get_cpu_var(host_gdt
));
2364 static void vmclear_local_loaded_vmcss(void)
2366 int cpu
= raw_smp_processor_id();
2367 struct loaded_vmcs
*v
, *n
;
2369 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2370 loaded_vmcss_on_cpu_link
)
2371 __loaded_vmcs_clear(v
);
2375 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2378 static void kvm_cpu_vmxoff(void)
2380 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2383 static void hardware_disable(void *garbage
)
2385 if (vmm_exclusive
) {
2386 vmclear_local_loaded_vmcss();
2389 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2392 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2393 u32 msr
, u32
*result
)
2395 u32 vmx_msr_low
, vmx_msr_high
;
2396 u32 ctl
= ctl_min
| ctl_opt
;
2398 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2400 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2401 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2403 /* Ensure minimum (required) set of control bits are supported. */
2411 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2413 u32 vmx_msr_low
, vmx_msr_high
;
2415 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2416 return vmx_msr_high
& ctl
;
2419 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2421 u32 vmx_msr_low
, vmx_msr_high
;
2422 u32 min
, opt
, min2
, opt2
;
2423 u32 _pin_based_exec_control
= 0;
2424 u32 _cpu_based_exec_control
= 0;
2425 u32 _cpu_based_2nd_exec_control
= 0;
2426 u32 _vmexit_control
= 0;
2427 u32 _vmentry_control
= 0;
2429 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2430 opt
= PIN_BASED_VIRTUAL_NMIS
;
2431 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2432 &_pin_based_exec_control
) < 0)
2435 min
= CPU_BASED_HLT_EXITING
|
2436 #ifdef CONFIG_X86_64
2437 CPU_BASED_CR8_LOAD_EXITING
|
2438 CPU_BASED_CR8_STORE_EXITING
|
2440 CPU_BASED_CR3_LOAD_EXITING
|
2441 CPU_BASED_CR3_STORE_EXITING
|
2442 CPU_BASED_USE_IO_BITMAPS
|
2443 CPU_BASED_MOV_DR_EXITING
|
2444 CPU_BASED_USE_TSC_OFFSETING
|
2445 CPU_BASED_MWAIT_EXITING
|
2446 CPU_BASED_MONITOR_EXITING
|
2447 CPU_BASED_INVLPG_EXITING
|
2448 CPU_BASED_RDPMC_EXITING
;
2450 opt
= CPU_BASED_TPR_SHADOW
|
2451 CPU_BASED_USE_MSR_BITMAPS
|
2452 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2453 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2454 &_cpu_based_exec_control
) < 0)
2456 #ifdef CONFIG_X86_64
2457 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2458 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2459 ~CPU_BASED_CR8_STORE_EXITING
;
2461 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2463 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2464 SECONDARY_EXEC_WBINVD_EXITING
|
2465 SECONDARY_EXEC_ENABLE_VPID
|
2466 SECONDARY_EXEC_ENABLE_EPT
|
2467 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2468 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2469 SECONDARY_EXEC_RDTSCP
;
2470 if (adjust_vmx_controls(min2
, opt2
,
2471 MSR_IA32_VMX_PROCBASED_CTLS2
,
2472 &_cpu_based_2nd_exec_control
) < 0)
2475 #ifndef CONFIG_X86_64
2476 if (!(_cpu_based_2nd_exec_control
&
2477 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2478 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2480 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2481 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2483 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2484 CPU_BASED_CR3_STORE_EXITING
|
2485 CPU_BASED_INVLPG_EXITING
);
2486 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2487 vmx_capability
.ept
, vmx_capability
.vpid
);
2491 #ifdef CONFIG_X86_64
2492 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2494 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2495 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2496 &_vmexit_control
) < 0)
2500 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2501 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2502 &_vmentry_control
) < 0)
2505 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2507 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2508 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2511 #ifdef CONFIG_X86_64
2512 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2513 if (vmx_msr_high
& (1u<<16))
2517 /* Require Write-Back (WB) memory type for VMCS accesses. */
2518 if (((vmx_msr_high
>> 18) & 15) != 6)
2521 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2522 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2523 vmcs_conf
->revision_id
= vmx_msr_low
;
2525 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2526 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2527 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2528 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2529 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2531 cpu_has_load_ia32_efer
=
2532 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2533 VM_ENTRY_LOAD_IA32_EFER
)
2534 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2535 VM_EXIT_LOAD_IA32_EFER
);
2537 cpu_has_load_perf_global_ctrl
=
2538 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2539 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2540 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2541 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2544 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2545 * but due to arrata below it can't be used. Workaround is to use
2546 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2548 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553 * BC86,AAY89,BD102 (model 44)
2557 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2558 switch (boot_cpu_data
.x86_model
) {
2564 cpu_has_load_perf_global_ctrl
= false;
2565 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2566 "does not work properly. Using workaround\n");
2576 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2578 int node
= cpu_to_node(cpu
);
2582 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2585 vmcs
= page_address(pages
);
2586 memset(vmcs
, 0, vmcs_config
.size
);
2587 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2591 static struct vmcs
*alloc_vmcs(void)
2593 return alloc_vmcs_cpu(raw_smp_processor_id());
2596 static void free_vmcs(struct vmcs
*vmcs
)
2598 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2602 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2604 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2606 if (!loaded_vmcs
->vmcs
)
2608 loaded_vmcs_clear(loaded_vmcs
);
2609 free_vmcs(loaded_vmcs
->vmcs
);
2610 loaded_vmcs
->vmcs
= NULL
;
2613 static void free_kvm_area(void)
2617 for_each_possible_cpu(cpu
) {
2618 free_vmcs(per_cpu(vmxarea
, cpu
));
2619 per_cpu(vmxarea
, cpu
) = NULL
;
2623 static __init
int alloc_kvm_area(void)
2627 for_each_possible_cpu(cpu
) {
2630 vmcs
= alloc_vmcs_cpu(cpu
);
2636 per_cpu(vmxarea
, cpu
) = vmcs
;
2641 static __init
int hardware_setup(void)
2643 if (setup_vmcs_config(&vmcs_config
) < 0)
2646 if (boot_cpu_has(X86_FEATURE_NX
))
2647 kvm_enable_efer_bits(EFER_NX
);
2649 if (!cpu_has_vmx_vpid())
2652 if (!cpu_has_vmx_ept() ||
2653 !cpu_has_vmx_ept_4levels()) {
2655 enable_unrestricted_guest
= 0;
2656 enable_ept_ad_bits
= 0;
2659 if (!cpu_has_vmx_ept_ad_bits())
2660 enable_ept_ad_bits
= 0;
2662 if (!cpu_has_vmx_unrestricted_guest())
2663 enable_unrestricted_guest
= 0;
2665 if (!cpu_has_vmx_flexpriority())
2666 flexpriority_enabled
= 0;
2668 if (!cpu_has_vmx_tpr_shadow())
2669 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2671 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2672 kvm_disable_largepages();
2674 if (!cpu_has_vmx_ple())
2678 nested_vmx_setup_ctls_msrs();
2680 return alloc_kvm_area();
2683 static __exit
void hardware_unsetup(void)
2688 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2690 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2692 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2693 vmcs_write16(sf
->selector
, save
->selector
);
2694 vmcs_writel(sf
->base
, save
->base
);
2695 vmcs_write32(sf
->limit
, save
->limit
);
2696 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2698 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2700 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2704 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2706 unsigned long flags
;
2707 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2709 vmx
->emulation_required
= 1;
2710 vmx
->rmode
.vm86_active
= 0;
2712 vmx_segment_cache_clear(vmx
);
2714 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2715 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2716 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2717 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2719 flags
= vmcs_readl(GUEST_RFLAGS
);
2720 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2721 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2722 vmcs_writel(GUEST_RFLAGS
, flags
);
2724 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2725 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2727 update_exception_bitmap(vcpu
);
2729 if (emulate_invalid_guest_state
)
2732 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2733 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2734 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2735 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2737 vmx_segment_cache_clear(vmx
);
2739 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2740 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2742 vmcs_write16(GUEST_CS_SELECTOR
,
2743 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2744 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2747 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2749 if (!kvm
->arch
.tss_addr
) {
2750 struct kvm_memslots
*slots
;
2751 struct kvm_memory_slot
*slot
;
2754 slots
= kvm_memslots(kvm
);
2755 slot
= id_to_memslot(slots
, 0);
2756 base_gfn
= slot
->base_gfn
+ slot
->npages
- 3;
2758 return base_gfn
<< PAGE_SHIFT
;
2760 return kvm
->arch
.tss_addr
;
2763 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2765 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2767 save
->selector
= vmcs_read16(sf
->selector
);
2768 save
->base
= vmcs_readl(sf
->base
);
2769 save
->limit
= vmcs_read32(sf
->limit
);
2770 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2771 vmcs_write16(sf
->selector
, save
->base
>> 4);
2772 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2773 vmcs_write32(sf
->limit
, 0xffff);
2774 vmcs_write32(sf
->ar_bytes
, 0xf3);
2775 if (save
->base
& 0xf)
2776 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2777 " aligned when entering protected mode (seg=%d)",
2781 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2783 unsigned long flags
;
2784 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2786 if (enable_unrestricted_guest
)
2789 vmx
->emulation_required
= 1;
2790 vmx
->rmode
.vm86_active
= 1;
2793 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2794 * vcpu. Call it here with phys address pointing 16M below 4G.
2796 if (!vcpu
->kvm
->arch
.tss_addr
) {
2797 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2798 "called before entering vcpu\n");
2799 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2800 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2801 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2804 vmx_segment_cache_clear(vmx
);
2806 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2807 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2808 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2810 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2811 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2813 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2814 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2816 flags
= vmcs_readl(GUEST_RFLAGS
);
2817 vmx
->rmode
.save_rflags
= flags
;
2819 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2821 vmcs_writel(GUEST_RFLAGS
, flags
);
2822 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2823 update_exception_bitmap(vcpu
);
2825 if (emulate_invalid_guest_state
)
2826 goto continue_rmode
;
2828 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
2829 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
2830 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
2832 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
2833 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
2834 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
2835 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
2836 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
2838 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2839 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2840 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2841 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2844 kvm_mmu_reset_context(vcpu
);
2847 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2850 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2856 * Force kernel_gs_base reloading before EFER changes, as control
2857 * of this msr depends on is_long_mode().
2859 vmx_load_host_state(to_vmx(vcpu
));
2860 vcpu
->arch
.efer
= efer
;
2861 if (efer
& EFER_LMA
) {
2862 vmcs_write32(VM_ENTRY_CONTROLS
,
2863 vmcs_read32(VM_ENTRY_CONTROLS
) |
2864 VM_ENTRY_IA32E_MODE
);
2867 vmcs_write32(VM_ENTRY_CONTROLS
,
2868 vmcs_read32(VM_ENTRY_CONTROLS
) &
2869 ~VM_ENTRY_IA32E_MODE
);
2871 msr
->data
= efer
& ~EFER_LME
;
2876 #ifdef CONFIG_X86_64
2878 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2882 vmx_segment_cache_clear(to_vmx(vcpu
));
2884 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2885 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2886 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2888 vmcs_write32(GUEST_TR_AR_BYTES
,
2889 (guest_tr_ar
& ~AR_TYPE_MASK
)
2890 | AR_TYPE_BUSY_64_TSS
);
2892 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2895 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2897 vmcs_write32(VM_ENTRY_CONTROLS
,
2898 vmcs_read32(VM_ENTRY_CONTROLS
)
2899 & ~VM_ENTRY_IA32E_MODE
);
2900 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2905 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2907 vpid_sync_context(to_vmx(vcpu
));
2909 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2911 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2915 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2917 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2919 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2920 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2923 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2925 if (enable_ept
&& is_paging(vcpu
))
2926 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2927 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2930 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2932 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2934 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2935 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2938 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2940 if (!test_bit(VCPU_EXREG_PDPTR
,
2941 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2944 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2945 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2946 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2947 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2948 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2952 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2954 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2955 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2956 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2957 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2958 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2961 __set_bit(VCPU_EXREG_PDPTR
,
2962 (unsigned long *)&vcpu
->arch
.regs_avail
);
2963 __set_bit(VCPU_EXREG_PDPTR
,
2964 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2967 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2969 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2971 struct kvm_vcpu
*vcpu
)
2973 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2974 vmx_decache_cr3(vcpu
);
2975 if (!(cr0
& X86_CR0_PG
)) {
2976 /* From paging/starting to nonpaging */
2977 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2978 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2979 (CPU_BASED_CR3_LOAD_EXITING
|
2980 CPU_BASED_CR3_STORE_EXITING
));
2981 vcpu
->arch
.cr0
= cr0
;
2982 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2983 } else if (!is_paging(vcpu
)) {
2984 /* From nonpaging to paging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
2987 ~(CPU_BASED_CR3_LOAD_EXITING
|
2988 CPU_BASED_CR3_STORE_EXITING
));
2989 vcpu
->arch
.cr0
= cr0
;
2990 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2993 if (!(cr0
& X86_CR0_WP
))
2994 *hw_cr0
&= ~X86_CR0_WP
;
2997 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2999 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3000 unsigned long hw_cr0
;
3002 if (enable_unrestricted_guest
)
3003 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
3004 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3006 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
3008 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3011 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3014 #ifdef CONFIG_X86_64
3015 if (vcpu
->arch
.efer
& EFER_LME
) {
3016 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3018 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3024 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3026 if (!vcpu
->fpu_active
)
3027 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3029 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3030 vmcs_writel(GUEST_CR0
, hw_cr0
);
3031 vcpu
->arch
.cr0
= cr0
;
3032 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3035 static u64
construct_eptp(unsigned long root_hpa
)
3039 /* TODO write the value reading from MSR */
3040 eptp
= VMX_EPT_DEFAULT_MT
|
3041 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3042 if (enable_ept_ad_bits
)
3043 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3044 eptp
|= (root_hpa
& PAGE_MASK
);
3049 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3051 unsigned long guest_cr3
;
3056 eptp
= construct_eptp(cr3
);
3057 vmcs_write64(EPT_POINTER
, eptp
);
3058 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3059 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3060 ept_load_pdptrs(vcpu
);
3063 vmx_flush_tlb(vcpu
);
3064 vmcs_writel(GUEST_CR3
, guest_cr3
);
3067 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3069 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3070 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3072 if (cr4
& X86_CR4_VMXE
) {
3074 * To use VMXON (and later other VMX instructions), a guest
3075 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3076 * So basically the check on whether to allow nested VMX
3079 if (!nested_vmx_allowed(vcpu
))
3081 } else if (to_vmx(vcpu
)->nested
.vmxon
)
3084 vcpu
->arch
.cr4
= cr4
;
3086 if (!is_paging(vcpu
)) {
3087 hw_cr4
&= ~X86_CR4_PAE
;
3088 hw_cr4
|= X86_CR4_PSE
;
3089 } else if (!(cr4
& X86_CR4_PAE
)) {
3090 hw_cr4
&= ~X86_CR4_PAE
;
3094 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3095 vmcs_writel(GUEST_CR4
, hw_cr4
);
3099 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3100 struct kvm_segment
*var
, int seg
)
3102 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3103 struct kvm_save_segment
*save
;
3106 if (vmx
->rmode
.vm86_active
3107 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
3108 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
3109 || seg
== VCPU_SREG_GS
)
3110 && !emulate_invalid_guest_state
) {
3112 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
3113 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
3114 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
3115 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
3116 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
3119 var
->selector
= save
->selector
;
3120 var
->base
= save
->base
;
3121 var
->limit
= save
->limit
;
3123 if (seg
== VCPU_SREG_TR
3124 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3125 goto use_saved_rmode_seg
;
3127 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3128 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3129 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3130 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3131 use_saved_rmode_seg
:
3132 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
3134 var
->type
= ar
& 15;
3135 var
->s
= (ar
>> 4) & 1;
3136 var
->dpl
= (ar
>> 5) & 3;
3137 var
->present
= (ar
>> 7) & 1;
3138 var
->avl
= (ar
>> 12) & 1;
3139 var
->l
= (ar
>> 13) & 1;
3140 var
->db
= (ar
>> 14) & 1;
3141 var
->g
= (ar
>> 15) & 1;
3142 var
->unusable
= (ar
>> 16) & 1;
3145 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3147 struct kvm_segment s
;
3149 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3150 vmx_get_segment(vcpu
, &s
, seg
);
3153 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3156 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3158 if (!is_protmode(vcpu
))
3161 if (!is_long_mode(vcpu
)
3162 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3165 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
3168 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3170 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3171 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3172 to_vmx(vcpu
)->cpl
= __vmx_get_cpl(vcpu
);
3174 return to_vmx(vcpu
)->cpl
;
3178 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3185 ar
= var
->type
& 15;
3186 ar
|= (var
->s
& 1) << 4;
3187 ar
|= (var
->dpl
& 3) << 5;
3188 ar
|= (var
->present
& 1) << 7;
3189 ar
|= (var
->avl
& 1) << 12;
3190 ar
|= (var
->l
& 1) << 13;
3191 ar
|= (var
->db
& 1) << 14;
3192 ar
|= (var
->g
& 1) << 15;
3194 if (ar
== 0) /* a 0 value means unusable */
3195 ar
= AR_UNUSABLE_MASK
;
3200 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3201 struct kvm_segment
*var
, int seg
)
3203 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3204 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3207 vmx_segment_cache_clear(vmx
);
3209 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
3210 vmcs_write16(sf
->selector
, var
->selector
);
3211 vmx
->rmode
.tr
.selector
= var
->selector
;
3212 vmx
->rmode
.tr
.base
= var
->base
;
3213 vmx
->rmode
.tr
.limit
= var
->limit
;
3214 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
3217 vmcs_writel(sf
->base
, var
->base
);
3218 vmcs_write32(sf
->limit
, var
->limit
);
3219 vmcs_write16(sf
->selector
, var
->selector
);
3220 if (vmx
->rmode
.vm86_active
&& var
->s
) {
3222 * Hack real-mode segments into vm86 compatibility.
3224 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
3225 vmcs_writel(sf
->base
, 0xf0000);
3228 ar
= vmx_segment_access_rights(var
);
3231 * Fix the "Accessed" bit in AR field of segment registers for older
3233 * IA32 arch specifies that at the time of processor reset the
3234 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3235 * is setting it to 0 in the usedland code. This causes invalid guest
3236 * state vmexit when "unrestricted guest" mode is turned on.
3237 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3238 * tree. Newer qemu binaries with that qemu fix would not need this
3241 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3242 ar
|= 0x1; /* Accessed */
3244 vmcs_write32(sf
->ar_bytes
, ar
);
3245 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3248 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3250 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3252 *db
= (ar
>> 14) & 1;
3253 *l
= (ar
>> 13) & 1;
3256 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3258 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3259 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3262 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3264 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3265 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3268 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3270 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3271 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3274 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3276 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3277 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3280 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3282 struct kvm_segment var
;
3285 vmx_get_segment(vcpu
, &var
, seg
);
3286 ar
= vmx_segment_access_rights(&var
);
3288 if (var
.base
!= (var
.selector
<< 4))
3290 if (var
.limit
!= 0xffff)
3298 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3300 struct kvm_segment cs
;
3301 unsigned int cs_rpl
;
3303 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3304 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3308 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3312 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3313 if (cs
.dpl
> cs_rpl
)
3316 if (cs
.dpl
!= cs_rpl
)
3322 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3326 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3328 struct kvm_segment ss
;
3329 unsigned int ss_rpl
;
3331 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3332 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3336 if (ss
.type
!= 3 && ss
.type
!= 7)
3340 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3348 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3350 struct kvm_segment var
;
3353 vmx_get_segment(vcpu
, &var
, seg
);
3354 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3362 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3363 if (var
.dpl
< rpl
) /* DPL < RPL */
3367 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3373 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3375 struct kvm_segment tr
;
3377 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3381 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3383 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3391 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3393 struct kvm_segment ldtr
;
3395 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3399 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3409 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3411 struct kvm_segment cs
, ss
;
3413 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3414 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3416 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3417 (ss
.selector
& SELECTOR_RPL_MASK
));
3421 * Check if guest state is valid. Returns true if valid, false if
3423 * We assume that registers are always usable
3425 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3427 /* real mode guest state checks */
3428 if (!is_protmode(vcpu
)) {
3429 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3431 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3433 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3435 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3437 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3439 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3442 /* protected mode guest state checks */
3443 if (!cs_ss_rpl_check(vcpu
))
3445 if (!code_segment_valid(vcpu
))
3447 if (!stack_segment_valid(vcpu
))
3449 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3451 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3453 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3455 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3457 if (!tr_valid(vcpu
))
3459 if (!ldtr_valid(vcpu
))
3463 * - Add checks on RIP
3464 * - Add checks on RFLAGS
3470 static int init_rmode_tss(struct kvm
*kvm
)
3474 int r
, idx
, ret
= 0;
3476 idx
= srcu_read_lock(&kvm
->srcu
);
3477 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3478 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3481 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3482 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3483 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3486 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3489 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3493 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3494 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3501 srcu_read_unlock(&kvm
->srcu
, idx
);
3505 static int init_rmode_identity_map(struct kvm
*kvm
)
3508 pfn_t identity_map_pfn
;
3513 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3514 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3515 "haven't been allocated!\n");
3518 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3521 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3522 idx
= srcu_read_lock(&kvm
->srcu
);
3523 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3526 /* Set up identity-mapping pagetable for EPT in real mode */
3527 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3528 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3529 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3530 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3531 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3535 kvm
->arch
.ept_identity_pagetable_done
= true;
3538 srcu_read_unlock(&kvm
->srcu
, idx
);
3542 static void seg_setup(int seg
)
3544 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3547 vmcs_write16(sf
->selector
, 0);
3548 vmcs_writel(sf
->base
, 0);
3549 vmcs_write32(sf
->limit
, 0xffff);
3550 if (enable_unrestricted_guest
) {
3552 if (seg
== VCPU_SREG_CS
)
3553 ar
|= 0x08; /* code segment */
3557 vmcs_write32(sf
->ar_bytes
, ar
);
3560 static int alloc_apic_access_page(struct kvm
*kvm
)
3562 struct kvm_userspace_memory_region kvm_userspace_mem
;
3565 mutex_lock(&kvm
->slots_lock
);
3566 if (kvm
->arch
.apic_access_page
)
3568 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3569 kvm_userspace_mem
.flags
= 0;
3570 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3571 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3572 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3576 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3578 mutex_unlock(&kvm
->slots_lock
);
3582 static int alloc_identity_pagetable(struct kvm
*kvm
)
3584 struct kvm_userspace_memory_region kvm_userspace_mem
;
3587 mutex_lock(&kvm
->slots_lock
);
3588 if (kvm
->arch
.ept_identity_pagetable
)
3590 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3591 kvm_userspace_mem
.flags
= 0;
3592 kvm_userspace_mem
.guest_phys_addr
=
3593 kvm
->arch
.ept_identity_map_addr
;
3594 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3595 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3599 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3600 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3602 mutex_unlock(&kvm
->slots_lock
);
3606 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3613 spin_lock(&vmx_vpid_lock
);
3614 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3615 if (vpid
< VMX_NR_VPIDS
) {
3617 __set_bit(vpid
, vmx_vpid_bitmap
);
3619 spin_unlock(&vmx_vpid_lock
);
3622 static void free_vpid(struct vcpu_vmx
*vmx
)
3626 spin_lock(&vmx_vpid_lock
);
3628 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3629 spin_unlock(&vmx_vpid_lock
);
3632 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3634 int f
= sizeof(unsigned long);
3636 if (!cpu_has_vmx_msr_bitmap())
3640 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3641 * have the write-low and read-high bitmap offsets the wrong way round.
3642 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3644 if (msr
<= 0x1fff) {
3645 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3646 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3647 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3649 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3650 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3654 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3657 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3658 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3662 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3663 * will not change in the lifetime of the guest.
3664 * Note that host-state that does change is set elsewhere. E.g., host-state
3665 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3667 static void vmx_set_constant_host_state(void)
3673 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3674 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3675 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3677 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3678 #ifdef CONFIG_X86_64
3680 * Load null selectors, so we can avoid reloading them in
3681 * __vmx_load_host_state(), in case userspace uses the null selectors
3682 * too (the expected case).
3684 vmcs_write16(HOST_DS_SELECTOR
, 0);
3685 vmcs_write16(HOST_ES_SELECTOR
, 0);
3687 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3688 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3690 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3691 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3693 native_store_idt(&dt
);
3694 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3696 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl
));
3697 vmcs_writel(HOST_RIP
, tmpl
); /* 22.2.5 */
3699 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3700 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3701 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3702 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3704 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3705 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3706 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3710 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3712 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3714 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3715 if (is_guest_mode(&vmx
->vcpu
))
3716 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3717 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3718 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3721 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3723 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3724 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3725 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3726 #ifdef CONFIG_X86_64
3727 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3728 CPU_BASED_CR8_LOAD_EXITING
;
3732 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3733 CPU_BASED_CR3_LOAD_EXITING
|
3734 CPU_BASED_INVLPG_EXITING
;
3735 return exec_control
;
3738 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3740 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3741 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3742 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3744 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3746 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3747 enable_unrestricted_guest
= 0;
3749 if (!enable_unrestricted_guest
)
3750 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3752 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3753 return exec_control
;
3756 static void ept_set_mmio_spte_mask(void)
3759 * EPT Misconfigurations can be generated if the value of bits 2:0
3760 * of an EPT paging-structure entry is 110b (write/execute).
3761 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3764 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
3768 * Sets up the vmcs for emulated real mode.
3770 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3772 #ifdef CONFIG_X86_64
3778 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3779 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3781 if (cpu_has_vmx_msr_bitmap())
3782 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3784 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3787 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3788 vmcs_config
.pin_based_exec_ctrl
);
3790 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
3792 if (cpu_has_secondary_exec_ctrls()) {
3793 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
3794 vmx_secondary_exec_control(vmx
));
3798 vmcs_write32(PLE_GAP
, ple_gap
);
3799 vmcs_write32(PLE_WINDOW
, ple_window
);
3802 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
3803 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
3804 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3806 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3807 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3808 vmx_set_constant_host_state();
3809 #ifdef CONFIG_X86_64
3810 rdmsrl(MSR_FS_BASE
, a
);
3811 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3812 rdmsrl(MSR_GS_BASE
, a
);
3813 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3815 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3816 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3819 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3820 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3821 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3822 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3823 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3825 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3826 u32 msr_low
, msr_high
;
3828 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3829 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3830 /* Write the default value follow host pat */
3831 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3832 /* Keep arch.pat sync with GUEST_IA32_PAT */
3833 vmx
->vcpu
.arch
.pat
= host_pat
;
3836 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3837 u32 index
= vmx_msr_index
[i
];
3838 u32 data_low
, data_high
;
3841 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3843 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3845 vmx
->guest_msrs
[j
].index
= i
;
3846 vmx
->guest_msrs
[j
].data
= 0;
3847 vmx
->guest_msrs
[j
].mask
= -1ull;
3851 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3853 /* 22.2.1, 20.8.1 */
3854 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3856 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3857 set_cr4_guest_host_mask(vmx
);
3859 kvm_write_tsc(&vmx
->vcpu
, 0);
3864 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3866 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3870 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3872 vmx
->rmode
.vm86_active
= 0;
3874 vmx
->soft_vnmi_blocked
= 0;
3876 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3877 kvm_set_cr8(&vmx
->vcpu
, 0);
3878 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3879 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3880 msr
|= MSR_IA32_APICBASE_BSP
;
3881 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3883 ret
= fx_init(&vmx
->vcpu
);
3887 vmx_segment_cache_clear(vmx
);
3889 seg_setup(VCPU_SREG_CS
);
3891 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3892 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3894 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3895 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3896 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3898 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3899 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3902 seg_setup(VCPU_SREG_DS
);
3903 seg_setup(VCPU_SREG_ES
);
3904 seg_setup(VCPU_SREG_FS
);
3905 seg_setup(VCPU_SREG_GS
);
3906 seg_setup(VCPU_SREG_SS
);
3908 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3909 vmcs_writel(GUEST_TR_BASE
, 0);
3910 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3911 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3913 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3914 vmcs_writel(GUEST_LDTR_BASE
, 0);
3915 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3916 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3918 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3919 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3920 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3922 vmcs_writel(GUEST_RFLAGS
, 0x02);
3923 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3924 kvm_rip_write(vcpu
, 0xfff0);
3926 kvm_rip_write(vcpu
, 0);
3927 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3929 vmcs_writel(GUEST_DR7
, 0x400);
3931 vmcs_writel(GUEST_GDTR_BASE
, 0);
3932 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3934 vmcs_writel(GUEST_IDTR_BASE
, 0);
3935 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3937 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3938 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3939 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3941 /* Special registers */
3942 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
3946 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
3948 if (cpu_has_vmx_tpr_shadow()) {
3949 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
3950 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
3951 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
3952 __pa(vmx
->vcpu
.arch
.apic
->regs
));
3953 vmcs_write32(TPR_THRESHOLD
, 0);
3956 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3957 vmcs_write64(APIC_ACCESS_ADDR
,
3958 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
3961 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
3963 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
3964 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
3965 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
3966 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
3967 vmx_set_cr4(&vmx
->vcpu
, 0);
3968 vmx_set_efer(&vmx
->vcpu
, 0);
3969 vmx_fpu_activate(&vmx
->vcpu
);
3970 update_exception_bitmap(&vmx
->vcpu
);
3972 vpid_sync_context(vmx
);
3976 /* HACK: Don't enable emulation on guest boot/reset */
3977 vmx
->emulation_required
= 0;
3984 * In nested virtualization, check if L1 asked to exit on external interrupts.
3985 * For most existing hypervisors, this will always return true.
3987 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
3989 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
3990 PIN_BASED_EXT_INTR_MASK
;
3993 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3995 u32 cpu_based_vm_exec_control
;
3996 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
3998 * We get here if vmx_interrupt_allowed() said we can't
3999 * inject to L1 now because L2 must run. Ask L2 to exit
4000 * right after entry, so we can inject to L1 more promptly.
4002 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT
, vcpu
);
4006 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4007 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4008 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4011 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4013 u32 cpu_based_vm_exec_control
;
4015 if (!cpu_has_virtual_nmis()) {
4016 enable_irq_window(vcpu
);
4020 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4021 enable_irq_window(vcpu
);
4024 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4025 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4026 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4029 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4031 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4033 int irq
= vcpu
->arch
.interrupt
.nr
;
4035 trace_kvm_inj_virq(irq
);
4037 ++vcpu
->stat
.irq_injections
;
4038 if (vmx
->rmode
.vm86_active
) {
4040 if (vcpu
->arch
.interrupt
.soft
)
4041 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4042 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4043 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4046 intr
= irq
| INTR_INFO_VALID_MASK
;
4047 if (vcpu
->arch
.interrupt
.soft
) {
4048 intr
|= INTR_TYPE_SOFT_INTR
;
4049 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4050 vmx
->vcpu
.arch
.event_exit_inst_len
);
4052 intr
|= INTR_TYPE_EXT_INTR
;
4053 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4056 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4060 if (is_guest_mode(vcpu
))
4063 if (!cpu_has_virtual_nmis()) {
4065 * Tracking the NMI-blocked state in software is built upon
4066 * finding the next open IRQ window. This, in turn, depends on
4067 * well-behaving guests: They have to keep IRQs disabled at
4068 * least as long as the NMI handler runs. Otherwise we may
4069 * cause NMI nesting, maybe breaking the guest. But as this is
4070 * highly unlikely, we can live with the residual risk.
4072 vmx
->soft_vnmi_blocked
= 1;
4073 vmx
->vnmi_blocked_time
= 0;
4076 ++vcpu
->stat
.nmi_injections
;
4077 vmx
->nmi_known_unmasked
= false;
4078 if (vmx
->rmode
.vm86_active
) {
4079 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4080 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4083 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4084 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4087 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4089 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4092 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4093 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4094 | GUEST_INTR_STATE_NMI
));
4097 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4099 if (!cpu_has_virtual_nmis())
4100 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4101 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4103 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4106 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4108 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4110 if (!cpu_has_virtual_nmis()) {
4111 if (vmx
->soft_vnmi_blocked
!= masked
) {
4112 vmx
->soft_vnmi_blocked
= masked
;
4113 vmx
->vnmi_blocked_time
= 0;
4116 vmx
->nmi_known_unmasked
= !masked
;
4118 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4119 GUEST_INTR_STATE_NMI
);
4121 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4122 GUEST_INTR_STATE_NMI
);
4126 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4128 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4129 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4130 if (to_vmx(vcpu
)->nested
.nested_run_pending
||
4131 (vmcs12
->idt_vectoring_info_field
&
4132 VECTORING_INFO_VALID_MASK
))
4134 nested_vmx_vmexit(vcpu
);
4135 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
4136 vmcs12
->vm_exit_intr_info
= 0;
4137 /* fall through to normal code, but now in L1, not L2 */
4140 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4141 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4142 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4145 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4148 struct kvm_userspace_memory_region tss_mem
= {
4149 .slot
= TSS_PRIVATE_MEMSLOT
,
4150 .guest_phys_addr
= addr
,
4151 .memory_size
= PAGE_SIZE
* 3,
4155 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
4158 kvm
->arch
.tss_addr
= addr
;
4159 if (!init_rmode_tss(kvm
))
4165 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4166 int vec
, u32 err_code
)
4169 * Instruction with address size override prefix opcode 0x67
4170 * Cause the #SS fault with 0 error code in VM86 mode.
4172 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
4173 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
4176 * Forward all other exceptions that are valid in real mode.
4177 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4178 * the required debugging infrastructure rework.
4182 if (vcpu
->guest_debug
&
4183 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4185 kvm_queue_exception(vcpu
, vec
);
4189 * Update instruction length as we may reinject the exception
4190 * from user space while in guest debugging mode.
4192 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4193 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4194 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4205 kvm_queue_exception(vcpu
, vec
);
4212 * Trigger machine check on the host. We assume all the MSRs are already set up
4213 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4214 * We pass a fake environment to the machine check handler because we want
4215 * the guest to be always treated like user space, no matter what context
4216 * it used internally.
4218 static void kvm_machine_check(void)
4220 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4221 struct pt_regs regs
= {
4222 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4223 .flags
= X86_EFLAGS_IF
,
4226 do_machine_check(®s
, 0);
4230 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4232 /* already handled by vcpu_run */
4236 static int handle_exception(struct kvm_vcpu
*vcpu
)
4238 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4239 struct kvm_run
*kvm_run
= vcpu
->run
;
4240 u32 intr_info
, ex_no
, error_code
;
4241 unsigned long cr2
, rip
, dr6
;
4243 enum emulation_result er
;
4245 vect_info
= vmx
->idt_vectoring_info
;
4246 intr_info
= vmx
->exit_intr_info
;
4248 if (is_machine_check(intr_info
))
4249 return handle_machine_check(vcpu
);
4251 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4252 !is_page_fault(intr_info
)) {
4253 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4254 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4255 vcpu
->run
->internal
.ndata
= 2;
4256 vcpu
->run
->internal
.data
[0] = vect_info
;
4257 vcpu
->run
->internal
.data
[1] = intr_info
;
4261 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4262 return 1; /* already handled by vmx_vcpu_run() */
4264 if (is_no_device(intr_info
)) {
4265 vmx_fpu_activate(vcpu
);
4269 if (is_invalid_opcode(intr_info
)) {
4270 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4271 if (er
!= EMULATE_DONE
)
4272 kvm_queue_exception(vcpu
, UD_VECTOR
);
4277 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4278 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4279 if (is_page_fault(intr_info
)) {
4280 /* EPT won't cause page fault directly */
4282 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4283 trace_kvm_page_fault(cr2
, error_code
);
4285 if (kvm_event_needs_reinjection(vcpu
))
4286 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4287 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4290 if (vmx
->rmode
.vm86_active
&&
4291 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
4293 if (vcpu
->arch
.halt_request
) {
4294 vcpu
->arch
.halt_request
= 0;
4295 return kvm_emulate_halt(vcpu
);
4300 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4303 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4304 if (!(vcpu
->guest_debug
&
4305 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4306 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4307 kvm_queue_exception(vcpu
, DB_VECTOR
);
4310 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4311 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4315 * Update instruction length as we may reinject #BP from
4316 * user space while in guest debugging mode. Reading it for
4317 * #DB as well causes no harm, it is not used in that case.
4319 vmx
->vcpu
.arch
.event_exit_inst_len
=
4320 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4321 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4322 rip
= kvm_rip_read(vcpu
);
4323 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4324 kvm_run
->debug
.arch
.exception
= ex_no
;
4327 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4328 kvm_run
->ex
.exception
= ex_no
;
4329 kvm_run
->ex
.error_code
= error_code
;
4335 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4337 ++vcpu
->stat
.irq_exits
;
4341 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4343 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4347 static int handle_io(struct kvm_vcpu
*vcpu
)
4349 unsigned long exit_qualification
;
4350 int size
, in
, string
;
4353 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4354 string
= (exit_qualification
& 16) != 0;
4355 in
= (exit_qualification
& 8) != 0;
4357 ++vcpu
->stat
.io_exits
;
4360 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4362 port
= exit_qualification
>> 16;
4363 size
= (exit_qualification
& 7) + 1;
4364 skip_emulated_instruction(vcpu
);
4366 return kvm_fast_pio_out(vcpu
, size
, port
);
4370 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4373 * Patch in the VMCALL instruction:
4375 hypercall
[0] = 0x0f;
4376 hypercall
[1] = 0x01;
4377 hypercall
[2] = 0xc1;
4380 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4381 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4383 if (to_vmx(vcpu
)->nested
.vmxon
&&
4384 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4387 if (is_guest_mode(vcpu
)) {
4389 * We get here when L2 changed cr0 in a way that did not change
4390 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4391 * but did change L0 shadowed bits. This can currently happen
4392 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4393 * loading) while pretending to allow the guest to change it.
4395 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4396 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4398 vmcs_writel(CR0_READ_SHADOW
, val
);
4401 return kvm_set_cr0(vcpu
, val
);
4404 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4406 if (is_guest_mode(vcpu
)) {
4407 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4408 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4410 vmcs_writel(CR4_READ_SHADOW
, val
);
4413 return kvm_set_cr4(vcpu
, val
);
4416 /* called to set cr0 as approriate for clts instruction exit. */
4417 static void handle_clts(struct kvm_vcpu
*vcpu
)
4419 if (is_guest_mode(vcpu
)) {
4421 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4422 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4423 * just pretend it's off (also in arch.cr0 for fpu_activate).
4425 vmcs_writel(CR0_READ_SHADOW
,
4426 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4427 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4429 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4432 static int handle_cr(struct kvm_vcpu
*vcpu
)
4434 unsigned long exit_qualification
, val
;
4439 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4440 cr
= exit_qualification
& 15;
4441 reg
= (exit_qualification
>> 8) & 15;
4442 switch ((exit_qualification
>> 4) & 3) {
4443 case 0: /* mov to cr */
4444 val
= kvm_register_read(vcpu
, reg
);
4445 trace_kvm_cr_write(cr
, val
);
4448 err
= handle_set_cr0(vcpu
, val
);
4449 kvm_complete_insn_gp(vcpu
, err
);
4452 err
= kvm_set_cr3(vcpu
, val
);
4453 kvm_complete_insn_gp(vcpu
, err
);
4456 err
= handle_set_cr4(vcpu
, val
);
4457 kvm_complete_insn_gp(vcpu
, err
);
4460 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4461 u8 cr8
= kvm_register_read(vcpu
, reg
);
4462 err
= kvm_set_cr8(vcpu
, cr8
);
4463 kvm_complete_insn_gp(vcpu
, err
);
4464 if (irqchip_in_kernel(vcpu
->kvm
))
4466 if (cr8_prev
<= cr8
)
4468 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4475 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4476 skip_emulated_instruction(vcpu
);
4477 vmx_fpu_activate(vcpu
);
4479 case 1: /*mov from cr*/
4482 val
= kvm_read_cr3(vcpu
);
4483 kvm_register_write(vcpu
, reg
, val
);
4484 trace_kvm_cr_read(cr
, val
);
4485 skip_emulated_instruction(vcpu
);
4488 val
= kvm_get_cr8(vcpu
);
4489 kvm_register_write(vcpu
, reg
, val
);
4490 trace_kvm_cr_read(cr
, val
);
4491 skip_emulated_instruction(vcpu
);
4496 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4497 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4498 kvm_lmsw(vcpu
, val
);
4500 skip_emulated_instruction(vcpu
);
4505 vcpu
->run
->exit_reason
= 0;
4506 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4507 (int)(exit_qualification
>> 4) & 3, cr
);
4511 static int handle_dr(struct kvm_vcpu
*vcpu
)
4513 unsigned long exit_qualification
;
4516 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4517 if (!kvm_require_cpl(vcpu
, 0))
4519 dr
= vmcs_readl(GUEST_DR7
);
4522 * As the vm-exit takes precedence over the debug trap, we
4523 * need to emulate the latter, either for the host or the
4524 * guest debugging itself.
4526 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4527 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4528 vcpu
->run
->debug
.arch
.dr7
= dr
;
4529 vcpu
->run
->debug
.arch
.pc
=
4530 vmcs_readl(GUEST_CS_BASE
) +
4531 vmcs_readl(GUEST_RIP
);
4532 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4533 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4536 vcpu
->arch
.dr7
&= ~DR7_GD
;
4537 vcpu
->arch
.dr6
|= DR6_BD
;
4538 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4539 kvm_queue_exception(vcpu
, DB_VECTOR
);
4544 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4545 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4546 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4547 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4549 if (!kvm_get_dr(vcpu
, dr
, &val
))
4550 kvm_register_write(vcpu
, reg
, val
);
4552 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4553 skip_emulated_instruction(vcpu
);
4557 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4559 vmcs_writel(GUEST_DR7
, val
);
4562 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4564 kvm_emulate_cpuid(vcpu
);
4568 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4570 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4573 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4574 trace_kvm_msr_read_ex(ecx
);
4575 kvm_inject_gp(vcpu
, 0);
4579 trace_kvm_msr_read(ecx
, data
);
4581 /* FIXME: handling of bits 32:63 of rax, rdx */
4582 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4583 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4584 skip_emulated_instruction(vcpu
);
4588 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4590 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4591 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4592 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4594 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
4595 trace_kvm_msr_write_ex(ecx
, data
);
4596 kvm_inject_gp(vcpu
, 0);
4600 trace_kvm_msr_write(ecx
, data
);
4601 skip_emulated_instruction(vcpu
);
4605 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4607 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4611 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4613 u32 cpu_based_vm_exec_control
;
4615 /* clear pending irq */
4616 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4617 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4618 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4620 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4622 ++vcpu
->stat
.irq_window_exits
;
4625 * If the user space waits to inject interrupts, exit as soon as
4628 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4629 vcpu
->run
->request_interrupt_window
&&
4630 !kvm_cpu_has_interrupt(vcpu
)) {
4631 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4637 static int handle_halt(struct kvm_vcpu
*vcpu
)
4639 skip_emulated_instruction(vcpu
);
4640 return kvm_emulate_halt(vcpu
);
4643 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4645 skip_emulated_instruction(vcpu
);
4646 kvm_emulate_hypercall(vcpu
);
4650 static int handle_invd(struct kvm_vcpu
*vcpu
)
4652 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4655 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4657 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4659 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4660 skip_emulated_instruction(vcpu
);
4664 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
4668 err
= kvm_rdpmc(vcpu
);
4669 kvm_complete_insn_gp(vcpu
, err
);
4674 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4676 skip_emulated_instruction(vcpu
);
4677 kvm_emulate_wbinvd(vcpu
);
4681 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4683 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4684 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4686 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4687 skip_emulated_instruction(vcpu
);
4691 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4693 if (likely(fasteoi
)) {
4694 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4695 int access_type
, offset
;
4697 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4698 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4700 * Sane guest uses MOV to write EOI, with written value
4701 * not cared. So make a short-circuit here by avoiding
4702 * heavy instruction emulation.
4704 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4705 (offset
== APIC_EOI
)) {
4706 kvm_lapic_set_eoi(vcpu
);
4707 skip_emulated_instruction(vcpu
);
4711 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4714 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4716 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4717 unsigned long exit_qualification
;
4718 bool has_error_code
= false;
4721 int reason
, type
, idt_v
, idt_index
;
4723 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4724 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
4725 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4727 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4729 reason
= (u32
)exit_qualification
>> 30;
4730 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4732 case INTR_TYPE_NMI_INTR
:
4733 vcpu
->arch
.nmi_injected
= false;
4734 vmx_set_nmi_mask(vcpu
, true);
4736 case INTR_TYPE_EXT_INTR
:
4737 case INTR_TYPE_SOFT_INTR
:
4738 kvm_clear_interrupt_queue(vcpu
);
4740 case INTR_TYPE_HARD_EXCEPTION
:
4741 if (vmx
->idt_vectoring_info
&
4742 VECTORING_INFO_DELIVER_CODE_MASK
) {
4743 has_error_code
= true;
4745 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4748 case INTR_TYPE_SOFT_EXCEPTION
:
4749 kvm_clear_exception_queue(vcpu
);
4755 tss_selector
= exit_qualification
;
4757 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4758 type
!= INTR_TYPE_EXT_INTR
&&
4759 type
!= INTR_TYPE_NMI_INTR
))
4760 skip_emulated_instruction(vcpu
);
4762 if (kvm_task_switch(vcpu
, tss_selector
,
4763 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
4764 has_error_code
, error_code
) == EMULATE_FAIL
) {
4765 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4766 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4767 vcpu
->run
->internal
.ndata
= 0;
4771 /* clear all local breakpoint enable flags */
4772 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4775 * TODO: What about debug traps on tss switch?
4776 * Are we supposed to inject them and update dr6?
4782 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4784 unsigned long exit_qualification
;
4788 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4790 if (exit_qualification
& (1 << 6)) {
4791 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4795 gla_validity
= (exit_qualification
>> 7) & 0x3;
4796 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4797 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4798 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4799 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4800 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4801 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4802 (long unsigned int)exit_qualification
);
4803 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4804 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4808 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4809 trace_kvm_page_fault(gpa
, exit_qualification
);
4810 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
4813 static u64
ept_rsvd_mask(u64 spte
, int level
)
4818 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4819 mask
|= (1ULL << i
);
4822 /* bits 7:3 reserved */
4824 else if (level
== 2) {
4825 if (spte
& (1ULL << 7))
4826 /* 2MB ref, bits 20:12 reserved */
4829 /* bits 6:3 reserved */
4836 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4839 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4841 /* 010b (write-only) */
4842 WARN_ON((spte
& 0x7) == 0x2);
4844 /* 110b (write/execute) */
4845 WARN_ON((spte
& 0x7) == 0x6);
4847 /* 100b (execute-only) and value not supported by logical processor */
4848 if (!cpu_has_vmx_ept_execute_only())
4849 WARN_ON((spte
& 0x7) == 0x4);
4853 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4855 if (rsvd_bits
!= 0) {
4856 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4857 __func__
, rsvd_bits
);
4861 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4862 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4864 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4865 ept_mem_type
== 7) {
4866 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4867 __func__
, ept_mem_type
);
4874 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4877 int nr_sptes
, i
, ret
;
4880 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4882 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
4883 if (likely(ret
== 1))
4884 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
4889 /* It is the real ept misconfig */
4890 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4891 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4893 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4895 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4896 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4898 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4899 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4904 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4906 u32 cpu_based_vm_exec_control
;
4908 /* clear pending NMI */
4909 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4910 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4911 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4912 ++vcpu
->stat
.nmi_window_exits
;
4913 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4918 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4920 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4921 enum emulation_result err
= EMULATE_DONE
;
4924 bool intr_window_requested
;
4926 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4927 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4929 while (!guest_state_valid(vcpu
)) {
4930 if (intr_window_requested
4931 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
4932 return handle_interrupt_window(&vmx
->vcpu
);
4934 err
= emulate_instruction(vcpu
, 0);
4936 if (err
== EMULATE_DO_MMIO
) {
4941 if (err
!= EMULATE_DONE
)
4944 if (signal_pending(current
))
4950 vmx
->emulation_required
= 0;
4956 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4957 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4959 static int handle_pause(struct kvm_vcpu
*vcpu
)
4961 skip_emulated_instruction(vcpu
);
4962 kvm_vcpu_on_spin(vcpu
);
4967 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
4969 kvm_queue_exception(vcpu
, UD_VECTOR
);
4974 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4975 * We could reuse a single VMCS for all the L2 guests, but we also want the
4976 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4977 * allows keeping them loaded on the processor, and in the future will allow
4978 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4979 * every entry if they never change.
4980 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4981 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4983 * The following functions allocate and free a vmcs02 in this pool.
4986 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4987 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
4989 struct vmcs02_list
*item
;
4990 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4991 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
4992 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4993 return &item
->vmcs02
;
4996 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
4997 /* Recycle the least recently used VMCS. */
4998 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
4999 struct vmcs02_list
, list
);
5000 item
->vmptr
= vmx
->nested
.current_vmptr
;
5001 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5002 return &item
->vmcs02
;
5005 /* Create a new VMCS */
5006 item
= (struct vmcs02_list
*)
5007 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5010 item
->vmcs02
.vmcs
= alloc_vmcs();
5011 if (!item
->vmcs02
.vmcs
) {
5015 loaded_vmcs_init(&item
->vmcs02
);
5016 item
->vmptr
= vmx
->nested
.current_vmptr
;
5017 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5018 vmx
->nested
.vmcs02_num
++;
5019 return &item
->vmcs02
;
5022 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5023 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5025 struct vmcs02_list
*item
;
5026 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5027 if (item
->vmptr
== vmptr
) {
5028 free_loaded_vmcs(&item
->vmcs02
);
5029 list_del(&item
->list
);
5031 vmx
->nested
.vmcs02_num
--;
5037 * Free all VMCSs saved for this vcpu, except the one pointed by
5038 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5039 * currently used, if running L2), and vmcs01 when running L2.
5041 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5043 struct vmcs02_list
*item
, *n
;
5044 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5045 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5046 free_loaded_vmcs(&item
->vmcs02
);
5047 list_del(&item
->list
);
5050 vmx
->nested
.vmcs02_num
= 0;
5052 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5053 free_loaded_vmcs(&vmx
->vmcs01
);
5057 * Emulate the VMXON instruction.
5058 * Currently, we just remember that VMX is active, and do not save or even
5059 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5060 * do not currently need to store anything in that guest-allocated memory
5061 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5062 * argument is different from the VMXON pointer (which the spec says they do).
5064 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5066 struct kvm_segment cs
;
5067 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5069 /* The Intel VMX Instruction Reference lists a bunch of bits that
5070 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5071 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5072 * Otherwise, we should fail with #UD. We test these now:
5074 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5075 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5076 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5077 kvm_queue_exception(vcpu
, UD_VECTOR
);
5081 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5082 if (is_long_mode(vcpu
) && !cs
.l
) {
5083 kvm_queue_exception(vcpu
, UD_VECTOR
);
5087 if (vmx_get_cpl(vcpu
)) {
5088 kvm_inject_gp(vcpu
, 0);
5092 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5093 vmx
->nested
.vmcs02_num
= 0;
5095 vmx
->nested
.vmxon
= true;
5097 skip_emulated_instruction(vcpu
);
5102 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5103 * for running VMX instructions (except VMXON, whose prerequisites are
5104 * slightly different). It also specifies what exception to inject otherwise.
5106 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5108 struct kvm_segment cs
;
5109 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5111 if (!vmx
->nested
.vmxon
) {
5112 kvm_queue_exception(vcpu
, UD_VECTOR
);
5116 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5117 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5118 (is_long_mode(vcpu
) && !cs
.l
)) {
5119 kvm_queue_exception(vcpu
, UD_VECTOR
);
5123 if (vmx_get_cpl(vcpu
)) {
5124 kvm_inject_gp(vcpu
, 0);
5132 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5133 * just stops using VMX.
5135 static void free_nested(struct vcpu_vmx
*vmx
)
5137 if (!vmx
->nested
.vmxon
)
5139 vmx
->nested
.vmxon
= false;
5140 if (vmx
->nested
.current_vmptr
!= -1ull) {
5141 kunmap(vmx
->nested
.current_vmcs12_page
);
5142 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5143 vmx
->nested
.current_vmptr
= -1ull;
5144 vmx
->nested
.current_vmcs12
= NULL
;
5146 /* Unpin physical memory we referred to in current vmcs02 */
5147 if (vmx
->nested
.apic_access_page
) {
5148 nested_release_page(vmx
->nested
.apic_access_page
);
5149 vmx
->nested
.apic_access_page
= 0;
5152 nested_free_all_saved_vmcss(vmx
);
5155 /* Emulate the VMXOFF instruction */
5156 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5158 if (!nested_vmx_check_permission(vcpu
))
5160 free_nested(to_vmx(vcpu
));
5161 skip_emulated_instruction(vcpu
);
5166 * Decode the memory-address operand of a vmx instruction, as recorded on an
5167 * exit caused by such an instruction (run by a guest hypervisor).
5168 * On success, returns 0. When the operand is invalid, returns 1 and throws
5171 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5172 unsigned long exit_qualification
,
5173 u32 vmx_instruction_info
, gva_t
*ret
)
5176 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5177 * Execution", on an exit, vmx_instruction_info holds most of the
5178 * addressing components of the operand. Only the displacement part
5179 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5180 * For how an actual address is calculated from all these components,
5181 * refer to Vol. 1, "Operand Addressing".
5183 int scaling
= vmx_instruction_info
& 3;
5184 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5185 bool is_reg
= vmx_instruction_info
& (1u << 10);
5186 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5187 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5188 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5189 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5190 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5193 kvm_queue_exception(vcpu
, UD_VECTOR
);
5197 /* Addr = segment_base + offset */
5198 /* offset = base + [index * scale] + displacement */
5199 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5201 *ret
+= kvm_register_read(vcpu
, base_reg
);
5203 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5204 *ret
+= exit_qualification
; /* holds the displacement */
5206 if (addr_size
== 1) /* 32 bit */
5210 * TODO: throw #GP (and return 1) in various cases that the VM*
5211 * instructions require it - e.g., offset beyond segment limit,
5212 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5213 * address, and so on. Currently these are not checked.
5219 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5220 * set the success or error code of an emulated VMX instruction, as specified
5221 * by Vol 2B, VMX Instruction Reference, "Conventions".
5223 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5225 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5226 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5227 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5230 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5232 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5233 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5234 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5238 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5239 u32 vm_instruction_error
)
5241 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5243 * failValid writes the error number to the current VMCS, which
5244 * can't be done there isn't a current VMCS.
5246 nested_vmx_failInvalid(vcpu
);
5249 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5250 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5251 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5253 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5256 /* Emulate the VMCLEAR instruction */
5257 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5259 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5262 struct vmcs12
*vmcs12
;
5264 struct x86_exception e
;
5266 if (!nested_vmx_check_permission(vcpu
))
5269 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5270 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5273 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5274 sizeof(vmptr
), &e
)) {
5275 kvm_inject_page_fault(vcpu
, &e
);
5279 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5280 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5281 skip_emulated_instruction(vcpu
);
5285 if (vmptr
== vmx
->nested
.current_vmptr
) {
5286 kunmap(vmx
->nested
.current_vmcs12_page
);
5287 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5288 vmx
->nested
.current_vmptr
= -1ull;
5289 vmx
->nested
.current_vmcs12
= NULL
;
5292 page
= nested_get_page(vcpu
, vmptr
);
5295 * For accurate processor emulation, VMCLEAR beyond available
5296 * physical memory should do nothing at all. However, it is
5297 * possible that a nested vmx bug, not a guest hypervisor bug,
5298 * resulted in this case, so let's shut down before doing any
5301 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5304 vmcs12
= kmap(page
);
5305 vmcs12
->launch_state
= 0;
5307 nested_release_page(page
);
5309 nested_free_vmcs02(vmx
, vmptr
);
5311 skip_emulated_instruction(vcpu
);
5312 nested_vmx_succeed(vcpu
);
5316 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5318 /* Emulate the VMLAUNCH instruction */
5319 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5321 return nested_vmx_run(vcpu
, true);
5324 /* Emulate the VMRESUME instruction */
5325 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5328 return nested_vmx_run(vcpu
, false);
5331 enum vmcs_field_type
{
5332 VMCS_FIELD_TYPE_U16
= 0,
5333 VMCS_FIELD_TYPE_U64
= 1,
5334 VMCS_FIELD_TYPE_U32
= 2,
5335 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5338 static inline int vmcs_field_type(unsigned long field
)
5340 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5341 return VMCS_FIELD_TYPE_U32
;
5342 return (field
>> 13) & 0x3 ;
5345 static inline int vmcs_field_readonly(unsigned long field
)
5347 return (((field
>> 10) & 0x3) == 1);
5351 * Read a vmcs12 field. Since these can have varying lengths and we return
5352 * one type, we chose the biggest type (u64) and zero-extend the return value
5353 * to that size. Note that the caller, handle_vmread, might need to use only
5354 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5355 * 64-bit fields are to be returned).
5357 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5358 unsigned long field
, u64
*ret
)
5360 short offset
= vmcs_field_to_offset(field
);
5366 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5368 switch (vmcs_field_type(field
)) {
5369 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5370 *ret
= *((natural_width
*)p
);
5372 case VMCS_FIELD_TYPE_U16
:
5375 case VMCS_FIELD_TYPE_U32
:
5378 case VMCS_FIELD_TYPE_U64
:
5382 return 0; /* can never happen. */
5387 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5388 * used before) all generate the same failure when it is missing.
5390 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5392 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5393 if (vmx
->nested
.current_vmptr
== -1ull) {
5394 nested_vmx_failInvalid(vcpu
);
5395 skip_emulated_instruction(vcpu
);
5401 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5403 unsigned long field
;
5405 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5406 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5409 if (!nested_vmx_check_permission(vcpu
) ||
5410 !nested_vmx_check_vmcs12(vcpu
))
5413 /* Decode instruction info and find the field to read */
5414 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5415 /* Read the field, zero-extended to a u64 field_value */
5416 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5417 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5418 skip_emulated_instruction(vcpu
);
5422 * Now copy part of this value to register or memory, as requested.
5423 * Note that the number of bits actually copied is 32 or 64 depending
5424 * on the guest's mode (32 or 64 bit), not on the given field's length.
5426 if (vmx_instruction_info
& (1u << 10)) {
5427 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5430 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5431 vmx_instruction_info
, &gva
))
5433 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5434 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5435 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5438 nested_vmx_succeed(vcpu
);
5439 skip_emulated_instruction(vcpu
);
5444 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5446 unsigned long field
;
5448 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5449 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5452 /* The value to write might be 32 or 64 bits, depending on L1's long
5453 * mode, and eventually we need to write that into a field of several
5454 * possible lengths. The code below first zero-extends the value to 64
5455 * bit (field_value), and then copies only the approriate number of
5456 * bits into the vmcs12 field.
5458 u64 field_value
= 0;
5459 struct x86_exception e
;
5461 if (!nested_vmx_check_permission(vcpu
) ||
5462 !nested_vmx_check_vmcs12(vcpu
))
5465 if (vmx_instruction_info
& (1u << 10))
5466 field_value
= kvm_register_read(vcpu
,
5467 (((vmx_instruction_info
) >> 3) & 0xf));
5469 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5470 vmx_instruction_info
, &gva
))
5472 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5473 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5474 kvm_inject_page_fault(vcpu
, &e
);
5480 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5481 if (vmcs_field_readonly(field
)) {
5482 nested_vmx_failValid(vcpu
,
5483 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5484 skip_emulated_instruction(vcpu
);
5488 offset
= vmcs_field_to_offset(field
);
5490 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5491 skip_emulated_instruction(vcpu
);
5494 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5496 switch (vmcs_field_type(field
)) {
5497 case VMCS_FIELD_TYPE_U16
:
5498 *(u16
*)p
= field_value
;
5500 case VMCS_FIELD_TYPE_U32
:
5501 *(u32
*)p
= field_value
;
5503 case VMCS_FIELD_TYPE_U64
:
5504 *(u64
*)p
= field_value
;
5506 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5507 *(natural_width
*)p
= field_value
;
5510 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5511 skip_emulated_instruction(vcpu
);
5515 nested_vmx_succeed(vcpu
);
5516 skip_emulated_instruction(vcpu
);
5520 /* Emulate the VMPTRLD instruction */
5521 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5523 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5526 struct x86_exception e
;
5528 if (!nested_vmx_check_permission(vcpu
))
5531 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5532 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5535 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5536 sizeof(vmptr
), &e
)) {
5537 kvm_inject_page_fault(vcpu
, &e
);
5541 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5542 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5543 skip_emulated_instruction(vcpu
);
5547 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5548 struct vmcs12
*new_vmcs12
;
5550 page
= nested_get_page(vcpu
, vmptr
);
5552 nested_vmx_failInvalid(vcpu
);
5553 skip_emulated_instruction(vcpu
);
5556 new_vmcs12
= kmap(page
);
5557 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5559 nested_release_page_clean(page
);
5560 nested_vmx_failValid(vcpu
,
5561 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5562 skip_emulated_instruction(vcpu
);
5565 if (vmx
->nested
.current_vmptr
!= -1ull) {
5566 kunmap(vmx
->nested
.current_vmcs12_page
);
5567 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5570 vmx
->nested
.current_vmptr
= vmptr
;
5571 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5572 vmx
->nested
.current_vmcs12_page
= page
;
5575 nested_vmx_succeed(vcpu
);
5576 skip_emulated_instruction(vcpu
);
5580 /* Emulate the VMPTRST instruction */
5581 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5583 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5584 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5586 struct x86_exception e
;
5588 if (!nested_vmx_check_permission(vcpu
))
5591 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5592 vmx_instruction_info
, &vmcs_gva
))
5594 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5595 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5596 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5598 kvm_inject_page_fault(vcpu
, &e
);
5601 nested_vmx_succeed(vcpu
);
5602 skip_emulated_instruction(vcpu
);
5607 * The exit handlers return 1 if the exit was handled fully and guest execution
5608 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5609 * to be done to userspace and return 0.
5611 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5612 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5613 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5614 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5615 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5616 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5617 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5618 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5619 [EXIT_REASON_CPUID
] = handle_cpuid
,
5620 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5621 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5622 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5623 [EXIT_REASON_HLT
] = handle_halt
,
5624 [EXIT_REASON_INVD
] = handle_invd
,
5625 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5626 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
5627 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5628 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5629 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5630 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5631 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5632 [EXIT_REASON_VMREAD
] = handle_vmread
,
5633 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5634 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5635 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5636 [EXIT_REASON_VMON
] = handle_vmon
,
5637 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5638 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5639 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5640 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5641 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5642 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5643 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5644 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5645 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5646 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5647 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5650 static const int kvm_vmx_max_exit_handlers
=
5651 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5654 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5655 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5656 * disinterest in the current event (read or write a specific MSR) by using an
5657 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5659 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5660 struct vmcs12
*vmcs12
, u32 exit_reason
)
5662 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5665 if (!nested_cpu_has(get_vmcs12(vcpu
), CPU_BASED_USE_MSR_BITMAPS
))
5669 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5670 * for the four combinations of read/write and low/high MSR numbers.
5671 * First we need to figure out which of the four to use:
5673 bitmap
= vmcs12
->msr_bitmap
;
5674 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5676 if (msr_index
>= 0xc0000000) {
5677 msr_index
-= 0xc0000000;
5681 /* Then read the msr_index'th bit from this bitmap: */
5682 if (msr_index
< 1024*8) {
5684 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5685 return 1 & (b
>> (msr_index
& 7));
5687 return 1; /* let L1 handle the wrong parameter */
5691 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5692 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5693 * intercept (via guest_host_mask etc.) the current event.
5695 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5696 struct vmcs12
*vmcs12
)
5698 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5699 int cr
= exit_qualification
& 15;
5700 int reg
= (exit_qualification
>> 8) & 15;
5701 unsigned long val
= kvm_register_read(vcpu
, reg
);
5703 switch ((exit_qualification
>> 4) & 3) {
5704 case 0: /* mov to cr */
5707 if (vmcs12
->cr0_guest_host_mask
&
5708 (val
^ vmcs12
->cr0_read_shadow
))
5712 if ((vmcs12
->cr3_target_count
>= 1 &&
5713 vmcs12
->cr3_target_value0
== val
) ||
5714 (vmcs12
->cr3_target_count
>= 2 &&
5715 vmcs12
->cr3_target_value1
== val
) ||
5716 (vmcs12
->cr3_target_count
>= 3 &&
5717 vmcs12
->cr3_target_value2
== val
) ||
5718 (vmcs12
->cr3_target_count
>= 4 &&
5719 vmcs12
->cr3_target_value3
== val
))
5721 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5725 if (vmcs12
->cr4_guest_host_mask
&
5726 (vmcs12
->cr4_read_shadow
^ val
))
5730 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5736 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5737 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5740 case 1: /* mov from cr */
5743 if (vmcs12
->cpu_based_vm_exec_control
&
5744 CPU_BASED_CR3_STORE_EXITING
)
5748 if (vmcs12
->cpu_based_vm_exec_control
&
5749 CPU_BASED_CR8_STORE_EXITING
)
5756 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5757 * cr0. Other attempted changes are ignored, with no exit.
5759 if (vmcs12
->cr0_guest_host_mask
& 0xe &
5760 (val
^ vmcs12
->cr0_read_shadow
))
5762 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
5763 !(vmcs12
->cr0_read_shadow
& 0x1) &&
5772 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5773 * should handle it ourselves in L0 (and then continue L2). Only call this
5774 * when in is_guest_mode (L2).
5776 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
5778 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5779 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5780 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5781 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5783 if (vmx
->nested
.nested_run_pending
)
5786 if (unlikely(vmx
->fail
)) {
5787 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
5788 vmcs_read32(VM_INSTRUCTION_ERROR
));
5792 switch (exit_reason
) {
5793 case EXIT_REASON_EXCEPTION_NMI
:
5794 if (!is_exception(intr_info
))
5796 else if (is_page_fault(intr_info
))
5798 return vmcs12
->exception_bitmap
&
5799 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
5800 case EXIT_REASON_EXTERNAL_INTERRUPT
:
5802 case EXIT_REASON_TRIPLE_FAULT
:
5804 case EXIT_REASON_PENDING_INTERRUPT
:
5805 case EXIT_REASON_NMI_WINDOW
:
5807 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5808 * (aka Interrupt Window Exiting) only when L1 turned it on,
5809 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5810 * Same for NMI Window Exiting.
5813 case EXIT_REASON_TASK_SWITCH
:
5815 case EXIT_REASON_CPUID
:
5817 case EXIT_REASON_HLT
:
5818 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
5819 case EXIT_REASON_INVD
:
5821 case EXIT_REASON_INVLPG
:
5822 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
5823 case EXIT_REASON_RDPMC
:
5824 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
5825 case EXIT_REASON_RDTSC
:
5826 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
5827 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
5828 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
5829 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
5830 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
5831 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
5833 * VMX instructions trap unconditionally. This allows L1 to
5834 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5837 case EXIT_REASON_CR_ACCESS
:
5838 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
5839 case EXIT_REASON_DR_ACCESS
:
5840 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
5841 case EXIT_REASON_IO_INSTRUCTION
:
5842 /* TODO: support IO bitmaps */
5844 case EXIT_REASON_MSR_READ
:
5845 case EXIT_REASON_MSR_WRITE
:
5846 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
5847 case EXIT_REASON_INVALID_STATE
:
5849 case EXIT_REASON_MWAIT_INSTRUCTION
:
5850 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
5851 case EXIT_REASON_MONITOR_INSTRUCTION
:
5852 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
5853 case EXIT_REASON_PAUSE_INSTRUCTION
:
5854 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
5855 nested_cpu_has2(vmcs12
,
5856 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
5857 case EXIT_REASON_MCE_DURING_VMENTRY
:
5859 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
5861 case EXIT_REASON_APIC_ACCESS
:
5862 return nested_cpu_has2(vmcs12
,
5863 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
5864 case EXIT_REASON_EPT_VIOLATION
:
5865 case EXIT_REASON_EPT_MISCONFIG
:
5867 case EXIT_REASON_WBINVD
:
5868 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
5869 case EXIT_REASON_XSETBV
:
5876 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
5878 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
5879 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
5883 * The guest has exited. See if we can fix it or if we need userspace
5886 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
5888 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5889 u32 exit_reason
= vmx
->exit_reason
;
5890 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5892 /* If guest state is invalid, start emulating */
5893 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5894 return handle_invalid_guest_state(vcpu
);
5897 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5898 * we did not inject a still-pending event to L1 now because of
5899 * nested_run_pending, we need to re-enable this bit.
5901 if (vmx
->nested
.nested_run_pending
)
5902 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5904 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
5905 exit_reason
== EXIT_REASON_VMRESUME
))
5906 vmx
->nested
.nested_run_pending
= 1;
5908 vmx
->nested
.nested_run_pending
= 0;
5910 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
5911 nested_vmx_vmexit(vcpu
);
5915 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
5916 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5917 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5922 if (unlikely(vmx
->fail
)) {
5923 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5924 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5925 = vmcs_read32(VM_INSTRUCTION_ERROR
);
5929 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5930 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
5931 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
5932 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
5933 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
5934 "(0x%x) and exit reason is 0x%x\n",
5935 __func__
, vectoring_info
, exit_reason
);
5937 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
5938 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
5939 get_vmcs12(vcpu
), vcpu
)))) {
5940 if (vmx_interrupt_allowed(vcpu
)) {
5941 vmx
->soft_vnmi_blocked
= 0;
5942 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
5943 vcpu
->arch
.nmi_pending
) {
5945 * This CPU don't support us in finding the end of an
5946 * NMI-blocked window if the guest runs with IRQs
5947 * disabled. So we pull the trigger after 1 s of
5948 * futile waiting, but inform the user about this.
5950 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
5951 "state on VCPU %d after 1 s timeout\n",
5952 __func__
, vcpu
->vcpu_id
);
5953 vmx
->soft_vnmi_blocked
= 0;
5957 if (exit_reason
< kvm_vmx_max_exit_handlers
5958 && kvm_vmx_exit_handlers
[exit_reason
])
5959 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
5961 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5962 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
5967 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5969 if (irr
== -1 || tpr
< irr
) {
5970 vmcs_write32(TPR_THRESHOLD
, 0);
5974 vmcs_write32(TPR_THRESHOLD
, irr
);
5977 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
5981 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
5982 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
5985 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5986 exit_intr_info
= vmx
->exit_intr_info
;
5988 /* Handle machine checks before interrupts are enabled */
5989 if (is_machine_check(exit_intr_info
))
5990 kvm_machine_check();
5992 /* We need to handle NMIs before interrupts are enabled */
5993 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
5994 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
5995 kvm_before_handle_nmi(&vmx
->vcpu
);
5997 kvm_after_handle_nmi(&vmx
->vcpu
);
6001 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6006 bool idtv_info_valid
;
6008 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6010 if (cpu_has_virtual_nmis()) {
6011 if (vmx
->nmi_known_unmasked
)
6014 * Can't use vmx->exit_intr_info since we're not sure what
6015 * the exit reason is.
6017 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6018 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6019 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6021 * SDM 3: 27.7.1.2 (September 2008)
6022 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6023 * a guest IRET fault.
6024 * SDM 3: 23.2.2 (September 2008)
6025 * Bit 12 is undefined in any of the following cases:
6026 * If the VM exit sets the valid bit in the IDT-vectoring
6027 * information field.
6028 * If the VM exit is due to a double fault.
6030 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6031 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6032 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6033 GUEST_INTR_STATE_NMI
);
6035 vmx
->nmi_known_unmasked
=
6036 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6037 & GUEST_INTR_STATE_NMI
);
6038 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6039 vmx
->vnmi_blocked_time
+=
6040 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6043 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
6044 u32 idt_vectoring_info
,
6045 int instr_len_field
,
6046 int error_code_field
)
6050 bool idtv_info_valid
;
6052 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6054 vmx
->vcpu
.arch
.nmi_injected
= false;
6055 kvm_clear_exception_queue(&vmx
->vcpu
);
6056 kvm_clear_interrupt_queue(&vmx
->vcpu
);
6058 if (!idtv_info_valid
)
6061 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6063 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6064 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6067 case INTR_TYPE_NMI_INTR
:
6068 vmx
->vcpu
.arch
.nmi_injected
= true;
6070 * SDM 3: 27.7.1.2 (September 2008)
6071 * Clear bit "block by NMI" before VM entry if a NMI
6074 vmx_set_nmi_mask(&vmx
->vcpu
, false);
6076 case INTR_TYPE_SOFT_EXCEPTION
:
6077 vmx
->vcpu
.arch
.event_exit_inst_len
=
6078 vmcs_read32(instr_len_field
);
6080 case INTR_TYPE_HARD_EXCEPTION
:
6081 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6082 u32 err
= vmcs_read32(error_code_field
);
6083 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
6085 kvm_queue_exception(&vmx
->vcpu
, vector
);
6087 case INTR_TYPE_SOFT_INTR
:
6088 vmx
->vcpu
.arch
.event_exit_inst_len
=
6089 vmcs_read32(instr_len_field
);
6091 case INTR_TYPE_EXT_INTR
:
6092 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
6093 type
== INTR_TYPE_SOFT_INTR
);
6100 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6102 if (is_guest_mode(&vmx
->vcpu
))
6104 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
6105 VM_EXIT_INSTRUCTION_LEN
,
6106 IDT_VECTORING_ERROR_CODE
);
6109 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6111 if (is_guest_mode(vcpu
))
6113 __vmx_complete_interrupts(to_vmx(vcpu
),
6114 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6115 VM_ENTRY_INSTRUCTION_LEN
,
6116 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6118 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6121 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6124 struct perf_guest_switch_msr
*msrs
;
6126 msrs
= perf_guest_get_msrs(&nr_msrs
);
6131 for (i
= 0; i
< nr_msrs
; i
++)
6132 if (msrs
[i
].host
== msrs
[i
].guest
)
6133 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6135 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6139 #ifdef CONFIG_X86_64
6147 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6149 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6151 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
6152 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6153 if (vmcs12
->idt_vectoring_info_field
&
6154 VECTORING_INFO_VALID_MASK
) {
6155 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6156 vmcs12
->idt_vectoring_info_field
);
6157 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6158 vmcs12
->vm_exit_instruction_len
);
6159 if (vmcs12
->idt_vectoring_info_field
&
6160 VECTORING_INFO_DELIVER_CODE_MASK
)
6161 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6162 vmcs12
->idt_vectoring_error_code
);
6166 /* Record the guest's net vcpu time for enforced NMI injections. */
6167 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6168 vmx
->entry_time
= ktime_get();
6170 /* Don't enter VMX if guest state is invalid, let the exit handler
6171 start emulation until we arrive back to a valid state */
6172 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
6175 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6176 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6177 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6178 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6180 /* When single-stepping over STI and MOV SS, we must clear the
6181 * corresponding interruptibility bits in the guest state. Otherwise
6182 * vmentry fails as it then expects bit 14 (BS) in pending debug
6183 * exceptions being set, but that's not correct for the guest debugging
6185 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6186 vmx_set_interrupt_shadow(vcpu
, 0);
6188 atomic_switch_perf_msrs(vmx
);
6190 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6192 /* Store host registers */
6193 "push %%"R
"dx; push %%"R
"bp;"
6194 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
6196 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
6198 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
6199 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6201 /* Reload cr2 if changed */
6202 "mov %c[cr2](%0), %%"R
"ax \n\t"
6203 "mov %%cr2, %%"R
"dx \n\t"
6204 "cmp %%"R
"ax, %%"R
"dx \n\t"
6206 "mov %%"R
"ax, %%cr2 \n\t"
6208 /* Check if vmlaunch of vmresume is needed */
6209 "cmpl $0, %c[launched](%0) \n\t"
6210 /* Load guest registers. Don't clobber flags. */
6211 "mov %c[rax](%0), %%"R
"ax \n\t"
6212 "mov %c[rbx](%0), %%"R
"bx \n\t"
6213 "mov %c[rdx](%0), %%"R
"dx \n\t"
6214 "mov %c[rsi](%0), %%"R
"si \n\t"
6215 "mov %c[rdi](%0), %%"R
"di \n\t"
6216 "mov %c[rbp](%0), %%"R
"bp \n\t"
6217 #ifdef CONFIG_X86_64
6218 "mov %c[r8](%0), %%r8 \n\t"
6219 "mov %c[r9](%0), %%r9 \n\t"
6220 "mov %c[r10](%0), %%r10 \n\t"
6221 "mov %c[r11](%0), %%r11 \n\t"
6222 "mov %c[r12](%0), %%r12 \n\t"
6223 "mov %c[r13](%0), %%r13 \n\t"
6224 "mov %c[r14](%0), %%r14 \n\t"
6225 "mov %c[r15](%0), %%r15 \n\t"
6227 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
6229 /* Enter guest mode */
6230 "jne .Llaunched \n\t"
6231 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6232 "jmp .Lkvm_vmx_return \n\t"
6233 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6234 ".Lkvm_vmx_return: "
6235 /* Save guest registers, load host registers, keep flags */
6236 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
6238 "mov %%"R
"ax, %c[rax](%0) \n\t"
6239 "mov %%"R
"bx, %c[rbx](%0) \n\t"
6240 "pop"Q
" %c[rcx](%0) \n\t"
6241 "mov %%"R
"dx, %c[rdx](%0) \n\t"
6242 "mov %%"R
"si, %c[rsi](%0) \n\t"
6243 "mov %%"R
"di, %c[rdi](%0) \n\t"
6244 "mov %%"R
"bp, %c[rbp](%0) \n\t"
6245 #ifdef CONFIG_X86_64
6246 "mov %%r8, %c[r8](%0) \n\t"
6247 "mov %%r9, %c[r9](%0) \n\t"
6248 "mov %%r10, %c[r10](%0) \n\t"
6249 "mov %%r11, %c[r11](%0) \n\t"
6250 "mov %%r12, %c[r12](%0) \n\t"
6251 "mov %%r13, %c[r13](%0) \n\t"
6252 "mov %%r14, %c[r14](%0) \n\t"
6253 "mov %%r15, %c[r15](%0) \n\t"
6255 "mov %%cr2, %%"R
"ax \n\t"
6256 "mov %%"R
"ax, %c[cr2](%0) \n\t"
6258 "pop %%"R
"bp; pop %%"R
"dx \n\t"
6259 "setbe %c[fail](%0) \n\t"
6260 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6261 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6262 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6263 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6264 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6265 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6266 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6267 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6268 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6269 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6270 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6271 #ifdef CONFIG_X86_64
6272 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6273 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6274 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6275 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6276 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6277 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6278 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6279 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6281 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6282 [wordsize
]"i"(sizeof(ulong
))
6284 , R
"ax", R
"bx", R
"di", R
"si"
6285 #ifdef CONFIG_X86_64
6286 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6290 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6291 | (1 << VCPU_EXREG_RFLAGS
)
6292 | (1 << VCPU_EXREG_CPL
)
6293 | (1 << VCPU_EXREG_PDPTR
)
6294 | (1 << VCPU_EXREG_SEGMENTS
)
6295 | (1 << VCPU_EXREG_CR3
));
6296 vcpu
->arch
.regs_dirty
= 0;
6298 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6300 if (is_guest_mode(vcpu
)) {
6301 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6302 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6303 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6304 vmcs12
->idt_vectoring_error_code
=
6305 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6306 vmcs12
->vm_exit_instruction_len
=
6307 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6311 vmx
->loaded_vmcs
->launched
= 1;
6313 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6314 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6316 vmx_complete_atomic_exit(vmx
);
6317 vmx_recover_nmi_blocking(vmx
);
6318 vmx_complete_interrupts(vmx
);
6324 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6326 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6330 free_loaded_vmcs(vmx
->loaded_vmcs
);
6331 kfree(vmx
->guest_msrs
);
6332 kvm_vcpu_uninit(vcpu
);
6333 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6336 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6339 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6343 return ERR_PTR(-ENOMEM
);
6347 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6351 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6353 if (!vmx
->guest_msrs
) {
6357 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6358 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6359 if (!vmx
->loaded_vmcs
->vmcs
)
6362 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6363 loaded_vmcs_init(vmx
->loaded_vmcs
);
6368 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6369 vmx
->vcpu
.cpu
= cpu
;
6370 err
= vmx_vcpu_setup(vmx
);
6371 vmx_vcpu_put(&vmx
->vcpu
);
6375 if (vm_need_virtualize_apic_accesses(kvm
))
6376 err
= alloc_apic_access_page(kvm
);
6381 if (!kvm
->arch
.ept_identity_map_addr
)
6382 kvm
->arch
.ept_identity_map_addr
=
6383 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6385 if (alloc_identity_pagetable(kvm
) != 0)
6387 if (!init_rmode_identity_map(kvm
))
6391 vmx
->nested
.current_vmptr
= -1ull;
6392 vmx
->nested
.current_vmcs12
= NULL
;
6397 free_loaded_vmcs(vmx
->loaded_vmcs
);
6399 kfree(vmx
->guest_msrs
);
6401 kvm_vcpu_uninit(&vmx
->vcpu
);
6404 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6405 return ERR_PTR(err
);
6408 static void __init
vmx_check_processor_compat(void *rtn
)
6410 struct vmcs_config vmcs_conf
;
6413 if (setup_vmcs_config(&vmcs_conf
) < 0)
6415 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6416 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6417 smp_processor_id());
6422 static int get_ept_level(void)
6424 return VMX_EPT_DEFAULT_GAW
+ 1;
6427 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6431 /* For VT-d and EPT combination
6432 * 1. MMIO: always map as UC
6434 * a. VT-d without snooping control feature: can't guarantee the
6435 * result, try to trust guest.
6436 * b. VT-d with snooping control feature: snooping control feature of
6437 * VT-d engine can guarantee the cache correctness. Just set it
6438 * to WB to keep consistent with host. So the same as item 3.
6439 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6440 * consistent with host MTRR
6443 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6444 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6445 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6446 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6447 VMX_EPT_MT_EPTE_SHIFT
;
6449 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6455 static int vmx_get_lpage_level(void)
6457 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6458 return PT_DIRECTORY_LEVEL
;
6460 /* For shadow and EPT supported 1GB page */
6461 return PT_PDPE_LEVEL
;
6464 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6466 struct kvm_cpuid_entry2
*best
;
6467 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6470 vmx
->rdtscp_enabled
= false;
6471 if (vmx_rdtscp_supported()) {
6472 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6473 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6474 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6475 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6476 vmx
->rdtscp_enabled
= true;
6478 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6479 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6486 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6488 if (func
== 1 && nested
)
6489 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6493 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6494 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6495 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6496 * guest in a way that will both be appropriate to L1's requests, and our
6497 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6498 * function also has additional necessary side-effects, like setting various
6499 * vcpu->arch fields.
6501 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6503 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6506 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6507 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6508 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6509 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6510 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6511 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6512 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6513 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6514 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6515 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6516 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6517 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6518 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6519 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6520 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6521 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6522 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6523 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6524 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6525 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6526 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6527 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6528 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6529 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6530 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6531 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6532 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6533 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6534 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6535 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6536 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6537 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6538 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6539 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6540 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6541 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6543 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6545 vmcs12
->vm_entry_intr_info_field
);
6546 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6547 vmcs12
->vm_entry_exception_error_code
);
6548 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6549 vmcs12
->vm_entry_instruction_len
);
6550 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6551 vmcs12
->guest_interruptibility_info
);
6552 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6553 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6554 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6555 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6556 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6557 vmcs12
->guest_pending_dbg_exceptions
);
6558 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6559 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6561 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6563 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6564 (vmcs_config
.pin_based_exec_ctrl
|
6565 vmcs12
->pin_based_vm_exec_control
));
6568 * Whether page-faults are trapped is determined by a combination of
6569 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6570 * If enable_ept, L0 doesn't care about page faults and we should
6571 * set all of these to L1's desires. However, if !enable_ept, L0 does
6572 * care about (at least some) page faults, and because it is not easy
6573 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6574 * to exit on each and every L2 page fault. This is done by setting
6575 * MASK=MATCH=0 and (see below) EB.PF=1.
6576 * Note that below we don't need special code to set EB.PF beyond the
6577 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6578 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6579 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6581 * A problem with this approach (when !enable_ept) is that L1 may be
6582 * injected with more page faults than it asked for. This could have
6583 * caused problems, but in practice existing hypervisors don't care.
6584 * To fix this, we will need to emulate the PFEC checking (on the L1
6585 * page tables), using walk_addr(), when injecting PFs to L1.
6587 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6588 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6589 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6590 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6592 if (cpu_has_secondary_exec_ctrls()) {
6593 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6594 if (!vmx
->rdtscp_enabled
)
6595 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6596 /* Take the following fields only from vmcs12 */
6597 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6598 if (nested_cpu_has(vmcs12
,
6599 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6600 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6602 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6604 * Translate L1 physical address to host physical
6605 * address for vmcs02. Keep the page pinned, so this
6606 * physical address remains valid. We keep a reference
6607 * to it so we can release it later.
6609 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6610 nested_release_page(vmx
->nested
.apic_access_page
);
6611 vmx
->nested
.apic_access_page
=
6612 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6614 * If translation failed, no matter: This feature asks
6615 * to exit when accessing the given address, and if it
6616 * can never be accessed, this feature won't do
6619 if (!vmx
->nested
.apic_access_page
)
6621 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6623 vmcs_write64(APIC_ACCESS_ADDR
,
6624 page_to_phys(vmx
->nested
.apic_access_page
));
6627 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6632 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6633 * Some constant fields are set here by vmx_set_constant_host_state().
6634 * Other fields are different per CPU, and will be set later when
6635 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6637 vmx_set_constant_host_state();
6640 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6641 * entry, but only if the current (host) sp changed from the value
6642 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6643 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6644 * here we just force the write to happen on entry.
6648 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
6649 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
6650 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6651 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6652 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
6654 * Merging of IO and MSR bitmaps not currently supported.
6655 * Rather, exit every time.
6657 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
6658 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
6659 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
6661 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
6663 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6664 * bitwise-or of what L1 wants to trap for L2, and what we want to
6665 * trap. Note that CR0.TS also needs updating - we do this later.
6667 update_exception_bitmap(vcpu
);
6668 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
6669 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6671 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6672 vmcs_write32(VM_EXIT_CONTROLS
,
6673 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
6674 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
6675 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
6677 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
6678 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
6679 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6680 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6683 set_cr4_guest_host_mask(vmx
);
6685 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
6686 vmcs_write64(TSC_OFFSET
,
6687 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
6689 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6693 * Trivially support vpid by letting L2s share their parent
6694 * L1's vpid. TODO: move to a more elaborate solution, giving
6695 * each L2 its own vpid and exposing the vpid feature to L1.
6697 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6698 vmx_flush_tlb(vcpu
);
6701 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
6702 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
6703 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
6704 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6706 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6707 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6708 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6711 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6712 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6713 * The CR0_READ_SHADOW is what L2 should have expected to read given
6714 * the specifications by L1; It's not enough to take
6715 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6716 * have more bits than L1 expected.
6718 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
6719 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
6721 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
6722 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
6724 /* shadow page tables on either EPT or shadow page tables */
6725 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
6726 kvm_mmu_reset_context(vcpu
);
6728 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
6729 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
6733 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6734 * for running an L2 nested guest.
6736 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
6738 struct vmcs12
*vmcs12
;
6739 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6741 struct loaded_vmcs
*vmcs02
;
6743 if (!nested_vmx_check_permission(vcpu
) ||
6744 !nested_vmx_check_vmcs12(vcpu
))
6747 skip_emulated_instruction(vcpu
);
6748 vmcs12
= get_vmcs12(vcpu
);
6751 * The nested entry process starts with enforcing various prerequisites
6752 * on vmcs12 as required by the Intel SDM, and act appropriately when
6753 * they fail: As the SDM explains, some conditions should cause the
6754 * instruction to fail, while others will cause the instruction to seem
6755 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6756 * To speed up the normal (success) code path, we should avoid checking
6757 * for misconfigurations which will anyway be caught by the processor
6758 * when using the merged vmcs02.
6760 if (vmcs12
->launch_state
== launch
) {
6761 nested_vmx_failValid(vcpu
,
6762 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6763 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
6767 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
6768 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
6769 /*TODO: Also verify bits beyond physical address width are 0*/
6770 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6774 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
6775 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
6776 /*TODO: Also verify bits beyond physical address width are 0*/
6777 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6781 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
6782 vmcs12
->vm_exit_msr_load_count
> 0 ||
6783 vmcs12
->vm_exit_msr_store_count
> 0) {
6784 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6786 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6790 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
6791 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
6792 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
6793 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
6794 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
6795 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
6796 !vmx_control_verify(vmcs12
->vm_exit_controls
,
6797 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
6798 !vmx_control_verify(vmcs12
->vm_entry_controls
,
6799 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
6801 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6805 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6806 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6807 nested_vmx_failValid(vcpu
,
6808 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
6812 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6813 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6814 nested_vmx_entry_failure(vcpu
, vmcs12
,
6815 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
6818 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
6819 nested_vmx_entry_failure(vcpu
, vmcs12
,
6820 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
6825 * We're finally done with prerequisite checking, and can start with
6829 vmcs02
= nested_get_current_vmcs02(vmx
);
6833 enter_guest_mode(vcpu
);
6835 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
6838 vmx
->loaded_vmcs
= vmcs02
;
6840 vmx_vcpu_load(vcpu
, cpu
);
6844 vmcs12
->launch_state
= 1;
6846 prepare_vmcs02(vcpu
, vmcs12
);
6849 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6850 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6851 * returned as far as L1 is concerned. It will only return (and set
6852 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6858 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6859 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6860 * This function returns the new value we should put in vmcs12.guest_cr0.
6861 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6862 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6863 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6864 * didn't trap the bit, because if L1 did, so would L0).
6865 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6866 * been modified by L2, and L1 knows it. So just leave the old value of
6867 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6868 * isn't relevant, because if L0 traps this bit it can set it to anything.
6869 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6870 * changed these bits, and therefore they need to be updated, but L0
6871 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6872 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6874 static inline unsigned long
6875 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6878 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
6879 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
6880 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
6881 vcpu
->arch
.cr0_guest_owned_bits
));
6884 static inline unsigned long
6885 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6888 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
6889 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
6890 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
6891 vcpu
->arch
.cr4_guest_owned_bits
));
6895 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6896 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6897 * and this function updates it to reflect the changes to the guest state while
6898 * L2 was running (and perhaps made some exits which were handled directly by L0
6899 * without going back to L1), and to reflect the exit reason.
6900 * Note that we do not have to copy here all VMCS fields, just those that
6901 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6902 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6903 * which already writes to vmcs12 directly.
6905 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6907 /* update guest state fields: */
6908 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
6909 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
6911 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
6912 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
6913 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
6914 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
6916 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
6917 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
6918 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
6919 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
6920 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
6921 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
6922 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
6923 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
6924 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
6925 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
6926 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
6927 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
6928 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
6929 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
6930 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
6931 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
6932 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
6933 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
6934 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
6935 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
6936 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
6937 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
6938 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
6939 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
6940 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
6941 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
6942 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
6943 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
6944 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
6945 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
6946 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
6947 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
6948 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
6949 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
6950 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
6951 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
6953 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
6954 vmcs12
->guest_interruptibility_info
=
6955 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
6956 vmcs12
->guest_pending_dbg_exceptions
=
6957 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
6959 /* TODO: These cannot have changed unless we have MSR bitmaps and
6960 * the relevant bit asks not to trap the change */
6961 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
6962 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
6963 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
6964 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
6965 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
6966 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
6968 /* update exit information fields: */
6970 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6971 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6973 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6974 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6975 vmcs12
->idt_vectoring_info_field
=
6976 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6977 vmcs12
->idt_vectoring_error_code
=
6978 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6979 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6980 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6982 /* clear vm-entry fields which are to be cleared on exit */
6983 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
6984 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
6988 * A part of what we need to when the nested L2 guest exits and we want to
6989 * run its L1 parent, is to reset L1's guest state to the host state specified
6991 * This function is to be called not only on normal nested exit, but also on
6992 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6993 * Failures During or After Loading Guest State").
6994 * This function should be called when the active VMCS is L1's (vmcs01).
6996 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6998 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
6999 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7000 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7001 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7003 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7004 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7006 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7007 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7009 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7010 * actually changed, because it depends on the current state of
7011 * fpu_active (which may have changed).
7012 * Note that vmx_set_cr0 refers to efer set above.
7014 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
7016 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7017 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7018 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7020 update_exception_bitmap(vcpu
);
7021 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
7022 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7025 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7026 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7028 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
7029 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
7031 /* shadow page tables on either EPT or shadow page tables */
7032 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
7033 kvm_mmu_reset_context(vcpu
);
7037 * Trivially support vpid by letting L2s share their parent
7038 * L1's vpid. TODO: move to a more elaborate solution, giving
7039 * each L2 its own vpid and exposing the vpid feature to L1.
7041 vmx_flush_tlb(vcpu
);
7045 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
7046 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
7047 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
7048 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
7049 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
7050 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
7051 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
7052 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
7053 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
7054 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
7055 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
7056 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
7057 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
7058 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
7059 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
7061 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
7062 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
7063 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7064 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
7065 vmcs12
->host_ia32_perf_global_ctrl
);
7069 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7070 * and modify vmcs12 to make it see what it would expect to see there if
7071 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7073 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
7075 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7077 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7079 leave_guest_mode(vcpu
);
7080 prepare_vmcs12(vcpu
, vmcs12
);
7083 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7085 vmx_vcpu_load(vcpu
, cpu
);
7089 /* if no vmcs02 cache requested, remove the one we used */
7090 if (VMCS02_POOL_SIZE
== 0)
7091 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
7093 load_vmcs12_host_state(vcpu
, vmcs12
);
7095 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7096 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7098 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7101 /* Unpin physical memory we referred to in vmcs02 */
7102 if (vmx
->nested
.apic_access_page
) {
7103 nested_release_page(vmx
->nested
.apic_access_page
);
7104 vmx
->nested
.apic_access_page
= 0;
7108 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7109 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7110 * success or failure flag accordingly.
7112 if (unlikely(vmx
->fail
)) {
7114 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
7116 nested_vmx_succeed(vcpu
);
7120 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7121 * 23.7 "VM-entry failures during or after loading guest state" (this also
7122 * lists the acceptable exit-reason and exit-qualification parameters).
7123 * It should only be called before L2 actually succeeded to run, and when
7124 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7126 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
7127 struct vmcs12
*vmcs12
,
7128 u32 reason
, unsigned long qualification
)
7130 load_vmcs12_host_state(vcpu
, vmcs12
);
7131 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
7132 vmcs12
->exit_qualification
= qualification
;
7133 nested_vmx_succeed(vcpu
);
7136 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7137 struct x86_instruction_info
*info
,
7138 enum x86_intercept_stage stage
)
7140 return X86EMUL_CONTINUE
;
7143 static struct kvm_x86_ops vmx_x86_ops
= {
7144 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7145 .disabled_by_bios
= vmx_disabled_by_bios
,
7146 .hardware_setup
= hardware_setup
,
7147 .hardware_unsetup
= hardware_unsetup
,
7148 .check_processor_compatibility
= vmx_check_processor_compat
,
7149 .hardware_enable
= hardware_enable
,
7150 .hardware_disable
= hardware_disable
,
7151 .cpu_has_accelerated_tpr
= report_flexpriority
,
7153 .vcpu_create
= vmx_create_vcpu
,
7154 .vcpu_free
= vmx_free_vcpu
,
7155 .vcpu_reset
= vmx_vcpu_reset
,
7157 .prepare_guest_switch
= vmx_save_host_state
,
7158 .vcpu_load
= vmx_vcpu_load
,
7159 .vcpu_put
= vmx_vcpu_put
,
7161 .set_guest_debug
= set_guest_debug
,
7162 .get_msr
= vmx_get_msr
,
7163 .set_msr
= vmx_set_msr
,
7164 .get_segment_base
= vmx_get_segment_base
,
7165 .get_segment
= vmx_get_segment
,
7166 .set_segment
= vmx_set_segment
,
7167 .get_cpl
= vmx_get_cpl
,
7168 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7169 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7170 .decache_cr3
= vmx_decache_cr3
,
7171 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7172 .set_cr0
= vmx_set_cr0
,
7173 .set_cr3
= vmx_set_cr3
,
7174 .set_cr4
= vmx_set_cr4
,
7175 .set_efer
= vmx_set_efer
,
7176 .get_idt
= vmx_get_idt
,
7177 .set_idt
= vmx_set_idt
,
7178 .get_gdt
= vmx_get_gdt
,
7179 .set_gdt
= vmx_set_gdt
,
7180 .set_dr7
= vmx_set_dr7
,
7181 .cache_reg
= vmx_cache_reg
,
7182 .get_rflags
= vmx_get_rflags
,
7183 .set_rflags
= vmx_set_rflags
,
7184 .fpu_activate
= vmx_fpu_activate
,
7185 .fpu_deactivate
= vmx_fpu_deactivate
,
7187 .tlb_flush
= vmx_flush_tlb
,
7189 .run
= vmx_vcpu_run
,
7190 .handle_exit
= vmx_handle_exit
,
7191 .skip_emulated_instruction
= skip_emulated_instruction
,
7192 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7193 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7194 .patch_hypercall
= vmx_patch_hypercall
,
7195 .set_irq
= vmx_inject_irq
,
7196 .set_nmi
= vmx_inject_nmi
,
7197 .queue_exception
= vmx_queue_exception
,
7198 .cancel_injection
= vmx_cancel_injection
,
7199 .interrupt_allowed
= vmx_interrupt_allowed
,
7200 .nmi_allowed
= vmx_nmi_allowed
,
7201 .get_nmi_mask
= vmx_get_nmi_mask
,
7202 .set_nmi_mask
= vmx_set_nmi_mask
,
7203 .enable_nmi_window
= enable_nmi_window
,
7204 .enable_irq_window
= enable_irq_window
,
7205 .update_cr8_intercept
= update_cr8_intercept
,
7207 .set_tss_addr
= vmx_set_tss_addr
,
7208 .get_tdp_level
= get_ept_level
,
7209 .get_mt_mask
= vmx_get_mt_mask
,
7211 .get_exit_info
= vmx_get_exit_info
,
7213 .get_lpage_level
= vmx_get_lpage_level
,
7215 .cpuid_update
= vmx_cpuid_update
,
7217 .rdtscp_supported
= vmx_rdtscp_supported
,
7219 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7221 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7223 .set_tsc_khz
= vmx_set_tsc_khz
,
7224 .write_tsc_offset
= vmx_write_tsc_offset
,
7225 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7226 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7227 .read_l1_tsc
= vmx_read_l1_tsc
,
7229 .set_tdp_cr3
= vmx_set_cr3
,
7231 .check_intercept
= vmx_check_intercept
,
7234 static int __init
vmx_init(void)
7238 rdmsrl_safe(MSR_EFER
, &host_efer
);
7240 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7241 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7243 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7244 if (!vmx_io_bitmap_a
)
7247 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7248 if (!vmx_io_bitmap_b
) {
7253 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7254 if (!vmx_msr_bitmap_legacy
) {
7259 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7260 if (!vmx_msr_bitmap_longmode
) {
7266 * Allow direct access to the PC debug port (it is often used for I/O
7267 * delays, but the vmexits simply slow things down).
7269 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7270 clear_bit(0x80, vmx_io_bitmap_a
);
7272 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7274 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7275 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7277 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7279 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7280 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7284 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7285 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7286 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7287 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7288 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7289 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7292 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7293 VMX_EPT_EXECUTABLE_MASK
);
7294 ept_set_mmio_spte_mask();
7302 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7304 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7306 free_page((unsigned long)vmx_io_bitmap_b
);
7308 free_page((unsigned long)vmx_io_bitmap_a
);
7312 static void __exit
vmx_exit(void)
7314 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7315 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7316 free_page((unsigned long)vmx_io_bitmap_b
);
7317 free_page((unsigned long)vmx_io_bitmap_a
);
7322 module_init(vmx_init
)
7323 module_exit(vmx_exit
)