projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: VMX: Only reload guest cr2 if different from host cr2
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int __read_mostly bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, S_IRUGO);
44
45 static int __read_mostly enable_vpid = 1;
46 module_param_named(vpid, enable_vpid, bool, 0444);
47
48 static int __read_mostly flexpriority_enabled = 1;
49 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
50
51 static int __read_mostly enable_ept = 1;
52 module_param_named(ept, enable_ept, bool, S_IRUGO);
53
54 static int __read_mostly enable_unrestricted_guest = 1;
55 module_param_named(unrestricted_guest,
56 enable_unrestricted_guest, bool, S_IRUGO);
57
58 static int __read_mostly emulate_invalid_guest_state = 0;
59 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
60
61 struct vmcs {
62 u32 revision_id;
63 u32 abort;
64 char data[0];
65 };
66
67 struct vcpu_vmx {
68 struct kvm_vcpu vcpu;
69 struct list_head local_vcpus_link;
70 unsigned long host_rsp;
71 int launched;
72 u8 fail;
73 u32 idt_vectoring_info;
74 struct kvm_msr_entry *guest_msrs;
75 struct kvm_msr_entry *host_msrs;
76 int nmsrs;
77 int save_nmsrs;
78 int msr_offset_efer;
79 #ifdef CONFIG_X86_64
80 int msr_offset_kernel_gs_base;
81 #endif
82 struct vmcs *vmcs;
83 struct {
84 int loaded;
85 u16 fs_sel, gs_sel, ldt_sel;
86 int gs_ldt_reload_needed;
87 int fs_reload_needed;
88 int guest_efer_loaded;
89 } host_state;
90 struct {
91 int vm86_active;
92 u8 save_iopl;
93 struct kvm_save_segment {
94 u16 selector;
95 unsigned long base;
96 u32 limit;
97 u32 ar;
98 } tr, es, ds, fs, gs;
99 struct {
100 bool pending;
101 u8 vector;
102 unsigned rip;
103 } irq;
104 } rmode;
105 int vpid;
106 bool emulation_required;
107 enum emulation_result invalid_state_emulation_result;
108
109 /* Support for vnmi-less CPUs */
110 int soft_vnmi_blocked;
111 ktime_t entry_time;
112 s64 vnmi_blocked_time;
113 u32 exit_reason;
114 };
115
116 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
117 {
118 return container_of(vcpu, struct vcpu_vmx, vcpu);
119 }
120
121 static int init_rmode(struct kvm *kvm);
122 static u64 construct_eptp(unsigned long root_hpa);
123
124 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
125 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
126 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
127
128 static unsigned long *vmx_io_bitmap_a;
129 static unsigned long *vmx_io_bitmap_b;
130 static unsigned long *vmx_msr_bitmap_legacy;
131 static unsigned long *vmx_msr_bitmap_longmode;
132
133 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
134 static DEFINE_SPINLOCK(vmx_vpid_lock);
135
136 static struct vmcs_config {
137 int size;
138 int order;
139 u32 revision_id;
140 u32 pin_based_exec_ctrl;
141 u32 cpu_based_exec_ctrl;
142 u32 cpu_based_2nd_exec_ctrl;
143 u32 vmexit_ctrl;
144 u32 vmentry_ctrl;
145 } vmcs_config;
146
147 static struct vmx_capability {
148 u32 ept;
149 u32 vpid;
150 } vmx_capability;
151
152 #define VMX_SEGMENT_FIELD(seg) \
153 [VCPU_SREG_##seg] = { \
154 .selector = GUEST_##seg##_SELECTOR, \
155 .base = GUEST_##seg##_BASE, \
156 .limit = GUEST_##seg##_LIMIT, \
157 .ar_bytes = GUEST_##seg##_AR_BYTES, \
158 }
159
160 static struct kvm_vmx_segment_field {
161 unsigned selector;
162 unsigned base;
163 unsigned limit;
164 unsigned ar_bytes;
165 } kvm_vmx_segment_fields[] = {
166 VMX_SEGMENT_FIELD(CS),
167 VMX_SEGMENT_FIELD(DS),
168 VMX_SEGMENT_FIELD(ES),
169 VMX_SEGMENT_FIELD(FS),
170 VMX_SEGMENT_FIELD(GS),
171 VMX_SEGMENT_FIELD(SS),
172 VMX_SEGMENT_FIELD(TR),
173 VMX_SEGMENT_FIELD(LDTR),
174 };
175
176 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
177
178 /*
179 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
180 * away by decrementing the array size.
181 */
182 static const u32 vmx_msr_index[] = {
183 #ifdef CONFIG_X86_64
184 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
185 #endif
186 MSR_EFER, MSR_K6_STAR,
187 };
188 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
189
190 static void load_msrs(struct kvm_msr_entry *e, int n)
191 {
192 int i;
193
194 for (i = 0; i < n; ++i)
195 wrmsrl(e[i].index, e[i].data);
196 }
197
198 static void save_msrs(struct kvm_msr_entry *e, int n)
199 {
200 int i;
201
202 for (i = 0; i < n; ++i)
203 rdmsrl(e[i].index, e[i].data);
204 }
205
206 static inline int is_page_fault(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_no_device(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
216 INTR_INFO_VALID_MASK)) ==
217 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
218 }
219
220 static inline int is_invalid_opcode(u32 intr_info)
221 {
222 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
223 INTR_INFO_VALID_MASK)) ==
224 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
225 }
226
227 static inline int is_external_interrupt(u32 intr_info)
228 {
229 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
230 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
231 }
232
233 static inline int is_machine_check(u32 intr_info)
234 {
235 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
236 INTR_INFO_VALID_MASK)) ==
237 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
238 }
239
240 static inline int cpu_has_vmx_msr_bitmap(void)
241 {
242 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
243 }
244
245 static inline int cpu_has_vmx_tpr_shadow(void)
246 {
247 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
248 }
249
250 static inline int vm_need_tpr_shadow(struct kvm *kvm)
251 {
252 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
253 }
254
255 static inline int cpu_has_secondary_exec_ctrls(void)
256 {
257 return vmcs_config.cpu_based_exec_ctrl &
258 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
259 }
260
261 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
262 {
263 return vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
265 }
266
267 static inline bool cpu_has_vmx_flexpriority(void)
268 {
269 return cpu_has_vmx_tpr_shadow() &&
270 cpu_has_vmx_virtualize_apic_accesses();
271 }
272
273 static inline bool cpu_has_vmx_ept_execute_only(void)
274 {
275 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
276 }
277
278 static inline bool cpu_has_vmx_eptp_uncacheable(void)
279 {
280 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
281 }
282
283 static inline bool cpu_has_vmx_eptp_writeback(void)
284 {
285 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
286 }
287
288 static inline bool cpu_has_vmx_ept_2m_page(void)
289 {
290 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
291 }
292
293 static inline int cpu_has_vmx_invept_individual_addr(void)
294 {
295 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
296 }
297
298 static inline int cpu_has_vmx_invept_context(void)
299 {
300 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
301 }
302
303 static inline int cpu_has_vmx_invept_global(void)
304 {
305 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
306 }
307
308 static inline int cpu_has_vmx_ept(void)
309 {
310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_ENABLE_EPT;
312 }
313
314 static inline int cpu_has_vmx_unrestricted_guest(void)
315 {
316 return vmcs_config.cpu_based_2nd_exec_ctrl &
317 SECONDARY_EXEC_UNRESTRICTED_GUEST;
318 }
319
320 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
321 {
322 return flexpriority_enabled &&
323 (cpu_has_vmx_virtualize_apic_accesses()) &&
324 (irqchip_in_kernel(kvm));
325 }
326
327 static inline int cpu_has_vmx_vpid(void)
328 {
329 return vmcs_config.cpu_based_2nd_exec_ctrl &
330 SECONDARY_EXEC_ENABLE_VPID;
331 }
332
333 static inline int cpu_has_virtual_nmis(void)
334 {
335 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
336 }
337
338 static inline bool report_flexpriority(void)
339 {
340 return flexpriority_enabled;
341 }
342
343 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
344 {
345 int i;
346
347 for (i = 0; i < vmx->nmsrs; ++i)
348 if (vmx->guest_msrs[i].index == msr)
349 return i;
350 return -1;
351 }
352
353 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
354 {
355 struct {
356 u64 vpid : 16;
357 u64 rsvd : 48;
358 u64 gva;
359 } operand = { vpid, 0, gva };
360
361 asm volatile (__ex(ASM_VMX_INVVPID)
362 /* CF==1 or ZF==1 --> rc = -1 */
363 "; ja 1f ; ud2 ; 1:"
364 : : "a"(&operand), "c"(ext) : "cc", "memory");
365 }
366
367 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
368 {
369 struct {
370 u64 eptp, gpa;
371 } operand = {eptp, gpa};
372
373 asm volatile (__ex(ASM_VMX_INVEPT)
374 /* CF==1 or ZF==1 --> rc = -1 */
375 "; ja 1f ; ud2 ; 1:\n"
376 : : "a" (&operand), "c" (ext) : "cc", "memory");
377 }
378
379 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
380 {
381 int i;
382
383 i = __find_msr_index(vmx, msr);
384 if (i >= 0)
385 return &vmx->guest_msrs[i];
386 return NULL;
387 }
388
389 static void vmcs_clear(struct vmcs *vmcs)
390 {
391 u64 phys_addr = __pa(vmcs);
392 u8 error;
393
394 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
395 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
396 : "cc", "memory");
397 if (error)
398 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
399 vmcs, phys_addr);
400 }
401
402 static void __vcpu_clear(void *arg)
403 {
404 struct vcpu_vmx *vmx = arg;
405 int cpu = raw_smp_processor_id();
406
407 if (vmx->vcpu.cpu == cpu)
408 vmcs_clear(vmx->vmcs);
409 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
410 per_cpu(current_vmcs, cpu) = NULL;
411 rdtscll(vmx->vcpu.arch.host_tsc);
412 list_del(&vmx->local_vcpus_link);
413 vmx->vcpu.cpu = -1;
414 vmx->launched = 0;
415 }
416
417 static void vcpu_clear(struct vcpu_vmx *vmx)
418 {
419 if (vmx->vcpu.cpu == -1)
420 return;
421 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
422 }
423
424 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
425 {
426 if (vmx->vpid == 0)
427 return;
428
429 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
430 }
431
432 static inline void ept_sync_global(void)
433 {
434 if (cpu_has_vmx_invept_global())
435 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
436 }
437
438 static inline void ept_sync_context(u64 eptp)
439 {
440 if (enable_ept) {
441 if (cpu_has_vmx_invept_context())
442 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
443 else
444 ept_sync_global();
445 }
446 }
447
448 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
449 {
450 if (enable_ept) {
451 if (cpu_has_vmx_invept_individual_addr())
452 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
453 eptp, gpa);
454 else
455 ept_sync_context(eptp);
456 }
457 }
458
459 static unsigned long vmcs_readl(unsigned long field)
460 {
461 unsigned long value;
462
463 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
464 : "=a"(value) : "d"(field) : "cc");
465 return value;
466 }
467
468 static u16 vmcs_read16(unsigned long field)
469 {
470 return vmcs_readl(field);
471 }
472
473 static u32 vmcs_read32(unsigned long field)
474 {
475 return vmcs_readl(field);
476 }
477
478 static u64 vmcs_read64(unsigned long field)
479 {
480 #ifdef CONFIG_X86_64
481 return vmcs_readl(field);
482 #else
483 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
484 #endif
485 }
486
487 static noinline void vmwrite_error(unsigned long field, unsigned long value)
488 {
489 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
490 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
491 dump_stack();
492 }
493
494 static void vmcs_writel(unsigned long field, unsigned long value)
495 {
496 u8 error;
497
498 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
499 : "=q"(error) : "a"(value), "d"(field) : "cc");
500 if (unlikely(error))
501 vmwrite_error(field, value);
502 }
503
504 static void vmcs_write16(unsigned long field, u16 value)
505 {
506 vmcs_writel(field, value);
507 }
508
509 static void vmcs_write32(unsigned long field, u32 value)
510 {
511 vmcs_writel(field, value);
512 }
513
514 static void vmcs_write64(unsigned long field, u64 value)
515 {
516 vmcs_writel(field, value);
517 #ifndef CONFIG_X86_64
518 asm volatile ("");
519 vmcs_writel(field+1, value >> 32);
520 #endif
521 }
522
523 static void vmcs_clear_bits(unsigned long field, u32 mask)
524 {
525 vmcs_writel(field, vmcs_readl(field) & ~mask);
526 }
527
528 static void vmcs_set_bits(unsigned long field, u32 mask)
529 {
530 vmcs_writel(field, vmcs_readl(field) | mask);
531 }
532
533 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
534 {
535 u32 eb;
536
537 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
538 if (!vcpu->fpu_active)
539 eb |= 1u << NM_VECTOR;
540 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
541 if (vcpu->guest_debug &
542 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
543 eb |= 1u << DB_VECTOR;
544 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
545 eb |= 1u << BP_VECTOR;
546 }
547 if (to_vmx(vcpu)->rmode.vm86_active)
548 eb = ~0;
549 if (enable_ept)
550 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
551 vmcs_write32(EXCEPTION_BITMAP, eb);
552 }
553
554 static void reload_tss(void)
555 {
556 /*
557 * VT restores TR but not its size. Useless.
558 */
559 struct descriptor_table gdt;
560 struct desc_struct *descs;
561
562 kvm_get_gdt(&gdt);
563 descs = (void *)gdt.base;
564 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
565 load_TR_desc();
566 }
567
568 static void load_transition_efer(struct vcpu_vmx *vmx)
569 {
570 int efer_offset = vmx->msr_offset_efer;
571 u64 host_efer = vmx->host_msrs[efer_offset].data;
572 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
573 u64 ignore_bits;
574
575 if (efer_offset < 0)
576 return;
577 /*
578 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
579 * outside long mode
580 */
581 ignore_bits = EFER_NX | EFER_SCE;
582 #ifdef CONFIG_X86_64
583 ignore_bits |= EFER_LMA | EFER_LME;
584 /* SCE is meaningful only in long mode on Intel */
585 if (guest_efer & EFER_LMA)
586 ignore_bits &= ~(u64)EFER_SCE;
587 #endif
588 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
589 return;
590
591 vmx->host_state.guest_efer_loaded = 1;
592 guest_efer &= ~ignore_bits;
593 guest_efer |= host_efer & ignore_bits;
594 wrmsrl(MSR_EFER, guest_efer);
595 vmx->vcpu.stat.efer_reload++;
596 }
597
598 static void reload_host_efer(struct vcpu_vmx *vmx)
599 {
600 if (vmx->host_state.guest_efer_loaded) {
601 vmx->host_state.guest_efer_loaded = 0;
602 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
603 }
604 }
605
606 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
607 {
608 struct vcpu_vmx *vmx = to_vmx(vcpu);
609
610 if (vmx->host_state.loaded)
611 return;
612
613 vmx->host_state.loaded = 1;
614 /*
615 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
616 * allow segment selectors with cpl > 0 or ti == 1.
617 */
618 vmx->host_state.ldt_sel = kvm_read_ldt();
619 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
620 vmx->host_state.fs_sel = kvm_read_fs();
621 if (!(vmx->host_state.fs_sel & 7)) {
622 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
623 vmx->host_state.fs_reload_needed = 0;
624 } else {
625 vmcs_write16(HOST_FS_SELECTOR, 0);
626 vmx->host_state.fs_reload_needed = 1;
627 }
628 vmx->host_state.gs_sel = kvm_read_gs();
629 if (!(vmx->host_state.gs_sel & 7))
630 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
631 else {
632 vmcs_write16(HOST_GS_SELECTOR, 0);
633 vmx->host_state.gs_ldt_reload_needed = 1;
634 }
635
636 #ifdef CONFIG_X86_64
637 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
638 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
639 #else
640 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
641 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
642 #endif
643
644 #ifdef CONFIG_X86_64
645 if (is_long_mode(&vmx->vcpu))
646 save_msrs(vmx->host_msrs +
647 vmx->msr_offset_kernel_gs_base, 1);
648
649 #endif
650 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
651 load_transition_efer(vmx);
652 }
653
654 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
655 {
656 unsigned long flags;
657
658 if (!vmx->host_state.loaded)
659 return;
660
661 ++vmx->vcpu.stat.host_state_reload;
662 vmx->host_state.loaded = 0;
663 if (vmx->host_state.fs_reload_needed)
664 kvm_load_fs(vmx->host_state.fs_sel);
665 if (vmx->host_state.gs_ldt_reload_needed) {
666 kvm_load_ldt(vmx->host_state.ldt_sel);
667 /*
668 * If we have to reload gs, we must take care to
669 * preserve our gs base.
670 */
671 local_irq_save(flags);
672 kvm_load_gs(vmx->host_state.gs_sel);
673 #ifdef CONFIG_X86_64
674 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
675 #endif
676 local_irq_restore(flags);
677 }
678 reload_tss();
679 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
680 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
681 reload_host_efer(vmx);
682 }
683
684 static void vmx_load_host_state(struct vcpu_vmx *vmx)
685 {
686 preempt_disable();
687 __vmx_load_host_state(vmx);
688 preempt_enable();
689 }
690
691 /*
692 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
693 * vcpu mutex is already taken.
694 */
695 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
696 {
697 struct vcpu_vmx *vmx = to_vmx(vcpu);
698 u64 phys_addr = __pa(vmx->vmcs);
699 u64 tsc_this, delta, new_offset;
700
701 if (vcpu->cpu != cpu) {
702 vcpu_clear(vmx);
703 kvm_migrate_timers(vcpu);
704 vpid_sync_vcpu_all(vmx);
705 local_irq_disable();
706 list_add(&vmx->local_vcpus_link,
707 &per_cpu(vcpus_on_cpu, cpu));
708 local_irq_enable();
709 }
710
711 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
712 u8 error;
713
714 per_cpu(current_vmcs, cpu) = vmx->vmcs;
715 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
716 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
717 : "cc");
718 if (error)
719 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
720 vmx->vmcs, phys_addr);
721 }
722
723 if (vcpu->cpu != cpu) {
724 struct descriptor_table dt;
725 unsigned long sysenter_esp;
726
727 vcpu->cpu = cpu;
728 /*
729 * Linux uses per-cpu TSS and GDT, so set these when switching
730 * processors.
731 */
732 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
733 kvm_get_gdt(&dt);
734 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
735
736 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
737 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
738
739 /*
740 * Make sure the time stamp counter is monotonous.
741 */
742 rdtscll(tsc_this);
743 if (tsc_this < vcpu->arch.host_tsc) {
744 delta = vcpu->arch.host_tsc - tsc_this;
745 new_offset = vmcs_read64(TSC_OFFSET) + delta;
746 vmcs_write64(TSC_OFFSET, new_offset);
747 }
748 }
749 }
750
751 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
752 {
753 __vmx_load_host_state(to_vmx(vcpu));
754 }
755
756 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
757 {
758 if (vcpu->fpu_active)
759 return;
760 vcpu->fpu_active = 1;
761 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
762 if (vcpu->arch.cr0 & X86_CR0_TS)
763 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
764 update_exception_bitmap(vcpu);
765 }
766
767 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
768 {
769 if (!vcpu->fpu_active)
770 return;
771 vcpu->fpu_active = 0;
772 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
773 update_exception_bitmap(vcpu);
774 }
775
776 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
777 {
778 return vmcs_readl(GUEST_RFLAGS);
779 }
780
781 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
782 {
783 if (to_vmx(vcpu)->rmode.vm86_active)
784 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
785 vmcs_writel(GUEST_RFLAGS, rflags);
786 }
787
788 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
789 {
790 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
791 int ret = 0;
792
793 if (interruptibility & GUEST_INTR_STATE_STI)
794 ret |= X86_SHADOW_INT_STI;
795 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
796 ret |= X86_SHADOW_INT_MOV_SS;
797
798 return ret & mask;
799 }
800
801 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
802 {
803 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
804 u32 interruptibility = interruptibility_old;
805
806 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
807
808 if (mask & X86_SHADOW_INT_MOV_SS)
809 interruptibility |= GUEST_INTR_STATE_MOV_SS;
810 if (mask & X86_SHADOW_INT_STI)
811 interruptibility |= GUEST_INTR_STATE_STI;
812
813 if ((interruptibility != interruptibility_old))
814 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
815 }
816
817 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
818 {
819 unsigned long rip;
820
821 rip = kvm_rip_read(vcpu);
822 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
823 kvm_rip_write(vcpu, rip);
824
825 /* skipping an emulated instruction also counts */
826 vmx_set_interrupt_shadow(vcpu, 0);
827 }
828
829 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
830 bool has_error_code, u32 error_code)
831 {
832 struct vcpu_vmx *vmx = to_vmx(vcpu);
833 u32 intr_info = nr | INTR_INFO_VALID_MASK;
834
835 if (has_error_code) {
836 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
837 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
838 }
839
840 if (vmx->rmode.vm86_active) {
841 vmx->rmode.irq.pending = true;
842 vmx->rmode.irq.vector = nr;
843 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
844 if (kvm_exception_is_soft(nr))
845 vmx->rmode.irq.rip +=
846 vmx->vcpu.arch.event_exit_inst_len;
847 intr_info |= INTR_TYPE_SOFT_INTR;
848 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
849 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
850 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
851 return;
852 }
853
854 if (kvm_exception_is_soft(nr)) {
855 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
856 vmx->vcpu.arch.event_exit_inst_len);
857 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
858 } else
859 intr_info |= INTR_TYPE_HARD_EXCEPTION;
860
861 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
862 }
863
864 /*
865 * Swap MSR entry in host/guest MSR entry array.
866 */
867 #ifdef CONFIG_X86_64
868 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
869 {
870 struct kvm_msr_entry tmp;
871
872 tmp = vmx->guest_msrs[to];
873 vmx->guest_msrs[to] = vmx->guest_msrs[from];
874 vmx->guest_msrs[from] = tmp;
875 tmp = vmx->host_msrs[to];
876 vmx->host_msrs[to] = vmx->host_msrs[from];
877 vmx->host_msrs[from] = tmp;
878 }
879 #endif
880
881 /*
882 * Set up the vmcs to automatically save and restore system
883 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
884 * mode, as fiddling with msrs is very expensive.
885 */
886 static void setup_msrs(struct vcpu_vmx *vmx)
887 {
888 int save_nmsrs;
889 unsigned long *msr_bitmap;
890
891 vmx_load_host_state(vmx);
892 save_nmsrs = 0;
893 #ifdef CONFIG_X86_64
894 if (is_long_mode(&vmx->vcpu)) {
895 int index;
896
897 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
898 if (index >= 0)
899 move_msr_up(vmx, index, save_nmsrs++);
900 index = __find_msr_index(vmx, MSR_LSTAR);
901 if (index >= 0)
902 move_msr_up(vmx, index, save_nmsrs++);
903 index = __find_msr_index(vmx, MSR_CSTAR);
904 if (index >= 0)
905 move_msr_up(vmx, index, save_nmsrs++);
906 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
907 if (index >= 0)
908 move_msr_up(vmx, index, save_nmsrs++);
909 /*
910 * MSR_K6_STAR is only needed on long mode guests, and only
911 * if efer.sce is enabled.
912 */
913 index = __find_msr_index(vmx, MSR_K6_STAR);
914 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
915 move_msr_up(vmx, index, save_nmsrs++);
916 }
917 #endif
918 vmx->save_nmsrs = save_nmsrs;
919
920 #ifdef CONFIG_X86_64
921 vmx->msr_offset_kernel_gs_base =
922 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
923 #endif
924 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
925
926 if (cpu_has_vmx_msr_bitmap()) {
927 if (is_long_mode(&vmx->vcpu))
928 msr_bitmap = vmx_msr_bitmap_longmode;
929 else
930 msr_bitmap = vmx_msr_bitmap_legacy;
931
932 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
933 }
934 }
935
936 /*
937 * reads and returns guest's timestamp counter "register"
938 * guest_tsc = host_tsc + tsc_offset -- 21.3
939 */
940 static u64 guest_read_tsc(void)
941 {
942 u64 host_tsc, tsc_offset;
943
944 rdtscll(host_tsc);
945 tsc_offset = vmcs_read64(TSC_OFFSET);
946 return host_tsc + tsc_offset;
947 }
948
949 /*
950 * writes 'guest_tsc' into guest's timestamp counter "register"
951 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
952 */
953 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
954 {
955 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
956 }
957
958 /*
959 * Reads an msr value (of 'msr_index') into 'pdata'.
960 * Returns 0 on success, non-0 otherwise.
961 * Assumes vcpu_load() was already called.
962 */
963 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
964 {
965 u64 data;
966 struct kvm_msr_entry *msr;
967
968 if (!pdata) {
969 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
970 return -EINVAL;
971 }
972
973 switch (msr_index) {
974 #ifdef CONFIG_X86_64
975 case MSR_FS_BASE:
976 data = vmcs_readl(GUEST_FS_BASE);
977 break;
978 case MSR_GS_BASE:
979 data = vmcs_readl(GUEST_GS_BASE);
980 break;
981 case MSR_EFER:
982 return kvm_get_msr_common(vcpu, msr_index, pdata);
983 #endif
984 case MSR_IA32_TSC:
985 data = guest_read_tsc();
986 break;
987 case MSR_IA32_SYSENTER_CS:
988 data = vmcs_read32(GUEST_SYSENTER_CS);
989 break;
990 case MSR_IA32_SYSENTER_EIP:
991 data = vmcs_readl(GUEST_SYSENTER_EIP);
992 break;
993 case MSR_IA32_SYSENTER_ESP:
994 data = vmcs_readl(GUEST_SYSENTER_ESP);
995 break;
996 default:
997 vmx_load_host_state(to_vmx(vcpu));
998 msr = find_msr_entry(to_vmx(vcpu), msr_index);
999 if (msr) {
1000 data = msr->data;
1001 break;
1002 }
1003 return kvm_get_msr_common(vcpu, msr_index, pdata);
1004 }
1005
1006 *pdata = data;
1007 return 0;
1008 }
1009
1010 /*
1011 * Writes msr value into into the appropriate "register".
1012 * Returns 0 on success, non-0 otherwise.
1013 * Assumes vcpu_load() was already called.
1014 */
1015 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1016 {
1017 struct vcpu_vmx *vmx = to_vmx(vcpu);
1018 struct kvm_msr_entry *msr;
1019 u64 host_tsc;
1020 int ret = 0;
1021
1022 switch (msr_index) {
1023 case MSR_EFER:
1024 vmx_load_host_state(vmx);
1025 ret = kvm_set_msr_common(vcpu, msr_index, data);
1026 break;
1027 #ifdef CONFIG_X86_64
1028 case MSR_FS_BASE:
1029 vmcs_writel(GUEST_FS_BASE, data);
1030 break;
1031 case MSR_GS_BASE:
1032 vmcs_writel(GUEST_GS_BASE, data);
1033 break;
1034 #endif
1035 case MSR_IA32_SYSENTER_CS:
1036 vmcs_write32(GUEST_SYSENTER_CS, data);
1037 break;
1038 case MSR_IA32_SYSENTER_EIP:
1039 vmcs_writel(GUEST_SYSENTER_EIP, data);
1040 break;
1041 case MSR_IA32_SYSENTER_ESP:
1042 vmcs_writel(GUEST_SYSENTER_ESP, data);
1043 break;
1044 case MSR_IA32_TSC:
1045 rdtscll(host_tsc);
1046 guest_write_tsc(data, host_tsc);
1047 break;
1048 case MSR_IA32_CR_PAT:
1049 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1050 vmcs_write64(GUEST_IA32_PAT, data);
1051 vcpu->arch.pat = data;
1052 break;
1053 }
1054 /* Otherwise falls through to kvm_set_msr_common */
1055 default:
1056 vmx_load_host_state(vmx);
1057 msr = find_msr_entry(vmx, msr_index);
1058 if (msr) {
1059 msr->data = data;
1060 break;
1061 }
1062 ret = kvm_set_msr_common(vcpu, msr_index, data);
1063 }
1064
1065 return ret;
1066 }
1067
1068 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1069 {
1070 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1071 switch (reg) {
1072 case VCPU_REGS_RSP:
1073 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1074 break;
1075 case VCPU_REGS_RIP:
1076 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1077 break;
1078 case VCPU_EXREG_PDPTR:
1079 if (enable_ept)
1080 ept_save_pdptrs(vcpu);
1081 break;
1082 default:
1083 break;
1084 }
1085 }
1086
1087 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1088 {
1089 int old_debug = vcpu->guest_debug;
1090 unsigned long flags;
1091
1092 vcpu->guest_debug = dbg->control;
1093 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1094 vcpu->guest_debug = 0;
1095
1096 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1097 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1098 else
1099 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1100
1101 flags = vmcs_readl(GUEST_RFLAGS);
1102 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1103 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1104 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1105 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1106 vmcs_writel(GUEST_RFLAGS, flags);
1107
1108 update_exception_bitmap(vcpu);
1109
1110 return 0;
1111 }
1112
1113 static __init int cpu_has_kvm_support(void)
1114 {
1115 return cpu_has_vmx();
1116 }
1117
1118 static __init int vmx_disabled_by_bios(void)
1119 {
1120 u64 msr;
1121
1122 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1123 return (msr & (FEATURE_CONTROL_LOCKED |
1124 FEATURE_CONTROL_VMXON_ENABLED))
1125 == FEATURE_CONTROL_LOCKED;
1126 /* locked but not enabled */
1127 }
1128
1129 static void hardware_enable(void *garbage)
1130 {
1131 int cpu = raw_smp_processor_id();
1132 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1133 u64 old;
1134
1135 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1136 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1137 if ((old & (FEATURE_CONTROL_LOCKED |
1138 FEATURE_CONTROL_VMXON_ENABLED))
1139 != (FEATURE_CONTROL_LOCKED |
1140 FEATURE_CONTROL_VMXON_ENABLED))
1141 /* enable and lock */
1142 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1143 FEATURE_CONTROL_LOCKED |
1144 FEATURE_CONTROL_VMXON_ENABLED);
1145 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1146 asm volatile (ASM_VMX_VMXON_RAX
1147 : : "a"(&phys_addr), "m"(phys_addr)
1148 : "memory", "cc");
1149 }
1150
1151 static void vmclear_local_vcpus(void)
1152 {
1153 int cpu = raw_smp_processor_id();
1154 struct vcpu_vmx *vmx, *n;
1155
1156 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1157 local_vcpus_link)
1158 __vcpu_clear(vmx);
1159 }
1160
1161
1162 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1163 * tricks.
1164 */
1165 static void kvm_cpu_vmxoff(void)
1166 {
1167 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1168 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1169 }
1170
1171 static void hardware_disable(void *garbage)
1172 {
1173 vmclear_local_vcpus();
1174 kvm_cpu_vmxoff();
1175 }
1176
1177 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1178 u32 msr, u32 *result)
1179 {
1180 u32 vmx_msr_low, vmx_msr_high;
1181 u32 ctl = ctl_min | ctl_opt;
1182
1183 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1184
1185 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1186 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1187
1188 /* Ensure minimum (required) set of control bits are supported. */
1189 if (ctl_min & ~ctl)
1190 return -EIO;
1191
1192 *result = ctl;
1193 return 0;
1194 }
1195
1196 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1197 {
1198 u32 vmx_msr_low, vmx_msr_high;
1199 u32 min, opt, min2, opt2;
1200 u32 _pin_based_exec_control = 0;
1201 u32 _cpu_based_exec_control = 0;
1202 u32 _cpu_based_2nd_exec_control = 0;
1203 u32 _vmexit_control = 0;
1204 u32 _vmentry_control = 0;
1205
1206 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1207 opt = PIN_BASED_VIRTUAL_NMIS;
1208 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1209 &_pin_based_exec_control) < 0)
1210 return -EIO;
1211
1212 min = CPU_BASED_HLT_EXITING |
1213 #ifdef CONFIG_X86_64
1214 CPU_BASED_CR8_LOAD_EXITING |
1215 CPU_BASED_CR8_STORE_EXITING |
1216 #endif
1217 CPU_BASED_CR3_LOAD_EXITING |
1218 CPU_BASED_CR3_STORE_EXITING |
1219 CPU_BASED_USE_IO_BITMAPS |
1220 CPU_BASED_MOV_DR_EXITING |
1221 CPU_BASED_USE_TSC_OFFSETING |
1222 CPU_BASED_INVLPG_EXITING;
1223 opt = CPU_BASED_TPR_SHADOW |
1224 CPU_BASED_USE_MSR_BITMAPS |
1225 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1226 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1227 &_cpu_based_exec_control) < 0)
1228 return -EIO;
1229 #ifdef CONFIG_X86_64
1230 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1231 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1232 ~CPU_BASED_CR8_STORE_EXITING;
1233 #endif
1234 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1235 min2 = 0;
1236 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1237 SECONDARY_EXEC_WBINVD_EXITING |
1238 SECONDARY_EXEC_ENABLE_VPID |
1239 SECONDARY_EXEC_ENABLE_EPT |
1240 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1241 if (adjust_vmx_controls(min2, opt2,
1242 MSR_IA32_VMX_PROCBASED_CTLS2,
1243 &_cpu_based_2nd_exec_control) < 0)
1244 return -EIO;
1245 }
1246 #ifndef CONFIG_X86_64
1247 if (!(_cpu_based_2nd_exec_control &
1248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1249 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1250 #endif
1251 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1252 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1253 enabled */
1254 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1255 CPU_BASED_CR3_STORE_EXITING |
1256 CPU_BASED_INVLPG_EXITING);
1257 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1258 &_cpu_based_exec_control) < 0)
1259 return -EIO;
1260 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1261 vmx_capability.ept, vmx_capability.vpid);
1262 }
1263
1264 min = 0;
1265 #ifdef CONFIG_X86_64
1266 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1267 #endif
1268 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1269 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1270 &_vmexit_control) < 0)
1271 return -EIO;
1272
1273 min = 0;
1274 opt = VM_ENTRY_LOAD_IA32_PAT;
1275 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1276 &_vmentry_control) < 0)
1277 return -EIO;
1278
1279 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1280
1281 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1282 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1283 return -EIO;
1284
1285 #ifdef CONFIG_X86_64
1286 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1287 if (vmx_msr_high & (1u<<16))
1288 return -EIO;
1289 #endif
1290
1291 /* Require Write-Back (WB) memory type for VMCS accesses. */
1292 if (((vmx_msr_high >> 18) & 15) != 6)
1293 return -EIO;
1294
1295 vmcs_conf->size = vmx_msr_high & 0x1fff;
1296 vmcs_conf->order = get_order(vmcs_config.size);
1297 vmcs_conf->revision_id = vmx_msr_low;
1298
1299 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1300 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1301 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1302 vmcs_conf->vmexit_ctrl = _vmexit_control;
1303 vmcs_conf->vmentry_ctrl = _vmentry_control;
1304
1305 return 0;
1306 }
1307
1308 static struct vmcs *alloc_vmcs_cpu(int cpu)
1309 {
1310 int node = cpu_to_node(cpu);
1311 struct page *pages;
1312 struct vmcs *vmcs;
1313
1314 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1315 if (!pages)
1316 return NULL;
1317 vmcs = page_address(pages);
1318 memset(vmcs, 0, vmcs_config.size);
1319 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1320 return vmcs;
1321 }
1322
1323 static struct vmcs *alloc_vmcs(void)
1324 {
1325 return alloc_vmcs_cpu(raw_smp_processor_id());
1326 }
1327
1328 static void free_vmcs(struct vmcs *vmcs)
1329 {
1330 free_pages((unsigned long)vmcs, vmcs_config.order);
1331 }
1332
1333 static void free_kvm_area(void)
1334 {
1335 int cpu;
1336
1337 for_each_online_cpu(cpu)
1338 free_vmcs(per_cpu(vmxarea, cpu));
1339 }
1340
1341 static __init int alloc_kvm_area(void)
1342 {
1343 int cpu;
1344
1345 for_each_online_cpu(cpu) {
1346 struct vmcs *vmcs;
1347
1348 vmcs = alloc_vmcs_cpu(cpu);
1349 if (!vmcs) {
1350 free_kvm_area();
1351 return -ENOMEM;
1352 }
1353
1354 per_cpu(vmxarea, cpu) = vmcs;
1355 }
1356 return 0;
1357 }
1358
1359 static __init int hardware_setup(void)
1360 {
1361 if (setup_vmcs_config(&vmcs_config) < 0)
1362 return -EIO;
1363
1364 if (boot_cpu_has(X86_FEATURE_NX))
1365 kvm_enable_efer_bits(EFER_NX);
1366
1367 if (!cpu_has_vmx_vpid())
1368 enable_vpid = 0;
1369
1370 if (!cpu_has_vmx_ept()) {
1371 enable_ept = 0;
1372 enable_unrestricted_guest = 0;
1373 }
1374
1375 if (!cpu_has_vmx_unrestricted_guest())
1376 enable_unrestricted_guest = 0;
1377
1378 if (!cpu_has_vmx_flexpriority())
1379 flexpriority_enabled = 0;
1380
1381 if (!cpu_has_vmx_tpr_shadow())
1382 kvm_x86_ops->update_cr8_intercept = NULL;
1383
1384 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1385 kvm_disable_largepages();
1386
1387 return alloc_kvm_area();
1388 }
1389
1390 static __exit void hardware_unsetup(void)
1391 {
1392 free_kvm_area();
1393 }
1394
1395 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1396 {
1397 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1398
1399 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1400 vmcs_write16(sf->selector, save->selector);
1401 vmcs_writel(sf->base, save->base);
1402 vmcs_write32(sf->limit, save->limit);
1403 vmcs_write32(sf->ar_bytes, save->ar);
1404 } else {
1405 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1406 << AR_DPL_SHIFT;
1407 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1408 }
1409 }
1410
1411 static void enter_pmode(struct kvm_vcpu *vcpu)
1412 {
1413 unsigned long flags;
1414 struct vcpu_vmx *vmx = to_vmx(vcpu);
1415
1416 vmx->emulation_required = 1;
1417 vmx->rmode.vm86_active = 0;
1418
1419 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1420 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1421 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1422
1423 flags = vmcs_readl(GUEST_RFLAGS);
1424 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1425 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1426 vmcs_writel(GUEST_RFLAGS, flags);
1427
1428 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1429 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1430
1431 update_exception_bitmap(vcpu);
1432
1433 if (emulate_invalid_guest_state)
1434 return;
1435
1436 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1437 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1438 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1439 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1440
1441 vmcs_write16(GUEST_SS_SELECTOR, 0);
1442 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1443
1444 vmcs_write16(GUEST_CS_SELECTOR,
1445 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1446 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1447 }
1448
1449 static gva_t rmode_tss_base(struct kvm *kvm)
1450 {
1451 if (!kvm->arch.tss_addr) {
1452 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1453 kvm->memslots[0].npages - 3;
1454 return base_gfn << PAGE_SHIFT;
1455 }
1456 return kvm->arch.tss_addr;
1457 }
1458
1459 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1460 {
1461 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1462
1463 save->selector = vmcs_read16(sf->selector);
1464 save->base = vmcs_readl(sf->base);
1465 save->limit = vmcs_read32(sf->limit);
1466 save->ar = vmcs_read32(sf->ar_bytes);
1467 vmcs_write16(sf->selector, save->base >> 4);
1468 vmcs_write32(sf->base, save->base & 0xfffff);
1469 vmcs_write32(sf->limit, 0xffff);
1470 vmcs_write32(sf->ar_bytes, 0xf3);
1471 }
1472
1473 static void enter_rmode(struct kvm_vcpu *vcpu)
1474 {
1475 unsigned long flags;
1476 struct vcpu_vmx *vmx = to_vmx(vcpu);
1477
1478 if (enable_unrestricted_guest)
1479 return;
1480
1481 vmx->emulation_required = 1;
1482 vmx->rmode.vm86_active = 1;
1483
1484 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1485 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1486
1487 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1488 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1489
1490 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1491 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1492
1493 flags = vmcs_readl(GUEST_RFLAGS);
1494 vmx->rmode.save_iopl
1495 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1496
1497 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1498
1499 vmcs_writel(GUEST_RFLAGS, flags);
1500 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1501 update_exception_bitmap(vcpu);
1502
1503 if (emulate_invalid_guest_state)
1504 goto continue_rmode;
1505
1506 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1507 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1508 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1509
1510 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1511 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1512 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1513 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1514 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1515
1516 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1517 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1518 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1519 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1520
1521 continue_rmode:
1522 kvm_mmu_reset_context(vcpu);
1523 init_rmode(vcpu->kvm);
1524 }
1525
1526 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1527 {
1528 struct vcpu_vmx *vmx = to_vmx(vcpu);
1529 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1530
1531 vcpu->arch.shadow_efer = efer;
1532 if (!msr)
1533 return;
1534 if (efer & EFER_LMA) {
1535 vmcs_write32(VM_ENTRY_CONTROLS,
1536 vmcs_read32(VM_ENTRY_CONTROLS) |
1537 VM_ENTRY_IA32E_MODE);
1538 msr->data = efer;
1539 } else {
1540 vmcs_write32(VM_ENTRY_CONTROLS,
1541 vmcs_read32(VM_ENTRY_CONTROLS) &
1542 ~VM_ENTRY_IA32E_MODE);
1543
1544 msr->data = efer & ~EFER_LME;
1545 }
1546 setup_msrs(vmx);
1547 }
1548
1549 #ifdef CONFIG_X86_64
1550
1551 static void enter_lmode(struct kvm_vcpu *vcpu)
1552 {
1553 u32 guest_tr_ar;
1554
1555 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1556 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1557 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1558 __func__);
1559 vmcs_write32(GUEST_TR_AR_BYTES,
1560 (guest_tr_ar & ~AR_TYPE_MASK)
1561 | AR_TYPE_BUSY_64_TSS);
1562 }
1563 vcpu->arch.shadow_efer |= EFER_LMA;
1564 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1565 }
1566
1567 static void exit_lmode(struct kvm_vcpu *vcpu)
1568 {
1569 vcpu->arch.shadow_efer &= ~EFER_LMA;
1570
1571 vmcs_write32(VM_ENTRY_CONTROLS,
1572 vmcs_read32(VM_ENTRY_CONTROLS)
1573 & ~VM_ENTRY_IA32E_MODE);
1574 }
1575
1576 #endif
1577
1578 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1579 {
1580 vpid_sync_vcpu_all(to_vmx(vcpu));
1581 if (enable_ept)
1582 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1583 }
1584
1585 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1586 {
1587 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1588 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1589 }
1590
1591 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1592 {
1593 if (!test_bit(VCPU_EXREG_PDPTR,
1594 (unsigned long *)&vcpu->arch.regs_dirty))
1595 return;
1596
1597 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1598 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1599 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1600 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1601 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1602 }
1603 }
1604
1605 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1606 {
1607 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1608 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1609 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1610 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1611 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1612 }
1613
1614 __set_bit(VCPU_EXREG_PDPTR,
1615 (unsigned long *)&vcpu->arch.regs_avail);
1616 __set_bit(VCPU_EXREG_PDPTR,
1617 (unsigned long *)&vcpu->arch.regs_dirty);
1618 }
1619
1620 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1621
1622 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1623 unsigned long cr0,
1624 struct kvm_vcpu *vcpu)
1625 {
1626 if (!(cr0 & X86_CR0_PG)) {
1627 /* From paging/starting to nonpaging */
1628 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1629 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1630 (CPU_BASED_CR3_LOAD_EXITING |
1631 CPU_BASED_CR3_STORE_EXITING));
1632 vcpu->arch.cr0 = cr0;
1633 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1634 *hw_cr0 &= ~X86_CR0_WP;
1635 } else if (!is_paging(vcpu)) {
1636 /* From nonpaging to paging */
1637 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1638 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1639 ~(CPU_BASED_CR3_LOAD_EXITING |
1640 CPU_BASED_CR3_STORE_EXITING));
1641 vcpu->arch.cr0 = cr0;
1642 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1643 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1644 *hw_cr0 &= ~X86_CR0_WP;
1645 }
1646 }
1647
1648 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1649 struct kvm_vcpu *vcpu)
1650 {
1651 if (!is_paging(vcpu)) {
1652 *hw_cr4 &= ~X86_CR4_PAE;
1653 *hw_cr4 |= X86_CR4_PSE;
1654 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1655 *hw_cr4 &= ~X86_CR4_PAE;
1656 }
1657
1658 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1659 {
1660 struct vcpu_vmx *vmx = to_vmx(vcpu);
1661 unsigned long hw_cr0;
1662
1663 if (enable_unrestricted_guest)
1664 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1665 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1666 else
1667 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1668
1669 vmx_fpu_deactivate(vcpu);
1670
1671 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1672 enter_pmode(vcpu);
1673
1674 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1675 enter_rmode(vcpu);
1676
1677 #ifdef CONFIG_X86_64
1678 if (vcpu->arch.shadow_efer & EFER_LME) {
1679 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1680 enter_lmode(vcpu);
1681 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1682 exit_lmode(vcpu);
1683 }
1684 #endif
1685
1686 if (enable_ept)
1687 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1688
1689 vmcs_writel(CR0_READ_SHADOW, cr0);
1690 vmcs_writel(GUEST_CR0, hw_cr0);
1691 vcpu->arch.cr0 = cr0;
1692
1693 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1694 vmx_fpu_activate(vcpu);
1695 }
1696
1697 static u64 construct_eptp(unsigned long root_hpa)
1698 {
1699 u64 eptp;
1700
1701 /* TODO write the value reading from MSR */
1702 eptp = VMX_EPT_DEFAULT_MT |
1703 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1704 eptp |= (root_hpa & PAGE_MASK);
1705
1706 return eptp;
1707 }
1708
1709 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1710 {
1711 unsigned long guest_cr3;
1712 u64 eptp;
1713
1714 guest_cr3 = cr3;
1715 if (enable_ept) {
1716 eptp = construct_eptp(cr3);
1717 vmcs_write64(EPT_POINTER, eptp);
1718 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1719 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1720 }
1721
1722 vmx_flush_tlb(vcpu);
1723 vmcs_writel(GUEST_CR3, guest_cr3);
1724 if (vcpu->arch.cr0 & X86_CR0_PE)
1725 vmx_fpu_deactivate(vcpu);
1726 }
1727
1728 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1729 {
1730 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1731 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1732
1733 vcpu->arch.cr4 = cr4;
1734 if (enable_ept)
1735 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1736
1737 vmcs_writel(CR4_READ_SHADOW, cr4);
1738 vmcs_writel(GUEST_CR4, hw_cr4);
1739 }
1740
1741 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1742 {
1743 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1744
1745 return vmcs_readl(sf->base);
1746 }
1747
1748 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1749 struct kvm_segment *var, int seg)
1750 {
1751 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1752 u32 ar;
1753
1754 var->base = vmcs_readl(sf->base);
1755 var->limit = vmcs_read32(sf->limit);
1756 var->selector = vmcs_read16(sf->selector);
1757 ar = vmcs_read32(sf->ar_bytes);
1758 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1759 ar = 0;
1760 var->type = ar & 15;
1761 var->s = (ar >> 4) & 1;
1762 var->dpl = (ar >> 5) & 3;
1763 var->present = (ar >> 7) & 1;
1764 var->avl = (ar >> 12) & 1;
1765 var->l = (ar >> 13) & 1;
1766 var->db = (ar >> 14) & 1;
1767 var->g = (ar >> 15) & 1;
1768 var->unusable = (ar >> 16) & 1;
1769 }
1770
1771 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1772 {
1773 struct kvm_segment kvm_seg;
1774
1775 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1776 return 0;
1777
1778 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1779 return 3;
1780
1781 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1782 return kvm_seg.selector & 3;
1783 }
1784
1785 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1786 {
1787 u32 ar;
1788
1789 if (var->unusable)
1790 ar = 1 << 16;
1791 else {
1792 ar = var->type & 15;
1793 ar |= (var->s & 1) << 4;
1794 ar |= (var->dpl & 3) << 5;
1795 ar |= (var->present & 1) << 7;
1796 ar |= (var->avl & 1) << 12;
1797 ar |= (var->l & 1) << 13;
1798 ar |= (var->db & 1) << 14;
1799 ar |= (var->g & 1) << 15;
1800 }
1801 if (ar == 0) /* a 0 value means unusable */
1802 ar = AR_UNUSABLE_MASK;
1803
1804 return ar;
1805 }
1806
1807 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1808 struct kvm_segment *var, int seg)
1809 {
1810 struct vcpu_vmx *vmx = to_vmx(vcpu);
1811 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1812 u32 ar;
1813
1814 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1815 vmx->rmode.tr.selector = var->selector;
1816 vmx->rmode.tr.base = var->base;
1817 vmx->rmode.tr.limit = var->limit;
1818 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1819 return;
1820 }
1821 vmcs_writel(sf->base, var->base);
1822 vmcs_write32(sf->limit, var->limit);
1823 vmcs_write16(sf->selector, var->selector);
1824 if (vmx->rmode.vm86_active && var->s) {
1825 /*
1826 * Hack real-mode segments into vm86 compatibility.
1827 */
1828 if (var->base == 0xffff0000 && var->selector == 0xf000)
1829 vmcs_writel(sf->base, 0xf0000);
1830 ar = 0xf3;
1831 } else
1832 ar = vmx_segment_access_rights(var);
1833
1834 /*
1835 * Fix the "Accessed" bit in AR field of segment registers for older
1836 * qemu binaries.
1837 * IA32 arch specifies that at the time of processor reset the
1838 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1839 * is setting it to 0 in the usedland code. This causes invalid guest
1840 * state vmexit when "unrestricted guest" mode is turned on.
1841 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1842 * tree. Newer qemu binaries with that qemu fix would not need this
1843 * kvm hack.
1844 */
1845 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1846 ar |= 0x1; /* Accessed */
1847
1848 vmcs_write32(sf->ar_bytes, ar);
1849 }
1850
1851 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1852 {
1853 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1854
1855 *db = (ar >> 14) & 1;
1856 *l = (ar >> 13) & 1;
1857 }
1858
1859 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1860 {
1861 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1862 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1863 }
1864
1865 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1866 {
1867 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1868 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1869 }
1870
1871 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1872 {
1873 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1874 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1875 }
1876
1877 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1878 {
1879 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1880 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1881 }
1882
1883 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1884 {
1885 struct kvm_segment var;
1886 u32 ar;
1887
1888 vmx_get_segment(vcpu, &var, seg);
1889 ar = vmx_segment_access_rights(&var);
1890
1891 if (var.base != (var.selector << 4))
1892 return false;
1893 if (var.limit != 0xffff)
1894 return false;
1895 if (ar != 0xf3)
1896 return false;
1897
1898 return true;
1899 }
1900
1901 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1902 {
1903 struct kvm_segment cs;
1904 unsigned int cs_rpl;
1905
1906 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1907 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1908
1909 if (cs.unusable)
1910 return false;
1911 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1912 return false;
1913 if (!cs.s)
1914 return false;
1915 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1916 if (cs.dpl > cs_rpl)
1917 return false;
1918 } else {
1919 if (cs.dpl != cs_rpl)
1920 return false;
1921 }
1922 if (!cs.present)
1923 return false;
1924
1925 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1926 return true;
1927 }
1928
1929 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1930 {
1931 struct kvm_segment ss;
1932 unsigned int ss_rpl;
1933
1934 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1935 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1936
1937 if (ss.unusable)
1938 return true;
1939 if (ss.type != 3 && ss.type != 7)
1940 return false;
1941 if (!ss.s)
1942 return false;
1943 if (ss.dpl != ss_rpl) /* DPL != RPL */
1944 return false;
1945 if (!ss.present)
1946 return false;
1947
1948 return true;
1949 }
1950
1951 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1952 {
1953 struct kvm_segment var;
1954 unsigned int rpl;
1955
1956 vmx_get_segment(vcpu, &var, seg);
1957 rpl = var.selector & SELECTOR_RPL_MASK;
1958
1959 if (var.unusable)
1960 return true;
1961 if (!var.s)
1962 return false;
1963 if (!var.present)
1964 return false;
1965 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1966 if (var.dpl < rpl) /* DPL < RPL */
1967 return false;
1968 }
1969
1970 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1971 * rights flags
1972 */
1973 return true;
1974 }
1975
1976 static bool tr_valid(struct kvm_vcpu *vcpu)
1977 {
1978 struct kvm_segment tr;
1979
1980 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1981
1982 if (tr.unusable)
1983 return false;
1984 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1985 return false;
1986 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1987 return false;
1988 if (!tr.present)
1989 return false;
1990
1991 return true;
1992 }
1993
1994 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1995 {
1996 struct kvm_segment ldtr;
1997
1998 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1999
2000 if (ldtr.unusable)
2001 return true;
2002 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2003 return false;
2004 if (ldtr.type != 2)
2005 return false;
2006 if (!ldtr.present)
2007 return false;
2008
2009 return true;
2010 }
2011
2012 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2013 {
2014 struct kvm_segment cs, ss;
2015
2016 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2017 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2018
2019 return ((cs.selector & SELECTOR_RPL_MASK) ==
2020 (ss.selector & SELECTOR_RPL_MASK));
2021 }
2022
2023 /*
2024 * Check if guest state is valid. Returns true if valid, false if
2025 * not.
2026 * We assume that registers are always usable
2027 */
2028 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2029 {
2030 /* real mode guest state checks */
2031 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2032 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2033 return false;
2034 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2035 return false;
2036 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2037 return false;
2038 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2039 return false;
2040 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2041 return false;
2042 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2043 return false;
2044 } else {
2045 /* protected mode guest state checks */
2046 if (!cs_ss_rpl_check(vcpu))
2047 return false;
2048 if (!code_segment_valid(vcpu))
2049 return false;
2050 if (!stack_segment_valid(vcpu))
2051 return false;
2052 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2053 return false;
2054 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2055 return false;
2056 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2057 return false;
2058 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2059 return false;
2060 if (!tr_valid(vcpu))
2061 return false;
2062 if (!ldtr_valid(vcpu))
2063 return false;
2064 }
2065 /* TODO:
2066 * - Add checks on RIP
2067 * - Add checks on RFLAGS
2068 */
2069
2070 return true;
2071 }
2072
2073 static int init_rmode_tss(struct kvm *kvm)
2074 {
2075 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2076 u16 data = 0;
2077 int ret = 0;
2078 int r;
2079
2080 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2081 if (r < 0)
2082 goto out;
2083 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2084 r = kvm_write_guest_page(kvm, fn++, &data,
2085 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2086 if (r < 0)
2087 goto out;
2088 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2089 if (r < 0)
2090 goto out;
2091 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2092 if (r < 0)
2093 goto out;
2094 data = ~0;
2095 r = kvm_write_guest_page(kvm, fn, &data,
2096 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2097 sizeof(u8));
2098 if (r < 0)
2099 goto out;
2100
2101 ret = 1;
2102 out:
2103 return ret;
2104 }
2105
2106 static int init_rmode_identity_map(struct kvm *kvm)
2107 {
2108 int i, r, ret;
2109 pfn_t identity_map_pfn;
2110 u32 tmp;
2111
2112 if (!enable_ept)
2113 return 1;
2114 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2115 printk(KERN_ERR "EPT: identity-mapping pagetable "
2116 "haven't been allocated!\n");
2117 return 0;
2118 }
2119 if (likely(kvm->arch.ept_identity_pagetable_done))
2120 return 1;
2121 ret = 0;
2122 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2123 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2124 if (r < 0)
2125 goto out;
2126 /* Set up identity-mapping pagetable for EPT in real mode */
2127 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2128 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2129 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2130 r = kvm_write_guest_page(kvm, identity_map_pfn,
2131 &tmp, i * sizeof(tmp), sizeof(tmp));
2132 if (r < 0)
2133 goto out;
2134 }
2135 kvm->arch.ept_identity_pagetable_done = true;
2136 ret = 1;
2137 out:
2138 return ret;
2139 }
2140
2141 static void seg_setup(int seg)
2142 {
2143 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2144 unsigned int ar;
2145
2146 vmcs_write16(sf->selector, 0);
2147 vmcs_writel(sf->base, 0);
2148 vmcs_write32(sf->limit, 0xffff);
2149 if (enable_unrestricted_guest) {
2150 ar = 0x93;
2151 if (seg == VCPU_SREG_CS)
2152 ar |= 0x08; /* code segment */
2153 } else
2154 ar = 0xf3;
2155
2156 vmcs_write32(sf->ar_bytes, ar);
2157 }
2158
2159 static int alloc_apic_access_page(struct kvm *kvm)
2160 {
2161 struct kvm_userspace_memory_region kvm_userspace_mem;
2162 int r = 0;
2163
2164 down_write(&kvm->slots_lock);
2165 if (kvm->arch.apic_access_page)
2166 goto out;
2167 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2168 kvm_userspace_mem.flags = 0;
2169 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2170 kvm_userspace_mem.memory_size = PAGE_SIZE;
2171 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2172 if (r)
2173 goto out;
2174
2175 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2176 out:
2177 up_write(&kvm->slots_lock);
2178 return r;
2179 }
2180
2181 static int alloc_identity_pagetable(struct kvm *kvm)
2182 {
2183 struct kvm_userspace_memory_region kvm_userspace_mem;
2184 int r = 0;
2185
2186 down_write(&kvm->slots_lock);
2187 if (kvm->arch.ept_identity_pagetable)
2188 goto out;
2189 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2190 kvm_userspace_mem.flags = 0;
2191 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2192 kvm_userspace_mem.memory_size = PAGE_SIZE;
2193 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2194 if (r)
2195 goto out;
2196
2197 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2198 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2199 out:
2200 up_write(&kvm->slots_lock);
2201 return r;
2202 }
2203
2204 static void allocate_vpid(struct vcpu_vmx *vmx)
2205 {
2206 int vpid;
2207
2208 vmx->vpid = 0;
2209 if (!enable_vpid)
2210 return;
2211 spin_lock(&vmx_vpid_lock);
2212 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2213 if (vpid < VMX_NR_VPIDS) {
2214 vmx->vpid = vpid;
2215 __set_bit(vpid, vmx_vpid_bitmap);
2216 }
2217 spin_unlock(&vmx_vpid_lock);
2218 }
2219
2220 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2221 {
2222 int f = sizeof(unsigned long);
2223
2224 if (!cpu_has_vmx_msr_bitmap())
2225 return;
2226
2227 /*
2228 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2229 * have the write-low and read-high bitmap offsets the wrong way round.
2230 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2231 */
2232 if (msr <= 0x1fff) {
2233 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2234 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2235 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2236 msr &= 0x1fff;
2237 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2238 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2239 }
2240 }
2241
2242 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2243 {
2244 if (!longmode_only)
2245 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2246 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2247 }
2248
2249 /*
2250 * Sets up the vmcs for emulated real mode.
2251 */
2252 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2253 {
2254 u32 host_sysenter_cs, msr_low, msr_high;
2255 u32 junk;
2256 u64 host_pat, tsc_this, tsc_base;
2257 unsigned long a;
2258 struct descriptor_table dt;
2259 int i;
2260 unsigned long kvm_vmx_return;
2261 u32 exec_control;
2262
2263 /* I/O */
2264 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2265 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2266
2267 if (cpu_has_vmx_msr_bitmap())
2268 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2269
2270 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2271
2272 /* Control */
2273 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2274 vmcs_config.pin_based_exec_ctrl);
2275
2276 exec_control = vmcs_config.cpu_based_exec_ctrl;
2277 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2278 exec_control &= ~CPU_BASED_TPR_SHADOW;
2279 #ifdef CONFIG_X86_64
2280 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2281 CPU_BASED_CR8_LOAD_EXITING;
2282 #endif
2283 }
2284 if (!enable_ept)
2285 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2286 CPU_BASED_CR3_LOAD_EXITING |
2287 CPU_BASED_INVLPG_EXITING;
2288 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2289
2290 if (cpu_has_secondary_exec_ctrls()) {
2291 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2292 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2293 exec_control &=
2294 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2295 if (vmx->vpid == 0)
2296 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2297 if (!enable_ept)
2298 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2299 if (!enable_unrestricted_guest)
2300 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2301 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2302 }
2303
2304 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2305 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2306 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2307
2308 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2309 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2310 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2311
2312 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2313 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2314 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2315 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2316 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2317 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2318 #ifdef CONFIG_X86_64
2319 rdmsrl(MSR_FS_BASE, a);
2320 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2321 rdmsrl(MSR_GS_BASE, a);
2322 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2323 #else
2324 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2325 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2326 #endif
2327
2328 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2329
2330 kvm_get_idt(&dt);
2331 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2332
2333 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2334 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2335 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2336 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2337 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2338
2339 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2340 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2341 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2342 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2343 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2344 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2345
2346 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2347 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2348 host_pat = msr_low | ((u64) msr_high << 32);
2349 vmcs_write64(HOST_IA32_PAT, host_pat);
2350 }
2351 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2352 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2353 host_pat = msr_low | ((u64) msr_high << 32);
2354 /* Write the default value follow host pat */
2355 vmcs_write64(GUEST_IA32_PAT, host_pat);
2356 /* Keep arch.pat sync with GUEST_IA32_PAT */
2357 vmx->vcpu.arch.pat = host_pat;
2358 }
2359
2360 for (i = 0; i < NR_VMX_MSR; ++i) {
2361 u32 index = vmx_msr_index[i];
2362 u32 data_low, data_high;
2363 u64 data;
2364 int j = vmx->nmsrs;
2365
2366 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2367 continue;
2368 if (wrmsr_safe(index, data_low, data_high) < 0)
2369 continue;
2370 data = data_low | ((u64)data_high << 32);
2371 vmx->host_msrs[j].index = index;
2372 vmx->host_msrs[j].reserved = 0;
2373 vmx->host_msrs[j].data = data;
2374 vmx->guest_msrs[j] = vmx->host_msrs[j];
2375 ++vmx->nmsrs;
2376 }
2377
2378 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2379
2380 /* 22.2.1, 20.8.1 */
2381 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2382
2383 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2384 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2385
2386 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2387 rdtscll(tsc_this);
2388 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2389 tsc_base = tsc_this;
2390
2391 guest_write_tsc(0, tsc_base);
2392
2393 return 0;
2394 }
2395
2396 static int init_rmode(struct kvm *kvm)
2397 {
2398 if (!init_rmode_tss(kvm))
2399 return 0;
2400 if (!init_rmode_identity_map(kvm))
2401 return 0;
2402 return 1;
2403 }
2404
2405 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2406 {
2407 struct vcpu_vmx *vmx = to_vmx(vcpu);
2408 u64 msr;
2409 int ret;
2410
2411 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2412 down_read(&vcpu->kvm->slots_lock);
2413 if (!init_rmode(vmx->vcpu.kvm)) {
2414 ret = -ENOMEM;
2415 goto out;
2416 }
2417
2418 vmx->rmode.vm86_active = 0;
2419
2420 vmx->soft_vnmi_blocked = 0;
2421
2422 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2423 kvm_set_cr8(&vmx->vcpu, 0);
2424 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2425 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2426 msr |= MSR_IA32_APICBASE_BSP;
2427 kvm_set_apic_base(&vmx->vcpu, msr);
2428
2429 fx_init(&vmx->vcpu);
2430
2431 seg_setup(VCPU_SREG_CS);
2432 /*
2433 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2434 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2435 */
2436 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2437 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2438 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2439 } else {
2440 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2441 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2442 }
2443
2444 seg_setup(VCPU_SREG_DS);
2445 seg_setup(VCPU_SREG_ES);
2446 seg_setup(VCPU_SREG_FS);
2447 seg_setup(VCPU_SREG_GS);
2448 seg_setup(VCPU_SREG_SS);
2449
2450 vmcs_write16(GUEST_TR_SELECTOR, 0);
2451 vmcs_writel(GUEST_TR_BASE, 0);
2452 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2453 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2454
2455 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2456 vmcs_writel(GUEST_LDTR_BASE, 0);
2457 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2458 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2459
2460 vmcs_write32(GUEST_SYSENTER_CS, 0);
2461 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2462 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2463
2464 vmcs_writel(GUEST_RFLAGS, 0x02);
2465 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2466 kvm_rip_write(vcpu, 0xfff0);
2467 else
2468 kvm_rip_write(vcpu, 0);
2469 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2470
2471 vmcs_writel(GUEST_DR7, 0x400);
2472
2473 vmcs_writel(GUEST_GDTR_BASE, 0);
2474 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2475
2476 vmcs_writel(GUEST_IDTR_BASE, 0);
2477 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2478
2479 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2480 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2481 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2482
2483 /* Special registers */
2484 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2485
2486 setup_msrs(vmx);
2487
2488 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2489
2490 if (cpu_has_vmx_tpr_shadow()) {
2491 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2492 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2493 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2494 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2495 vmcs_write32(TPR_THRESHOLD, 0);
2496 }
2497
2498 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2499 vmcs_write64(APIC_ACCESS_ADDR,
2500 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2501
2502 if (vmx->vpid != 0)
2503 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2504
2505 vmx->vcpu.arch.cr0 = 0x60000010;
2506 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2507 vmx_set_cr4(&vmx->vcpu, 0);
2508 vmx_set_efer(&vmx->vcpu, 0);
2509 vmx_fpu_activate(&vmx->vcpu);
2510 update_exception_bitmap(&vmx->vcpu);
2511
2512 vpid_sync_vcpu_all(vmx);
2513
2514 ret = 0;
2515
2516 /* HACK: Don't enable emulation on guest boot/reset */
2517 vmx->emulation_required = 0;
2518
2519 out:
2520 up_read(&vcpu->kvm->slots_lock);
2521 return ret;
2522 }
2523
2524 static void enable_irq_window(struct kvm_vcpu *vcpu)
2525 {
2526 u32 cpu_based_vm_exec_control;
2527
2528 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2529 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2530 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2531 }
2532
2533 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2534 {
2535 u32 cpu_based_vm_exec_control;
2536
2537 if (!cpu_has_virtual_nmis()) {
2538 enable_irq_window(vcpu);
2539 return;
2540 }
2541
2542 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2543 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2544 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2545 }
2546
2547 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2548 {
2549 struct vcpu_vmx *vmx = to_vmx(vcpu);
2550 uint32_t intr;
2551 int irq = vcpu->arch.interrupt.nr;
2552
2553 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2554
2555 ++vcpu->stat.irq_injections;
2556 if (vmx->rmode.vm86_active) {
2557 vmx->rmode.irq.pending = true;
2558 vmx->rmode.irq.vector = irq;
2559 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2560 if (vcpu->arch.interrupt.soft)
2561 vmx->rmode.irq.rip +=
2562 vmx->vcpu.arch.event_exit_inst_len;
2563 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2564 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2565 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2566 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2567 return;
2568 }
2569 intr = irq | INTR_INFO_VALID_MASK;
2570 if (vcpu->arch.interrupt.soft) {
2571 intr |= INTR_TYPE_SOFT_INTR;
2572 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2573 vmx->vcpu.arch.event_exit_inst_len);
2574 } else
2575 intr |= INTR_TYPE_EXT_INTR;
2576 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2577 }
2578
2579 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2580 {
2581 struct vcpu_vmx *vmx = to_vmx(vcpu);
2582
2583 if (!cpu_has_virtual_nmis()) {
2584 /*
2585 * Tracking the NMI-blocked state in software is built upon
2586 * finding the next open IRQ window. This, in turn, depends on
2587 * well-behaving guests: They have to keep IRQs disabled at
2588 * least as long as the NMI handler runs. Otherwise we may
2589 * cause NMI nesting, maybe breaking the guest. But as this is
2590 * highly unlikely, we can live with the residual risk.
2591 */
2592 vmx->soft_vnmi_blocked = 1;
2593 vmx->vnmi_blocked_time = 0;
2594 }
2595
2596 ++vcpu->stat.nmi_injections;
2597 if (vmx->rmode.vm86_active) {
2598 vmx->rmode.irq.pending = true;
2599 vmx->rmode.irq.vector = NMI_VECTOR;
2600 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2602 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2603 INTR_INFO_VALID_MASK);
2604 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2605 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2606 return;
2607 }
2608 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2609 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2610 }
2611
2612 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2613 {
2614 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2615 return 0;
2616
2617 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2618 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2619 GUEST_INTR_STATE_NMI));
2620 }
2621
2622 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2623 {
2624 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2625 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2626 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2627 }
2628
2629 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2630 {
2631 int ret;
2632 struct kvm_userspace_memory_region tss_mem = {
2633 .slot = TSS_PRIVATE_MEMSLOT,
2634 .guest_phys_addr = addr,
2635 .memory_size = PAGE_SIZE * 3,
2636 .flags = 0,
2637 };
2638
2639 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2640 if (ret)
2641 return ret;
2642 kvm->arch.tss_addr = addr;
2643 return 0;
2644 }
2645
2646 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2647 int vec, u32 err_code)
2648 {
2649 /*
2650 * Instruction with address size override prefix opcode 0x67
2651 * Cause the #SS fault with 0 error code in VM86 mode.
2652 */
2653 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2654 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2655 return 1;
2656 /*
2657 * Forward all other exceptions that are valid in real mode.
2658 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2659 * the required debugging infrastructure rework.
2660 */
2661 switch (vec) {
2662 case DB_VECTOR:
2663 if (vcpu->guest_debug &
2664 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2665 return 0;
2666 kvm_queue_exception(vcpu, vec);
2667 return 1;
2668 case BP_VECTOR:
2669 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2670 return 0;
2671 /* fall through */
2672 case DE_VECTOR:
2673 case OF_VECTOR:
2674 case BR_VECTOR:
2675 case UD_VECTOR:
2676 case DF_VECTOR:
2677 case SS_VECTOR:
2678 case GP_VECTOR:
2679 case MF_VECTOR:
2680 kvm_queue_exception(vcpu, vec);
2681 return 1;
2682 }
2683 return 0;
2684 }
2685
2686 /*
2687 * Trigger machine check on the host. We assume all the MSRs are already set up
2688 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2689 * We pass a fake environment to the machine check handler because we want
2690 * the guest to be always treated like user space, no matter what context
2691 * it used internally.
2692 */
2693 static void kvm_machine_check(void)
2694 {
2695 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2696 struct pt_regs regs = {
2697 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2698 .flags = X86_EFLAGS_IF,
2699 };
2700
2701 do_machine_check(&regs, 0);
2702 #endif
2703 }
2704
2705 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2706 {
2707 /* already handled by vcpu_run */
2708 return 1;
2709 }
2710
2711 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2712 {
2713 struct vcpu_vmx *vmx = to_vmx(vcpu);
2714 u32 intr_info, ex_no, error_code;
2715 unsigned long cr2, rip, dr6;
2716 u32 vect_info;
2717 enum emulation_result er;
2718
2719 vect_info = vmx->idt_vectoring_info;
2720 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2721
2722 if (is_machine_check(intr_info))
2723 return handle_machine_check(vcpu, kvm_run);
2724
2725 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2726 !is_page_fault(intr_info))
2727 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2728 "intr info 0x%x\n", __func__, vect_info, intr_info);
2729
2730 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2731 return 1; /* already handled by vmx_vcpu_run() */
2732
2733 if (is_no_device(intr_info)) {
2734 vmx_fpu_activate(vcpu);
2735 return 1;
2736 }
2737
2738 if (is_invalid_opcode(intr_info)) {
2739 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2740 if (er != EMULATE_DONE)
2741 kvm_queue_exception(vcpu, UD_VECTOR);
2742 return 1;
2743 }
2744
2745 error_code = 0;
2746 rip = kvm_rip_read(vcpu);
2747 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2748 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2749 if (is_page_fault(intr_info)) {
2750 /* EPT won't cause page fault directly */
2751 if (enable_ept)
2752 BUG();
2753 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2754 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2755 (u32)((u64)cr2 >> 32), handler);
2756 if (kvm_event_needs_reinjection(vcpu))
2757 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2758 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2759 }
2760
2761 if (vmx->rmode.vm86_active &&
2762 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2763 error_code)) {
2764 if (vcpu->arch.halt_request) {
2765 vcpu->arch.halt_request = 0;
2766 return kvm_emulate_halt(vcpu);
2767 }
2768 return 1;
2769 }
2770
2771 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2772 switch (ex_no) {
2773 case DB_VECTOR:
2774 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2775 if (!(vcpu->guest_debug &
2776 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2777 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2778 kvm_queue_exception(vcpu, DB_VECTOR);
2779 return 1;
2780 }
2781 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2782 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2783 /* fall through */
2784 case BP_VECTOR:
2785 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2786 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2787 kvm_run->debug.arch.exception = ex_no;
2788 break;
2789 default:
2790 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2791 kvm_run->ex.exception = ex_no;
2792 kvm_run->ex.error_code = error_code;
2793 break;
2794 }
2795 return 0;
2796 }
2797
2798 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2799 struct kvm_run *kvm_run)
2800 {
2801 ++vcpu->stat.irq_exits;
2802 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2803 return 1;
2804 }
2805
2806 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2807 {
2808 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2809 return 0;
2810 }
2811
2812 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2813 {
2814 unsigned long exit_qualification;
2815 int size, in, string;
2816 unsigned port;
2817
2818 ++vcpu->stat.io_exits;
2819 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2820 string = (exit_qualification & 16) != 0;
2821
2822 if (string) {
2823 if (emulate_instruction(vcpu,
2824 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2825 return 0;
2826 return 1;
2827 }
2828
2829 size = (exit_qualification & 7) + 1;
2830 in = (exit_qualification & 8) != 0;
2831 port = exit_qualification >> 16;
2832
2833 skip_emulated_instruction(vcpu);
2834 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2835 }
2836
2837 static void
2838 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2839 {
2840 /*
2841 * Patch in the VMCALL instruction:
2842 */
2843 hypercall[0] = 0x0f;
2844 hypercall[1] = 0x01;
2845 hypercall[2] = 0xc1;
2846 }
2847
2848 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2849 {
2850 unsigned long exit_qualification;
2851 int cr;
2852 int reg;
2853
2854 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2855 cr = exit_qualification & 15;
2856 reg = (exit_qualification >> 8) & 15;
2857 switch ((exit_qualification >> 4) & 3) {
2858 case 0: /* mov to cr */
2859 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2860 (u32)kvm_register_read(vcpu, reg),
2861 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2862 handler);
2863 switch (cr) {
2864 case 0:
2865 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2866 skip_emulated_instruction(vcpu);
2867 return 1;
2868 case 3:
2869 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2870 skip_emulated_instruction(vcpu);
2871 return 1;
2872 case 4:
2873 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2874 skip_emulated_instruction(vcpu);
2875 return 1;
2876 case 8: {
2877 u8 cr8_prev = kvm_get_cr8(vcpu);
2878 u8 cr8 = kvm_register_read(vcpu, reg);
2879 kvm_set_cr8(vcpu, cr8);
2880 skip_emulated_instruction(vcpu);
2881 if (irqchip_in_kernel(vcpu->kvm))
2882 return 1;
2883 if (cr8_prev <= cr8)
2884 return 1;
2885 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2886 return 0;
2887 }
2888 };
2889 break;
2890 case 2: /* clts */
2891 vmx_fpu_deactivate(vcpu);
2892 vcpu->arch.cr0 &= ~X86_CR0_TS;
2893 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2894 vmx_fpu_activate(vcpu);
2895 KVMTRACE_0D(CLTS, vcpu, handler);
2896 skip_emulated_instruction(vcpu);
2897 return 1;
2898 case 1: /*mov from cr*/
2899 switch (cr) {
2900 case 3:
2901 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2902 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2903 (u32)kvm_register_read(vcpu, reg),
2904 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2905 handler);
2906 skip_emulated_instruction(vcpu);
2907 return 1;
2908 case 8:
2909 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2910 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2911 (u32)kvm_register_read(vcpu, reg), handler);
2912 skip_emulated_instruction(vcpu);
2913 return 1;
2914 }
2915 break;
2916 case 3: /* lmsw */
2917 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2918
2919 skip_emulated_instruction(vcpu);
2920 return 1;
2921 default:
2922 break;
2923 }
2924 kvm_run->exit_reason = 0;
2925 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2926 (int)(exit_qualification >> 4) & 3, cr);
2927 return 0;
2928 }
2929
2930 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2931 {
2932 unsigned long exit_qualification;
2933 unsigned long val;
2934 int dr, reg;
2935
2936 dr = vmcs_readl(GUEST_DR7);
2937 if (dr & DR7_GD) {
2938 /*
2939 * As the vm-exit takes precedence over the debug trap, we
2940 * need to emulate the latter, either for the host or the
2941 * guest debugging itself.
2942 */
2943 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2944 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2945 kvm_run->debug.arch.dr7 = dr;
2946 kvm_run->debug.arch.pc =
2947 vmcs_readl(GUEST_CS_BASE) +
2948 vmcs_readl(GUEST_RIP);
2949 kvm_run->debug.arch.exception = DB_VECTOR;
2950 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2951 return 0;
2952 } else {
2953 vcpu->arch.dr7 &= ~DR7_GD;
2954 vcpu->arch.dr6 |= DR6_BD;
2955 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2956 kvm_queue_exception(vcpu, DB_VECTOR);
2957 return 1;
2958 }
2959 }
2960
2961 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2962 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2963 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2964 if (exit_qualification & TYPE_MOV_FROM_DR) {
2965 switch (dr) {
2966 case 0 ... 3:
2967 val = vcpu->arch.db[dr];
2968 break;
2969 case 6:
2970 val = vcpu->arch.dr6;
2971 break;
2972 case 7:
2973 val = vcpu->arch.dr7;
2974 break;
2975 default:
2976 val = 0;
2977 }
2978 kvm_register_write(vcpu, reg, val);
2979 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2980 } else {
2981 val = vcpu->arch.regs[reg];
2982 switch (dr) {
2983 case 0 ... 3:
2984 vcpu->arch.db[dr] = val;
2985 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2986 vcpu->arch.eff_db[dr] = val;
2987 break;
2988 case 4 ... 5:
2989 if (vcpu->arch.cr4 & X86_CR4_DE)
2990 kvm_queue_exception(vcpu, UD_VECTOR);
2991 break;
2992 case 6:
2993 if (val & 0xffffffff00000000ULL) {
2994 kvm_queue_exception(vcpu, GP_VECTOR);
2995 break;
2996 }
2997 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2998 break;
2999 case 7:
3000 if (val & 0xffffffff00000000ULL) {
3001 kvm_queue_exception(vcpu, GP_VECTOR);
3002 break;
3003 }
3004 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3005 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3006 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3007 vcpu->arch.switch_db_regs =
3008 (val & DR7_BP_EN_MASK);
3009 }
3010 break;
3011 }
3012 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
3013 }
3014 skip_emulated_instruction(vcpu);
3015 return 1;
3016 }
3017
3018 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3019 {
3020 kvm_emulate_cpuid(vcpu);
3021 return 1;
3022 }
3023
3024 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3025 {
3026 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3027 u64 data;
3028
3029 if (vmx_get_msr(vcpu, ecx, &data)) {
3030 kvm_inject_gp(vcpu, 0);
3031 return 1;
3032 }
3033
3034 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
3035 handler);
3036
3037 /* FIXME: handling of bits 32:63 of rax, rdx */
3038 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3039 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3040 skip_emulated_instruction(vcpu);
3041 return 1;
3042 }
3043
3044 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3045 {
3046 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3047 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3048 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3049
3050 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
3051 handler);
3052
3053 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3054 kvm_inject_gp(vcpu, 0);
3055 return 1;
3056 }
3057
3058 skip_emulated_instruction(vcpu);
3059 return 1;
3060 }
3061
3062 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3063 struct kvm_run *kvm_run)
3064 {
3065 return 1;
3066 }
3067
3068 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3069 struct kvm_run *kvm_run)
3070 {
3071 u32 cpu_based_vm_exec_control;
3072
3073 /* clear pending irq */
3074 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3075 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3076 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3077
3078 KVMTRACE_0D(PEND_INTR, vcpu, handler);
3079 ++vcpu->stat.irq_window_exits;
3080
3081 /*
3082 * If the user space waits to inject interrupts, exit as soon as
3083 * possible
3084 */
3085 if (!irqchip_in_kernel(vcpu->kvm) &&
3086 kvm_run->request_interrupt_window &&
3087 !kvm_cpu_has_interrupt(vcpu)) {
3088 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3089 return 0;
3090 }
3091 return 1;
3092 }
3093
3094 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3095 {
3096 skip_emulated_instruction(vcpu);
3097 return kvm_emulate_halt(vcpu);
3098 }
3099
3100 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3101 {
3102 skip_emulated_instruction(vcpu);
3103 kvm_emulate_hypercall(vcpu);
3104 return 1;
3105 }
3106
3107 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3108 {
3109 kvm_queue_exception(vcpu, UD_VECTOR);
3110 return 1;
3111 }
3112
3113 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3114 {
3115 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3116
3117 kvm_mmu_invlpg(vcpu, exit_qualification);
3118 skip_emulated_instruction(vcpu);
3119 return 1;
3120 }
3121
3122 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3123 {
3124 skip_emulated_instruction(vcpu);
3125 /* TODO: Add support for VT-d/pass-through device */
3126 return 1;
3127 }
3128
3129 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3130 {
3131 unsigned long exit_qualification;
3132 enum emulation_result er;
3133 unsigned long offset;
3134
3135 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3136 offset = exit_qualification & 0xffful;
3137
3138 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3139
3140 if (er != EMULATE_DONE) {
3141 printk(KERN_ERR
3142 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3143 offset);
3144 return -ENOTSUPP;
3145 }
3146 return 1;
3147 }
3148
3149 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3150 {
3151 struct vcpu_vmx *vmx = to_vmx(vcpu);
3152 unsigned long exit_qualification;
3153 u16 tss_selector;
3154 int reason, type, idt_v;
3155
3156 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3157 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3158
3159 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3160
3161 reason = (u32)exit_qualification >> 30;
3162 if (reason == TASK_SWITCH_GATE && idt_v) {
3163 switch (type) {
3164 case INTR_TYPE_NMI_INTR:
3165 vcpu->arch.nmi_injected = false;
3166 if (cpu_has_virtual_nmis())
3167 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3168 GUEST_INTR_STATE_NMI);
3169 break;
3170 case INTR_TYPE_EXT_INTR:
3171 case INTR_TYPE_SOFT_INTR:
3172 kvm_clear_interrupt_queue(vcpu);
3173 break;
3174 case INTR_TYPE_HARD_EXCEPTION:
3175 case INTR_TYPE_SOFT_EXCEPTION:
3176 kvm_clear_exception_queue(vcpu);
3177 break;
3178 default:
3179 break;
3180 }
3181 }
3182 tss_selector = exit_qualification;
3183
3184 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3185 type != INTR_TYPE_EXT_INTR &&
3186 type != INTR_TYPE_NMI_INTR))
3187 skip_emulated_instruction(vcpu);
3188
3189 if (!kvm_task_switch(vcpu, tss_selector, reason))
3190 return 0;
3191
3192 /* clear all local breakpoint enable flags */
3193 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3194
3195 /*
3196 * TODO: What about debug traps on tss switch?
3197 * Are we supposed to inject them and update dr6?
3198 */
3199
3200 return 1;
3201 }
3202
3203 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3204 {
3205 unsigned long exit_qualification;
3206 gpa_t gpa;
3207 int gla_validity;
3208
3209 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3210
3211 if (exit_qualification & (1 << 6)) {
3212 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3213 return -ENOTSUPP;
3214 }
3215
3216 gla_validity = (exit_qualification >> 7) & 0x3;
3217 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3218 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3219 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3220 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3221 vmcs_readl(GUEST_LINEAR_ADDRESS));
3222 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3223 (long unsigned int)exit_qualification);
3224 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3225 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3226 return 0;
3227 }
3228
3229 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3230 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3231 }
3232
3233 static u64 ept_rsvd_mask(u64 spte, int level)
3234 {
3235 int i;
3236 u64 mask = 0;
3237
3238 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3239 mask |= (1ULL << i);
3240
3241 if (level > 2)
3242 /* bits 7:3 reserved */
3243 mask |= 0xf8;
3244 else if (level == 2) {
3245 if (spte & (1ULL << 7))
3246 /* 2MB ref, bits 20:12 reserved */
3247 mask |= 0x1ff000;
3248 else
3249 /* bits 6:3 reserved */
3250 mask |= 0x78;
3251 }
3252
3253 return mask;
3254 }
3255
3256 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3257 int level)
3258 {
3259 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3260
3261 /* 010b (write-only) */
3262 WARN_ON((spte & 0x7) == 0x2);
3263
3264 /* 110b (write/execute) */
3265 WARN_ON((spte & 0x7) == 0x6);
3266
3267 /* 100b (execute-only) and value not supported by logical processor */
3268 if (!cpu_has_vmx_ept_execute_only())
3269 WARN_ON((spte & 0x7) == 0x4);
3270
3271 /* not 000b */
3272 if ((spte & 0x7)) {
3273 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3274
3275 if (rsvd_bits != 0) {
3276 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3277 __func__, rsvd_bits);
3278 WARN_ON(1);
3279 }
3280
3281 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3282 u64 ept_mem_type = (spte & 0x38) >> 3;
3283
3284 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3285 ept_mem_type == 7) {
3286 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3287 __func__, ept_mem_type);
3288 WARN_ON(1);
3289 }
3290 }
3291 }
3292 }
3293
3294 static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3295 {
3296 u64 sptes[4];
3297 int nr_sptes, i;
3298 gpa_t gpa;
3299
3300 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3301
3302 printk(KERN_ERR "EPT: Misconfiguration.\n");
3303 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3304
3305 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3306
3307 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3308 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3309
3310 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3311 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3312
3313 return 0;
3314 }
3315
3316 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3317 {
3318 u32 cpu_based_vm_exec_control;
3319
3320 /* clear pending NMI */
3321 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3322 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3323 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3324 ++vcpu->stat.nmi_window_exits;
3325
3326 return 1;
3327 }
3328
3329 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3330 struct kvm_run *kvm_run)
3331 {
3332 struct vcpu_vmx *vmx = to_vmx(vcpu);
3333 enum emulation_result err = EMULATE_DONE;
3334
3335 local_irq_enable();
3336 preempt_enable();
3337
3338 while (!guest_state_valid(vcpu)) {
3339 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3340
3341 if (err == EMULATE_DO_MMIO)
3342 break;
3343
3344 if (err != EMULATE_DONE) {
3345 kvm_report_emulation_failure(vcpu, "emulation failure");
3346 break;
3347 }
3348
3349 if (signal_pending(current))
3350 break;
3351 if (need_resched())
3352 schedule();
3353 }
3354
3355 preempt_disable();
3356 local_irq_disable();
3357
3358 vmx->invalid_state_emulation_result = err;
3359 }
3360
3361 /*
3362 * The exit handlers return 1 if the exit was handled fully and guest execution
3363 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3364 * to be done to userspace and return 0.
3365 */
3366 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3367 struct kvm_run *kvm_run) = {
3368 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3369 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3370 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3371 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3372 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3373 [EXIT_REASON_CR_ACCESS] = handle_cr,
3374 [EXIT_REASON_DR_ACCESS] = handle_dr,
3375 [EXIT_REASON_CPUID] = handle_cpuid,
3376 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3377 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3378 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3379 [EXIT_REASON_HLT] = handle_halt,
3380 [EXIT_REASON_INVLPG] = handle_invlpg,
3381 [EXIT_REASON_VMCALL] = handle_vmcall,
3382 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3383 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3384 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3385 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3386 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3387 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3388 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3389 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3390 [EXIT_REASON_VMON] = handle_vmx_insn,
3391 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3392 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3393 [EXIT_REASON_WBINVD] = handle_wbinvd,
3394 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3395 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3396 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3397 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3398 };
3399
3400 static const int kvm_vmx_max_exit_handlers =
3401 ARRAY_SIZE(kvm_vmx_exit_handlers);
3402
3403 /*
3404 * The guest has exited. See if we can fix it or if we need userspace
3405 * assistance.
3406 */
3407 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3408 {
3409 struct vcpu_vmx *vmx = to_vmx(vcpu);
3410 u32 exit_reason = vmx->exit_reason;
3411 u32 vectoring_info = vmx->idt_vectoring_info;
3412
3413 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3414 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3415
3416 /* If we need to emulate an MMIO from handle_invalid_guest_state
3417 * we just return 0 */
3418 if (vmx->emulation_required && emulate_invalid_guest_state) {
3419 if (guest_state_valid(vcpu))
3420 vmx->emulation_required = 0;
3421 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3422 }
3423
3424 /* Access CR3 don't cause VMExit in paging mode, so we need
3425 * to sync with guest real CR3. */
3426 if (enable_ept && is_paging(vcpu))
3427 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3428
3429 if (unlikely(vmx->fail)) {
3430 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3431 kvm_run->fail_entry.hardware_entry_failure_reason
3432 = vmcs_read32(VM_INSTRUCTION_ERROR);
3433 return 0;
3434 }
3435
3436 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3437 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3438 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3439 exit_reason != EXIT_REASON_TASK_SWITCH))
3440 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3441 "(0x%x) and exit reason is 0x%x\n",
3442 __func__, vectoring_info, exit_reason);
3443
3444 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3445 if (vmx_interrupt_allowed(vcpu)) {
3446 vmx->soft_vnmi_blocked = 0;
3447 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3448 vcpu->arch.nmi_pending) {
3449 /*
3450 * This CPU don't support us in finding the end of an
3451 * NMI-blocked window if the guest runs with IRQs
3452 * disabled. So we pull the trigger after 1 s of
3453 * futile waiting, but inform the user about this.
3454 */
3455 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3456 "state on VCPU %d after 1 s timeout\n",
3457 __func__, vcpu->vcpu_id);
3458 vmx->soft_vnmi_blocked = 0;
3459 }
3460 }
3461
3462 if (exit_reason < kvm_vmx_max_exit_handlers
3463 && kvm_vmx_exit_handlers[exit_reason])
3464 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3465 else {
3466 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3467 kvm_run->hw.hardware_exit_reason = exit_reason;
3468 }
3469 return 0;
3470 }
3471
3472 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3473 {
3474 if (irr == -1 || tpr < irr) {
3475 vmcs_write32(TPR_THRESHOLD, 0);
3476 return;
3477 }
3478
3479 vmcs_write32(TPR_THRESHOLD, irr);
3480 }
3481
3482 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3483 {
3484 u32 exit_intr_info;
3485 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3486 bool unblock_nmi;
3487 u8 vector;
3488 int type;
3489 bool idtv_info_valid;
3490
3491 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3492
3493 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3494
3495 /* Handle machine checks before interrupts are enabled */
3496 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3497 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3498 && is_machine_check(exit_intr_info)))
3499 kvm_machine_check();
3500
3501 /* We need to handle NMIs before interrupts are enabled */
3502 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3503 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3504 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3505 asm("int $2");
3506 }
3507
3508 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3509
3510 if (cpu_has_virtual_nmis()) {
3511 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3512 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3513 /*
3514 * SDM 3: 27.7.1.2 (September 2008)
3515 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3516 * a guest IRET fault.
3517 * SDM 3: 23.2.2 (September 2008)
3518 * Bit 12 is undefined in any of the following cases:
3519 * If the VM exit sets the valid bit in the IDT-vectoring
3520 * information field.
3521 * If the VM exit is due to a double fault.
3522 */
3523 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3524 vector != DF_VECTOR && !idtv_info_valid)
3525 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3526 GUEST_INTR_STATE_NMI);
3527 } else if (unlikely(vmx->soft_vnmi_blocked))
3528 vmx->vnmi_blocked_time +=
3529 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3530
3531 vmx->vcpu.arch.nmi_injected = false;
3532 kvm_clear_exception_queue(&vmx->vcpu);
3533 kvm_clear_interrupt_queue(&vmx->vcpu);
3534
3535 if (!idtv_info_valid)
3536 return;
3537
3538 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3539 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3540
3541 switch (type) {
3542 case INTR_TYPE_NMI_INTR:
3543 vmx->vcpu.arch.nmi_injected = true;
3544 /*
3545 * SDM 3: 27.7.1.2 (September 2008)
3546 * Clear bit "block by NMI" before VM entry if a NMI
3547 * delivery faulted.
3548 */
3549 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3550 GUEST_INTR_STATE_NMI);
3551 break;
3552 case INTR_TYPE_SOFT_EXCEPTION:
3553 vmx->vcpu.arch.event_exit_inst_len =
3554 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3555 /* fall through */
3556 case INTR_TYPE_HARD_EXCEPTION:
3557 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3558 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3559 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3560 } else
3561 kvm_queue_exception(&vmx->vcpu, vector);
3562 break;
3563 case INTR_TYPE_SOFT_INTR:
3564 vmx->vcpu.arch.event_exit_inst_len =
3565 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3566 /* fall through */
3567 case INTR_TYPE_EXT_INTR:
3568 kvm_queue_interrupt(&vmx->vcpu, vector,
3569 type == INTR_TYPE_SOFT_INTR);
3570 break;
3571 default:
3572 break;
3573 }
3574 }
3575
3576 /*
3577 * Failure to inject an interrupt should give us the information
3578 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3579 * when fetching the interrupt redirection bitmap in the real-mode
3580 * tss, this doesn't happen. So we do it ourselves.
3581 */
3582 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3583 {
3584 vmx->rmode.irq.pending = 0;
3585 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3586 return;
3587 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3588 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3589 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3590 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3591 return;
3592 }
3593 vmx->idt_vectoring_info =
3594 VECTORING_INFO_VALID_MASK
3595 | INTR_TYPE_EXT_INTR
3596 | vmx->rmode.irq.vector;
3597 }
3598
3599 #ifdef CONFIG_X86_64
3600 #define R "r"
3601 #define Q "q"
3602 #else
3603 #define R "e"
3604 #define Q "l"
3605 #endif
3606
3607 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3608 {
3609 struct vcpu_vmx *vmx = to_vmx(vcpu);
3610
3611 if (enable_ept && is_paging(vcpu)) {
3612 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3613 ept_load_pdptrs(vcpu);
3614 }
3615 /* Record the guest's net vcpu time for enforced NMI injections. */
3616 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3617 vmx->entry_time = ktime_get();
3618
3619 /* Handle invalid guest state instead of entering VMX */
3620 if (vmx->emulation_required && emulate_invalid_guest_state) {
3621 handle_invalid_guest_state(vcpu, kvm_run);
3622 return;
3623 }
3624
3625 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3626 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3627 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3628 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3629
3630 /* When single-stepping over STI and MOV SS, we must clear the
3631 * corresponding interruptibility bits in the guest state. Otherwise
3632 * vmentry fails as it then expects bit 14 (BS) in pending debug
3633 * exceptions being set, but that's not correct for the guest debugging
3634 * case. */
3635 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3636 vmx_set_interrupt_shadow(vcpu, 0);
3637
3638 /*
3639 * Loading guest fpu may have cleared host cr0.ts
3640 */
3641 vmcs_writel(HOST_CR0, read_cr0());
3642
3643 set_debugreg(vcpu->arch.dr6, 6);
3644
3645 asm(
3646 /* Store host registers */
3647 "push %%"R"dx; push %%"R"bp;"
3648 "push %%"R"cx \n\t"
3649 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3650 "je 1f \n\t"
3651 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3652 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3653 "1: \n\t"
3654 /* Reload cr2 if changed */
3655 "mov %c[cr2](%0), %%"R"ax \n\t"
3656 "mov %%cr2, %%"R"dx \n\t"
3657 "cmp %%"R"ax, %%"R"dx \n\t"
3658 "je 2f \n\t"
3659 "mov %%"R"ax, %%cr2 \n\t"
3660 "2: \n\t"
3661 /* Check if vmlaunch of vmresume is needed */
3662 "cmpl $0, %c[launched](%0) \n\t"
3663 /* Load guest registers. Don't clobber flags. */
3664 "mov %c[rax](%0), %%"R"ax \n\t"
3665 "mov %c[rbx](%0), %%"R"bx \n\t"
3666 "mov %c[rdx](%0), %%"R"dx \n\t"
3667 "mov %c[rsi](%0), %%"R"si \n\t"
3668 "mov %c[rdi](%0), %%"R"di \n\t"
3669 "mov %c[rbp](%0), %%"R"bp \n\t"
3670 #ifdef CONFIG_X86_64
3671 "mov %c[r8](%0), %%r8 \n\t"
3672 "mov %c[r9](%0), %%r9 \n\t"
3673 "mov %c[r10](%0), %%r10 \n\t"
3674 "mov %c[r11](%0), %%r11 \n\t"
3675 "mov %c[r12](%0), %%r12 \n\t"
3676 "mov %c[r13](%0), %%r13 \n\t"
3677 "mov %c[r14](%0), %%r14 \n\t"
3678 "mov %c[r15](%0), %%r15 \n\t"
3679 #endif
3680 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3681
3682 /* Enter guest mode */
3683 "jne .Llaunched \n\t"
3684 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3685 "jmp .Lkvm_vmx_return \n\t"
3686 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3687 ".Lkvm_vmx_return: "
3688 /* Save guest registers, load host registers, keep flags */
3689 "xchg %0, (%%"R"sp) \n\t"
3690 "mov %%"R"ax, %c[rax](%0) \n\t"
3691 "mov %%"R"bx, %c[rbx](%0) \n\t"
3692 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3693 "mov %%"R"dx, %c[rdx](%0) \n\t"
3694 "mov %%"R"si, %c[rsi](%0) \n\t"
3695 "mov %%"R"di, %c[rdi](%0) \n\t"
3696 "mov %%"R"bp, %c[rbp](%0) \n\t"
3697 #ifdef CONFIG_X86_64
3698 "mov %%r8, %c[r8](%0) \n\t"
3699 "mov %%r9, %c[r9](%0) \n\t"
3700 "mov %%r10, %c[r10](%0) \n\t"
3701 "mov %%r11, %c[r11](%0) \n\t"
3702 "mov %%r12, %c[r12](%0) \n\t"
3703 "mov %%r13, %c[r13](%0) \n\t"
3704 "mov %%r14, %c[r14](%0) \n\t"
3705 "mov %%r15, %c[r15](%0) \n\t"
3706 #endif
3707 "mov %%cr2, %%"R"ax \n\t"
3708 "mov %%"R"ax, %c[cr2](%0) \n\t"
3709
3710 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3711 "setbe %c[fail](%0) \n\t"
3712 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3713 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3714 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3715 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3716 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3717 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3718 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3719 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3720 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3721 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3722 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3723 #ifdef CONFIG_X86_64
3724 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3725 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3726 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3727 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3728 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3729 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3730 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3731 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3732 #endif
3733 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3734 : "cc", "memory"
3735 , R"bx", R"di", R"si"
3736 #ifdef CONFIG_X86_64
3737 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3738 #endif
3739 );
3740
3741 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3742 | (1 << VCPU_EXREG_PDPTR));
3743 vcpu->arch.regs_dirty = 0;
3744
3745 get_debugreg(vcpu->arch.dr6, 6);
3746
3747 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3748 if (vmx->rmode.irq.pending)
3749 fixup_rmode_irq(vmx);
3750
3751 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3752 vmx->launched = 1;
3753
3754 vmx_complete_interrupts(vmx);
3755 }
3756
3757 #undef R
3758 #undef Q
3759
3760 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3761 {
3762 struct vcpu_vmx *vmx = to_vmx(vcpu);
3763
3764 if (vmx->vmcs) {
3765 vcpu_clear(vmx);
3766 free_vmcs(vmx->vmcs);
3767 vmx->vmcs = NULL;
3768 }
3769 }
3770
3771 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3772 {
3773 struct vcpu_vmx *vmx = to_vmx(vcpu);
3774
3775 spin_lock(&vmx_vpid_lock);
3776 if (vmx->vpid != 0)
3777 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3778 spin_unlock(&vmx_vpid_lock);
3779 vmx_free_vmcs(vcpu);
3780 kfree(vmx->host_msrs);
3781 kfree(vmx->guest_msrs);
3782 kvm_vcpu_uninit(vcpu);
3783 kmem_cache_free(kvm_vcpu_cache, vmx);
3784 }
3785
3786 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3787 {
3788 int err;
3789 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3790 int cpu;
3791
3792 if (!vmx)
3793 return ERR_PTR(-ENOMEM);
3794
3795 allocate_vpid(vmx);
3796
3797 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3798 if (err)
3799 goto free_vcpu;
3800
3801 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3802 if (!vmx->guest_msrs) {
3803 err = -ENOMEM;
3804 goto uninit_vcpu;
3805 }
3806
3807 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3808 if (!vmx->host_msrs)
3809 goto free_guest_msrs;
3810
3811 vmx->vmcs = alloc_vmcs();
3812 if (!vmx->vmcs)
3813 goto free_msrs;
3814
3815 vmcs_clear(vmx->vmcs);
3816
3817 cpu = get_cpu();
3818 vmx_vcpu_load(&vmx->vcpu, cpu);
3819 err = vmx_vcpu_setup(vmx);
3820 vmx_vcpu_put(&vmx->vcpu);
3821 put_cpu();
3822 if (err)
3823 goto free_vmcs;
3824 if (vm_need_virtualize_apic_accesses(kvm))
3825 if (alloc_apic_access_page(kvm) != 0)
3826 goto free_vmcs;
3827
3828 if (enable_ept)
3829 if (alloc_identity_pagetable(kvm) != 0)
3830 goto free_vmcs;
3831
3832 return &vmx->vcpu;
3833
3834 free_vmcs:
3835 free_vmcs(vmx->vmcs);
3836 free_msrs:
3837 kfree(vmx->host_msrs);
3838 free_guest_msrs:
3839 kfree(vmx->guest_msrs);
3840 uninit_vcpu:
3841 kvm_vcpu_uninit(&vmx->vcpu);
3842 free_vcpu:
3843 kmem_cache_free(kvm_vcpu_cache, vmx);
3844 return ERR_PTR(err);
3845 }
3846
3847 static void __init vmx_check_processor_compat(void *rtn)
3848 {
3849 struct vmcs_config vmcs_conf;
3850
3851 *(int *)rtn = 0;
3852 if (setup_vmcs_config(&vmcs_conf) < 0)
3853 *(int *)rtn = -EIO;
3854 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3855 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3856 smp_processor_id());
3857 *(int *)rtn = -EIO;
3858 }
3859 }
3860
3861 static int get_ept_level(void)
3862 {
3863 return VMX_EPT_DEFAULT_GAW + 1;
3864 }
3865
3866 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3867 {
3868 u64 ret;
3869
3870 /* For VT-d and EPT combination
3871 * 1. MMIO: always map as UC
3872 * 2. EPT with VT-d:
3873 * a. VT-d without snooping control feature: can't guarantee the
3874 * result, try to trust guest.
3875 * b. VT-d with snooping control feature: snooping control feature of
3876 * VT-d engine can guarantee the cache correctness. Just set it
3877 * to WB to keep consistent with host. So the same as item 3.
3878 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3879 * consistent with host MTRR
3880 */
3881 if (is_mmio)
3882 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3883 else if (vcpu->kvm->arch.iommu_domain &&
3884 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3885 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3886 VMX_EPT_MT_EPTE_SHIFT;
3887 else
3888 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3889 | VMX_EPT_IGMT_BIT;
3890
3891 return ret;
3892 }
3893
3894 static struct kvm_x86_ops vmx_x86_ops = {
3895 .cpu_has_kvm_support = cpu_has_kvm_support,
3896 .disabled_by_bios = vmx_disabled_by_bios,
3897 .hardware_setup = hardware_setup,
3898 .hardware_unsetup = hardware_unsetup,
3899 .check_processor_compatibility = vmx_check_processor_compat,
3900 .hardware_enable = hardware_enable,
3901 .hardware_disable = hardware_disable,
3902 .cpu_has_accelerated_tpr = report_flexpriority,
3903
3904 .vcpu_create = vmx_create_vcpu,
3905 .vcpu_free = vmx_free_vcpu,
3906 .vcpu_reset = vmx_vcpu_reset,
3907
3908 .prepare_guest_switch = vmx_save_host_state,
3909 .vcpu_load = vmx_vcpu_load,
3910 .vcpu_put = vmx_vcpu_put,
3911
3912 .set_guest_debug = set_guest_debug,
3913 .get_msr = vmx_get_msr,
3914 .set_msr = vmx_set_msr,
3915 .get_segment_base = vmx_get_segment_base,
3916 .get_segment = vmx_get_segment,
3917 .set_segment = vmx_set_segment,
3918 .get_cpl = vmx_get_cpl,
3919 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3920 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3921 .set_cr0 = vmx_set_cr0,
3922 .set_cr3 = vmx_set_cr3,
3923 .set_cr4 = vmx_set_cr4,
3924 .set_efer = vmx_set_efer,
3925 .get_idt = vmx_get_idt,
3926 .set_idt = vmx_set_idt,
3927 .get_gdt = vmx_get_gdt,
3928 .set_gdt = vmx_set_gdt,
3929 .cache_reg = vmx_cache_reg,
3930 .get_rflags = vmx_get_rflags,
3931 .set_rflags = vmx_set_rflags,
3932
3933 .tlb_flush = vmx_flush_tlb,
3934
3935 .run = vmx_vcpu_run,
3936 .handle_exit = vmx_handle_exit,
3937 .skip_emulated_instruction = skip_emulated_instruction,
3938 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3939 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3940 .patch_hypercall = vmx_patch_hypercall,
3941 .set_irq = vmx_inject_irq,
3942 .set_nmi = vmx_inject_nmi,
3943 .queue_exception = vmx_queue_exception,
3944 .interrupt_allowed = vmx_interrupt_allowed,
3945 .nmi_allowed = vmx_nmi_allowed,
3946 .enable_nmi_window = enable_nmi_window,
3947 .enable_irq_window = enable_irq_window,
3948 .update_cr8_intercept = update_cr8_intercept,
3949
3950 .set_tss_addr = vmx_set_tss_addr,
3951 .get_tdp_level = get_ept_level,
3952 .get_mt_mask = vmx_get_mt_mask,
3953 };
3954
3955 static int __init vmx_init(void)
3956 {
3957 int r;
3958
3959 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3960 if (!vmx_io_bitmap_a)
3961 return -ENOMEM;
3962
3963 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3964 if (!vmx_io_bitmap_b) {
3965 r = -ENOMEM;
3966 goto out;
3967 }
3968
3969 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3970 if (!vmx_msr_bitmap_legacy) {
3971 r = -ENOMEM;
3972 goto out1;
3973 }
3974
3975 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3976 if (!vmx_msr_bitmap_longmode) {
3977 r = -ENOMEM;
3978 goto out2;
3979 }
3980
3981 /*
3982 * Allow direct access to the PC debug port (it is often used for I/O
3983 * delays, but the vmexits simply slow things down).
3984 */
3985 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3986 clear_bit(0x80, vmx_io_bitmap_a);
3987
3988 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3989
3990 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3991 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3992
3993 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3994
3995 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3996 if (r)
3997 goto out3;
3998
3999 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4000 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4001 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4002 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4003 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4004 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4005
4006 if (enable_ept) {
4007 bypass_guest_pf = 0;
4008 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4009 VMX_EPT_WRITABLE_MASK);
4010 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4011 VMX_EPT_EXECUTABLE_MASK);
4012 kvm_enable_tdp();
4013 } else
4014 kvm_disable_tdp();
4015
4016 if (bypass_guest_pf)
4017 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4018
4019 ept_sync_global();
4020
4021 return 0;
4022
4023 out3:
4024 free_page((unsigned long)vmx_msr_bitmap_longmode);
4025 out2:
4026 free_page((unsigned long)vmx_msr_bitmap_legacy);
4027 out1:
4028 free_page((unsigned long)vmx_io_bitmap_b);
4029 out:
4030 free_page((unsigned long)vmx_io_bitmap_a);
4031 return r;
4032 }
4033
4034 static void __exit vmx_exit(void)
4035 {
4036 free_page((unsigned long)vmx_msr_bitmap_legacy);
4037 free_page((unsigned long)vmx_msr_bitmap_longmode);
4038 free_page((unsigned long)vmx_io_bitmap_b);
4039 free_page((unsigned long)vmx_io_bitmap_a);
4040
4041 kvm_exit();
4042 }
4043
4044 module_init(vmx_init)
4045 module_exit(vmx_exit)
Linux kernel - Deliverables
This page took 0.156921 seconds and 6 git commands to generate.