2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending
;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page
*apic_access_page
;
376 u64 msr_ia32_feature_control
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
421 u32 vm_entry_controls_shadow
;
422 u32 vm_exit_controls_shadow
;
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
428 struct loaded_vmcs vmcs01
;
429 struct loaded_vmcs
*loaded_vmcs
;
430 bool __launched
; /* temporary, used in vmx_vcpu_run */
431 struct msr_autoload
{
433 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
434 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
438 u16 fs_sel
, gs_sel
, ldt_sel
;
442 int gs_ldt_reload_needed
;
443 int fs_reload_needed
;
448 struct kvm_segment segs
[8];
451 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
452 struct kvm_save_segment
{
460 bool emulation_required
;
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked
;
465 s64 vnmi_blocked_time
;
470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc
;
473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested
;
477 enum segment_cache_field
{
486 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
488 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
491 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
497 static const unsigned long shadow_read_only_fields
[] = {
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
512 VM_EXIT_INSTRUCTION_LEN
,
513 IDT_VECTORING_INFO_FIELD
,
514 IDT_VECTORING_ERROR_CODE
,
515 VM_EXIT_INTR_ERROR_CODE
,
517 GUEST_LINEAR_ADDRESS
,
518 GUEST_PHYSICAL_ADDRESS
520 static const int max_shadow_read_only_fields
=
521 ARRAY_SIZE(shadow_read_only_fields
);
523 static const unsigned long shadow_read_write_fields
[] = {
529 GUEST_INTERRUPTIBILITY_INFO
,
541 CPU_BASED_VM_EXEC_CONTROL
,
542 VM_ENTRY_EXCEPTION_ERROR_CODE
,
543 VM_ENTRY_INTR_INFO_FIELD
,
544 VM_ENTRY_INSTRUCTION_LEN
,
545 VM_ENTRY_EXCEPTION_ERROR_CODE
,
551 static const int max_shadow_read_write_fields
=
552 ARRAY_SIZE(shadow_read_write_fields
);
554 static const unsigned short vmcs_field_to_offset_table
[] = {
555 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
556 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
557 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
558 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
559 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
560 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
561 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
562 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
563 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
564 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
565 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
566 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
567 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
568 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
569 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
570 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
571 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
572 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
573 FIELD64(MSR_BITMAP
, msr_bitmap
),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
577 FIELD64(TSC_OFFSET
, tsc_offset
),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
579 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
580 FIELD64(EPT_POINTER
, ept_pointer
),
581 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
582 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
583 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
584 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
585 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
587 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
588 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
589 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
590 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
591 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
592 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
596 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
599 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
600 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
601 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
603 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
608 FIELD(TPR_THRESHOLD
, tpr_threshold
),
609 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
610 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
611 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
612 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
613 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
614 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
615 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
616 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
617 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
618 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
619 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
620 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
621 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
622 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
623 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
624 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
625 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
626 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
627 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
628 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
629 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
630 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
631 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
632 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
633 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
634 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
635 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
637 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
638 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
639 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
640 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
641 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
642 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
643 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
644 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
645 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
646 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
647 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
648 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
649 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
650 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
651 FIELD(GUEST_CR0
, guest_cr0
),
652 FIELD(GUEST_CR3
, guest_cr3
),
653 FIELD(GUEST_CR4
, guest_cr4
),
654 FIELD(GUEST_ES_BASE
, guest_es_base
),
655 FIELD(GUEST_CS_BASE
, guest_cs_base
),
656 FIELD(GUEST_SS_BASE
, guest_ss_base
),
657 FIELD(GUEST_DS_BASE
, guest_ds_base
),
658 FIELD(GUEST_FS_BASE
, guest_fs_base
),
659 FIELD(GUEST_GS_BASE
, guest_gs_base
),
660 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
661 FIELD(GUEST_TR_BASE
, guest_tr_base
),
662 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
663 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
664 FIELD(GUEST_DR7
, guest_dr7
),
665 FIELD(GUEST_RSP
, guest_rsp
),
666 FIELD(GUEST_RIP
, guest_rip
),
667 FIELD(GUEST_RFLAGS
, guest_rflags
),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
669 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
670 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
671 FIELD(HOST_CR0
, host_cr0
),
672 FIELD(HOST_CR3
, host_cr3
),
673 FIELD(HOST_CR4
, host_cr4
),
674 FIELD(HOST_FS_BASE
, host_fs_base
),
675 FIELD(HOST_GS_BASE
, host_gs_base
),
676 FIELD(HOST_TR_BASE
, host_tr_base
),
677 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
678 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
679 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
680 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
681 FIELD(HOST_RSP
, host_rsp
),
682 FIELD(HOST_RIP
, host_rip
),
684 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
686 static inline short vmcs_field_to_offset(unsigned long field
)
688 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
690 return vmcs_field_to_offset_table
[field
];
693 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
695 return to_vmx(vcpu
)->nested
.current_vmcs12
;
698 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
700 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
701 if (is_error_page(page
))
707 static void nested_release_page(struct page
*page
)
709 kvm_release_page_dirty(page
);
712 static void nested_release_page_clean(struct page
*page
)
714 kvm_release_page_clean(page
);
717 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
718 static u64
construct_eptp(unsigned long root_hpa
);
719 static void kvm_cpu_vmxon(u64 addr
);
720 static void kvm_cpu_vmxoff(void);
721 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
722 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
723 struct kvm_segment
*var
, int seg
);
724 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
725 struct kvm_segment
*var
, int seg
);
726 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
727 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
728 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
729 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
730 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
732 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
733 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
738 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
739 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
741 static unsigned long *vmx_io_bitmap_a
;
742 static unsigned long *vmx_io_bitmap_b
;
743 static unsigned long *vmx_msr_bitmap_legacy
;
744 static unsigned long *vmx_msr_bitmap_longmode
;
745 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
746 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
747 static unsigned long *vmx_vmread_bitmap
;
748 static unsigned long *vmx_vmwrite_bitmap
;
750 static bool cpu_has_load_ia32_efer
;
751 static bool cpu_has_load_perf_global_ctrl
;
753 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
754 static DEFINE_SPINLOCK(vmx_vpid_lock
);
756 static struct vmcs_config
{
760 u32 pin_based_exec_ctrl
;
761 u32 cpu_based_exec_ctrl
;
762 u32 cpu_based_2nd_exec_ctrl
;
767 static struct vmx_capability
{
772 #define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
780 static const struct kvm_vmx_segment_field
{
785 } kvm_vmx_segment_fields
[] = {
786 VMX_SEGMENT_FIELD(CS
),
787 VMX_SEGMENT_FIELD(DS
),
788 VMX_SEGMENT_FIELD(ES
),
789 VMX_SEGMENT_FIELD(FS
),
790 VMX_SEGMENT_FIELD(GS
),
791 VMX_SEGMENT_FIELD(SS
),
792 VMX_SEGMENT_FIELD(TR
),
793 VMX_SEGMENT_FIELD(LDTR
),
796 static u64 host_efer
;
798 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
802 * away by decrementing the array size.
804 static const u32 vmx_msr_index
[] = {
806 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
808 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
810 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
812 static inline bool is_page_fault(u32 intr_info
)
814 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
815 INTR_INFO_VALID_MASK
)) ==
816 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
819 static inline bool is_no_device(u32 intr_info
)
821 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
822 INTR_INFO_VALID_MASK
)) ==
823 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
826 static inline bool is_invalid_opcode(u32 intr_info
)
828 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
829 INTR_INFO_VALID_MASK
)) ==
830 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
833 static inline bool is_external_interrupt(u32 intr_info
)
835 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
836 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
839 static inline bool is_machine_check(u32 intr_info
)
841 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
842 INTR_INFO_VALID_MASK
)) ==
843 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
846 static inline bool cpu_has_vmx_msr_bitmap(void)
848 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
851 static inline bool cpu_has_vmx_tpr_shadow(void)
853 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
856 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
861 static inline bool cpu_has_secondary_exec_ctrls(void)
863 return vmcs_config
.cpu_based_exec_ctrl
&
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
867 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
869 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
873 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
875 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
879 static inline bool cpu_has_vmx_apic_register_virt(void)
881 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
882 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
885 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
887 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
891 static inline bool cpu_has_vmx_posted_intr(void)
893 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
896 static inline bool cpu_has_vmx_apicv(void)
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
903 static inline bool cpu_has_vmx_flexpriority(void)
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
909 static inline bool cpu_has_vmx_ept_execute_only(void)
911 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
914 static inline bool cpu_has_vmx_eptp_uncacheable(void)
916 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
919 static inline bool cpu_has_vmx_eptp_writeback(void)
921 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
924 static inline bool cpu_has_vmx_ept_2m_page(void)
926 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
929 static inline bool cpu_has_vmx_ept_1g_page(void)
931 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
934 static inline bool cpu_has_vmx_ept_4levels(void)
936 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
939 static inline bool cpu_has_vmx_ept_ad_bits(void)
941 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
944 static inline bool cpu_has_vmx_invept_context(void)
946 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
949 static inline bool cpu_has_vmx_invept_global(void)
951 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
954 static inline bool cpu_has_vmx_invvpid_single(void)
956 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
959 static inline bool cpu_has_vmx_invvpid_global(void)
961 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
964 static inline bool cpu_has_vmx_ept(void)
966 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
967 SECONDARY_EXEC_ENABLE_EPT
;
970 static inline bool cpu_has_vmx_unrestricted_guest(void)
972 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
973 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
976 static inline bool cpu_has_vmx_ple(void)
978 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
982 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
984 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
987 static inline bool cpu_has_vmx_vpid(void)
989 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
990 SECONDARY_EXEC_ENABLE_VPID
;
993 static inline bool cpu_has_vmx_rdtscp(void)
995 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
996 SECONDARY_EXEC_RDTSCP
;
999 static inline bool cpu_has_vmx_invpcid(void)
1001 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1002 SECONDARY_EXEC_ENABLE_INVPCID
;
1005 static inline bool cpu_has_virtual_nmis(void)
1007 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1010 static inline bool cpu_has_vmx_wbinvd_exit(void)
1012 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1013 SECONDARY_EXEC_WBINVD_EXITING
;
1016 static inline bool cpu_has_vmx_shadow_vmcs(void)
1019 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1024 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1025 SECONDARY_EXEC_SHADOW_VMCS
;
1028 static inline bool report_flexpriority(void)
1030 return flexpriority_enabled
;
1033 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1035 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1038 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1040 return (vmcs12
->cpu_based_vm_exec_control
&
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1042 (vmcs12
->secondary_vm_exec_control
& bit
);
1045 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1047 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1050 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1052 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1055 static inline bool is_exception(u32 intr_info
)
1057 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1058 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1061 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1063 unsigned long exit_qualification
);
1064 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1065 struct vmcs12
*vmcs12
,
1066 u32 reason
, unsigned long qualification
);
1068 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1072 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1073 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1078 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1084 } operand
= { vpid
, 0, gva
};
1086 asm volatile (__ex(ASM_VMX_INVVPID
)
1087 /* CF==1 or ZF==1 --> rc = -1 */
1088 "; ja 1f ; ud2 ; 1:"
1089 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1092 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1096 } operand
= {eptp
, gpa
};
1098 asm volatile (__ex(ASM_VMX_INVEPT
)
1099 /* CF==1 or ZF==1 --> rc = -1 */
1100 "; ja 1f ; ud2 ; 1:\n"
1101 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1104 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1108 i
= __find_msr_index(vmx
, msr
);
1110 return &vmx
->guest_msrs
[i
];
1114 static void vmcs_clear(struct vmcs
*vmcs
)
1116 u64 phys_addr
= __pa(vmcs
);
1119 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1120 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1123 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1127 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1129 vmcs_clear(loaded_vmcs
->vmcs
);
1130 loaded_vmcs
->cpu
= -1;
1131 loaded_vmcs
->launched
= 0;
1134 static void vmcs_load(struct vmcs
*vmcs
)
1136 u64 phys_addr
= __pa(vmcs
);
1139 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1140 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1143 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1149 * This bitmap is used to indicate whether the vmclear
1150 * operation is enabled on all cpus. All disabled by
1153 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1155 static inline void crash_enable_local_vmclear(int cpu
)
1157 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1160 static inline void crash_disable_local_vmclear(int cpu
)
1162 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1165 static inline int crash_local_vmclear_enabled(int cpu
)
1167 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1170 static void crash_vmclear_local_loaded_vmcss(void)
1172 int cpu
= raw_smp_processor_id();
1173 struct loaded_vmcs
*v
;
1175 if (!crash_local_vmclear_enabled(cpu
))
1178 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1179 loaded_vmcss_on_cpu_link
)
1180 vmcs_clear(v
->vmcs
);
1183 static inline void crash_enable_local_vmclear(int cpu
) { }
1184 static inline void crash_disable_local_vmclear(int cpu
) { }
1185 #endif /* CONFIG_KEXEC */
1187 static void __loaded_vmcs_clear(void *arg
)
1189 struct loaded_vmcs
*loaded_vmcs
= arg
;
1190 int cpu
= raw_smp_processor_id();
1192 if (loaded_vmcs
->cpu
!= cpu
)
1193 return; /* vcpu migration can race with cpu offline */
1194 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1195 per_cpu(current_vmcs
, cpu
) = NULL
;
1196 crash_disable_local_vmclear(cpu
);
1197 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1200 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1201 * is before setting loaded_vmcs->vcpu to -1 which is done in
1202 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1203 * then adds the vmcs into percpu list before it is deleted.
1207 loaded_vmcs_init(loaded_vmcs
);
1208 crash_enable_local_vmclear(cpu
);
1211 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1213 int cpu
= loaded_vmcs
->cpu
;
1216 smp_call_function_single(cpu
,
1217 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1220 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1225 if (cpu_has_vmx_invvpid_single())
1226 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1229 static inline void vpid_sync_vcpu_global(void)
1231 if (cpu_has_vmx_invvpid_global())
1232 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1235 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1237 if (cpu_has_vmx_invvpid_single())
1238 vpid_sync_vcpu_single(vmx
);
1240 vpid_sync_vcpu_global();
1243 static inline void ept_sync_global(void)
1245 if (cpu_has_vmx_invept_global())
1246 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1249 static inline void ept_sync_context(u64 eptp
)
1252 if (cpu_has_vmx_invept_context())
1253 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1259 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1261 unsigned long value
;
1263 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1264 : "=a"(value
) : "d"(field
) : "cc");
1268 static __always_inline u16
vmcs_read16(unsigned long field
)
1270 return vmcs_readl(field
);
1273 static __always_inline u32
vmcs_read32(unsigned long field
)
1275 return vmcs_readl(field
);
1278 static __always_inline u64
vmcs_read64(unsigned long field
)
1280 #ifdef CONFIG_X86_64
1281 return vmcs_readl(field
);
1283 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1287 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1289 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1290 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1294 static void vmcs_writel(unsigned long field
, unsigned long value
)
1298 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1299 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1300 if (unlikely(error
))
1301 vmwrite_error(field
, value
);
1304 static void vmcs_write16(unsigned long field
, u16 value
)
1306 vmcs_writel(field
, value
);
1309 static void vmcs_write32(unsigned long field
, u32 value
)
1311 vmcs_writel(field
, value
);
1314 static void vmcs_write64(unsigned long field
, u64 value
)
1316 vmcs_writel(field
, value
);
1317 #ifndef CONFIG_X86_64
1319 vmcs_writel(field
+1, value
>> 32);
1323 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1325 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1328 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1330 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1333 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1335 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1336 vmx
->vm_entry_controls_shadow
= val
;
1339 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1341 if (vmx
->vm_entry_controls_shadow
!= val
)
1342 vm_entry_controls_init(vmx
, val
);
1345 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1347 return vmx
->vm_entry_controls_shadow
;
1351 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1353 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1356 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1358 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1361 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1363 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1364 vmx
->vm_exit_controls_shadow
= val
;
1367 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1369 if (vmx
->vm_exit_controls_shadow
!= val
)
1370 vm_exit_controls_init(vmx
, val
);
1373 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1375 return vmx
->vm_exit_controls_shadow
;
1379 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1381 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1384 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1386 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1389 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1391 vmx
->segment_cache
.bitmask
= 0;
1394 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1398 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1400 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1401 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1402 vmx
->segment_cache
.bitmask
= 0;
1404 ret
= vmx
->segment_cache
.bitmask
& mask
;
1405 vmx
->segment_cache
.bitmask
|= mask
;
1409 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1411 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1413 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1414 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1418 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1420 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1422 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1423 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1427 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1429 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1431 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1432 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1436 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1438 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1440 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1441 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1445 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1449 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1450 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1451 if ((vcpu
->guest_debug
&
1452 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1453 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1454 eb
|= 1u << BP_VECTOR
;
1455 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1458 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1459 if (vcpu
->fpu_active
)
1460 eb
&= ~(1u << NM_VECTOR
);
1462 /* When we are running a nested L2 guest and L1 specified for it a
1463 * certain exception bitmap, we must trap the same exceptions and pass
1464 * them to L1. When running L2, we will only handle the exceptions
1465 * specified above if L1 did not want them.
1467 if (is_guest_mode(vcpu
))
1468 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1470 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1473 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1474 unsigned long entry
, unsigned long exit
)
1476 vm_entry_controls_clearbit(vmx
, entry
);
1477 vm_exit_controls_clearbit(vmx
, exit
);
1480 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1483 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1487 if (cpu_has_load_ia32_efer
) {
1488 clear_atomic_switch_msr_special(vmx
,
1489 VM_ENTRY_LOAD_IA32_EFER
,
1490 VM_EXIT_LOAD_IA32_EFER
);
1494 case MSR_CORE_PERF_GLOBAL_CTRL
:
1495 if (cpu_has_load_perf_global_ctrl
) {
1496 clear_atomic_switch_msr_special(vmx
,
1497 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1498 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1504 for (i
= 0; i
< m
->nr
; ++i
)
1505 if (m
->guest
[i
].index
== msr
)
1511 m
->guest
[i
] = m
->guest
[m
->nr
];
1512 m
->host
[i
] = m
->host
[m
->nr
];
1513 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1514 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1517 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1518 unsigned long entry
, unsigned long exit
,
1519 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1520 u64 guest_val
, u64 host_val
)
1522 vmcs_write64(guest_val_vmcs
, guest_val
);
1523 vmcs_write64(host_val_vmcs
, host_val
);
1524 vm_entry_controls_setbit(vmx
, entry
);
1525 vm_exit_controls_setbit(vmx
, exit
);
1528 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1529 u64 guest_val
, u64 host_val
)
1532 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1536 if (cpu_has_load_ia32_efer
) {
1537 add_atomic_switch_msr_special(vmx
,
1538 VM_ENTRY_LOAD_IA32_EFER
,
1539 VM_EXIT_LOAD_IA32_EFER
,
1542 guest_val
, host_val
);
1546 case MSR_CORE_PERF_GLOBAL_CTRL
:
1547 if (cpu_has_load_perf_global_ctrl
) {
1548 add_atomic_switch_msr_special(vmx
,
1549 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1550 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1551 GUEST_IA32_PERF_GLOBAL_CTRL
,
1552 HOST_IA32_PERF_GLOBAL_CTRL
,
1553 guest_val
, host_val
);
1559 for (i
= 0; i
< m
->nr
; ++i
)
1560 if (m
->guest
[i
].index
== msr
)
1563 if (i
== NR_AUTOLOAD_MSRS
) {
1564 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1565 "Can't add msr %x\n", msr
);
1567 } else if (i
== m
->nr
) {
1569 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1570 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1573 m
->guest
[i
].index
= msr
;
1574 m
->guest
[i
].value
= guest_val
;
1575 m
->host
[i
].index
= msr
;
1576 m
->host
[i
].value
= host_val
;
1579 static void reload_tss(void)
1582 * VT restores TR but not its size. Useless.
1584 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1585 struct desc_struct
*descs
;
1587 descs
= (void *)gdt
->address
;
1588 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1592 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1597 guest_efer
= vmx
->vcpu
.arch
.efer
;
1600 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1603 ignore_bits
= EFER_NX
| EFER_SCE
;
1604 #ifdef CONFIG_X86_64
1605 ignore_bits
|= EFER_LMA
| EFER_LME
;
1606 /* SCE is meaningful only in long mode on Intel */
1607 if (guest_efer
& EFER_LMA
)
1608 ignore_bits
&= ~(u64
)EFER_SCE
;
1610 guest_efer
&= ~ignore_bits
;
1611 guest_efer
|= host_efer
& ignore_bits
;
1612 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1613 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1615 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1616 /* On ept, can't emulate nx, and must switch nx atomically */
1617 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1618 guest_efer
= vmx
->vcpu
.arch
.efer
;
1619 if (!(guest_efer
& EFER_LMA
))
1620 guest_efer
&= ~EFER_LME
;
1621 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1628 static unsigned long segment_base(u16 selector
)
1630 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1631 struct desc_struct
*d
;
1632 unsigned long table_base
;
1635 if (!(selector
& ~3))
1638 table_base
= gdt
->address
;
1640 if (selector
& 4) { /* from ldt */
1641 u16 ldt_selector
= kvm_read_ldt();
1643 if (!(ldt_selector
& ~3))
1646 table_base
= segment_base(ldt_selector
);
1648 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1649 v
= get_desc_base(d
);
1650 #ifdef CONFIG_X86_64
1651 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1652 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1657 static inline unsigned long kvm_read_tr_base(void)
1660 asm("str %0" : "=g"(tr
));
1661 return segment_base(tr
);
1664 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1666 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1669 if (vmx
->host_state
.loaded
)
1672 vmx
->host_state
.loaded
= 1;
1674 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1675 * allow segment selectors with cpl > 0 or ti == 1.
1677 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1678 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1679 savesegment(fs
, vmx
->host_state
.fs_sel
);
1680 if (!(vmx
->host_state
.fs_sel
& 7)) {
1681 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1682 vmx
->host_state
.fs_reload_needed
= 0;
1684 vmcs_write16(HOST_FS_SELECTOR
, 0);
1685 vmx
->host_state
.fs_reload_needed
= 1;
1687 savesegment(gs
, vmx
->host_state
.gs_sel
);
1688 if (!(vmx
->host_state
.gs_sel
& 7))
1689 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1691 vmcs_write16(HOST_GS_SELECTOR
, 0);
1692 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1695 #ifdef CONFIG_X86_64
1696 savesegment(ds
, vmx
->host_state
.ds_sel
);
1697 savesegment(es
, vmx
->host_state
.es_sel
);
1700 #ifdef CONFIG_X86_64
1701 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1702 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1704 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1705 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1708 #ifdef CONFIG_X86_64
1709 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1710 if (is_long_mode(&vmx
->vcpu
))
1711 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1713 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1714 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1715 vmx
->guest_msrs
[i
].data
,
1716 vmx
->guest_msrs
[i
].mask
);
1719 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1721 if (!vmx
->host_state
.loaded
)
1724 ++vmx
->vcpu
.stat
.host_state_reload
;
1725 vmx
->host_state
.loaded
= 0;
1726 #ifdef CONFIG_X86_64
1727 if (is_long_mode(&vmx
->vcpu
))
1728 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1730 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1731 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1732 #ifdef CONFIG_X86_64
1733 load_gs_index(vmx
->host_state
.gs_sel
);
1735 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1738 if (vmx
->host_state
.fs_reload_needed
)
1739 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1740 #ifdef CONFIG_X86_64
1741 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1742 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1743 loadsegment(es
, vmx
->host_state
.es_sel
);
1747 #ifdef CONFIG_X86_64
1748 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1751 * If the FPU is not active (through the host task or
1752 * the guest vcpu), then restore the cr0.TS bit.
1754 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1756 load_gdt(&__get_cpu_var(host_gdt
));
1759 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1762 __vmx_load_host_state(vmx
);
1767 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1768 * vcpu mutex is already taken.
1770 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1773 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1776 kvm_cpu_vmxon(phys_addr
);
1777 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1778 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1780 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1781 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1782 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1785 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1786 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1787 unsigned long sysenter_esp
;
1789 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1790 local_irq_disable();
1791 crash_disable_local_vmclear(cpu
);
1794 * Read loaded_vmcs->cpu should be before fetching
1795 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1796 * See the comments in __loaded_vmcs_clear().
1800 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1801 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1802 crash_enable_local_vmclear(cpu
);
1806 * Linux uses per-cpu TSS and GDT, so set these when switching
1809 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1810 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1812 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1813 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1814 vmx
->loaded_vmcs
->cpu
= cpu
;
1818 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1820 __vmx_load_host_state(to_vmx(vcpu
));
1821 if (!vmm_exclusive
) {
1822 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1828 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1832 if (vcpu
->fpu_active
)
1834 vcpu
->fpu_active
= 1;
1835 cr0
= vmcs_readl(GUEST_CR0
);
1836 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1837 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1838 vmcs_writel(GUEST_CR0
, cr0
);
1839 update_exception_bitmap(vcpu
);
1840 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1841 if (is_guest_mode(vcpu
))
1842 vcpu
->arch
.cr0_guest_owned_bits
&=
1843 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1844 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1847 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1850 * Return the cr0 value that a nested guest would read. This is a combination
1851 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1852 * its hypervisor (cr0_read_shadow).
1854 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1856 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1857 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1859 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1861 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1862 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1865 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1867 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1868 * set this *before* calling this function.
1870 vmx_decache_cr0_guest_bits(vcpu
);
1871 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1872 update_exception_bitmap(vcpu
);
1873 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1874 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1875 if (is_guest_mode(vcpu
)) {
1877 * L1's specified read shadow might not contain the TS bit,
1878 * so now that we turned on shadowing of this bit, we need to
1879 * set this bit of the shadow. Like in nested_vmx_run we need
1880 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1881 * up-to-date here because we just decached cr0.TS (and we'll
1882 * only update vmcs12->guest_cr0 on nested exit).
1884 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1885 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1886 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1887 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1889 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1892 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1894 unsigned long rflags
, save_rflags
;
1896 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1897 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1898 rflags
= vmcs_readl(GUEST_RFLAGS
);
1899 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1900 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1901 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1902 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1904 to_vmx(vcpu
)->rflags
= rflags
;
1906 return to_vmx(vcpu
)->rflags
;
1909 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1911 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1912 to_vmx(vcpu
)->rflags
= rflags
;
1913 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1914 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1915 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1917 vmcs_writel(GUEST_RFLAGS
, rflags
);
1920 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1922 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1925 if (interruptibility
& GUEST_INTR_STATE_STI
)
1926 ret
|= KVM_X86_SHADOW_INT_STI
;
1927 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1928 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1933 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1935 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1936 u32 interruptibility
= interruptibility_old
;
1938 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1940 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1941 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1942 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1943 interruptibility
|= GUEST_INTR_STATE_STI
;
1945 if ((interruptibility
!= interruptibility_old
))
1946 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1949 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1953 rip
= kvm_rip_read(vcpu
);
1954 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1955 kvm_rip_write(vcpu
, rip
);
1957 /* skipping an emulated instruction also counts */
1958 vmx_set_interrupt_shadow(vcpu
, 0);
1962 * KVM wants to inject page-faults which it got to the guest. This function
1963 * checks whether in a nested guest, we need to inject them to L1 or L2.
1965 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1967 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1969 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1972 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
1973 vmcs_read32(VM_EXIT_INTR_INFO
),
1974 vmcs_readl(EXIT_QUALIFICATION
));
1978 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1979 bool has_error_code
, u32 error_code
,
1982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1983 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1985 if (!reinject
&& is_guest_mode(vcpu
) &&
1986 nested_vmx_check_exception(vcpu
, nr
))
1989 if (has_error_code
) {
1990 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1991 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1994 if (vmx
->rmode
.vm86_active
) {
1996 if (kvm_exception_is_soft(nr
))
1997 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1998 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1999 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2003 if (kvm_exception_is_soft(nr
)) {
2004 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2005 vmx
->vcpu
.arch
.event_exit_inst_len
);
2006 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2008 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2010 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2013 static bool vmx_rdtscp_supported(void)
2015 return cpu_has_vmx_rdtscp();
2018 static bool vmx_invpcid_supported(void)
2020 return cpu_has_vmx_invpcid() && enable_ept
;
2024 * Swap MSR entry in host/guest MSR entry array.
2026 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2028 struct shared_msr_entry tmp
;
2030 tmp
= vmx
->guest_msrs
[to
];
2031 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2032 vmx
->guest_msrs
[from
] = tmp
;
2035 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2037 unsigned long *msr_bitmap
;
2039 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2040 if (is_long_mode(vcpu
))
2041 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2043 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2045 if (is_long_mode(vcpu
))
2046 msr_bitmap
= vmx_msr_bitmap_longmode
;
2048 msr_bitmap
= vmx_msr_bitmap_legacy
;
2051 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2055 * Set up the vmcs to automatically save and restore system
2056 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2057 * mode, as fiddling with msrs is very expensive.
2059 static void setup_msrs(struct vcpu_vmx
*vmx
)
2061 int save_nmsrs
, index
;
2064 #ifdef CONFIG_X86_64
2065 if (is_long_mode(&vmx
->vcpu
)) {
2066 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2068 move_msr_up(vmx
, index
, save_nmsrs
++);
2069 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2071 move_msr_up(vmx
, index
, save_nmsrs
++);
2072 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2074 move_msr_up(vmx
, index
, save_nmsrs
++);
2075 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2076 if (index
>= 0 && vmx
->rdtscp_enabled
)
2077 move_msr_up(vmx
, index
, save_nmsrs
++);
2079 * MSR_STAR is only needed on long mode guests, and only
2080 * if efer.sce is enabled.
2082 index
= __find_msr_index(vmx
, MSR_STAR
);
2083 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2084 move_msr_up(vmx
, index
, save_nmsrs
++);
2087 index
= __find_msr_index(vmx
, MSR_EFER
);
2088 if (index
>= 0 && update_transition_efer(vmx
, index
))
2089 move_msr_up(vmx
, index
, save_nmsrs
++);
2091 vmx
->save_nmsrs
= save_nmsrs
;
2093 if (cpu_has_vmx_msr_bitmap())
2094 vmx_set_msr_bitmap(&vmx
->vcpu
);
2098 * reads and returns guest's timestamp counter "register"
2099 * guest_tsc = host_tsc + tsc_offset -- 21.3
2101 static u64
guest_read_tsc(void)
2103 u64 host_tsc
, tsc_offset
;
2106 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2107 return host_tsc
+ tsc_offset
;
2111 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2112 * counter, even if a nested guest (L2) is currently running.
2114 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2118 tsc_offset
= is_guest_mode(vcpu
) ?
2119 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2120 vmcs_read64(TSC_OFFSET
);
2121 return host_tsc
+ tsc_offset
;
2125 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2126 * software catchup for faster rates on slower CPUs.
2128 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2133 if (user_tsc_khz
> tsc_khz
) {
2134 vcpu
->arch
.tsc_catchup
= 1;
2135 vcpu
->arch
.tsc_always_catchup
= 1;
2137 WARN(1, "user requested TSC rate below hardware speed\n");
2140 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2142 return vmcs_read64(TSC_OFFSET
);
2146 * writes 'offset' into guest's timestamp counter offset register
2148 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2150 if (is_guest_mode(vcpu
)) {
2152 * We're here if L1 chose not to trap WRMSR to TSC. According
2153 * to the spec, this should set L1's TSC; The offset that L1
2154 * set for L2 remains unchanged, and still needs to be added
2155 * to the newly set TSC to get L2's TSC.
2157 struct vmcs12
*vmcs12
;
2158 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2159 /* recalculate vmcs02.TSC_OFFSET: */
2160 vmcs12
= get_vmcs12(vcpu
);
2161 vmcs_write64(TSC_OFFSET
, offset
+
2162 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2163 vmcs12
->tsc_offset
: 0));
2165 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2166 vmcs_read64(TSC_OFFSET
), offset
);
2167 vmcs_write64(TSC_OFFSET
, offset
);
2171 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2173 u64 offset
= vmcs_read64(TSC_OFFSET
);
2175 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2176 if (is_guest_mode(vcpu
)) {
2177 /* Even when running L2, the adjustment needs to apply to L1 */
2178 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2180 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2181 offset
+ adjustment
);
2184 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2186 return target_tsc
- native_read_tsc();
2189 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2191 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2192 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2196 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2197 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2198 * all guests if the "nested" module option is off, and can also be disabled
2199 * for a single guest by disabling its VMX cpuid bit.
2201 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2203 return nested
&& guest_cpuid_has_vmx(vcpu
);
2207 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2208 * returned for the various VMX controls MSRs when nested VMX is enabled.
2209 * The same values should also be used to verify that vmcs12 control fields are
2210 * valid during nested entry from L1 to L2.
2211 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2212 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2213 * bit in the high half is on if the corresponding bit in the control field
2214 * may be on. See also vmx_control_verify().
2215 * TODO: allow these variables to be modified (downgraded) by module options
2218 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2219 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2220 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2221 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2222 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2223 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2224 static u32 nested_vmx_ept_caps
;
2225 static __init
void nested_vmx_setup_ctls_msrs(void)
2228 * Note that as a general rule, the high half of the MSRs (bits in
2229 * the control fields which may be 1) should be initialized by the
2230 * intersection of the underlying hardware's MSR (i.e., features which
2231 * can be supported) and the list of features we want to expose -
2232 * because they are known to be properly supported in our code.
2233 * Also, usually, the low half of the MSRs (bits which must be 1) can
2234 * be set to 0, meaning that L1 may turn off any of these bits. The
2235 * reason is that if one of these bits is necessary, it will appear
2236 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2237 * fields of vmcs01 and vmcs02, will turn these bits off - and
2238 * nested_vmx_exit_handled() will not pass related exits to L1.
2239 * These rules have exceptions below.
2242 /* pin-based controls */
2243 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2244 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2246 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2247 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2249 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2250 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2251 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2252 PIN_BASED_VMX_PREEMPTION_TIMER
;
2253 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2257 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2260 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2261 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2262 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2263 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2264 nested_vmx_exit_ctls_high
&=
2265 #ifdef CONFIG_X86_64
2266 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2268 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
|
2269 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2270 if (!(nested_vmx_pinbased_ctls_high
& PIN_BASED_VMX_PREEMPTION_TIMER
) ||
2271 !(nested_vmx_exit_ctls_high
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)) {
2272 nested_vmx_exit_ctls_high
&= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2273 nested_vmx_pinbased_ctls_high
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2275 nested_vmx_exit_ctls_high
|= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2276 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
);
2278 /* entry controls */
2279 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2280 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2281 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2282 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2283 nested_vmx_entry_ctls_high
&=
2284 #ifdef CONFIG_X86_64
2285 VM_ENTRY_IA32E_MODE
|
2287 VM_ENTRY_LOAD_IA32_PAT
;
2288 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2289 VM_ENTRY_LOAD_IA32_EFER
);
2291 /* cpu-based controls */
2292 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2293 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2294 nested_vmx_procbased_ctls_low
= 0;
2295 nested_vmx_procbased_ctls_high
&=
2296 CPU_BASED_VIRTUAL_INTR_PENDING
|
2297 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2298 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2299 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2300 CPU_BASED_CR3_STORE_EXITING
|
2301 #ifdef CONFIG_X86_64
2302 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2304 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2305 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2306 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2307 CPU_BASED_PAUSE_EXITING
|
2308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2310 * We can allow some features even when not supported by the
2311 * hardware. For example, L1 can specify an MSR bitmap - and we
2312 * can use it to avoid exits to L1 - even when L0 runs L2
2313 * without MSR bitmaps.
2315 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2317 /* secondary cpu-based controls */
2318 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2319 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2320 nested_vmx_secondary_ctls_low
= 0;
2321 nested_vmx_secondary_ctls_high
&=
2322 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2323 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2324 SECONDARY_EXEC_WBINVD_EXITING
;
2327 /* nested EPT: emulate EPT also to L1 */
2328 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2329 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2330 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2332 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2334 * Since invept is completely emulated we support both global
2335 * and context invalidation independent of what host cpu
2338 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2339 VMX_EPT_EXTENT_CONTEXT_BIT
;
2341 nested_vmx_ept_caps
= 0;
2343 /* miscellaneous data */
2344 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2345 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2346 VMX_MISC_SAVE_EFER_LMA
;
2347 nested_vmx_misc_low
|= VMX_MISC_ACTIVITY_HLT
;
2348 nested_vmx_misc_high
= 0;
2351 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2354 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2356 return ((control
& high
) | low
) == control
;
2359 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2361 return low
| ((u64
)high
<< 32);
2364 /* Returns 0 on success, non-0 otherwise. */
2365 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2367 switch (msr_index
) {
2368 case MSR_IA32_VMX_BASIC
:
2370 * This MSR reports some information about VMX support. We
2371 * should return information about the VMX we emulate for the
2372 * guest, and the VMCS structure we give it - not about the
2373 * VMX support of the underlying hardware.
2375 *pdata
= VMCS12_REVISION
|
2376 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2377 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2379 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2380 case MSR_IA32_VMX_PINBASED_CTLS
:
2381 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2382 nested_vmx_pinbased_ctls_high
);
2384 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2385 case MSR_IA32_VMX_PROCBASED_CTLS
:
2386 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2387 nested_vmx_procbased_ctls_high
);
2389 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2390 case MSR_IA32_VMX_EXIT_CTLS
:
2391 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2392 nested_vmx_exit_ctls_high
);
2394 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2395 case MSR_IA32_VMX_ENTRY_CTLS
:
2396 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2397 nested_vmx_entry_ctls_high
);
2399 case MSR_IA32_VMX_MISC
:
2400 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2401 nested_vmx_misc_high
);
2404 * These MSRs specify bits which the guest must keep fixed (on or off)
2405 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2406 * We picked the standard core2 setting.
2408 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2409 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2410 case MSR_IA32_VMX_CR0_FIXED0
:
2411 *pdata
= VMXON_CR0_ALWAYSON
;
2413 case MSR_IA32_VMX_CR0_FIXED1
:
2416 case MSR_IA32_VMX_CR4_FIXED0
:
2417 *pdata
= VMXON_CR4_ALWAYSON
;
2419 case MSR_IA32_VMX_CR4_FIXED1
:
2422 case MSR_IA32_VMX_VMCS_ENUM
:
2425 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2426 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2427 nested_vmx_secondary_ctls_high
);
2429 case MSR_IA32_VMX_EPT_VPID_CAP
:
2430 /* Currently, no nested vpid support */
2431 *pdata
= nested_vmx_ept_caps
;
2441 * Reads an msr value (of 'msr_index') into 'pdata'.
2442 * Returns 0 on success, non-0 otherwise.
2443 * Assumes vcpu_load() was already called.
2445 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2448 struct shared_msr_entry
*msr
;
2451 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2455 switch (msr_index
) {
2456 #ifdef CONFIG_X86_64
2458 data
= vmcs_readl(GUEST_FS_BASE
);
2461 data
= vmcs_readl(GUEST_GS_BASE
);
2463 case MSR_KERNEL_GS_BASE
:
2464 vmx_load_host_state(to_vmx(vcpu
));
2465 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2469 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2471 data
= guest_read_tsc();
2473 case MSR_IA32_SYSENTER_CS
:
2474 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2476 case MSR_IA32_SYSENTER_EIP
:
2477 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2479 case MSR_IA32_SYSENTER_ESP
:
2480 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2482 case MSR_IA32_FEATURE_CONTROL
:
2483 if (!nested_vmx_allowed(vcpu
))
2485 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2487 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2488 if (!nested_vmx_allowed(vcpu
))
2490 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2492 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2494 /* Otherwise falls through */
2496 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2501 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2508 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2511 * Writes msr value into into the appropriate "register".
2512 * Returns 0 on success, non-0 otherwise.
2513 * Assumes vcpu_load() was already called.
2515 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2517 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2518 struct shared_msr_entry
*msr
;
2520 u32 msr_index
= msr_info
->index
;
2521 u64 data
= msr_info
->data
;
2523 switch (msr_index
) {
2525 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2527 #ifdef CONFIG_X86_64
2529 vmx_segment_cache_clear(vmx
);
2530 vmcs_writel(GUEST_FS_BASE
, data
);
2533 vmx_segment_cache_clear(vmx
);
2534 vmcs_writel(GUEST_GS_BASE
, data
);
2536 case MSR_KERNEL_GS_BASE
:
2537 vmx_load_host_state(vmx
);
2538 vmx
->msr_guest_kernel_gs_base
= data
;
2541 case MSR_IA32_SYSENTER_CS
:
2542 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2544 case MSR_IA32_SYSENTER_EIP
:
2545 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2547 case MSR_IA32_SYSENTER_ESP
:
2548 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2551 kvm_write_tsc(vcpu
, msr_info
);
2553 case MSR_IA32_CR_PAT
:
2554 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2555 vmcs_write64(GUEST_IA32_PAT
, data
);
2556 vcpu
->arch
.pat
= data
;
2559 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2561 case MSR_IA32_TSC_ADJUST
:
2562 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2564 case MSR_IA32_FEATURE_CONTROL
:
2565 if (!nested_vmx_allowed(vcpu
) ||
2566 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2567 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2569 vmx
->nested
.msr_ia32_feature_control
= data
;
2570 if (msr_info
->host_initiated
&& data
== 0)
2571 vmx_leave_nested(vcpu
);
2573 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2574 return 1; /* they are read-only */
2576 if (!vmx
->rdtscp_enabled
)
2578 /* Check reserved bit, higher 32 bits should be zero */
2579 if ((data
>> 32) != 0)
2581 /* Otherwise falls through */
2583 msr
= find_msr_entry(vmx
, msr_index
);
2586 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2588 kvm_set_shared_msr(msr
->index
, msr
->data
,
2594 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2600 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2602 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2605 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2608 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2610 case VCPU_EXREG_PDPTR
:
2612 ept_save_pdptrs(vcpu
);
2619 static __init
int cpu_has_kvm_support(void)
2621 return cpu_has_vmx();
2624 static __init
int vmx_disabled_by_bios(void)
2628 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2629 if (msr
& FEATURE_CONTROL_LOCKED
) {
2630 /* launched w/ TXT and VMX disabled */
2631 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2634 /* launched w/o TXT and VMX only enabled w/ TXT */
2635 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2636 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2637 && !tboot_enabled()) {
2638 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2639 "activate TXT before enabling KVM\n");
2642 /* launched w/o TXT and VMX disabled */
2643 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2644 && !tboot_enabled())
2651 static void kvm_cpu_vmxon(u64 addr
)
2653 asm volatile (ASM_VMX_VMXON_RAX
2654 : : "a"(&addr
), "m"(addr
)
2658 static int hardware_enable(void *garbage
)
2660 int cpu
= raw_smp_processor_id();
2661 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2664 if (read_cr4() & X86_CR4_VMXE
)
2667 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2670 * Now we can enable the vmclear operation in kdump
2671 * since the loaded_vmcss_on_cpu list on this cpu
2672 * has been initialized.
2674 * Though the cpu is not in VMX operation now, there
2675 * is no problem to enable the vmclear operation
2676 * for the loaded_vmcss_on_cpu list is empty!
2678 crash_enable_local_vmclear(cpu
);
2680 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2682 test_bits
= FEATURE_CONTROL_LOCKED
;
2683 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2684 if (tboot_enabled())
2685 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2687 if ((old
& test_bits
) != test_bits
) {
2688 /* enable and lock */
2689 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2691 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2693 if (vmm_exclusive
) {
2694 kvm_cpu_vmxon(phys_addr
);
2698 native_store_gdt(&__get_cpu_var(host_gdt
));
2703 static void vmclear_local_loaded_vmcss(void)
2705 int cpu
= raw_smp_processor_id();
2706 struct loaded_vmcs
*v
, *n
;
2708 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2709 loaded_vmcss_on_cpu_link
)
2710 __loaded_vmcs_clear(v
);
2714 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2717 static void kvm_cpu_vmxoff(void)
2719 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2722 static void hardware_disable(void *garbage
)
2724 if (vmm_exclusive
) {
2725 vmclear_local_loaded_vmcss();
2728 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2731 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2732 u32 msr
, u32
*result
)
2734 u32 vmx_msr_low
, vmx_msr_high
;
2735 u32 ctl
= ctl_min
| ctl_opt
;
2737 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2739 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2740 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2742 /* Ensure minimum (required) set of control bits are supported. */
2750 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2752 u32 vmx_msr_low
, vmx_msr_high
;
2754 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2755 return vmx_msr_high
& ctl
;
2758 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2760 u32 vmx_msr_low
, vmx_msr_high
;
2761 u32 min
, opt
, min2
, opt2
;
2762 u32 _pin_based_exec_control
= 0;
2763 u32 _cpu_based_exec_control
= 0;
2764 u32 _cpu_based_2nd_exec_control
= 0;
2765 u32 _vmexit_control
= 0;
2766 u32 _vmentry_control
= 0;
2768 min
= CPU_BASED_HLT_EXITING
|
2769 #ifdef CONFIG_X86_64
2770 CPU_BASED_CR8_LOAD_EXITING
|
2771 CPU_BASED_CR8_STORE_EXITING
|
2773 CPU_BASED_CR3_LOAD_EXITING
|
2774 CPU_BASED_CR3_STORE_EXITING
|
2775 CPU_BASED_USE_IO_BITMAPS
|
2776 CPU_BASED_MOV_DR_EXITING
|
2777 CPU_BASED_USE_TSC_OFFSETING
|
2778 CPU_BASED_MWAIT_EXITING
|
2779 CPU_BASED_MONITOR_EXITING
|
2780 CPU_BASED_INVLPG_EXITING
|
2781 CPU_BASED_RDPMC_EXITING
;
2783 opt
= CPU_BASED_TPR_SHADOW
|
2784 CPU_BASED_USE_MSR_BITMAPS
|
2785 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2786 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2787 &_cpu_based_exec_control
) < 0)
2789 #ifdef CONFIG_X86_64
2790 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2791 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2792 ~CPU_BASED_CR8_STORE_EXITING
;
2794 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2796 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2797 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2798 SECONDARY_EXEC_WBINVD_EXITING
|
2799 SECONDARY_EXEC_ENABLE_VPID
|
2800 SECONDARY_EXEC_ENABLE_EPT
|
2801 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2802 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2803 SECONDARY_EXEC_RDTSCP
|
2804 SECONDARY_EXEC_ENABLE_INVPCID
|
2805 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2806 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2807 SECONDARY_EXEC_SHADOW_VMCS
;
2808 if (adjust_vmx_controls(min2
, opt2
,
2809 MSR_IA32_VMX_PROCBASED_CTLS2
,
2810 &_cpu_based_2nd_exec_control
) < 0)
2813 #ifndef CONFIG_X86_64
2814 if (!(_cpu_based_2nd_exec_control
&
2815 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2816 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2819 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2820 _cpu_based_2nd_exec_control
&= ~(
2821 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2822 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2823 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2825 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2826 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2828 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2829 CPU_BASED_CR3_STORE_EXITING
|
2830 CPU_BASED_INVLPG_EXITING
);
2831 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2832 vmx_capability
.ept
, vmx_capability
.vpid
);
2836 #ifdef CONFIG_X86_64
2837 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2839 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2840 VM_EXIT_ACK_INTR_ON_EXIT
;
2841 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2842 &_vmexit_control
) < 0)
2845 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2846 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2847 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2848 &_pin_based_exec_control
) < 0)
2851 if (!(_cpu_based_2nd_exec_control
&
2852 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2853 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2854 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2857 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2858 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2859 &_vmentry_control
) < 0)
2862 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2864 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2865 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2868 #ifdef CONFIG_X86_64
2869 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2870 if (vmx_msr_high
& (1u<<16))
2874 /* Require Write-Back (WB) memory type for VMCS accesses. */
2875 if (((vmx_msr_high
>> 18) & 15) != 6)
2878 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2879 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2880 vmcs_conf
->revision_id
= vmx_msr_low
;
2882 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2883 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2884 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2885 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2886 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2888 cpu_has_load_ia32_efer
=
2889 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2890 VM_ENTRY_LOAD_IA32_EFER
)
2891 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2892 VM_EXIT_LOAD_IA32_EFER
);
2894 cpu_has_load_perf_global_ctrl
=
2895 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2896 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2897 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2898 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2901 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2902 * but due to arrata below it can't be used. Workaround is to use
2903 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2905 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2910 * BC86,AAY89,BD102 (model 44)
2914 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2915 switch (boot_cpu_data
.x86_model
) {
2921 cpu_has_load_perf_global_ctrl
= false;
2922 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2923 "does not work properly. Using workaround\n");
2933 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2935 int node
= cpu_to_node(cpu
);
2939 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2942 vmcs
= page_address(pages
);
2943 memset(vmcs
, 0, vmcs_config
.size
);
2944 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2948 static struct vmcs
*alloc_vmcs(void)
2950 return alloc_vmcs_cpu(raw_smp_processor_id());
2953 static void free_vmcs(struct vmcs
*vmcs
)
2955 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2959 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2961 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2963 if (!loaded_vmcs
->vmcs
)
2965 loaded_vmcs_clear(loaded_vmcs
);
2966 free_vmcs(loaded_vmcs
->vmcs
);
2967 loaded_vmcs
->vmcs
= NULL
;
2970 static void free_kvm_area(void)
2974 for_each_possible_cpu(cpu
) {
2975 free_vmcs(per_cpu(vmxarea
, cpu
));
2976 per_cpu(vmxarea
, cpu
) = NULL
;
2980 static __init
int alloc_kvm_area(void)
2984 for_each_possible_cpu(cpu
) {
2987 vmcs
= alloc_vmcs_cpu(cpu
);
2993 per_cpu(vmxarea
, cpu
) = vmcs
;
2998 static __init
int hardware_setup(void)
3000 if (setup_vmcs_config(&vmcs_config
) < 0)
3003 if (boot_cpu_has(X86_FEATURE_NX
))
3004 kvm_enable_efer_bits(EFER_NX
);
3006 if (!cpu_has_vmx_vpid())
3008 if (!cpu_has_vmx_shadow_vmcs())
3009 enable_shadow_vmcs
= 0;
3011 if (!cpu_has_vmx_ept() ||
3012 !cpu_has_vmx_ept_4levels()) {
3014 enable_unrestricted_guest
= 0;
3015 enable_ept_ad_bits
= 0;
3018 if (!cpu_has_vmx_ept_ad_bits())
3019 enable_ept_ad_bits
= 0;
3021 if (!cpu_has_vmx_unrestricted_guest())
3022 enable_unrestricted_guest
= 0;
3024 if (!cpu_has_vmx_flexpriority())
3025 flexpriority_enabled
= 0;
3027 if (!cpu_has_vmx_tpr_shadow())
3028 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3030 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3031 kvm_disable_largepages();
3033 if (!cpu_has_vmx_ple())
3036 if (!cpu_has_vmx_apicv())
3040 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3042 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3043 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3044 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3048 nested_vmx_setup_ctls_msrs();
3050 return alloc_kvm_area();
3053 static __exit
void hardware_unsetup(void)
3058 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3060 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3063 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3064 struct kvm_segment
*save
)
3066 if (!emulate_invalid_guest_state
) {
3068 * CS and SS RPL should be equal during guest entry according
3069 * to VMX spec, but in reality it is not always so. Since vcpu
3070 * is in the middle of the transition from real mode to
3071 * protected mode it is safe to assume that RPL 0 is a good
3074 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3075 save
->selector
&= ~SELECTOR_RPL_MASK
;
3076 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3079 vmx_set_segment(vcpu
, save
, seg
);
3082 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3084 unsigned long flags
;
3085 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3088 * Update real mode segment cache. It may be not up-to-date if sement
3089 * register was written while vcpu was in a guest mode.
3091 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3092 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3093 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3094 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3095 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3096 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3098 vmx
->rmode
.vm86_active
= 0;
3100 vmx_segment_cache_clear(vmx
);
3102 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3104 flags
= vmcs_readl(GUEST_RFLAGS
);
3105 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3106 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3107 vmcs_writel(GUEST_RFLAGS
, flags
);
3109 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3110 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3112 update_exception_bitmap(vcpu
);
3114 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3115 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3116 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3117 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3118 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3119 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3121 /* CPL is always 0 when CPU enters protected mode */
3122 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3126 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3128 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3129 struct kvm_segment var
= *save
;
3132 if (seg
== VCPU_SREG_CS
)
3135 if (!emulate_invalid_guest_state
) {
3136 var
.selector
= var
.base
>> 4;
3137 var
.base
= var
.base
& 0xffff0;
3147 if (save
->base
& 0xf)
3148 printk_once(KERN_WARNING
"kvm: segment base is not "
3149 "paragraph aligned when entering "
3150 "protected mode (seg=%d)", seg
);
3153 vmcs_write16(sf
->selector
, var
.selector
);
3154 vmcs_write32(sf
->base
, var
.base
);
3155 vmcs_write32(sf
->limit
, var
.limit
);
3156 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3159 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3161 unsigned long flags
;
3162 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3164 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3165 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3166 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3167 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3168 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3169 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3170 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3172 vmx
->rmode
.vm86_active
= 1;
3175 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3176 * vcpu. Warn the user that an update is overdue.
3178 if (!vcpu
->kvm
->arch
.tss_addr
)
3179 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3180 "called before entering vcpu\n");
3182 vmx_segment_cache_clear(vmx
);
3184 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3185 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3186 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3188 flags
= vmcs_readl(GUEST_RFLAGS
);
3189 vmx
->rmode
.save_rflags
= flags
;
3191 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3193 vmcs_writel(GUEST_RFLAGS
, flags
);
3194 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3195 update_exception_bitmap(vcpu
);
3197 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3198 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3199 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3200 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3201 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3202 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3204 kvm_mmu_reset_context(vcpu
);
3207 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3210 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3216 * Force kernel_gs_base reloading before EFER changes, as control
3217 * of this msr depends on is_long_mode().
3219 vmx_load_host_state(to_vmx(vcpu
));
3220 vcpu
->arch
.efer
= efer
;
3221 if (efer
& EFER_LMA
) {
3222 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3225 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3227 msr
->data
= efer
& ~EFER_LME
;
3232 #ifdef CONFIG_X86_64
3234 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3238 vmx_segment_cache_clear(to_vmx(vcpu
));
3240 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3241 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3242 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3244 vmcs_write32(GUEST_TR_AR_BYTES
,
3245 (guest_tr_ar
& ~AR_TYPE_MASK
)
3246 | AR_TYPE_BUSY_64_TSS
);
3248 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3251 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3253 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3254 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3259 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3261 vpid_sync_context(to_vmx(vcpu
));
3263 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3265 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3269 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3271 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3273 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3274 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3277 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3279 if (enable_ept
&& is_paging(vcpu
))
3280 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3281 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3284 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3286 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3288 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3289 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3292 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3294 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3296 if (!test_bit(VCPU_EXREG_PDPTR
,
3297 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3300 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3301 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3302 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3303 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3304 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3308 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3310 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3312 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3313 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3314 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3315 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3316 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3319 __set_bit(VCPU_EXREG_PDPTR
,
3320 (unsigned long *)&vcpu
->arch
.regs_avail
);
3321 __set_bit(VCPU_EXREG_PDPTR
,
3322 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3325 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3327 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3329 struct kvm_vcpu
*vcpu
)
3331 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3332 vmx_decache_cr3(vcpu
);
3333 if (!(cr0
& X86_CR0_PG
)) {
3334 /* From paging/starting to nonpaging */
3335 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3336 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3337 (CPU_BASED_CR3_LOAD_EXITING
|
3338 CPU_BASED_CR3_STORE_EXITING
));
3339 vcpu
->arch
.cr0
= cr0
;
3340 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3341 } else if (!is_paging(vcpu
)) {
3342 /* From nonpaging to paging */
3343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3344 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3345 ~(CPU_BASED_CR3_LOAD_EXITING
|
3346 CPU_BASED_CR3_STORE_EXITING
));
3347 vcpu
->arch
.cr0
= cr0
;
3348 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3351 if (!(cr0
& X86_CR0_WP
))
3352 *hw_cr0
&= ~X86_CR0_WP
;
3355 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3357 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3358 unsigned long hw_cr0
;
3360 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3361 if (enable_unrestricted_guest
)
3362 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3364 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3366 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3369 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3373 #ifdef CONFIG_X86_64
3374 if (vcpu
->arch
.efer
& EFER_LME
) {
3375 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3377 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3383 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3385 if (!vcpu
->fpu_active
)
3386 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3388 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3389 vmcs_writel(GUEST_CR0
, hw_cr0
);
3390 vcpu
->arch
.cr0
= cr0
;
3392 /* depends on vcpu->arch.cr0 to be set to a new value */
3393 vmx
->emulation_required
= emulation_required(vcpu
);
3396 static u64
construct_eptp(unsigned long root_hpa
)
3400 /* TODO write the value reading from MSR */
3401 eptp
= VMX_EPT_DEFAULT_MT
|
3402 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3403 if (enable_ept_ad_bits
)
3404 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3405 eptp
|= (root_hpa
& PAGE_MASK
);
3410 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3412 unsigned long guest_cr3
;
3417 eptp
= construct_eptp(cr3
);
3418 vmcs_write64(EPT_POINTER
, eptp
);
3419 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3420 guest_cr3
= kvm_read_cr3(vcpu
);
3422 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3423 ept_load_pdptrs(vcpu
);
3426 vmx_flush_tlb(vcpu
);
3427 vmcs_writel(GUEST_CR3
, guest_cr3
);
3430 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3432 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3433 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3435 if (cr4
& X86_CR4_VMXE
) {
3437 * To use VMXON (and later other VMX instructions), a guest
3438 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3439 * So basically the check on whether to allow nested VMX
3442 if (!nested_vmx_allowed(vcpu
))
3445 if (to_vmx(vcpu
)->nested
.vmxon
&&
3446 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3449 vcpu
->arch
.cr4
= cr4
;
3451 if (!is_paging(vcpu
)) {
3452 hw_cr4
&= ~X86_CR4_PAE
;
3453 hw_cr4
|= X86_CR4_PSE
;
3455 * SMEP is disabled if CPU is in non-paging mode in
3456 * hardware. However KVM always uses paging mode to
3457 * emulate guest non-paging mode with TDP.
3458 * To emulate this behavior, SMEP needs to be manually
3459 * disabled when guest switches to non-paging mode.
3461 hw_cr4
&= ~X86_CR4_SMEP
;
3462 } else if (!(cr4
& X86_CR4_PAE
)) {
3463 hw_cr4
&= ~X86_CR4_PAE
;
3467 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3468 vmcs_writel(GUEST_CR4
, hw_cr4
);
3472 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3473 struct kvm_segment
*var
, int seg
)
3475 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3478 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3479 *var
= vmx
->rmode
.segs
[seg
];
3480 if (seg
== VCPU_SREG_TR
3481 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3483 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3484 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3487 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3488 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3489 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3490 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3491 var
->unusable
= (ar
>> 16) & 1;
3492 var
->type
= ar
& 15;
3493 var
->s
= (ar
>> 4) & 1;
3494 var
->dpl
= (ar
>> 5) & 3;
3496 * Some userspaces do not preserve unusable property. Since usable
3497 * segment has to be present according to VMX spec we can use present
3498 * property to amend userspace bug by making unusable segment always
3499 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3500 * segment as unusable.
3502 var
->present
= !var
->unusable
;
3503 var
->avl
= (ar
>> 12) & 1;
3504 var
->l
= (ar
>> 13) & 1;
3505 var
->db
= (ar
>> 14) & 1;
3506 var
->g
= (ar
>> 15) & 1;
3509 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3511 struct kvm_segment s
;
3513 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3514 vmx_get_segment(vcpu
, &s
, seg
);
3517 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3520 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3522 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3524 if (!is_protmode(vcpu
))
3527 if (!is_long_mode(vcpu
)
3528 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3531 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3532 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3533 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3540 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3544 if (var
->unusable
|| !var
->present
)
3547 ar
= var
->type
& 15;
3548 ar
|= (var
->s
& 1) << 4;
3549 ar
|= (var
->dpl
& 3) << 5;
3550 ar
|= (var
->present
& 1) << 7;
3551 ar
|= (var
->avl
& 1) << 12;
3552 ar
|= (var
->l
& 1) << 13;
3553 ar
|= (var
->db
& 1) << 14;
3554 ar
|= (var
->g
& 1) << 15;
3560 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3561 struct kvm_segment
*var
, int seg
)
3563 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3564 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3566 vmx_segment_cache_clear(vmx
);
3567 if (seg
== VCPU_SREG_CS
)
3568 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3570 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3571 vmx
->rmode
.segs
[seg
] = *var
;
3572 if (seg
== VCPU_SREG_TR
)
3573 vmcs_write16(sf
->selector
, var
->selector
);
3575 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3579 vmcs_writel(sf
->base
, var
->base
);
3580 vmcs_write32(sf
->limit
, var
->limit
);
3581 vmcs_write16(sf
->selector
, var
->selector
);
3584 * Fix the "Accessed" bit in AR field of segment registers for older
3586 * IA32 arch specifies that at the time of processor reset the
3587 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3588 * is setting it to 0 in the userland code. This causes invalid guest
3589 * state vmexit when "unrestricted guest" mode is turned on.
3590 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3591 * tree. Newer qemu binaries with that qemu fix would not need this
3594 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3595 var
->type
|= 0x1; /* Accessed */
3597 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3600 vmx
->emulation_required
|= emulation_required(vcpu
);
3603 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3605 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3607 *db
= (ar
>> 14) & 1;
3608 *l
= (ar
>> 13) & 1;
3611 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3613 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3614 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3617 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3619 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3620 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3623 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3625 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3626 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3629 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3631 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3632 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3635 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3637 struct kvm_segment var
;
3640 vmx_get_segment(vcpu
, &var
, seg
);
3642 if (seg
== VCPU_SREG_CS
)
3644 ar
= vmx_segment_access_rights(&var
);
3646 if (var
.base
!= (var
.selector
<< 4))
3648 if (var
.limit
!= 0xffff)
3656 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3658 struct kvm_segment cs
;
3659 unsigned int cs_rpl
;
3661 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3662 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3666 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3670 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3671 if (cs
.dpl
> cs_rpl
)
3674 if (cs
.dpl
!= cs_rpl
)
3680 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3684 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3686 struct kvm_segment ss
;
3687 unsigned int ss_rpl
;
3689 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3690 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3694 if (ss
.type
!= 3 && ss
.type
!= 7)
3698 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3706 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3708 struct kvm_segment var
;
3711 vmx_get_segment(vcpu
, &var
, seg
);
3712 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3720 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3721 if (var
.dpl
< rpl
) /* DPL < RPL */
3725 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3731 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3733 struct kvm_segment tr
;
3735 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3739 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3741 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3749 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3751 struct kvm_segment ldtr
;
3753 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3757 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3767 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3769 struct kvm_segment cs
, ss
;
3771 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3772 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3774 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3775 (ss
.selector
& SELECTOR_RPL_MASK
));
3779 * Check if guest state is valid. Returns true if valid, false if
3781 * We assume that registers are always usable
3783 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3785 if (enable_unrestricted_guest
)
3788 /* real mode guest state checks */
3789 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3790 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3792 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3794 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3796 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3798 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3800 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3803 /* protected mode guest state checks */
3804 if (!cs_ss_rpl_check(vcpu
))
3806 if (!code_segment_valid(vcpu
))
3808 if (!stack_segment_valid(vcpu
))
3810 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3812 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3814 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3816 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3818 if (!tr_valid(vcpu
))
3820 if (!ldtr_valid(vcpu
))
3824 * - Add checks on RIP
3825 * - Add checks on RFLAGS
3831 static int init_rmode_tss(struct kvm
*kvm
)
3835 int r
, idx
, ret
= 0;
3837 idx
= srcu_read_lock(&kvm
->srcu
);
3838 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3839 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3842 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3843 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3844 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3847 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3850 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3854 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3855 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3862 srcu_read_unlock(&kvm
->srcu
, idx
);
3866 static int init_rmode_identity_map(struct kvm
*kvm
)
3869 pfn_t identity_map_pfn
;
3874 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3875 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3876 "haven't been allocated!\n");
3879 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3882 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3883 idx
= srcu_read_lock(&kvm
->srcu
);
3884 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3887 /* Set up identity-mapping pagetable for EPT in real mode */
3888 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3889 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3890 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3891 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3892 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3896 kvm
->arch
.ept_identity_pagetable_done
= true;
3899 srcu_read_unlock(&kvm
->srcu
, idx
);
3903 static void seg_setup(int seg
)
3905 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3908 vmcs_write16(sf
->selector
, 0);
3909 vmcs_writel(sf
->base
, 0);
3910 vmcs_write32(sf
->limit
, 0xffff);
3912 if (seg
== VCPU_SREG_CS
)
3913 ar
|= 0x08; /* code segment */
3915 vmcs_write32(sf
->ar_bytes
, ar
);
3918 static int alloc_apic_access_page(struct kvm
*kvm
)
3921 struct kvm_userspace_memory_region kvm_userspace_mem
;
3924 mutex_lock(&kvm
->slots_lock
);
3925 if (kvm
->arch
.apic_access_page
)
3927 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3928 kvm_userspace_mem
.flags
= 0;
3929 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3930 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3931 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3935 page
= gfn_to_page(kvm
, 0xfee00);
3936 if (is_error_page(page
)) {
3941 kvm
->arch
.apic_access_page
= page
;
3943 mutex_unlock(&kvm
->slots_lock
);
3947 static int alloc_identity_pagetable(struct kvm
*kvm
)
3950 struct kvm_userspace_memory_region kvm_userspace_mem
;
3953 mutex_lock(&kvm
->slots_lock
);
3954 if (kvm
->arch
.ept_identity_pagetable
)
3956 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3957 kvm_userspace_mem
.flags
= 0;
3958 kvm_userspace_mem
.guest_phys_addr
=
3959 kvm
->arch
.ept_identity_map_addr
;
3960 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3961 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3965 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3966 if (is_error_page(page
)) {
3971 kvm
->arch
.ept_identity_pagetable
= page
;
3973 mutex_unlock(&kvm
->slots_lock
);
3977 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3984 spin_lock(&vmx_vpid_lock
);
3985 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3986 if (vpid
< VMX_NR_VPIDS
) {
3988 __set_bit(vpid
, vmx_vpid_bitmap
);
3990 spin_unlock(&vmx_vpid_lock
);
3993 static void free_vpid(struct vcpu_vmx
*vmx
)
3997 spin_lock(&vmx_vpid_lock
);
3999 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4000 spin_unlock(&vmx_vpid_lock
);
4003 #define MSR_TYPE_R 1
4004 #define MSR_TYPE_W 2
4005 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4008 int f
= sizeof(unsigned long);
4010 if (!cpu_has_vmx_msr_bitmap())
4014 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4015 * have the write-low and read-high bitmap offsets the wrong way round.
4016 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4018 if (msr
<= 0x1fff) {
4019 if (type
& MSR_TYPE_R
)
4021 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4023 if (type
& MSR_TYPE_W
)
4025 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4027 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4029 if (type
& MSR_TYPE_R
)
4031 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4033 if (type
& MSR_TYPE_W
)
4035 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4040 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4043 int f
= sizeof(unsigned long);
4045 if (!cpu_has_vmx_msr_bitmap())
4049 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4050 * have the write-low and read-high bitmap offsets the wrong way round.
4051 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4053 if (msr
<= 0x1fff) {
4054 if (type
& MSR_TYPE_R
)
4056 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4058 if (type
& MSR_TYPE_W
)
4060 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4062 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4064 if (type
& MSR_TYPE_R
)
4066 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4068 if (type
& MSR_TYPE_W
)
4070 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4075 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4078 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4079 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4080 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4081 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4084 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4086 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4088 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4092 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4094 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4096 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4100 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4102 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4104 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4108 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4110 return enable_apicv
&& irqchip_in_kernel(kvm
);
4114 * Send interrupt to vcpu via posted interrupt way.
4115 * 1. If target vcpu is running(non-root mode), send posted interrupt
4116 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4117 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4118 * interrupt from PIR in next vmentry.
4120 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4125 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4128 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4129 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4131 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4132 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4133 POSTED_INTR_VECTOR
);
4136 kvm_vcpu_kick(vcpu
);
4139 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4141 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4143 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4146 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4149 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4155 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4156 * will not change in the lifetime of the guest.
4157 * Note that host-state that does change is set elsewhere. E.g., host-state
4158 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4160 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4166 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4167 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4168 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4170 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4171 #ifdef CONFIG_X86_64
4173 * Load null selectors, so we can avoid reloading them in
4174 * __vmx_load_host_state(), in case userspace uses the null selectors
4175 * too (the expected case).
4177 vmcs_write16(HOST_DS_SELECTOR
, 0);
4178 vmcs_write16(HOST_ES_SELECTOR
, 0);
4180 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4181 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4183 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4184 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4186 native_store_idt(&dt
);
4187 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4188 vmx
->host_idt_base
= dt
.address
;
4190 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4192 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4193 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4194 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4195 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4197 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4198 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4199 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4203 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4205 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4207 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4208 if (is_guest_mode(&vmx
->vcpu
))
4209 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4210 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4211 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4214 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4216 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4218 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4219 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4220 return pin_based_exec_ctrl
;
4223 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4225 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4226 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4227 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4228 #ifdef CONFIG_X86_64
4229 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4230 CPU_BASED_CR8_LOAD_EXITING
;
4234 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4235 CPU_BASED_CR3_LOAD_EXITING
|
4236 CPU_BASED_INVLPG_EXITING
;
4237 return exec_control
;
4240 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4242 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4243 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4244 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4246 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4248 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4249 enable_unrestricted_guest
= 0;
4250 /* Enable INVPCID for non-ept guests may cause performance regression. */
4251 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4253 if (!enable_unrestricted_guest
)
4254 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4256 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4257 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4258 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4259 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4260 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4261 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4263 We can NOT enable shadow_vmcs here because we don't have yet
4266 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4267 return exec_control
;
4270 static void ept_set_mmio_spte_mask(void)
4273 * EPT Misconfigurations can be generated if the value of bits 2:0
4274 * of an EPT paging-structure entry is 110b (write/execute).
4275 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4278 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4282 * Sets up the vmcs for emulated real mode.
4284 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4286 #ifdef CONFIG_X86_64
4292 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4293 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4295 if (enable_shadow_vmcs
) {
4296 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4297 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4299 if (cpu_has_vmx_msr_bitmap())
4300 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4302 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4305 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4309 if (cpu_has_secondary_exec_ctrls()) {
4310 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4311 vmx_secondary_exec_control(vmx
));
4314 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4315 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4316 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4317 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4318 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4320 vmcs_write16(GUEST_INTR_STATUS
, 0);
4322 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4323 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4327 vmcs_write32(PLE_GAP
, ple_gap
);
4328 vmcs_write32(PLE_WINDOW
, ple_window
);
4331 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4332 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4333 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4335 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4336 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4337 vmx_set_constant_host_state(vmx
);
4338 #ifdef CONFIG_X86_64
4339 rdmsrl(MSR_FS_BASE
, a
);
4340 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4341 rdmsrl(MSR_GS_BASE
, a
);
4342 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4344 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4345 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4348 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4349 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4350 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4351 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4352 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4354 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4355 u32 msr_low
, msr_high
;
4357 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4358 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4359 /* Write the default value follow host pat */
4360 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4361 /* Keep arch.pat sync with GUEST_IA32_PAT */
4362 vmx
->vcpu
.arch
.pat
= host_pat
;
4365 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4366 u32 index
= vmx_msr_index
[i
];
4367 u32 data_low
, data_high
;
4370 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4372 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4374 vmx
->guest_msrs
[j
].index
= i
;
4375 vmx
->guest_msrs
[j
].data
= 0;
4376 vmx
->guest_msrs
[j
].mask
= -1ull;
4381 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4383 /* 22.2.1, 20.8.1 */
4384 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4386 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4387 set_cr4_guest_host_mask(vmx
);
4392 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4394 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4397 vmx
->rmode
.vm86_active
= 0;
4399 vmx
->soft_vnmi_blocked
= 0;
4401 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4402 kvm_set_cr8(&vmx
->vcpu
, 0);
4403 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4404 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4405 msr
|= MSR_IA32_APICBASE_BSP
;
4406 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4408 vmx_segment_cache_clear(vmx
);
4410 seg_setup(VCPU_SREG_CS
);
4411 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4412 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4414 seg_setup(VCPU_SREG_DS
);
4415 seg_setup(VCPU_SREG_ES
);
4416 seg_setup(VCPU_SREG_FS
);
4417 seg_setup(VCPU_SREG_GS
);
4418 seg_setup(VCPU_SREG_SS
);
4420 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4421 vmcs_writel(GUEST_TR_BASE
, 0);
4422 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4423 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4425 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4426 vmcs_writel(GUEST_LDTR_BASE
, 0);
4427 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4428 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4430 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4431 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4432 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4434 vmcs_writel(GUEST_RFLAGS
, 0x02);
4435 kvm_rip_write(vcpu
, 0xfff0);
4437 vmcs_writel(GUEST_GDTR_BASE
, 0);
4438 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4440 vmcs_writel(GUEST_IDTR_BASE
, 0);
4441 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4443 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4444 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4445 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4447 /* Special registers */
4448 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4452 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4454 if (cpu_has_vmx_tpr_shadow()) {
4455 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4456 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4457 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4458 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4459 vmcs_write32(TPR_THRESHOLD
, 0);
4462 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4463 vmcs_write64(APIC_ACCESS_ADDR
,
4464 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4466 if (vmx_vm_has_apicv(vcpu
->kvm
))
4467 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4470 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4472 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4473 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4474 vmx_set_cr4(&vmx
->vcpu
, 0);
4475 vmx_set_efer(&vmx
->vcpu
, 0);
4476 vmx_fpu_activate(&vmx
->vcpu
);
4477 update_exception_bitmap(&vmx
->vcpu
);
4479 vpid_sync_context(vmx
);
4483 * In nested virtualization, check if L1 asked to exit on external interrupts.
4484 * For most existing hypervisors, this will always return true.
4486 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4488 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4489 PIN_BASED_EXT_INTR_MASK
;
4492 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4494 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4495 PIN_BASED_NMI_EXITING
;
4498 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4500 u32 cpu_based_vm_exec_control
;
4502 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4504 * We get here if vmx_interrupt_allowed() said we can't
4505 * inject to L1 now because L2 must run. The caller will have
4506 * to make L2 exit right after entry, so we can inject to L1
4511 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4512 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4513 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4517 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4519 u32 cpu_based_vm_exec_control
;
4521 if (!cpu_has_virtual_nmis())
4522 return enable_irq_window(vcpu
);
4524 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4525 return enable_irq_window(vcpu
);
4527 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4528 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4533 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4535 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4537 int irq
= vcpu
->arch
.interrupt
.nr
;
4539 trace_kvm_inj_virq(irq
);
4541 ++vcpu
->stat
.irq_injections
;
4542 if (vmx
->rmode
.vm86_active
) {
4544 if (vcpu
->arch
.interrupt
.soft
)
4545 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4546 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4547 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4550 intr
= irq
| INTR_INFO_VALID_MASK
;
4551 if (vcpu
->arch
.interrupt
.soft
) {
4552 intr
|= INTR_TYPE_SOFT_INTR
;
4553 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4554 vmx
->vcpu
.arch
.event_exit_inst_len
);
4556 intr
|= INTR_TYPE_EXT_INTR
;
4557 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4560 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4562 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4564 if (is_guest_mode(vcpu
))
4567 if (!cpu_has_virtual_nmis()) {
4569 * Tracking the NMI-blocked state in software is built upon
4570 * finding the next open IRQ window. This, in turn, depends on
4571 * well-behaving guests: They have to keep IRQs disabled at
4572 * least as long as the NMI handler runs. Otherwise we may
4573 * cause NMI nesting, maybe breaking the guest. But as this is
4574 * highly unlikely, we can live with the residual risk.
4576 vmx
->soft_vnmi_blocked
= 1;
4577 vmx
->vnmi_blocked_time
= 0;
4580 ++vcpu
->stat
.nmi_injections
;
4581 vmx
->nmi_known_unmasked
= false;
4582 if (vmx
->rmode
.vm86_active
) {
4583 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4584 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4587 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4588 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4591 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4593 if (!cpu_has_virtual_nmis())
4594 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4595 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4597 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4600 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4602 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4604 if (!cpu_has_virtual_nmis()) {
4605 if (vmx
->soft_vnmi_blocked
!= masked
) {
4606 vmx
->soft_vnmi_blocked
= masked
;
4607 vmx
->vnmi_blocked_time
= 0;
4610 vmx
->nmi_known_unmasked
= !masked
;
4612 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4613 GUEST_INTR_STATE_NMI
);
4615 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4616 GUEST_INTR_STATE_NMI
);
4620 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4622 if (is_guest_mode(vcpu
)) {
4623 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4625 if (nested_exit_on_nmi(vcpu
)) {
4626 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
4627 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
4628 INTR_INFO_VALID_MASK
, 0);
4630 * The NMI-triggered VM exit counts as injection:
4631 * clear this one and block further NMIs.
4633 vcpu
->arch
.nmi_pending
= 0;
4634 vmx_set_nmi_mask(vcpu
, true);
4639 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4642 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4643 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4644 | GUEST_INTR_STATE_NMI
));
4647 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4649 if (is_guest_mode(vcpu
)) {
4650 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4652 if (nested_exit_on_intr(vcpu
)) {
4653 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
,
4656 * fall through to normal code, but now in L1, not L2
4661 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4662 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4663 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4666 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4669 struct kvm_userspace_memory_region tss_mem
= {
4670 .slot
= TSS_PRIVATE_MEMSLOT
,
4671 .guest_phys_addr
= addr
,
4672 .memory_size
= PAGE_SIZE
* 3,
4676 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4679 kvm
->arch
.tss_addr
= addr
;
4680 if (!init_rmode_tss(kvm
))
4686 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4691 * Update instruction length as we may reinject the exception
4692 * from user space while in guest debugging mode.
4694 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4695 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4696 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4700 if (vcpu
->guest_debug
&
4701 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4718 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4719 int vec
, u32 err_code
)
4722 * Instruction with address size override prefix opcode 0x67
4723 * Cause the #SS fault with 0 error code in VM86 mode.
4725 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4726 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4727 if (vcpu
->arch
.halt_request
) {
4728 vcpu
->arch
.halt_request
= 0;
4729 return kvm_emulate_halt(vcpu
);
4737 * Forward all other exceptions that are valid in real mode.
4738 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4739 * the required debugging infrastructure rework.
4741 kvm_queue_exception(vcpu
, vec
);
4746 * Trigger machine check on the host. We assume all the MSRs are already set up
4747 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4748 * We pass a fake environment to the machine check handler because we want
4749 * the guest to be always treated like user space, no matter what context
4750 * it used internally.
4752 static void kvm_machine_check(void)
4754 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4755 struct pt_regs regs
= {
4756 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4757 .flags
= X86_EFLAGS_IF
,
4760 do_machine_check(®s
, 0);
4764 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4766 /* already handled by vcpu_run */
4770 static int handle_exception(struct kvm_vcpu
*vcpu
)
4772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4773 struct kvm_run
*kvm_run
= vcpu
->run
;
4774 u32 intr_info
, ex_no
, error_code
;
4775 unsigned long cr2
, rip
, dr6
;
4777 enum emulation_result er
;
4779 vect_info
= vmx
->idt_vectoring_info
;
4780 intr_info
= vmx
->exit_intr_info
;
4782 if (is_machine_check(intr_info
))
4783 return handle_machine_check(vcpu
);
4785 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4786 return 1; /* already handled by vmx_vcpu_run() */
4788 if (is_no_device(intr_info
)) {
4789 vmx_fpu_activate(vcpu
);
4793 if (is_invalid_opcode(intr_info
)) {
4794 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4795 if (er
!= EMULATE_DONE
)
4796 kvm_queue_exception(vcpu
, UD_VECTOR
);
4801 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4802 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4805 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4806 * MMIO, it is better to report an internal error.
4807 * See the comments in vmx_handle_exit.
4809 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4810 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4811 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4812 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4813 vcpu
->run
->internal
.ndata
= 2;
4814 vcpu
->run
->internal
.data
[0] = vect_info
;
4815 vcpu
->run
->internal
.data
[1] = intr_info
;
4819 if (is_page_fault(intr_info
)) {
4820 /* EPT won't cause page fault directly */
4822 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4823 trace_kvm_page_fault(cr2
, error_code
);
4825 if (kvm_event_needs_reinjection(vcpu
))
4826 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4827 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4830 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4832 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4833 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4837 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4838 if (!(vcpu
->guest_debug
&
4839 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4840 vcpu
->arch
.dr6
&= ~15;
4841 vcpu
->arch
.dr6
|= dr6
;
4842 kvm_queue_exception(vcpu
, DB_VECTOR
);
4845 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4846 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4850 * Update instruction length as we may reinject #BP from
4851 * user space while in guest debugging mode. Reading it for
4852 * #DB as well causes no harm, it is not used in that case.
4854 vmx
->vcpu
.arch
.event_exit_inst_len
=
4855 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4856 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4857 rip
= kvm_rip_read(vcpu
);
4858 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4859 kvm_run
->debug
.arch
.exception
= ex_no
;
4862 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4863 kvm_run
->ex
.exception
= ex_no
;
4864 kvm_run
->ex
.error_code
= error_code
;
4870 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4872 ++vcpu
->stat
.irq_exits
;
4876 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4878 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4882 static int handle_io(struct kvm_vcpu
*vcpu
)
4884 unsigned long exit_qualification
;
4885 int size
, in
, string
;
4888 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4889 string
= (exit_qualification
& 16) != 0;
4890 in
= (exit_qualification
& 8) != 0;
4892 ++vcpu
->stat
.io_exits
;
4895 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4897 port
= exit_qualification
>> 16;
4898 size
= (exit_qualification
& 7) + 1;
4899 skip_emulated_instruction(vcpu
);
4901 return kvm_fast_pio_out(vcpu
, size
, port
);
4905 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4908 * Patch in the VMCALL instruction:
4910 hypercall
[0] = 0x0f;
4911 hypercall
[1] = 0x01;
4912 hypercall
[2] = 0xc1;
4915 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4917 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4919 if (nested_vmx_secondary_ctls_high
&
4920 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4921 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4922 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4923 return (val
& always_on
) == always_on
;
4926 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4927 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4929 if (is_guest_mode(vcpu
)) {
4930 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4931 unsigned long orig_val
= val
;
4934 * We get here when L2 changed cr0 in a way that did not change
4935 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4936 * but did change L0 shadowed bits. So we first calculate the
4937 * effective cr0 value that L1 would like to write into the
4938 * hardware. It consists of the L2-owned bits from the new
4939 * value combined with the L1-owned bits from L1's guest_cr0.
4941 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4942 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4944 if (!nested_cr0_valid(vmcs12
, val
))
4947 if (kvm_set_cr0(vcpu
, val
))
4949 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4952 if (to_vmx(vcpu
)->nested
.vmxon
&&
4953 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4955 return kvm_set_cr0(vcpu
, val
);
4959 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4961 if (is_guest_mode(vcpu
)) {
4962 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4963 unsigned long orig_val
= val
;
4965 /* analogously to handle_set_cr0 */
4966 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4967 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4968 if (kvm_set_cr4(vcpu
, val
))
4970 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4973 return kvm_set_cr4(vcpu
, val
);
4976 /* called to set cr0 as approriate for clts instruction exit. */
4977 static void handle_clts(struct kvm_vcpu
*vcpu
)
4979 if (is_guest_mode(vcpu
)) {
4981 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4982 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4983 * just pretend it's off (also in arch.cr0 for fpu_activate).
4985 vmcs_writel(CR0_READ_SHADOW
,
4986 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4987 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4989 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4992 static int handle_cr(struct kvm_vcpu
*vcpu
)
4994 unsigned long exit_qualification
, val
;
4999 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5000 cr
= exit_qualification
& 15;
5001 reg
= (exit_qualification
>> 8) & 15;
5002 switch ((exit_qualification
>> 4) & 3) {
5003 case 0: /* mov to cr */
5004 val
= kvm_register_read(vcpu
, reg
);
5005 trace_kvm_cr_write(cr
, val
);
5008 err
= handle_set_cr0(vcpu
, val
);
5009 kvm_complete_insn_gp(vcpu
, err
);
5012 err
= kvm_set_cr3(vcpu
, val
);
5013 kvm_complete_insn_gp(vcpu
, err
);
5016 err
= handle_set_cr4(vcpu
, val
);
5017 kvm_complete_insn_gp(vcpu
, err
);
5020 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5021 u8 cr8
= kvm_register_read(vcpu
, reg
);
5022 err
= kvm_set_cr8(vcpu
, cr8
);
5023 kvm_complete_insn_gp(vcpu
, err
);
5024 if (irqchip_in_kernel(vcpu
->kvm
))
5026 if (cr8_prev
<= cr8
)
5028 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5035 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5036 skip_emulated_instruction(vcpu
);
5037 vmx_fpu_activate(vcpu
);
5039 case 1: /*mov from cr*/
5042 val
= kvm_read_cr3(vcpu
);
5043 kvm_register_write(vcpu
, reg
, val
);
5044 trace_kvm_cr_read(cr
, val
);
5045 skip_emulated_instruction(vcpu
);
5048 val
= kvm_get_cr8(vcpu
);
5049 kvm_register_write(vcpu
, reg
, val
);
5050 trace_kvm_cr_read(cr
, val
);
5051 skip_emulated_instruction(vcpu
);
5056 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5057 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5058 kvm_lmsw(vcpu
, val
);
5060 skip_emulated_instruction(vcpu
);
5065 vcpu
->run
->exit_reason
= 0;
5066 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5067 (int)(exit_qualification
>> 4) & 3, cr
);
5071 static int handle_dr(struct kvm_vcpu
*vcpu
)
5073 unsigned long exit_qualification
;
5076 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5077 if (!kvm_require_cpl(vcpu
, 0))
5079 dr
= vmcs_readl(GUEST_DR7
);
5082 * As the vm-exit takes precedence over the debug trap, we
5083 * need to emulate the latter, either for the host or the
5084 * guest debugging itself.
5086 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5087 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5088 vcpu
->run
->debug
.arch
.dr7
= dr
;
5089 vcpu
->run
->debug
.arch
.pc
=
5090 vmcs_readl(GUEST_CS_BASE
) +
5091 vmcs_readl(GUEST_RIP
);
5092 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5093 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5096 vcpu
->arch
.dr7
&= ~DR7_GD
;
5097 vcpu
->arch
.dr6
|= DR6_BD
;
5098 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5099 kvm_queue_exception(vcpu
, DB_VECTOR
);
5104 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5105 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5106 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5107 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5110 if (kvm_get_dr(vcpu
, dr
, &val
))
5112 kvm_register_write(vcpu
, reg
, val
);
5114 if (kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]))
5117 skip_emulated_instruction(vcpu
);
5121 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5123 return vcpu
->arch
.dr6
;
5126 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5130 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5132 vmcs_writel(GUEST_DR7
, val
);
5135 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5137 kvm_emulate_cpuid(vcpu
);
5141 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5143 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5146 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5147 trace_kvm_msr_read_ex(ecx
);
5148 kvm_inject_gp(vcpu
, 0);
5152 trace_kvm_msr_read(ecx
, data
);
5154 /* FIXME: handling of bits 32:63 of rax, rdx */
5155 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5156 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5157 skip_emulated_instruction(vcpu
);
5161 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5163 struct msr_data msr
;
5164 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5165 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5166 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5170 msr
.host_initiated
= false;
5171 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5172 trace_kvm_msr_write_ex(ecx
, data
);
5173 kvm_inject_gp(vcpu
, 0);
5177 trace_kvm_msr_write(ecx
, data
);
5178 skip_emulated_instruction(vcpu
);
5182 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5184 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5188 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5190 u32 cpu_based_vm_exec_control
;
5192 /* clear pending irq */
5193 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5194 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5195 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5197 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5199 ++vcpu
->stat
.irq_window_exits
;
5202 * If the user space waits to inject interrupts, exit as soon as
5205 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5206 vcpu
->run
->request_interrupt_window
&&
5207 !kvm_cpu_has_interrupt(vcpu
)) {
5208 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5214 static int handle_halt(struct kvm_vcpu
*vcpu
)
5216 skip_emulated_instruction(vcpu
);
5217 return kvm_emulate_halt(vcpu
);
5220 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5222 skip_emulated_instruction(vcpu
);
5223 kvm_emulate_hypercall(vcpu
);
5227 static int handle_invd(struct kvm_vcpu
*vcpu
)
5229 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5232 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5234 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5236 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5237 skip_emulated_instruction(vcpu
);
5241 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5245 err
= kvm_rdpmc(vcpu
);
5246 kvm_complete_insn_gp(vcpu
, err
);
5251 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5253 skip_emulated_instruction(vcpu
);
5254 kvm_emulate_wbinvd(vcpu
);
5258 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5260 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5261 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5263 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5264 skip_emulated_instruction(vcpu
);
5268 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5270 if (likely(fasteoi
)) {
5271 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5272 int access_type
, offset
;
5274 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5275 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5277 * Sane guest uses MOV to write EOI, with written value
5278 * not cared. So make a short-circuit here by avoiding
5279 * heavy instruction emulation.
5281 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5282 (offset
== APIC_EOI
)) {
5283 kvm_lapic_set_eoi(vcpu
);
5284 skip_emulated_instruction(vcpu
);
5288 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5291 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5293 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5294 int vector
= exit_qualification
& 0xff;
5296 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5297 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5301 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5303 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5304 u32 offset
= exit_qualification
& 0xfff;
5306 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5307 kvm_apic_write_nodecode(vcpu
, offset
);
5311 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5314 unsigned long exit_qualification
;
5315 bool has_error_code
= false;
5318 int reason
, type
, idt_v
, idt_index
;
5320 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5321 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5322 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5324 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5326 reason
= (u32
)exit_qualification
>> 30;
5327 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5329 case INTR_TYPE_NMI_INTR
:
5330 vcpu
->arch
.nmi_injected
= false;
5331 vmx_set_nmi_mask(vcpu
, true);
5333 case INTR_TYPE_EXT_INTR
:
5334 case INTR_TYPE_SOFT_INTR
:
5335 kvm_clear_interrupt_queue(vcpu
);
5337 case INTR_TYPE_HARD_EXCEPTION
:
5338 if (vmx
->idt_vectoring_info
&
5339 VECTORING_INFO_DELIVER_CODE_MASK
) {
5340 has_error_code
= true;
5342 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5345 case INTR_TYPE_SOFT_EXCEPTION
:
5346 kvm_clear_exception_queue(vcpu
);
5352 tss_selector
= exit_qualification
;
5354 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5355 type
!= INTR_TYPE_EXT_INTR
&&
5356 type
!= INTR_TYPE_NMI_INTR
))
5357 skip_emulated_instruction(vcpu
);
5359 if (kvm_task_switch(vcpu
, tss_selector
,
5360 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5361 has_error_code
, error_code
) == EMULATE_FAIL
) {
5362 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5363 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5364 vcpu
->run
->internal
.ndata
= 0;
5368 /* clear all local breakpoint enable flags */
5369 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5372 * TODO: What about debug traps on tss switch?
5373 * Are we supposed to inject them and update dr6?
5379 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5381 unsigned long exit_qualification
;
5386 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5388 gla_validity
= (exit_qualification
>> 7) & 0x3;
5389 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5390 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5391 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5392 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5393 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5394 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5395 (long unsigned int)exit_qualification
);
5396 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5397 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5402 * EPT violation happened while executing iret from NMI,
5403 * "blocked by NMI" bit has to be set before next VM entry.
5404 * There are errata that may cause this bit to not be set:
5407 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5408 cpu_has_virtual_nmis() &&
5409 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5410 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5412 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5413 trace_kvm_page_fault(gpa
, exit_qualification
);
5415 /* It is a write fault? */
5416 error_code
= exit_qualification
& (1U << 1);
5417 /* It is a fetch fault? */
5418 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5419 /* ept page table is present? */
5420 error_code
|= (exit_qualification
>> 3) & 0x1;
5422 vcpu
->arch
.exit_qualification
= exit_qualification
;
5424 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5427 static u64
ept_rsvd_mask(u64 spte
, int level
)
5432 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5433 mask
|= (1ULL << i
);
5436 /* bits 7:3 reserved */
5438 else if (level
== 2) {
5439 if (spte
& (1ULL << 7))
5440 /* 2MB ref, bits 20:12 reserved */
5443 /* bits 6:3 reserved */
5450 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5453 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5455 /* 010b (write-only) */
5456 WARN_ON((spte
& 0x7) == 0x2);
5458 /* 110b (write/execute) */
5459 WARN_ON((spte
& 0x7) == 0x6);
5461 /* 100b (execute-only) and value not supported by logical processor */
5462 if (!cpu_has_vmx_ept_execute_only())
5463 WARN_ON((spte
& 0x7) == 0x4);
5467 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5469 if (rsvd_bits
!= 0) {
5470 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5471 __func__
, rsvd_bits
);
5475 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5476 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5478 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5479 ept_mem_type
== 7) {
5480 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5481 __func__
, ept_mem_type
);
5488 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5491 int nr_sptes
, i
, ret
;
5494 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5496 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5497 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5498 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5501 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5502 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5504 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5507 /* It is the real ept misconfig */
5508 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5509 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5511 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5513 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5514 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5516 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5517 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5522 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5524 u32 cpu_based_vm_exec_control
;
5526 /* clear pending NMI */
5527 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5528 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5530 ++vcpu
->stat
.nmi_window_exits
;
5531 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5536 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5538 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5539 enum emulation_result err
= EMULATE_DONE
;
5542 bool intr_window_requested
;
5543 unsigned count
= 130;
5545 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5546 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5548 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5549 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5550 return handle_interrupt_window(&vmx
->vcpu
);
5552 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5555 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5557 if (err
== EMULATE_USER_EXIT
) {
5558 ++vcpu
->stat
.mmio_exits
;
5563 if (err
!= EMULATE_DONE
) {
5564 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5565 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5566 vcpu
->run
->internal
.ndata
= 0;
5570 if (vcpu
->arch
.halt_request
) {
5571 vcpu
->arch
.halt_request
= 0;
5572 ret
= kvm_emulate_halt(vcpu
);
5576 if (signal_pending(current
))
5582 vmx
->emulation_required
= emulation_required(vcpu
);
5588 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5589 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5591 static int handle_pause(struct kvm_vcpu
*vcpu
)
5593 skip_emulated_instruction(vcpu
);
5594 kvm_vcpu_on_spin(vcpu
);
5599 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5601 kvm_queue_exception(vcpu
, UD_VECTOR
);
5606 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5607 * We could reuse a single VMCS for all the L2 guests, but we also want the
5608 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5609 * allows keeping them loaded on the processor, and in the future will allow
5610 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5611 * every entry if they never change.
5612 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5613 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5615 * The following functions allocate and free a vmcs02 in this pool.
5618 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5619 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5621 struct vmcs02_list
*item
;
5622 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5623 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5624 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5625 return &item
->vmcs02
;
5628 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5629 /* Recycle the least recently used VMCS. */
5630 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5631 struct vmcs02_list
, list
);
5632 item
->vmptr
= vmx
->nested
.current_vmptr
;
5633 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5634 return &item
->vmcs02
;
5637 /* Create a new VMCS */
5638 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5641 item
->vmcs02
.vmcs
= alloc_vmcs();
5642 if (!item
->vmcs02
.vmcs
) {
5646 loaded_vmcs_init(&item
->vmcs02
);
5647 item
->vmptr
= vmx
->nested
.current_vmptr
;
5648 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5649 vmx
->nested
.vmcs02_num
++;
5650 return &item
->vmcs02
;
5653 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5654 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5656 struct vmcs02_list
*item
;
5657 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5658 if (item
->vmptr
== vmptr
) {
5659 free_loaded_vmcs(&item
->vmcs02
);
5660 list_del(&item
->list
);
5662 vmx
->nested
.vmcs02_num
--;
5668 * Free all VMCSs saved for this vcpu, except the one pointed by
5669 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5670 * currently used, if running L2), and vmcs01 when running L2.
5672 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5674 struct vmcs02_list
*item
, *n
;
5675 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5676 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5677 free_loaded_vmcs(&item
->vmcs02
);
5678 list_del(&item
->list
);
5681 vmx
->nested
.vmcs02_num
= 0;
5683 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5684 free_loaded_vmcs(&vmx
->vmcs01
);
5688 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5689 * set the success or error code of an emulated VMX instruction, as specified
5690 * by Vol 2B, VMX Instruction Reference, "Conventions".
5692 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5694 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5695 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5696 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5699 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5701 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5702 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5703 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5707 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5708 u32 vm_instruction_error
)
5710 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5712 * failValid writes the error number to the current VMCS, which
5713 * can't be done there isn't a current VMCS.
5715 nested_vmx_failInvalid(vcpu
);
5718 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5719 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5720 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5722 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5724 * We don't need to force a shadow sync because
5725 * VM_INSTRUCTION_ERROR is not shadowed
5730 * Emulate the VMXON instruction.
5731 * Currently, we just remember that VMX is active, and do not save or even
5732 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5733 * do not currently need to store anything in that guest-allocated memory
5734 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5735 * argument is different from the VMXON pointer (which the spec says they do).
5737 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5739 struct kvm_segment cs
;
5740 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5741 struct vmcs
*shadow_vmcs
;
5742 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5743 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5745 /* The Intel VMX Instruction Reference lists a bunch of bits that
5746 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5747 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5748 * Otherwise, we should fail with #UD. We test these now:
5750 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5751 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5752 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5753 kvm_queue_exception(vcpu
, UD_VECTOR
);
5757 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5758 if (is_long_mode(vcpu
) && !cs
.l
) {
5759 kvm_queue_exception(vcpu
, UD_VECTOR
);
5763 if (vmx_get_cpl(vcpu
)) {
5764 kvm_inject_gp(vcpu
, 0);
5767 if (vmx
->nested
.vmxon
) {
5768 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5769 skip_emulated_instruction(vcpu
);
5773 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5774 != VMXON_NEEDED_FEATURES
) {
5775 kvm_inject_gp(vcpu
, 0);
5779 if (enable_shadow_vmcs
) {
5780 shadow_vmcs
= alloc_vmcs();
5783 /* mark vmcs as shadow */
5784 shadow_vmcs
->revision_id
|= (1u << 31);
5785 /* init shadow vmcs */
5786 vmcs_clear(shadow_vmcs
);
5787 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5790 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5791 vmx
->nested
.vmcs02_num
= 0;
5793 vmx
->nested
.vmxon
= true;
5795 skip_emulated_instruction(vcpu
);
5796 nested_vmx_succeed(vcpu
);
5801 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5802 * for running VMX instructions (except VMXON, whose prerequisites are
5803 * slightly different). It also specifies what exception to inject otherwise.
5805 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5807 struct kvm_segment cs
;
5808 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5810 if (!vmx
->nested
.vmxon
) {
5811 kvm_queue_exception(vcpu
, UD_VECTOR
);
5815 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5816 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5817 (is_long_mode(vcpu
) && !cs
.l
)) {
5818 kvm_queue_exception(vcpu
, UD_VECTOR
);
5822 if (vmx_get_cpl(vcpu
)) {
5823 kvm_inject_gp(vcpu
, 0);
5830 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5833 if (enable_shadow_vmcs
) {
5834 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5835 /* copy to memory all shadowed fields in case
5836 they were modified */
5837 copy_shadow_to_vmcs12(vmx
);
5838 vmx
->nested
.sync_shadow_vmcs
= false;
5839 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5840 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5841 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5842 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5845 kunmap(vmx
->nested
.current_vmcs12_page
);
5846 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5850 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5851 * just stops using VMX.
5853 static void free_nested(struct vcpu_vmx
*vmx
)
5855 if (!vmx
->nested
.vmxon
)
5857 vmx
->nested
.vmxon
= false;
5858 if (vmx
->nested
.current_vmptr
!= -1ull) {
5859 nested_release_vmcs12(vmx
);
5860 vmx
->nested
.current_vmptr
= -1ull;
5861 vmx
->nested
.current_vmcs12
= NULL
;
5863 if (enable_shadow_vmcs
)
5864 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5865 /* Unpin physical memory we referred to in current vmcs02 */
5866 if (vmx
->nested
.apic_access_page
) {
5867 nested_release_page(vmx
->nested
.apic_access_page
);
5868 vmx
->nested
.apic_access_page
= 0;
5871 nested_free_all_saved_vmcss(vmx
);
5874 /* Emulate the VMXOFF instruction */
5875 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5877 if (!nested_vmx_check_permission(vcpu
))
5879 free_nested(to_vmx(vcpu
));
5880 skip_emulated_instruction(vcpu
);
5881 nested_vmx_succeed(vcpu
);
5886 * Decode the memory-address operand of a vmx instruction, as recorded on an
5887 * exit caused by such an instruction (run by a guest hypervisor).
5888 * On success, returns 0. When the operand is invalid, returns 1 and throws
5891 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5892 unsigned long exit_qualification
,
5893 u32 vmx_instruction_info
, gva_t
*ret
)
5896 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5897 * Execution", on an exit, vmx_instruction_info holds most of the
5898 * addressing components of the operand. Only the displacement part
5899 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5900 * For how an actual address is calculated from all these components,
5901 * refer to Vol. 1, "Operand Addressing".
5903 int scaling
= vmx_instruction_info
& 3;
5904 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5905 bool is_reg
= vmx_instruction_info
& (1u << 10);
5906 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5907 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5908 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5909 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5910 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5913 kvm_queue_exception(vcpu
, UD_VECTOR
);
5917 /* Addr = segment_base + offset */
5918 /* offset = base + [index * scale] + displacement */
5919 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5921 *ret
+= kvm_register_read(vcpu
, base_reg
);
5923 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5924 *ret
+= exit_qualification
; /* holds the displacement */
5926 if (addr_size
== 1) /* 32 bit */
5930 * TODO: throw #GP (and return 1) in various cases that the VM*
5931 * instructions require it - e.g., offset beyond segment limit,
5932 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5933 * address, and so on. Currently these are not checked.
5938 /* Emulate the VMCLEAR instruction */
5939 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5941 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5944 struct vmcs12
*vmcs12
;
5946 struct x86_exception e
;
5948 if (!nested_vmx_check_permission(vcpu
))
5951 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5952 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5955 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5956 sizeof(vmptr
), &e
)) {
5957 kvm_inject_page_fault(vcpu
, &e
);
5961 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5962 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5963 skip_emulated_instruction(vcpu
);
5967 if (vmptr
== vmx
->nested
.current_vmptr
) {
5968 nested_release_vmcs12(vmx
);
5969 vmx
->nested
.current_vmptr
= -1ull;
5970 vmx
->nested
.current_vmcs12
= NULL
;
5973 page
= nested_get_page(vcpu
, vmptr
);
5976 * For accurate processor emulation, VMCLEAR beyond available
5977 * physical memory should do nothing at all. However, it is
5978 * possible that a nested vmx bug, not a guest hypervisor bug,
5979 * resulted in this case, so let's shut down before doing any
5982 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5985 vmcs12
= kmap(page
);
5986 vmcs12
->launch_state
= 0;
5988 nested_release_page(page
);
5990 nested_free_vmcs02(vmx
, vmptr
);
5992 skip_emulated_instruction(vcpu
);
5993 nested_vmx_succeed(vcpu
);
5997 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5999 /* Emulate the VMLAUNCH instruction */
6000 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6002 return nested_vmx_run(vcpu
, true);
6005 /* Emulate the VMRESUME instruction */
6006 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6009 return nested_vmx_run(vcpu
, false);
6012 enum vmcs_field_type
{
6013 VMCS_FIELD_TYPE_U16
= 0,
6014 VMCS_FIELD_TYPE_U64
= 1,
6015 VMCS_FIELD_TYPE_U32
= 2,
6016 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6019 static inline int vmcs_field_type(unsigned long field
)
6021 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6022 return VMCS_FIELD_TYPE_U32
;
6023 return (field
>> 13) & 0x3 ;
6026 static inline int vmcs_field_readonly(unsigned long field
)
6028 return (((field
>> 10) & 0x3) == 1);
6032 * Read a vmcs12 field. Since these can have varying lengths and we return
6033 * one type, we chose the biggest type (u64) and zero-extend the return value
6034 * to that size. Note that the caller, handle_vmread, might need to use only
6035 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6036 * 64-bit fields are to be returned).
6038 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6039 unsigned long field
, u64
*ret
)
6041 short offset
= vmcs_field_to_offset(field
);
6047 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6049 switch (vmcs_field_type(field
)) {
6050 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6051 *ret
= *((natural_width
*)p
);
6053 case VMCS_FIELD_TYPE_U16
:
6056 case VMCS_FIELD_TYPE_U32
:
6059 case VMCS_FIELD_TYPE_U64
:
6063 return 0; /* can never happen. */
6068 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6069 unsigned long field
, u64 field_value
){
6070 short offset
= vmcs_field_to_offset(field
);
6071 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6075 switch (vmcs_field_type(field
)) {
6076 case VMCS_FIELD_TYPE_U16
:
6077 *(u16
*)p
= field_value
;
6079 case VMCS_FIELD_TYPE_U32
:
6080 *(u32
*)p
= field_value
;
6082 case VMCS_FIELD_TYPE_U64
:
6083 *(u64
*)p
= field_value
;
6085 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6086 *(natural_width
*)p
= field_value
;
6089 return false; /* can never happen. */
6094 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6097 unsigned long field
;
6099 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6100 const unsigned long *fields
= shadow_read_write_fields
;
6101 const int num_fields
= max_shadow_read_write_fields
;
6103 vmcs_load(shadow_vmcs
);
6105 for (i
= 0; i
< num_fields
; i
++) {
6107 switch (vmcs_field_type(field
)) {
6108 case VMCS_FIELD_TYPE_U16
:
6109 field_value
= vmcs_read16(field
);
6111 case VMCS_FIELD_TYPE_U32
:
6112 field_value
= vmcs_read32(field
);
6114 case VMCS_FIELD_TYPE_U64
:
6115 field_value
= vmcs_read64(field
);
6117 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6118 field_value
= vmcs_readl(field
);
6121 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6124 vmcs_clear(shadow_vmcs
);
6125 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6128 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6130 const unsigned long *fields
[] = {
6131 shadow_read_write_fields
,
6132 shadow_read_only_fields
6134 const int max_fields
[] = {
6135 max_shadow_read_write_fields
,
6136 max_shadow_read_only_fields
6139 unsigned long field
;
6140 u64 field_value
= 0;
6141 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6143 vmcs_load(shadow_vmcs
);
6145 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6146 for (i
= 0; i
< max_fields
[q
]; i
++) {
6147 field
= fields
[q
][i
];
6148 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6150 switch (vmcs_field_type(field
)) {
6151 case VMCS_FIELD_TYPE_U16
:
6152 vmcs_write16(field
, (u16
)field_value
);
6154 case VMCS_FIELD_TYPE_U32
:
6155 vmcs_write32(field
, (u32
)field_value
);
6157 case VMCS_FIELD_TYPE_U64
:
6158 vmcs_write64(field
, (u64
)field_value
);
6160 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6161 vmcs_writel(field
, (long)field_value
);
6167 vmcs_clear(shadow_vmcs
);
6168 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6172 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6173 * used before) all generate the same failure when it is missing.
6175 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6177 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6178 if (vmx
->nested
.current_vmptr
== -1ull) {
6179 nested_vmx_failInvalid(vcpu
);
6180 skip_emulated_instruction(vcpu
);
6186 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6188 unsigned long field
;
6190 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6191 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6194 if (!nested_vmx_check_permission(vcpu
) ||
6195 !nested_vmx_check_vmcs12(vcpu
))
6198 /* Decode instruction info and find the field to read */
6199 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6200 /* Read the field, zero-extended to a u64 field_value */
6201 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6202 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6203 skip_emulated_instruction(vcpu
);
6207 * Now copy part of this value to register or memory, as requested.
6208 * Note that the number of bits actually copied is 32 or 64 depending
6209 * on the guest's mode (32 or 64 bit), not on the given field's length.
6211 if (vmx_instruction_info
& (1u << 10)) {
6212 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6215 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6216 vmx_instruction_info
, &gva
))
6218 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6219 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6220 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6223 nested_vmx_succeed(vcpu
);
6224 skip_emulated_instruction(vcpu
);
6229 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6231 unsigned long field
;
6233 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6234 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6235 /* The value to write might be 32 or 64 bits, depending on L1's long
6236 * mode, and eventually we need to write that into a field of several
6237 * possible lengths. The code below first zero-extends the value to 64
6238 * bit (field_value), and then copies only the approriate number of
6239 * bits into the vmcs12 field.
6241 u64 field_value
= 0;
6242 struct x86_exception e
;
6244 if (!nested_vmx_check_permission(vcpu
) ||
6245 !nested_vmx_check_vmcs12(vcpu
))
6248 if (vmx_instruction_info
& (1u << 10))
6249 field_value
= kvm_register_read(vcpu
,
6250 (((vmx_instruction_info
) >> 3) & 0xf));
6252 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6253 vmx_instruction_info
, &gva
))
6255 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6256 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6257 kvm_inject_page_fault(vcpu
, &e
);
6263 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6264 if (vmcs_field_readonly(field
)) {
6265 nested_vmx_failValid(vcpu
,
6266 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6267 skip_emulated_instruction(vcpu
);
6271 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6272 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6273 skip_emulated_instruction(vcpu
);
6277 nested_vmx_succeed(vcpu
);
6278 skip_emulated_instruction(vcpu
);
6282 /* Emulate the VMPTRLD instruction */
6283 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6288 struct x86_exception e
;
6291 if (!nested_vmx_check_permission(vcpu
))
6294 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6295 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6298 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6299 sizeof(vmptr
), &e
)) {
6300 kvm_inject_page_fault(vcpu
, &e
);
6304 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6305 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6306 skip_emulated_instruction(vcpu
);
6310 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6311 struct vmcs12
*new_vmcs12
;
6313 page
= nested_get_page(vcpu
, vmptr
);
6315 nested_vmx_failInvalid(vcpu
);
6316 skip_emulated_instruction(vcpu
);
6319 new_vmcs12
= kmap(page
);
6320 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6322 nested_release_page_clean(page
);
6323 nested_vmx_failValid(vcpu
,
6324 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6325 skip_emulated_instruction(vcpu
);
6328 if (vmx
->nested
.current_vmptr
!= -1ull)
6329 nested_release_vmcs12(vmx
);
6331 vmx
->nested
.current_vmptr
= vmptr
;
6332 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6333 vmx
->nested
.current_vmcs12_page
= page
;
6334 if (enable_shadow_vmcs
) {
6335 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6336 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6337 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6338 vmcs_write64(VMCS_LINK_POINTER
,
6339 __pa(vmx
->nested
.current_shadow_vmcs
));
6340 vmx
->nested
.sync_shadow_vmcs
= true;
6344 nested_vmx_succeed(vcpu
);
6345 skip_emulated_instruction(vcpu
);
6349 /* Emulate the VMPTRST instruction */
6350 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6352 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6353 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6355 struct x86_exception e
;
6357 if (!nested_vmx_check_permission(vcpu
))
6360 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6361 vmx_instruction_info
, &vmcs_gva
))
6363 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6364 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6365 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6367 kvm_inject_page_fault(vcpu
, &e
);
6370 nested_vmx_succeed(vcpu
);
6371 skip_emulated_instruction(vcpu
);
6375 /* Emulate the INVEPT instruction */
6376 static int handle_invept(struct kvm_vcpu
*vcpu
)
6378 u32 vmx_instruction_info
, types
;
6381 struct x86_exception e
;
6385 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6387 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6388 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6389 kvm_queue_exception(vcpu
, UD_VECTOR
);
6393 if (!nested_vmx_check_permission(vcpu
))
6396 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6397 kvm_queue_exception(vcpu
, UD_VECTOR
);
6401 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6402 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6404 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6406 if (!(types
& (1UL << type
))) {
6407 nested_vmx_failValid(vcpu
,
6408 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6412 /* According to the Intel VMX instruction reference, the memory
6413 * operand is read even if it isn't needed (e.g., for type==global)
6415 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6416 vmx_instruction_info
, &gva
))
6418 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6419 sizeof(operand
), &e
)) {
6420 kvm_inject_page_fault(vcpu
, &e
);
6425 case VMX_EPT_EXTENT_CONTEXT
:
6426 if ((operand
.eptp
& eptp_mask
) !=
6427 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6429 case VMX_EPT_EXTENT_GLOBAL
:
6430 kvm_mmu_sync_roots(vcpu
);
6431 kvm_mmu_flush_tlb(vcpu
);
6432 nested_vmx_succeed(vcpu
);
6439 skip_emulated_instruction(vcpu
);
6444 * The exit handlers return 1 if the exit was handled fully and guest execution
6445 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6446 * to be done to userspace and return 0.
6448 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6449 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6450 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6451 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6452 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6453 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6454 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6455 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6456 [EXIT_REASON_CPUID
] = handle_cpuid
,
6457 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6458 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6459 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6460 [EXIT_REASON_HLT
] = handle_halt
,
6461 [EXIT_REASON_INVD
] = handle_invd
,
6462 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6463 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6464 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6465 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6466 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6467 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6468 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6469 [EXIT_REASON_VMREAD
] = handle_vmread
,
6470 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6471 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6472 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6473 [EXIT_REASON_VMON
] = handle_vmon
,
6474 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6475 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6476 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6477 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6478 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6479 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6480 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6481 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6482 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6483 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6484 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6485 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6486 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6487 [EXIT_REASON_INVEPT
] = handle_invept
,
6490 static const int kvm_vmx_max_exit_handlers
=
6491 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6493 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6494 struct vmcs12
*vmcs12
)
6496 unsigned long exit_qualification
;
6497 gpa_t bitmap
, last_bitmap
;
6502 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6503 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6505 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6507 port
= exit_qualification
>> 16;
6508 size
= (exit_qualification
& 7) + 1;
6510 last_bitmap
= (gpa_t
)-1;
6515 bitmap
= vmcs12
->io_bitmap_a
;
6516 else if (port
< 0x10000)
6517 bitmap
= vmcs12
->io_bitmap_b
;
6520 bitmap
+= (port
& 0x7fff) / 8;
6522 if (last_bitmap
!= bitmap
)
6523 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6525 if (b
& (1 << (port
& 7)))
6530 last_bitmap
= bitmap
;
6537 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6538 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6539 * disinterest in the current event (read or write a specific MSR) by using an
6540 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6542 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6543 struct vmcs12
*vmcs12
, u32 exit_reason
)
6545 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6548 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6552 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6553 * for the four combinations of read/write and low/high MSR numbers.
6554 * First we need to figure out which of the four to use:
6556 bitmap
= vmcs12
->msr_bitmap
;
6557 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6559 if (msr_index
>= 0xc0000000) {
6560 msr_index
-= 0xc0000000;
6564 /* Then read the msr_index'th bit from this bitmap: */
6565 if (msr_index
< 1024*8) {
6567 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6569 return 1 & (b
>> (msr_index
& 7));
6571 return 1; /* let L1 handle the wrong parameter */
6575 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6576 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6577 * intercept (via guest_host_mask etc.) the current event.
6579 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6580 struct vmcs12
*vmcs12
)
6582 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6583 int cr
= exit_qualification
& 15;
6584 int reg
= (exit_qualification
>> 8) & 15;
6585 unsigned long val
= kvm_register_read(vcpu
, reg
);
6587 switch ((exit_qualification
>> 4) & 3) {
6588 case 0: /* mov to cr */
6591 if (vmcs12
->cr0_guest_host_mask
&
6592 (val
^ vmcs12
->cr0_read_shadow
))
6596 if ((vmcs12
->cr3_target_count
>= 1 &&
6597 vmcs12
->cr3_target_value0
== val
) ||
6598 (vmcs12
->cr3_target_count
>= 2 &&
6599 vmcs12
->cr3_target_value1
== val
) ||
6600 (vmcs12
->cr3_target_count
>= 3 &&
6601 vmcs12
->cr3_target_value2
== val
) ||
6602 (vmcs12
->cr3_target_count
>= 4 &&
6603 vmcs12
->cr3_target_value3
== val
))
6605 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6609 if (vmcs12
->cr4_guest_host_mask
&
6610 (vmcs12
->cr4_read_shadow
^ val
))
6614 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6620 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6621 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6624 case 1: /* mov from cr */
6627 if (vmcs12
->cpu_based_vm_exec_control
&
6628 CPU_BASED_CR3_STORE_EXITING
)
6632 if (vmcs12
->cpu_based_vm_exec_control
&
6633 CPU_BASED_CR8_STORE_EXITING
)
6640 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6641 * cr0. Other attempted changes are ignored, with no exit.
6643 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6644 (val
^ vmcs12
->cr0_read_shadow
))
6646 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6647 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6656 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6657 * should handle it ourselves in L0 (and then continue L2). Only call this
6658 * when in is_guest_mode (L2).
6660 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6662 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6663 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6664 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6665 u32 exit_reason
= vmx
->exit_reason
;
6667 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6668 vmcs_readl(EXIT_QUALIFICATION
),
6669 vmx
->idt_vectoring_info
,
6671 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6674 if (vmx
->nested
.nested_run_pending
)
6677 if (unlikely(vmx
->fail
)) {
6678 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6679 vmcs_read32(VM_INSTRUCTION_ERROR
));
6683 switch (exit_reason
) {
6684 case EXIT_REASON_EXCEPTION_NMI
:
6685 if (!is_exception(intr_info
))
6687 else if (is_page_fault(intr_info
))
6689 else if (is_no_device(intr_info
) &&
6690 !(nested_read_cr0(vmcs12
) & X86_CR0_TS
))
6692 return vmcs12
->exception_bitmap
&
6693 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6694 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6696 case EXIT_REASON_TRIPLE_FAULT
:
6698 case EXIT_REASON_PENDING_INTERRUPT
:
6699 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6700 case EXIT_REASON_NMI_WINDOW
:
6701 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6702 case EXIT_REASON_TASK_SWITCH
:
6704 case EXIT_REASON_CPUID
:
6706 case EXIT_REASON_HLT
:
6707 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6708 case EXIT_REASON_INVD
:
6710 case EXIT_REASON_INVLPG
:
6711 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6712 case EXIT_REASON_RDPMC
:
6713 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6714 case EXIT_REASON_RDTSC
:
6715 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6716 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6717 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6718 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6719 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6720 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6721 case EXIT_REASON_INVEPT
:
6723 * VMX instructions trap unconditionally. This allows L1 to
6724 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6727 case EXIT_REASON_CR_ACCESS
:
6728 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6729 case EXIT_REASON_DR_ACCESS
:
6730 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6731 case EXIT_REASON_IO_INSTRUCTION
:
6732 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6733 case EXIT_REASON_MSR_READ
:
6734 case EXIT_REASON_MSR_WRITE
:
6735 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6736 case EXIT_REASON_INVALID_STATE
:
6738 case EXIT_REASON_MWAIT_INSTRUCTION
:
6739 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6740 case EXIT_REASON_MONITOR_INSTRUCTION
:
6741 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6742 case EXIT_REASON_PAUSE_INSTRUCTION
:
6743 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6744 nested_cpu_has2(vmcs12
,
6745 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6746 case EXIT_REASON_MCE_DURING_VMENTRY
:
6748 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6750 case EXIT_REASON_APIC_ACCESS
:
6751 return nested_cpu_has2(vmcs12
,
6752 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6753 case EXIT_REASON_EPT_VIOLATION
:
6755 * L0 always deals with the EPT violation. If nested EPT is
6756 * used, and the nested mmu code discovers that the address is
6757 * missing in the guest EPT table (EPT12), the EPT violation
6758 * will be injected with nested_ept_inject_page_fault()
6761 case EXIT_REASON_EPT_MISCONFIG
:
6763 * L2 never uses directly L1's EPT, but rather L0's own EPT
6764 * table (shadow on EPT) or a merged EPT table that L0 built
6765 * (EPT on EPT). So any problems with the structure of the
6766 * table is L0's fault.
6769 case EXIT_REASON_PREEMPTION_TIMER
:
6770 return vmcs12
->pin_based_vm_exec_control
&
6771 PIN_BASED_VMX_PREEMPTION_TIMER
;
6772 case EXIT_REASON_WBINVD
:
6773 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6774 case EXIT_REASON_XSETBV
:
6781 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6783 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6784 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6787 static void nested_adjust_preemption_timer(struct kvm_vcpu
*vcpu
)
6790 u32 preempt_val_l1
, preempt_val_l2
, preempt_scale
;
6792 if (!(get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
6793 PIN_BASED_VMX_PREEMPTION_TIMER
))
6795 preempt_scale
= native_read_msr(MSR_IA32_VMX_MISC
) &
6796 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE
;
6797 preempt_val_l2
= vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
6798 delta_tsc_l1
= vmx_read_l1_tsc(vcpu
, native_read_tsc())
6799 - vcpu
->arch
.last_guest_tsc
;
6800 preempt_val_l1
= delta_tsc_l1
>> preempt_scale
;
6801 if (preempt_val_l2
<= preempt_val_l1
)
6804 preempt_val_l2
-= preempt_val_l1
;
6805 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, preempt_val_l2
);
6809 * The guest has exited. See if we can fix it or if we need userspace
6812 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6814 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6815 u32 exit_reason
= vmx
->exit_reason
;
6816 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6818 /* If guest state is invalid, start emulating */
6819 if (vmx
->emulation_required
)
6820 return handle_invalid_guest_state(vcpu
);
6822 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6823 nested_vmx_vmexit(vcpu
, exit_reason
,
6824 vmcs_read32(VM_EXIT_INTR_INFO
),
6825 vmcs_readl(EXIT_QUALIFICATION
));
6829 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6830 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6831 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6836 if (unlikely(vmx
->fail
)) {
6837 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6838 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6839 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6845 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6846 * delivery event since it indicates guest is accessing MMIO.
6847 * The vm-exit can be triggered again after return to guest that
6848 * will cause infinite loop.
6850 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6851 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6852 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6853 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6854 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6855 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6856 vcpu
->run
->internal
.ndata
= 2;
6857 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6858 vcpu
->run
->internal
.data
[1] = exit_reason
;
6862 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6863 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6864 get_vmcs12(vcpu
))))) {
6865 if (vmx_interrupt_allowed(vcpu
)) {
6866 vmx
->soft_vnmi_blocked
= 0;
6867 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6868 vcpu
->arch
.nmi_pending
) {
6870 * This CPU don't support us in finding the end of an
6871 * NMI-blocked window if the guest runs with IRQs
6872 * disabled. So we pull the trigger after 1 s of
6873 * futile waiting, but inform the user about this.
6875 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6876 "state on VCPU %d after 1 s timeout\n",
6877 __func__
, vcpu
->vcpu_id
);
6878 vmx
->soft_vnmi_blocked
= 0;
6882 if (exit_reason
< kvm_vmx_max_exit_handlers
6883 && kvm_vmx_exit_handlers
[exit_reason
])
6884 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6886 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6887 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6892 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6894 if (irr
== -1 || tpr
< irr
) {
6895 vmcs_write32(TPR_THRESHOLD
, 0);
6899 vmcs_write32(TPR_THRESHOLD
, irr
);
6902 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6904 u32 sec_exec_control
;
6907 * There is not point to enable virtualize x2apic without enable
6910 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6911 !vmx_vm_has_apicv(vcpu
->kvm
))
6914 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6917 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6920 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6921 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6923 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6924 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6926 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6928 vmx_set_msr_bitmap(vcpu
);
6931 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6936 if (!vmx_vm_has_apicv(kvm
))
6942 status
= vmcs_read16(GUEST_INTR_STATUS
);
6947 vmcs_write16(GUEST_INTR_STATUS
, status
);
6951 static void vmx_set_rvi(int vector
)
6956 status
= vmcs_read16(GUEST_INTR_STATUS
);
6957 old
= (u8
)status
& 0xff;
6958 if ((u8
)vector
!= old
) {
6960 status
|= (u8
)vector
;
6961 vmcs_write16(GUEST_INTR_STATUS
, status
);
6965 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6970 vmx_set_rvi(max_irr
);
6973 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6975 if (!vmx_vm_has_apicv(vcpu
->kvm
))
6978 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6979 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6980 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6981 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6984 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6988 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6989 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6992 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6993 exit_intr_info
= vmx
->exit_intr_info
;
6995 /* Handle machine checks before interrupts are enabled */
6996 if (is_machine_check(exit_intr_info
))
6997 kvm_machine_check();
6999 /* We need to handle NMIs before interrupts are enabled */
7000 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7001 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7002 kvm_before_handle_nmi(&vmx
->vcpu
);
7004 kvm_after_handle_nmi(&vmx
->vcpu
);
7008 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7010 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7013 * If external interrupt exists, IF bit is set in rflags/eflags on the
7014 * interrupt stack frame, and interrupt will be enabled on a return
7015 * from interrupt handler.
7017 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7018 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7019 unsigned int vector
;
7020 unsigned long entry
;
7022 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7023 #ifdef CONFIG_X86_64
7027 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7028 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7029 entry
= gate_offset(*desc
);
7031 #ifdef CONFIG_X86_64
7032 "mov %%" _ASM_SP
", %[sp]\n\t"
7033 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7038 "orl $0x200, (%%" _ASM_SP
")\n\t"
7039 __ASM_SIZE(push
) " $%c[cs]\n\t"
7040 "call *%[entry]\n\t"
7042 #ifdef CONFIG_X86_64
7047 [ss
]"i"(__KERNEL_DS
),
7048 [cs
]"i"(__KERNEL_CS
)
7054 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7059 bool idtv_info_valid
;
7061 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7063 if (cpu_has_virtual_nmis()) {
7064 if (vmx
->nmi_known_unmasked
)
7067 * Can't use vmx->exit_intr_info since we're not sure what
7068 * the exit reason is.
7070 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7071 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7072 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7074 * SDM 3: 27.7.1.2 (September 2008)
7075 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7076 * a guest IRET fault.
7077 * SDM 3: 23.2.2 (September 2008)
7078 * Bit 12 is undefined in any of the following cases:
7079 * If the VM exit sets the valid bit in the IDT-vectoring
7080 * information field.
7081 * If the VM exit is due to a double fault.
7083 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7084 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7085 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7086 GUEST_INTR_STATE_NMI
);
7088 vmx
->nmi_known_unmasked
=
7089 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7090 & GUEST_INTR_STATE_NMI
);
7091 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7092 vmx
->vnmi_blocked_time
+=
7093 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7096 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7097 u32 idt_vectoring_info
,
7098 int instr_len_field
,
7099 int error_code_field
)
7103 bool idtv_info_valid
;
7105 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7107 vcpu
->arch
.nmi_injected
= false;
7108 kvm_clear_exception_queue(vcpu
);
7109 kvm_clear_interrupt_queue(vcpu
);
7111 if (!idtv_info_valid
)
7114 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7116 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7117 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7120 case INTR_TYPE_NMI_INTR
:
7121 vcpu
->arch
.nmi_injected
= true;
7123 * SDM 3: 27.7.1.2 (September 2008)
7124 * Clear bit "block by NMI" before VM entry if a NMI
7127 vmx_set_nmi_mask(vcpu
, false);
7129 case INTR_TYPE_SOFT_EXCEPTION
:
7130 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7132 case INTR_TYPE_HARD_EXCEPTION
:
7133 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7134 u32 err
= vmcs_read32(error_code_field
);
7135 kvm_requeue_exception_e(vcpu
, vector
, err
);
7137 kvm_requeue_exception(vcpu
, vector
);
7139 case INTR_TYPE_SOFT_INTR
:
7140 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7142 case INTR_TYPE_EXT_INTR
:
7143 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7150 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7152 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7153 VM_EXIT_INSTRUCTION_LEN
,
7154 IDT_VECTORING_ERROR_CODE
);
7157 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7159 __vmx_complete_interrupts(vcpu
,
7160 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7161 VM_ENTRY_INSTRUCTION_LEN
,
7162 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7164 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7167 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7170 struct perf_guest_switch_msr
*msrs
;
7172 msrs
= perf_guest_get_msrs(&nr_msrs
);
7177 for (i
= 0; i
< nr_msrs
; i
++)
7178 if (msrs
[i
].host
== msrs
[i
].guest
)
7179 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7181 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7185 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7187 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7188 unsigned long debugctlmsr
;
7190 /* Record the guest's net vcpu time for enforced NMI injections. */
7191 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7192 vmx
->entry_time
= ktime_get();
7194 /* Don't enter VMX if guest state is invalid, let the exit handler
7195 start emulation until we arrive back to a valid state */
7196 if (vmx
->emulation_required
)
7199 if (vmx
->nested
.sync_shadow_vmcs
) {
7200 copy_vmcs12_to_shadow(vmx
);
7201 vmx
->nested
.sync_shadow_vmcs
= false;
7204 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7205 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7206 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7207 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7209 /* When single-stepping over STI and MOV SS, we must clear the
7210 * corresponding interruptibility bits in the guest state. Otherwise
7211 * vmentry fails as it then expects bit 14 (BS) in pending debug
7212 * exceptions being set, but that's not correct for the guest debugging
7214 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7215 vmx_set_interrupt_shadow(vcpu
, 0);
7217 atomic_switch_perf_msrs(vmx
);
7218 debugctlmsr
= get_debugctlmsr();
7220 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
)
7221 nested_adjust_preemption_timer(vcpu
);
7222 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7224 /* Store host registers */
7225 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7226 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7227 "push %%" _ASM_CX
" \n\t"
7228 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7230 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7231 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7233 /* Reload cr2 if changed */
7234 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7235 "mov %%cr2, %%" _ASM_DX
" \n\t"
7236 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7238 "mov %%" _ASM_AX
", %%cr2 \n\t"
7240 /* Check if vmlaunch of vmresume is needed */
7241 "cmpl $0, %c[launched](%0) \n\t"
7242 /* Load guest registers. Don't clobber flags. */
7243 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7244 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7245 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7246 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7247 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7248 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7249 #ifdef CONFIG_X86_64
7250 "mov %c[r8](%0), %%r8 \n\t"
7251 "mov %c[r9](%0), %%r9 \n\t"
7252 "mov %c[r10](%0), %%r10 \n\t"
7253 "mov %c[r11](%0), %%r11 \n\t"
7254 "mov %c[r12](%0), %%r12 \n\t"
7255 "mov %c[r13](%0), %%r13 \n\t"
7256 "mov %c[r14](%0), %%r14 \n\t"
7257 "mov %c[r15](%0), %%r15 \n\t"
7259 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7261 /* Enter guest mode */
7263 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7265 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7267 /* Save guest registers, load host registers, keep flags */
7268 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7270 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7271 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7272 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7273 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7274 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7275 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7276 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7277 #ifdef CONFIG_X86_64
7278 "mov %%r8, %c[r8](%0) \n\t"
7279 "mov %%r9, %c[r9](%0) \n\t"
7280 "mov %%r10, %c[r10](%0) \n\t"
7281 "mov %%r11, %c[r11](%0) \n\t"
7282 "mov %%r12, %c[r12](%0) \n\t"
7283 "mov %%r13, %c[r13](%0) \n\t"
7284 "mov %%r14, %c[r14](%0) \n\t"
7285 "mov %%r15, %c[r15](%0) \n\t"
7287 "mov %%cr2, %%" _ASM_AX
" \n\t"
7288 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7290 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7291 "setbe %c[fail](%0) \n\t"
7292 ".pushsection .rodata \n\t"
7293 ".global vmx_return \n\t"
7294 "vmx_return: " _ASM_PTR
" 2b \n\t"
7296 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7297 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7298 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7299 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7300 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7301 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7302 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7303 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7304 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7305 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7306 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7307 #ifdef CONFIG_X86_64
7308 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7309 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7310 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7311 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7312 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7313 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7314 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7315 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7317 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7318 [wordsize
]"i"(sizeof(ulong
))
7320 #ifdef CONFIG_X86_64
7321 , "rax", "rbx", "rdi", "rsi"
7322 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7324 , "eax", "ebx", "edi", "esi"
7328 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7330 update_debugctlmsr(debugctlmsr
);
7332 #ifndef CONFIG_X86_64
7334 * The sysexit path does not restore ds/es, so we must set them to
7335 * a reasonable value ourselves.
7337 * We can't defer this to vmx_load_host_state() since that function
7338 * may be executed in interrupt context, which saves and restore segments
7339 * around it, nullifying its effect.
7341 loadsegment(ds
, __USER_DS
);
7342 loadsegment(es
, __USER_DS
);
7345 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7346 | (1 << VCPU_EXREG_RFLAGS
)
7347 | (1 << VCPU_EXREG_CPL
)
7348 | (1 << VCPU_EXREG_PDPTR
)
7349 | (1 << VCPU_EXREG_SEGMENTS
)
7350 | (1 << VCPU_EXREG_CR3
));
7351 vcpu
->arch
.regs_dirty
= 0;
7353 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7355 vmx
->loaded_vmcs
->launched
= 1;
7357 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7358 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7361 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7362 * we did not inject a still-pending event to L1 now because of
7363 * nested_run_pending, we need to re-enable this bit.
7365 if (vmx
->nested
.nested_run_pending
)
7366 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7368 vmx
->nested
.nested_run_pending
= 0;
7370 vmx_complete_atomic_exit(vmx
);
7371 vmx_recover_nmi_blocking(vmx
);
7372 vmx_complete_interrupts(vmx
);
7375 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7377 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7380 free_loaded_vmcs(vmx
->loaded_vmcs
);
7382 kfree(vmx
->guest_msrs
);
7383 kvm_vcpu_uninit(vcpu
);
7384 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7387 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7390 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7394 return ERR_PTR(-ENOMEM
);
7398 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7402 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7404 if (!vmx
->guest_msrs
) {
7408 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7409 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7410 if (!vmx
->loaded_vmcs
->vmcs
)
7413 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7414 loaded_vmcs_init(vmx
->loaded_vmcs
);
7419 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7420 vmx
->vcpu
.cpu
= cpu
;
7421 err
= vmx_vcpu_setup(vmx
);
7422 vmx_vcpu_put(&vmx
->vcpu
);
7426 if (vm_need_virtualize_apic_accesses(kvm
)) {
7427 err
= alloc_apic_access_page(kvm
);
7433 if (!kvm
->arch
.ept_identity_map_addr
)
7434 kvm
->arch
.ept_identity_map_addr
=
7435 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7437 if (alloc_identity_pagetable(kvm
) != 0)
7439 if (!init_rmode_identity_map(kvm
))
7443 vmx
->nested
.current_vmptr
= -1ull;
7444 vmx
->nested
.current_vmcs12
= NULL
;
7449 free_loaded_vmcs(vmx
->loaded_vmcs
);
7451 kfree(vmx
->guest_msrs
);
7453 kvm_vcpu_uninit(&vmx
->vcpu
);
7456 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7457 return ERR_PTR(err
);
7460 static void __init
vmx_check_processor_compat(void *rtn
)
7462 struct vmcs_config vmcs_conf
;
7465 if (setup_vmcs_config(&vmcs_conf
) < 0)
7467 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7468 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7469 smp_processor_id());
7474 static int get_ept_level(void)
7476 return VMX_EPT_DEFAULT_GAW
+ 1;
7479 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7483 /* For VT-d and EPT combination
7484 * 1. MMIO: always map as UC
7486 * a. VT-d without snooping control feature: can't guarantee the
7487 * result, try to trust guest.
7488 * b. VT-d with snooping control feature: snooping control feature of
7489 * VT-d engine can guarantee the cache correctness. Just set it
7490 * to WB to keep consistent with host. So the same as item 3.
7491 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7492 * consistent with host MTRR
7495 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7496 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7497 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7498 VMX_EPT_MT_EPTE_SHIFT
;
7500 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7506 static int vmx_get_lpage_level(void)
7508 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7509 return PT_DIRECTORY_LEVEL
;
7511 /* For shadow and EPT supported 1GB page */
7512 return PT_PDPE_LEVEL
;
7515 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7517 struct kvm_cpuid_entry2
*best
;
7518 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7521 vmx
->rdtscp_enabled
= false;
7522 if (vmx_rdtscp_supported()) {
7523 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7524 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7525 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7526 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7527 vmx
->rdtscp_enabled
= true;
7529 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7530 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7536 /* Exposing INVPCID only when PCID is exposed */
7537 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7538 if (vmx_invpcid_supported() &&
7539 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7540 guest_cpuid_has_pcid(vcpu
)) {
7541 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7542 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7543 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7546 if (cpu_has_secondary_exec_ctrls()) {
7547 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7548 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7549 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7553 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7557 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7559 if (func
== 1 && nested
)
7560 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7563 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7564 struct x86_exception
*fault
)
7566 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7569 if (fault
->error_code
& PFERR_RSVD_MASK
)
7570 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7572 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7573 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7574 vmcs12
->guest_physical_address
= fault
->address
;
7577 /* Callbacks for nested_ept_init_mmu_context: */
7579 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7581 /* return the page table to be shadowed - in our case, EPT12 */
7582 return get_vmcs12(vcpu
)->ept_pointer
;
7585 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7587 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7588 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7590 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7591 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7592 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7594 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7597 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7599 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7602 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7603 struct x86_exception
*fault
)
7605 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7607 WARN_ON(!is_guest_mode(vcpu
));
7609 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7610 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7611 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7612 vmcs_read32(VM_EXIT_INTR_INFO
),
7613 vmcs_readl(EXIT_QUALIFICATION
));
7615 kvm_inject_page_fault(vcpu
, fault
);
7619 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7620 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7621 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7622 * guest in a way that will both be appropriate to L1's requests, and our
7623 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7624 * function also has additional necessary side-effects, like setting various
7625 * vcpu->arch fields.
7627 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7629 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7633 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7634 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7635 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7636 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7637 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7638 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7639 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7640 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7641 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7642 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7643 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7644 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7645 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7646 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7647 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7648 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7649 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7650 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7651 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7652 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7653 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7654 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7655 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7656 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7657 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7658 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7659 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7660 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7661 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7662 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7663 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7664 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7665 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7666 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7667 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7668 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7670 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7671 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7672 vmcs12
->vm_entry_intr_info_field
);
7673 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7674 vmcs12
->vm_entry_exception_error_code
);
7675 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7676 vmcs12
->vm_entry_instruction_len
);
7677 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7678 vmcs12
->guest_interruptibility_info
);
7679 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7680 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7681 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7682 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7683 vmcs12
->guest_pending_dbg_exceptions
);
7684 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7685 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7687 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7689 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7690 (vmcs_config
.pin_based_exec_ctrl
|
7691 vmcs12
->pin_based_vm_exec_control
));
7693 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7694 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7695 vmcs12
->vmx_preemption_timer_value
);
7698 * Whether page-faults are trapped is determined by a combination of
7699 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7700 * If enable_ept, L0 doesn't care about page faults and we should
7701 * set all of these to L1's desires. However, if !enable_ept, L0 does
7702 * care about (at least some) page faults, and because it is not easy
7703 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7704 * to exit on each and every L2 page fault. This is done by setting
7705 * MASK=MATCH=0 and (see below) EB.PF=1.
7706 * Note that below we don't need special code to set EB.PF beyond the
7707 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7708 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7709 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7711 * A problem with this approach (when !enable_ept) is that L1 may be
7712 * injected with more page faults than it asked for. This could have
7713 * caused problems, but in practice existing hypervisors don't care.
7714 * To fix this, we will need to emulate the PFEC checking (on the L1
7715 * page tables), using walk_addr(), when injecting PFs to L1.
7717 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7718 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7719 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7720 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7722 if (cpu_has_secondary_exec_ctrls()) {
7723 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7724 if (!vmx
->rdtscp_enabled
)
7725 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7726 /* Take the following fields only from vmcs12 */
7727 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7728 if (nested_cpu_has(vmcs12
,
7729 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7730 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7732 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7734 * Translate L1 physical address to host physical
7735 * address for vmcs02. Keep the page pinned, so this
7736 * physical address remains valid. We keep a reference
7737 * to it so we can release it later.
7739 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7740 nested_release_page(vmx
->nested
.apic_access_page
);
7741 vmx
->nested
.apic_access_page
=
7742 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7744 * If translation failed, no matter: This feature asks
7745 * to exit when accessing the given address, and if it
7746 * can never be accessed, this feature won't do
7749 if (!vmx
->nested
.apic_access_page
)
7751 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7753 vmcs_write64(APIC_ACCESS_ADDR
,
7754 page_to_phys(vmx
->nested
.apic_access_page
));
7755 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
7757 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7758 vmcs_write64(APIC_ACCESS_ADDR
,
7759 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
7762 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7767 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7768 * Some constant fields are set here by vmx_set_constant_host_state().
7769 * Other fields are different per CPU, and will be set later when
7770 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7772 vmx_set_constant_host_state(vmx
);
7775 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7776 * entry, but only if the current (host) sp changed from the value
7777 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7778 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7779 * here we just force the write to happen on entry.
7783 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7784 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7785 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7786 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7787 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7789 * Merging of IO and MSR bitmaps not currently supported.
7790 * Rather, exit every time.
7792 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7793 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7794 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7796 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7798 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7799 * bitwise-or of what L1 wants to trap for L2, and what we want to
7800 * trap. Note that CR0.TS also needs updating - we do this later.
7802 update_exception_bitmap(vcpu
);
7803 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7804 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7806 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7807 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7808 * bits are further modified by vmx_set_efer() below.
7810 exit_control
= vmcs_config
.vmexit_ctrl
;
7811 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7812 exit_control
|= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
7813 vm_exit_controls_init(vmx
, exit_control
);
7815 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7816 * emulated by vmx_set_efer(), below.
7818 vm_entry_controls_init(vmx
,
7819 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7820 ~VM_ENTRY_IA32E_MODE
) |
7821 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7823 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7824 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7825 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7826 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7827 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7830 set_cr4_guest_host_mask(vmx
);
7832 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7833 vmcs_write64(TSC_OFFSET
,
7834 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7836 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7840 * Trivially support vpid by letting L2s share their parent
7841 * L1's vpid. TODO: move to a more elaborate solution, giving
7842 * each L2 its own vpid and exposing the vpid feature to L1.
7844 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7845 vmx_flush_tlb(vcpu
);
7848 if (nested_cpu_has_ept(vmcs12
)) {
7849 kvm_mmu_unload(vcpu
);
7850 nested_ept_init_mmu_context(vcpu
);
7853 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7854 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7855 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7856 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7858 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7859 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7860 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7863 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7864 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7865 * The CR0_READ_SHADOW is what L2 should have expected to read given
7866 * the specifications by L1; It's not enough to take
7867 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7868 * have more bits than L1 expected.
7870 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7871 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7873 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7874 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7876 /* shadow page tables on either EPT or shadow page tables */
7877 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7878 kvm_mmu_reset_context(vcpu
);
7881 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7884 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7887 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7888 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7889 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7890 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7893 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7894 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7898 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7899 * for running an L2 nested guest.
7901 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7903 struct vmcs12
*vmcs12
;
7904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7906 struct loaded_vmcs
*vmcs02
;
7909 if (!nested_vmx_check_permission(vcpu
) ||
7910 !nested_vmx_check_vmcs12(vcpu
))
7913 skip_emulated_instruction(vcpu
);
7914 vmcs12
= get_vmcs12(vcpu
);
7916 if (enable_shadow_vmcs
)
7917 copy_shadow_to_vmcs12(vmx
);
7920 * The nested entry process starts with enforcing various prerequisites
7921 * on vmcs12 as required by the Intel SDM, and act appropriately when
7922 * they fail: As the SDM explains, some conditions should cause the
7923 * instruction to fail, while others will cause the instruction to seem
7924 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7925 * To speed up the normal (success) code path, we should avoid checking
7926 * for misconfigurations which will anyway be caught by the processor
7927 * when using the merged vmcs02.
7929 if (vmcs12
->launch_state
== launch
) {
7930 nested_vmx_failValid(vcpu
,
7931 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7932 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7936 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
7937 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
7938 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7942 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7943 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7944 /*TODO: Also verify bits beyond physical address width are 0*/
7945 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7949 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7950 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7951 /*TODO: Also verify bits beyond physical address width are 0*/
7952 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7956 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7957 vmcs12
->vm_exit_msr_load_count
> 0 ||
7958 vmcs12
->vm_exit_msr_store_count
> 0) {
7959 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7961 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7965 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7966 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7967 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7968 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7969 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7970 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7971 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7972 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7973 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7974 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7976 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7980 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7981 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7982 nested_vmx_failValid(vcpu
,
7983 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7987 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
7988 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7989 nested_vmx_entry_failure(vcpu
, vmcs12
,
7990 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7993 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7994 nested_vmx_entry_failure(vcpu
, vmcs12
,
7995 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8000 * If the load IA32_EFER VM-entry control is 1, the following checks
8001 * are performed on the field for the IA32_EFER MSR:
8002 * - Bits reserved in the IA32_EFER MSR must be 0.
8003 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8004 * the IA-32e mode guest VM-exit control. It must also be identical
8005 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8008 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8009 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8010 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8011 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8012 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8013 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8014 nested_vmx_entry_failure(vcpu
, vmcs12
,
8015 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8021 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8022 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8023 * the values of the LMA and LME bits in the field must each be that of
8024 * the host address-space size VM-exit control.
8026 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8027 ia32e
= (vmcs12
->vm_exit_controls
&
8028 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8029 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8030 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8031 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8032 nested_vmx_entry_failure(vcpu
, vmcs12
,
8033 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8039 * We're finally done with prerequisite checking, and can start with
8043 vmcs02
= nested_get_current_vmcs02(vmx
);
8047 enter_guest_mode(vcpu
);
8049 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8052 vmx
->loaded_vmcs
= vmcs02
;
8054 vmx_vcpu_load(vcpu
, cpu
);
8058 vmx_segment_cache_clear(vmx
);
8060 vmcs12
->launch_state
= 1;
8062 prepare_vmcs02(vcpu
, vmcs12
);
8064 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8065 return kvm_emulate_halt(vcpu
);
8067 vmx
->nested
.nested_run_pending
= 1;
8070 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8071 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8072 * returned as far as L1 is concerned. It will only return (and set
8073 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8079 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8080 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8081 * This function returns the new value we should put in vmcs12.guest_cr0.
8082 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8083 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8084 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8085 * didn't trap the bit, because if L1 did, so would L0).
8086 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8087 * been modified by L2, and L1 knows it. So just leave the old value of
8088 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8089 * isn't relevant, because if L0 traps this bit it can set it to anything.
8090 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8091 * changed these bits, and therefore they need to be updated, but L0
8092 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8093 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8095 static inline unsigned long
8096 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8099 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8100 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8101 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8102 vcpu
->arch
.cr0_guest_owned_bits
));
8105 static inline unsigned long
8106 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8109 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8110 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8111 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8112 vcpu
->arch
.cr4_guest_owned_bits
));
8115 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8116 struct vmcs12
*vmcs12
)
8121 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8122 nr
= vcpu
->arch
.exception
.nr
;
8123 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8125 if (kvm_exception_is_soft(nr
)) {
8126 vmcs12
->vm_exit_instruction_len
=
8127 vcpu
->arch
.event_exit_inst_len
;
8128 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8130 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8132 if (vcpu
->arch
.exception
.has_error_code
) {
8133 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8134 vmcs12
->idt_vectoring_error_code
=
8135 vcpu
->arch
.exception
.error_code
;
8138 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8139 } else if (vcpu
->arch
.nmi_injected
) {
8140 vmcs12
->idt_vectoring_info_field
=
8141 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8142 } else if (vcpu
->arch
.interrupt
.pending
) {
8143 nr
= vcpu
->arch
.interrupt
.nr
;
8144 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8146 if (vcpu
->arch
.interrupt
.soft
) {
8147 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8148 vmcs12
->vm_entry_instruction_len
=
8149 vcpu
->arch
.event_exit_inst_len
;
8151 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8153 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8158 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8159 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8160 * and this function updates it to reflect the changes to the guest state while
8161 * L2 was running (and perhaps made some exits which were handled directly by L0
8162 * without going back to L1), and to reflect the exit reason.
8163 * Note that we do not have to copy here all VMCS fields, just those that
8164 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8165 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8166 * which already writes to vmcs12 directly.
8168 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8169 u32 exit_reason
, u32 exit_intr_info
,
8170 unsigned long exit_qualification
)
8172 /* update guest state fields: */
8173 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8174 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8176 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8177 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8178 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8179 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8181 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8182 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8183 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8184 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8185 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8186 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8187 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8188 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8189 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8190 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8191 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8192 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8193 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8194 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8195 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8196 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8197 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8198 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8199 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8200 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8201 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8202 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8203 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8204 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8205 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8206 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8207 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8208 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8209 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8210 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8211 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8212 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8213 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8214 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8215 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8216 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8218 vmcs12
->guest_interruptibility_info
=
8219 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8220 vmcs12
->guest_pending_dbg_exceptions
=
8221 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8222 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8223 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8225 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8227 if ((vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
) &&
8228 (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
))
8229 vmcs12
->vmx_preemption_timer_value
=
8230 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
8233 * In some cases (usually, nested EPT), L2 is allowed to change its
8234 * own CR3 without exiting. If it has changed it, we must keep it.
8235 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8236 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8238 * Additionally, restore L2's PDPTR to vmcs12.
8241 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8242 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8243 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8244 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8245 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8248 vmcs12
->vm_entry_controls
=
8249 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8250 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8252 /* TODO: These cannot have changed unless we have MSR bitmaps and
8253 * the relevant bit asks not to trap the change */
8254 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8255 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8256 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8257 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8258 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8259 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8260 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8261 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8263 /* update exit information fields: */
8265 vmcs12
->vm_exit_reason
= exit_reason
;
8266 vmcs12
->exit_qualification
= exit_qualification
;
8268 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8269 if ((vmcs12
->vm_exit_intr_info
&
8270 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8271 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8272 vmcs12
->vm_exit_intr_error_code
=
8273 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8274 vmcs12
->idt_vectoring_info_field
= 0;
8275 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8276 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8278 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8279 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8280 * instead of reading the real value. */
8281 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8284 * Transfer the event that L0 or L1 may wanted to inject into
8285 * L2 to IDT_VECTORING_INFO_FIELD.
8287 vmcs12_save_pending_event(vcpu
, vmcs12
);
8291 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8292 * preserved above and would only end up incorrectly in L1.
8294 vcpu
->arch
.nmi_injected
= false;
8295 kvm_clear_exception_queue(vcpu
);
8296 kvm_clear_interrupt_queue(vcpu
);
8300 * A part of what we need to when the nested L2 guest exits and we want to
8301 * run its L1 parent, is to reset L1's guest state to the host state specified
8303 * This function is to be called not only on normal nested exit, but also on
8304 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8305 * Failures During or After Loading Guest State").
8306 * This function should be called when the active VMCS is L1's (vmcs01).
8308 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8309 struct vmcs12
*vmcs12
)
8311 struct kvm_segment seg
;
8313 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8314 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8315 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8316 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8318 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8319 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8321 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8322 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8323 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8325 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8326 * actually changed, because it depends on the current state of
8327 * fpu_active (which may have changed).
8328 * Note that vmx_set_cr0 refers to efer set above.
8330 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8332 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8333 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8334 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8336 update_exception_bitmap(vcpu
);
8337 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8338 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8341 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8342 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8344 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8345 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8347 nested_ept_uninit_mmu_context(vcpu
);
8349 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8350 kvm_mmu_reset_context(vcpu
);
8353 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8357 * Trivially support vpid by letting L2s share their parent
8358 * L1's vpid. TODO: move to a more elaborate solution, giving
8359 * each L2 its own vpid and exposing the vpid feature to L1.
8361 vmx_flush_tlb(vcpu
);
8365 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8366 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8367 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8368 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8369 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8371 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8372 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8373 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8375 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8376 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8377 vmcs12
->host_ia32_perf_global_ctrl
);
8379 /* Set L1 segment info according to Intel SDM
8380 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8381 seg
= (struct kvm_segment
) {
8383 .limit
= 0xFFFFFFFF,
8384 .selector
= vmcs12
->host_cs_selector
,
8390 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8394 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8395 seg
= (struct kvm_segment
) {
8397 .limit
= 0xFFFFFFFF,
8404 seg
.selector
= vmcs12
->host_ds_selector
;
8405 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8406 seg
.selector
= vmcs12
->host_es_selector
;
8407 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8408 seg
.selector
= vmcs12
->host_ss_selector
;
8409 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8410 seg
.selector
= vmcs12
->host_fs_selector
;
8411 seg
.base
= vmcs12
->host_fs_base
;
8412 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8413 seg
.selector
= vmcs12
->host_gs_selector
;
8414 seg
.base
= vmcs12
->host_gs_base
;
8415 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8416 seg
= (struct kvm_segment
) {
8417 .base
= vmcs12
->host_tr_base
,
8419 .selector
= vmcs12
->host_tr_selector
,
8423 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8425 kvm_set_dr(vcpu
, 7, 0x400);
8426 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8430 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8431 * and modify vmcs12 to make it see what it would expect to see there if
8432 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8434 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8436 unsigned long exit_qualification
)
8438 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8440 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8442 /* trying to cancel vmlaunch/vmresume is a bug */
8443 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8445 leave_guest_mode(vcpu
);
8446 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8447 exit_qualification
);
8449 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8450 vmcs12
->exit_qualification
,
8451 vmcs12
->idt_vectoring_info_field
,
8452 vmcs12
->vm_exit_intr_info
,
8453 vmcs12
->vm_exit_intr_error_code
,
8457 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8459 vmx_vcpu_load(vcpu
, cpu
);
8463 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8464 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8465 vmx_segment_cache_clear(vmx
);
8467 /* if no vmcs02 cache requested, remove the one we used */
8468 if (VMCS02_POOL_SIZE
== 0)
8469 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8471 load_vmcs12_host_state(vcpu
, vmcs12
);
8473 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8474 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8476 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8479 /* Unpin physical memory we referred to in vmcs02 */
8480 if (vmx
->nested
.apic_access_page
) {
8481 nested_release_page(vmx
->nested
.apic_access_page
);
8482 vmx
->nested
.apic_access_page
= 0;
8486 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8487 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8488 * success or failure flag accordingly.
8490 if (unlikely(vmx
->fail
)) {
8492 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8494 nested_vmx_succeed(vcpu
);
8495 if (enable_shadow_vmcs
)
8496 vmx
->nested
.sync_shadow_vmcs
= true;
8500 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8502 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8504 if (is_guest_mode(vcpu
))
8505 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8506 free_nested(to_vmx(vcpu
));
8510 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8511 * 23.7 "VM-entry failures during or after loading guest state" (this also
8512 * lists the acceptable exit-reason and exit-qualification parameters).
8513 * It should only be called before L2 actually succeeded to run, and when
8514 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8516 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8517 struct vmcs12
*vmcs12
,
8518 u32 reason
, unsigned long qualification
)
8520 load_vmcs12_host_state(vcpu
, vmcs12
);
8521 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8522 vmcs12
->exit_qualification
= qualification
;
8523 nested_vmx_succeed(vcpu
);
8524 if (enable_shadow_vmcs
)
8525 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8528 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8529 struct x86_instruction_info
*info
,
8530 enum x86_intercept_stage stage
)
8532 return X86EMUL_CONTINUE
;
8535 static struct kvm_x86_ops vmx_x86_ops
= {
8536 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8537 .disabled_by_bios
= vmx_disabled_by_bios
,
8538 .hardware_setup
= hardware_setup
,
8539 .hardware_unsetup
= hardware_unsetup
,
8540 .check_processor_compatibility
= vmx_check_processor_compat
,
8541 .hardware_enable
= hardware_enable
,
8542 .hardware_disable
= hardware_disable
,
8543 .cpu_has_accelerated_tpr
= report_flexpriority
,
8545 .vcpu_create
= vmx_create_vcpu
,
8546 .vcpu_free
= vmx_free_vcpu
,
8547 .vcpu_reset
= vmx_vcpu_reset
,
8549 .prepare_guest_switch
= vmx_save_host_state
,
8550 .vcpu_load
= vmx_vcpu_load
,
8551 .vcpu_put
= vmx_vcpu_put
,
8553 .update_db_bp_intercept
= update_exception_bitmap
,
8554 .get_msr
= vmx_get_msr
,
8555 .set_msr
= vmx_set_msr
,
8556 .get_segment_base
= vmx_get_segment_base
,
8557 .get_segment
= vmx_get_segment
,
8558 .set_segment
= vmx_set_segment
,
8559 .get_cpl
= vmx_get_cpl
,
8560 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8561 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8562 .decache_cr3
= vmx_decache_cr3
,
8563 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8564 .set_cr0
= vmx_set_cr0
,
8565 .set_cr3
= vmx_set_cr3
,
8566 .set_cr4
= vmx_set_cr4
,
8567 .set_efer
= vmx_set_efer
,
8568 .get_idt
= vmx_get_idt
,
8569 .set_idt
= vmx_set_idt
,
8570 .get_gdt
= vmx_get_gdt
,
8571 .set_gdt
= vmx_set_gdt
,
8572 .get_dr6
= vmx_get_dr6
,
8573 .set_dr6
= vmx_set_dr6
,
8574 .set_dr7
= vmx_set_dr7
,
8575 .cache_reg
= vmx_cache_reg
,
8576 .get_rflags
= vmx_get_rflags
,
8577 .set_rflags
= vmx_set_rflags
,
8578 .fpu_activate
= vmx_fpu_activate
,
8579 .fpu_deactivate
= vmx_fpu_deactivate
,
8581 .tlb_flush
= vmx_flush_tlb
,
8583 .run
= vmx_vcpu_run
,
8584 .handle_exit
= vmx_handle_exit
,
8585 .skip_emulated_instruction
= skip_emulated_instruction
,
8586 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8587 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8588 .patch_hypercall
= vmx_patch_hypercall
,
8589 .set_irq
= vmx_inject_irq
,
8590 .set_nmi
= vmx_inject_nmi
,
8591 .queue_exception
= vmx_queue_exception
,
8592 .cancel_injection
= vmx_cancel_injection
,
8593 .interrupt_allowed
= vmx_interrupt_allowed
,
8594 .nmi_allowed
= vmx_nmi_allowed
,
8595 .get_nmi_mask
= vmx_get_nmi_mask
,
8596 .set_nmi_mask
= vmx_set_nmi_mask
,
8597 .enable_nmi_window
= enable_nmi_window
,
8598 .enable_irq_window
= enable_irq_window
,
8599 .update_cr8_intercept
= update_cr8_intercept
,
8600 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8601 .vm_has_apicv
= vmx_vm_has_apicv
,
8602 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8603 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8604 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8605 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8606 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8608 .set_tss_addr
= vmx_set_tss_addr
,
8609 .get_tdp_level
= get_ept_level
,
8610 .get_mt_mask
= vmx_get_mt_mask
,
8612 .get_exit_info
= vmx_get_exit_info
,
8614 .get_lpage_level
= vmx_get_lpage_level
,
8616 .cpuid_update
= vmx_cpuid_update
,
8618 .rdtscp_supported
= vmx_rdtscp_supported
,
8619 .invpcid_supported
= vmx_invpcid_supported
,
8621 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8623 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8625 .set_tsc_khz
= vmx_set_tsc_khz
,
8626 .read_tsc_offset
= vmx_read_tsc_offset
,
8627 .write_tsc_offset
= vmx_write_tsc_offset
,
8628 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8629 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8630 .read_l1_tsc
= vmx_read_l1_tsc
,
8632 .set_tdp_cr3
= vmx_set_cr3
,
8634 .check_intercept
= vmx_check_intercept
,
8635 .handle_external_intr
= vmx_handle_external_intr
,
8638 static int __init
vmx_init(void)
8642 rdmsrl_safe(MSR_EFER
, &host_efer
);
8644 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8645 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8647 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8648 if (!vmx_io_bitmap_a
)
8653 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8654 if (!vmx_io_bitmap_b
)
8657 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8658 if (!vmx_msr_bitmap_legacy
)
8661 vmx_msr_bitmap_legacy_x2apic
=
8662 (unsigned long *)__get_free_page(GFP_KERNEL
);
8663 if (!vmx_msr_bitmap_legacy_x2apic
)
8666 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8667 if (!vmx_msr_bitmap_longmode
)
8670 vmx_msr_bitmap_longmode_x2apic
=
8671 (unsigned long *)__get_free_page(GFP_KERNEL
);
8672 if (!vmx_msr_bitmap_longmode_x2apic
)
8674 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8675 if (!vmx_vmread_bitmap
)
8678 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8679 if (!vmx_vmwrite_bitmap
)
8682 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8683 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8684 /* shadowed read/write fields */
8685 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8686 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8687 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8689 /* shadowed read only fields */
8690 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8691 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8694 * Allow direct access to the PC debug port (it is often used for I/O
8695 * delays, but the vmexits simply slow things down).
8697 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8698 clear_bit(0x80, vmx_io_bitmap_a
);
8700 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8702 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8703 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8705 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8707 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8708 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8713 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8714 crash_vmclear_local_loaded_vmcss
);
8717 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8718 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8719 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8720 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8721 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8722 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8723 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8724 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8725 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8726 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8729 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8730 vmx_disable_intercept_msr_read_x2apic(msr
);
8732 /* According SDM, in x2apic mode, the whole id reg is used.
8733 * But in KVM, it only use the highest eight bits. Need to
8735 vmx_enable_intercept_msr_read_x2apic(0x802);
8737 vmx_enable_intercept_msr_read_x2apic(0x839);
8739 vmx_disable_intercept_msr_write_x2apic(0x808);
8741 vmx_disable_intercept_msr_write_x2apic(0x80b);
8743 vmx_disable_intercept_msr_write_x2apic(0x83f);
8747 kvm_mmu_set_mask_ptes(0ull,
8748 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8749 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8750 0ull, VMX_EPT_EXECUTABLE_MASK
);
8751 ept_set_mmio_spte_mask();
8759 free_page((unsigned long)vmx_vmwrite_bitmap
);
8761 free_page((unsigned long)vmx_vmread_bitmap
);
8763 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8765 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8767 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8769 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8771 free_page((unsigned long)vmx_io_bitmap_b
);
8773 free_page((unsigned long)vmx_io_bitmap_a
);
8777 static void __exit
vmx_exit(void)
8779 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8780 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8781 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8782 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8783 free_page((unsigned long)vmx_io_bitmap_b
);
8784 free_page((unsigned long)vmx_io_bitmap_a
);
8785 free_page((unsigned long)vmx_vmwrite_bitmap
);
8786 free_page((unsigned long)vmx_vmread_bitmap
);
8789 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8796 module_init(vmx_init
)
8797 module_exit(vmx_exit
)