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kvm/x86: Hyper-V HV_X64_MSR_VP_RUNTIME support
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <trace/events/kvm.h>
55
56 #define CREATE_TRACE_POINTS
57 #include "trace.h"
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 static bool __read_mostly kvmclock_periodic_sync = true;
103 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
105 bool kvm_has_tsc_control;
106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107 u32 kvm_max_guest_tsc_khz;
108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111 static u32 tsc_tolerance_ppm = 250;
112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
115 unsigned int lapic_timer_advance_ns = 0;
116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
118 static bool backwards_tsc_observed = false;
119
120 #define KVM_NR_SHARED_MSRS 16
121
122 struct kvm_shared_msrs_global {
123 int nr;
124 u32 msrs[KVM_NR_SHARED_MSRS];
125 };
126
127 struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
134 };
135
136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
137 static struct kvm_shared_msrs __percpu *shared_msrs;
138
139 struct kvm_stats_debugfs_item debugfs_entries[] = {
140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
150 { "halt_exits", VCPU_STAT(halt_exits) },
151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
154 { "hypercalls", VCPU_STAT(hypercalls) },
155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
162 { "irq_injections", VCPU_STAT(irq_injections) },
163 { "nmi_injections", VCPU_STAT(nmi_injections) },
164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
171 { "mmu_unsync", VM_STAT(mmu_unsync) },
172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
173 { "largepages", VM_STAT(lpages) },
174 { NULL }
175 };
176
177 u64 __read_mostly host_xcr0;
178
179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
180
181 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182 {
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186 }
187
188 static void kvm_on_user_return(struct user_return_notifier *urn)
189 {
190 unsigned slot;
191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
193 struct kvm_shared_msr_values *values;
194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204 }
205
206 static void shared_msr_update(unsigned slot, u32 msr)
207 {
208 u64 value;
209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
211
212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221 }
222
223 void kvm_define_shared_msr(unsigned slot, u32 msr)
224 {
225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
226 shared_msrs_global.msrs[slot] = msr;
227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
229 }
230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232 static void kvm_shared_msr_cpu_online(void)
233 {
234 unsigned i;
235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
237 shared_msr_update(i, shared_msrs_global.msrs[i]);
238 }
239
240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
241 {
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 int err;
245
246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
247 return 0;
248 smsr->values[slot].curr = value;
249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
258 return 0;
259 }
260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
262 static void drop_user_return_notifiers(void)
263 {
264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269 }
270
271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272 {
273 return vcpu->arch.apic_base;
274 }
275 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278 {
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
297 }
298 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
300 asmlinkage __visible void kvm_spurious_fault(void)
301 {
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304 }
305 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
307 #define EXCPT_BENIGN 0
308 #define EXCPT_CONTRIBUTORY 1
309 #define EXCPT_PF 2
310
311 static int exception_class(int vector)
312 {
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326 }
327
328 #define EXCPT_FAULT 0
329 #define EXCPT_TRAP 1
330 #define EXCPT_ABORT 2
331 #define EXCPT_INTERRUPT 3
332
333 static int exception_type(int vector)
334 {
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351 }
352
353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
356 {
357 u32 prev_nr;
358 int class1, class2;
359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
362 if (!vcpu->arch.exception.pending) {
363 queue:
364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
370 vcpu->arch.exception.reinject = reinject;
371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395 }
396
397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398 {
399 kvm_multiple_exception(vcpu, nr, false, 0, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404 {
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
410 {
411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415 }
416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
417
418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
419 {
420 ++vcpu->stat.pf_guest;
421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
423 }
424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
425
426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
430 else
431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
432
433 return fault->nested_page_fault;
434 }
435
436 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437 {
438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
440 }
441 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444 {
445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
446 }
447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450 {
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452 }
453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
455 /*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
460 {
461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
465 }
466 EXPORT_SYMBOL_GPL(kvm_require_cpl);
467
468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469 {
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475 }
476 EXPORT_SYMBOL_GPL(kvm_require_dr);
477
478 /*
479 * This function will be used to read from the physical memory of the currently
480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
481 * can read from guest physical or from the guest's guest physical memory.
482 */
483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486 {
487 struct x86_exception exception;
488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
499 }
500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
503 void *data, int offset, int len, u32 access)
504 {
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507 }
508
509 /*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
513 {
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
519
520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
528 if (is_present_gpte(pdpte[i]) &&
529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
542 out:
543
544 return ret;
545 }
546 EXPORT_SYMBOL_GPL(load_pdptrs);
547
548 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549 {
550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
551 bool changed = true;
552 int offset;
553 gfn_t gfn;
554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
567 if (r < 0)
568 goto out;
569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
570 out:
571
572 return changed;
573 }
574
575 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
576 {
577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
579
580 cr0 |= X86_CR0_ET;
581
582 #ifdef CONFIG_X86_64
583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
585 #endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
588
589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
591
592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596 #ifdef CONFIG_X86_64
597 if ((vcpu->arch.efer & EFER_LME)) {
598 int cs_db, cs_l;
599
600 if (!is_pae(vcpu))
601 return 1;
602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
603 if (cs_l)
604 return 1;
605 } else
606 #endif
607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
608 kvm_read_cr3(vcpu)))
609 return 1;
610 }
611
612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
615 kvm_x86_ops->set_cr0(vcpu, cr0);
616
617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
618 kvm_clear_async_pf_completion_queue(vcpu);
619 kvm_async_pf_hash_reset(vcpu);
620 }
621
622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
628 return 0;
629 }
630 EXPORT_SYMBOL_GPL(kvm_set_cr0);
631
632 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
633 {
634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
635 }
636 EXPORT_SYMBOL_GPL(kvm_lmsw);
637
638 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639 {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646 }
647
648 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655 }
656
657 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
658 {
659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
661 u64 valid_bits;
662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
678 return 1;
679
680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
689 kvm_put_guest_xcr0(vcpu);
690 vcpu->arch.xcr0 = xcr0;
691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
694 return 0;
695 }
696
697 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698 {
699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
708 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
709 {
710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
716
717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
727 return 1;
728
729 if (is_long_mode(vcpu)) {
730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
736 return 1;
737
738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
748 return 1;
749
750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
752 kvm_mmu_reset_context(vcpu);
753
754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
755 kvm_update_cpuid(vcpu);
756
757 return 0;
758 }
759 EXPORT_SYMBOL_GPL(kvm_set_cr4);
760
761 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
762 {
763 #ifdef CONFIG_X86_64
764 cr3 &= ~CR3_PCID_INVD;
765 #endif
766
767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
768 kvm_mmu_sync_roots(vcpu);
769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
770 return 0;
771 }
772
773 if (is_long_mode(vcpu)) {
774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
778 return 1;
779
780 vcpu->arch.cr3 = cr3;
781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
782 kvm_mmu_new_cr3(vcpu);
783 return 0;
784 }
785 EXPORT_SYMBOL_GPL(kvm_set_cr3);
786
787 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
788 {
789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
791 if (lapic_in_kernel(vcpu))
792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
794 vcpu->arch.cr8 = cr8;
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_set_cr8);
798
799 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
800 {
801 if (lapic_in_kernel(vcpu))
802 return kvm_lapic_get_cr8(vcpu);
803 else
804 return vcpu->arch.cr8;
805 }
806 EXPORT_SYMBOL_GPL(kvm_get_cr8);
807
808 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809 {
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817 }
818
819 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820 {
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823 }
824
825 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826 {
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
837 }
838
839 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840 {
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846 }
847
848 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
849 {
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
857 /* fall through */
858 case 6:
859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
862 kvm_update_dr6(vcpu);
863 break;
864 case 5:
865 /* fall through */
866 default: /* 7 */
867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
870 kvm_update_dr7(vcpu);
871 break;
872 }
873
874 return 0;
875 }
876
877 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878 {
879 if (__kvm_set_dr(vcpu, dr, val)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884 }
885 EXPORT_SYMBOL_GPL(kvm_set_dr);
886
887 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
888 {
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
894 /* fall through */
895 case 6:
896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
900 break;
901 case 5:
902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(kvm_get_dr);
910
911 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912 {
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923 }
924 EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
926 /*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
931 * capabilities of the host cpu. This capabilities test skips MSRs that are
932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
934 */
935
936 static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
938 MSR_STAR,
939 #ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 #endif
942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
944 };
945
946 static unsigned num_msrs_to_save;
947
948 static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
955 HV_X64_MSR_RESET,
956 HV_X64_MSR_VP_INDEX,
957 HV_X64_MSR_VP_RUNTIME,
958 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
959 MSR_KVM_PV_EOI_EN,
960
961 MSR_IA32_TSC_ADJUST,
962 MSR_IA32_TSCDEADLINE,
963 MSR_IA32_MISC_ENABLE,
964 MSR_IA32_MCG_STATUS,
965 MSR_IA32_MCG_CTL,
966 MSR_IA32_SMBASE,
967 };
968
969 static unsigned num_emulated_msrs;
970
971 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
972 {
973 if (efer & efer_reserved_bits)
974 return false;
975
976 if (efer & EFER_FFXSR) {
977 struct kvm_cpuid_entry2 *feat;
978
979 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
980 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
981 return false;
982 }
983
984 if (efer & EFER_SVME) {
985 struct kvm_cpuid_entry2 *feat;
986
987 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
988 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
989 return false;
990 }
991
992 return true;
993 }
994 EXPORT_SYMBOL_GPL(kvm_valid_efer);
995
996 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
997 {
998 u64 old_efer = vcpu->arch.efer;
999
1000 if (!kvm_valid_efer(vcpu, efer))
1001 return 1;
1002
1003 if (is_paging(vcpu)
1004 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1005 return 1;
1006
1007 efer &= ~EFER_LMA;
1008 efer |= vcpu->arch.efer & EFER_LMA;
1009
1010 kvm_x86_ops->set_efer(vcpu, efer);
1011
1012 /* Update reserved bits */
1013 if ((efer ^ old_efer) & EFER_NX)
1014 kvm_mmu_reset_context(vcpu);
1015
1016 return 0;
1017 }
1018
1019 void kvm_enable_efer_bits(u64 mask)
1020 {
1021 efer_reserved_bits &= ~mask;
1022 }
1023 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1024
1025 /*
1026 * Writes msr value into into the appropriate "register".
1027 * Returns 0 on success, non-0 otherwise.
1028 * Assumes vcpu_load() was already called.
1029 */
1030 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1031 {
1032 switch (msr->index) {
1033 case MSR_FS_BASE:
1034 case MSR_GS_BASE:
1035 case MSR_KERNEL_GS_BASE:
1036 case MSR_CSTAR:
1037 case MSR_LSTAR:
1038 if (is_noncanonical_address(msr->data))
1039 return 1;
1040 break;
1041 case MSR_IA32_SYSENTER_EIP:
1042 case MSR_IA32_SYSENTER_ESP:
1043 /*
1044 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1045 * non-canonical address is written on Intel but not on
1046 * AMD (which ignores the top 32-bits, because it does
1047 * not implement 64-bit SYSENTER).
1048 *
1049 * 64-bit code should hence be able to write a non-canonical
1050 * value on AMD. Making the address canonical ensures that
1051 * vmentry does not fail on Intel after writing a non-canonical
1052 * value, and that something deterministic happens if the guest
1053 * invokes 64-bit SYSENTER.
1054 */
1055 msr->data = get_canonical(msr->data);
1056 }
1057 return kvm_x86_ops->set_msr(vcpu, msr);
1058 }
1059 EXPORT_SYMBOL_GPL(kvm_set_msr);
1060
1061 /*
1062 * Adapt set_msr() to msr_io()'s calling convention
1063 */
1064 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1065 {
1066 struct msr_data msr;
1067 int r;
1068
1069 msr.index = index;
1070 msr.host_initiated = true;
1071 r = kvm_get_msr(vcpu, &msr);
1072 if (r)
1073 return r;
1074
1075 *data = msr.data;
1076 return 0;
1077 }
1078
1079 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1080 {
1081 struct msr_data msr;
1082
1083 msr.data = *data;
1084 msr.index = index;
1085 msr.host_initiated = true;
1086 return kvm_set_msr(vcpu, &msr);
1087 }
1088
1089 #ifdef CONFIG_X86_64
1090 struct pvclock_gtod_data {
1091 seqcount_t seq;
1092
1093 struct { /* extract of a clocksource struct */
1094 int vclock_mode;
1095 cycle_t cycle_last;
1096 cycle_t mask;
1097 u32 mult;
1098 u32 shift;
1099 } clock;
1100
1101 u64 boot_ns;
1102 u64 nsec_base;
1103 };
1104
1105 static struct pvclock_gtod_data pvclock_gtod_data;
1106
1107 static void update_pvclock_gtod(struct timekeeper *tk)
1108 {
1109 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1110 u64 boot_ns;
1111
1112 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1113
1114 write_seqcount_begin(&vdata->seq);
1115
1116 /* copy pvclock gtod data */
1117 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1118 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1119 vdata->clock.mask = tk->tkr_mono.mask;
1120 vdata->clock.mult = tk->tkr_mono.mult;
1121 vdata->clock.shift = tk->tkr_mono.shift;
1122
1123 vdata->boot_ns = boot_ns;
1124 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1125
1126 write_seqcount_end(&vdata->seq);
1127 }
1128 #endif
1129
1130 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1131 {
1132 /*
1133 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1134 * vcpu_enter_guest. This function is only called from
1135 * the physical CPU that is running vcpu.
1136 */
1137 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1138 }
1139
1140 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1141 {
1142 int version;
1143 int r;
1144 struct pvclock_wall_clock wc;
1145 struct timespec boot;
1146
1147 if (!wall_clock)
1148 return;
1149
1150 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1151 if (r)
1152 return;
1153
1154 if (version & 1)
1155 ++version; /* first time write, random junk */
1156
1157 ++version;
1158
1159 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1160
1161 /*
1162 * The guest calculates current wall clock time by adding
1163 * system time (updated by kvm_guest_time_update below) to the
1164 * wall clock specified here. guest system time equals host
1165 * system time for us, thus we must fill in host boot time here.
1166 */
1167 getboottime(&boot);
1168
1169 if (kvm->arch.kvmclock_offset) {
1170 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1171 boot = timespec_sub(boot, ts);
1172 }
1173 wc.sec = boot.tv_sec;
1174 wc.nsec = boot.tv_nsec;
1175 wc.version = version;
1176
1177 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1178
1179 version++;
1180 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1181 }
1182
1183 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1184 {
1185 uint32_t quotient, remainder;
1186
1187 /* Don't try to replace with do_div(), this one calculates
1188 * "(dividend << 32) / divisor" */
1189 __asm__ ( "divl %4"
1190 : "=a" (quotient), "=d" (remainder)
1191 : "0" (0), "1" (dividend), "r" (divisor) );
1192 return quotient;
1193 }
1194
1195 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1196 s8 *pshift, u32 *pmultiplier)
1197 {
1198 uint64_t scaled64;
1199 int32_t shift = 0;
1200 uint64_t tps64;
1201 uint32_t tps32;
1202
1203 tps64 = base_khz * 1000LL;
1204 scaled64 = scaled_khz * 1000LL;
1205 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1206 tps64 >>= 1;
1207 shift--;
1208 }
1209
1210 tps32 = (uint32_t)tps64;
1211 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1212 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1213 scaled64 >>= 1;
1214 else
1215 tps32 <<= 1;
1216 shift++;
1217 }
1218
1219 *pshift = shift;
1220 *pmultiplier = div_frac(scaled64, tps32);
1221
1222 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1223 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1224 }
1225
1226 #ifdef CONFIG_X86_64
1227 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1228 #endif
1229
1230 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1231 static unsigned long max_tsc_khz;
1232
1233 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1234 {
1235 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1236 vcpu->arch.virtual_tsc_shift);
1237 }
1238
1239 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1240 {
1241 u64 v = (u64)khz * (1000000 + ppm);
1242 do_div(v, 1000000);
1243 return v;
1244 }
1245
1246 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1247 {
1248 u32 thresh_lo, thresh_hi;
1249 int use_scaling = 0;
1250
1251 /* tsc_khz can be zero if TSC calibration fails */
1252 if (this_tsc_khz == 0)
1253 return;
1254
1255 /* Compute a scale to convert nanoseconds in TSC cycles */
1256 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1257 &vcpu->arch.virtual_tsc_shift,
1258 &vcpu->arch.virtual_tsc_mult);
1259 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1260
1261 /*
1262 * Compute the variation in TSC rate which is acceptable
1263 * within the range of tolerance and decide if the
1264 * rate being applied is within that bounds of the hardware
1265 * rate. If so, no scaling or compensation need be done.
1266 */
1267 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1268 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1269 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1270 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1271 use_scaling = 1;
1272 }
1273 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1274 }
1275
1276 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1277 {
1278 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1279 vcpu->arch.virtual_tsc_mult,
1280 vcpu->arch.virtual_tsc_shift);
1281 tsc += vcpu->arch.this_tsc_write;
1282 return tsc;
1283 }
1284
1285 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1286 {
1287 #ifdef CONFIG_X86_64
1288 bool vcpus_matched;
1289 struct kvm_arch *ka = &vcpu->kvm->arch;
1290 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1291
1292 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1293 atomic_read(&vcpu->kvm->online_vcpus));
1294
1295 /*
1296 * Once the masterclock is enabled, always perform request in
1297 * order to update it.
1298 *
1299 * In order to enable masterclock, the host clocksource must be TSC
1300 * and the vcpus need to have matched TSCs. When that happens,
1301 * perform request to enable masterclock.
1302 */
1303 if (ka->use_master_clock ||
1304 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1305 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1306
1307 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1308 atomic_read(&vcpu->kvm->online_vcpus),
1309 ka->use_master_clock, gtod->clock.vclock_mode);
1310 #endif
1311 }
1312
1313 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1314 {
1315 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1316 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1317 }
1318
1319 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1320 {
1321 struct kvm *kvm = vcpu->kvm;
1322 u64 offset, ns, elapsed;
1323 unsigned long flags;
1324 s64 usdiff;
1325 bool matched;
1326 bool already_matched;
1327 u64 data = msr->data;
1328
1329 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1330 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1331 ns = get_kernel_ns();
1332 elapsed = ns - kvm->arch.last_tsc_nsec;
1333
1334 if (vcpu->arch.virtual_tsc_khz) {
1335 int faulted = 0;
1336
1337 /* n.b - signed multiplication and division required */
1338 usdiff = data - kvm->arch.last_tsc_write;
1339 #ifdef CONFIG_X86_64
1340 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1341 #else
1342 /* do_div() only does unsigned */
1343 asm("1: idivl %[divisor]\n"
1344 "2: xor %%edx, %%edx\n"
1345 " movl $0, %[faulted]\n"
1346 "3:\n"
1347 ".section .fixup,\"ax\"\n"
1348 "4: movl $1, %[faulted]\n"
1349 " jmp 3b\n"
1350 ".previous\n"
1351
1352 _ASM_EXTABLE(1b, 4b)
1353
1354 : "=A"(usdiff), [faulted] "=r" (faulted)
1355 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1356
1357 #endif
1358 do_div(elapsed, 1000);
1359 usdiff -= elapsed;
1360 if (usdiff < 0)
1361 usdiff = -usdiff;
1362
1363 /* idivl overflow => difference is larger than USEC_PER_SEC */
1364 if (faulted)
1365 usdiff = USEC_PER_SEC;
1366 } else
1367 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1368
1369 /*
1370 * Special case: TSC write with a small delta (1 second) of virtual
1371 * cycle time against real time is interpreted as an attempt to
1372 * synchronize the CPU.
1373 *
1374 * For a reliable TSC, we can match TSC offsets, and for an unstable
1375 * TSC, we add elapsed time in this computation. We could let the
1376 * compensation code attempt to catch up if we fall behind, but
1377 * it's better to try to match offsets from the beginning.
1378 */
1379 if (usdiff < USEC_PER_SEC &&
1380 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1381 if (!check_tsc_unstable()) {
1382 offset = kvm->arch.cur_tsc_offset;
1383 pr_debug("kvm: matched tsc offset for %llu\n", data);
1384 } else {
1385 u64 delta = nsec_to_cycles(vcpu, elapsed);
1386 data += delta;
1387 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1388 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1389 }
1390 matched = true;
1391 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1392 } else {
1393 /*
1394 * We split periods of matched TSC writes into generations.
1395 * For each generation, we track the original measured
1396 * nanosecond time, offset, and write, so if TSCs are in
1397 * sync, we can match exact offset, and if not, we can match
1398 * exact software computation in compute_guest_tsc()
1399 *
1400 * These values are tracked in kvm->arch.cur_xxx variables.
1401 */
1402 kvm->arch.cur_tsc_generation++;
1403 kvm->arch.cur_tsc_nsec = ns;
1404 kvm->arch.cur_tsc_write = data;
1405 kvm->arch.cur_tsc_offset = offset;
1406 matched = false;
1407 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1408 kvm->arch.cur_tsc_generation, data);
1409 }
1410
1411 /*
1412 * We also track th most recent recorded KHZ, write and time to
1413 * allow the matching interval to be extended at each write.
1414 */
1415 kvm->arch.last_tsc_nsec = ns;
1416 kvm->arch.last_tsc_write = data;
1417 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1418
1419 vcpu->arch.last_guest_tsc = data;
1420
1421 /* Keep track of which generation this VCPU has synchronized to */
1422 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1423 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1424 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1425
1426 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1427 update_ia32_tsc_adjust_msr(vcpu, offset);
1428 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1429 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1430
1431 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1432 if (!matched) {
1433 kvm->arch.nr_vcpus_matched_tsc = 0;
1434 } else if (!already_matched) {
1435 kvm->arch.nr_vcpus_matched_tsc++;
1436 }
1437
1438 kvm_track_tsc_matching(vcpu);
1439 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1440 }
1441
1442 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1443
1444 #ifdef CONFIG_X86_64
1445
1446 static cycle_t read_tsc(void)
1447 {
1448 cycle_t ret = (cycle_t)rdtsc_ordered();
1449 u64 last = pvclock_gtod_data.clock.cycle_last;
1450
1451 if (likely(ret >= last))
1452 return ret;
1453
1454 /*
1455 * GCC likes to generate cmov here, but this branch is extremely
1456 * predictable (it's just a funciton of time and the likely is
1457 * very likely) and there's a data dependence, so force GCC
1458 * to generate a branch instead. I don't barrier() because
1459 * we don't actually need a barrier, and if this function
1460 * ever gets inlined it will generate worse code.
1461 */
1462 asm volatile ("");
1463 return last;
1464 }
1465
1466 static inline u64 vgettsc(cycle_t *cycle_now)
1467 {
1468 long v;
1469 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1470
1471 *cycle_now = read_tsc();
1472
1473 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1474 return v * gtod->clock.mult;
1475 }
1476
1477 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1478 {
1479 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1480 unsigned long seq;
1481 int mode;
1482 u64 ns;
1483
1484 do {
1485 seq = read_seqcount_begin(&gtod->seq);
1486 mode = gtod->clock.vclock_mode;
1487 ns = gtod->nsec_base;
1488 ns += vgettsc(cycle_now);
1489 ns >>= gtod->clock.shift;
1490 ns += gtod->boot_ns;
1491 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1492 *t = ns;
1493
1494 return mode;
1495 }
1496
1497 /* returns true if host is using tsc clocksource */
1498 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1499 {
1500 /* checked again under seqlock below */
1501 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1502 return false;
1503
1504 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1505 }
1506 #endif
1507
1508 /*
1509 *
1510 * Assuming a stable TSC across physical CPUS, and a stable TSC
1511 * across virtual CPUs, the following condition is possible.
1512 * Each numbered line represents an event visible to both
1513 * CPUs at the next numbered event.
1514 *
1515 * "timespecX" represents host monotonic time. "tscX" represents
1516 * RDTSC value.
1517 *
1518 * VCPU0 on CPU0 | VCPU1 on CPU1
1519 *
1520 * 1. read timespec0,tsc0
1521 * 2. | timespec1 = timespec0 + N
1522 * | tsc1 = tsc0 + M
1523 * 3. transition to guest | transition to guest
1524 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1525 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1526 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1527 *
1528 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1529 *
1530 * - ret0 < ret1
1531 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1532 * ...
1533 * - 0 < N - M => M < N
1534 *
1535 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1536 * always the case (the difference between two distinct xtime instances
1537 * might be smaller then the difference between corresponding TSC reads,
1538 * when updating guest vcpus pvclock areas).
1539 *
1540 * To avoid that problem, do not allow visibility of distinct
1541 * system_timestamp/tsc_timestamp values simultaneously: use a master
1542 * copy of host monotonic time values. Update that master copy
1543 * in lockstep.
1544 *
1545 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1546 *
1547 */
1548
1549 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1550 {
1551 #ifdef CONFIG_X86_64
1552 struct kvm_arch *ka = &kvm->arch;
1553 int vclock_mode;
1554 bool host_tsc_clocksource, vcpus_matched;
1555
1556 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1557 atomic_read(&kvm->online_vcpus));
1558
1559 /*
1560 * If the host uses TSC clock, then passthrough TSC as stable
1561 * to the guest.
1562 */
1563 host_tsc_clocksource = kvm_get_time_and_clockread(
1564 &ka->master_kernel_ns,
1565 &ka->master_cycle_now);
1566
1567 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1568 && !backwards_tsc_observed
1569 && !ka->boot_vcpu_runs_old_kvmclock;
1570
1571 if (ka->use_master_clock)
1572 atomic_set(&kvm_guest_has_master_clock, 1);
1573
1574 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1575 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1576 vcpus_matched);
1577 #endif
1578 }
1579
1580 static void kvm_gen_update_masterclock(struct kvm *kvm)
1581 {
1582 #ifdef CONFIG_X86_64
1583 int i;
1584 struct kvm_vcpu *vcpu;
1585 struct kvm_arch *ka = &kvm->arch;
1586
1587 spin_lock(&ka->pvclock_gtod_sync_lock);
1588 kvm_make_mclock_inprogress_request(kvm);
1589 /* no guest entries from this point */
1590 pvclock_update_vm_gtod_copy(kvm);
1591
1592 kvm_for_each_vcpu(i, vcpu, kvm)
1593 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1594
1595 /* guest entries allowed */
1596 kvm_for_each_vcpu(i, vcpu, kvm)
1597 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1598
1599 spin_unlock(&ka->pvclock_gtod_sync_lock);
1600 #endif
1601 }
1602
1603 static int kvm_guest_time_update(struct kvm_vcpu *v)
1604 {
1605 unsigned long flags, this_tsc_khz;
1606 struct kvm_vcpu_arch *vcpu = &v->arch;
1607 struct kvm_arch *ka = &v->kvm->arch;
1608 s64 kernel_ns;
1609 u64 tsc_timestamp, host_tsc;
1610 struct pvclock_vcpu_time_info guest_hv_clock;
1611 u8 pvclock_flags;
1612 bool use_master_clock;
1613
1614 kernel_ns = 0;
1615 host_tsc = 0;
1616
1617 /*
1618 * If the host uses TSC clock, then passthrough TSC as stable
1619 * to the guest.
1620 */
1621 spin_lock(&ka->pvclock_gtod_sync_lock);
1622 use_master_clock = ka->use_master_clock;
1623 if (use_master_clock) {
1624 host_tsc = ka->master_cycle_now;
1625 kernel_ns = ka->master_kernel_ns;
1626 }
1627 spin_unlock(&ka->pvclock_gtod_sync_lock);
1628
1629 /* Keep irq disabled to prevent changes to the clock */
1630 local_irq_save(flags);
1631 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1632 if (unlikely(this_tsc_khz == 0)) {
1633 local_irq_restore(flags);
1634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1635 return 1;
1636 }
1637 if (!use_master_clock) {
1638 host_tsc = rdtsc();
1639 kernel_ns = get_kernel_ns();
1640 }
1641
1642 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1643
1644 /*
1645 * We may have to catch up the TSC to match elapsed wall clock
1646 * time for two reasons, even if kvmclock is used.
1647 * 1) CPU could have been running below the maximum TSC rate
1648 * 2) Broken TSC compensation resets the base at each VCPU
1649 * entry to avoid unknown leaps of TSC even when running
1650 * again on the same CPU. This may cause apparent elapsed
1651 * time to disappear, and the guest to stand still or run
1652 * very slowly.
1653 */
1654 if (vcpu->tsc_catchup) {
1655 u64 tsc = compute_guest_tsc(v, kernel_ns);
1656 if (tsc > tsc_timestamp) {
1657 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1658 tsc_timestamp = tsc;
1659 }
1660 }
1661
1662 local_irq_restore(flags);
1663
1664 if (!vcpu->pv_time_enabled)
1665 return 0;
1666
1667 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1668 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1669 &vcpu->hv_clock.tsc_shift,
1670 &vcpu->hv_clock.tsc_to_system_mul);
1671 vcpu->hw_tsc_khz = this_tsc_khz;
1672 }
1673
1674 /* With all the info we got, fill in the values */
1675 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1676 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1677 vcpu->last_guest_tsc = tsc_timestamp;
1678
1679 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1680 &guest_hv_clock, sizeof(guest_hv_clock))))
1681 return 0;
1682
1683 /* This VCPU is paused, but it's legal for a guest to read another
1684 * VCPU's kvmclock, so we really have to follow the specification where
1685 * it says that version is odd if data is being modified, and even after
1686 * it is consistent.
1687 *
1688 * Version field updates must be kept separate. This is because
1689 * kvm_write_guest_cached might use a "rep movs" instruction, and
1690 * writes within a string instruction are weakly ordered. So there
1691 * are three writes overall.
1692 *
1693 * As a small optimization, only write the version field in the first
1694 * and third write. The vcpu->pv_time cache is still valid, because the
1695 * version field is the first in the struct.
1696 */
1697 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1698
1699 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1700 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1701 &vcpu->hv_clock,
1702 sizeof(vcpu->hv_clock.version));
1703
1704 smp_wmb();
1705
1706 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1707 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1708
1709 if (vcpu->pvclock_set_guest_stopped_request) {
1710 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1711 vcpu->pvclock_set_guest_stopped_request = false;
1712 }
1713
1714 /* If the host uses TSC clocksource, then it is stable */
1715 if (use_master_clock)
1716 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1717
1718 vcpu->hv_clock.flags = pvclock_flags;
1719
1720 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1721
1722 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1723 &vcpu->hv_clock,
1724 sizeof(vcpu->hv_clock));
1725
1726 smp_wmb();
1727
1728 vcpu->hv_clock.version++;
1729 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1730 &vcpu->hv_clock,
1731 sizeof(vcpu->hv_clock.version));
1732 return 0;
1733 }
1734
1735 /*
1736 * kvmclock updates which are isolated to a given vcpu, such as
1737 * vcpu->cpu migration, should not allow system_timestamp from
1738 * the rest of the vcpus to remain static. Otherwise ntp frequency
1739 * correction applies to one vcpu's system_timestamp but not
1740 * the others.
1741 *
1742 * So in those cases, request a kvmclock update for all vcpus.
1743 * We need to rate-limit these requests though, as they can
1744 * considerably slow guests that have a large number of vcpus.
1745 * The time for a remote vcpu to update its kvmclock is bound
1746 * by the delay we use to rate-limit the updates.
1747 */
1748
1749 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1750
1751 static void kvmclock_update_fn(struct work_struct *work)
1752 {
1753 int i;
1754 struct delayed_work *dwork = to_delayed_work(work);
1755 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1756 kvmclock_update_work);
1757 struct kvm *kvm = container_of(ka, struct kvm, arch);
1758 struct kvm_vcpu *vcpu;
1759
1760 kvm_for_each_vcpu(i, vcpu, kvm) {
1761 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1762 kvm_vcpu_kick(vcpu);
1763 }
1764 }
1765
1766 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1767 {
1768 struct kvm *kvm = v->kvm;
1769
1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1771 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1772 KVMCLOCK_UPDATE_DELAY);
1773 }
1774
1775 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1776
1777 static void kvmclock_sync_fn(struct work_struct *work)
1778 {
1779 struct delayed_work *dwork = to_delayed_work(work);
1780 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1781 kvmclock_sync_work);
1782 struct kvm *kvm = container_of(ka, struct kvm, arch);
1783
1784 if (!kvmclock_periodic_sync)
1785 return;
1786
1787 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1788 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1789 KVMCLOCK_SYNC_PERIOD);
1790 }
1791
1792 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1793 {
1794 u64 mcg_cap = vcpu->arch.mcg_cap;
1795 unsigned bank_num = mcg_cap & 0xff;
1796
1797 switch (msr) {
1798 case MSR_IA32_MCG_STATUS:
1799 vcpu->arch.mcg_status = data;
1800 break;
1801 case MSR_IA32_MCG_CTL:
1802 if (!(mcg_cap & MCG_CTL_P))
1803 return 1;
1804 if (data != 0 && data != ~(u64)0)
1805 return -1;
1806 vcpu->arch.mcg_ctl = data;
1807 break;
1808 default:
1809 if (msr >= MSR_IA32_MC0_CTL &&
1810 msr < MSR_IA32_MCx_CTL(bank_num)) {
1811 u32 offset = msr - MSR_IA32_MC0_CTL;
1812 /* only 0 or all 1s can be written to IA32_MCi_CTL
1813 * some Linux kernels though clear bit 10 in bank 4 to
1814 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1815 * this to avoid an uncatched #GP in the guest
1816 */
1817 if ((offset & 0x3) == 0 &&
1818 data != 0 && (data | (1 << 10)) != ~(u64)0)
1819 return -1;
1820 vcpu->arch.mce_banks[offset] = data;
1821 break;
1822 }
1823 return 1;
1824 }
1825 return 0;
1826 }
1827
1828 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1829 {
1830 struct kvm *kvm = vcpu->kvm;
1831 int lm = is_long_mode(vcpu);
1832 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1833 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1834 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1835 : kvm->arch.xen_hvm_config.blob_size_32;
1836 u32 page_num = data & ~PAGE_MASK;
1837 u64 page_addr = data & PAGE_MASK;
1838 u8 *page;
1839 int r;
1840
1841 r = -E2BIG;
1842 if (page_num >= blob_size)
1843 goto out;
1844 r = -ENOMEM;
1845 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1846 if (IS_ERR(page)) {
1847 r = PTR_ERR(page);
1848 goto out;
1849 }
1850 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1851 goto out_free;
1852 r = 0;
1853 out_free:
1854 kfree(page);
1855 out:
1856 return r;
1857 }
1858
1859 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1860 {
1861 gpa_t gpa = data & ~0x3f;
1862
1863 /* Bits 2:5 are reserved, Should be zero */
1864 if (data & 0x3c)
1865 return 1;
1866
1867 vcpu->arch.apf.msr_val = data;
1868
1869 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1870 kvm_clear_async_pf_completion_queue(vcpu);
1871 kvm_async_pf_hash_reset(vcpu);
1872 return 0;
1873 }
1874
1875 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1876 sizeof(u32)))
1877 return 1;
1878
1879 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1880 kvm_async_pf_wakeup_all(vcpu);
1881 return 0;
1882 }
1883
1884 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1885 {
1886 vcpu->arch.pv_time_enabled = false;
1887 }
1888
1889 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1890 {
1891 u64 delta;
1892
1893 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1894 return;
1895
1896 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1897 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1898 vcpu->arch.st.accum_steal = delta;
1899 }
1900
1901 static void record_steal_time(struct kvm_vcpu *vcpu)
1902 {
1903 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1904 return;
1905
1906 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1907 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1908 return;
1909
1910 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1911 vcpu->arch.st.steal.version += 2;
1912 vcpu->arch.st.accum_steal = 0;
1913
1914 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1915 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1916 }
1917
1918 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1919 {
1920 bool pr = false;
1921 u32 msr = msr_info->index;
1922 u64 data = msr_info->data;
1923
1924 switch (msr) {
1925 case MSR_AMD64_NB_CFG:
1926 case MSR_IA32_UCODE_REV:
1927 case MSR_IA32_UCODE_WRITE:
1928 case MSR_VM_HSAVE_PA:
1929 case MSR_AMD64_PATCH_LOADER:
1930 case MSR_AMD64_BU_CFG2:
1931 break;
1932
1933 case MSR_EFER:
1934 return set_efer(vcpu, data);
1935 case MSR_K7_HWCR:
1936 data &= ~(u64)0x40; /* ignore flush filter disable */
1937 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1938 data &= ~(u64)0x8; /* ignore TLB cache disable */
1939 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1940 if (data != 0) {
1941 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1942 data);
1943 return 1;
1944 }
1945 break;
1946 case MSR_FAM10H_MMIO_CONF_BASE:
1947 if (data != 0) {
1948 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1949 "0x%llx\n", data);
1950 return 1;
1951 }
1952 break;
1953 case MSR_IA32_DEBUGCTLMSR:
1954 if (!data) {
1955 /* We support the non-activated case already */
1956 break;
1957 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1958 /* Values other than LBR and BTF are vendor-specific,
1959 thus reserved and should throw a #GP */
1960 return 1;
1961 }
1962 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1963 __func__, data);
1964 break;
1965 case 0x200 ... 0x2ff:
1966 return kvm_mtrr_set_msr(vcpu, msr, data);
1967 case MSR_IA32_APICBASE:
1968 return kvm_set_apic_base(vcpu, msr_info);
1969 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1970 return kvm_x2apic_msr_write(vcpu, msr, data);
1971 case MSR_IA32_TSCDEADLINE:
1972 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1973 break;
1974 case MSR_IA32_TSC_ADJUST:
1975 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1976 if (!msr_info->host_initiated) {
1977 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1978 adjust_tsc_offset_guest(vcpu, adj);
1979 }
1980 vcpu->arch.ia32_tsc_adjust_msr = data;
1981 }
1982 break;
1983 case MSR_IA32_MISC_ENABLE:
1984 vcpu->arch.ia32_misc_enable_msr = data;
1985 break;
1986 case MSR_IA32_SMBASE:
1987 if (!msr_info->host_initiated)
1988 return 1;
1989 vcpu->arch.smbase = data;
1990 break;
1991 case MSR_KVM_WALL_CLOCK_NEW:
1992 case MSR_KVM_WALL_CLOCK:
1993 vcpu->kvm->arch.wall_clock = data;
1994 kvm_write_wall_clock(vcpu->kvm, data);
1995 break;
1996 case MSR_KVM_SYSTEM_TIME_NEW:
1997 case MSR_KVM_SYSTEM_TIME: {
1998 u64 gpa_offset;
1999 struct kvm_arch *ka = &vcpu->kvm->arch;
2000
2001 kvmclock_reset(vcpu);
2002
2003 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2004 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2005
2006 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2007 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2008 &vcpu->requests);
2009
2010 ka->boot_vcpu_runs_old_kvmclock = tmp;
2011 }
2012
2013 vcpu->arch.time = data;
2014 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2015
2016 /* we verify if the enable bit is set... */
2017 if (!(data & 1))
2018 break;
2019
2020 gpa_offset = data & ~(PAGE_MASK | 1);
2021
2022 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2023 &vcpu->arch.pv_time, data & ~1ULL,
2024 sizeof(struct pvclock_vcpu_time_info)))
2025 vcpu->arch.pv_time_enabled = false;
2026 else
2027 vcpu->arch.pv_time_enabled = true;
2028
2029 break;
2030 }
2031 case MSR_KVM_ASYNC_PF_EN:
2032 if (kvm_pv_enable_async_pf(vcpu, data))
2033 return 1;
2034 break;
2035 case MSR_KVM_STEAL_TIME:
2036
2037 if (unlikely(!sched_info_on()))
2038 return 1;
2039
2040 if (data & KVM_STEAL_RESERVED_MASK)
2041 return 1;
2042
2043 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2044 data & KVM_STEAL_VALID_BITS,
2045 sizeof(struct kvm_steal_time)))
2046 return 1;
2047
2048 vcpu->arch.st.msr_val = data;
2049
2050 if (!(data & KVM_MSR_ENABLED))
2051 break;
2052
2053 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2054
2055 preempt_disable();
2056 accumulate_steal_time(vcpu);
2057 preempt_enable();
2058
2059 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2060
2061 break;
2062 case MSR_KVM_PV_EOI_EN:
2063 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2064 return 1;
2065 break;
2066
2067 case MSR_IA32_MCG_CTL:
2068 case MSR_IA32_MCG_STATUS:
2069 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2070 return set_msr_mce(vcpu, msr, data);
2071
2072 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2073 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2074 pr = true; /* fall through */
2075 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2076 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2077 if (kvm_pmu_is_valid_msr(vcpu, msr))
2078 return kvm_pmu_set_msr(vcpu, msr_info);
2079
2080 if (pr || data != 0)
2081 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2082 "0x%x data 0x%llx\n", msr, data);
2083 break;
2084 case MSR_K7_CLK_CTL:
2085 /*
2086 * Ignore all writes to this no longer documented MSR.
2087 * Writes are only relevant for old K7 processors,
2088 * all pre-dating SVM, but a recommended workaround from
2089 * AMD for these chips. It is possible to specify the
2090 * affected processor models on the command line, hence
2091 * the need to ignore the workaround.
2092 */
2093 break;
2094 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2095 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2096 case HV_X64_MSR_CRASH_CTL:
2097 return kvm_hv_set_msr_common(vcpu, msr, data,
2098 msr_info->host_initiated);
2099 case MSR_IA32_BBL_CR_CTL3:
2100 /* Drop writes to this legacy MSR -- see rdmsr
2101 * counterpart for further detail.
2102 */
2103 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2104 break;
2105 case MSR_AMD64_OSVW_ID_LENGTH:
2106 if (!guest_cpuid_has_osvw(vcpu))
2107 return 1;
2108 vcpu->arch.osvw.length = data;
2109 break;
2110 case MSR_AMD64_OSVW_STATUS:
2111 if (!guest_cpuid_has_osvw(vcpu))
2112 return 1;
2113 vcpu->arch.osvw.status = data;
2114 break;
2115 default:
2116 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2117 return xen_hvm_config(vcpu, data);
2118 if (kvm_pmu_is_valid_msr(vcpu, msr))
2119 return kvm_pmu_set_msr(vcpu, msr_info);
2120 if (!ignore_msrs) {
2121 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2122 msr, data);
2123 return 1;
2124 } else {
2125 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2126 msr, data);
2127 break;
2128 }
2129 }
2130 return 0;
2131 }
2132 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2133
2134
2135 /*
2136 * Reads an msr value (of 'msr_index') into 'pdata'.
2137 * Returns 0 on success, non-0 otherwise.
2138 * Assumes vcpu_load() was already called.
2139 */
2140 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2141 {
2142 return kvm_x86_ops->get_msr(vcpu, msr);
2143 }
2144 EXPORT_SYMBOL_GPL(kvm_get_msr);
2145
2146 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2147 {
2148 u64 data;
2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
2151
2152 switch (msr) {
2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
2155 data = 0;
2156 break;
2157 case MSR_IA32_MCG_CAP:
2158 data = vcpu->arch.mcg_cap;
2159 break;
2160 case MSR_IA32_MCG_CTL:
2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 data = vcpu->arch.mcg_ctl;
2164 break;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2167 break;
2168 default:
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MCx_CTL(bank_num)) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2173 break;
2174 }
2175 return 1;
2176 }
2177 *pdata = data;
2178 return 0;
2179 }
2180
2181 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2182 {
2183 switch (msr_info->index) {
2184 case MSR_IA32_PLATFORM_ID:
2185 case MSR_IA32_EBL_CR_POWERON:
2186 case MSR_IA32_DEBUGCTLMSR:
2187 case MSR_IA32_LASTBRANCHFROMIP:
2188 case MSR_IA32_LASTBRANCHTOIP:
2189 case MSR_IA32_LASTINTFROMIP:
2190 case MSR_IA32_LASTINTTOIP:
2191 case MSR_K8_SYSCFG:
2192 case MSR_K8_TSEG_ADDR:
2193 case MSR_K8_TSEG_MASK:
2194 case MSR_K7_HWCR:
2195 case MSR_VM_HSAVE_PA:
2196 case MSR_K8_INT_PENDING_MSG:
2197 case MSR_AMD64_NB_CFG:
2198 case MSR_FAM10H_MMIO_CONF_BASE:
2199 case MSR_AMD64_BU_CFG2:
2200 msr_info->data = 0;
2201 break;
2202 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2203 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2204 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2205 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2206 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2207 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2208 msr_info->data = 0;
2209 break;
2210 case MSR_IA32_UCODE_REV:
2211 msr_info->data = 0x100000000ULL;
2212 break;
2213 case MSR_MTRRcap:
2214 case 0x200 ... 0x2ff:
2215 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2216 case 0xcd: /* fsb frequency */
2217 msr_info->data = 3;
2218 break;
2219 /*
2220 * MSR_EBC_FREQUENCY_ID
2221 * Conservative value valid for even the basic CPU models.
2222 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2223 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2224 * and 266MHz for model 3, or 4. Set Core Clock
2225 * Frequency to System Bus Frequency Ratio to 1 (bits
2226 * 31:24) even though these are only valid for CPU
2227 * models > 2, however guests may end up dividing or
2228 * multiplying by zero otherwise.
2229 */
2230 case MSR_EBC_FREQUENCY_ID:
2231 msr_info->data = 1 << 24;
2232 break;
2233 case MSR_IA32_APICBASE:
2234 msr_info->data = kvm_get_apic_base(vcpu);
2235 break;
2236 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2237 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2238 break;
2239 case MSR_IA32_TSCDEADLINE:
2240 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2241 break;
2242 case MSR_IA32_TSC_ADJUST:
2243 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2244 break;
2245 case MSR_IA32_MISC_ENABLE:
2246 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2247 break;
2248 case MSR_IA32_SMBASE:
2249 if (!msr_info->host_initiated)
2250 return 1;
2251 msr_info->data = vcpu->arch.smbase;
2252 break;
2253 case MSR_IA32_PERF_STATUS:
2254 /* TSC increment by tick */
2255 msr_info->data = 1000ULL;
2256 /* CPU multiplier */
2257 msr_info->data |= (((uint64_t)4ULL) << 40);
2258 break;
2259 case MSR_EFER:
2260 msr_info->data = vcpu->arch.efer;
2261 break;
2262 case MSR_KVM_WALL_CLOCK:
2263 case MSR_KVM_WALL_CLOCK_NEW:
2264 msr_info->data = vcpu->kvm->arch.wall_clock;
2265 break;
2266 case MSR_KVM_SYSTEM_TIME:
2267 case MSR_KVM_SYSTEM_TIME_NEW:
2268 msr_info->data = vcpu->arch.time;
2269 break;
2270 case MSR_KVM_ASYNC_PF_EN:
2271 msr_info->data = vcpu->arch.apf.msr_val;
2272 break;
2273 case MSR_KVM_STEAL_TIME:
2274 msr_info->data = vcpu->arch.st.msr_val;
2275 break;
2276 case MSR_KVM_PV_EOI_EN:
2277 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2278 break;
2279 case MSR_IA32_P5_MC_ADDR:
2280 case MSR_IA32_P5_MC_TYPE:
2281 case MSR_IA32_MCG_CAP:
2282 case MSR_IA32_MCG_CTL:
2283 case MSR_IA32_MCG_STATUS:
2284 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2285 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2286 case MSR_K7_CLK_CTL:
2287 /*
2288 * Provide expected ramp-up count for K7. All other
2289 * are set to zero, indicating minimum divisors for
2290 * every field.
2291 *
2292 * This prevents guest kernels on AMD host with CPU
2293 * type 6, model 8 and higher from exploding due to
2294 * the rdmsr failing.
2295 */
2296 msr_info->data = 0x20000000;
2297 break;
2298 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2299 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2300 case HV_X64_MSR_CRASH_CTL:
2301 return kvm_hv_get_msr_common(vcpu,
2302 msr_info->index, &msr_info->data);
2303 break;
2304 case MSR_IA32_BBL_CR_CTL3:
2305 /* This legacy MSR exists but isn't fully documented in current
2306 * silicon. It is however accessed by winxp in very narrow
2307 * scenarios where it sets bit #19, itself documented as
2308 * a "reserved" bit. Best effort attempt to source coherent
2309 * read data here should the balance of the register be
2310 * interpreted by the guest:
2311 *
2312 * L2 cache control register 3: 64GB range, 256KB size,
2313 * enabled, latency 0x1, configured
2314 */
2315 msr_info->data = 0xbe702111;
2316 break;
2317 case MSR_AMD64_OSVW_ID_LENGTH:
2318 if (!guest_cpuid_has_osvw(vcpu))
2319 return 1;
2320 msr_info->data = vcpu->arch.osvw.length;
2321 break;
2322 case MSR_AMD64_OSVW_STATUS:
2323 if (!guest_cpuid_has_osvw(vcpu))
2324 return 1;
2325 msr_info->data = vcpu->arch.osvw.status;
2326 break;
2327 default:
2328 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2329 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2330 if (!ignore_msrs) {
2331 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2332 return 1;
2333 } else {
2334 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2335 msr_info->data = 0;
2336 }
2337 break;
2338 }
2339 return 0;
2340 }
2341 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2342
2343 /*
2344 * Read or write a bunch of msrs. All parameters are kernel addresses.
2345 *
2346 * @return number of msrs set successfully.
2347 */
2348 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2349 struct kvm_msr_entry *entries,
2350 int (*do_msr)(struct kvm_vcpu *vcpu,
2351 unsigned index, u64 *data))
2352 {
2353 int i, idx;
2354
2355 idx = srcu_read_lock(&vcpu->kvm->srcu);
2356 for (i = 0; i < msrs->nmsrs; ++i)
2357 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2358 break;
2359 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2360
2361 return i;
2362 }
2363
2364 /*
2365 * Read or write a bunch of msrs. Parameters are user addresses.
2366 *
2367 * @return number of msrs set successfully.
2368 */
2369 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2370 int (*do_msr)(struct kvm_vcpu *vcpu,
2371 unsigned index, u64 *data),
2372 int writeback)
2373 {
2374 struct kvm_msrs msrs;
2375 struct kvm_msr_entry *entries;
2376 int r, n;
2377 unsigned size;
2378
2379 r = -EFAULT;
2380 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2381 goto out;
2382
2383 r = -E2BIG;
2384 if (msrs.nmsrs >= MAX_IO_MSRS)
2385 goto out;
2386
2387 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2388 entries = memdup_user(user_msrs->entries, size);
2389 if (IS_ERR(entries)) {
2390 r = PTR_ERR(entries);
2391 goto out;
2392 }
2393
2394 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2395 if (r < 0)
2396 goto out_free;
2397
2398 r = -EFAULT;
2399 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2400 goto out_free;
2401
2402 r = n;
2403
2404 out_free:
2405 kfree(entries);
2406 out:
2407 return r;
2408 }
2409
2410 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2411 {
2412 int r;
2413
2414 switch (ext) {
2415 case KVM_CAP_IRQCHIP:
2416 case KVM_CAP_HLT:
2417 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2418 case KVM_CAP_SET_TSS_ADDR:
2419 case KVM_CAP_EXT_CPUID:
2420 case KVM_CAP_EXT_EMUL_CPUID:
2421 case KVM_CAP_CLOCKSOURCE:
2422 case KVM_CAP_PIT:
2423 case KVM_CAP_NOP_IO_DELAY:
2424 case KVM_CAP_MP_STATE:
2425 case KVM_CAP_SYNC_MMU:
2426 case KVM_CAP_USER_NMI:
2427 case KVM_CAP_REINJECT_CONTROL:
2428 case KVM_CAP_IRQ_INJECT_STATUS:
2429 case KVM_CAP_IOEVENTFD:
2430 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2431 case KVM_CAP_PIT2:
2432 case KVM_CAP_PIT_STATE2:
2433 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2434 case KVM_CAP_XEN_HVM:
2435 case KVM_CAP_ADJUST_CLOCK:
2436 case KVM_CAP_VCPU_EVENTS:
2437 case KVM_CAP_HYPERV:
2438 case KVM_CAP_HYPERV_VAPIC:
2439 case KVM_CAP_HYPERV_SPIN:
2440 case KVM_CAP_PCI_SEGMENT:
2441 case KVM_CAP_DEBUGREGS:
2442 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2443 case KVM_CAP_XSAVE:
2444 case KVM_CAP_ASYNC_PF:
2445 case KVM_CAP_GET_TSC_KHZ:
2446 case KVM_CAP_KVMCLOCK_CTRL:
2447 case KVM_CAP_READONLY_MEM:
2448 case KVM_CAP_HYPERV_TIME:
2449 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2450 case KVM_CAP_TSC_DEADLINE_TIMER:
2451 case KVM_CAP_ENABLE_CAP_VM:
2452 case KVM_CAP_DISABLE_QUIRKS:
2453 case KVM_CAP_SET_BOOT_CPU_ID:
2454 case KVM_CAP_SPLIT_IRQCHIP:
2455 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2456 case KVM_CAP_ASSIGN_DEV_IRQ:
2457 case KVM_CAP_PCI_2_3:
2458 #endif
2459 r = 1;
2460 break;
2461 case KVM_CAP_X86_SMM:
2462 /* SMBASE is usually relocated above 1M on modern chipsets,
2463 * and SMM handlers might indeed rely on 4G segment limits,
2464 * so do not report SMM to be available if real mode is
2465 * emulated via vm86 mode. Still, do not go to great lengths
2466 * to avoid userspace's usage of the feature, because it is a
2467 * fringe case that is not enabled except via specific settings
2468 * of the module parameters.
2469 */
2470 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2471 break;
2472 case KVM_CAP_COALESCED_MMIO:
2473 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2474 break;
2475 case KVM_CAP_VAPIC:
2476 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2477 break;
2478 case KVM_CAP_NR_VCPUS:
2479 r = KVM_SOFT_MAX_VCPUS;
2480 break;
2481 case KVM_CAP_MAX_VCPUS:
2482 r = KVM_MAX_VCPUS;
2483 break;
2484 case KVM_CAP_NR_MEMSLOTS:
2485 r = KVM_USER_MEM_SLOTS;
2486 break;
2487 case KVM_CAP_PV_MMU: /* obsolete */
2488 r = 0;
2489 break;
2490 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2491 case KVM_CAP_IOMMU:
2492 r = iommu_present(&pci_bus_type);
2493 break;
2494 #endif
2495 case KVM_CAP_MCE:
2496 r = KVM_MAX_MCE_BANKS;
2497 break;
2498 case KVM_CAP_XCRS:
2499 r = cpu_has_xsave;
2500 break;
2501 case KVM_CAP_TSC_CONTROL:
2502 r = kvm_has_tsc_control;
2503 break;
2504 default:
2505 r = 0;
2506 break;
2507 }
2508 return r;
2509
2510 }
2511
2512 long kvm_arch_dev_ioctl(struct file *filp,
2513 unsigned int ioctl, unsigned long arg)
2514 {
2515 void __user *argp = (void __user *)arg;
2516 long r;
2517
2518 switch (ioctl) {
2519 case KVM_GET_MSR_INDEX_LIST: {
2520 struct kvm_msr_list __user *user_msr_list = argp;
2521 struct kvm_msr_list msr_list;
2522 unsigned n;
2523
2524 r = -EFAULT;
2525 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2526 goto out;
2527 n = msr_list.nmsrs;
2528 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2529 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2530 goto out;
2531 r = -E2BIG;
2532 if (n < msr_list.nmsrs)
2533 goto out;
2534 r = -EFAULT;
2535 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2536 num_msrs_to_save * sizeof(u32)))
2537 goto out;
2538 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2539 &emulated_msrs,
2540 num_emulated_msrs * sizeof(u32)))
2541 goto out;
2542 r = 0;
2543 break;
2544 }
2545 case KVM_GET_SUPPORTED_CPUID:
2546 case KVM_GET_EMULATED_CPUID: {
2547 struct kvm_cpuid2 __user *cpuid_arg = argp;
2548 struct kvm_cpuid2 cpuid;
2549
2550 r = -EFAULT;
2551 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2552 goto out;
2553
2554 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2555 ioctl);
2556 if (r)
2557 goto out;
2558
2559 r = -EFAULT;
2560 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2561 goto out;
2562 r = 0;
2563 break;
2564 }
2565 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2566 u64 mce_cap;
2567
2568 mce_cap = KVM_MCE_CAP_SUPPORTED;
2569 r = -EFAULT;
2570 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2571 goto out;
2572 r = 0;
2573 break;
2574 }
2575 default:
2576 r = -EINVAL;
2577 }
2578 out:
2579 return r;
2580 }
2581
2582 static void wbinvd_ipi(void *garbage)
2583 {
2584 wbinvd();
2585 }
2586
2587 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2588 {
2589 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2590 }
2591
2592 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2593 {
2594 /* Address WBINVD may be executed by guest */
2595 if (need_emulate_wbinvd(vcpu)) {
2596 if (kvm_x86_ops->has_wbinvd_exit())
2597 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2598 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2599 smp_call_function_single(vcpu->cpu,
2600 wbinvd_ipi, NULL, 1);
2601 }
2602
2603 kvm_x86_ops->vcpu_load(vcpu, cpu);
2604
2605 /* Apply any externally detected TSC adjustments (due to suspend) */
2606 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2607 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2608 vcpu->arch.tsc_offset_adjustment = 0;
2609 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2610 }
2611
2612 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2613 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2614 rdtsc() - vcpu->arch.last_host_tsc;
2615 if (tsc_delta < 0)
2616 mark_tsc_unstable("KVM discovered backwards TSC");
2617 if (check_tsc_unstable()) {
2618 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2619 vcpu->arch.last_guest_tsc);
2620 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2621 vcpu->arch.tsc_catchup = 1;
2622 }
2623 /*
2624 * On a host with synchronized TSC, there is no need to update
2625 * kvmclock on vcpu->cpu migration
2626 */
2627 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2628 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2629 if (vcpu->cpu != cpu)
2630 kvm_migrate_timers(vcpu);
2631 vcpu->cpu = cpu;
2632 }
2633
2634 accumulate_steal_time(vcpu);
2635 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2636 }
2637
2638 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2639 {
2640 kvm_x86_ops->vcpu_put(vcpu);
2641 kvm_put_guest_fpu(vcpu);
2642 vcpu->arch.last_host_tsc = rdtsc();
2643 }
2644
2645 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2646 struct kvm_lapic_state *s)
2647 {
2648 kvm_x86_ops->sync_pir_to_irr(vcpu);
2649 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2650
2651 return 0;
2652 }
2653
2654 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2655 struct kvm_lapic_state *s)
2656 {
2657 kvm_apic_post_state_restore(vcpu, s);
2658 update_cr8_intercept(vcpu);
2659
2660 return 0;
2661 }
2662
2663 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2664 struct kvm_interrupt *irq)
2665 {
2666 if (irq->irq >= KVM_NR_INTERRUPTS)
2667 return -EINVAL;
2668
2669 if (!irqchip_in_kernel(vcpu->kvm)) {
2670 kvm_queue_interrupt(vcpu, irq->irq, false);
2671 kvm_make_request(KVM_REQ_EVENT, vcpu);
2672 return 0;
2673 }
2674
2675 /*
2676 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2677 * fail for in-kernel 8259.
2678 */
2679 if (pic_in_kernel(vcpu->kvm))
2680 return -ENXIO;
2681
2682 if (vcpu->arch.pending_external_vector != -1)
2683 return -EEXIST;
2684
2685 vcpu->arch.pending_external_vector = irq->irq;
2686 return 0;
2687 }
2688
2689 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2690 {
2691 kvm_inject_nmi(vcpu);
2692
2693 return 0;
2694 }
2695
2696 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2697 {
2698 kvm_make_request(KVM_REQ_SMI, vcpu);
2699
2700 return 0;
2701 }
2702
2703 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2704 struct kvm_tpr_access_ctl *tac)
2705 {
2706 if (tac->flags)
2707 return -EINVAL;
2708 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2709 return 0;
2710 }
2711
2712 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2713 u64 mcg_cap)
2714 {
2715 int r;
2716 unsigned bank_num = mcg_cap & 0xff, bank;
2717
2718 r = -EINVAL;
2719 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2720 goto out;
2721 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2722 goto out;
2723 r = 0;
2724 vcpu->arch.mcg_cap = mcg_cap;
2725 /* Init IA32_MCG_CTL to all 1s */
2726 if (mcg_cap & MCG_CTL_P)
2727 vcpu->arch.mcg_ctl = ~(u64)0;
2728 /* Init IA32_MCi_CTL to all 1s */
2729 for (bank = 0; bank < bank_num; bank++)
2730 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2731 out:
2732 return r;
2733 }
2734
2735 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2736 struct kvm_x86_mce *mce)
2737 {
2738 u64 mcg_cap = vcpu->arch.mcg_cap;
2739 unsigned bank_num = mcg_cap & 0xff;
2740 u64 *banks = vcpu->arch.mce_banks;
2741
2742 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2743 return -EINVAL;
2744 /*
2745 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2746 * reporting is disabled
2747 */
2748 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2749 vcpu->arch.mcg_ctl != ~(u64)0)
2750 return 0;
2751 banks += 4 * mce->bank;
2752 /*
2753 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2754 * reporting is disabled for the bank
2755 */
2756 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2757 return 0;
2758 if (mce->status & MCI_STATUS_UC) {
2759 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2760 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2761 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2762 return 0;
2763 }
2764 if (banks[1] & MCI_STATUS_VAL)
2765 mce->status |= MCI_STATUS_OVER;
2766 banks[2] = mce->addr;
2767 banks[3] = mce->misc;
2768 vcpu->arch.mcg_status = mce->mcg_status;
2769 banks[1] = mce->status;
2770 kvm_queue_exception(vcpu, MC_VECTOR);
2771 } else if (!(banks[1] & MCI_STATUS_VAL)
2772 || !(banks[1] & MCI_STATUS_UC)) {
2773 if (banks[1] & MCI_STATUS_VAL)
2774 mce->status |= MCI_STATUS_OVER;
2775 banks[2] = mce->addr;
2776 banks[3] = mce->misc;
2777 banks[1] = mce->status;
2778 } else
2779 banks[1] |= MCI_STATUS_OVER;
2780 return 0;
2781 }
2782
2783 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2784 struct kvm_vcpu_events *events)
2785 {
2786 process_nmi(vcpu);
2787 events->exception.injected =
2788 vcpu->arch.exception.pending &&
2789 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2790 events->exception.nr = vcpu->arch.exception.nr;
2791 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2792 events->exception.pad = 0;
2793 events->exception.error_code = vcpu->arch.exception.error_code;
2794
2795 events->interrupt.injected =
2796 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2797 events->interrupt.nr = vcpu->arch.interrupt.nr;
2798 events->interrupt.soft = 0;
2799 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2800
2801 events->nmi.injected = vcpu->arch.nmi_injected;
2802 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2803 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2804 events->nmi.pad = 0;
2805
2806 events->sipi_vector = 0; /* never valid when reporting to user space */
2807
2808 events->smi.smm = is_smm(vcpu);
2809 events->smi.pending = vcpu->arch.smi_pending;
2810 events->smi.smm_inside_nmi =
2811 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2812 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2813
2814 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2815 | KVM_VCPUEVENT_VALID_SHADOW
2816 | KVM_VCPUEVENT_VALID_SMM);
2817 memset(&events->reserved, 0, sizeof(events->reserved));
2818 }
2819
2820 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2821 struct kvm_vcpu_events *events)
2822 {
2823 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2824 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2825 | KVM_VCPUEVENT_VALID_SHADOW
2826 | KVM_VCPUEVENT_VALID_SMM))
2827 return -EINVAL;
2828
2829 process_nmi(vcpu);
2830 vcpu->arch.exception.pending = events->exception.injected;
2831 vcpu->arch.exception.nr = events->exception.nr;
2832 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2833 vcpu->arch.exception.error_code = events->exception.error_code;
2834
2835 vcpu->arch.interrupt.pending = events->interrupt.injected;
2836 vcpu->arch.interrupt.nr = events->interrupt.nr;
2837 vcpu->arch.interrupt.soft = events->interrupt.soft;
2838 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2839 kvm_x86_ops->set_interrupt_shadow(vcpu,
2840 events->interrupt.shadow);
2841
2842 vcpu->arch.nmi_injected = events->nmi.injected;
2843 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2844 vcpu->arch.nmi_pending = events->nmi.pending;
2845 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2846
2847 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2848 kvm_vcpu_has_lapic(vcpu))
2849 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2850
2851 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2852 if (events->smi.smm)
2853 vcpu->arch.hflags |= HF_SMM_MASK;
2854 else
2855 vcpu->arch.hflags &= ~HF_SMM_MASK;
2856 vcpu->arch.smi_pending = events->smi.pending;
2857 if (events->smi.smm_inside_nmi)
2858 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2859 else
2860 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2861 if (kvm_vcpu_has_lapic(vcpu)) {
2862 if (events->smi.latched_init)
2863 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 else
2865 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2866 }
2867 }
2868
2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
2870
2871 return 0;
2872 }
2873
2874 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2875 struct kvm_debugregs *dbgregs)
2876 {
2877 unsigned long val;
2878
2879 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2880 kvm_get_dr(vcpu, 6, &val);
2881 dbgregs->dr6 = val;
2882 dbgregs->dr7 = vcpu->arch.dr7;
2883 dbgregs->flags = 0;
2884 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2885 }
2886
2887 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2888 struct kvm_debugregs *dbgregs)
2889 {
2890 if (dbgregs->flags)
2891 return -EINVAL;
2892
2893 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2894 kvm_update_dr0123(vcpu);
2895 vcpu->arch.dr6 = dbgregs->dr6;
2896 kvm_update_dr6(vcpu);
2897 vcpu->arch.dr7 = dbgregs->dr7;
2898 kvm_update_dr7(vcpu);
2899
2900 return 0;
2901 }
2902
2903 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2904
2905 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2906 {
2907 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2908 u64 xstate_bv = xsave->header.xfeatures;
2909 u64 valid;
2910
2911 /*
2912 * Copy legacy XSAVE area, to avoid complications with CPUID
2913 * leaves 0 and 1 in the loop below.
2914 */
2915 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2916
2917 /* Set XSTATE_BV */
2918 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2919
2920 /*
2921 * Copy each region from the possibly compacted offset to the
2922 * non-compacted offset.
2923 */
2924 valid = xstate_bv & ~XSTATE_FPSSE;
2925 while (valid) {
2926 u64 feature = valid & -valid;
2927 int index = fls64(feature) - 1;
2928 void *src = get_xsave_addr(xsave, feature);
2929
2930 if (src) {
2931 u32 size, offset, ecx, edx;
2932 cpuid_count(XSTATE_CPUID, index,
2933 &size, &offset, &ecx, &edx);
2934 memcpy(dest + offset, src, size);
2935 }
2936
2937 valid -= feature;
2938 }
2939 }
2940
2941 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2942 {
2943 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2944 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2945 u64 valid;
2946
2947 /*
2948 * Copy legacy XSAVE area, to avoid complications with CPUID
2949 * leaves 0 and 1 in the loop below.
2950 */
2951 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2952
2953 /* Set XSTATE_BV and possibly XCOMP_BV. */
2954 xsave->header.xfeatures = xstate_bv;
2955 if (cpu_has_xsaves)
2956 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2957
2958 /*
2959 * Copy each region from the non-compacted offset to the
2960 * possibly compacted offset.
2961 */
2962 valid = xstate_bv & ~XSTATE_FPSSE;
2963 while (valid) {
2964 u64 feature = valid & -valid;
2965 int index = fls64(feature) - 1;
2966 void *dest = get_xsave_addr(xsave, feature);
2967
2968 if (dest) {
2969 u32 size, offset, ecx, edx;
2970 cpuid_count(XSTATE_CPUID, index,
2971 &size, &offset, &ecx, &edx);
2972 memcpy(dest, src + offset, size);
2973 }
2974
2975 valid -= feature;
2976 }
2977 }
2978
2979 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2980 struct kvm_xsave *guest_xsave)
2981 {
2982 if (cpu_has_xsave) {
2983 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2984 fill_xsave((u8 *) guest_xsave->region, vcpu);
2985 } else {
2986 memcpy(guest_xsave->region,
2987 &vcpu->arch.guest_fpu.state.fxsave,
2988 sizeof(struct fxregs_state));
2989 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2990 XSTATE_FPSSE;
2991 }
2992 }
2993
2994 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2995 struct kvm_xsave *guest_xsave)
2996 {
2997 u64 xstate_bv =
2998 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2999
3000 if (cpu_has_xsave) {
3001 /*
3002 * Here we allow setting states that are not present in
3003 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3004 * with old userspace.
3005 */
3006 if (xstate_bv & ~kvm_supported_xcr0())
3007 return -EINVAL;
3008 load_xsave(vcpu, (u8 *)guest_xsave->region);
3009 } else {
3010 if (xstate_bv & ~XSTATE_FPSSE)
3011 return -EINVAL;
3012 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3013 guest_xsave->region, sizeof(struct fxregs_state));
3014 }
3015 return 0;
3016 }
3017
3018 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3019 struct kvm_xcrs *guest_xcrs)
3020 {
3021 if (!cpu_has_xsave) {
3022 guest_xcrs->nr_xcrs = 0;
3023 return;
3024 }
3025
3026 guest_xcrs->nr_xcrs = 1;
3027 guest_xcrs->flags = 0;
3028 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3029 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3030 }
3031
3032 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3033 struct kvm_xcrs *guest_xcrs)
3034 {
3035 int i, r = 0;
3036
3037 if (!cpu_has_xsave)
3038 return -EINVAL;
3039
3040 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3041 return -EINVAL;
3042
3043 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3044 /* Only support XCR0 currently */
3045 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3046 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3047 guest_xcrs->xcrs[i].value);
3048 break;
3049 }
3050 if (r)
3051 r = -EINVAL;
3052 return r;
3053 }
3054
3055 /*
3056 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3057 * stopped by the hypervisor. This function will be called from the host only.
3058 * EINVAL is returned when the host attempts to set the flag for a guest that
3059 * does not support pv clocks.
3060 */
3061 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3062 {
3063 if (!vcpu->arch.pv_time_enabled)
3064 return -EINVAL;
3065 vcpu->arch.pvclock_set_guest_stopped_request = true;
3066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3067 return 0;
3068 }
3069
3070 long kvm_arch_vcpu_ioctl(struct file *filp,
3071 unsigned int ioctl, unsigned long arg)
3072 {
3073 struct kvm_vcpu *vcpu = filp->private_data;
3074 void __user *argp = (void __user *)arg;
3075 int r;
3076 union {
3077 struct kvm_lapic_state *lapic;
3078 struct kvm_xsave *xsave;
3079 struct kvm_xcrs *xcrs;
3080 void *buffer;
3081 } u;
3082
3083 u.buffer = NULL;
3084 switch (ioctl) {
3085 case KVM_GET_LAPIC: {
3086 r = -EINVAL;
3087 if (!vcpu->arch.apic)
3088 goto out;
3089 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3090
3091 r = -ENOMEM;
3092 if (!u.lapic)
3093 goto out;
3094 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3095 if (r)
3096 goto out;
3097 r = -EFAULT;
3098 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3099 goto out;
3100 r = 0;
3101 break;
3102 }
3103 case KVM_SET_LAPIC: {
3104 r = -EINVAL;
3105 if (!vcpu->arch.apic)
3106 goto out;
3107 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3108 if (IS_ERR(u.lapic))
3109 return PTR_ERR(u.lapic);
3110
3111 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3112 break;
3113 }
3114 case KVM_INTERRUPT: {
3115 struct kvm_interrupt irq;
3116
3117 r = -EFAULT;
3118 if (copy_from_user(&irq, argp, sizeof irq))
3119 goto out;
3120 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3121 break;
3122 }
3123 case KVM_NMI: {
3124 r = kvm_vcpu_ioctl_nmi(vcpu);
3125 break;
3126 }
3127 case KVM_SMI: {
3128 r = kvm_vcpu_ioctl_smi(vcpu);
3129 break;
3130 }
3131 case KVM_SET_CPUID: {
3132 struct kvm_cpuid __user *cpuid_arg = argp;
3133 struct kvm_cpuid cpuid;
3134
3135 r = -EFAULT;
3136 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3137 goto out;
3138 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3139 break;
3140 }
3141 case KVM_SET_CPUID2: {
3142 struct kvm_cpuid2 __user *cpuid_arg = argp;
3143 struct kvm_cpuid2 cpuid;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3147 goto out;
3148 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3149 cpuid_arg->entries);
3150 break;
3151 }
3152 case KVM_GET_CPUID2: {
3153 struct kvm_cpuid2 __user *cpuid_arg = argp;
3154 struct kvm_cpuid2 cpuid;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3158 goto out;
3159 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3160 cpuid_arg->entries);
3161 if (r)
3162 goto out;
3163 r = -EFAULT;
3164 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3165 goto out;
3166 r = 0;
3167 break;
3168 }
3169 case KVM_GET_MSRS:
3170 r = msr_io(vcpu, argp, do_get_msr, 1);
3171 break;
3172 case KVM_SET_MSRS:
3173 r = msr_io(vcpu, argp, do_set_msr, 0);
3174 break;
3175 case KVM_TPR_ACCESS_REPORTING: {
3176 struct kvm_tpr_access_ctl tac;
3177
3178 r = -EFAULT;
3179 if (copy_from_user(&tac, argp, sizeof tac))
3180 goto out;
3181 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3182 if (r)
3183 goto out;
3184 r = -EFAULT;
3185 if (copy_to_user(argp, &tac, sizeof tac))
3186 goto out;
3187 r = 0;
3188 break;
3189 };
3190 case KVM_SET_VAPIC_ADDR: {
3191 struct kvm_vapic_addr va;
3192
3193 r = -EINVAL;
3194 if (!lapic_in_kernel(vcpu))
3195 goto out;
3196 r = -EFAULT;
3197 if (copy_from_user(&va, argp, sizeof va))
3198 goto out;
3199 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3200 break;
3201 }
3202 case KVM_X86_SETUP_MCE: {
3203 u64 mcg_cap;
3204
3205 r = -EFAULT;
3206 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3207 goto out;
3208 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3209 break;
3210 }
3211 case KVM_X86_SET_MCE: {
3212 struct kvm_x86_mce mce;
3213
3214 r = -EFAULT;
3215 if (copy_from_user(&mce, argp, sizeof mce))
3216 goto out;
3217 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3218 break;
3219 }
3220 case KVM_GET_VCPU_EVENTS: {
3221 struct kvm_vcpu_events events;
3222
3223 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3224
3225 r = -EFAULT;
3226 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3227 break;
3228 r = 0;
3229 break;
3230 }
3231 case KVM_SET_VCPU_EVENTS: {
3232 struct kvm_vcpu_events events;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3236 break;
3237
3238 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3239 break;
3240 }
3241 case KVM_GET_DEBUGREGS: {
3242 struct kvm_debugregs dbgregs;
3243
3244 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3245
3246 r = -EFAULT;
3247 if (copy_to_user(argp, &dbgregs,
3248 sizeof(struct kvm_debugregs)))
3249 break;
3250 r = 0;
3251 break;
3252 }
3253 case KVM_SET_DEBUGREGS: {
3254 struct kvm_debugregs dbgregs;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&dbgregs, argp,
3258 sizeof(struct kvm_debugregs)))
3259 break;
3260
3261 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3262 break;
3263 }
3264 case KVM_GET_XSAVE: {
3265 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3266 r = -ENOMEM;
3267 if (!u.xsave)
3268 break;
3269
3270 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3271
3272 r = -EFAULT;
3273 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3274 break;
3275 r = 0;
3276 break;
3277 }
3278 case KVM_SET_XSAVE: {
3279 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3280 if (IS_ERR(u.xsave))
3281 return PTR_ERR(u.xsave);
3282
3283 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3284 break;
3285 }
3286 case KVM_GET_XCRS: {
3287 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3288 r = -ENOMEM;
3289 if (!u.xcrs)
3290 break;
3291
3292 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3293
3294 r = -EFAULT;
3295 if (copy_to_user(argp, u.xcrs,
3296 sizeof(struct kvm_xcrs)))
3297 break;
3298 r = 0;
3299 break;
3300 }
3301 case KVM_SET_XCRS: {
3302 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3303 if (IS_ERR(u.xcrs))
3304 return PTR_ERR(u.xcrs);
3305
3306 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3307 break;
3308 }
3309 case KVM_SET_TSC_KHZ: {
3310 u32 user_tsc_khz;
3311
3312 r = -EINVAL;
3313 user_tsc_khz = (u32)arg;
3314
3315 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3316 goto out;
3317
3318 if (user_tsc_khz == 0)
3319 user_tsc_khz = tsc_khz;
3320
3321 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3322
3323 r = 0;
3324 goto out;
3325 }
3326 case KVM_GET_TSC_KHZ: {
3327 r = vcpu->arch.virtual_tsc_khz;
3328 goto out;
3329 }
3330 case KVM_KVMCLOCK_CTRL: {
3331 r = kvm_set_guest_paused(vcpu);
3332 goto out;
3333 }
3334 default:
3335 r = -EINVAL;
3336 }
3337 out:
3338 kfree(u.buffer);
3339 return r;
3340 }
3341
3342 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3343 {
3344 return VM_FAULT_SIGBUS;
3345 }
3346
3347 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3348 {
3349 int ret;
3350
3351 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3352 return -EINVAL;
3353 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3354 return ret;
3355 }
3356
3357 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3358 u64 ident_addr)
3359 {
3360 kvm->arch.ept_identity_map_addr = ident_addr;
3361 return 0;
3362 }
3363
3364 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3365 u32 kvm_nr_mmu_pages)
3366 {
3367 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3368 return -EINVAL;
3369
3370 mutex_lock(&kvm->slots_lock);
3371
3372 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3373 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3374
3375 mutex_unlock(&kvm->slots_lock);
3376 return 0;
3377 }
3378
3379 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3380 {
3381 return kvm->arch.n_max_mmu_pages;
3382 }
3383
3384 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3385 {
3386 int r;
3387
3388 r = 0;
3389 switch (chip->chip_id) {
3390 case KVM_IRQCHIP_PIC_MASTER:
3391 memcpy(&chip->chip.pic,
3392 &pic_irqchip(kvm)->pics[0],
3393 sizeof(struct kvm_pic_state));
3394 break;
3395 case KVM_IRQCHIP_PIC_SLAVE:
3396 memcpy(&chip->chip.pic,
3397 &pic_irqchip(kvm)->pics[1],
3398 sizeof(struct kvm_pic_state));
3399 break;
3400 case KVM_IRQCHIP_IOAPIC:
3401 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3402 break;
3403 default:
3404 r = -EINVAL;
3405 break;
3406 }
3407 return r;
3408 }
3409
3410 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3411 {
3412 int r;
3413
3414 r = 0;
3415 switch (chip->chip_id) {
3416 case KVM_IRQCHIP_PIC_MASTER:
3417 spin_lock(&pic_irqchip(kvm)->lock);
3418 memcpy(&pic_irqchip(kvm)->pics[0],
3419 &chip->chip.pic,
3420 sizeof(struct kvm_pic_state));
3421 spin_unlock(&pic_irqchip(kvm)->lock);
3422 break;
3423 case KVM_IRQCHIP_PIC_SLAVE:
3424 spin_lock(&pic_irqchip(kvm)->lock);
3425 memcpy(&pic_irqchip(kvm)->pics[1],
3426 &chip->chip.pic,
3427 sizeof(struct kvm_pic_state));
3428 spin_unlock(&pic_irqchip(kvm)->lock);
3429 break;
3430 case KVM_IRQCHIP_IOAPIC:
3431 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3432 break;
3433 default:
3434 r = -EINVAL;
3435 break;
3436 }
3437 kvm_pic_update_irq(pic_irqchip(kvm));
3438 return r;
3439 }
3440
3441 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3442 {
3443 int r = 0;
3444
3445 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3446 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3447 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3448 return r;
3449 }
3450
3451 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3452 {
3453 int r = 0;
3454
3455 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3456 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3457 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3458 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3459 return r;
3460 }
3461
3462 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3463 {
3464 int r = 0;
3465
3466 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3467 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3468 sizeof(ps->channels));
3469 ps->flags = kvm->arch.vpit->pit_state.flags;
3470 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3471 memset(&ps->reserved, 0, sizeof(ps->reserved));
3472 return r;
3473 }
3474
3475 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3476 {
3477 int r = 0, start = 0;
3478 u32 prev_legacy, cur_legacy;
3479 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3480 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3481 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3482 if (!prev_legacy && cur_legacy)
3483 start = 1;
3484 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3485 sizeof(kvm->arch.vpit->pit_state.channels));
3486 kvm->arch.vpit->pit_state.flags = ps->flags;
3487 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3488 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3489 return r;
3490 }
3491
3492 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3493 struct kvm_reinject_control *control)
3494 {
3495 if (!kvm->arch.vpit)
3496 return -ENXIO;
3497 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3498 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3499 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3500 return 0;
3501 }
3502
3503 /**
3504 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3505 * @kvm: kvm instance
3506 * @log: slot id and address to which we copy the log
3507 *
3508 * Steps 1-4 below provide general overview of dirty page logging. See
3509 * kvm_get_dirty_log_protect() function description for additional details.
3510 *
3511 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3512 * always flush the TLB (step 4) even if previous step failed and the dirty
3513 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3514 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3515 * writes will be marked dirty for next log read.
3516 *
3517 * 1. Take a snapshot of the bit and clear it if needed.
3518 * 2. Write protect the corresponding page.
3519 * 3. Copy the snapshot to the userspace.
3520 * 4. Flush TLB's if needed.
3521 */
3522 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3523 {
3524 bool is_dirty = false;
3525 int r;
3526
3527 mutex_lock(&kvm->slots_lock);
3528
3529 /*
3530 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3531 */
3532 if (kvm_x86_ops->flush_log_dirty)
3533 kvm_x86_ops->flush_log_dirty(kvm);
3534
3535 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3536
3537 /*
3538 * All the TLBs can be flushed out of mmu lock, see the comments in
3539 * kvm_mmu_slot_remove_write_access().
3540 */
3541 lockdep_assert_held(&kvm->slots_lock);
3542 if (is_dirty)
3543 kvm_flush_remote_tlbs(kvm);
3544
3545 mutex_unlock(&kvm->slots_lock);
3546 return r;
3547 }
3548
3549 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3550 bool line_status)
3551 {
3552 if (!irqchip_in_kernel(kvm))
3553 return -ENXIO;
3554
3555 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3556 irq_event->irq, irq_event->level,
3557 line_status);
3558 return 0;
3559 }
3560
3561 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3562 struct kvm_enable_cap *cap)
3563 {
3564 int r;
3565
3566 if (cap->flags)
3567 return -EINVAL;
3568
3569 switch (cap->cap) {
3570 case KVM_CAP_DISABLE_QUIRKS:
3571 kvm->arch.disabled_quirks = cap->args[0];
3572 r = 0;
3573 break;
3574 case KVM_CAP_SPLIT_IRQCHIP: {
3575 mutex_lock(&kvm->lock);
3576 r = -EINVAL;
3577 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3578 goto split_irqchip_unlock;
3579 r = -EEXIST;
3580 if (irqchip_in_kernel(kvm))
3581 goto split_irqchip_unlock;
3582 if (atomic_read(&kvm->online_vcpus))
3583 goto split_irqchip_unlock;
3584 r = kvm_setup_empty_irq_routing(kvm);
3585 if (r)
3586 goto split_irqchip_unlock;
3587 /* Pairs with irqchip_in_kernel. */
3588 smp_wmb();
3589 kvm->arch.irqchip_split = true;
3590 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3591 r = 0;
3592 split_irqchip_unlock:
3593 mutex_unlock(&kvm->lock);
3594 break;
3595 }
3596 default:
3597 r = -EINVAL;
3598 break;
3599 }
3600 return r;
3601 }
3602
3603 long kvm_arch_vm_ioctl(struct file *filp,
3604 unsigned int ioctl, unsigned long arg)
3605 {
3606 struct kvm *kvm = filp->private_data;
3607 void __user *argp = (void __user *)arg;
3608 int r = -ENOTTY;
3609 /*
3610 * This union makes it completely explicit to gcc-3.x
3611 * that these two variables' stack usage should be
3612 * combined, not added together.
3613 */
3614 union {
3615 struct kvm_pit_state ps;
3616 struct kvm_pit_state2 ps2;
3617 struct kvm_pit_config pit_config;
3618 } u;
3619
3620 switch (ioctl) {
3621 case KVM_SET_TSS_ADDR:
3622 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3623 break;
3624 case KVM_SET_IDENTITY_MAP_ADDR: {
3625 u64 ident_addr;
3626
3627 r = -EFAULT;
3628 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3629 goto out;
3630 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3631 break;
3632 }
3633 case KVM_SET_NR_MMU_PAGES:
3634 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3635 break;
3636 case KVM_GET_NR_MMU_PAGES:
3637 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3638 break;
3639 case KVM_CREATE_IRQCHIP: {
3640 struct kvm_pic *vpic;
3641
3642 mutex_lock(&kvm->lock);
3643 r = -EEXIST;
3644 if (kvm->arch.vpic)
3645 goto create_irqchip_unlock;
3646 r = -EINVAL;
3647 if (atomic_read(&kvm->online_vcpus))
3648 goto create_irqchip_unlock;
3649 r = -ENOMEM;
3650 vpic = kvm_create_pic(kvm);
3651 if (vpic) {
3652 r = kvm_ioapic_init(kvm);
3653 if (r) {
3654 mutex_lock(&kvm->slots_lock);
3655 kvm_destroy_pic(vpic);
3656 mutex_unlock(&kvm->slots_lock);
3657 goto create_irqchip_unlock;
3658 }
3659 } else
3660 goto create_irqchip_unlock;
3661 r = kvm_setup_default_irq_routing(kvm);
3662 if (r) {
3663 mutex_lock(&kvm->slots_lock);
3664 mutex_lock(&kvm->irq_lock);
3665 kvm_ioapic_destroy(kvm);
3666 kvm_destroy_pic(vpic);
3667 mutex_unlock(&kvm->irq_lock);
3668 mutex_unlock(&kvm->slots_lock);
3669 goto create_irqchip_unlock;
3670 }
3671 /* Write kvm->irq_routing before kvm->arch.vpic. */
3672 smp_wmb();
3673 kvm->arch.vpic = vpic;
3674 create_irqchip_unlock:
3675 mutex_unlock(&kvm->lock);
3676 break;
3677 }
3678 case KVM_CREATE_PIT:
3679 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3680 goto create_pit;
3681 case KVM_CREATE_PIT2:
3682 r = -EFAULT;
3683 if (copy_from_user(&u.pit_config, argp,
3684 sizeof(struct kvm_pit_config)))
3685 goto out;
3686 create_pit:
3687 mutex_lock(&kvm->slots_lock);
3688 r = -EEXIST;
3689 if (kvm->arch.vpit)
3690 goto create_pit_unlock;
3691 r = -ENOMEM;
3692 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3693 if (kvm->arch.vpit)
3694 r = 0;
3695 create_pit_unlock:
3696 mutex_unlock(&kvm->slots_lock);
3697 break;
3698 case KVM_GET_IRQCHIP: {
3699 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3700 struct kvm_irqchip *chip;
3701
3702 chip = memdup_user(argp, sizeof(*chip));
3703 if (IS_ERR(chip)) {
3704 r = PTR_ERR(chip);
3705 goto out;
3706 }
3707
3708 r = -ENXIO;
3709 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3710 goto get_irqchip_out;
3711 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3712 if (r)
3713 goto get_irqchip_out;
3714 r = -EFAULT;
3715 if (copy_to_user(argp, chip, sizeof *chip))
3716 goto get_irqchip_out;
3717 r = 0;
3718 get_irqchip_out:
3719 kfree(chip);
3720 break;
3721 }
3722 case KVM_SET_IRQCHIP: {
3723 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3724 struct kvm_irqchip *chip;
3725
3726 chip = memdup_user(argp, sizeof(*chip));
3727 if (IS_ERR(chip)) {
3728 r = PTR_ERR(chip);
3729 goto out;
3730 }
3731
3732 r = -ENXIO;
3733 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3734 goto set_irqchip_out;
3735 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3736 if (r)
3737 goto set_irqchip_out;
3738 r = 0;
3739 set_irqchip_out:
3740 kfree(chip);
3741 break;
3742 }
3743 case KVM_GET_PIT: {
3744 r = -EFAULT;
3745 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3746 goto out;
3747 r = -ENXIO;
3748 if (!kvm->arch.vpit)
3749 goto out;
3750 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3751 if (r)
3752 goto out;
3753 r = -EFAULT;
3754 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3755 goto out;
3756 r = 0;
3757 break;
3758 }
3759 case KVM_SET_PIT: {
3760 r = -EFAULT;
3761 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3762 goto out;
3763 r = -ENXIO;
3764 if (!kvm->arch.vpit)
3765 goto out;
3766 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3767 break;
3768 }
3769 case KVM_GET_PIT2: {
3770 r = -ENXIO;
3771 if (!kvm->arch.vpit)
3772 goto out;
3773 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3774 if (r)
3775 goto out;
3776 r = -EFAULT;
3777 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3778 goto out;
3779 r = 0;
3780 break;
3781 }
3782 case KVM_SET_PIT2: {
3783 r = -EFAULT;
3784 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3785 goto out;
3786 r = -ENXIO;
3787 if (!kvm->arch.vpit)
3788 goto out;
3789 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3790 break;
3791 }
3792 case KVM_REINJECT_CONTROL: {
3793 struct kvm_reinject_control control;
3794 r = -EFAULT;
3795 if (copy_from_user(&control, argp, sizeof(control)))
3796 goto out;
3797 r = kvm_vm_ioctl_reinject(kvm, &control);
3798 break;
3799 }
3800 case KVM_SET_BOOT_CPU_ID:
3801 r = 0;
3802 mutex_lock(&kvm->lock);
3803 if (atomic_read(&kvm->online_vcpus) != 0)
3804 r = -EBUSY;
3805 else
3806 kvm->arch.bsp_vcpu_id = arg;
3807 mutex_unlock(&kvm->lock);
3808 break;
3809 case KVM_XEN_HVM_CONFIG: {
3810 r = -EFAULT;
3811 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3812 sizeof(struct kvm_xen_hvm_config)))
3813 goto out;
3814 r = -EINVAL;
3815 if (kvm->arch.xen_hvm_config.flags)
3816 goto out;
3817 r = 0;
3818 break;
3819 }
3820 case KVM_SET_CLOCK: {
3821 struct kvm_clock_data user_ns;
3822 u64 now_ns;
3823 s64 delta;
3824
3825 r = -EFAULT;
3826 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3827 goto out;
3828
3829 r = -EINVAL;
3830 if (user_ns.flags)
3831 goto out;
3832
3833 r = 0;
3834 local_irq_disable();
3835 now_ns = get_kernel_ns();
3836 delta = user_ns.clock - now_ns;
3837 local_irq_enable();
3838 kvm->arch.kvmclock_offset = delta;
3839 kvm_gen_update_masterclock(kvm);
3840 break;
3841 }
3842 case KVM_GET_CLOCK: {
3843 struct kvm_clock_data user_ns;
3844 u64 now_ns;
3845
3846 local_irq_disable();
3847 now_ns = get_kernel_ns();
3848 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3849 local_irq_enable();
3850 user_ns.flags = 0;
3851 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3852
3853 r = -EFAULT;
3854 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3855 goto out;
3856 r = 0;
3857 break;
3858 }
3859 case KVM_ENABLE_CAP: {
3860 struct kvm_enable_cap cap;
3861
3862 r = -EFAULT;
3863 if (copy_from_user(&cap, argp, sizeof(cap)))
3864 goto out;
3865 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3866 break;
3867 }
3868 default:
3869 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3870 }
3871 out:
3872 return r;
3873 }
3874
3875 static void kvm_init_msr_list(void)
3876 {
3877 u32 dummy[2];
3878 unsigned i, j;
3879
3880 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3881 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3882 continue;
3883
3884 /*
3885 * Even MSRs that are valid in the host may not be exposed
3886 * to the guests in some cases. We could work around this
3887 * in VMX with the generic MSR save/load machinery, but it
3888 * is not really worthwhile since it will really only
3889 * happen with nested virtualization.
3890 */
3891 switch (msrs_to_save[i]) {
3892 case MSR_IA32_BNDCFGS:
3893 if (!kvm_x86_ops->mpx_supported())
3894 continue;
3895 break;
3896 default:
3897 break;
3898 }
3899
3900 if (j < i)
3901 msrs_to_save[j] = msrs_to_save[i];
3902 j++;
3903 }
3904 num_msrs_to_save = j;
3905
3906 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3907 switch (emulated_msrs[i]) {
3908 case MSR_IA32_SMBASE:
3909 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3910 continue;
3911 break;
3912 default:
3913 break;
3914 }
3915
3916 if (j < i)
3917 emulated_msrs[j] = emulated_msrs[i];
3918 j++;
3919 }
3920 num_emulated_msrs = j;
3921 }
3922
3923 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3924 const void *v)
3925 {
3926 int handled = 0;
3927 int n;
3928
3929 do {
3930 n = min(len, 8);
3931 if (!(vcpu->arch.apic &&
3932 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3933 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3934 break;
3935 handled += n;
3936 addr += n;
3937 len -= n;
3938 v += n;
3939 } while (len);
3940
3941 return handled;
3942 }
3943
3944 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3945 {
3946 int handled = 0;
3947 int n;
3948
3949 do {
3950 n = min(len, 8);
3951 if (!(vcpu->arch.apic &&
3952 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3953 addr, n, v))
3954 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3955 break;
3956 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3957 handled += n;
3958 addr += n;
3959 len -= n;
3960 v += n;
3961 } while (len);
3962
3963 return handled;
3964 }
3965
3966 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3967 struct kvm_segment *var, int seg)
3968 {
3969 kvm_x86_ops->set_segment(vcpu, var, seg);
3970 }
3971
3972 void kvm_get_segment(struct kvm_vcpu *vcpu,
3973 struct kvm_segment *var, int seg)
3974 {
3975 kvm_x86_ops->get_segment(vcpu, var, seg);
3976 }
3977
3978 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3979 struct x86_exception *exception)
3980 {
3981 gpa_t t_gpa;
3982
3983 BUG_ON(!mmu_is_nested(vcpu));
3984
3985 /* NPT walks are always user-walks */
3986 access |= PFERR_USER_MASK;
3987 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3988
3989 return t_gpa;
3990 }
3991
3992 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3993 struct x86_exception *exception)
3994 {
3995 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3996 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3997 }
3998
3999 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
4001 {
4002 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4003 access |= PFERR_FETCH_MASK;
4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4005 }
4006
4007 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4008 struct x86_exception *exception)
4009 {
4010 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4011 access |= PFERR_WRITE_MASK;
4012 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4013 }
4014
4015 /* uses this to access any guest's mapped memory without checking CPL */
4016 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4017 struct x86_exception *exception)
4018 {
4019 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4020 }
4021
4022 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4023 struct kvm_vcpu *vcpu, u32 access,
4024 struct x86_exception *exception)
4025 {
4026 void *data = val;
4027 int r = X86EMUL_CONTINUE;
4028
4029 while (bytes) {
4030 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4031 exception);
4032 unsigned offset = addr & (PAGE_SIZE-1);
4033 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4034 int ret;
4035
4036 if (gpa == UNMAPPED_GVA)
4037 return X86EMUL_PROPAGATE_FAULT;
4038 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4039 offset, toread);
4040 if (ret < 0) {
4041 r = X86EMUL_IO_NEEDED;
4042 goto out;
4043 }
4044
4045 bytes -= toread;
4046 data += toread;
4047 addr += toread;
4048 }
4049 out:
4050 return r;
4051 }
4052
4053 /* used for instruction fetching */
4054 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4055 gva_t addr, void *val, unsigned int bytes,
4056 struct x86_exception *exception)
4057 {
4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4060 unsigned offset;
4061 int ret;
4062
4063 /* Inline kvm_read_guest_virt_helper for speed. */
4064 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4065 exception);
4066 if (unlikely(gpa == UNMAPPED_GVA))
4067 return X86EMUL_PROPAGATE_FAULT;
4068
4069 offset = addr & (PAGE_SIZE-1);
4070 if (WARN_ON(offset + bytes > PAGE_SIZE))
4071 bytes = (unsigned)PAGE_SIZE - offset;
4072 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4073 offset, bytes);
4074 if (unlikely(ret < 0))
4075 return X86EMUL_IO_NEEDED;
4076
4077 return X86EMUL_CONTINUE;
4078 }
4079
4080 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4081 gva_t addr, void *val, unsigned int bytes,
4082 struct x86_exception *exception)
4083 {
4084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4085 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4086
4087 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4088 exception);
4089 }
4090 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4091
4092 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4093 gva_t addr, void *val, unsigned int bytes,
4094 struct x86_exception *exception)
4095 {
4096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4097 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4098 }
4099
4100 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4101 gva_t addr, void *val,
4102 unsigned int bytes,
4103 struct x86_exception *exception)
4104 {
4105 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4106 void *data = val;
4107 int r = X86EMUL_CONTINUE;
4108
4109 while (bytes) {
4110 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4111 PFERR_WRITE_MASK,
4112 exception);
4113 unsigned offset = addr & (PAGE_SIZE-1);
4114 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4115 int ret;
4116
4117 if (gpa == UNMAPPED_GVA)
4118 return X86EMUL_PROPAGATE_FAULT;
4119 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4120 if (ret < 0) {
4121 r = X86EMUL_IO_NEEDED;
4122 goto out;
4123 }
4124
4125 bytes -= towrite;
4126 data += towrite;
4127 addr += towrite;
4128 }
4129 out:
4130 return r;
4131 }
4132 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4133
4134 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4135 gpa_t *gpa, struct x86_exception *exception,
4136 bool write)
4137 {
4138 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4139 | (write ? PFERR_WRITE_MASK : 0);
4140
4141 if (vcpu_match_mmio_gva(vcpu, gva)
4142 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4143 vcpu->arch.access, access)) {
4144 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4145 (gva & (PAGE_SIZE - 1));
4146 trace_vcpu_match_mmio(gva, *gpa, write, false);
4147 return 1;
4148 }
4149
4150 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4151
4152 if (*gpa == UNMAPPED_GVA)
4153 return -1;
4154
4155 /* For APIC access vmexit */
4156 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4157 return 1;
4158
4159 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4160 trace_vcpu_match_mmio(gva, *gpa, write, true);
4161 return 1;
4162 }
4163
4164 return 0;
4165 }
4166
4167 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4168 const void *val, int bytes)
4169 {
4170 int ret;
4171
4172 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4173 if (ret < 0)
4174 return 0;
4175 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4176 return 1;
4177 }
4178
4179 struct read_write_emulator_ops {
4180 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4181 int bytes);
4182 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4183 void *val, int bytes);
4184 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4185 int bytes, void *val);
4186 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4187 void *val, int bytes);
4188 bool write;
4189 };
4190
4191 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4192 {
4193 if (vcpu->mmio_read_completed) {
4194 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4195 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4196 vcpu->mmio_read_completed = 0;
4197 return 1;
4198 }
4199
4200 return 0;
4201 }
4202
4203 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4204 void *val, int bytes)
4205 {
4206 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4207 }
4208
4209 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4210 void *val, int bytes)
4211 {
4212 return emulator_write_phys(vcpu, gpa, val, bytes);
4213 }
4214
4215 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4216 {
4217 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4218 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4219 }
4220
4221 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4222 void *val, int bytes)
4223 {
4224 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4225 return X86EMUL_IO_NEEDED;
4226 }
4227
4228 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4229 void *val, int bytes)
4230 {
4231 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4232
4233 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4234 return X86EMUL_CONTINUE;
4235 }
4236
4237 static const struct read_write_emulator_ops read_emultor = {
4238 .read_write_prepare = read_prepare,
4239 .read_write_emulate = read_emulate,
4240 .read_write_mmio = vcpu_mmio_read,
4241 .read_write_exit_mmio = read_exit_mmio,
4242 };
4243
4244 static const struct read_write_emulator_ops write_emultor = {
4245 .read_write_emulate = write_emulate,
4246 .read_write_mmio = write_mmio,
4247 .read_write_exit_mmio = write_exit_mmio,
4248 .write = true,
4249 };
4250
4251 static int emulator_read_write_onepage(unsigned long addr, void *val,
4252 unsigned int bytes,
4253 struct x86_exception *exception,
4254 struct kvm_vcpu *vcpu,
4255 const struct read_write_emulator_ops *ops)
4256 {
4257 gpa_t gpa;
4258 int handled, ret;
4259 bool write = ops->write;
4260 struct kvm_mmio_fragment *frag;
4261
4262 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4263
4264 if (ret < 0)
4265 return X86EMUL_PROPAGATE_FAULT;
4266
4267 /* For APIC access vmexit */
4268 if (ret)
4269 goto mmio;
4270
4271 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4272 return X86EMUL_CONTINUE;
4273
4274 mmio:
4275 /*
4276 * Is this MMIO handled locally?
4277 */
4278 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4279 if (handled == bytes)
4280 return X86EMUL_CONTINUE;
4281
4282 gpa += handled;
4283 bytes -= handled;
4284 val += handled;
4285
4286 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4287 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4288 frag->gpa = gpa;
4289 frag->data = val;
4290 frag->len = bytes;
4291 return X86EMUL_CONTINUE;
4292 }
4293
4294 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4295 unsigned long addr,
4296 void *val, unsigned int bytes,
4297 struct x86_exception *exception,
4298 const struct read_write_emulator_ops *ops)
4299 {
4300 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4301 gpa_t gpa;
4302 int rc;
4303
4304 if (ops->read_write_prepare &&
4305 ops->read_write_prepare(vcpu, val, bytes))
4306 return X86EMUL_CONTINUE;
4307
4308 vcpu->mmio_nr_fragments = 0;
4309
4310 /* Crossing a page boundary? */
4311 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4312 int now;
4313
4314 now = -addr & ~PAGE_MASK;
4315 rc = emulator_read_write_onepage(addr, val, now, exception,
4316 vcpu, ops);
4317
4318 if (rc != X86EMUL_CONTINUE)
4319 return rc;
4320 addr += now;
4321 if (ctxt->mode != X86EMUL_MODE_PROT64)
4322 addr = (u32)addr;
4323 val += now;
4324 bytes -= now;
4325 }
4326
4327 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4328 vcpu, ops);
4329 if (rc != X86EMUL_CONTINUE)
4330 return rc;
4331
4332 if (!vcpu->mmio_nr_fragments)
4333 return rc;
4334
4335 gpa = vcpu->mmio_fragments[0].gpa;
4336
4337 vcpu->mmio_needed = 1;
4338 vcpu->mmio_cur_fragment = 0;
4339
4340 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4341 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4342 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4343 vcpu->run->mmio.phys_addr = gpa;
4344
4345 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4346 }
4347
4348 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4349 unsigned long addr,
4350 void *val,
4351 unsigned int bytes,
4352 struct x86_exception *exception)
4353 {
4354 return emulator_read_write(ctxt, addr, val, bytes,
4355 exception, &read_emultor);
4356 }
4357
4358 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4359 unsigned long addr,
4360 const void *val,
4361 unsigned int bytes,
4362 struct x86_exception *exception)
4363 {
4364 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4365 exception, &write_emultor);
4366 }
4367
4368 #define CMPXCHG_TYPE(t, ptr, old, new) \
4369 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4370
4371 #ifdef CONFIG_X86_64
4372 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4373 #else
4374 # define CMPXCHG64(ptr, old, new) \
4375 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4376 #endif
4377
4378 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4379 unsigned long addr,
4380 const void *old,
4381 const void *new,
4382 unsigned int bytes,
4383 struct x86_exception *exception)
4384 {
4385 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4386 gpa_t gpa;
4387 struct page *page;
4388 char *kaddr;
4389 bool exchanged;
4390
4391 /* guests cmpxchg8b have to be emulated atomically */
4392 if (bytes > 8 || (bytes & (bytes - 1)))
4393 goto emul_write;
4394
4395 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4396
4397 if (gpa == UNMAPPED_GVA ||
4398 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4399 goto emul_write;
4400
4401 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4402 goto emul_write;
4403
4404 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4405 if (is_error_page(page))
4406 goto emul_write;
4407
4408 kaddr = kmap_atomic(page);
4409 kaddr += offset_in_page(gpa);
4410 switch (bytes) {
4411 case 1:
4412 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4413 break;
4414 case 2:
4415 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4416 break;
4417 case 4:
4418 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4419 break;
4420 case 8:
4421 exchanged = CMPXCHG64(kaddr, old, new);
4422 break;
4423 default:
4424 BUG();
4425 }
4426 kunmap_atomic(kaddr);
4427 kvm_release_page_dirty(page);
4428
4429 if (!exchanged)
4430 return X86EMUL_CMPXCHG_FAILED;
4431
4432 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4433 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4434
4435 return X86EMUL_CONTINUE;
4436
4437 emul_write:
4438 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4439
4440 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4441 }
4442
4443 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4444 {
4445 /* TODO: String I/O for in kernel device */
4446 int r;
4447
4448 if (vcpu->arch.pio.in)
4449 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4450 vcpu->arch.pio.size, pd);
4451 else
4452 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4453 vcpu->arch.pio.port, vcpu->arch.pio.size,
4454 pd);
4455 return r;
4456 }
4457
4458 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4459 unsigned short port, void *val,
4460 unsigned int count, bool in)
4461 {
4462 vcpu->arch.pio.port = port;
4463 vcpu->arch.pio.in = in;
4464 vcpu->arch.pio.count = count;
4465 vcpu->arch.pio.size = size;
4466
4467 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4468 vcpu->arch.pio.count = 0;
4469 return 1;
4470 }
4471
4472 vcpu->run->exit_reason = KVM_EXIT_IO;
4473 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4474 vcpu->run->io.size = size;
4475 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4476 vcpu->run->io.count = count;
4477 vcpu->run->io.port = port;
4478
4479 return 0;
4480 }
4481
4482 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4483 int size, unsigned short port, void *val,
4484 unsigned int count)
4485 {
4486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4487 int ret;
4488
4489 if (vcpu->arch.pio.count)
4490 goto data_avail;
4491
4492 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4493 if (ret) {
4494 data_avail:
4495 memcpy(val, vcpu->arch.pio_data, size * count);
4496 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4497 vcpu->arch.pio.count = 0;
4498 return 1;
4499 }
4500
4501 return 0;
4502 }
4503
4504 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4505 int size, unsigned short port,
4506 const void *val, unsigned int count)
4507 {
4508 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4509
4510 memcpy(vcpu->arch.pio_data, val, size * count);
4511 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4512 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4513 }
4514
4515 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4516 {
4517 return kvm_x86_ops->get_segment_base(vcpu, seg);
4518 }
4519
4520 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4521 {
4522 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4523 }
4524
4525 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4526 {
4527 if (!need_emulate_wbinvd(vcpu))
4528 return X86EMUL_CONTINUE;
4529
4530 if (kvm_x86_ops->has_wbinvd_exit()) {
4531 int cpu = get_cpu();
4532
4533 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4534 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4535 wbinvd_ipi, NULL, 1);
4536 put_cpu();
4537 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4538 } else
4539 wbinvd();
4540 return X86EMUL_CONTINUE;
4541 }
4542
4543 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4544 {
4545 kvm_x86_ops->skip_emulated_instruction(vcpu);
4546 return kvm_emulate_wbinvd_noskip(vcpu);
4547 }
4548 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4549
4550
4551
4552 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4553 {
4554 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4555 }
4556
4557 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4558 unsigned long *dest)
4559 {
4560 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4561 }
4562
4563 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4564 unsigned long value)
4565 {
4566
4567 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4568 }
4569
4570 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4571 {
4572 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4573 }
4574
4575 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4576 {
4577 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4578 unsigned long value;
4579
4580 switch (cr) {
4581 case 0:
4582 value = kvm_read_cr0(vcpu);
4583 break;
4584 case 2:
4585 value = vcpu->arch.cr2;
4586 break;
4587 case 3:
4588 value = kvm_read_cr3(vcpu);
4589 break;
4590 case 4:
4591 value = kvm_read_cr4(vcpu);
4592 break;
4593 case 8:
4594 value = kvm_get_cr8(vcpu);
4595 break;
4596 default:
4597 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4598 return 0;
4599 }
4600
4601 return value;
4602 }
4603
4604 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4605 {
4606 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4607 int res = 0;
4608
4609 switch (cr) {
4610 case 0:
4611 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4612 break;
4613 case 2:
4614 vcpu->arch.cr2 = val;
4615 break;
4616 case 3:
4617 res = kvm_set_cr3(vcpu, val);
4618 break;
4619 case 4:
4620 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4621 break;
4622 case 8:
4623 res = kvm_set_cr8(vcpu, val);
4624 break;
4625 default:
4626 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4627 res = -1;
4628 }
4629
4630 return res;
4631 }
4632
4633 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4634 {
4635 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4636 }
4637
4638 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4639 {
4640 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4641 }
4642
4643 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4644 {
4645 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4646 }
4647
4648 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4649 {
4650 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4651 }
4652
4653 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4654 {
4655 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4656 }
4657
4658 static unsigned long emulator_get_cached_segment_base(
4659 struct x86_emulate_ctxt *ctxt, int seg)
4660 {
4661 return get_segment_base(emul_to_vcpu(ctxt), seg);
4662 }
4663
4664 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4665 struct desc_struct *desc, u32 *base3,
4666 int seg)
4667 {
4668 struct kvm_segment var;
4669
4670 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4671 *selector = var.selector;
4672
4673 if (var.unusable) {
4674 memset(desc, 0, sizeof(*desc));
4675 return false;
4676 }
4677
4678 if (var.g)
4679 var.limit >>= 12;
4680 set_desc_limit(desc, var.limit);
4681 set_desc_base(desc, (unsigned long)var.base);
4682 #ifdef CONFIG_X86_64
4683 if (base3)
4684 *base3 = var.base >> 32;
4685 #endif
4686 desc->type = var.type;
4687 desc->s = var.s;
4688 desc->dpl = var.dpl;
4689 desc->p = var.present;
4690 desc->avl = var.avl;
4691 desc->l = var.l;
4692 desc->d = var.db;
4693 desc->g = var.g;
4694
4695 return true;
4696 }
4697
4698 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4699 struct desc_struct *desc, u32 base3,
4700 int seg)
4701 {
4702 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4703 struct kvm_segment var;
4704
4705 var.selector = selector;
4706 var.base = get_desc_base(desc);
4707 #ifdef CONFIG_X86_64
4708 var.base |= ((u64)base3) << 32;
4709 #endif
4710 var.limit = get_desc_limit(desc);
4711 if (desc->g)
4712 var.limit = (var.limit << 12) | 0xfff;
4713 var.type = desc->type;
4714 var.dpl = desc->dpl;
4715 var.db = desc->d;
4716 var.s = desc->s;
4717 var.l = desc->l;
4718 var.g = desc->g;
4719 var.avl = desc->avl;
4720 var.present = desc->p;
4721 var.unusable = !var.present;
4722 var.padding = 0;
4723
4724 kvm_set_segment(vcpu, &var, seg);
4725 return;
4726 }
4727
4728 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4729 u32 msr_index, u64 *pdata)
4730 {
4731 struct msr_data msr;
4732 int r;
4733
4734 msr.index = msr_index;
4735 msr.host_initiated = false;
4736 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4737 if (r)
4738 return r;
4739
4740 *pdata = msr.data;
4741 return 0;
4742 }
4743
4744 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4745 u32 msr_index, u64 data)
4746 {
4747 struct msr_data msr;
4748
4749 msr.data = data;
4750 msr.index = msr_index;
4751 msr.host_initiated = false;
4752 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4753 }
4754
4755 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4756 {
4757 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4758
4759 return vcpu->arch.smbase;
4760 }
4761
4762 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4763 {
4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4765
4766 vcpu->arch.smbase = smbase;
4767 }
4768
4769 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4770 u32 pmc)
4771 {
4772 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4773 }
4774
4775 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4776 u32 pmc, u64 *pdata)
4777 {
4778 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4779 }
4780
4781 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4782 {
4783 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4784 }
4785
4786 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4787 {
4788 preempt_disable();
4789 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4790 /*
4791 * CR0.TS may reference the host fpu state, not the guest fpu state,
4792 * so it may be clear at this point.
4793 */
4794 clts();
4795 }
4796
4797 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4798 {
4799 preempt_enable();
4800 }
4801
4802 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4803 struct x86_instruction_info *info,
4804 enum x86_intercept_stage stage)
4805 {
4806 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4807 }
4808
4809 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4810 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4811 {
4812 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4813 }
4814
4815 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4816 {
4817 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4818 }
4819
4820 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4821 {
4822 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4823 }
4824
4825 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4826 {
4827 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4828 }
4829
4830 static const struct x86_emulate_ops emulate_ops = {
4831 .read_gpr = emulator_read_gpr,
4832 .write_gpr = emulator_write_gpr,
4833 .read_std = kvm_read_guest_virt_system,
4834 .write_std = kvm_write_guest_virt_system,
4835 .fetch = kvm_fetch_guest_virt,
4836 .read_emulated = emulator_read_emulated,
4837 .write_emulated = emulator_write_emulated,
4838 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4839 .invlpg = emulator_invlpg,
4840 .pio_in_emulated = emulator_pio_in_emulated,
4841 .pio_out_emulated = emulator_pio_out_emulated,
4842 .get_segment = emulator_get_segment,
4843 .set_segment = emulator_set_segment,
4844 .get_cached_segment_base = emulator_get_cached_segment_base,
4845 .get_gdt = emulator_get_gdt,
4846 .get_idt = emulator_get_idt,
4847 .set_gdt = emulator_set_gdt,
4848 .set_idt = emulator_set_idt,
4849 .get_cr = emulator_get_cr,
4850 .set_cr = emulator_set_cr,
4851 .cpl = emulator_get_cpl,
4852 .get_dr = emulator_get_dr,
4853 .set_dr = emulator_set_dr,
4854 .get_smbase = emulator_get_smbase,
4855 .set_smbase = emulator_set_smbase,
4856 .set_msr = emulator_set_msr,
4857 .get_msr = emulator_get_msr,
4858 .check_pmc = emulator_check_pmc,
4859 .read_pmc = emulator_read_pmc,
4860 .halt = emulator_halt,
4861 .wbinvd = emulator_wbinvd,
4862 .fix_hypercall = emulator_fix_hypercall,
4863 .get_fpu = emulator_get_fpu,
4864 .put_fpu = emulator_put_fpu,
4865 .intercept = emulator_intercept,
4866 .get_cpuid = emulator_get_cpuid,
4867 .set_nmi_mask = emulator_set_nmi_mask,
4868 };
4869
4870 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4871 {
4872 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4873 /*
4874 * an sti; sti; sequence only disable interrupts for the first
4875 * instruction. So, if the last instruction, be it emulated or
4876 * not, left the system with the INT_STI flag enabled, it
4877 * means that the last instruction is an sti. We should not
4878 * leave the flag on in this case. The same goes for mov ss
4879 */
4880 if (int_shadow & mask)
4881 mask = 0;
4882 if (unlikely(int_shadow || mask)) {
4883 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4884 if (!mask)
4885 kvm_make_request(KVM_REQ_EVENT, vcpu);
4886 }
4887 }
4888
4889 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4890 {
4891 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4892 if (ctxt->exception.vector == PF_VECTOR)
4893 return kvm_propagate_fault(vcpu, &ctxt->exception);
4894
4895 if (ctxt->exception.error_code_valid)
4896 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4897 ctxt->exception.error_code);
4898 else
4899 kvm_queue_exception(vcpu, ctxt->exception.vector);
4900 return false;
4901 }
4902
4903 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4904 {
4905 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4906 int cs_db, cs_l;
4907
4908 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4909
4910 ctxt->eflags = kvm_get_rflags(vcpu);
4911 ctxt->eip = kvm_rip_read(vcpu);
4912 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4913 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4914 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4915 cs_db ? X86EMUL_MODE_PROT32 :
4916 X86EMUL_MODE_PROT16;
4917 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4918 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4919 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4920 ctxt->emul_flags = vcpu->arch.hflags;
4921
4922 init_decode_cache(ctxt);
4923 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4924 }
4925
4926 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4927 {
4928 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4929 int ret;
4930
4931 init_emulate_ctxt(vcpu);
4932
4933 ctxt->op_bytes = 2;
4934 ctxt->ad_bytes = 2;
4935 ctxt->_eip = ctxt->eip + inc_eip;
4936 ret = emulate_int_real(ctxt, irq);
4937
4938 if (ret != X86EMUL_CONTINUE)
4939 return EMULATE_FAIL;
4940
4941 ctxt->eip = ctxt->_eip;
4942 kvm_rip_write(vcpu, ctxt->eip);
4943 kvm_set_rflags(vcpu, ctxt->eflags);
4944
4945 if (irq == NMI_VECTOR)
4946 vcpu->arch.nmi_pending = 0;
4947 else
4948 vcpu->arch.interrupt.pending = false;
4949
4950 return EMULATE_DONE;
4951 }
4952 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4953
4954 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4955 {
4956 int r = EMULATE_DONE;
4957
4958 ++vcpu->stat.insn_emulation_fail;
4959 trace_kvm_emulate_insn_failed(vcpu);
4960 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4961 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4962 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4963 vcpu->run->internal.ndata = 0;
4964 r = EMULATE_FAIL;
4965 }
4966 kvm_queue_exception(vcpu, UD_VECTOR);
4967
4968 return r;
4969 }
4970
4971 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4972 bool write_fault_to_shadow_pgtable,
4973 int emulation_type)
4974 {
4975 gpa_t gpa = cr2;
4976 pfn_t pfn;
4977
4978 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4979 return false;
4980
4981 if (!vcpu->arch.mmu.direct_map) {
4982 /*
4983 * Write permission should be allowed since only
4984 * write access need to be emulated.
4985 */
4986 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4987
4988 /*
4989 * If the mapping is invalid in guest, let cpu retry
4990 * it to generate fault.
4991 */
4992 if (gpa == UNMAPPED_GVA)
4993 return true;
4994 }
4995
4996 /*
4997 * Do not retry the unhandleable instruction if it faults on the
4998 * readonly host memory, otherwise it will goto a infinite loop:
4999 * retry instruction -> write #PF -> emulation fail -> retry
5000 * instruction -> ...
5001 */
5002 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5003
5004 /*
5005 * If the instruction failed on the error pfn, it can not be fixed,
5006 * report the error to userspace.
5007 */
5008 if (is_error_noslot_pfn(pfn))
5009 return false;
5010
5011 kvm_release_pfn_clean(pfn);
5012
5013 /* The instructions are well-emulated on direct mmu. */
5014 if (vcpu->arch.mmu.direct_map) {
5015 unsigned int indirect_shadow_pages;
5016
5017 spin_lock(&vcpu->kvm->mmu_lock);
5018 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5019 spin_unlock(&vcpu->kvm->mmu_lock);
5020
5021 if (indirect_shadow_pages)
5022 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5023
5024 return true;
5025 }
5026
5027 /*
5028 * if emulation was due to access to shadowed page table
5029 * and it failed try to unshadow page and re-enter the
5030 * guest to let CPU execute the instruction.
5031 */
5032 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5033
5034 /*
5035 * If the access faults on its page table, it can not
5036 * be fixed by unprotecting shadow page and it should
5037 * be reported to userspace.
5038 */
5039 return !write_fault_to_shadow_pgtable;
5040 }
5041
5042 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5043 unsigned long cr2, int emulation_type)
5044 {
5045 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5046 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5047
5048 last_retry_eip = vcpu->arch.last_retry_eip;
5049 last_retry_addr = vcpu->arch.last_retry_addr;
5050
5051 /*
5052 * If the emulation is caused by #PF and it is non-page_table
5053 * writing instruction, it means the VM-EXIT is caused by shadow
5054 * page protected, we can zap the shadow page and retry this
5055 * instruction directly.
5056 *
5057 * Note: if the guest uses a non-page-table modifying instruction
5058 * on the PDE that points to the instruction, then we will unmap
5059 * the instruction and go to an infinite loop. So, we cache the
5060 * last retried eip and the last fault address, if we meet the eip
5061 * and the address again, we can break out of the potential infinite
5062 * loop.
5063 */
5064 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5065
5066 if (!(emulation_type & EMULTYPE_RETRY))
5067 return false;
5068
5069 if (x86_page_table_writing_insn(ctxt))
5070 return false;
5071
5072 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5073 return false;
5074
5075 vcpu->arch.last_retry_eip = ctxt->eip;
5076 vcpu->arch.last_retry_addr = cr2;
5077
5078 if (!vcpu->arch.mmu.direct_map)
5079 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5080
5081 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5082
5083 return true;
5084 }
5085
5086 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5087 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5088
5089 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5090 {
5091 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5092 /* This is a good place to trace that we are exiting SMM. */
5093 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5094
5095 if (unlikely(vcpu->arch.smi_pending)) {
5096 kvm_make_request(KVM_REQ_SMI, vcpu);
5097 vcpu->arch.smi_pending = 0;
5098 } else {
5099 /* Process a latched INIT, if any. */
5100 kvm_make_request(KVM_REQ_EVENT, vcpu);
5101 }
5102 }
5103
5104 kvm_mmu_reset_context(vcpu);
5105 }
5106
5107 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5108 {
5109 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5110
5111 vcpu->arch.hflags = emul_flags;
5112
5113 if (changed & HF_SMM_MASK)
5114 kvm_smm_changed(vcpu);
5115 }
5116
5117 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5118 unsigned long *db)
5119 {
5120 u32 dr6 = 0;
5121 int i;
5122 u32 enable, rwlen;
5123
5124 enable = dr7;
5125 rwlen = dr7 >> 16;
5126 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5127 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5128 dr6 |= (1 << i);
5129 return dr6;
5130 }
5131
5132 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5133 {
5134 struct kvm_run *kvm_run = vcpu->run;
5135
5136 /*
5137 * rflags is the old, "raw" value of the flags. The new value has
5138 * not been saved yet.
5139 *
5140 * This is correct even for TF set by the guest, because "the
5141 * processor will not generate this exception after the instruction
5142 * that sets the TF flag".
5143 */
5144 if (unlikely(rflags & X86_EFLAGS_TF)) {
5145 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5146 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5147 DR6_RTM;
5148 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5149 kvm_run->debug.arch.exception = DB_VECTOR;
5150 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5151 *r = EMULATE_USER_EXIT;
5152 } else {
5153 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5154 /*
5155 * "Certain debug exceptions may clear bit 0-3. The
5156 * remaining contents of the DR6 register are never
5157 * cleared by the processor".
5158 */
5159 vcpu->arch.dr6 &= ~15;
5160 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5161 kvm_queue_exception(vcpu, DB_VECTOR);
5162 }
5163 }
5164 }
5165
5166 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5167 {
5168 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5169 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5170 struct kvm_run *kvm_run = vcpu->run;
5171 unsigned long eip = kvm_get_linear_rip(vcpu);
5172 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5173 vcpu->arch.guest_debug_dr7,
5174 vcpu->arch.eff_db);
5175
5176 if (dr6 != 0) {
5177 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5178 kvm_run->debug.arch.pc = eip;
5179 kvm_run->debug.arch.exception = DB_VECTOR;
5180 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5181 *r = EMULATE_USER_EXIT;
5182 return true;
5183 }
5184 }
5185
5186 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5187 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5188 unsigned long eip = kvm_get_linear_rip(vcpu);
5189 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5190 vcpu->arch.dr7,
5191 vcpu->arch.db);
5192
5193 if (dr6 != 0) {
5194 vcpu->arch.dr6 &= ~15;
5195 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5196 kvm_queue_exception(vcpu, DB_VECTOR);
5197 *r = EMULATE_DONE;
5198 return true;
5199 }
5200 }
5201
5202 return false;
5203 }
5204
5205 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5206 unsigned long cr2,
5207 int emulation_type,
5208 void *insn,
5209 int insn_len)
5210 {
5211 int r;
5212 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5213 bool writeback = true;
5214 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5215
5216 /*
5217 * Clear write_fault_to_shadow_pgtable here to ensure it is
5218 * never reused.
5219 */
5220 vcpu->arch.write_fault_to_shadow_pgtable = false;
5221 kvm_clear_exception_queue(vcpu);
5222
5223 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5224 init_emulate_ctxt(vcpu);
5225
5226 /*
5227 * We will reenter on the same instruction since
5228 * we do not set complete_userspace_io. This does not
5229 * handle watchpoints yet, those would be handled in
5230 * the emulate_ops.
5231 */
5232 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5233 return r;
5234
5235 ctxt->interruptibility = 0;
5236 ctxt->have_exception = false;
5237 ctxt->exception.vector = -1;
5238 ctxt->perm_ok = false;
5239
5240 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5241
5242 r = x86_decode_insn(ctxt, insn, insn_len);
5243
5244 trace_kvm_emulate_insn_start(vcpu);
5245 ++vcpu->stat.insn_emulation;
5246 if (r != EMULATION_OK) {
5247 if (emulation_type & EMULTYPE_TRAP_UD)
5248 return EMULATE_FAIL;
5249 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5250 emulation_type))
5251 return EMULATE_DONE;
5252 if (emulation_type & EMULTYPE_SKIP)
5253 return EMULATE_FAIL;
5254 return handle_emulation_failure(vcpu);
5255 }
5256 }
5257
5258 if (emulation_type & EMULTYPE_SKIP) {
5259 kvm_rip_write(vcpu, ctxt->_eip);
5260 if (ctxt->eflags & X86_EFLAGS_RF)
5261 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5262 return EMULATE_DONE;
5263 }
5264
5265 if (retry_instruction(ctxt, cr2, emulation_type))
5266 return EMULATE_DONE;
5267
5268 /* this is needed for vmware backdoor interface to work since it
5269 changes registers values during IO operation */
5270 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5271 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5272 emulator_invalidate_register_cache(ctxt);
5273 }
5274
5275 restart:
5276 r = x86_emulate_insn(ctxt);
5277
5278 if (r == EMULATION_INTERCEPTED)
5279 return EMULATE_DONE;
5280
5281 if (r == EMULATION_FAILED) {
5282 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5283 emulation_type))
5284 return EMULATE_DONE;
5285
5286 return handle_emulation_failure(vcpu);
5287 }
5288
5289 if (ctxt->have_exception) {
5290 r = EMULATE_DONE;
5291 if (inject_emulated_exception(vcpu))
5292 return r;
5293 } else if (vcpu->arch.pio.count) {
5294 if (!vcpu->arch.pio.in) {
5295 /* FIXME: return into emulator if single-stepping. */
5296 vcpu->arch.pio.count = 0;
5297 } else {
5298 writeback = false;
5299 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5300 }
5301 r = EMULATE_USER_EXIT;
5302 } else if (vcpu->mmio_needed) {
5303 if (!vcpu->mmio_is_write)
5304 writeback = false;
5305 r = EMULATE_USER_EXIT;
5306 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5307 } else if (r == EMULATION_RESTART)
5308 goto restart;
5309 else
5310 r = EMULATE_DONE;
5311
5312 if (writeback) {
5313 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5314 toggle_interruptibility(vcpu, ctxt->interruptibility);
5315 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5316 if (vcpu->arch.hflags != ctxt->emul_flags)
5317 kvm_set_hflags(vcpu, ctxt->emul_flags);
5318 kvm_rip_write(vcpu, ctxt->eip);
5319 if (r == EMULATE_DONE)
5320 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5321 if (!ctxt->have_exception ||
5322 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5323 __kvm_set_rflags(vcpu, ctxt->eflags);
5324
5325 /*
5326 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5327 * do nothing, and it will be requested again as soon as
5328 * the shadow expires. But we still need to check here,
5329 * because POPF has no interrupt shadow.
5330 */
5331 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5332 kvm_make_request(KVM_REQ_EVENT, vcpu);
5333 } else
5334 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5335
5336 return r;
5337 }
5338 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5339
5340 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5341 {
5342 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5343 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5344 size, port, &val, 1);
5345 /* do not return to emulator after return from userspace */
5346 vcpu->arch.pio.count = 0;
5347 return ret;
5348 }
5349 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5350
5351 static void tsc_bad(void *info)
5352 {
5353 __this_cpu_write(cpu_tsc_khz, 0);
5354 }
5355
5356 static void tsc_khz_changed(void *data)
5357 {
5358 struct cpufreq_freqs *freq = data;
5359 unsigned long khz = 0;
5360
5361 if (data)
5362 khz = freq->new;
5363 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5364 khz = cpufreq_quick_get(raw_smp_processor_id());
5365 if (!khz)
5366 khz = tsc_khz;
5367 __this_cpu_write(cpu_tsc_khz, khz);
5368 }
5369
5370 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5371 void *data)
5372 {
5373 struct cpufreq_freqs *freq = data;
5374 struct kvm *kvm;
5375 struct kvm_vcpu *vcpu;
5376 int i, send_ipi = 0;
5377
5378 /*
5379 * We allow guests to temporarily run on slowing clocks,
5380 * provided we notify them after, or to run on accelerating
5381 * clocks, provided we notify them before. Thus time never
5382 * goes backwards.
5383 *
5384 * However, we have a problem. We can't atomically update
5385 * the frequency of a given CPU from this function; it is
5386 * merely a notifier, which can be called from any CPU.
5387 * Changing the TSC frequency at arbitrary points in time
5388 * requires a recomputation of local variables related to
5389 * the TSC for each VCPU. We must flag these local variables
5390 * to be updated and be sure the update takes place with the
5391 * new frequency before any guests proceed.
5392 *
5393 * Unfortunately, the combination of hotplug CPU and frequency
5394 * change creates an intractable locking scenario; the order
5395 * of when these callouts happen is undefined with respect to
5396 * CPU hotplug, and they can race with each other. As such,
5397 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5398 * undefined; you can actually have a CPU frequency change take
5399 * place in between the computation of X and the setting of the
5400 * variable. To protect against this problem, all updates of
5401 * the per_cpu tsc_khz variable are done in an interrupt
5402 * protected IPI, and all callers wishing to update the value
5403 * must wait for a synchronous IPI to complete (which is trivial
5404 * if the caller is on the CPU already). This establishes the
5405 * necessary total order on variable updates.
5406 *
5407 * Note that because a guest time update may take place
5408 * anytime after the setting of the VCPU's request bit, the
5409 * correct TSC value must be set before the request. However,
5410 * to ensure the update actually makes it to any guest which
5411 * starts running in hardware virtualization between the set
5412 * and the acquisition of the spinlock, we must also ping the
5413 * CPU after setting the request bit.
5414 *
5415 */
5416
5417 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5418 return 0;
5419 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5420 return 0;
5421
5422 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5423
5424 spin_lock(&kvm_lock);
5425 list_for_each_entry(kvm, &vm_list, vm_list) {
5426 kvm_for_each_vcpu(i, vcpu, kvm) {
5427 if (vcpu->cpu != freq->cpu)
5428 continue;
5429 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5430 if (vcpu->cpu != smp_processor_id())
5431 send_ipi = 1;
5432 }
5433 }
5434 spin_unlock(&kvm_lock);
5435
5436 if (freq->old < freq->new && send_ipi) {
5437 /*
5438 * We upscale the frequency. Must make the guest
5439 * doesn't see old kvmclock values while running with
5440 * the new frequency, otherwise we risk the guest sees
5441 * time go backwards.
5442 *
5443 * In case we update the frequency for another cpu
5444 * (which might be in guest context) send an interrupt
5445 * to kick the cpu out of guest context. Next time
5446 * guest context is entered kvmclock will be updated,
5447 * so the guest will not see stale values.
5448 */
5449 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5450 }
5451 return 0;
5452 }
5453
5454 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5455 .notifier_call = kvmclock_cpufreq_notifier
5456 };
5457
5458 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5459 unsigned long action, void *hcpu)
5460 {
5461 unsigned int cpu = (unsigned long)hcpu;
5462
5463 switch (action) {
5464 case CPU_ONLINE:
5465 case CPU_DOWN_FAILED:
5466 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5467 break;
5468 case CPU_DOWN_PREPARE:
5469 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5470 break;
5471 }
5472 return NOTIFY_OK;
5473 }
5474
5475 static struct notifier_block kvmclock_cpu_notifier_block = {
5476 .notifier_call = kvmclock_cpu_notifier,
5477 .priority = -INT_MAX
5478 };
5479
5480 static void kvm_timer_init(void)
5481 {
5482 int cpu;
5483
5484 max_tsc_khz = tsc_khz;
5485
5486 cpu_notifier_register_begin();
5487 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5488 #ifdef CONFIG_CPU_FREQ
5489 struct cpufreq_policy policy;
5490 memset(&policy, 0, sizeof(policy));
5491 cpu = get_cpu();
5492 cpufreq_get_policy(&policy, cpu);
5493 if (policy.cpuinfo.max_freq)
5494 max_tsc_khz = policy.cpuinfo.max_freq;
5495 put_cpu();
5496 #endif
5497 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5498 CPUFREQ_TRANSITION_NOTIFIER);
5499 }
5500 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5501 for_each_online_cpu(cpu)
5502 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5503
5504 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5505 cpu_notifier_register_done();
5506
5507 }
5508
5509 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5510
5511 int kvm_is_in_guest(void)
5512 {
5513 return __this_cpu_read(current_vcpu) != NULL;
5514 }
5515
5516 static int kvm_is_user_mode(void)
5517 {
5518 int user_mode = 3;
5519
5520 if (__this_cpu_read(current_vcpu))
5521 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5522
5523 return user_mode != 0;
5524 }
5525
5526 static unsigned long kvm_get_guest_ip(void)
5527 {
5528 unsigned long ip = 0;
5529
5530 if (__this_cpu_read(current_vcpu))
5531 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5532
5533 return ip;
5534 }
5535
5536 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5537 .is_in_guest = kvm_is_in_guest,
5538 .is_user_mode = kvm_is_user_mode,
5539 .get_guest_ip = kvm_get_guest_ip,
5540 };
5541
5542 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5543 {
5544 __this_cpu_write(current_vcpu, vcpu);
5545 }
5546 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5547
5548 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5549 {
5550 __this_cpu_write(current_vcpu, NULL);
5551 }
5552 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5553
5554 static void kvm_set_mmio_spte_mask(void)
5555 {
5556 u64 mask;
5557 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5558
5559 /*
5560 * Set the reserved bits and the present bit of an paging-structure
5561 * entry to generate page fault with PFER.RSV = 1.
5562 */
5563 /* Mask the reserved physical address bits. */
5564 mask = rsvd_bits(maxphyaddr, 51);
5565
5566 /* Bit 62 is always reserved for 32bit host. */
5567 mask |= 0x3ull << 62;
5568
5569 /* Set the present bit. */
5570 mask |= 1ull;
5571
5572 #ifdef CONFIG_X86_64
5573 /*
5574 * If reserved bit is not supported, clear the present bit to disable
5575 * mmio page fault.
5576 */
5577 if (maxphyaddr == 52)
5578 mask &= ~1ull;
5579 #endif
5580
5581 kvm_mmu_set_mmio_spte_mask(mask);
5582 }
5583
5584 #ifdef CONFIG_X86_64
5585 static void pvclock_gtod_update_fn(struct work_struct *work)
5586 {
5587 struct kvm *kvm;
5588
5589 struct kvm_vcpu *vcpu;
5590 int i;
5591
5592 spin_lock(&kvm_lock);
5593 list_for_each_entry(kvm, &vm_list, vm_list)
5594 kvm_for_each_vcpu(i, vcpu, kvm)
5595 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5596 atomic_set(&kvm_guest_has_master_clock, 0);
5597 spin_unlock(&kvm_lock);
5598 }
5599
5600 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5601
5602 /*
5603 * Notification about pvclock gtod data update.
5604 */
5605 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5606 void *priv)
5607 {
5608 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5609 struct timekeeper *tk = priv;
5610
5611 update_pvclock_gtod(tk);
5612
5613 /* disable master clock if host does not trust, or does not
5614 * use, TSC clocksource
5615 */
5616 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5617 atomic_read(&kvm_guest_has_master_clock) != 0)
5618 queue_work(system_long_wq, &pvclock_gtod_work);
5619
5620 return 0;
5621 }
5622
5623 static struct notifier_block pvclock_gtod_notifier = {
5624 .notifier_call = pvclock_gtod_notify,
5625 };
5626 #endif
5627
5628 int kvm_arch_init(void *opaque)
5629 {
5630 int r;
5631 struct kvm_x86_ops *ops = opaque;
5632
5633 if (kvm_x86_ops) {
5634 printk(KERN_ERR "kvm: already loaded the other module\n");
5635 r = -EEXIST;
5636 goto out;
5637 }
5638
5639 if (!ops->cpu_has_kvm_support()) {
5640 printk(KERN_ERR "kvm: no hardware support\n");
5641 r = -EOPNOTSUPP;
5642 goto out;
5643 }
5644 if (ops->disabled_by_bios()) {
5645 printk(KERN_ERR "kvm: disabled by bios\n");
5646 r = -EOPNOTSUPP;
5647 goto out;
5648 }
5649
5650 r = -ENOMEM;
5651 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5652 if (!shared_msrs) {
5653 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5654 goto out;
5655 }
5656
5657 r = kvm_mmu_module_init();
5658 if (r)
5659 goto out_free_percpu;
5660
5661 kvm_set_mmio_spte_mask();
5662
5663 kvm_x86_ops = ops;
5664
5665 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5666 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5667
5668 kvm_timer_init();
5669
5670 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5671
5672 if (cpu_has_xsave)
5673 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5674
5675 kvm_lapic_init();
5676 #ifdef CONFIG_X86_64
5677 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5678 #endif
5679
5680 return 0;
5681
5682 out_free_percpu:
5683 free_percpu(shared_msrs);
5684 out:
5685 return r;
5686 }
5687
5688 void kvm_arch_exit(void)
5689 {
5690 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5691
5692 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5693 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5694 CPUFREQ_TRANSITION_NOTIFIER);
5695 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5696 #ifdef CONFIG_X86_64
5697 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5698 #endif
5699 kvm_x86_ops = NULL;
5700 kvm_mmu_module_exit();
5701 free_percpu(shared_msrs);
5702 }
5703
5704 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5705 {
5706 ++vcpu->stat.halt_exits;
5707 if (lapic_in_kernel(vcpu)) {
5708 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5709 return 1;
5710 } else {
5711 vcpu->run->exit_reason = KVM_EXIT_HLT;
5712 return 0;
5713 }
5714 }
5715 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5716
5717 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5718 {
5719 kvm_x86_ops->skip_emulated_instruction(vcpu);
5720 return kvm_vcpu_halt(vcpu);
5721 }
5722 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5723
5724 /*
5725 * kvm_pv_kick_cpu_op: Kick a vcpu.
5726 *
5727 * @apicid - apicid of vcpu to be kicked.
5728 */
5729 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5730 {
5731 struct kvm_lapic_irq lapic_irq;
5732
5733 lapic_irq.shorthand = 0;
5734 lapic_irq.dest_mode = 0;
5735 lapic_irq.dest_id = apicid;
5736 lapic_irq.msi_redir_hint = false;
5737
5738 lapic_irq.delivery_mode = APIC_DM_REMRD;
5739 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5740 }
5741
5742 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5743 {
5744 unsigned long nr, a0, a1, a2, a3, ret;
5745 int op_64_bit, r = 1;
5746
5747 kvm_x86_ops->skip_emulated_instruction(vcpu);
5748
5749 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5750 return kvm_hv_hypercall(vcpu);
5751
5752 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5753 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5754 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5755 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5756 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5757
5758 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5759
5760 op_64_bit = is_64_bit_mode(vcpu);
5761 if (!op_64_bit) {
5762 nr &= 0xFFFFFFFF;
5763 a0 &= 0xFFFFFFFF;
5764 a1 &= 0xFFFFFFFF;
5765 a2 &= 0xFFFFFFFF;
5766 a3 &= 0xFFFFFFFF;
5767 }
5768
5769 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5770 ret = -KVM_EPERM;
5771 goto out;
5772 }
5773
5774 switch (nr) {
5775 case KVM_HC_VAPIC_POLL_IRQ:
5776 ret = 0;
5777 break;
5778 case KVM_HC_KICK_CPU:
5779 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5780 ret = 0;
5781 break;
5782 default:
5783 ret = -KVM_ENOSYS;
5784 break;
5785 }
5786 out:
5787 if (!op_64_bit)
5788 ret = (u32)ret;
5789 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5790 ++vcpu->stat.hypercalls;
5791 return r;
5792 }
5793 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5794
5795 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5796 {
5797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5798 char instruction[3];
5799 unsigned long rip = kvm_rip_read(vcpu);
5800
5801 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5802
5803 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5804 }
5805
5806 /*
5807 * Check if userspace requested an interrupt window, and that the
5808 * interrupt window is open.
5809 *
5810 * No need to exit to userspace if we already have an interrupt queued.
5811 */
5812 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5813 {
5814 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5815 return false;
5816
5817 if (kvm_cpu_has_interrupt(vcpu))
5818 return false;
5819
5820 return (irqchip_split(vcpu->kvm)
5821 ? kvm_apic_accept_pic_intr(vcpu)
5822 : kvm_arch_interrupt_allowed(vcpu));
5823 }
5824
5825 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5826 {
5827 struct kvm_run *kvm_run = vcpu->run;
5828
5829 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5830 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5831 kvm_run->cr8 = kvm_get_cr8(vcpu);
5832 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5833 if (!irqchip_in_kernel(vcpu->kvm))
5834 kvm_run->ready_for_interrupt_injection =
5835 kvm_arch_interrupt_allowed(vcpu) &&
5836 !kvm_cpu_has_interrupt(vcpu) &&
5837 !kvm_event_needs_reinjection(vcpu);
5838 else if (!pic_in_kernel(vcpu->kvm))
5839 kvm_run->ready_for_interrupt_injection =
5840 kvm_apic_accept_pic_intr(vcpu) &&
5841 !kvm_cpu_has_interrupt(vcpu);
5842 else
5843 kvm_run->ready_for_interrupt_injection = 1;
5844 }
5845
5846 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5847 {
5848 int max_irr, tpr;
5849
5850 if (!kvm_x86_ops->update_cr8_intercept)
5851 return;
5852
5853 if (!vcpu->arch.apic)
5854 return;
5855
5856 if (!vcpu->arch.apic->vapic_addr)
5857 max_irr = kvm_lapic_find_highest_irr(vcpu);
5858 else
5859 max_irr = -1;
5860
5861 if (max_irr != -1)
5862 max_irr >>= 4;
5863
5864 tpr = kvm_lapic_get_cr8(vcpu);
5865
5866 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5867 }
5868
5869 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5870 {
5871 int r;
5872
5873 /* try to reinject previous events if any */
5874 if (vcpu->arch.exception.pending) {
5875 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5876 vcpu->arch.exception.has_error_code,
5877 vcpu->arch.exception.error_code);
5878
5879 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5880 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5881 X86_EFLAGS_RF);
5882
5883 if (vcpu->arch.exception.nr == DB_VECTOR &&
5884 (vcpu->arch.dr7 & DR7_GD)) {
5885 vcpu->arch.dr7 &= ~DR7_GD;
5886 kvm_update_dr7(vcpu);
5887 }
5888
5889 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5890 vcpu->arch.exception.has_error_code,
5891 vcpu->arch.exception.error_code,
5892 vcpu->arch.exception.reinject);
5893 return 0;
5894 }
5895
5896 if (vcpu->arch.nmi_injected) {
5897 kvm_x86_ops->set_nmi(vcpu);
5898 return 0;
5899 }
5900
5901 if (vcpu->arch.interrupt.pending) {
5902 kvm_x86_ops->set_irq(vcpu);
5903 return 0;
5904 }
5905
5906 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5907 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5908 if (r != 0)
5909 return r;
5910 }
5911
5912 /* try to inject new event if pending */
5913 if (vcpu->arch.nmi_pending) {
5914 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5915 --vcpu->arch.nmi_pending;
5916 vcpu->arch.nmi_injected = true;
5917 kvm_x86_ops->set_nmi(vcpu);
5918 }
5919 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5920 /*
5921 * Because interrupts can be injected asynchronously, we are
5922 * calling check_nested_events again here to avoid a race condition.
5923 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5924 * proposal and current concerns. Perhaps we should be setting
5925 * KVM_REQ_EVENT only on certain events and not unconditionally?
5926 */
5927 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5928 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5929 if (r != 0)
5930 return r;
5931 }
5932 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5933 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5934 false);
5935 kvm_x86_ops->set_irq(vcpu);
5936 }
5937 }
5938 return 0;
5939 }
5940
5941 static void process_nmi(struct kvm_vcpu *vcpu)
5942 {
5943 unsigned limit = 2;
5944
5945 /*
5946 * x86 is limited to one NMI running, and one NMI pending after it.
5947 * If an NMI is already in progress, limit further NMIs to just one.
5948 * Otherwise, allow two (and we'll inject the first one immediately).
5949 */
5950 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5951 limit = 1;
5952
5953 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5954 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5955 kvm_make_request(KVM_REQ_EVENT, vcpu);
5956 }
5957
5958 #define put_smstate(type, buf, offset, val) \
5959 *(type *)((buf) + (offset) - 0x7e00) = val
5960
5961 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5962 {
5963 u32 flags = 0;
5964 flags |= seg->g << 23;
5965 flags |= seg->db << 22;
5966 flags |= seg->l << 21;
5967 flags |= seg->avl << 20;
5968 flags |= seg->present << 15;
5969 flags |= seg->dpl << 13;
5970 flags |= seg->s << 12;
5971 flags |= seg->type << 8;
5972 return flags;
5973 }
5974
5975 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5976 {
5977 struct kvm_segment seg;
5978 int offset;
5979
5980 kvm_get_segment(vcpu, &seg, n);
5981 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5982
5983 if (n < 3)
5984 offset = 0x7f84 + n * 12;
5985 else
5986 offset = 0x7f2c + (n - 3) * 12;
5987
5988 put_smstate(u32, buf, offset + 8, seg.base);
5989 put_smstate(u32, buf, offset + 4, seg.limit);
5990 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5991 }
5992
5993 #ifdef CONFIG_X86_64
5994 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5995 {
5996 struct kvm_segment seg;
5997 int offset;
5998 u16 flags;
5999
6000 kvm_get_segment(vcpu, &seg, n);
6001 offset = 0x7e00 + n * 16;
6002
6003 flags = process_smi_get_segment_flags(&seg) >> 8;
6004 put_smstate(u16, buf, offset, seg.selector);
6005 put_smstate(u16, buf, offset + 2, flags);
6006 put_smstate(u32, buf, offset + 4, seg.limit);
6007 put_smstate(u64, buf, offset + 8, seg.base);
6008 }
6009 #endif
6010
6011 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6012 {
6013 struct desc_ptr dt;
6014 struct kvm_segment seg;
6015 unsigned long val;
6016 int i;
6017
6018 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6019 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6020 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6021 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6022
6023 for (i = 0; i < 8; i++)
6024 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6025
6026 kvm_get_dr(vcpu, 6, &val);
6027 put_smstate(u32, buf, 0x7fcc, (u32)val);
6028 kvm_get_dr(vcpu, 7, &val);
6029 put_smstate(u32, buf, 0x7fc8, (u32)val);
6030
6031 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6032 put_smstate(u32, buf, 0x7fc4, seg.selector);
6033 put_smstate(u32, buf, 0x7f64, seg.base);
6034 put_smstate(u32, buf, 0x7f60, seg.limit);
6035 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6036
6037 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6038 put_smstate(u32, buf, 0x7fc0, seg.selector);
6039 put_smstate(u32, buf, 0x7f80, seg.base);
6040 put_smstate(u32, buf, 0x7f7c, seg.limit);
6041 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6042
6043 kvm_x86_ops->get_gdt(vcpu, &dt);
6044 put_smstate(u32, buf, 0x7f74, dt.address);
6045 put_smstate(u32, buf, 0x7f70, dt.size);
6046
6047 kvm_x86_ops->get_idt(vcpu, &dt);
6048 put_smstate(u32, buf, 0x7f58, dt.address);
6049 put_smstate(u32, buf, 0x7f54, dt.size);
6050
6051 for (i = 0; i < 6; i++)
6052 process_smi_save_seg_32(vcpu, buf, i);
6053
6054 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6055
6056 /* revision id */
6057 put_smstate(u32, buf, 0x7efc, 0x00020000);
6058 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6059 }
6060
6061 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6062 {
6063 #ifdef CONFIG_X86_64
6064 struct desc_ptr dt;
6065 struct kvm_segment seg;
6066 unsigned long val;
6067 int i;
6068
6069 for (i = 0; i < 16; i++)
6070 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6071
6072 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6073 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6074
6075 kvm_get_dr(vcpu, 6, &val);
6076 put_smstate(u64, buf, 0x7f68, val);
6077 kvm_get_dr(vcpu, 7, &val);
6078 put_smstate(u64, buf, 0x7f60, val);
6079
6080 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6081 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6082 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6083
6084 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6085
6086 /* revision id */
6087 put_smstate(u32, buf, 0x7efc, 0x00020064);
6088
6089 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6090
6091 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6092 put_smstate(u16, buf, 0x7e90, seg.selector);
6093 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6094 put_smstate(u32, buf, 0x7e94, seg.limit);
6095 put_smstate(u64, buf, 0x7e98, seg.base);
6096
6097 kvm_x86_ops->get_idt(vcpu, &dt);
6098 put_smstate(u32, buf, 0x7e84, dt.size);
6099 put_smstate(u64, buf, 0x7e88, dt.address);
6100
6101 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6102 put_smstate(u16, buf, 0x7e70, seg.selector);
6103 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6104 put_smstate(u32, buf, 0x7e74, seg.limit);
6105 put_smstate(u64, buf, 0x7e78, seg.base);
6106
6107 kvm_x86_ops->get_gdt(vcpu, &dt);
6108 put_smstate(u32, buf, 0x7e64, dt.size);
6109 put_smstate(u64, buf, 0x7e68, dt.address);
6110
6111 for (i = 0; i < 6; i++)
6112 process_smi_save_seg_64(vcpu, buf, i);
6113 #else
6114 WARN_ON_ONCE(1);
6115 #endif
6116 }
6117
6118 static void process_smi(struct kvm_vcpu *vcpu)
6119 {
6120 struct kvm_segment cs, ds;
6121 struct desc_ptr dt;
6122 char buf[512];
6123 u32 cr0;
6124
6125 if (is_smm(vcpu)) {
6126 vcpu->arch.smi_pending = true;
6127 return;
6128 }
6129
6130 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6131 vcpu->arch.hflags |= HF_SMM_MASK;
6132 memset(buf, 0, 512);
6133 if (guest_cpuid_has_longmode(vcpu))
6134 process_smi_save_state_64(vcpu, buf);
6135 else
6136 process_smi_save_state_32(vcpu, buf);
6137
6138 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6139
6140 if (kvm_x86_ops->get_nmi_mask(vcpu))
6141 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6142 else
6143 kvm_x86_ops->set_nmi_mask(vcpu, true);
6144
6145 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6146 kvm_rip_write(vcpu, 0x8000);
6147
6148 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6149 kvm_x86_ops->set_cr0(vcpu, cr0);
6150 vcpu->arch.cr0 = cr0;
6151
6152 kvm_x86_ops->set_cr4(vcpu, 0);
6153
6154 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6155 dt.address = dt.size = 0;
6156 kvm_x86_ops->set_idt(vcpu, &dt);
6157
6158 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6159
6160 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6161 cs.base = vcpu->arch.smbase;
6162
6163 ds.selector = 0;
6164 ds.base = 0;
6165
6166 cs.limit = ds.limit = 0xffffffff;
6167 cs.type = ds.type = 0x3;
6168 cs.dpl = ds.dpl = 0;
6169 cs.db = ds.db = 0;
6170 cs.s = ds.s = 1;
6171 cs.l = ds.l = 0;
6172 cs.g = ds.g = 1;
6173 cs.avl = ds.avl = 0;
6174 cs.present = ds.present = 1;
6175 cs.unusable = ds.unusable = 0;
6176 cs.padding = ds.padding = 0;
6177
6178 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6182 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6183 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6184
6185 if (guest_cpuid_has_longmode(vcpu))
6186 kvm_x86_ops->set_efer(vcpu, 0);
6187
6188 kvm_update_cpuid(vcpu);
6189 kvm_mmu_reset_context(vcpu);
6190 }
6191
6192 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6193 {
6194 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6195 return;
6196
6197 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
6198
6199 if (irqchip_split(vcpu->kvm))
6200 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6201 else
6202 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
6203 kvm_x86_ops->load_eoi_exitmap(vcpu);
6204 }
6205
6206 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6207 {
6208 ++vcpu->stat.tlb_flush;
6209 kvm_x86_ops->tlb_flush(vcpu);
6210 }
6211
6212 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6213 {
6214 struct page *page = NULL;
6215
6216 if (!lapic_in_kernel(vcpu))
6217 return;
6218
6219 if (!kvm_x86_ops->set_apic_access_page_addr)
6220 return;
6221
6222 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6223 if (is_error_page(page))
6224 return;
6225 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6226
6227 /*
6228 * Do not pin apic access page in memory, the MMU notifier
6229 * will call us again if it is migrated or swapped out.
6230 */
6231 put_page(page);
6232 }
6233 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6234
6235 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6236 unsigned long address)
6237 {
6238 /*
6239 * The physical address of apic access page is stored in the VMCS.
6240 * Update it when it becomes invalid.
6241 */
6242 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6243 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6244 }
6245
6246 /*
6247 * Returns 1 to let vcpu_run() continue the guest execution loop without
6248 * exiting to the userspace. Otherwise, the value will be returned to the
6249 * userspace.
6250 */
6251 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6252 {
6253 int r;
6254 bool req_int_win = !lapic_in_kernel(vcpu) &&
6255 vcpu->run->request_interrupt_window;
6256 bool req_immediate_exit = false;
6257
6258 if (vcpu->requests) {
6259 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6260 kvm_mmu_unload(vcpu);
6261 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6262 __kvm_migrate_timers(vcpu);
6263 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6264 kvm_gen_update_masterclock(vcpu->kvm);
6265 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6266 kvm_gen_kvmclock_update(vcpu);
6267 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6268 r = kvm_guest_time_update(vcpu);
6269 if (unlikely(r))
6270 goto out;
6271 }
6272 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6273 kvm_mmu_sync_roots(vcpu);
6274 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6275 kvm_vcpu_flush_tlb(vcpu);
6276 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6277 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6278 r = 0;
6279 goto out;
6280 }
6281 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6282 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6283 r = 0;
6284 goto out;
6285 }
6286 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6287 vcpu->fpu_active = 0;
6288 kvm_x86_ops->fpu_deactivate(vcpu);
6289 }
6290 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6291 /* Page is swapped out. Do synthetic halt */
6292 vcpu->arch.apf.halted = true;
6293 r = 1;
6294 goto out;
6295 }
6296 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6297 record_steal_time(vcpu);
6298 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6299 process_smi(vcpu);
6300 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6301 process_nmi(vcpu);
6302 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6303 kvm_pmu_handle_event(vcpu);
6304 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6305 kvm_pmu_deliver_pmi(vcpu);
6306 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6307 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6308 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6309 (void *) vcpu->arch.eoi_exit_bitmap)) {
6310 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6311 vcpu->run->eoi.vector =
6312 vcpu->arch.pending_ioapic_eoi;
6313 r = 0;
6314 goto out;
6315 }
6316 }
6317 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6318 vcpu_scan_ioapic(vcpu);
6319 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6320 kvm_vcpu_reload_apic_access_page(vcpu);
6321 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6322 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6323 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6324 r = 0;
6325 goto out;
6326 }
6327 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6328 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6329 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6330 r = 0;
6331 goto out;
6332 }
6333 }
6334
6335 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6336 kvm_apic_accept_events(vcpu);
6337 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6338 r = 1;
6339 goto out;
6340 }
6341
6342 if (inject_pending_event(vcpu, req_int_win) != 0)
6343 req_immediate_exit = true;
6344 /* enable NMI/IRQ window open exits if needed */
6345 else if (vcpu->arch.nmi_pending)
6346 kvm_x86_ops->enable_nmi_window(vcpu);
6347 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6348 kvm_x86_ops->enable_irq_window(vcpu);
6349
6350 if (kvm_lapic_enabled(vcpu)) {
6351 /*
6352 * Update architecture specific hints for APIC
6353 * virtual interrupt delivery.
6354 */
6355 if (kvm_x86_ops->hwapic_irr_update)
6356 kvm_x86_ops->hwapic_irr_update(vcpu,
6357 kvm_lapic_find_highest_irr(vcpu));
6358 update_cr8_intercept(vcpu);
6359 kvm_lapic_sync_to_vapic(vcpu);
6360 }
6361 }
6362
6363 r = kvm_mmu_reload(vcpu);
6364 if (unlikely(r)) {
6365 goto cancel_injection;
6366 }
6367
6368 preempt_disable();
6369
6370 kvm_x86_ops->prepare_guest_switch(vcpu);
6371 if (vcpu->fpu_active)
6372 kvm_load_guest_fpu(vcpu);
6373 kvm_load_guest_xcr0(vcpu);
6374
6375 vcpu->mode = IN_GUEST_MODE;
6376
6377 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6378
6379 /* We should set ->mode before check ->requests,
6380 * see the comment in make_all_cpus_request.
6381 */
6382 smp_mb__after_srcu_read_unlock();
6383
6384 local_irq_disable();
6385
6386 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6387 || need_resched() || signal_pending(current)) {
6388 vcpu->mode = OUTSIDE_GUEST_MODE;
6389 smp_wmb();
6390 local_irq_enable();
6391 preempt_enable();
6392 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6393 r = 1;
6394 goto cancel_injection;
6395 }
6396
6397 if (req_immediate_exit)
6398 smp_send_reschedule(vcpu->cpu);
6399
6400 __kvm_guest_enter();
6401
6402 if (unlikely(vcpu->arch.switch_db_regs)) {
6403 set_debugreg(0, 7);
6404 set_debugreg(vcpu->arch.eff_db[0], 0);
6405 set_debugreg(vcpu->arch.eff_db[1], 1);
6406 set_debugreg(vcpu->arch.eff_db[2], 2);
6407 set_debugreg(vcpu->arch.eff_db[3], 3);
6408 set_debugreg(vcpu->arch.dr6, 6);
6409 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6410 }
6411
6412 trace_kvm_entry(vcpu->vcpu_id);
6413 wait_lapic_expire(vcpu);
6414 kvm_x86_ops->run(vcpu);
6415
6416 /*
6417 * Do this here before restoring debug registers on the host. And
6418 * since we do this before handling the vmexit, a DR access vmexit
6419 * can (a) read the correct value of the debug registers, (b) set
6420 * KVM_DEBUGREG_WONT_EXIT again.
6421 */
6422 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6423 int i;
6424
6425 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6426 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6427 for (i = 0; i < KVM_NR_DB_REGS; i++)
6428 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6429 }
6430
6431 /*
6432 * If the guest has used debug registers, at least dr7
6433 * will be disabled while returning to the host.
6434 * If we don't have active breakpoints in the host, we don't
6435 * care about the messed up debug address registers. But if
6436 * we have some of them active, restore the old state.
6437 */
6438 if (hw_breakpoint_active())
6439 hw_breakpoint_restore();
6440
6441 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6442 rdtsc());
6443
6444 vcpu->mode = OUTSIDE_GUEST_MODE;
6445 smp_wmb();
6446
6447 /* Interrupt is enabled by handle_external_intr() */
6448 kvm_x86_ops->handle_external_intr(vcpu);
6449
6450 ++vcpu->stat.exits;
6451
6452 /*
6453 * We must have an instruction between local_irq_enable() and
6454 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6455 * the interrupt shadow. The stat.exits increment will do nicely.
6456 * But we need to prevent reordering, hence this barrier():
6457 */
6458 barrier();
6459
6460 kvm_guest_exit();
6461
6462 preempt_enable();
6463
6464 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6465
6466 /*
6467 * Profile KVM exit RIPs:
6468 */
6469 if (unlikely(prof_on == KVM_PROFILING)) {
6470 unsigned long rip = kvm_rip_read(vcpu);
6471 profile_hit(KVM_PROFILING, (void *)rip);
6472 }
6473
6474 if (unlikely(vcpu->arch.tsc_always_catchup))
6475 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6476
6477 if (vcpu->arch.apic_attention)
6478 kvm_lapic_sync_from_vapic(vcpu);
6479
6480 r = kvm_x86_ops->handle_exit(vcpu);
6481 return r;
6482
6483 cancel_injection:
6484 kvm_x86_ops->cancel_injection(vcpu);
6485 if (unlikely(vcpu->arch.apic_attention))
6486 kvm_lapic_sync_from_vapic(vcpu);
6487 out:
6488 return r;
6489 }
6490
6491 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6492 {
6493 if (!kvm_arch_vcpu_runnable(vcpu)) {
6494 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6495 kvm_vcpu_block(vcpu);
6496 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6497 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6498 return 1;
6499 }
6500
6501 kvm_apic_accept_events(vcpu);
6502 switch(vcpu->arch.mp_state) {
6503 case KVM_MP_STATE_HALTED:
6504 vcpu->arch.pv.pv_unhalted = false;
6505 vcpu->arch.mp_state =
6506 KVM_MP_STATE_RUNNABLE;
6507 case KVM_MP_STATE_RUNNABLE:
6508 vcpu->arch.apf.halted = false;
6509 break;
6510 case KVM_MP_STATE_INIT_RECEIVED:
6511 break;
6512 default:
6513 return -EINTR;
6514 break;
6515 }
6516 return 1;
6517 }
6518
6519 static int vcpu_run(struct kvm_vcpu *vcpu)
6520 {
6521 int r;
6522 struct kvm *kvm = vcpu->kvm;
6523
6524 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6525
6526 for (;;) {
6527 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6528 !vcpu->arch.apf.halted)
6529 r = vcpu_enter_guest(vcpu);
6530 else
6531 r = vcpu_block(kvm, vcpu);
6532 if (r <= 0)
6533 break;
6534
6535 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6536 if (kvm_cpu_has_pending_timer(vcpu))
6537 kvm_inject_pending_timer_irqs(vcpu);
6538
6539 if (dm_request_for_irq_injection(vcpu)) {
6540 r = 0;
6541 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6542 ++vcpu->stat.request_irq_exits;
6543 break;
6544 }
6545
6546 kvm_check_async_pf_completion(vcpu);
6547
6548 if (signal_pending(current)) {
6549 r = -EINTR;
6550 vcpu->run->exit_reason = KVM_EXIT_INTR;
6551 ++vcpu->stat.signal_exits;
6552 break;
6553 }
6554 if (need_resched()) {
6555 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6556 cond_resched();
6557 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6558 }
6559 }
6560
6561 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6562
6563 return r;
6564 }
6565
6566 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6567 {
6568 int r;
6569 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6570 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6571 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6572 if (r != EMULATE_DONE)
6573 return 0;
6574 return 1;
6575 }
6576
6577 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6578 {
6579 BUG_ON(!vcpu->arch.pio.count);
6580
6581 return complete_emulated_io(vcpu);
6582 }
6583
6584 /*
6585 * Implements the following, as a state machine:
6586 *
6587 * read:
6588 * for each fragment
6589 * for each mmio piece in the fragment
6590 * write gpa, len
6591 * exit
6592 * copy data
6593 * execute insn
6594 *
6595 * write:
6596 * for each fragment
6597 * for each mmio piece in the fragment
6598 * write gpa, len
6599 * copy data
6600 * exit
6601 */
6602 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6603 {
6604 struct kvm_run *run = vcpu->run;
6605 struct kvm_mmio_fragment *frag;
6606 unsigned len;
6607
6608 BUG_ON(!vcpu->mmio_needed);
6609
6610 /* Complete previous fragment */
6611 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6612 len = min(8u, frag->len);
6613 if (!vcpu->mmio_is_write)
6614 memcpy(frag->data, run->mmio.data, len);
6615
6616 if (frag->len <= 8) {
6617 /* Switch to the next fragment. */
6618 frag++;
6619 vcpu->mmio_cur_fragment++;
6620 } else {
6621 /* Go forward to the next mmio piece. */
6622 frag->data += len;
6623 frag->gpa += len;
6624 frag->len -= len;
6625 }
6626
6627 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6628 vcpu->mmio_needed = 0;
6629
6630 /* FIXME: return into emulator if single-stepping. */
6631 if (vcpu->mmio_is_write)
6632 return 1;
6633 vcpu->mmio_read_completed = 1;
6634 return complete_emulated_io(vcpu);
6635 }
6636
6637 run->exit_reason = KVM_EXIT_MMIO;
6638 run->mmio.phys_addr = frag->gpa;
6639 if (vcpu->mmio_is_write)
6640 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6641 run->mmio.len = min(8u, frag->len);
6642 run->mmio.is_write = vcpu->mmio_is_write;
6643 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6644 return 0;
6645 }
6646
6647
6648 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6649 {
6650 struct fpu *fpu = &current->thread.fpu;
6651 int r;
6652 sigset_t sigsaved;
6653
6654 fpu__activate_curr(fpu);
6655
6656 if (vcpu->sigset_active)
6657 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6658
6659 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6660 kvm_vcpu_block(vcpu);
6661 kvm_apic_accept_events(vcpu);
6662 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6663 r = -EAGAIN;
6664 goto out;
6665 }
6666
6667 /* re-sync apic's tpr */
6668 if (!lapic_in_kernel(vcpu)) {
6669 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6670 r = -EINVAL;
6671 goto out;
6672 }
6673 }
6674
6675 if (unlikely(vcpu->arch.complete_userspace_io)) {
6676 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6677 vcpu->arch.complete_userspace_io = NULL;
6678 r = cui(vcpu);
6679 if (r <= 0)
6680 goto out;
6681 } else
6682 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6683
6684 r = vcpu_run(vcpu);
6685
6686 out:
6687 post_kvm_run_save(vcpu);
6688 if (vcpu->sigset_active)
6689 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6690
6691 return r;
6692 }
6693
6694 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6695 {
6696 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6697 /*
6698 * We are here if userspace calls get_regs() in the middle of
6699 * instruction emulation. Registers state needs to be copied
6700 * back from emulation context to vcpu. Userspace shouldn't do
6701 * that usually, but some bad designed PV devices (vmware
6702 * backdoor interface) need this to work
6703 */
6704 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6705 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6706 }
6707 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6708 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6709 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6710 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6711 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6712 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6713 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6714 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6715 #ifdef CONFIG_X86_64
6716 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6717 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6718 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6719 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6720 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6721 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6722 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6723 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6724 #endif
6725
6726 regs->rip = kvm_rip_read(vcpu);
6727 regs->rflags = kvm_get_rflags(vcpu);
6728
6729 return 0;
6730 }
6731
6732 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6733 {
6734 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6735 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6736
6737 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6738 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6739 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6740 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6741 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6742 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6743 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6744 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6745 #ifdef CONFIG_X86_64
6746 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6747 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6748 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6749 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6750 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6751 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6752 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6753 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6754 #endif
6755
6756 kvm_rip_write(vcpu, regs->rip);
6757 kvm_set_rflags(vcpu, regs->rflags);
6758
6759 vcpu->arch.exception.pending = false;
6760
6761 kvm_make_request(KVM_REQ_EVENT, vcpu);
6762
6763 return 0;
6764 }
6765
6766 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6767 {
6768 struct kvm_segment cs;
6769
6770 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6771 *db = cs.db;
6772 *l = cs.l;
6773 }
6774 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6775
6776 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6777 struct kvm_sregs *sregs)
6778 {
6779 struct desc_ptr dt;
6780
6781 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6782 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6783 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6784 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6785 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6786 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6787
6788 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6789 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6790
6791 kvm_x86_ops->get_idt(vcpu, &dt);
6792 sregs->idt.limit = dt.size;
6793 sregs->idt.base = dt.address;
6794 kvm_x86_ops->get_gdt(vcpu, &dt);
6795 sregs->gdt.limit = dt.size;
6796 sregs->gdt.base = dt.address;
6797
6798 sregs->cr0 = kvm_read_cr0(vcpu);
6799 sregs->cr2 = vcpu->arch.cr2;
6800 sregs->cr3 = kvm_read_cr3(vcpu);
6801 sregs->cr4 = kvm_read_cr4(vcpu);
6802 sregs->cr8 = kvm_get_cr8(vcpu);
6803 sregs->efer = vcpu->arch.efer;
6804 sregs->apic_base = kvm_get_apic_base(vcpu);
6805
6806 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6807
6808 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6809 set_bit(vcpu->arch.interrupt.nr,
6810 (unsigned long *)sregs->interrupt_bitmap);
6811
6812 return 0;
6813 }
6814
6815 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6816 struct kvm_mp_state *mp_state)
6817 {
6818 kvm_apic_accept_events(vcpu);
6819 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6820 vcpu->arch.pv.pv_unhalted)
6821 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6822 else
6823 mp_state->mp_state = vcpu->arch.mp_state;
6824
6825 return 0;
6826 }
6827
6828 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6829 struct kvm_mp_state *mp_state)
6830 {
6831 if (!kvm_vcpu_has_lapic(vcpu) &&
6832 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6833 return -EINVAL;
6834
6835 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6836 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6837 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6838 } else
6839 vcpu->arch.mp_state = mp_state->mp_state;
6840 kvm_make_request(KVM_REQ_EVENT, vcpu);
6841 return 0;
6842 }
6843
6844 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6845 int reason, bool has_error_code, u32 error_code)
6846 {
6847 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6848 int ret;
6849
6850 init_emulate_ctxt(vcpu);
6851
6852 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6853 has_error_code, error_code);
6854
6855 if (ret)
6856 return EMULATE_FAIL;
6857
6858 kvm_rip_write(vcpu, ctxt->eip);
6859 kvm_set_rflags(vcpu, ctxt->eflags);
6860 kvm_make_request(KVM_REQ_EVENT, vcpu);
6861 return EMULATE_DONE;
6862 }
6863 EXPORT_SYMBOL_GPL(kvm_task_switch);
6864
6865 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6866 struct kvm_sregs *sregs)
6867 {
6868 struct msr_data apic_base_msr;
6869 int mmu_reset_needed = 0;
6870 int pending_vec, max_bits, idx;
6871 struct desc_ptr dt;
6872
6873 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6874 return -EINVAL;
6875
6876 dt.size = sregs->idt.limit;
6877 dt.address = sregs->idt.base;
6878 kvm_x86_ops->set_idt(vcpu, &dt);
6879 dt.size = sregs->gdt.limit;
6880 dt.address = sregs->gdt.base;
6881 kvm_x86_ops->set_gdt(vcpu, &dt);
6882
6883 vcpu->arch.cr2 = sregs->cr2;
6884 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6885 vcpu->arch.cr3 = sregs->cr3;
6886 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6887
6888 kvm_set_cr8(vcpu, sregs->cr8);
6889
6890 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6891 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6892 apic_base_msr.data = sregs->apic_base;
6893 apic_base_msr.host_initiated = true;
6894 kvm_set_apic_base(vcpu, &apic_base_msr);
6895
6896 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6897 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6898 vcpu->arch.cr0 = sregs->cr0;
6899
6900 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6901 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6902 if (sregs->cr4 & X86_CR4_OSXSAVE)
6903 kvm_update_cpuid(vcpu);
6904
6905 idx = srcu_read_lock(&vcpu->kvm->srcu);
6906 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6907 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6908 mmu_reset_needed = 1;
6909 }
6910 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6911
6912 if (mmu_reset_needed)
6913 kvm_mmu_reset_context(vcpu);
6914
6915 max_bits = KVM_NR_INTERRUPTS;
6916 pending_vec = find_first_bit(
6917 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6918 if (pending_vec < max_bits) {
6919 kvm_queue_interrupt(vcpu, pending_vec, false);
6920 pr_debug("Set back pending irq %d\n", pending_vec);
6921 }
6922
6923 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6924 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6925 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6926 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6927 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6928 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6929
6930 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6931 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6932
6933 update_cr8_intercept(vcpu);
6934
6935 /* Older userspace won't unhalt the vcpu on reset. */
6936 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6937 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6938 !is_protmode(vcpu))
6939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6940
6941 kvm_make_request(KVM_REQ_EVENT, vcpu);
6942
6943 return 0;
6944 }
6945
6946 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6947 struct kvm_guest_debug *dbg)
6948 {
6949 unsigned long rflags;
6950 int i, r;
6951
6952 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6953 r = -EBUSY;
6954 if (vcpu->arch.exception.pending)
6955 goto out;
6956 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6957 kvm_queue_exception(vcpu, DB_VECTOR);
6958 else
6959 kvm_queue_exception(vcpu, BP_VECTOR);
6960 }
6961
6962 /*
6963 * Read rflags as long as potentially injected trace flags are still
6964 * filtered out.
6965 */
6966 rflags = kvm_get_rflags(vcpu);
6967
6968 vcpu->guest_debug = dbg->control;
6969 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6970 vcpu->guest_debug = 0;
6971
6972 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6973 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6974 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6975 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6976 } else {
6977 for (i = 0; i < KVM_NR_DB_REGS; i++)
6978 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6979 }
6980 kvm_update_dr7(vcpu);
6981
6982 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6983 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6984 get_segment_base(vcpu, VCPU_SREG_CS);
6985
6986 /*
6987 * Trigger an rflags update that will inject or remove the trace
6988 * flags.
6989 */
6990 kvm_set_rflags(vcpu, rflags);
6991
6992 kvm_x86_ops->update_db_bp_intercept(vcpu);
6993
6994 r = 0;
6995
6996 out:
6997
6998 return r;
6999 }
7000
7001 /*
7002 * Translate a guest virtual address to a guest physical address.
7003 */
7004 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7005 struct kvm_translation *tr)
7006 {
7007 unsigned long vaddr = tr->linear_address;
7008 gpa_t gpa;
7009 int idx;
7010
7011 idx = srcu_read_lock(&vcpu->kvm->srcu);
7012 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7013 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7014 tr->physical_address = gpa;
7015 tr->valid = gpa != UNMAPPED_GVA;
7016 tr->writeable = 1;
7017 tr->usermode = 0;
7018
7019 return 0;
7020 }
7021
7022 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7023 {
7024 struct fxregs_state *fxsave =
7025 &vcpu->arch.guest_fpu.state.fxsave;
7026
7027 memcpy(fpu->fpr, fxsave->st_space, 128);
7028 fpu->fcw = fxsave->cwd;
7029 fpu->fsw = fxsave->swd;
7030 fpu->ftwx = fxsave->twd;
7031 fpu->last_opcode = fxsave->fop;
7032 fpu->last_ip = fxsave->rip;
7033 fpu->last_dp = fxsave->rdp;
7034 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7035
7036 return 0;
7037 }
7038
7039 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7040 {
7041 struct fxregs_state *fxsave =
7042 &vcpu->arch.guest_fpu.state.fxsave;
7043
7044 memcpy(fxsave->st_space, fpu->fpr, 128);
7045 fxsave->cwd = fpu->fcw;
7046 fxsave->swd = fpu->fsw;
7047 fxsave->twd = fpu->ftwx;
7048 fxsave->fop = fpu->last_opcode;
7049 fxsave->rip = fpu->last_ip;
7050 fxsave->rdp = fpu->last_dp;
7051 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7052
7053 return 0;
7054 }
7055
7056 static void fx_init(struct kvm_vcpu *vcpu)
7057 {
7058 fpstate_init(&vcpu->arch.guest_fpu.state);
7059 if (cpu_has_xsaves)
7060 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7061 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7062
7063 /*
7064 * Ensure guest xcr0 is valid for loading
7065 */
7066 vcpu->arch.xcr0 = XSTATE_FP;
7067
7068 vcpu->arch.cr0 |= X86_CR0_ET;
7069 }
7070
7071 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7072 {
7073 if (vcpu->guest_fpu_loaded)
7074 return;
7075
7076 /*
7077 * Restore all possible states in the guest,
7078 * and assume host would use all available bits.
7079 * Guest xcr0 would be loaded later.
7080 */
7081 kvm_put_guest_xcr0(vcpu);
7082 vcpu->guest_fpu_loaded = 1;
7083 __kernel_fpu_begin();
7084 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7085 trace_kvm_fpu(1);
7086 }
7087
7088 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7089 {
7090 kvm_put_guest_xcr0(vcpu);
7091
7092 if (!vcpu->guest_fpu_loaded) {
7093 vcpu->fpu_counter = 0;
7094 return;
7095 }
7096
7097 vcpu->guest_fpu_loaded = 0;
7098 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7099 __kernel_fpu_end();
7100 ++vcpu->stat.fpu_reload;
7101 /*
7102 * If using eager FPU mode, or if the guest is a frequent user
7103 * of the FPU, just leave the FPU active for next time.
7104 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7105 * the FPU in bursts will revert to loading it on demand.
7106 */
7107 if (!vcpu->arch.eager_fpu) {
7108 if (++vcpu->fpu_counter < 5)
7109 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7110 }
7111 trace_kvm_fpu(0);
7112 }
7113
7114 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7115 {
7116 kvmclock_reset(vcpu);
7117
7118 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7119 kvm_x86_ops->vcpu_free(vcpu);
7120 }
7121
7122 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7123 unsigned int id)
7124 {
7125 struct kvm_vcpu *vcpu;
7126
7127 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7128 printk_once(KERN_WARNING
7129 "kvm: SMP vm created on host with unstable TSC; "
7130 "guest TSC will not be reliable\n");
7131
7132 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7133
7134 return vcpu;
7135 }
7136
7137 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7138 {
7139 int r;
7140
7141 kvm_vcpu_mtrr_init(vcpu);
7142 r = vcpu_load(vcpu);
7143 if (r)
7144 return r;
7145 kvm_vcpu_reset(vcpu, false);
7146 kvm_mmu_setup(vcpu);
7147 vcpu_put(vcpu);
7148 return r;
7149 }
7150
7151 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7152 {
7153 struct msr_data msr;
7154 struct kvm *kvm = vcpu->kvm;
7155
7156 if (vcpu_load(vcpu))
7157 return;
7158 msr.data = 0x0;
7159 msr.index = MSR_IA32_TSC;
7160 msr.host_initiated = true;
7161 kvm_write_tsc(vcpu, &msr);
7162 vcpu_put(vcpu);
7163
7164 if (!kvmclock_periodic_sync)
7165 return;
7166
7167 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7168 KVMCLOCK_SYNC_PERIOD);
7169 }
7170
7171 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7172 {
7173 int r;
7174 vcpu->arch.apf.msr_val = 0;
7175
7176 r = vcpu_load(vcpu);
7177 BUG_ON(r);
7178 kvm_mmu_unload(vcpu);
7179 vcpu_put(vcpu);
7180
7181 kvm_x86_ops->vcpu_free(vcpu);
7182 }
7183
7184 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7185 {
7186 vcpu->arch.hflags = 0;
7187
7188 atomic_set(&vcpu->arch.nmi_queued, 0);
7189 vcpu->arch.nmi_pending = 0;
7190 vcpu->arch.nmi_injected = false;
7191 kvm_clear_interrupt_queue(vcpu);
7192 kvm_clear_exception_queue(vcpu);
7193
7194 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7195 kvm_update_dr0123(vcpu);
7196 vcpu->arch.dr6 = DR6_INIT;
7197 kvm_update_dr6(vcpu);
7198 vcpu->arch.dr7 = DR7_FIXED_1;
7199 kvm_update_dr7(vcpu);
7200
7201 vcpu->arch.cr2 = 0;
7202
7203 kvm_make_request(KVM_REQ_EVENT, vcpu);
7204 vcpu->arch.apf.msr_val = 0;
7205 vcpu->arch.st.msr_val = 0;
7206
7207 kvmclock_reset(vcpu);
7208
7209 kvm_clear_async_pf_completion_queue(vcpu);
7210 kvm_async_pf_hash_reset(vcpu);
7211 vcpu->arch.apf.halted = false;
7212
7213 if (!init_event) {
7214 kvm_pmu_reset(vcpu);
7215 vcpu->arch.smbase = 0x30000;
7216 }
7217
7218 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7219 vcpu->arch.regs_avail = ~0;
7220 vcpu->arch.regs_dirty = ~0;
7221
7222 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7223 }
7224
7225 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7226 {
7227 struct kvm_segment cs;
7228
7229 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7230 cs.selector = vector << 8;
7231 cs.base = vector << 12;
7232 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7233 kvm_rip_write(vcpu, 0);
7234 }
7235
7236 int kvm_arch_hardware_enable(void)
7237 {
7238 struct kvm *kvm;
7239 struct kvm_vcpu *vcpu;
7240 int i;
7241 int ret;
7242 u64 local_tsc;
7243 u64 max_tsc = 0;
7244 bool stable, backwards_tsc = false;
7245
7246 kvm_shared_msr_cpu_online();
7247 ret = kvm_x86_ops->hardware_enable();
7248 if (ret != 0)
7249 return ret;
7250
7251 local_tsc = rdtsc();
7252 stable = !check_tsc_unstable();
7253 list_for_each_entry(kvm, &vm_list, vm_list) {
7254 kvm_for_each_vcpu(i, vcpu, kvm) {
7255 if (!stable && vcpu->cpu == smp_processor_id())
7256 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7257 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7258 backwards_tsc = true;
7259 if (vcpu->arch.last_host_tsc > max_tsc)
7260 max_tsc = vcpu->arch.last_host_tsc;
7261 }
7262 }
7263 }
7264
7265 /*
7266 * Sometimes, even reliable TSCs go backwards. This happens on
7267 * platforms that reset TSC during suspend or hibernate actions, but
7268 * maintain synchronization. We must compensate. Fortunately, we can
7269 * detect that condition here, which happens early in CPU bringup,
7270 * before any KVM threads can be running. Unfortunately, we can't
7271 * bring the TSCs fully up to date with real time, as we aren't yet far
7272 * enough into CPU bringup that we know how much real time has actually
7273 * elapsed; our helper function, get_kernel_ns() will be using boot
7274 * variables that haven't been updated yet.
7275 *
7276 * So we simply find the maximum observed TSC above, then record the
7277 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7278 * the adjustment will be applied. Note that we accumulate
7279 * adjustments, in case multiple suspend cycles happen before some VCPU
7280 * gets a chance to run again. In the event that no KVM threads get a
7281 * chance to run, we will miss the entire elapsed period, as we'll have
7282 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7283 * loose cycle time. This isn't too big a deal, since the loss will be
7284 * uniform across all VCPUs (not to mention the scenario is extremely
7285 * unlikely). It is possible that a second hibernate recovery happens
7286 * much faster than a first, causing the observed TSC here to be
7287 * smaller; this would require additional padding adjustment, which is
7288 * why we set last_host_tsc to the local tsc observed here.
7289 *
7290 * N.B. - this code below runs only on platforms with reliable TSC,
7291 * as that is the only way backwards_tsc is set above. Also note
7292 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7293 * have the same delta_cyc adjustment applied if backwards_tsc
7294 * is detected. Note further, this adjustment is only done once,
7295 * as we reset last_host_tsc on all VCPUs to stop this from being
7296 * called multiple times (one for each physical CPU bringup).
7297 *
7298 * Platforms with unreliable TSCs don't have to deal with this, they
7299 * will be compensated by the logic in vcpu_load, which sets the TSC to
7300 * catchup mode. This will catchup all VCPUs to real time, but cannot
7301 * guarantee that they stay in perfect synchronization.
7302 */
7303 if (backwards_tsc) {
7304 u64 delta_cyc = max_tsc - local_tsc;
7305 backwards_tsc_observed = true;
7306 list_for_each_entry(kvm, &vm_list, vm_list) {
7307 kvm_for_each_vcpu(i, vcpu, kvm) {
7308 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7309 vcpu->arch.last_host_tsc = local_tsc;
7310 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7311 }
7312
7313 /*
7314 * We have to disable TSC offset matching.. if you were
7315 * booting a VM while issuing an S4 host suspend....
7316 * you may have some problem. Solving this issue is
7317 * left as an exercise to the reader.
7318 */
7319 kvm->arch.last_tsc_nsec = 0;
7320 kvm->arch.last_tsc_write = 0;
7321 }
7322
7323 }
7324 return 0;
7325 }
7326
7327 void kvm_arch_hardware_disable(void)
7328 {
7329 kvm_x86_ops->hardware_disable();
7330 drop_user_return_notifiers();
7331 }
7332
7333 int kvm_arch_hardware_setup(void)
7334 {
7335 int r;
7336
7337 r = kvm_x86_ops->hardware_setup();
7338 if (r != 0)
7339 return r;
7340
7341 kvm_init_msr_list();
7342 return 0;
7343 }
7344
7345 void kvm_arch_hardware_unsetup(void)
7346 {
7347 kvm_x86_ops->hardware_unsetup();
7348 }
7349
7350 void kvm_arch_check_processor_compat(void *rtn)
7351 {
7352 kvm_x86_ops->check_processor_compatibility(rtn);
7353 }
7354
7355 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7356 {
7357 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7358 }
7359 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7360
7361 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7362 {
7363 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7364 }
7365
7366 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7367 {
7368 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7369 }
7370
7371 struct static_key kvm_no_apic_vcpu __read_mostly;
7372
7373 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7374 {
7375 struct page *page;
7376 struct kvm *kvm;
7377 int r;
7378
7379 BUG_ON(vcpu->kvm == NULL);
7380 kvm = vcpu->kvm;
7381
7382 vcpu->arch.pv.pv_unhalted = false;
7383 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7384 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7385 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7386 else
7387 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7388
7389 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7390 if (!page) {
7391 r = -ENOMEM;
7392 goto fail;
7393 }
7394 vcpu->arch.pio_data = page_address(page);
7395
7396 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7397
7398 r = kvm_mmu_create(vcpu);
7399 if (r < 0)
7400 goto fail_free_pio_data;
7401
7402 if (irqchip_in_kernel(kvm)) {
7403 r = kvm_create_lapic(vcpu);
7404 if (r < 0)
7405 goto fail_mmu_destroy;
7406 } else
7407 static_key_slow_inc(&kvm_no_apic_vcpu);
7408
7409 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7410 GFP_KERNEL);
7411 if (!vcpu->arch.mce_banks) {
7412 r = -ENOMEM;
7413 goto fail_free_lapic;
7414 }
7415 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7416
7417 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7418 r = -ENOMEM;
7419 goto fail_free_mce_banks;
7420 }
7421
7422 fx_init(vcpu);
7423
7424 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7425 vcpu->arch.pv_time_enabled = false;
7426
7427 vcpu->arch.guest_supported_xcr0 = 0;
7428 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7429
7430 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7431
7432 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7433
7434 kvm_async_pf_hash_reset(vcpu);
7435 kvm_pmu_init(vcpu);
7436
7437 vcpu->arch.pending_external_vector = -1;
7438
7439 return 0;
7440
7441 fail_free_mce_banks:
7442 kfree(vcpu->arch.mce_banks);
7443 fail_free_lapic:
7444 kvm_free_lapic(vcpu);
7445 fail_mmu_destroy:
7446 kvm_mmu_destroy(vcpu);
7447 fail_free_pio_data:
7448 free_page((unsigned long)vcpu->arch.pio_data);
7449 fail:
7450 return r;
7451 }
7452
7453 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7454 {
7455 int idx;
7456
7457 kvm_pmu_destroy(vcpu);
7458 kfree(vcpu->arch.mce_banks);
7459 kvm_free_lapic(vcpu);
7460 idx = srcu_read_lock(&vcpu->kvm->srcu);
7461 kvm_mmu_destroy(vcpu);
7462 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7463 free_page((unsigned long)vcpu->arch.pio_data);
7464 if (!lapic_in_kernel(vcpu))
7465 static_key_slow_dec(&kvm_no_apic_vcpu);
7466 }
7467
7468 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7469 {
7470 kvm_x86_ops->sched_in(vcpu, cpu);
7471 }
7472
7473 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7474 {
7475 if (type)
7476 return -EINVAL;
7477
7478 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7479 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7480 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7481 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7482 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7483
7484 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7485 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7486 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7487 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7488 &kvm->arch.irq_sources_bitmap);
7489
7490 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7491 mutex_init(&kvm->arch.apic_map_lock);
7492 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7493
7494 pvclock_update_vm_gtod_copy(kvm);
7495
7496 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7497 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7498
7499 return 0;
7500 }
7501
7502 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7503 {
7504 int r;
7505 r = vcpu_load(vcpu);
7506 BUG_ON(r);
7507 kvm_mmu_unload(vcpu);
7508 vcpu_put(vcpu);
7509 }
7510
7511 static void kvm_free_vcpus(struct kvm *kvm)
7512 {
7513 unsigned int i;
7514 struct kvm_vcpu *vcpu;
7515
7516 /*
7517 * Unpin any mmu pages first.
7518 */
7519 kvm_for_each_vcpu(i, vcpu, kvm) {
7520 kvm_clear_async_pf_completion_queue(vcpu);
7521 kvm_unload_vcpu_mmu(vcpu);
7522 }
7523 kvm_for_each_vcpu(i, vcpu, kvm)
7524 kvm_arch_vcpu_free(vcpu);
7525
7526 mutex_lock(&kvm->lock);
7527 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7528 kvm->vcpus[i] = NULL;
7529
7530 atomic_set(&kvm->online_vcpus, 0);
7531 mutex_unlock(&kvm->lock);
7532 }
7533
7534 void kvm_arch_sync_events(struct kvm *kvm)
7535 {
7536 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7537 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7538 kvm_free_all_assigned_devices(kvm);
7539 kvm_free_pit(kvm);
7540 }
7541
7542 int __x86_set_memory_region(struct kvm *kvm,
7543 const struct kvm_userspace_memory_region *mem)
7544 {
7545 int i, r;
7546
7547 /* Called with kvm->slots_lock held. */
7548 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7549
7550 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7551 struct kvm_userspace_memory_region m = *mem;
7552
7553 m.slot |= i << 16;
7554 r = __kvm_set_memory_region(kvm, &m);
7555 if (r < 0)
7556 return r;
7557 }
7558
7559 return 0;
7560 }
7561 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7562
7563 int x86_set_memory_region(struct kvm *kvm,
7564 const struct kvm_userspace_memory_region *mem)
7565 {
7566 int r;
7567
7568 mutex_lock(&kvm->slots_lock);
7569 r = __x86_set_memory_region(kvm, mem);
7570 mutex_unlock(&kvm->slots_lock);
7571
7572 return r;
7573 }
7574 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7575
7576 void kvm_arch_destroy_vm(struct kvm *kvm)
7577 {
7578 if (current->mm == kvm->mm) {
7579 /*
7580 * Free memory regions allocated on behalf of userspace,
7581 * unless the the memory map has changed due to process exit
7582 * or fd copying.
7583 */
7584 struct kvm_userspace_memory_region mem;
7585 memset(&mem, 0, sizeof(mem));
7586 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7587 x86_set_memory_region(kvm, &mem);
7588
7589 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7590 x86_set_memory_region(kvm, &mem);
7591
7592 mem.slot = TSS_PRIVATE_MEMSLOT;
7593 x86_set_memory_region(kvm, &mem);
7594 }
7595 kvm_iommu_unmap_guest(kvm);
7596 kfree(kvm->arch.vpic);
7597 kfree(kvm->arch.vioapic);
7598 kvm_free_vcpus(kvm);
7599 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7600 }
7601
7602 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7603 struct kvm_memory_slot *dont)
7604 {
7605 int i;
7606
7607 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7608 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7609 kvfree(free->arch.rmap[i]);
7610 free->arch.rmap[i] = NULL;
7611 }
7612 if (i == 0)
7613 continue;
7614
7615 if (!dont || free->arch.lpage_info[i - 1] !=
7616 dont->arch.lpage_info[i - 1]) {
7617 kvfree(free->arch.lpage_info[i - 1]);
7618 free->arch.lpage_info[i - 1] = NULL;
7619 }
7620 }
7621 }
7622
7623 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7624 unsigned long npages)
7625 {
7626 int i;
7627
7628 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7629 unsigned long ugfn;
7630 int lpages;
7631 int level = i + 1;
7632
7633 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7634 slot->base_gfn, level) + 1;
7635
7636 slot->arch.rmap[i] =
7637 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7638 if (!slot->arch.rmap[i])
7639 goto out_free;
7640 if (i == 0)
7641 continue;
7642
7643 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7644 sizeof(*slot->arch.lpage_info[i - 1]));
7645 if (!slot->arch.lpage_info[i - 1])
7646 goto out_free;
7647
7648 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7649 slot->arch.lpage_info[i - 1][0].write_count = 1;
7650 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7651 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7652 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7653 /*
7654 * If the gfn and userspace address are not aligned wrt each
7655 * other, or if explicitly asked to, disable large page
7656 * support for this slot
7657 */
7658 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7659 !kvm_largepages_enabled()) {
7660 unsigned long j;
7661
7662 for (j = 0; j < lpages; ++j)
7663 slot->arch.lpage_info[i - 1][j].write_count = 1;
7664 }
7665 }
7666
7667 return 0;
7668
7669 out_free:
7670 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7671 kvfree(slot->arch.rmap[i]);
7672 slot->arch.rmap[i] = NULL;
7673 if (i == 0)
7674 continue;
7675
7676 kvfree(slot->arch.lpage_info[i - 1]);
7677 slot->arch.lpage_info[i - 1] = NULL;
7678 }
7679 return -ENOMEM;
7680 }
7681
7682 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7683 {
7684 /*
7685 * memslots->generation has been incremented.
7686 * mmio generation may have reached its maximum value.
7687 */
7688 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7689 }
7690
7691 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7692 struct kvm_memory_slot *memslot,
7693 const struct kvm_userspace_memory_region *mem,
7694 enum kvm_mr_change change)
7695 {
7696 /*
7697 * Only private memory slots need to be mapped here since
7698 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7699 */
7700 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7701 unsigned long userspace_addr;
7702
7703 /*
7704 * MAP_SHARED to prevent internal slot pages from being moved
7705 * by fork()/COW.
7706 */
7707 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7708 PROT_READ | PROT_WRITE,
7709 MAP_SHARED | MAP_ANONYMOUS, 0);
7710
7711 if (IS_ERR((void *)userspace_addr))
7712 return PTR_ERR((void *)userspace_addr);
7713
7714 memslot->userspace_addr = userspace_addr;
7715 }
7716
7717 return 0;
7718 }
7719
7720 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7721 struct kvm_memory_slot *new)
7722 {
7723 /* Still write protect RO slot */
7724 if (new->flags & KVM_MEM_READONLY) {
7725 kvm_mmu_slot_remove_write_access(kvm, new);
7726 return;
7727 }
7728
7729 /*
7730 * Call kvm_x86_ops dirty logging hooks when they are valid.
7731 *
7732 * kvm_x86_ops->slot_disable_log_dirty is called when:
7733 *
7734 * - KVM_MR_CREATE with dirty logging is disabled
7735 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7736 *
7737 * The reason is, in case of PML, we need to set D-bit for any slots
7738 * with dirty logging disabled in order to eliminate unnecessary GPA
7739 * logging in PML buffer (and potential PML buffer full VMEXT). This
7740 * guarantees leaving PML enabled during guest's lifetime won't have
7741 * any additonal overhead from PML when guest is running with dirty
7742 * logging disabled for memory slots.
7743 *
7744 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7745 * to dirty logging mode.
7746 *
7747 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7748 *
7749 * In case of write protect:
7750 *
7751 * Write protect all pages for dirty logging.
7752 *
7753 * All the sptes including the large sptes which point to this
7754 * slot are set to readonly. We can not create any new large
7755 * spte on this slot until the end of the logging.
7756 *
7757 * See the comments in fast_page_fault().
7758 */
7759 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7760 if (kvm_x86_ops->slot_enable_log_dirty)
7761 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7762 else
7763 kvm_mmu_slot_remove_write_access(kvm, new);
7764 } else {
7765 if (kvm_x86_ops->slot_disable_log_dirty)
7766 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7767 }
7768 }
7769
7770 void kvm_arch_commit_memory_region(struct kvm *kvm,
7771 const struct kvm_userspace_memory_region *mem,
7772 const struct kvm_memory_slot *old,
7773 const struct kvm_memory_slot *new,
7774 enum kvm_mr_change change)
7775 {
7776 int nr_mmu_pages = 0;
7777
7778 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7779 int ret;
7780
7781 ret = vm_munmap(old->userspace_addr,
7782 old->npages * PAGE_SIZE);
7783 if (ret < 0)
7784 printk(KERN_WARNING
7785 "kvm_vm_ioctl_set_memory_region: "
7786 "failed to munmap memory\n");
7787 }
7788
7789 if (!kvm->arch.n_requested_mmu_pages)
7790 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7791
7792 if (nr_mmu_pages)
7793 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7794
7795 /*
7796 * Dirty logging tracks sptes in 4k granularity, meaning that large
7797 * sptes have to be split. If live migration is successful, the guest
7798 * in the source machine will be destroyed and large sptes will be
7799 * created in the destination. However, if the guest continues to run
7800 * in the source machine (for example if live migration fails), small
7801 * sptes will remain around and cause bad performance.
7802 *
7803 * Scan sptes if dirty logging has been stopped, dropping those
7804 * which can be collapsed into a single large-page spte. Later
7805 * page faults will create the large-page sptes.
7806 */
7807 if ((change != KVM_MR_DELETE) &&
7808 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7809 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7810 kvm_mmu_zap_collapsible_sptes(kvm, new);
7811
7812 /*
7813 * Set up write protection and/or dirty logging for the new slot.
7814 *
7815 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7816 * been zapped so no dirty logging staff is needed for old slot. For
7817 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7818 * new and it's also covered when dealing with the new slot.
7819 *
7820 * FIXME: const-ify all uses of struct kvm_memory_slot.
7821 */
7822 if (change != KVM_MR_DELETE)
7823 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7824 }
7825
7826 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7827 {
7828 kvm_mmu_invalidate_zap_all_pages(kvm);
7829 }
7830
7831 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7832 struct kvm_memory_slot *slot)
7833 {
7834 kvm_mmu_invalidate_zap_all_pages(kvm);
7835 }
7836
7837 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7838 {
7839 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7840 kvm_x86_ops->check_nested_events(vcpu, false);
7841
7842 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7843 !vcpu->arch.apf.halted)
7844 || !list_empty_careful(&vcpu->async_pf.done)
7845 || kvm_apic_has_events(vcpu)
7846 || vcpu->arch.pv.pv_unhalted
7847 || atomic_read(&vcpu->arch.nmi_queued) ||
7848 (kvm_arch_interrupt_allowed(vcpu) &&
7849 kvm_cpu_has_interrupt(vcpu));
7850 }
7851
7852 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7853 {
7854 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7855 }
7856
7857 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7858 {
7859 return kvm_x86_ops->interrupt_allowed(vcpu);
7860 }
7861
7862 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7863 {
7864 if (is_64_bit_mode(vcpu))
7865 return kvm_rip_read(vcpu);
7866 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7867 kvm_rip_read(vcpu));
7868 }
7869 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7870
7871 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7872 {
7873 return kvm_get_linear_rip(vcpu) == linear_rip;
7874 }
7875 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7876
7877 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7878 {
7879 unsigned long rflags;
7880
7881 rflags = kvm_x86_ops->get_rflags(vcpu);
7882 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7883 rflags &= ~X86_EFLAGS_TF;
7884 return rflags;
7885 }
7886 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7887
7888 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7889 {
7890 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7891 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7892 rflags |= X86_EFLAGS_TF;
7893 kvm_x86_ops->set_rflags(vcpu, rflags);
7894 }
7895
7896 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7897 {
7898 __kvm_set_rflags(vcpu, rflags);
7899 kvm_make_request(KVM_REQ_EVENT, vcpu);
7900 }
7901 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7902
7903 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7904 {
7905 int r;
7906
7907 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7908 work->wakeup_all)
7909 return;
7910
7911 r = kvm_mmu_reload(vcpu);
7912 if (unlikely(r))
7913 return;
7914
7915 if (!vcpu->arch.mmu.direct_map &&
7916 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7917 return;
7918
7919 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7920 }
7921
7922 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7923 {
7924 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7925 }
7926
7927 static inline u32 kvm_async_pf_next_probe(u32 key)
7928 {
7929 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7930 }
7931
7932 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7933 {
7934 u32 key = kvm_async_pf_hash_fn(gfn);
7935
7936 while (vcpu->arch.apf.gfns[key] != ~0)
7937 key = kvm_async_pf_next_probe(key);
7938
7939 vcpu->arch.apf.gfns[key] = gfn;
7940 }
7941
7942 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7943 {
7944 int i;
7945 u32 key = kvm_async_pf_hash_fn(gfn);
7946
7947 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7948 (vcpu->arch.apf.gfns[key] != gfn &&
7949 vcpu->arch.apf.gfns[key] != ~0); i++)
7950 key = kvm_async_pf_next_probe(key);
7951
7952 return key;
7953 }
7954
7955 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7956 {
7957 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7958 }
7959
7960 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7961 {
7962 u32 i, j, k;
7963
7964 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7965 while (true) {
7966 vcpu->arch.apf.gfns[i] = ~0;
7967 do {
7968 j = kvm_async_pf_next_probe(j);
7969 if (vcpu->arch.apf.gfns[j] == ~0)
7970 return;
7971 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7972 /*
7973 * k lies cyclically in ]i,j]
7974 * | i.k.j |
7975 * |....j i.k.| or |.k..j i...|
7976 */
7977 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7978 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7979 i = j;
7980 }
7981 }
7982
7983 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7984 {
7985
7986 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7987 sizeof(val));
7988 }
7989
7990 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7991 struct kvm_async_pf *work)
7992 {
7993 struct x86_exception fault;
7994
7995 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7996 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7997
7998 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7999 (vcpu->arch.apf.send_user_only &&
8000 kvm_x86_ops->get_cpl(vcpu) == 0))
8001 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8002 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8003 fault.vector = PF_VECTOR;
8004 fault.error_code_valid = true;
8005 fault.error_code = 0;
8006 fault.nested_page_fault = false;
8007 fault.address = work->arch.token;
8008 kvm_inject_page_fault(vcpu, &fault);
8009 }
8010 }
8011
8012 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8013 struct kvm_async_pf *work)
8014 {
8015 struct x86_exception fault;
8016
8017 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8018 if (work->wakeup_all)
8019 work->arch.token = ~0; /* broadcast wakeup */
8020 else
8021 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8022
8023 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8024 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8025 fault.vector = PF_VECTOR;
8026 fault.error_code_valid = true;
8027 fault.error_code = 0;
8028 fault.nested_page_fault = false;
8029 fault.address = work->arch.token;
8030 kvm_inject_page_fault(vcpu, &fault);
8031 }
8032 vcpu->arch.apf.halted = false;
8033 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8034 }
8035
8036 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8037 {
8038 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8039 return true;
8040 else
8041 return !kvm_event_needs_reinjection(vcpu) &&
8042 kvm_x86_ops->interrupt_allowed(vcpu);
8043 }
8044
8045 void kvm_arch_start_assignment(struct kvm *kvm)
8046 {
8047 atomic_inc(&kvm->arch.assigned_device_count);
8048 }
8049 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8050
8051 void kvm_arch_end_assignment(struct kvm *kvm)
8052 {
8053 atomic_dec(&kvm->arch.assigned_device_count);
8054 }
8055 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8056
8057 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8058 {
8059 return atomic_read(&kvm->arch.assigned_device_count);
8060 }
8061 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8062
8063 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8064 {
8065 atomic_inc(&kvm->arch.noncoherent_dma_count);
8066 }
8067 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8068
8069 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8070 {
8071 atomic_dec(&kvm->arch.noncoherent_dma_count);
8072 }
8073 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8074
8075 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8076 {
8077 return atomic_read(&kvm->arch.noncoherent_dma_count);
8078 }
8079 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8080
8081 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8082 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8083 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8084 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8085 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8086 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8087 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8088 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8089 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8090 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8091 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8092 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8093 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8094 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8095 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8096 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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