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297b36fa3b803002462eeda5b95f2080191c9448
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <trace/events/kvm.h>
55
56 #define CREATE_TRACE_POINTS
57 #include "trace.h"
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 static bool __read_mostly kvmclock_periodic_sync = true;
103 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
105 bool kvm_has_tsc_control;
106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107 u32 kvm_max_guest_tsc_khz;
108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111 static u32 tsc_tolerance_ppm = 250;
112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
115 unsigned int lapic_timer_advance_ns = 0;
116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
118 static bool backwards_tsc_observed = false;
119
120 #define KVM_NR_SHARED_MSRS 16
121
122 struct kvm_shared_msrs_global {
123 int nr;
124 u32 msrs[KVM_NR_SHARED_MSRS];
125 };
126
127 struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
134 };
135
136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
137 static struct kvm_shared_msrs __percpu *shared_msrs;
138
139 struct kvm_stats_debugfs_item debugfs_entries[] = {
140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
150 { "halt_exits", VCPU_STAT(halt_exits) },
151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
154 { "hypercalls", VCPU_STAT(hypercalls) },
155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
162 { "irq_injections", VCPU_STAT(irq_injections) },
163 { "nmi_injections", VCPU_STAT(nmi_injections) },
164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
171 { "mmu_unsync", VM_STAT(mmu_unsync) },
172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
173 { "largepages", VM_STAT(lpages) },
174 { NULL }
175 };
176
177 u64 __read_mostly host_xcr0;
178
179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
180
181 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182 {
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186 }
187
188 static void kvm_on_user_return(struct user_return_notifier *urn)
189 {
190 unsigned slot;
191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
193 struct kvm_shared_msr_values *values;
194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204 }
205
206 static void shared_msr_update(unsigned slot, u32 msr)
207 {
208 u64 value;
209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
211
212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221 }
222
223 void kvm_define_shared_msr(unsigned slot, u32 msr)
224 {
225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
226 shared_msrs_global.msrs[slot] = msr;
227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
229 }
230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232 static void kvm_shared_msr_cpu_online(void)
233 {
234 unsigned i;
235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
237 shared_msr_update(i, shared_msrs_global.msrs[i]);
238 }
239
240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
241 {
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 int err;
245
246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
247 return 0;
248 smsr->values[slot].curr = value;
249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
258 return 0;
259 }
260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
262 static void drop_user_return_notifiers(void)
263 {
264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269 }
270
271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272 {
273 return vcpu->arch.apic_base;
274 }
275 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278 {
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
297 }
298 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
300 asmlinkage __visible void kvm_spurious_fault(void)
301 {
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304 }
305 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
307 #define EXCPT_BENIGN 0
308 #define EXCPT_CONTRIBUTORY 1
309 #define EXCPT_PF 2
310
311 static int exception_class(int vector)
312 {
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326 }
327
328 #define EXCPT_FAULT 0
329 #define EXCPT_TRAP 1
330 #define EXCPT_ABORT 2
331 #define EXCPT_INTERRUPT 3
332
333 static int exception_type(int vector)
334 {
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351 }
352
353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
356 {
357 u32 prev_nr;
358 int class1, class2;
359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
362 if (!vcpu->arch.exception.pending) {
363 queue:
364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
370 vcpu->arch.exception.reinject = reinject;
371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395 }
396
397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398 {
399 kvm_multiple_exception(vcpu, nr, false, 0, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404 {
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
410 {
411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415 }
416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
417
418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
419 {
420 ++vcpu->stat.pf_guest;
421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
423 }
424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
425
426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
430 else
431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
432
433 return fault->nested_page_fault;
434 }
435
436 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437 {
438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
440 }
441 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444 {
445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
446 }
447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450 {
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452 }
453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
455 /*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
460 {
461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
465 }
466 EXPORT_SYMBOL_GPL(kvm_require_cpl);
467
468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469 {
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475 }
476 EXPORT_SYMBOL_GPL(kvm_require_dr);
477
478 /*
479 * This function will be used to read from the physical memory of the currently
480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
481 * can read from guest physical or from the guest's guest physical memory.
482 */
483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486 {
487 struct x86_exception exception;
488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
499 }
500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
503 void *data, int offset, int len, u32 access)
504 {
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507 }
508
509 /*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
513 {
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
519
520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
528 if (is_present_gpte(pdpte[i]) &&
529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
542 out:
543
544 return ret;
545 }
546 EXPORT_SYMBOL_GPL(load_pdptrs);
547
548 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549 {
550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
551 bool changed = true;
552 int offset;
553 gfn_t gfn;
554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
567 if (r < 0)
568 goto out;
569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
570 out:
571
572 return changed;
573 }
574
575 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
576 {
577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
579
580 cr0 |= X86_CR0_ET;
581
582 #ifdef CONFIG_X86_64
583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
585 #endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
588
589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
591
592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596 #ifdef CONFIG_X86_64
597 if ((vcpu->arch.efer & EFER_LME)) {
598 int cs_db, cs_l;
599
600 if (!is_pae(vcpu))
601 return 1;
602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
603 if (cs_l)
604 return 1;
605 } else
606 #endif
607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
608 kvm_read_cr3(vcpu)))
609 return 1;
610 }
611
612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
615 kvm_x86_ops->set_cr0(vcpu, cr0);
616
617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
618 kvm_clear_async_pf_completion_queue(vcpu);
619 kvm_async_pf_hash_reset(vcpu);
620 }
621
622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
628 return 0;
629 }
630 EXPORT_SYMBOL_GPL(kvm_set_cr0);
631
632 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
633 {
634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
635 }
636 EXPORT_SYMBOL_GPL(kvm_lmsw);
637
638 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639 {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646 }
647
648 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655 }
656
657 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
658 {
659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
661 u64 valid_bits;
662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
678 return 1;
679
680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
689 kvm_put_guest_xcr0(vcpu);
690 vcpu->arch.xcr0 = xcr0;
691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
694 return 0;
695 }
696
697 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698 {
699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
708 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
709 {
710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
716
717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
727 return 1;
728
729 if (is_long_mode(vcpu)) {
730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
736 return 1;
737
738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
748 return 1;
749
750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
752 kvm_mmu_reset_context(vcpu);
753
754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
755 kvm_update_cpuid(vcpu);
756
757 return 0;
758 }
759 EXPORT_SYMBOL_GPL(kvm_set_cr4);
760
761 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
762 {
763 #ifdef CONFIG_X86_64
764 cr3 &= ~CR3_PCID_INVD;
765 #endif
766
767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
768 kvm_mmu_sync_roots(vcpu);
769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
770 return 0;
771 }
772
773 if (is_long_mode(vcpu)) {
774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
778 return 1;
779
780 vcpu->arch.cr3 = cr3;
781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
782 kvm_mmu_new_cr3(vcpu);
783 return 0;
784 }
785 EXPORT_SYMBOL_GPL(kvm_set_cr3);
786
787 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
788 {
789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
791 if (lapic_in_kernel(vcpu))
792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
794 vcpu->arch.cr8 = cr8;
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_set_cr8);
798
799 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
800 {
801 if (lapic_in_kernel(vcpu))
802 return kvm_lapic_get_cr8(vcpu);
803 else
804 return vcpu->arch.cr8;
805 }
806 EXPORT_SYMBOL_GPL(kvm_get_cr8);
807
808 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809 {
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817 }
818
819 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820 {
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823 }
824
825 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826 {
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
837 }
838
839 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840 {
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846 }
847
848 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
849 {
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
857 /* fall through */
858 case 6:
859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
862 kvm_update_dr6(vcpu);
863 break;
864 case 5:
865 /* fall through */
866 default: /* 7 */
867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
870 kvm_update_dr7(vcpu);
871 break;
872 }
873
874 return 0;
875 }
876
877 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878 {
879 if (__kvm_set_dr(vcpu, dr, val)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884 }
885 EXPORT_SYMBOL_GPL(kvm_set_dr);
886
887 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
888 {
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
894 /* fall through */
895 case 6:
896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
900 break;
901 case 5:
902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(kvm_get_dr);
910
911 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912 {
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923 }
924 EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
926 /*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
931 * capabilities of the host cpu. This capabilities test skips MSRs that are
932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
934 */
935
936 static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
938 MSR_STAR,
939 #ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 #endif
942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
944 };
945
946 static unsigned num_msrs_to_save;
947
948 static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
955 HV_X64_MSR_RESET,
956 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
957 MSR_KVM_PV_EOI_EN,
958
959 MSR_IA32_TSC_ADJUST,
960 MSR_IA32_TSCDEADLINE,
961 MSR_IA32_MISC_ENABLE,
962 MSR_IA32_MCG_STATUS,
963 MSR_IA32_MCG_CTL,
964 MSR_IA32_SMBASE,
965 };
966
967 static unsigned num_emulated_msrs;
968
969 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
970 {
971 if (efer & efer_reserved_bits)
972 return false;
973
974 if (efer & EFER_FFXSR) {
975 struct kvm_cpuid_entry2 *feat;
976
977 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
978 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
979 return false;
980 }
981
982 if (efer & EFER_SVME) {
983 struct kvm_cpuid_entry2 *feat;
984
985 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
986 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
987 return false;
988 }
989
990 return true;
991 }
992 EXPORT_SYMBOL_GPL(kvm_valid_efer);
993
994 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
995 {
996 u64 old_efer = vcpu->arch.efer;
997
998 if (!kvm_valid_efer(vcpu, efer))
999 return 1;
1000
1001 if (is_paging(vcpu)
1002 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1003 return 1;
1004
1005 efer &= ~EFER_LMA;
1006 efer |= vcpu->arch.efer & EFER_LMA;
1007
1008 kvm_x86_ops->set_efer(vcpu, efer);
1009
1010 /* Update reserved bits */
1011 if ((efer ^ old_efer) & EFER_NX)
1012 kvm_mmu_reset_context(vcpu);
1013
1014 return 0;
1015 }
1016
1017 void kvm_enable_efer_bits(u64 mask)
1018 {
1019 efer_reserved_bits &= ~mask;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1022
1023 /*
1024 * Writes msr value into into the appropriate "register".
1025 * Returns 0 on success, non-0 otherwise.
1026 * Assumes vcpu_load() was already called.
1027 */
1028 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1029 {
1030 switch (msr->index) {
1031 case MSR_FS_BASE:
1032 case MSR_GS_BASE:
1033 case MSR_KERNEL_GS_BASE:
1034 case MSR_CSTAR:
1035 case MSR_LSTAR:
1036 if (is_noncanonical_address(msr->data))
1037 return 1;
1038 break;
1039 case MSR_IA32_SYSENTER_EIP:
1040 case MSR_IA32_SYSENTER_ESP:
1041 /*
1042 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1043 * non-canonical address is written on Intel but not on
1044 * AMD (which ignores the top 32-bits, because it does
1045 * not implement 64-bit SYSENTER).
1046 *
1047 * 64-bit code should hence be able to write a non-canonical
1048 * value on AMD. Making the address canonical ensures that
1049 * vmentry does not fail on Intel after writing a non-canonical
1050 * value, and that something deterministic happens if the guest
1051 * invokes 64-bit SYSENTER.
1052 */
1053 msr->data = get_canonical(msr->data);
1054 }
1055 return kvm_x86_ops->set_msr(vcpu, msr);
1056 }
1057 EXPORT_SYMBOL_GPL(kvm_set_msr);
1058
1059 /*
1060 * Adapt set_msr() to msr_io()'s calling convention
1061 */
1062 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1063 {
1064 struct msr_data msr;
1065 int r;
1066
1067 msr.index = index;
1068 msr.host_initiated = true;
1069 r = kvm_get_msr(vcpu, &msr);
1070 if (r)
1071 return r;
1072
1073 *data = msr.data;
1074 return 0;
1075 }
1076
1077 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078 {
1079 struct msr_data msr;
1080
1081 msr.data = *data;
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 return kvm_set_msr(vcpu, &msr);
1085 }
1086
1087 #ifdef CONFIG_X86_64
1088 struct pvclock_gtod_data {
1089 seqcount_t seq;
1090
1091 struct { /* extract of a clocksource struct */
1092 int vclock_mode;
1093 cycle_t cycle_last;
1094 cycle_t mask;
1095 u32 mult;
1096 u32 shift;
1097 } clock;
1098
1099 u64 boot_ns;
1100 u64 nsec_base;
1101 };
1102
1103 static struct pvclock_gtod_data pvclock_gtod_data;
1104
1105 static void update_pvclock_gtod(struct timekeeper *tk)
1106 {
1107 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1108 u64 boot_ns;
1109
1110 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1111
1112 write_seqcount_begin(&vdata->seq);
1113
1114 /* copy pvclock gtod data */
1115 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1116 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1117 vdata->clock.mask = tk->tkr_mono.mask;
1118 vdata->clock.mult = tk->tkr_mono.mult;
1119 vdata->clock.shift = tk->tkr_mono.shift;
1120
1121 vdata->boot_ns = boot_ns;
1122 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1123
1124 write_seqcount_end(&vdata->seq);
1125 }
1126 #endif
1127
1128 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1129 {
1130 /*
1131 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1132 * vcpu_enter_guest. This function is only called from
1133 * the physical CPU that is running vcpu.
1134 */
1135 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1136 }
1137
1138 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1139 {
1140 int version;
1141 int r;
1142 struct pvclock_wall_clock wc;
1143 struct timespec boot;
1144
1145 if (!wall_clock)
1146 return;
1147
1148 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1149 if (r)
1150 return;
1151
1152 if (version & 1)
1153 ++version; /* first time write, random junk */
1154
1155 ++version;
1156
1157 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1158
1159 /*
1160 * The guest calculates current wall clock time by adding
1161 * system time (updated by kvm_guest_time_update below) to the
1162 * wall clock specified here. guest system time equals host
1163 * system time for us, thus we must fill in host boot time here.
1164 */
1165 getboottime(&boot);
1166
1167 if (kvm->arch.kvmclock_offset) {
1168 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1169 boot = timespec_sub(boot, ts);
1170 }
1171 wc.sec = boot.tv_sec;
1172 wc.nsec = boot.tv_nsec;
1173 wc.version = version;
1174
1175 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1176
1177 version++;
1178 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1179 }
1180
1181 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1182 {
1183 uint32_t quotient, remainder;
1184
1185 /* Don't try to replace with do_div(), this one calculates
1186 * "(dividend << 32) / divisor" */
1187 __asm__ ( "divl %4"
1188 : "=a" (quotient), "=d" (remainder)
1189 : "0" (0), "1" (dividend), "r" (divisor) );
1190 return quotient;
1191 }
1192
1193 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1194 s8 *pshift, u32 *pmultiplier)
1195 {
1196 uint64_t scaled64;
1197 int32_t shift = 0;
1198 uint64_t tps64;
1199 uint32_t tps32;
1200
1201 tps64 = base_khz * 1000LL;
1202 scaled64 = scaled_khz * 1000LL;
1203 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1204 tps64 >>= 1;
1205 shift--;
1206 }
1207
1208 tps32 = (uint32_t)tps64;
1209 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1210 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1211 scaled64 >>= 1;
1212 else
1213 tps32 <<= 1;
1214 shift++;
1215 }
1216
1217 *pshift = shift;
1218 *pmultiplier = div_frac(scaled64, tps32);
1219
1220 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1221 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1222 }
1223
1224 #ifdef CONFIG_X86_64
1225 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1226 #endif
1227
1228 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1229 static unsigned long max_tsc_khz;
1230
1231 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1232 {
1233 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1234 vcpu->arch.virtual_tsc_shift);
1235 }
1236
1237 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1238 {
1239 u64 v = (u64)khz * (1000000 + ppm);
1240 do_div(v, 1000000);
1241 return v;
1242 }
1243
1244 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1245 {
1246 u32 thresh_lo, thresh_hi;
1247 int use_scaling = 0;
1248
1249 /* tsc_khz can be zero if TSC calibration fails */
1250 if (this_tsc_khz == 0)
1251 return;
1252
1253 /* Compute a scale to convert nanoseconds in TSC cycles */
1254 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1255 &vcpu->arch.virtual_tsc_shift,
1256 &vcpu->arch.virtual_tsc_mult);
1257 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1258
1259 /*
1260 * Compute the variation in TSC rate which is acceptable
1261 * within the range of tolerance and decide if the
1262 * rate being applied is within that bounds of the hardware
1263 * rate. If so, no scaling or compensation need be done.
1264 */
1265 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1266 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1267 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1268 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1269 use_scaling = 1;
1270 }
1271 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1272 }
1273
1274 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1275 {
1276 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1277 vcpu->arch.virtual_tsc_mult,
1278 vcpu->arch.virtual_tsc_shift);
1279 tsc += vcpu->arch.this_tsc_write;
1280 return tsc;
1281 }
1282
1283 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1284 {
1285 #ifdef CONFIG_X86_64
1286 bool vcpus_matched;
1287 struct kvm_arch *ka = &vcpu->kvm->arch;
1288 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1289
1290 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1291 atomic_read(&vcpu->kvm->online_vcpus));
1292
1293 /*
1294 * Once the masterclock is enabled, always perform request in
1295 * order to update it.
1296 *
1297 * In order to enable masterclock, the host clocksource must be TSC
1298 * and the vcpus need to have matched TSCs. When that happens,
1299 * perform request to enable masterclock.
1300 */
1301 if (ka->use_master_clock ||
1302 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1303 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1304
1305 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1306 atomic_read(&vcpu->kvm->online_vcpus),
1307 ka->use_master_clock, gtod->clock.vclock_mode);
1308 #endif
1309 }
1310
1311 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1312 {
1313 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1314 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1315 }
1316
1317 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1318 {
1319 struct kvm *kvm = vcpu->kvm;
1320 u64 offset, ns, elapsed;
1321 unsigned long flags;
1322 s64 usdiff;
1323 bool matched;
1324 bool already_matched;
1325 u64 data = msr->data;
1326
1327 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1328 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1329 ns = get_kernel_ns();
1330 elapsed = ns - kvm->arch.last_tsc_nsec;
1331
1332 if (vcpu->arch.virtual_tsc_khz) {
1333 int faulted = 0;
1334
1335 /* n.b - signed multiplication and division required */
1336 usdiff = data - kvm->arch.last_tsc_write;
1337 #ifdef CONFIG_X86_64
1338 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1339 #else
1340 /* do_div() only does unsigned */
1341 asm("1: idivl %[divisor]\n"
1342 "2: xor %%edx, %%edx\n"
1343 " movl $0, %[faulted]\n"
1344 "3:\n"
1345 ".section .fixup,\"ax\"\n"
1346 "4: movl $1, %[faulted]\n"
1347 " jmp 3b\n"
1348 ".previous\n"
1349
1350 _ASM_EXTABLE(1b, 4b)
1351
1352 : "=A"(usdiff), [faulted] "=r" (faulted)
1353 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1354
1355 #endif
1356 do_div(elapsed, 1000);
1357 usdiff -= elapsed;
1358 if (usdiff < 0)
1359 usdiff = -usdiff;
1360
1361 /* idivl overflow => difference is larger than USEC_PER_SEC */
1362 if (faulted)
1363 usdiff = USEC_PER_SEC;
1364 } else
1365 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1366
1367 /*
1368 * Special case: TSC write with a small delta (1 second) of virtual
1369 * cycle time against real time is interpreted as an attempt to
1370 * synchronize the CPU.
1371 *
1372 * For a reliable TSC, we can match TSC offsets, and for an unstable
1373 * TSC, we add elapsed time in this computation. We could let the
1374 * compensation code attempt to catch up if we fall behind, but
1375 * it's better to try to match offsets from the beginning.
1376 */
1377 if (usdiff < USEC_PER_SEC &&
1378 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1379 if (!check_tsc_unstable()) {
1380 offset = kvm->arch.cur_tsc_offset;
1381 pr_debug("kvm: matched tsc offset for %llu\n", data);
1382 } else {
1383 u64 delta = nsec_to_cycles(vcpu, elapsed);
1384 data += delta;
1385 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1386 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1387 }
1388 matched = true;
1389 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1390 } else {
1391 /*
1392 * We split periods of matched TSC writes into generations.
1393 * For each generation, we track the original measured
1394 * nanosecond time, offset, and write, so if TSCs are in
1395 * sync, we can match exact offset, and if not, we can match
1396 * exact software computation in compute_guest_tsc()
1397 *
1398 * These values are tracked in kvm->arch.cur_xxx variables.
1399 */
1400 kvm->arch.cur_tsc_generation++;
1401 kvm->arch.cur_tsc_nsec = ns;
1402 kvm->arch.cur_tsc_write = data;
1403 kvm->arch.cur_tsc_offset = offset;
1404 matched = false;
1405 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1406 kvm->arch.cur_tsc_generation, data);
1407 }
1408
1409 /*
1410 * We also track th most recent recorded KHZ, write and time to
1411 * allow the matching interval to be extended at each write.
1412 */
1413 kvm->arch.last_tsc_nsec = ns;
1414 kvm->arch.last_tsc_write = data;
1415 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1416
1417 vcpu->arch.last_guest_tsc = data;
1418
1419 /* Keep track of which generation this VCPU has synchronized to */
1420 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1421 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1422 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1423
1424 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1425 update_ia32_tsc_adjust_msr(vcpu, offset);
1426 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1427 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1428
1429 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1430 if (!matched) {
1431 kvm->arch.nr_vcpus_matched_tsc = 0;
1432 } else if (!already_matched) {
1433 kvm->arch.nr_vcpus_matched_tsc++;
1434 }
1435
1436 kvm_track_tsc_matching(vcpu);
1437 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1438 }
1439
1440 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1441
1442 #ifdef CONFIG_X86_64
1443
1444 static cycle_t read_tsc(void)
1445 {
1446 cycle_t ret = (cycle_t)rdtsc_ordered();
1447 u64 last = pvclock_gtod_data.clock.cycle_last;
1448
1449 if (likely(ret >= last))
1450 return ret;
1451
1452 /*
1453 * GCC likes to generate cmov here, but this branch is extremely
1454 * predictable (it's just a funciton of time and the likely is
1455 * very likely) and there's a data dependence, so force GCC
1456 * to generate a branch instead. I don't barrier() because
1457 * we don't actually need a barrier, and if this function
1458 * ever gets inlined it will generate worse code.
1459 */
1460 asm volatile ("");
1461 return last;
1462 }
1463
1464 static inline u64 vgettsc(cycle_t *cycle_now)
1465 {
1466 long v;
1467 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1468
1469 *cycle_now = read_tsc();
1470
1471 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1472 return v * gtod->clock.mult;
1473 }
1474
1475 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1476 {
1477 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1478 unsigned long seq;
1479 int mode;
1480 u64 ns;
1481
1482 do {
1483 seq = read_seqcount_begin(&gtod->seq);
1484 mode = gtod->clock.vclock_mode;
1485 ns = gtod->nsec_base;
1486 ns += vgettsc(cycle_now);
1487 ns >>= gtod->clock.shift;
1488 ns += gtod->boot_ns;
1489 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1490 *t = ns;
1491
1492 return mode;
1493 }
1494
1495 /* returns true if host is using tsc clocksource */
1496 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1497 {
1498 /* checked again under seqlock below */
1499 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1500 return false;
1501
1502 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1503 }
1504 #endif
1505
1506 /*
1507 *
1508 * Assuming a stable TSC across physical CPUS, and a stable TSC
1509 * across virtual CPUs, the following condition is possible.
1510 * Each numbered line represents an event visible to both
1511 * CPUs at the next numbered event.
1512 *
1513 * "timespecX" represents host monotonic time. "tscX" represents
1514 * RDTSC value.
1515 *
1516 * VCPU0 on CPU0 | VCPU1 on CPU1
1517 *
1518 * 1. read timespec0,tsc0
1519 * 2. | timespec1 = timespec0 + N
1520 * | tsc1 = tsc0 + M
1521 * 3. transition to guest | transition to guest
1522 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1523 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1524 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1525 *
1526 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1527 *
1528 * - ret0 < ret1
1529 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1530 * ...
1531 * - 0 < N - M => M < N
1532 *
1533 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1534 * always the case (the difference between two distinct xtime instances
1535 * might be smaller then the difference between corresponding TSC reads,
1536 * when updating guest vcpus pvclock areas).
1537 *
1538 * To avoid that problem, do not allow visibility of distinct
1539 * system_timestamp/tsc_timestamp values simultaneously: use a master
1540 * copy of host monotonic time values. Update that master copy
1541 * in lockstep.
1542 *
1543 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1544 *
1545 */
1546
1547 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1548 {
1549 #ifdef CONFIG_X86_64
1550 struct kvm_arch *ka = &kvm->arch;
1551 int vclock_mode;
1552 bool host_tsc_clocksource, vcpus_matched;
1553
1554 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1555 atomic_read(&kvm->online_vcpus));
1556
1557 /*
1558 * If the host uses TSC clock, then passthrough TSC as stable
1559 * to the guest.
1560 */
1561 host_tsc_clocksource = kvm_get_time_and_clockread(
1562 &ka->master_kernel_ns,
1563 &ka->master_cycle_now);
1564
1565 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1566 && !backwards_tsc_observed
1567 && !ka->boot_vcpu_runs_old_kvmclock;
1568
1569 if (ka->use_master_clock)
1570 atomic_set(&kvm_guest_has_master_clock, 1);
1571
1572 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1573 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1574 vcpus_matched);
1575 #endif
1576 }
1577
1578 static void kvm_gen_update_masterclock(struct kvm *kvm)
1579 {
1580 #ifdef CONFIG_X86_64
1581 int i;
1582 struct kvm_vcpu *vcpu;
1583 struct kvm_arch *ka = &kvm->arch;
1584
1585 spin_lock(&ka->pvclock_gtod_sync_lock);
1586 kvm_make_mclock_inprogress_request(kvm);
1587 /* no guest entries from this point */
1588 pvclock_update_vm_gtod_copy(kvm);
1589
1590 kvm_for_each_vcpu(i, vcpu, kvm)
1591 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1592
1593 /* guest entries allowed */
1594 kvm_for_each_vcpu(i, vcpu, kvm)
1595 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1596
1597 spin_unlock(&ka->pvclock_gtod_sync_lock);
1598 #endif
1599 }
1600
1601 static int kvm_guest_time_update(struct kvm_vcpu *v)
1602 {
1603 unsigned long flags, this_tsc_khz;
1604 struct kvm_vcpu_arch *vcpu = &v->arch;
1605 struct kvm_arch *ka = &v->kvm->arch;
1606 s64 kernel_ns;
1607 u64 tsc_timestamp, host_tsc;
1608 struct pvclock_vcpu_time_info guest_hv_clock;
1609 u8 pvclock_flags;
1610 bool use_master_clock;
1611
1612 kernel_ns = 0;
1613 host_tsc = 0;
1614
1615 /*
1616 * If the host uses TSC clock, then passthrough TSC as stable
1617 * to the guest.
1618 */
1619 spin_lock(&ka->pvclock_gtod_sync_lock);
1620 use_master_clock = ka->use_master_clock;
1621 if (use_master_clock) {
1622 host_tsc = ka->master_cycle_now;
1623 kernel_ns = ka->master_kernel_ns;
1624 }
1625 spin_unlock(&ka->pvclock_gtod_sync_lock);
1626
1627 /* Keep irq disabled to prevent changes to the clock */
1628 local_irq_save(flags);
1629 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1630 if (unlikely(this_tsc_khz == 0)) {
1631 local_irq_restore(flags);
1632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1633 return 1;
1634 }
1635 if (!use_master_clock) {
1636 host_tsc = rdtsc();
1637 kernel_ns = get_kernel_ns();
1638 }
1639
1640 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1641
1642 /*
1643 * We may have to catch up the TSC to match elapsed wall clock
1644 * time for two reasons, even if kvmclock is used.
1645 * 1) CPU could have been running below the maximum TSC rate
1646 * 2) Broken TSC compensation resets the base at each VCPU
1647 * entry to avoid unknown leaps of TSC even when running
1648 * again on the same CPU. This may cause apparent elapsed
1649 * time to disappear, and the guest to stand still or run
1650 * very slowly.
1651 */
1652 if (vcpu->tsc_catchup) {
1653 u64 tsc = compute_guest_tsc(v, kernel_ns);
1654 if (tsc > tsc_timestamp) {
1655 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1656 tsc_timestamp = tsc;
1657 }
1658 }
1659
1660 local_irq_restore(flags);
1661
1662 if (!vcpu->pv_time_enabled)
1663 return 0;
1664
1665 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1666 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1667 &vcpu->hv_clock.tsc_shift,
1668 &vcpu->hv_clock.tsc_to_system_mul);
1669 vcpu->hw_tsc_khz = this_tsc_khz;
1670 }
1671
1672 /* With all the info we got, fill in the values */
1673 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1674 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1675 vcpu->last_guest_tsc = tsc_timestamp;
1676
1677 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1678 &guest_hv_clock, sizeof(guest_hv_clock))))
1679 return 0;
1680
1681 /* This VCPU is paused, but it's legal for a guest to read another
1682 * VCPU's kvmclock, so we really have to follow the specification where
1683 * it says that version is odd if data is being modified, and even after
1684 * it is consistent.
1685 *
1686 * Version field updates must be kept separate. This is because
1687 * kvm_write_guest_cached might use a "rep movs" instruction, and
1688 * writes within a string instruction are weakly ordered. So there
1689 * are three writes overall.
1690 *
1691 * As a small optimization, only write the version field in the first
1692 * and third write. The vcpu->pv_time cache is still valid, because the
1693 * version field is the first in the struct.
1694 */
1695 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1696
1697 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1698 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1699 &vcpu->hv_clock,
1700 sizeof(vcpu->hv_clock.version));
1701
1702 smp_wmb();
1703
1704 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1705 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1706
1707 if (vcpu->pvclock_set_guest_stopped_request) {
1708 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1709 vcpu->pvclock_set_guest_stopped_request = false;
1710 }
1711
1712 /* If the host uses TSC clocksource, then it is stable */
1713 if (use_master_clock)
1714 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1715
1716 vcpu->hv_clock.flags = pvclock_flags;
1717
1718 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1719
1720 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1721 &vcpu->hv_clock,
1722 sizeof(vcpu->hv_clock));
1723
1724 smp_wmb();
1725
1726 vcpu->hv_clock.version++;
1727 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1728 &vcpu->hv_clock,
1729 sizeof(vcpu->hv_clock.version));
1730 return 0;
1731 }
1732
1733 /*
1734 * kvmclock updates which are isolated to a given vcpu, such as
1735 * vcpu->cpu migration, should not allow system_timestamp from
1736 * the rest of the vcpus to remain static. Otherwise ntp frequency
1737 * correction applies to one vcpu's system_timestamp but not
1738 * the others.
1739 *
1740 * So in those cases, request a kvmclock update for all vcpus.
1741 * We need to rate-limit these requests though, as they can
1742 * considerably slow guests that have a large number of vcpus.
1743 * The time for a remote vcpu to update its kvmclock is bound
1744 * by the delay we use to rate-limit the updates.
1745 */
1746
1747 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1748
1749 static void kvmclock_update_fn(struct work_struct *work)
1750 {
1751 int i;
1752 struct delayed_work *dwork = to_delayed_work(work);
1753 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1754 kvmclock_update_work);
1755 struct kvm *kvm = container_of(ka, struct kvm, arch);
1756 struct kvm_vcpu *vcpu;
1757
1758 kvm_for_each_vcpu(i, vcpu, kvm) {
1759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1760 kvm_vcpu_kick(vcpu);
1761 }
1762 }
1763
1764 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1765 {
1766 struct kvm *kvm = v->kvm;
1767
1768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1769 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1770 KVMCLOCK_UPDATE_DELAY);
1771 }
1772
1773 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1774
1775 static void kvmclock_sync_fn(struct work_struct *work)
1776 {
1777 struct delayed_work *dwork = to_delayed_work(work);
1778 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1779 kvmclock_sync_work);
1780 struct kvm *kvm = container_of(ka, struct kvm, arch);
1781
1782 if (!kvmclock_periodic_sync)
1783 return;
1784
1785 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1786 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1787 KVMCLOCK_SYNC_PERIOD);
1788 }
1789
1790 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1791 {
1792 u64 mcg_cap = vcpu->arch.mcg_cap;
1793 unsigned bank_num = mcg_cap & 0xff;
1794
1795 switch (msr) {
1796 case MSR_IA32_MCG_STATUS:
1797 vcpu->arch.mcg_status = data;
1798 break;
1799 case MSR_IA32_MCG_CTL:
1800 if (!(mcg_cap & MCG_CTL_P))
1801 return 1;
1802 if (data != 0 && data != ~(u64)0)
1803 return -1;
1804 vcpu->arch.mcg_ctl = data;
1805 break;
1806 default:
1807 if (msr >= MSR_IA32_MC0_CTL &&
1808 msr < MSR_IA32_MCx_CTL(bank_num)) {
1809 u32 offset = msr - MSR_IA32_MC0_CTL;
1810 /* only 0 or all 1s can be written to IA32_MCi_CTL
1811 * some Linux kernels though clear bit 10 in bank 4 to
1812 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1813 * this to avoid an uncatched #GP in the guest
1814 */
1815 if ((offset & 0x3) == 0 &&
1816 data != 0 && (data | (1 << 10)) != ~(u64)0)
1817 return -1;
1818 vcpu->arch.mce_banks[offset] = data;
1819 break;
1820 }
1821 return 1;
1822 }
1823 return 0;
1824 }
1825
1826 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1827 {
1828 struct kvm *kvm = vcpu->kvm;
1829 int lm = is_long_mode(vcpu);
1830 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1831 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1832 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1833 : kvm->arch.xen_hvm_config.blob_size_32;
1834 u32 page_num = data & ~PAGE_MASK;
1835 u64 page_addr = data & PAGE_MASK;
1836 u8 *page;
1837 int r;
1838
1839 r = -E2BIG;
1840 if (page_num >= blob_size)
1841 goto out;
1842 r = -ENOMEM;
1843 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1844 if (IS_ERR(page)) {
1845 r = PTR_ERR(page);
1846 goto out;
1847 }
1848 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1849 goto out_free;
1850 r = 0;
1851 out_free:
1852 kfree(page);
1853 out:
1854 return r;
1855 }
1856
1857 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1858 {
1859 gpa_t gpa = data & ~0x3f;
1860
1861 /* Bits 2:5 are reserved, Should be zero */
1862 if (data & 0x3c)
1863 return 1;
1864
1865 vcpu->arch.apf.msr_val = data;
1866
1867 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1868 kvm_clear_async_pf_completion_queue(vcpu);
1869 kvm_async_pf_hash_reset(vcpu);
1870 return 0;
1871 }
1872
1873 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1874 sizeof(u32)))
1875 return 1;
1876
1877 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1878 kvm_async_pf_wakeup_all(vcpu);
1879 return 0;
1880 }
1881
1882 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1883 {
1884 vcpu->arch.pv_time_enabled = false;
1885 }
1886
1887 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1888 {
1889 u64 delta;
1890
1891 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1892 return;
1893
1894 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1895 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1896 vcpu->arch.st.accum_steal = delta;
1897 }
1898
1899 static void record_steal_time(struct kvm_vcpu *vcpu)
1900 {
1901 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1902 return;
1903
1904 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1905 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1906 return;
1907
1908 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1909 vcpu->arch.st.steal.version += 2;
1910 vcpu->arch.st.accum_steal = 0;
1911
1912 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1913 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1914 }
1915
1916 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1917 {
1918 bool pr = false;
1919 u32 msr = msr_info->index;
1920 u64 data = msr_info->data;
1921
1922 switch (msr) {
1923 case MSR_AMD64_NB_CFG:
1924 case MSR_IA32_UCODE_REV:
1925 case MSR_IA32_UCODE_WRITE:
1926 case MSR_VM_HSAVE_PA:
1927 case MSR_AMD64_PATCH_LOADER:
1928 case MSR_AMD64_BU_CFG2:
1929 break;
1930
1931 case MSR_EFER:
1932 return set_efer(vcpu, data);
1933 case MSR_K7_HWCR:
1934 data &= ~(u64)0x40; /* ignore flush filter disable */
1935 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1936 data &= ~(u64)0x8; /* ignore TLB cache disable */
1937 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1938 if (data != 0) {
1939 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1940 data);
1941 return 1;
1942 }
1943 break;
1944 case MSR_FAM10H_MMIO_CONF_BASE:
1945 if (data != 0) {
1946 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1947 "0x%llx\n", data);
1948 return 1;
1949 }
1950 break;
1951 case MSR_IA32_DEBUGCTLMSR:
1952 if (!data) {
1953 /* We support the non-activated case already */
1954 break;
1955 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1956 /* Values other than LBR and BTF are vendor-specific,
1957 thus reserved and should throw a #GP */
1958 return 1;
1959 }
1960 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1961 __func__, data);
1962 break;
1963 case 0x200 ... 0x2ff:
1964 return kvm_mtrr_set_msr(vcpu, msr, data);
1965 case MSR_IA32_APICBASE:
1966 return kvm_set_apic_base(vcpu, msr_info);
1967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1968 return kvm_x2apic_msr_write(vcpu, msr, data);
1969 case MSR_IA32_TSCDEADLINE:
1970 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1971 break;
1972 case MSR_IA32_TSC_ADJUST:
1973 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1974 if (!msr_info->host_initiated) {
1975 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1976 adjust_tsc_offset_guest(vcpu, adj);
1977 }
1978 vcpu->arch.ia32_tsc_adjust_msr = data;
1979 }
1980 break;
1981 case MSR_IA32_MISC_ENABLE:
1982 vcpu->arch.ia32_misc_enable_msr = data;
1983 break;
1984 case MSR_IA32_SMBASE:
1985 if (!msr_info->host_initiated)
1986 return 1;
1987 vcpu->arch.smbase = data;
1988 break;
1989 case MSR_KVM_WALL_CLOCK_NEW:
1990 case MSR_KVM_WALL_CLOCK:
1991 vcpu->kvm->arch.wall_clock = data;
1992 kvm_write_wall_clock(vcpu->kvm, data);
1993 break;
1994 case MSR_KVM_SYSTEM_TIME_NEW:
1995 case MSR_KVM_SYSTEM_TIME: {
1996 u64 gpa_offset;
1997 struct kvm_arch *ka = &vcpu->kvm->arch;
1998
1999 kvmclock_reset(vcpu);
2000
2001 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2002 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2003
2004 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2005 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2006 &vcpu->requests);
2007
2008 ka->boot_vcpu_runs_old_kvmclock = tmp;
2009 }
2010
2011 vcpu->arch.time = data;
2012 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2013
2014 /* we verify if the enable bit is set... */
2015 if (!(data & 1))
2016 break;
2017
2018 gpa_offset = data & ~(PAGE_MASK | 1);
2019
2020 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2021 &vcpu->arch.pv_time, data & ~1ULL,
2022 sizeof(struct pvclock_vcpu_time_info)))
2023 vcpu->arch.pv_time_enabled = false;
2024 else
2025 vcpu->arch.pv_time_enabled = true;
2026
2027 break;
2028 }
2029 case MSR_KVM_ASYNC_PF_EN:
2030 if (kvm_pv_enable_async_pf(vcpu, data))
2031 return 1;
2032 break;
2033 case MSR_KVM_STEAL_TIME:
2034
2035 if (unlikely(!sched_info_on()))
2036 return 1;
2037
2038 if (data & KVM_STEAL_RESERVED_MASK)
2039 return 1;
2040
2041 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2042 data & KVM_STEAL_VALID_BITS,
2043 sizeof(struct kvm_steal_time)))
2044 return 1;
2045
2046 vcpu->arch.st.msr_val = data;
2047
2048 if (!(data & KVM_MSR_ENABLED))
2049 break;
2050
2051 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2052
2053 preempt_disable();
2054 accumulate_steal_time(vcpu);
2055 preempt_enable();
2056
2057 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2058
2059 break;
2060 case MSR_KVM_PV_EOI_EN:
2061 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2062 return 1;
2063 break;
2064
2065 case MSR_IA32_MCG_CTL:
2066 case MSR_IA32_MCG_STATUS:
2067 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2068 return set_msr_mce(vcpu, msr, data);
2069
2070 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2071 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2072 pr = true; /* fall through */
2073 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2074 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2075 if (kvm_pmu_is_valid_msr(vcpu, msr))
2076 return kvm_pmu_set_msr(vcpu, msr_info);
2077
2078 if (pr || data != 0)
2079 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2080 "0x%x data 0x%llx\n", msr, data);
2081 break;
2082 case MSR_K7_CLK_CTL:
2083 /*
2084 * Ignore all writes to this no longer documented MSR.
2085 * Writes are only relevant for old K7 processors,
2086 * all pre-dating SVM, but a recommended workaround from
2087 * AMD for these chips. It is possible to specify the
2088 * affected processor models on the command line, hence
2089 * the need to ignore the workaround.
2090 */
2091 break;
2092 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2093 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2094 case HV_X64_MSR_CRASH_CTL:
2095 return kvm_hv_set_msr_common(vcpu, msr, data,
2096 msr_info->host_initiated);
2097 case MSR_IA32_BBL_CR_CTL3:
2098 /* Drop writes to this legacy MSR -- see rdmsr
2099 * counterpart for further detail.
2100 */
2101 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2102 break;
2103 case MSR_AMD64_OSVW_ID_LENGTH:
2104 if (!guest_cpuid_has_osvw(vcpu))
2105 return 1;
2106 vcpu->arch.osvw.length = data;
2107 break;
2108 case MSR_AMD64_OSVW_STATUS:
2109 if (!guest_cpuid_has_osvw(vcpu))
2110 return 1;
2111 vcpu->arch.osvw.status = data;
2112 break;
2113 default:
2114 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2115 return xen_hvm_config(vcpu, data);
2116 if (kvm_pmu_is_valid_msr(vcpu, msr))
2117 return kvm_pmu_set_msr(vcpu, msr_info);
2118 if (!ignore_msrs) {
2119 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2120 msr, data);
2121 return 1;
2122 } else {
2123 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2124 msr, data);
2125 break;
2126 }
2127 }
2128 return 0;
2129 }
2130 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2131
2132
2133 /*
2134 * Reads an msr value (of 'msr_index') into 'pdata'.
2135 * Returns 0 on success, non-0 otherwise.
2136 * Assumes vcpu_load() was already called.
2137 */
2138 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2139 {
2140 return kvm_x86_ops->get_msr(vcpu, msr);
2141 }
2142 EXPORT_SYMBOL_GPL(kvm_get_msr);
2143
2144 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2145 {
2146 u64 data;
2147 u64 mcg_cap = vcpu->arch.mcg_cap;
2148 unsigned bank_num = mcg_cap & 0xff;
2149
2150 switch (msr) {
2151 case MSR_IA32_P5_MC_ADDR:
2152 case MSR_IA32_P5_MC_TYPE:
2153 data = 0;
2154 break;
2155 case MSR_IA32_MCG_CAP:
2156 data = vcpu->arch.mcg_cap;
2157 break;
2158 case MSR_IA32_MCG_CTL:
2159 if (!(mcg_cap & MCG_CTL_P))
2160 return 1;
2161 data = vcpu->arch.mcg_ctl;
2162 break;
2163 case MSR_IA32_MCG_STATUS:
2164 data = vcpu->arch.mcg_status;
2165 break;
2166 default:
2167 if (msr >= MSR_IA32_MC0_CTL &&
2168 msr < MSR_IA32_MCx_CTL(bank_num)) {
2169 u32 offset = msr - MSR_IA32_MC0_CTL;
2170 data = vcpu->arch.mce_banks[offset];
2171 break;
2172 }
2173 return 1;
2174 }
2175 *pdata = data;
2176 return 0;
2177 }
2178
2179 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2180 {
2181 switch (msr_info->index) {
2182 case MSR_IA32_PLATFORM_ID:
2183 case MSR_IA32_EBL_CR_POWERON:
2184 case MSR_IA32_DEBUGCTLMSR:
2185 case MSR_IA32_LASTBRANCHFROMIP:
2186 case MSR_IA32_LASTBRANCHTOIP:
2187 case MSR_IA32_LASTINTFROMIP:
2188 case MSR_IA32_LASTINTTOIP:
2189 case MSR_K8_SYSCFG:
2190 case MSR_K8_TSEG_ADDR:
2191 case MSR_K8_TSEG_MASK:
2192 case MSR_K7_HWCR:
2193 case MSR_VM_HSAVE_PA:
2194 case MSR_K8_INT_PENDING_MSG:
2195 case MSR_AMD64_NB_CFG:
2196 case MSR_FAM10H_MMIO_CONF_BASE:
2197 case MSR_AMD64_BU_CFG2:
2198 msr_info->data = 0;
2199 break;
2200 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2201 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2202 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2203 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2204 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2205 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2206 msr_info->data = 0;
2207 break;
2208 case MSR_IA32_UCODE_REV:
2209 msr_info->data = 0x100000000ULL;
2210 break;
2211 case MSR_MTRRcap:
2212 case 0x200 ... 0x2ff:
2213 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2214 case 0xcd: /* fsb frequency */
2215 msr_info->data = 3;
2216 break;
2217 /*
2218 * MSR_EBC_FREQUENCY_ID
2219 * Conservative value valid for even the basic CPU models.
2220 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2221 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2222 * and 266MHz for model 3, or 4. Set Core Clock
2223 * Frequency to System Bus Frequency Ratio to 1 (bits
2224 * 31:24) even though these are only valid for CPU
2225 * models > 2, however guests may end up dividing or
2226 * multiplying by zero otherwise.
2227 */
2228 case MSR_EBC_FREQUENCY_ID:
2229 msr_info->data = 1 << 24;
2230 break;
2231 case MSR_IA32_APICBASE:
2232 msr_info->data = kvm_get_apic_base(vcpu);
2233 break;
2234 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2235 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2236 break;
2237 case MSR_IA32_TSCDEADLINE:
2238 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2239 break;
2240 case MSR_IA32_TSC_ADJUST:
2241 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2242 break;
2243 case MSR_IA32_MISC_ENABLE:
2244 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2245 break;
2246 case MSR_IA32_SMBASE:
2247 if (!msr_info->host_initiated)
2248 return 1;
2249 msr_info->data = vcpu->arch.smbase;
2250 break;
2251 case MSR_IA32_PERF_STATUS:
2252 /* TSC increment by tick */
2253 msr_info->data = 1000ULL;
2254 /* CPU multiplier */
2255 msr_info->data |= (((uint64_t)4ULL) << 40);
2256 break;
2257 case MSR_EFER:
2258 msr_info->data = vcpu->arch.efer;
2259 break;
2260 case MSR_KVM_WALL_CLOCK:
2261 case MSR_KVM_WALL_CLOCK_NEW:
2262 msr_info->data = vcpu->kvm->arch.wall_clock;
2263 break;
2264 case MSR_KVM_SYSTEM_TIME:
2265 case MSR_KVM_SYSTEM_TIME_NEW:
2266 msr_info->data = vcpu->arch.time;
2267 break;
2268 case MSR_KVM_ASYNC_PF_EN:
2269 msr_info->data = vcpu->arch.apf.msr_val;
2270 break;
2271 case MSR_KVM_STEAL_TIME:
2272 msr_info->data = vcpu->arch.st.msr_val;
2273 break;
2274 case MSR_KVM_PV_EOI_EN:
2275 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2276 break;
2277 case MSR_IA32_P5_MC_ADDR:
2278 case MSR_IA32_P5_MC_TYPE:
2279 case MSR_IA32_MCG_CAP:
2280 case MSR_IA32_MCG_CTL:
2281 case MSR_IA32_MCG_STATUS:
2282 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2283 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2284 case MSR_K7_CLK_CTL:
2285 /*
2286 * Provide expected ramp-up count for K7. All other
2287 * are set to zero, indicating minimum divisors for
2288 * every field.
2289 *
2290 * This prevents guest kernels on AMD host with CPU
2291 * type 6, model 8 and higher from exploding due to
2292 * the rdmsr failing.
2293 */
2294 msr_info->data = 0x20000000;
2295 break;
2296 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2297 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2298 case HV_X64_MSR_CRASH_CTL:
2299 return kvm_hv_get_msr_common(vcpu,
2300 msr_info->index, &msr_info->data);
2301 break;
2302 case MSR_IA32_BBL_CR_CTL3:
2303 /* This legacy MSR exists but isn't fully documented in current
2304 * silicon. It is however accessed by winxp in very narrow
2305 * scenarios where it sets bit #19, itself documented as
2306 * a "reserved" bit. Best effort attempt to source coherent
2307 * read data here should the balance of the register be
2308 * interpreted by the guest:
2309 *
2310 * L2 cache control register 3: 64GB range, 256KB size,
2311 * enabled, latency 0x1, configured
2312 */
2313 msr_info->data = 0xbe702111;
2314 break;
2315 case MSR_AMD64_OSVW_ID_LENGTH:
2316 if (!guest_cpuid_has_osvw(vcpu))
2317 return 1;
2318 msr_info->data = vcpu->arch.osvw.length;
2319 break;
2320 case MSR_AMD64_OSVW_STATUS:
2321 if (!guest_cpuid_has_osvw(vcpu))
2322 return 1;
2323 msr_info->data = vcpu->arch.osvw.status;
2324 break;
2325 default:
2326 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2327 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2328 if (!ignore_msrs) {
2329 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2330 return 1;
2331 } else {
2332 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2333 msr_info->data = 0;
2334 }
2335 break;
2336 }
2337 return 0;
2338 }
2339 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2340
2341 /*
2342 * Read or write a bunch of msrs. All parameters are kernel addresses.
2343 *
2344 * @return number of msrs set successfully.
2345 */
2346 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2347 struct kvm_msr_entry *entries,
2348 int (*do_msr)(struct kvm_vcpu *vcpu,
2349 unsigned index, u64 *data))
2350 {
2351 int i, idx;
2352
2353 idx = srcu_read_lock(&vcpu->kvm->srcu);
2354 for (i = 0; i < msrs->nmsrs; ++i)
2355 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2356 break;
2357 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2358
2359 return i;
2360 }
2361
2362 /*
2363 * Read or write a bunch of msrs. Parameters are user addresses.
2364 *
2365 * @return number of msrs set successfully.
2366 */
2367 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2368 int (*do_msr)(struct kvm_vcpu *vcpu,
2369 unsigned index, u64 *data),
2370 int writeback)
2371 {
2372 struct kvm_msrs msrs;
2373 struct kvm_msr_entry *entries;
2374 int r, n;
2375 unsigned size;
2376
2377 r = -EFAULT;
2378 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2379 goto out;
2380
2381 r = -E2BIG;
2382 if (msrs.nmsrs >= MAX_IO_MSRS)
2383 goto out;
2384
2385 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2386 entries = memdup_user(user_msrs->entries, size);
2387 if (IS_ERR(entries)) {
2388 r = PTR_ERR(entries);
2389 goto out;
2390 }
2391
2392 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2393 if (r < 0)
2394 goto out_free;
2395
2396 r = -EFAULT;
2397 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2398 goto out_free;
2399
2400 r = n;
2401
2402 out_free:
2403 kfree(entries);
2404 out:
2405 return r;
2406 }
2407
2408 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2409 {
2410 int r;
2411
2412 switch (ext) {
2413 case KVM_CAP_IRQCHIP:
2414 case KVM_CAP_HLT:
2415 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2416 case KVM_CAP_SET_TSS_ADDR:
2417 case KVM_CAP_EXT_CPUID:
2418 case KVM_CAP_EXT_EMUL_CPUID:
2419 case KVM_CAP_CLOCKSOURCE:
2420 case KVM_CAP_PIT:
2421 case KVM_CAP_NOP_IO_DELAY:
2422 case KVM_CAP_MP_STATE:
2423 case KVM_CAP_SYNC_MMU:
2424 case KVM_CAP_USER_NMI:
2425 case KVM_CAP_REINJECT_CONTROL:
2426 case KVM_CAP_IRQ_INJECT_STATUS:
2427 case KVM_CAP_IOEVENTFD:
2428 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2429 case KVM_CAP_PIT2:
2430 case KVM_CAP_PIT_STATE2:
2431 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2432 case KVM_CAP_XEN_HVM:
2433 case KVM_CAP_ADJUST_CLOCK:
2434 case KVM_CAP_VCPU_EVENTS:
2435 case KVM_CAP_HYPERV:
2436 case KVM_CAP_HYPERV_VAPIC:
2437 case KVM_CAP_HYPERV_SPIN:
2438 case KVM_CAP_PCI_SEGMENT:
2439 case KVM_CAP_DEBUGREGS:
2440 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2441 case KVM_CAP_XSAVE:
2442 case KVM_CAP_ASYNC_PF:
2443 case KVM_CAP_GET_TSC_KHZ:
2444 case KVM_CAP_KVMCLOCK_CTRL:
2445 case KVM_CAP_READONLY_MEM:
2446 case KVM_CAP_HYPERV_TIME:
2447 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2448 case KVM_CAP_TSC_DEADLINE_TIMER:
2449 case KVM_CAP_ENABLE_CAP_VM:
2450 case KVM_CAP_DISABLE_QUIRKS:
2451 case KVM_CAP_SET_BOOT_CPU_ID:
2452 case KVM_CAP_SPLIT_IRQCHIP:
2453 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2454 case KVM_CAP_ASSIGN_DEV_IRQ:
2455 case KVM_CAP_PCI_2_3:
2456 #endif
2457 r = 1;
2458 break;
2459 case KVM_CAP_X86_SMM:
2460 /* SMBASE is usually relocated above 1M on modern chipsets,
2461 * and SMM handlers might indeed rely on 4G segment limits,
2462 * so do not report SMM to be available if real mode is
2463 * emulated via vm86 mode. Still, do not go to great lengths
2464 * to avoid userspace's usage of the feature, because it is a
2465 * fringe case that is not enabled except via specific settings
2466 * of the module parameters.
2467 */
2468 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2469 break;
2470 case KVM_CAP_COALESCED_MMIO:
2471 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2472 break;
2473 case KVM_CAP_VAPIC:
2474 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2475 break;
2476 case KVM_CAP_NR_VCPUS:
2477 r = KVM_SOFT_MAX_VCPUS;
2478 break;
2479 case KVM_CAP_MAX_VCPUS:
2480 r = KVM_MAX_VCPUS;
2481 break;
2482 case KVM_CAP_NR_MEMSLOTS:
2483 r = KVM_USER_MEM_SLOTS;
2484 break;
2485 case KVM_CAP_PV_MMU: /* obsolete */
2486 r = 0;
2487 break;
2488 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2489 case KVM_CAP_IOMMU:
2490 r = iommu_present(&pci_bus_type);
2491 break;
2492 #endif
2493 case KVM_CAP_MCE:
2494 r = KVM_MAX_MCE_BANKS;
2495 break;
2496 case KVM_CAP_XCRS:
2497 r = cpu_has_xsave;
2498 break;
2499 case KVM_CAP_TSC_CONTROL:
2500 r = kvm_has_tsc_control;
2501 break;
2502 default:
2503 r = 0;
2504 break;
2505 }
2506 return r;
2507
2508 }
2509
2510 long kvm_arch_dev_ioctl(struct file *filp,
2511 unsigned int ioctl, unsigned long arg)
2512 {
2513 void __user *argp = (void __user *)arg;
2514 long r;
2515
2516 switch (ioctl) {
2517 case KVM_GET_MSR_INDEX_LIST: {
2518 struct kvm_msr_list __user *user_msr_list = argp;
2519 struct kvm_msr_list msr_list;
2520 unsigned n;
2521
2522 r = -EFAULT;
2523 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2524 goto out;
2525 n = msr_list.nmsrs;
2526 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2527 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2528 goto out;
2529 r = -E2BIG;
2530 if (n < msr_list.nmsrs)
2531 goto out;
2532 r = -EFAULT;
2533 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2534 num_msrs_to_save * sizeof(u32)))
2535 goto out;
2536 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2537 &emulated_msrs,
2538 num_emulated_msrs * sizeof(u32)))
2539 goto out;
2540 r = 0;
2541 break;
2542 }
2543 case KVM_GET_SUPPORTED_CPUID:
2544 case KVM_GET_EMULATED_CPUID: {
2545 struct kvm_cpuid2 __user *cpuid_arg = argp;
2546 struct kvm_cpuid2 cpuid;
2547
2548 r = -EFAULT;
2549 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2550 goto out;
2551
2552 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2553 ioctl);
2554 if (r)
2555 goto out;
2556
2557 r = -EFAULT;
2558 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2559 goto out;
2560 r = 0;
2561 break;
2562 }
2563 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2564 u64 mce_cap;
2565
2566 mce_cap = KVM_MCE_CAP_SUPPORTED;
2567 r = -EFAULT;
2568 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2569 goto out;
2570 r = 0;
2571 break;
2572 }
2573 default:
2574 r = -EINVAL;
2575 }
2576 out:
2577 return r;
2578 }
2579
2580 static void wbinvd_ipi(void *garbage)
2581 {
2582 wbinvd();
2583 }
2584
2585 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2586 {
2587 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2588 }
2589
2590 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2591 {
2592 /* Address WBINVD may be executed by guest */
2593 if (need_emulate_wbinvd(vcpu)) {
2594 if (kvm_x86_ops->has_wbinvd_exit())
2595 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2596 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2597 smp_call_function_single(vcpu->cpu,
2598 wbinvd_ipi, NULL, 1);
2599 }
2600
2601 kvm_x86_ops->vcpu_load(vcpu, cpu);
2602
2603 /* Apply any externally detected TSC adjustments (due to suspend) */
2604 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2605 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2606 vcpu->arch.tsc_offset_adjustment = 0;
2607 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2608 }
2609
2610 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2611 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2612 rdtsc() - vcpu->arch.last_host_tsc;
2613 if (tsc_delta < 0)
2614 mark_tsc_unstable("KVM discovered backwards TSC");
2615 if (check_tsc_unstable()) {
2616 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2617 vcpu->arch.last_guest_tsc);
2618 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2619 vcpu->arch.tsc_catchup = 1;
2620 }
2621 /*
2622 * On a host with synchronized TSC, there is no need to update
2623 * kvmclock on vcpu->cpu migration
2624 */
2625 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2626 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2627 if (vcpu->cpu != cpu)
2628 kvm_migrate_timers(vcpu);
2629 vcpu->cpu = cpu;
2630 }
2631
2632 accumulate_steal_time(vcpu);
2633 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2634 }
2635
2636 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2637 {
2638 kvm_x86_ops->vcpu_put(vcpu);
2639 kvm_put_guest_fpu(vcpu);
2640 vcpu->arch.last_host_tsc = rdtsc();
2641 }
2642
2643 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2644 struct kvm_lapic_state *s)
2645 {
2646 kvm_x86_ops->sync_pir_to_irr(vcpu);
2647 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2648
2649 return 0;
2650 }
2651
2652 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2653 struct kvm_lapic_state *s)
2654 {
2655 kvm_apic_post_state_restore(vcpu, s);
2656 update_cr8_intercept(vcpu);
2657
2658 return 0;
2659 }
2660
2661 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2662 struct kvm_interrupt *irq)
2663 {
2664 if (irq->irq >= KVM_NR_INTERRUPTS)
2665 return -EINVAL;
2666
2667 if (!irqchip_in_kernel(vcpu->kvm)) {
2668 kvm_queue_interrupt(vcpu, irq->irq, false);
2669 kvm_make_request(KVM_REQ_EVENT, vcpu);
2670 return 0;
2671 }
2672
2673 /*
2674 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2675 * fail for in-kernel 8259.
2676 */
2677 if (pic_in_kernel(vcpu->kvm))
2678 return -ENXIO;
2679
2680 if (vcpu->arch.pending_external_vector != -1)
2681 return -EEXIST;
2682
2683 vcpu->arch.pending_external_vector = irq->irq;
2684 return 0;
2685 }
2686
2687 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2688 {
2689 kvm_inject_nmi(vcpu);
2690
2691 return 0;
2692 }
2693
2694 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2695 {
2696 kvm_make_request(KVM_REQ_SMI, vcpu);
2697
2698 return 0;
2699 }
2700
2701 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2702 struct kvm_tpr_access_ctl *tac)
2703 {
2704 if (tac->flags)
2705 return -EINVAL;
2706 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2707 return 0;
2708 }
2709
2710 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2711 u64 mcg_cap)
2712 {
2713 int r;
2714 unsigned bank_num = mcg_cap & 0xff, bank;
2715
2716 r = -EINVAL;
2717 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2718 goto out;
2719 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2720 goto out;
2721 r = 0;
2722 vcpu->arch.mcg_cap = mcg_cap;
2723 /* Init IA32_MCG_CTL to all 1s */
2724 if (mcg_cap & MCG_CTL_P)
2725 vcpu->arch.mcg_ctl = ~(u64)0;
2726 /* Init IA32_MCi_CTL to all 1s */
2727 for (bank = 0; bank < bank_num; bank++)
2728 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2729 out:
2730 return r;
2731 }
2732
2733 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2734 struct kvm_x86_mce *mce)
2735 {
2736 u64 mcg_cap = vcpu->arch.mcg_cap;
2737 unsigned bank_num = mcg_cap & 0xff;
2738 u64 *banks = vcpu->arch.mce_banks;
2739
2740 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2741 return -EINVAL;
2742 /*
2743 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2744 * reporting is disabled
2745 */
2746 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2747 vcpu->arch.mcg_ctl != ~(u64)0)
2748 return 0;
2749 banks += 4 * mce->bank;
2750 /*
2751 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2752 * reporting is disabled for the bank
2753 */
2754 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2755 return 0;
2756 if (mce->status & MCI_STATUS_UC) {
2757 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2758 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2759 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2760 return 0;
2761 }
2762 if (banks[1] & MCI_STATUS_VAL)
2763 mce->status |= MCI_STATUS_OVER;
2764 banks[2] = mce->addr;
2765 banks[3] = mce->misc;
2766 vcpu->arch.mcg_status = mce->mcg_status;
2767 banks[1] = mce->status;
2768 kvm_queue_exception(vcpu, MC_VECTOR);
2769 } else if (!(banks[1] & MCI_STATUS_VAL)
2770 || !(banks[1] & MCI_STATUS_UC)) {
2771 if (banks[1] & MCI_STATUS_VAL)
2772 mce->status |= MCI_STATUS_OVER;
2773 banks[2] = mce->addr;
2774 banks[3] = mce->misc;
2775 banks[1] = mce->status;
2776 } else
2777 banks[1] |= MCI_STATUS_OVER;
2778 return 0;
2779 }
2780
2781 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2782 struct kvm_vcpu_events *events)
2783 {
2784 process_nmi(vcpu);
2785 events->exception.injected =
2786 vcpu->arch.exception.pending &&
2787 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2788 events->exception.nr = vcpu->arch.exception.nr;
2789 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2790 events->exception.pad = 0;
2791 events->exception.error_code = vcpu->arch.exception.error_code;
2792
2793 events->interrupt.injected =
2794 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2795 events->interrupt.nr = vcpu->arch.interrupt.nr;
2796 events->interrupt.soft = 0;
2797 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2798
2799 events->nmi.injected = vcpu->arch.nmi_injected;
2800 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2801 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2802 events->nmi.pad = 0;
2803
2804 events->sipi_vector = 0; /* never valid when reporting to user space */
2805
2806 events->smi.smm = is_smm(vcpu);
2807 events->smi.pending = vcpu->arch.smi_pending;
2808 events->smi.smm_inside_nmi =
2809 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2810 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2811
2812 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2813 | KVM_VCPUEVENT_VALID_SHADOW
2814 | KVM_VCPUEVENT_VALID_SMM);
2815 memset(&events->reserved, 0, sizeof(events->reserved));
2816 }
2817
2818 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2819 struct kvm_vcpu_events *events)
2820 {
2821 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2822 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2823 | KVM_VCPUEVENT_VALID_SHADOW
2824 | KVM_VCPUEVENT_VALID_SMM))
2825 return -EINVAL;
2826
2827 process_nmi(vcpu);
2828 vcpu->arch.exception.pending = events->exception.injected;
2829 vcpu->arch.exception.nr = events->exception.nr;
2830 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2831 vcpu->arch.exception.error_code = events->exception.error_code;
2832
2833 vcpu->arch.interrupt.pending = events->interrupt.injected;
2834 vcpu->arch.interrupt.nr = events->interrupt.nr;
2835 vcpu->arch.interrupt.soft = events->interrupt.soft;
2836 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2837 kvm_x86_ops->set_interrupt_shadow(vcpu,
2838 events->interrupt.shadow);
2839
2840 vcpu->arch.nmi_injected = events->nmi.injected;
2841 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2842 vcpu->arch.nmi_pending = events->nmi.pending;
2843 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2844
2845 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2846 kvm_vcpu_has_lapic(vcpu))
2847 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2848
2849 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2850 if (events->smi.smm)
2851 vcpu->arch.hflags |= HF_SMM_MASK;
2852 else
2853 vcpu->arch.hflags &= ~HF_SMM_MASK;
2854 vcpu->arch.smi_pending = events->smi.pending;
2855 if (events->smi.smm_inside_nmi)
2856 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2857 else
2858 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2859 if (kvm_vcpu_has_lapic(vcpu)) {
2860 if (events->smi.latched_init)
2861 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2862 else
2863 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 }
2865 }
2866
2867 kvm_make_request(KVM_REQ_EVENT, vcpu);
2868
2869 return 0;
2870 }
2871
2872 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2873 struct kvm_debugregs *dbgregs)
2874 {
2875 unsigned long val;
2876
2877 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2878 kvm_get_dr(vcpu, 6, &val);
2879 dbgregs->dr6 = val;
2880 dbgregs->dr7 = vcpu->arch.dr7;
2881 dbgregs->flags = 0;
2882 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2883 }
2884
2885 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2886 struct kvm_debugregs *dbgregs)
2887 {
2888 if (dbgregs->flags)
2889 return -EINVAL;
2890
2891 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2892 kvm_update_dr0123(vcpu);
2893 vcpu->arch.dr6 = dbgregs->dr6;
2894 kvm_update_dr6(vcpu);
2895 vcpu->arch.dr7 = dbgregs->dr7;
2896 kvm_update_dr7(vcpu);
2897
2898 return 0;
2899 }
2900
2901 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2902
2903 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2904 {
2905 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2906 u64 xstate_bv = xsave->header.xfeatures;
2907 u64 valid;
2908
2909 /*
2910 * Copy legacy XSAVE area, to avoid complications with CPUID
2911 * leaves 0 and 1 in the loop below.
2912 */
2913 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2914
2915 /* Set XSTATE_BV */
2916 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2917
2918 /*
2919 * Copy each region from the possibly compacted offset to the
2920 * non-compacted offset.
2921 */
2922 valid = xstate_bv & ~XSTATE_FPSSE;
2923 while (valid) {
2924 u64 feature = valid & -valid;
2925 int index = fls64(feature) - 1;
2926 void *src = get_xsave_addr(xsave, feature);
2927
2928 if (src) {
2929 u32 size, offset, ecx, edx;
2930 cpuid_count(XSTATE_CPUID, index,
2931 &size, &offset, &ecx, &edx);
2932 memcpy(dest + offset, src, size);
2933 }
2934
2935 valid -= feature;
2936 }
2937 }
2938
2939 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2940 {
2941 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2942 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2943 u64 valid;
2944
2945 /*
2946 * Copy legacy XSAVE area, to avoid complications with CPUID
2947 * leaves 0 and 1 in the loop below.
2948 */
2949 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2950
2951 /* Set XSTATE_BV and possibly XCOMP_BV. */
2952 xsave->header.xfeatures = xstate_bv;
2953 if (cpu_has_xsaves)
2954 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2955
2956 /*
2957 * Copy each region from the non-compacted offset to the
2958 * possibly compacted offset.
2959 */
2960 valid = xstate_bv & ~XSTATE_FPSSE;
2961 while (valid) {
2962 u64 feature = valid & -valid;
2963 int index = fls64(feature) - 1;
2964 void *dest = get_xsave_addr(xsave, feature);
2965
2966 if (dest) {
2967 u32 size, offset, ecx, edx;
2968 cpuid_count(XSTATE_CPUID, index,
2969 &size, &offset, &ecx, &edx);
2970 memcpy(dest, src + offset, size);
2971 }
2972
2973 valid -= feature;
2974 }
2975 }
2976
2977 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2978 struct kvm_xsave *guest_xsave)
2979 {
2980 if (cpu_has_xsave) {
2981 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2982 fill_xsave((u8 *) guest_xsave->region, vcpu);
2983 } else {
2984 memcpy(guest_xsave->region,
2985 &vcpu->arch.guest_fpu.state.fxsave,
2986 sizeof(struct fxregs_state));
2987 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2988 XSTATE_FPSSE;
2989 }
2990 }
2991
2992 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2993 struct kvm_xsave *guest_xsave)
2994 {
2995 u64 xstate_bv =
2996 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2997
2998 if (cpu_has_xsave) {
2999 /*
3000 * Here we allow setting states that are not present in
3001 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3002 * with old userspace.
3003 */
3004 if (xstate_bv & ~kvm_supported_xcr0())
3005 return -EINVAL;
3006 load_xsave(vcpu, (u8 *)guest_xsave->region);
3007 } else {
3008 if (xstate_bv & ~XSTATE_FPSSE)
3009 return -EINVAL;
3010 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3011 guest_xsave->region, sizeof(struct fxregs_state));
3012 }
3013 return 0;
3014 }
3015
3016 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3017 struct kvm_xcrs *guest_xcrs)
3018 {
3019 if (!cpu_has_xsave) {
3020 guest_xcrs->nr_xcrs = 0;
3021 return;
3022 }
3023
3024 guest_xcrs->nr_xcrs = 1;
3025 guest_xcrs->flags = 0;
3026 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3027 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3028 }
3029
3030 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3031 struct kvm_xcrs *guest_xcrs)
3032 {
3033 int i, r = 0;
3034
3035 if (!cpu_has_xsave)
3036 return -EINVAL;
3037
3038 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3039 return -EINVAL;
3040
3041 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3042 /* Only support XCR0 currently */
3043 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3044 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3045 guest_xcrs->xcrs[i].value);
3046 break;
3047 }
3048 if (r)
3049 r = -EINVAL;
3050 return r;
3051 }
3052
3053 /*
3054 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3055 * stopped by the hypervisor. This function will be called from the host only.
3056 * EINVAL is returned when the host attempts to set the flag for a guest that
3057 * does not support pv clocks.
3058 */
3059 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3060 {
3061 if (!vcpu->arch.pv_time_enabled)
3062 return -EINVAL;
3063 vcpu->arch.pvclock_set_guest_stopped_request = true;
3064 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3065 return 0;
3066 }
3067
3068 long kvm_arch_vcpu_ioctl(struct file *filp,
3069 unsigned int ioctl, unsigned long arg)
3070 {
3071 struct kvm_vcpu *vcpu = filp->private_data;
3072 void __user *argp = (void __user *)arg;
3073 int r;
3074 union {
3075 struct kvm_lapic_state *lapic;
3076 struct kvm_xsave *xsave;
3077 struct kvm_xcrs *xcrs;
3078 void *buffer;
3079 } u;
3080
3081 u.buffer = NULL;
3082 switch (ioctl) {
3083 case KVM_GET_LAPIC: {
3084 r = -EINVAL;
3085 if (!vcpu->arch.apic)
3086 goto out;
3087 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3088
3089 r = -ENOMEM;
3090 if (!u.lapic)
3091 goto out;
3092 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3093 if (r)
3094 goto out;
3095 r = -EFAULT;
3096 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3097 goto out;
3098 r = 0;
3099 break;
3100 }
3101 case KVM_SET_LAPIC: {
3102 r = -EINVAL;
3103 if (!vcpu->arch.apic)
3104 goto out;
3105 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3106 if (IS_ERR(u.lapic))
3107 return PTR_ERR(u.lapic);
3108
3109 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3110 break;
3111 }
3112 case KVM_INTERRUPT: {
3113 struct kvm_interrupt irq;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&irq, argp, sizeof irq))
3117 goto out;
3118 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3119 break;
3120 }
3121 case KVM_NMI: {
3122 r = kvm_vcpu_ioctl_nmi(vcpu);
3123 break;
3124 }
3125 case KVM_SMI: {
3126 r = kvm_vcpu_ioctl_smi(vcpu);
3127 break;
3128 }
3129 case KVM_SET_CPUID: {
3130 struct kvm_cpuid __user *cpuid_arg = argp;
3131 struct kvm_cpuid cpuid;
3132
3133 r = -EFAULT;
3134 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3135 goto out;
3136 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3137 break;
3138 }
3139 case KVM_SET_CPUID2: {
3140 struct kvm_cpuid2 __user *cpuid_arg = argp;
3141 struct kvm_cpuid2 cpuid;
3142
3143 r = -EFAULT;
3144 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3145 goto out;
3146 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3147 cpuid_arg->entries);
3148 break;
3149 }
3150 case KVM_GET_CPUID2: {
3151 struct kvm_cpuid2 __user *cpuid_arg = argp;
3152 struct kvm_cpuid2 cpuid;
3153
3154 r = -EFAULT;
3155 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3156 goto out;
3157 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3158 cpuid_arg->entries);
3159 if (r)
3160 goto out;
3161 r = -EFAULT;
3162 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3163 goto out;
3164 r = 0;
3165 break;
3166 }
3167 case KVM_GET_MSRS:
3168 r = msr_io(vcpu, argp, do_get_msr, 1);
3169 break;
3170 case KVM_SET_MSRS:
3171 r = msr_io(vcpu, argp, do_set_msr, 0);
3172 break;
3173 case KVM_TPR_ACCESS_REPORTING: {
3174 struct kvm_tpr_access_ctl tac;
3175
3176 r = -EFAULT;
3177 if (copy_from_user(&tac, argp, sizeof tac))
3178 goto out;
3179 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3180 if (r)
3181 goto out;
3182 r = -EFAULT;
3183 if (copy_to_user(argp, &tac, sizeof tac))
3184 goto out;
3185 r = 0;
3186 break;
3187 };
3188 case KVM_SET_VAPIC_ADDR: {
3189 struct kvm_vapic_addr va;
3190
3191 r = -EINVAL;
3192 if (!lapic_in_kernel(vcpu))
3193 goto out;
3194 r = -EFAULT;
3195 if (copy_from_user(&va, argp, sizeof va))
3196 goto out;
3197 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3198 break;
3199 }
3200 case KVM_X86_SETUP_MCE: {
3201 u64 mcg_cap;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3205 goto out;
3206 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3207 break;
3208 }
3209 case KVM_X86_SET_MCE: {
3210 struct kvm_x86_mce mce;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&mce, argp, sizeof mce))
3214 goto out;
3215 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3216 break;
3217 }
3218 case KVM_GET_VCPU_EVENTS: {
3219 struct kvm_vcpu_events events;
3220
3221 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3222
3223 r = -EFAULT;
3224 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3225 break;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_SET_VCPU_EVENTS: {
3230 struct kvm_vcpu_events events;
3231
3232 r = -EFAULT;
3233 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3234 break;
3235
3236 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3237 break;
3238 }
3239 case KVM_GET_DEBUGREGS: {
3240 struct kvm_debugregs dbgregs;
3241
3242 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3243
3244 r = -EFAULT;
3245 if (copy_to_user(argp, &dbgregs,
3246 sizeof(struct kvm_debugregs)))
3247 break;
3248 r = 0;
3249 break;
3250 }
3251 case KVM_SET_DEBUGREGS: {
3252 struct kvm_debugregs dbgregs;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&dbgregs, argp,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258
3259 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3260 break;
3261 }
3262 case KVM_GET_XSAVE: {
3263 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3264 r = -ENOMEM;
3265 if (!u.xsave)
3266 break;
3267
3268 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3269
3270 r = -EFAULT;
3271 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3272 break;
3273 r = 0;
3274 break;
3275 }
3276 case KVM_SET_XSAVE: {
3277 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3278 if (IS_ERR(u.xsave))
3279 return PTR_ERR(u.xsave);
3280
3281 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3282 break;
3283 }
3284 case KVM_GET_XCRS: {
3285 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3286 r = -ENOMEM;
3287 if (!u.xcrs)
3288 break;
3289
3290 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3291
3292 r = -EFAULT;
3293 if (copy_to_user(argp, u.xcrs,
3294 sizeof(struct kvm_xcrs)))
3295 break;
3296 r = 0;
3297 break;
3298 }
3299 case KVM_SET_XCRS: {
3300 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3301 if (IS_ERR(u.xcrs))
3302 return PTR_ERR(u.xcrs);
3303
3304 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3305 break;
3306 }
3307 case KVM_SET_TSC_KHZ: {
3308 u32 user_tsc_khz;
3309
3310 r = -EINVAL;
3311 user_tsc_khz = (u32)arg;
3312
3313 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3314 goto out;
3315
3316 if (user_tsc_khz == 0)
3317 user_tsc_khz = tsc_khz;
3318
3319 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3320
3321 r = 0;
3322 goto out;
3323 }
3324 case KVM_GET_TSC_KHZ: {
3325 r = vcpu->arch.virtual_tsc_khz;
3326 goto out;
3327 }
3328 case KVM_KVMCLOCK_CTRL: {
3329 r = kvm_set_guest_paused(vcpu);
3330 goto out;
3331 }
3332 default:
3333 r = -EINVAL;
3334 }
3335 out:
3336 kfree(u.buffer);
3337 return r;
3338 }
3339
3340 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3341 {
3342 return VM_FAULT_SIGBUS;
3343 }
3344
3345 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3346 {
3347 int ret;
3348
3349 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3350 return -EINVAL;
3351 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3352 return ret;
3353 }
3354
3355 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3356 u64 ident_addr)
3357 {
3358 kvm->arch.ept_identity_map_addr = ident_addr;
3359 return 0;
3360 }
3361
3362 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3363 u32 kvm_nr_mmu_pages)
3364 {
3365 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3366 return -EINVAL;
3367
3368 mutex_lock(&kvm->slots_lock);
3369
3370 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3371 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3372
3373 mutex_unlock(&kvm->slots_lock);
3374 return 0;
3375 }
3376
3377 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3378 {
3379 return kvm->arch.n_max_mmu_pages;
3380 }
3381
3382 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3383 {
3384 int r;
3385
3386 r = 0;
3387 switch (chip->chip_id) {
3388 case KVM_IRQCHIP_PIC_MASTER:
3389 memcpy(&chip->chip.pic,
3390 &pic_irqchip(kvm)->pics[0],
3391 sizeof(struct kvm_pic_state));
3392 break;
3393 case KVM_IRQCHIP_PIC_SLAVE:
3394 memcpy(&chip->chip.pic,
3395 &pic_irqchip(kvm)->pics[1],
3396 sizeof(struct kvm_pic_state));
3397 break;
3398 case KVM_IRQCHIP_IOAPIC:
3399 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3400 break;
3401 default:
3402 r = -EINVAL;
3403 break;
3404 }
3405 return r;
3406 }
3407
3408 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3409 {
3410 int r;
3411
3412 r = 0;
3413 switch (chip->chip_id) {
3414 case KVM_IRQCHIP_PIC_MASTER:
3415 spin_lock(&pic_irqchip(kvm)->lock);
3416 memcpy(&pic_irqchip(kvm)->pics[0],
3417 &chip->chip.pic,
3418 sizeof(struct kvm_pic_state));
3419 spin_unlock(&pic_irqchip(kvm)->lock);
3420 break;
3421 case KVM_IRQCHIP_PIC_SLAVE:
3422 spin_lock(&pic_irqchip(kvm)->lock);
3423 memcpy(&pic_irqchip(kvm)->pics[1],
3424 &chip->chip.pic,
3425 sizeof(struct kvm_pic_state));
3426 spin_unlock(&pic_irqchip(kvm)->lock);
3427 break;
3428 case KVM_IRQCHIP_IOAPIC:
3429 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3430 break;
3431 default:
3432 r = -EINVAL;
3433 break;
3434 }
3435 kvm_pic_update_irq(pic_irqchip(kvm));
3436 return r;
3437 }
3438
3439 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3440 {
3441 int r = 0;
3442
3443 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3444 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3445 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3446 return r;
3447 }
3448
3449 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450 {
3451 int r = 0;
3452
3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3454 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3455 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3456 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3457 return r;
3458 }
3459
3460 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461 {
3462 int r = 0;
3463
3464 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3465 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3466 sizeof(ps->channels));
3467 ps->flags = kvm->arch.vpit->pit_state.flags;
3468 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3469 memset(&ps->reserved, 0, sizeof(ps->reserved));
3470 return r;
3471 }
3472
3473 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3474 {
3475 int r = 0, start = 0;
3476 u32 prev_legacy, cur_legacy;
3477 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3478 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3479 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3480 if (!prev_legacy && cur_legacy)
3481 start = 1;
3482 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3483 sizeof(kvm->arch.vpit->pit_state.channels));
3484 kvm->arch.vpit->pit_state.flags = ps->flags;
3485 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3486 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3487 return r;
3488 }
3489
3490 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3491 struct kvm_reinject_control *control)
3492 {
3493 if (!kvm->arch.vpit)
3494 return -ENXIO;
3495 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3496 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3497 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3498 return 0;
3499 }
3500
3501 /**
3502 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3503 * @kvm: kvm instance
3504 * @log: slot id and address to which we copy the log
3505 *
3506 * Steps 1-4 below provide general overview of dirty page logging. See
3507 * kvm_get_dirty_log_protect() function description for additional details.
3508 *
3509 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3510 * always flush the TLB (step 4) even if previous step failed and the dirty
3511 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3512 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3513 * writes will be marked dirty for next log read.
3514 *
3515 * 1. Take a snapshot of the bit and clear it if needed.
3516 * 2. Write protect the corresponding page.
3517 * 3. Copy the snapshot to the userspace.
3518 * 4. Flush TLB's if needed.
3519 */
3520 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3521 {
3522 bool is_dirty = false;
3523 int r;
3524
3525 mutex_lock(&kvm->slots_lock);
3526
3527 /*
3528 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3529 */
3530 if (kvm_x86_ops->flush_log_dirty)
3531 kvm_x86_ops->flush_log_dirty(kvm);
3532
3533 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3534
3535 /*
3536 * All the TLBs can be flushed out of mmu lock, see the comments in
3537 * kvm_mmu_slot_remove_write_access().
3538 */
3539 lockdep_assert_held(&kvm->slots_lock);
3540 if (is_dirty)
3541 kvm_flush_remote_tlbs(kvm);
3542
3543 mutex_unlock(&kvm->slots_lock);
3544 return r;
3545 }
3546
3547 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3548 bool line_status)
3549 {
3550 if (!irqchip_in_kernel(kvm))
3551 return -ENXIO;
3552
3553 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3554 irq_event->irq, irq_event->level,
3555 line_status);
3556 return 0;
3557 }
3558
3559 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3560 struct kvm_enable_cap *cap)
3561 {
3562 int r;
3563
3564 if (cap->flags)
3565 return -EINVAL;
3566
3567 switch (cap->cap) {
3568 case KVM_CAP_DISABLE_QUIRKS:
3569 kvm->arch.disabled_quirks = cap->args[0];
3570 r = 0;
3571 break;
3572 case KVM_CAP_SPLIT_IRQCHIP: {
3573 mutex_lock(&kvm->lock);
3574 r = -EINVAL;
3575 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3576 goto split_irqchip_unlock;
3577 r = -EEXIST;
3578 if (irqchip_in_kernel(kvm))
3579 goto split_irqchip_unlock;
3580 if (atomic_read(&kvm->online_vcpus))
3581 goto split_irqchip_unlock;
3582 r = kvm_setup_empty_irq_routing(kvm);
3583 if (r)
3584 goto split_irqchip_unlock;
3585 /* Pairs with irqchip_in_kernel. */
3586 smp_wmb();
3587 kvm->arch.irqchip_split = true;
3588 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3589 r = 0;
3590 split_irqchip_unlock:
3591 mutex_unlock(&kvm->lock);
3592 break;
3593 }
3594 default:
3595 r = -EINVAL;
3596 break;
3597 }
3598 return r;
3599 }
3600
3601 long kvm_arch_vm_ioctl(struct file *filp,
3602 unsigned int ioctl, unsigned long arg)
3603 {
3604 struct kvm *kvm = filp->private_data;
3605 void __user *argp = (void __user *)arg;
3606 int r = -ENOTTY;
3607 /*
3608 * This union makes it completely explicit to gcc-3.x
3609 * that these two variables' stack usage should be
3610 * combined, not added together.
3611 */
3612 union {
3613 struct kvm_pit_state ps;
3614 struct kvm_pit_state2 ps2;
3615 struct kvm_pit_config pit_config;
3616 } u;
3617
3618 switch (ioctl) {
3619 case KVM_SET_TSS_ADDR:
3620 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3621 break;
3622 case KVM_SET_IDENTITY_MAP_ADDR: {
3623 u64 ident_addr;
3624
3625 r = -EFAULT;
3626 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3627 goto out;
3628 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3629 break;
3630 }
3631 case KVM_SET_NR_MMU_PAGES:
3632 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3633 break;
3634 case KVM_GET_NR_MMU_PAGES:
3635 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3636 break;
3637 case KVM_CREATE_IRQCHIP: {
3638 struct kvm_pic *vpic;
3639
3640 mutex_lock(&kvm->lock);
3641 r = -EEXIST;
3642 if (kvm->arch.vpic)
3643 goto create_irqchip_unlock;
3644 r = -EINVAL;
3645 if (atomic_read(&kvm->online_vcpus))
3646 goto create_irqchip_unlock;
3647 r = -ENOMEM;
3648 vpic = kvm_create_pic(kvm);
3649 if (vpic) {
3650 r = kvm_ioapic_init(kvm);
3651 if (r) {
3652 mutex_lock(&kvm->slots_lock);
3653 kvm_destroy_pic(vpic);
3654 mutex_unlock(&kvm->slots_lock);
3655 goto create_irqchip_unlock;
3656 }
3657 } else
3658 goto create_irqchip_unlock;
3659 r = kvm_setup_default_irq_routing(kvm);
3660 if (r) {
3661 mutex_lock(&kvm->slots_lock);
3662 mutex_lock(&kvm->irq_lock);
3663 kvm_ioapic_destroy(kvm);
3664 kvm_destroy_pic(vpic);
3665 mutex_unlock(&kvm->irq_lock);
3666 mutex_unlock(&kvm->slots_lock);
3667 goto create_irqchip_unlock;
3668 }
3669 /* Write kvm->irq_routing before kvm->arch.vpic. */
3670 smp_wmb();
3671 kvm->arch.vpic = vpic;
3672 create_irqchip_unlock:
3673 mutex_unlock(&kvm->lock);
3674 break;
3675 }
3676 case KVM_CREATE_PIT:
3677 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3678 goto create_pit;
3679 case KVM_CREATE_PIT2:
3680 r = -EFAULT;
3681 if (copy_from_user(&u.pit_config, argp,
3682 sizeof(struct kvm_pit_config)))
3683 goto out;
3684 create_pit:
3685 mutex_lock(&kvm->slots_lock);
3686 r = -EEXIST;
3687 if (kvm->arch.vpit)
3688 goto create_pit_unlock;
3689 r = -ENOMEM;
3690 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3691 if (kvm->arch.vpit)
3692 r = 0;
3693 create_pit_unlock:
3694 mutex_unlock(&kvm->slots_lock);
3695 break;
3696 case KVM_GET_IRQCHIP: {
3697 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3698 struct kvm_irqchip *chip;
3699
3700 chip = memdup_user(argp, sizeof(*chip));
3701 if (IS_ERR(chip)) {
3702 r = PTR_ERR(chip);
3703 goto out;
3704 }
3705
3706 r = -ENXIO;
3707 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3708 goto get_irqchip_out;
3709 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3710 if (r)
3711 goto get_irqchip_out;
3712 r = -EFAULT;
3713 if (copy_to_user(argp, chip, sizeof *chip))
3714 goto get_irqchip_out;
3715 r = 0;
3716 get_irqchip_out:
3717 kfree(chip);
3718 break;
3719 }
3720 case KVM_SET_IRQCHIP: {
3721 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3722 struct kvm_irqchip *chip;
3723
3724 chip = memdup_user(argp, sizeof(*chip));
3725 if (IS_ERR(chip)) {
3726 r = PTR_ERR(chip);
3727 goto out;
3728 }
3729
3730 r = -ENXIO;
3731 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3732 goto set_irqchip_out;
3733 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3734 if (r)
3735 goto set_irqchip_out;
3736 r = 0;
3737 set_irqchip_out:
3738 kfree(chip);
3739 break;
3740 }
3741 case KVM_GET_PIT: {
3742 r = -EFAULT;
3743 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3744 goto out;
3745 r = -ENXIO;
3746 if (!kvm->arch.vpit)
3747 goto out;
3748 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3749 if (r)
3750 goto out;
3751 r = -EFAULT;
3752 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3753 goto out;
3754 r = 0;
3755 break;
3756 }
3757 case KVM_SET_PIT: {
3758 r = -EFAULT;
3759 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3760 goto out;
3761 r = -ENXIO;
3762 if (!kvm->arch.vpit)
3763 goto out;
3764 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3765 break;
3766 }
3767 case KVM_GET_PIT2: {
3768 r = -ENXIO;
3769 if (!kvm->arch.vpit)
3770 goto out;
3771 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3772 if (r)
3773 goto out;
3774 r = -EFAULT;
3775 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3776 goto out;
3777 r = 0;
3778 break;
3779 }
3780 case KVM_SET_PIT2: {
3781 r = -EFAULT;
3782 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3783 goto out;
3784 r = -ENXIO;
3785 if (!kvm->arch.vpit)
3786 goto out;
3787 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3788 break;
3789 }
3790 case KVM_REINJECT_CONTROL: {
3791 struct kvm_reinject_control control;
3792 r = -EFAULT;
3793 if (copy_from_user(&control, argp, sizeof(control)))
3794 goto out;
3795 r = kvm_vm_ioctl_reinject(kvm, &control);
3796 break;
3797 }
3798 case KVM_SET_BOOT_CPU_ID:
3799 r = 0;
3800 mutex_lock(&kvm->lock);
3801 if (atomic_read(&kvm->online_vcpus) != 0)
3802 r = -EBUSY;
3803 else
3804 kvm->arch.bsp_vcpu_id = arg;
3805 mutex_unlock(&kvm->lock);
3806 break;
3807 case KVM_XEN_HVM_CONFIG: {
3808 r = -EFAULT;
3809 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3810 sizeof(struct kvm_xen_hvm_config)))
3811 goto out;
3812 r = -EINVAL;
3813 if (kvm->arch.xen_hvm_config.flags)
3814 goto out;
3815 r = 0;
3816 break;
3817 }
3818 case KVM_SET_CLOCK: {
3819 struct kvm_clock_data user_ns;
3820 u64 now_ns;
3821 s64 delta;
3822
3823 r = -EFAULT;
3824 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3825 goto out;
3826
3827 r = -EINVAL;
3828 if (user_ns.flags)
3829 goto out;
3830
3831 r = 0;
3832 local_irq_disable();
3833 now_ns = get_kernel_ns();
3834 delta = user_ns.clock - now_ns;
3835 local_irq_enable();
3836 kvm->arch.kvmclock_offset = delta;
3837 kvm_gen_update_masterclock(kvm);
3838 break;
3839 }
3840 case KVM_GET_CLOCK: {
3841 struct kvm_clock_data user_ns;
3842 u64 now_ns;
3843
3844 local_irq_disable();
3845 now_ns = get_kernel_ns();
3846 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3847 local_irq_enable();
3848 user_ns.flags = 0;
3849 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3850
3851 r = -EFAULT;
3852 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3853 goto out;
3854 r = 0;
3855 break;
3856 }
3857 case KVM_ENABLE_CAP: {
3858 struct kvm_enable_cap cap;
3859
3860 r = -EFAULT;
3861 if (copy_from_user(&cap, argp, sizeof(cap)))
3862 goto out;
3863 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3864 break;
3865 }
3866 default:
3867 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3868 }
3869 out:
3870 return r;
3871 }
3872
3873 static void kvm_init_msr_list(void)
3874 {
3875 u32 dummy[2];
3876 unsigned i, j;
3877
3878 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3879 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3880 continue;
3881
3882 /*
3883 * Even MSRs that are valid in the host may not be exposed
3884 * to the guests in some cases. We could work around this
3885 * in VMX with the generic MSR save/load machinery, but it
3886 * is not really worthwhile since it will really only
3887 * happen with nested virtualization.
3888 */
3889 switch (msrs_to_save[i]) {
3890 case MSR_IA32_BNDCFGS:
3891 if (!kvm_x86_ops->mpx_supported())
3892 continue;
3893 break;
3894 default:
3895 break;
3896 }
3897
3898 if (j < i)
3899 msrs_to_save[j] = msrs_to_save[i];
3900 j++;
3901 }
3902 num_msrs_to_save = j;
3903
3904 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3905 switch (emulated_msrs[i]) {
3906 case MSR_IA32_SMBASE:
3907 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3908 continue;
3909 break;
3910 default:
3911 break;
3912 }
3913
3914 if (j < i)
3915 emulated_msrs[j] = emulated_msrs[i];
3916 j++;
3917 }
3918 num_emulated_msrs = j;
3919 }
3920
3921 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3922 const void *v)
3923 {
3924 int handled = 0;
3925 int n;
3926
3927 do {
3928 n = min(len, 8);
3929 if (!(vcpu->arch.apic &&
3930 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3931 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3932 break;
3933 handled += n;
3934 addr += n;
3935 len -= n;
3936 v += n;
3937 } while (len);
3938
3939 return handled;
3940 }
3941
3942 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3943 {
3944 int handled = 0;
3945 int n;
3946
3947 do {
3948 n = min(len, 8);
3949 if (!(vcpu->arch.apic &&
3950 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3951 addr, n, v))
3952 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3953 break;
3954 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3955 handled += n;
3956 addr += n;
3957 len -= n;
3958 v += n;
3959 } while (len);
3960
3961 return handled;
3962 }
3963
3964 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3965 struct kvm_segment *var, int seg)
3966 {
3967 kvm_x86_ops->set_segment(vcpu, var, seg);
3968 }
3969
3970 void kvm_get_segment(struct kvm_vcpu *vcpu,
3971 struct kvm_segment *var, int seg)
3972 {
3973 kvm_x86_ops->get_segment(vcpu, var, seg);
3974 }
3975
3976 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3977 struct x86_exception *exception)
3978 {
3979 gpa_t t_gpa;
3980
3981 BUG_ON(!mmu_is_nested(vcpu));
3982
3983 /* NPT walks are always user-walks */
3984 access |= PFERR_USER_MASK;
3985 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3986
3987 return t_gpa;
3988 }
3989
3990 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3991 struct x86_exception *exception)
3992 {
3993 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3994 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3995 }
3996
3997 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3998 struct x86_exception *exception)
3999 {
4000 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4001 access |= PFERR_FETCH_MASK;
4002 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4003 }
4004
4005 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4006 struct x86_exception *exception)
4007 {
4008 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4009 access |= PFERR_WRITE_MASK;
4010 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4011 }
4012
4013 /* uses this to access any guest's mapped memory without checking CPL */
4014 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4015 struct x86_exception *exception)
4016 {
4017 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4018 }
4019
4020 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4021 struct kvm_vcpu *vcpu, u32 access,
4022 struct x86_exception *exception)
4023 {
4024 void *data = val;
4025 int r = X86EMUL_CONTINUE;
4026
4027 while (bytes) {
4028 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4029 exception);
4030 unsigned offset = addr & (PAGE_SIZE-1);
4031 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4032 int ret;
4033
4034 if (gpa == UNMAPPED_GVA)
4035 return X86EMUL_PROPAGATE_FAULT;
4036 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4037 offset, toread);
4038 if (ret < 0) {
4039 r = X86EMUL_IO_NEEDED;
4040 goto out;
4041 }
4042
4043 bytes -= toread;
4044 data += toread;
4045 addr += toread;
4046 }
4047 out:
4048 return r;
4049 }
4050
4051 /* used for instruction fetching */
4052 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4053 gva_t addr, void *val, unsigned int bytes,
4054 struct x86_exception *exception)
4055 {
4056 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4057 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4058 unsigned offset;
4059 int ret;
4060
4061 /* Inline kvm_read_guest_virt_helper for speed. */
4062 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4063 exception);
4064 if (unlikely(gpa == UNMAPPED_GVA))
4065 return X86EMUL_PROPAGATE_FAULT;
4066
4067 offset = addr & (PAGE_SIZE-1);
4068 if (WARN_ON(offset + bytes > PAGE_SIZE))
4069 bytes = (unsigned)PAGE_SIZE - offset;
4070 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4071 offset, bytes);
4072 if (unlikely(ret < 0))
4073 return X86EMUL_IO_NEEDED;
4074
4075 return X86EMUL_CONTINUE;
4076 }
4077
4078 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4079 gva_t addr, void *val, unsigned int bytes,
4080 struct x86_exception *exception)
4081 {
4082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4083 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4084
4085 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4086 exception);
4087 }
4088 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4089
4090 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4091 gva_t addr, void *val, unsigned int bytes,
4092 struct x86_exception *exception)
4093 {
4094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4095 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4096 }
4097
4098 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4099 gva_t addr, void *val,
4100 unsigned int bytes,
4101 struct x86_exception *exception)
4102 {
4103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4104 void *data = val;
4105 int r = X86EMUL_CONTINUE;
4106
4107 while (bytes) {
4108 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4109 PFERR_WRITE_MASK,
4110 exception);
4111 unsigned offset = addr & (PAGE_SIZE-1);
4112 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4113 int ret;
4114
4115 if (gpa == UNMAPPED_GVA)
4116 return X86EMUL_PROPAGATE_FAULT;
4117 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4118 if (ret < 0) {
4119 r = X86EMUL_IO_NEEDED;
4120 goto out;
4121 }
4122
4123 bytes -= towrite;
4124 data += towrite;
4125 addr += towrite;
4126 }
4127 out:
4128 return r;
4129 }
4130 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4131
4132 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4133 gpa_t *gpa, struct x86_exception *exception,
4134 bool write)
4135 {
4136 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4137 | (write ? PFERR_WRITE_MASK : 0);
4138
4139 if (vcpu_match_mmio_gva(vcpu, gva)
4140 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4141 vcpu->arch.access, access)) {
4142 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4143 (gva & (PAGE_SIZE - 1));
4144 trace_vcpu_match_mmio(gva, *gpa, write, false);
4145 return 1;
4146 }
4147
4148 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4149
4150 if (*gpa == UNMAPPED_GVA)
4151 return -1;
4152
4153 /* For APIC access vmexit */
4154 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4155 return 1;
4156
4157 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4158 trace_vcpu_match_mmio(gva, *gpa, write, true);
4159 return 1;
4160 }
4161
4162 return 0;
4163 }
4164
4165 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4166 const void *val, int bytes)
4167 {
4168 int ret;
4169
4170 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4171 if (ret < 0)
4172 return 0;
4173 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4174 return 1;
4175 }
4176
4177 struct read_write_emulator_ops {
4178 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4179 int bytes);
4180 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4181 void *val, int bytes);
4182 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4183 int bytes, void *val);
4184 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4185 void *val, int bytes);
4186 bool write;
4187 };
4188
4189 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4190 {
4191 if (vcpu->mmio_read_completed) {
4192 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4193 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4194 vcpu->mmio_read_completed = 0;
4195 return 1;
4196 }
4197
4198 return 0;
4199 }
4200
4201 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4202 void *val, int bytes)
4203 {
4204 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4205 }
4206
4207 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4208 void *val, int bytes)
4209 {
4210 return emulator_write_phys(vcpu, gpa, val, bytes);
4211 }
4212
4213 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4214 {
4215 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4216 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4217 }
4218
4219 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4220 void *val, int bytes)
4221 {
4222 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4223 return X86EMUL_IO_NEEDED;
4224 }
4225
4226 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4227 void *val, int bytes)
4228 {
4229 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4230
4231 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4232 return X86EMUL_CONTINUE;
4233 }
4234
4235 static const struct read_write_emulator_ops read_emultor = {
4236 .read_write_prepare = read_prepare,
4237 .read_write_emulate = read_emulate,
4238 .read_write_mmio = vcpu_mmio_read,
4239 .read_write_exit_mmio = read_exit_mmio,
4240 };
4241
4242 static const struct read_write_emulator_ops write_emultor = {
4243 .read_write_emulate = write_emulate,
4244 .read_write_mmio = write_mmio,
4245 .read_write_exit_mmio = write_exit_mmio,
4246 .write = true,
4247 };
4248
4249 static int emulator_read_write_onepage(unsigned long addr, void *val,
4250 unsigned int bytes,
4251 struct x86_exception *exception,
4252 struct kvm_vcpu *vcpu,
4253 const struct read_write_emulator_ops *ops)
4254 {
4255 gpa_t gpa;
4256 int handled, ret;
4257 bool write = ops->write;
4258 struct kvm_mmio_fragment *frag;
4259
4260 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4261
4262 if (ret < 0)
4263 return X86EMUL_PROPAGATE_FAULT;
4264
4265 /* For APIC access vmexit */
4266 if (ret)
4267 goto mmio;
4268
4269 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4270 return X86EMUL_CONTINUE;
4271
4272 mmio:
4273 /*
4274 * Is this MMIO handled locally?
4275 */
4276 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4277 if (handled == bytes)
4278 return X86EMUL_CONTINUE;
4279
4280 gpa += handled;
4281 bytes -= handled;
4282 val += handled;
4283
4284 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4285 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4286 frag->gpa = gpa;
4287 frag->data = val;
4288 frag->len = bytes;
4289 return X86EMUL_CONTINUE;
4290 }
4291
4292 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4293 unsigned long addr,
4294 void *val, unsigned int bytes,
4295 struct x86_exception *exception,
4296 const struct read_write_emulator_ops *ops)
4297 {
4298 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4299 gpa_t gpa;
4300 int rc;
4301
4302 if (ops->read_write_prepare &&
4303 ops->read_write_prepare(vcpu, val, bytes))
4304 return X86EMUL_CONTINUE;
4305
4306 vcpu->mmio_nr_fragments = 0;
4307
4308 /* Crossing a page boundary? */
4309 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4310 int now;
4311
4312 now = -addr & ~PAGE_MASK;
4313 rc = emulator_read_write_onepage(addr, val, now, exception,
4314 vcpu, ops);
4315
4316 if (rc != X86EMUL_CONTINUE)
4317 return rc;
4318 addr += now;
4319 if (ctxt->mode != X86EMUL_MODE_PROT64)
4320 addr = (u32)addr;
4321 val += now;
4322 bytes -= now;
4323 }
4324
4325 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4326 vcpu, ops);
4327 if (rc != X86EMUL_CONTINUE)
4328 return rc;
4329
4330 if (!vcpu->mmio_nr_fragments)
4331 return rc;
4332
4333 gpa = vcpu->mmio_fragments[0].gpa;
4334
4335 vcpu->mmio_needed = 1;
4336 vcpu->mmio_cur_fragment = 0;
4337
4338 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4339 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4340 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4341 vcpu->run->mmio.phys_addr = gpa;
4342
4343 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4344 }
4345
4346 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4347 unsigned long addr,
4348 void *val,
4349 unsigned int bytes,
4350 struct x86_exception *exception)
4351 {
4352 return emulator_read_write(ctxt, addr, val, bytes,
4353 exception, &read_emultor);
4354 }
4355
4356 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4357 unsigned long addr,
4358 const void *val,
4359 unsigned int bytes,
4360 struct x86_exception *exception)
4361 {
4362 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4363 exception, &write_emultor);
4364 }
4365
4366 #define CMPXCHG_TYPE(t, ptr, old, new) \
4367 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4368
4369 #ifdef CONFIG_X86_64
4370 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4371 #else
4372 # define CMPXCHG64(ptr, old, new) \
4373 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4374 #endif
4375
4376 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4377 unsigned long addr,
4378 const void *old,
4379 const void *new,
4380 unsigned int bytes,
4381 struct x86_exception *exception)
4382 {
4383 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4384 gpa_t gpa;
4385 struct page *page;
4386 char *kaddr;
4387 bool exchanged;
4388
4389 /* guests cmpxchg8b have to be emulated atomically */
4390 if (bytes > 8 || (bytes & (bytes - 1)))
4391 goto emul_write;
4392
4393 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4394
4395 if (gpa == UNMAPPED_GVA ||
4396 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4397 goto emul_write;
4398
4399 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4400 goto emul_write;
4401
4402 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4403 if (is_error_page(page))
4404 goto emul_write;
4405
4406 kaddr = kmap_atomic(page);
4407 kaddr += offset_in_page(gpa);
4408 switch (bytes) {
4409 case 1:
4410 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4411 break;
4412 case 2:
4413 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4414 break;
4415 case 4:
4416 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4417 break;
4418 case 8:
4419 exchanged = CMPXCHG64(kaddr, old, new);
4420 break;
4421 default:
4422 BUG();
4423 }
4424 kunmap_atomic(kaddr);
4425 kvm_release_page_dirty(page);
4426
4427 if (!exchanged)
4428 return X86EMUL_CMPXCHG_FAILED;
4429
4430 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4431 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4432
4433 return X86EMUL_CONTINUE;
4434
4435 emul_write:
4436 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4437
4438 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4439 }
4440
4441 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4442 {
4443 /* TODO: String I/O for in kernel device */
4444 int r;
4445
4446 if (vcpu->arch.pio.in)
4447 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4448 vcpu->arch.pio.size, pd);
4449 else
4450 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4451 vcpu->arch.pio.port, vcpu->arch.pio.size,
4452 pd);
4453 return r;
4454 }
4455
4456 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4457 unsigned short port, void *val,
4458 unsigned int count, bool in)
4459 {
4460 vcpu->arch.pio.port = port;
4461 vcpu->arch.pio.in = in;
4462 vcpu->arch.pio.count = count;
4463 vcpu->arch.pio.size = size;
4464
4465 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4466 vcpu->arch.pio.count = 0;
4467 return 1;
4468 }
4469
4470 vcpu->run->exit_reason = KVM_EXIT_IO;
4471 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4472 vcpu->run->io.size = size;
4473 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4474 vcpu->run->io.count = count;
4475 vcpu->run->io.port = port;
4476
4477 return 0;
4478 }
4479
4480 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4481 int size, unsigned short port, void *val,
4482 unsigned int count)
4483 {
4484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4485 int ret;
4486
4487 if (vcpu->arch.pio.count)
4488 goto data_avail;
4489
4490 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4491 if (ret) {
4492 data_avail:
4493 memcpy(val, vcpu->arch.pio_data, size * count);
4494 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4495 vcpu->arch.pio.count = 0;
4496 return 1;
4497 }
4498
4499 return 0;
4500 }
4501
4502 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4503 int size, unsigned short port,
4504 const void *val, unsigned int count)
4505 {
4506 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4507
4508 memcpy(vcpu->arch.pio_data, val, size * count);
4509 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4510 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4511 }
4512
4513 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4514 {
4515 return kvm_x86_ops->get_segment_base(vcpu, seg);
4516 }
4517
4518 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4519 {
4520 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4521 }
4522
4523 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4524 {
4525 if (!need_emulate_wbinvd(vcpu))
4526 return X86EMUL_CONTINUE;
4527
4528 if (kvm_x86_ops->has_wbinvd_exit()) {
4529 int cpu = get_cpu();
4530
4531 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4532 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4533 wbinvd_ipi, NULL, 1);
4534 put_cpu();
4535 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4536 } else
4537 wbinvd();
4538 return X86EMUL_CONTINUE;
4539 }
4540
4541 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4542 {
4543 kvm_x86_ops->skip_emulated_instruction(vcpu);
4544 return kvm_emulate_wbinvd_noskip(vcpu);
4545 }
4546 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4547
4548
4549
4550 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4551 {
4552 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4553 }
4554
4555 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4556 unsigned long *dest)
4557 {
4558 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4559 }
4560
4561 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4562 unsigned long value)
4563 {
4564
4565 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4566 }
4567
4568 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4569 {
4570 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4571 }
4572
4573 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4574 {
4575 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4576 unsigned long value;
4577
4578 switch (cr) {
4579 case 0:
4580 value = kvm_read_cr0(vcpu);
4581 break;
4582 case 2:
4583 value = vcpu->arch.cr2;
4584 break;
4585 case 3:
4586 value = kvm_read_cr3(vcpu);
4587 break;
4588 case 4:
4589 value = kvm_read_cr4(vcpu);
4590 break;
4591 case 8:
4592 value = kvm_get_cr8(vcpu);
4593 break;
4594 default:
4595 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4596 return 0;
4597 }
4598
4599 return value;
4600 }
4601
4602 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4603 {
4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4605 int res = 0;
4606
4607 switch (cr) {
4608 case 0:
4609 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4610 break;
4611 case 2:
4612 vcpu->arch.cr2 = val;
4613 break;
4614 case 3:
4615 res = kvm_set_cr3(vcpu, val);
4616 break;
4617 case 4:
4618 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4619 break;
4620 case 8:
4621 res = kvm_set_cr8(vcpu, val);
4622 break;
4623 default:
4624 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4625 res = -1;
4626 }
4627
4628 return res;
4629 }
4630
4631 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4632 {
4633 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4634 }
4635
4636 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4637 {
4638 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4639 }
4640
4641 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4642 {
4643 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4644 }
4645
4646 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4647 {
4648 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4649 }
4650
4651 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4652 {
4653 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4654 }
4655
4656 static unsigned long emulator_get_cached_segment_base(
4657 struct x86_emulate_ctxt *ctxt, int seg)
4658 {
4659 return get_segment_base(emul_to_vcpu(ctxt), seg);
4660 }
4661
4662 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4663 struct desc_struct *desc, u32 *base3,
4664 int seg)
4665 {
4666 struct kvm_segment var;
4667
4668 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4669 *selector = var.selector;
4670
4671 if (var.unusable) {
4672 memset(desc, 0, sizeof(*desc));
4673 return false;
4674 }
4675
4676 if (var.g)
4677 var.limit >>= 12;
4678 set_desc_limit(desc, var.limit);
4679 set_desc_base(desc, (unsigned long)var.base);
4680 #ifdef CONFIG_X86_64
4681 if (base3)
4682 *base3 = var.base >> 32;
4683 #endif
4684 desc->type = var.type;
4685 desc->s = var.s;
4686 desc->dpl = var.dpl;
4687 desc->p = var.present;
4688 desc->avl = var.avl;
4689 desc->l = var.l;
4690 desc->d = var.db;
4691 desc->g = var.g;
4692
4693 return true;
4694 }
4695
4696 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4697 struct desc_struct *desc, u32 base3,
4698 int seg)
4699 {
4700 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4701 struct kvm_segment var;
4702
4703 var.selector = selector;
4704 var.base = get_desc_base(desc);
4705 #ifdef CONFIG_X86_64
4706 var.base |= ((u64)base3) << 32;
4707 #endif
4708 var.limit = get_desc_limit(desc);
4709 if (desc->g)
4710 var.limit = (var.limit << 12) | 0xfff;
4711 var.type = desc->type;
4712 var.dpl = desc->dpl;
4713 var.db = desc->d;
4714 var.s = desc->s;
4715 var.l = desc->l;
4716 var.g = desc->g;
4717 var.avl = desc->avl;
4718 var.present = desc->p;
4719 var.unusable = !var.present;
4720 var.padding = 0;
4721
4722 kvm_set_segment(vcpu, &var, seg);
4723 return;
4724 }
4725
4726 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4727 u32 msr_index, u64 *pdata)
4728 {
4729 struct msr_data msr;
4730 int r;
4731
4732 msr.index = msr_index;
4733 msr.host_initiated = false;
4734 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4735 if (r)
4736 return r;
4737
4738 *pdata = msr.data;
4739 return 0;
4740 }
4741
4742 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4743 u32 msr_index, u64 data)
4744 {
4745 struct msr_data msr;
4746
4747 msr.data = data;
4748 msr.index = msr_index;
4749 msr.host_initiated = false;
4750 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4751 }
4752
4753 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4754 {
4755 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4756
4757 return vcpu->arch.smbase;
4758 }
4759
4760 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4761 {
4762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4763
4764 vcpu->arch.smbase = smbase;
4765 }
4766
4767 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4768 u32 pmc)
4769 {
4770 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4771 }
4772
4773 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4774 u32 pmc, u64 *pdata)
4775 {
4776 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4777 }
4778
4779 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4780 {
4781 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4782 }
4783
4784 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4785 {
4786 preempt_disable();
4787 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4788 /*
4789 * CR0.TS may reference the host fpu state, not the guest fpu state,
4790 * so it may be clear at this point.
4791 */
4792 clts();
4793 }
4794
4795 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4796 {
4797 preempt_enable();
4798 }
4799
4800 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4801 struct x86_instruction_info *info,
4802 enum x86_intercept_stage stage)
4803 {
4804 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4805 }
4806
4807 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4808 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4809 {
4810 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4811 }
4812
4813 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4814 {
4815 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4816 }
4817
4818 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4819 {
4820 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4821 }
4822
4823 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4824 {
4825 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4826 }
4827
4828 static const struct x86_emulate_ops emulate_ops = {
4829 .read_gpr = emulator_read_gpr,
4830 .write_gpr = emulator_write_gpr,
4831 .read_std = kvm_read_guest_virt_system,
4832 .write_std = kvm_write_guest_virt_system,
4833 .fetch = kvm_fetch_guest_virt,
4834 .read_emulated = emulator_read_emulated,
4835 .write_emulated = emulator_write_emulated,
4836 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4837 .invlpg = emulator_invlpg,
4838 .pio_in_emulated = emulator_pio_in_emulated,
4839 .pio_out_emulated = emulator_pio_out_emulated,
4840 .get_segment = emulator_get_segment,
4841 .set_segment = emulator_set_segment,
4842 .get_cached_segment_base = emulator_get_cached_segment_base,
4843 .get_gdt = emulator_get_gdt,
4844 .get_idt = emulator_get_idt,
4845 .set_gdt = emulator_set_gdt,
4846 .set_idt = emulator_set_idt,
4847 .get_cr = emulator_get_cr,
4848 .set_cr = emulator_set_cr,
4849 .cpl = emulator_get_cpl,
4850 .get_dr = emulator_get_dr,
4851 .set_dr = emulator_set_dr,
4852 .get_smbase = emulator_get_smbase,
4853 .set_smbase = emulator_set_smbase,
4854 .set_msr = emulator_set_msr,
4855 .get_msr = emulator_get_msr,
4856 .check_pmc = emulator_check_pmc,
4857 .read_pmc = emulator_read_pmc,
4858 .halt = emulator_halt,
4859 .wbinvd = emulator_wbinvd,
4860 .fix_hypercall = emulator_fix_hypercall,
4861 .get_fpu = emulator_get_fpu,
4862 .put_fpu = emulator_put_fpu,
4863 .intercept = emulator_intercept,
4864 .get_cpuid = emulator_get_cpuid,
4865 .set_nmi_mask = emulator_set_nmi_mask,
4866 };
4867
4868 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4869 {
4870 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4871 /*
4872 * an sti; sti; sequence only disable interrupts for the first
4873 * instruction. So, if the last instruction, be it emulated or
4874 * not, left the system with the INT_STI flag enabled, it
4875 * means that the last instruction is an sti. We should not
4876 * leave the flag on in this case. The same goes for mov ss
4877 */
4878 if (int_shadow & mask)
4879 mask = 0;
4880 if (unlikely(int_shadow || mask)) {
4881 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4882 if (!mask)
4883 kvm_make_request(KVM_REQ_EVENT, vcpu);
4884 }
4885 }
4886
4887 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4888 {
4889 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4890 if (ctxt->exception.vector == PF_VECTOR)
4891 return kvm_propagate_fault(vcpu, &ctxt->exception);
4892
4893 if (ctxt->exception.error_code_valid)
4894 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4895 ctxt->exception.error_code);
4896 else
4897 kvm_queue_exception(vcpu, ctxt->exception.vector);
4898 return false;
4899 }
4900
4901 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4902 {
4903 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4904 int cs_db, cs_l;
4905
4906 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4907
4908 ctxt->eflags = kvm_get_rflags(vcpu);
4909 ctxt->eip = kvm_rip_read(vcpu);
4910 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4911 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4912 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4913 cs_db ? X86EMUL_MODE_PROT32 :
4914 X86EMUL_MODE_PROT16;
4915 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4916 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4917 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4918 ctxt->emul_flags = vcpu->arch.hflags;
4919
4920 init_decode_cache(ctxt);
4921 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4922 }
4923
4924 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4925 {
4926 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4927 int ret;
4928
4929 init_emulate_ctxt(vcpu);
4930
4931 ctxt->op_bytes = 2;
4932 ctxt->ad_bytes = 2;
4933 ctxt->_eip = ctxt->eip + inc_eip;
4934 ret = emulate_int_real(ctxt, irq);
4935
4936 if (ret != X86EMUL_CONTINUE)
4937 return EMULATE_FAIL;
4938
4939 ctxt->eip = ctxt->_eip;
4940 kvm_rip_write(vcpu, ctxt->eip);
4941 kvm_set_rflags(vcpu, ctxt->eflags);
4942
4943 if (irq == NMI_VECTOR)
4944 vcpu->arch.nmi_pending = 0;
4945 else
4946 vcpu->arch.interrupt.pending = false;
4947
4948 return EMULATE_DONE;
4949 }
4950 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4951
4952 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4953 {
4954 int r = EMULATE_DONE;
4955
4956 ++vcpu->stat.insn_emulation_fail;
4957 trace_kvm_emulate_insn_failed(vcpu);
4958 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4959 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4960 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4961 vcpu->run->internal.ndata = 0;
4962 r = EMULATE_FAIL;
4963 }
4964 kvm_queue_exception(vcpu, UD_VECTOR);
4965
4966 return r;
4967 }
4968
4969 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4970 bool write_fault_to_shadow_pgtable,
4971 int emulation_type)
4972 {
4973 gpa_t gpa = cr2;
4974 pfn_t pfn;
4975
4976 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4977 return false;
4978
4979 if (!vcpu->arch.mmu.direct_map) {
4980 /*
4981 * Write permission should be allowed since only
4982 * write access need to be emulated.
4983 */
4984 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4985
4986 /*
4987 * If the mapping is invalid in guest, let cpu retry
4988 * it to generate fault.
4989 */
4990 if (gpa == UNMAPPED_GVA)
4991 return true;
4992 }
4993
4994 /*
4995 * Do not retry the unhandleable instruction if it faults on the
4996 * readonly host memory, otherwise it will goto a infinite loop:
4997 * retry instruction -> write #PF -> emulation fail -> retry
4998 * instruction -> ...
4999 */
5000 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5001
5002 /*
5003 * If the instruction failed on the error pfn, it can not be fixed,
5004 * report the error to userspace.
5005 */
5006 if (is_error_noslot_pfn(pfn))
5007 return false;
5008
5009 kvm_release_pfn_clean(pfn);
5010
5011 /* The instructions are well-emulated on direct mmu. */
5012 if (vcpu->arch.mmu.direct_map) {
5013 unsigned int indirect_shadow_pages;
5014
5015 spin_lock(&vcpu->kvm->mmu_lock);
5016 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5017 spin_unlock(&vcpu->kvm->mmu_lock);
5018
5019 if (indirect_shadow_pages)
5020 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5021
5022 return true;
5023 }
5024
5025 /*
5026 * if emulation was due to access to shadowed page table
5027 * and it failed try to unshadow page and re-enter the
5028 * guest to let CPU execute the instruction.
5029 */
5030 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5031
5032 /*
5033 * If the access faults on its page table, it can not
5034 * be fixed by unprotecting shadow page and it should
5035 * be reported to userspace.
5036 */
5037 return !write_fault_to_shadow_pgtable;
5038 }
5039
5040 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5041 unsigned long cr2, int emulation_type)
5042 {
5043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5044 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5045
5046 last_retry_eip = vcpu->arch.last_retry_eip;
5047 last_retry_addr = vcpu->arch.last_retry_addr;
5048
5049 /*
5050 * If the emulation is caused by #PF and it is non-page_table
5051 * writing instruction, it means the VM-EXIT is caused by shadow
5052 * page protected, we can zap the shadow page and retry this
5053 * instruction directly.
5054 *
5055 * Note: if the guest uses a non-page-table modifying instruction
5056 * on the PDE that points to the instruction, then we will unmap
5057 * the instruction and go to an infinite loop. So, we cache the
5058 * last retried eip and the last fault address, if we meet the eip
5059 * and the address again, we can break out of the potential infinite
5060 * loop.
5061 */
5062 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5063
5064 if (!(emulation_type & EMULTYPE_RETRY))
5065 return false;
5066
5067 if (x86_page_table_writing_insn(ctxt))
5068 return false;
5069
5070 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5071 return false;
5072
5073 vcpu->arch.last_retry_eip = ctxt->eip;
5074 vcpu->arch.last_retry_addr = cr2;
5075
5076 if (!vcpu->arch.mmu.direct_map)
5077 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5078
5079 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5080
5081 return true;
5082 }
5083
5084 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5085 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5086
5087 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5088 {
5089 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5090 /* This is a good place to trace that we are exiting SMM. */
5091 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5092
5093 if (unlikely(vcpu->arch.smi_pending)) {
5094 kvm_make_request(KVM_REQ_SMI, vcpu);
5095 vcpu->arch.smi_pending = 0;
5096 } else {
5097 /* Process a latched INIT, if any. */
5098 kvm_make_request(KVM_REQ_EVENT, vcpu);
5099 }
5100 }
5101
5102 kvm_mmu_reset_context(vcpu);
5103 }
5104
5105 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5106 {
5107 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5108
5109 vcpu->arch.hflags = emul_flags;
5110
5111 if (changed & HF_SMM_MASK)
5112 kvm_smm_changed(vcpu);
5113 }
5114
5115 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5116 unsigned long *db)
5117 {
5118 u32 dr6 = 0;
5119 int i;
5120 u32 enable, rwlen;
5121
5122 enable = dr7;
5123 rwlen = dr7 >> 16;
5124 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5125 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5126 dr6 |= (1 << i);
5127 return dr6;
5128 }
5129
5130 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5131 {
5132 struct kvm_run *kvm_run = vcpu->run;
5133
5134 /*
5135 * rflags is the old, "raw" value of the flags. The new value has
5136 * not been saved yet.
5137 *
5138 * This is correct even for TF set by the guest, because "the
5139 * processor will not generate this exception after the instruction
5140 * that sets the TF flag".
5141 */
5142 if (unlikely(rflags & X86_EFLAGS_TF)) {
5143 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5144 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5145 DR6_RTM;
5146 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5147 kvm_run->debug.arch.exception = DB_VECTOR;
5148 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5149 *r = EMULATE_USER_EXIT;
5150 } else {
5151 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5152 /*
5153 * "Certain debug exceptions may clear bit 0-3. The
5154 * remaining contents of the DR6 register are never
5155 * cleared by the processor".
5156 */
5157 vcpu->arch.dr6 &= ~15;
5158 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5159 kvm_queue_exception(vcpu, DB_VECTOR);
5160 }
5161 }
5162 }
5163
5164 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5165 {
5166 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5167 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5168 struct kvm_run *kvm_run = vcpu->run;
5169 unsigned long eip = kvm_get_linear_rip(vcpu);
5170 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5171 vcpu->arch.guest_debug_dr7,
5172 vcpu->arch.eff_db);
5173
5174 if (dr6 != 0) {
5175 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5176 kvm_run->debug.arch.pc = eip;
5177 kvm_run->debug.arch.exception = DB_VECTOR;
5178 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5179 *r = EMULATE_USER_EXIT;
5180 return true;
5181 }
5182 }
5183
5184 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5185 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5186 unsigned long eip = kvm_get_linear_rip(vcpu);
5187 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5188 vcpu->arch.dr7,
5189 vcpu->arch.db);
5190
5191 if (dr6 != 0) {
5192 vcpu->arch.dr6 &= ~15;
5193 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5194 kvm_queue_exception(vcpu, DB_VECTOR);
5195 *r = EMULATE_DONE;
5196 return true;
5197 }
5198 }
5199
5200 return false;
5201 }
5202
5203 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5204 unsigned long cr2,
5205 int emulation_type,
5206 void *insn,
5207 int insn_len)
5208 {
5209 int r;
5210 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5211 bool writeback = true;
5212 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5213
5214 /*
5215 * Clear write_fault_to_shadow_pgtable here to ensure it is
5216 * never reused.
5217 */
5218 vcpu->arch.write_fault_to_shadow_pgtable = false;
5219 kvm_clear_exception_queue(vcpu);
5220
5221 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5222 init_emulate_ctxt(vcpu);
5223
5224 /*
5225 * We will reenter on the same instruction since
5226 * we do not set complete_userspace_io. This does not
5227 * handle watchpoints yet, those would be handled in
5228 * the emulate_ops.
5229 */
5230 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5231 return r;
5232
5233 ctxt->interruptibility = 0;
5234 ctxt->have_exception = false;
5235 ctxt->exception.vector = -1;
5236 ctxt->perm_ok = false;
5237
5238 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5239
5240 r = x86_decode_insn(ctxt, insn, insn_len);
5241
5242 trace_kvm_emulate_insn_start(vcpu);
5243 ++vcpu->stat.insn_emulation;
5244 if (r != EMULATION_OK) {
5245 if (emulation_type & EMULTYPE_TRAP_UD)
5246 return EMULATE_FAIL;
5247 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5248 emulation_type))
5249 return EMULATE_DONE;
5250 if (emulation_type & EMULTYPE_SKIP)
5251 return EMULATE_FAIL;
5252 return handle_emulation_failure(vcpu);
5253 }
5254 }
5255
5256 if (emulation_type & EMULTYPE_SKIP) {
5257 kvm_rip_write(vcpu, ctxt->_eip);
5258 if (ctxt->eflags & X86_EFLAGS_RF)
5259 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5260 return EMULATE_DONE;
5261 }
5262
5263 if (retry_instruction(ctxt, cr2, emulation_type))
5264 return EMULATE_DONE;
5265
5266 /* this is needed for vmware backdoor interface to work since it
5267 changes registers values during IO operation */
5268 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5269 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5270 emulator_invalidate_register_cache(ctxt);
5271 }
5272
5273 restart:
5274 r = x86_emulate_insn(ctxt);
5275
5276 if (r == EMULATION_INTERCEPTED)
5277 return EMULATE_DONE;
5278
5279 if (r == EMULATION_FAILED) {
5280 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5281 emulation_type))
5282 return EMULATE_DONE;
5283
5284 return handle_emulation_failure(vcpu);
5285 }
5286
5287 if (ctxt->have_exception) {
5288 r = EMULATE_DONE;
5289 if (inject_emulated_exception(vcpu))
5290 return r;
5291 } else if (vcpu->arch.pio.count) {
5292 if (!vcpu->arch.pio.in) {
5293 /* FIXME: return into emulator if single-stepping. */
5294 vcpu->arch.pio.count = 0;
5295 } else {
5296 writeback = false;
5297 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5298 }
5299 r = EMULATE_USER_EXIT;
5300 } else if (vcpu->mmio_needed) {
5301 if (!vcpu->mmio_is_write)
5302 writeback = false;
5303 r = EMULATE_USER_EXIT;
5304 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5305 } else if (r == EMULATION_RESTART)
5306 goto restart;
5307 else
5308 r = EMULATE_DONE;
5309
5310 if (writeback) {
5311 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5312 toggle_interruptibility(vcpu, ctxt->interruptibility);
5313 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5314 if (vcpu->arch.hflags != ctxt->emul_flags)
5315 kvm_set_hflags(vcpu, ctxt->emul_flags);
5316 kvm_rip_write(vcpu, ctxt->eip);
5317 if (r == EMULATE_DONE)
5318 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5319 if (!ctxt->have_exception ||
5320 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5321 __kvm_set_rflags(vcpu, ctxt->eflags);
5322
5323 /*
5324 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5325 * do nothing, and it will be requested again as soon as
5326 * the shadow expires. But we still need to check here,
5327 * because POPF has no interrupt shadow.
5328 */
5329 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5330 kvm_make_request(KVM_REQ_EVENT, vcpu);
5331 } else
5332 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5333
5334 return r;
5335 }
5336 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5337
5338 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5339 {
5340 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5341 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5342 size, port, &val, 1);
5343 /* do not return to emulator after return from userspace */
5344 vcpu->arch.pio.count = 0;
5345 return ret;
5346 }
5347 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5348
5349 static void tsc_bad(void *info)
5350 {
5351 __this_cpu_write(cpu_tsc_khz, 0);
5352 }
5353
5354 static void tsc_khz_changed(void *data)
5355 {
5356 struct cpufreq_freqs *freq = data;
5357 unsigned long khz = 0;
5358
5359 if (data)
5360 khz = freq->new;
5361 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5362 khz = cpufreq_quick_get(raw_smp_processor_id());
5363 if (!khz)
5364 khz = tsc_khz;
5365 __this_cpu_write(cpu_tsc_khz, khz);
5366 }
5367
5368 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5369 void *data)
5370 {
5371 struct cpufreq_freqs *freq = data;
5372 struct kvm *kvm;
5373 struct kvm_vcpu *vcpu;
5374 int i, send_ipi = 0;
5375
5376 /*
5377 * We allow guests to temporarily run on slowing clocks,
5378 * provided we notify them after, or to run on accelerating
5379 * clocks, provided we notify them before. Thus time never
5380 * goes backwards.
5381 *
5382 * However, we have a problem. We can't atomically update
5383 * the frequency of a given CPU from this function; it is
5384 * merely a notifier, which can be called from any CPU.
5385 * Changing the TSC frequency at arbitrary points in time
5386 * requires a recomputation of local variables related to
5387 * the TSC for each VCPU. We must flag these local variables
5388 * to be updated and be sure the update takes place with the
5389 * new frequency before any guests proceed.
5390 *
5391 * Unfortunately, the combination of hotplug CPU and frequency
5392 * change creates an intractable locking scenario; the order
5393 * of when these callouts happen is undefined with respect to
5394 * CPU hotplug, and they can race with each other. As such,
5395 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5396 * undefined; you can actually have a CPU frequency change take
5397 * place in between the computation of X and the setting of the
5398 * variable. To protect against this problem, all updates of
5399 * the per_cpu tsc_khz variable are done in an interrupt
5400 * protected IPI, and all callers wishing to update the value
5401 * must wait for a synchronous IPI to complete (which is trivial
5402 * if the caller is on the CPU already). This establishes the
5403 * necessary total order on variable updates.
5404 *
5405 * Note that because a guest time update may take place
5406 * anytime after the setting of the VCPU's request bit, the
5407 * correct TSC value must be set before the request. However,
5408 * to ensure the update actually makes it to any guest which
5409 * starts running in hardware virtualization between the set
5410 * and the acquisition of the spinlock, we must also ping the
5411 * CPU after setting the request bit.
5412 *
5413 */
5414
5415 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5416 return 0;
5417 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5418 return 0;
5419
5420 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5421
5422 spin_lock(&kvm_lock);
5423 list_for_each_entry(kvm, &vm_list, vm_list) {
5424 kvm_for_each_vcpu(i, vcpu, kvm) {
5425 if (vcpu->cpu != freq->cpu)
5426 continue;
5427 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5428 if (vcpu->cpu != smp_processor_id())
5429 send_ipi = 1;
5430 }
5431 }
5432 spin_unlock(&kvm_lock);
5433
5434 if (freq->old < freq->new && send_ipi) {
5435 /*
5436 * We upscale the frequency. Must make the guest
5437 * doesn't see old kvmclock values while running with
5438 * the new frequency, otherwise we risk the guest sees
5439 * time go backwards.
5440 *
5441 * In case we update the frequency for another cpu
5442 * (which might be in guest context) send an interrupt
5443 * to kick the cpu out of guest context. Next time
5444 * guest context is entered kvmclock will be updated,
5445 * so the guest will not see stale values.
5446 */
5447 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5448 }
5449 return 0;
5450 }
5451
5452 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5453 .notifier_call = kvmclock_cpufreq_notifier
5454 };
5455
5456 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5457 unsigned long action, void *hcpu)
5458 {
5459 unsigned int cpu = (unsigned long)hcpu;
5460
5461 switch (action) {
5462 case CPU_ONLINE:
5463 case CPU_DOWN_FAILED:
5464 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5465 break;
5466 case CPU_DOWN_PREPARE:
5467 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5468 break;
5469 }
5470 return NOTIFY_OK;
5471 }
5472
5473 static struct notifier_block kvmclock_cpu_notifier_block = {
5474 .notifier_call = kvmclock_cpu_notifier,
5475 .priority = -INT_MAX
5476 };
5477
5478 static void kvm_timer_init(void)
5479 {
5480 int cpu;
5481
5482 max_tsc_khz = tsc_khz;
5483
5484 cpu_notifier_register_begin();
5485 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5486 #ifdef CONFIG_CPU_FREQ
5487 struct cpufreq_policy policy;
5488 memset(&policy, 0, sizeof(policy));
5489 cpu = get_cpu();
5490 cpufreq_get_policy(&policy, cpu);
5491 if (policy.cpuinfo.max_freq)
5492 max_tsc_khz = policy.cpuinfo.max_freq;
5493 put_cpu();
5494 #endif
5495 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5496 CPUFREQ_TRANSITION_NOTIFIER);
5497 }
5498 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5499 for_each_online_cpu(cpu)
5500 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5501
5502 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5503 cpu_notifier_register_done();
5504
5505 }
5506
5507 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5508
5509 int kvm_is_in_guest(void)
5510 {
5511 return __this_cpu_read(current_vcpu) != NULL;
5512 }
5513
5514 static int kvm_is_user_mode(void)
5515 {
5516 int user_mode = 3;
5517
5518 if (__this_cpu_read(current_vcpu))
5519 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5520
5521 return user_mode != 0;
5522 }
5523
5524 static unsigned long kvm_get_guest_ip(void)
5525 {
5526 unsigned long ip = 0;
5527
5528 if (__this_cpu_read(current_vcpu))
5529 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5530
5531 return ip;
5532 }
5533
5534 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5535 .is_in_guest = kvm_is_in_guest,
5536 .is_user_mode = kvm_is_user_mode,
5537 .get_guest_ip = kvm_get_guest_ip,
5538 };
5539
5540 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5541 {
5542 __this_cpu_write(current_vcpu, vcpu);
5543 }
5544 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5545
5546 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5547 {
5548 __this_cpu_write(current_vcpu, NULL);
5549 }
5550 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5551
5552 static void kvm_set_mmio_spte_mask(void)
5553 {
5554 u64 mask;
5555 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5556
5557 /*
5558 * Set the reserved bits and the present bit of an paging-structure
5559 * entry to generate page fault with PFER.RSV = 1.
5560 */
5561 /* Mask the reserved physical address bits. */
5562 mask = rsvd_bits(maxphyaddr, 51);
5563
5564 /* Bit 62 is always reserved for 32bit host. */
5565 mask |= 0x3ull << 62;
5566
5567 /* Set the present bit. */
5568 mask |= 1ull;
5569
5570 #ifdef CONFIG_X86_64
5571 /*
5572 * If reserved bit is not supported, clear the present bit to disable
5573 * mmio page fault.
5574 */
5575 if (maxphyaddr == 52)
5576 mask &= ~1ull;
5577 #endif
5578
5579 kvm_mmu_set_mmio_spte_mask(mask);
5580 }
5581
5582 #ifdef CONFIG_X86_64
5583 static void pvclock_gtod_update_fn(struct work_struct *work)
5584 {
5585 struct kvm *kvm;
5586
5587 struct kvm_vcpu *vcpu;
5588 int i;
5589
5590 spin_lock(&kvm_lock);
5591 list_for_each_entry(kvm, &vm_list, vm_list)
5592 kvm_for_each_vcpu(i, vcpu, kvm)
5593 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5594 atomic_set(&kvm_guest_has_master_clock, 0);
5595 spin_unlock(&kvm_lock);
5596 }
5597
5598 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5599
5600 /*
5601 * Notification about pvclock gtod data update.
5602 */
5603 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5604 void *priv)
5605 {
5606 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5607 struct timekeeper *tk = priv;
5608
5609 update_pvclock_gtod(tk);
5610
5611 /* disable master clock if host does not trust, or does not
5612 * use, TSC clocksource
5613 */
5614 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5615 atomic_read(&kvm_guest_has_master_clock) != 0)
5616 queue_work(system_long_wq, &pvclock_gtod_work);
5617
5618 return 0;
5619 }
5620
5621 static struct notifier_block pvclock_gtod_notifier = {
5622 .notifier_call = pvclock_gtod_notify,
5623 };
5624 #endif
5625
5626 int kvm_arch_init(void *opaque)
5627 {
5628 int r;
5629 struct kvm_x86_ops *ops = opaque;
5630
5631 if (kvm_x86_ops) {
5632 printk(KERN_ERR "kvm: already loaded the other module\n");
5633 r = -EEXIST;
5634 goto out;
5635 }
5636
5637 if (!ops->cpu_has_kvm_support()) {
5638 printk(KERN_ERR "kvm: no hardware support\n");
5639 r = -EOPNOTSUPP;
5640 goto out;
5641 }
5642 if (ops->disabled_by_bios()) {
5643 printk(KERN_ERR "kvm: disabled by bios\n");
5644 r = -EOPNOTSUPP;
5645 goto out;
5646 }
5647
5648 r = -ENOMEM;
5649 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5650 if (!shared_msrs) {
5651 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5652 goto out;
5653 }
5654
5655 r = kvm_mmu_module_init();
5656 if (r)
5657 goto out_free_percpu;
5658
5659 kvm_set_mmio_spte_mask();
5660
5661 kvm_x86_ops = ops;
5662
5663 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5664 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5665
5666 kvm_timer_init();
5667
5668 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5669
5670 if (cpu_has_xsave)
5671 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5672
5673 kvm_lapic_init();
5674 #ifdef CONFIG_X86_64
5675 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5676 #endif
5677
5678 return 0;
5679
5680 out_free_percpu:
5681 free_percpu(shared_msrs);
5682 out:
5683 return r;
5684 }
5685
5686 void kvm_arch_exit(void)
5687 {
5688 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5689
5690 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5691 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5692 CPUFREQ_TRANSITION_NOTIFIER);
5693 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5694 #ifdef CONFIG_X86_64
5695 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5696 #endif
5697 kvm_x86_ops = NULL;
5698 kvm_mmu_module_exit();
5699 free_percpu(shared_msrs);
5700 }
5701
5702 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5703 {
5704 ++vcpu->stat.halt_exits;
5705 if (lapic_in_kernel(vcpu)) {
5706 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5707 return 1;
5708 } else {
5709 vcpu->run->exit_reason = KVM_EXIT_HLT;
5710 return 0;
5711 }
5712 }
5713 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5714
5715 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5716 {
5717 kvm_x86_ops->skip_emulated_instruction(vcpu);
5718 return kvm_vcpu_halt(vcpu);
5719 }
5720 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5721
5722 /*
5723 * kvm_pv_kick_cpu_op: Kick a vcpu.
5724 *
5725 * @apicid - apicid of vcpu to be kicked.
5726 */
5727 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5728 {
5729 struct kvm_lapic_irq lapic_irq;
5730
5731 lapic_irq.shorthand = 0;
5732 lapic_irq.dest_mode = 0;
5733 lapic_irq.dest_id = apicid;
5734 lapic_irq.msi_redir_hint = false;
5735
5736 lapic_irq.delivery_mode = APIC_DM_REMRD;
5737 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5738 }
5739
5740 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5741 {
5742 unsigned long nr, a0, a1, a2, a3, ret;
5743 int op_64_bit, r = 1;
5744
5745 kvm_x86_ops->skip_emulated_instruction(vcpu);
5746
5747 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5748 return kvm_hv_hypercall(vcpu);
5749
5750 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5751 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5752 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5753 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5754 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5755
5756 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5757
5758 op_64_bit = is_64_bit_mode(vcpu);
5759 if (!op_64_bit) {
5760 nr &= 0xFFFFFFFF;
5761 a0 &= 0xFFFFFFFF;
5762 a1 &= 0xFFFFFFFF;
5763 a2 &= 0xFFFFFFFF;
5764 a3 &= 0xFFFFFFFF;
5765 }
5766
5767 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5768 ret = -KVM_EPERM;
5769 goto out;
5770 }
5771
5772 switch (nr) {
5773 case KVM_HC_VAPIC_POLL_IRQ:
5774 ret = 0;
5775 break;
5776 case KVM_HC_KICK_CPU:
5777 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5778 ret = 0;
5779 break;
5780 default:
5781 ret = -KVM_ENOSYS;
5782 break;
5783 }
5784 out:
5785 if (!op_64_bit)
5786 ret = (u32)ret;
5787 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5788 ++vcpu->stat.hypercalls;
5789 return r;
5790 }
5791 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5792
5793 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5794 {
5795 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5796 char instruction[3];
5797 unsigned long rip = kvm_rip_read(vcpu);
5798
5799 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5800
5801 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5802 }
5803
5804 /*
5805 * Check if userspace requested an interrupt window, and that the
5806 * interrupt window is open.
5807 *
5808 * No need to exit to userspace if we already have an interrupt queued.
5809 */
5810 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5811 {
5812 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5813 return false;
5814
5815 if (kvm_cpu_has_interrupt(vcpu))
5816 return false;
5817
5818 return (irqchip_split(vcpu->kvm)
5819 ? kvm_apic_accept_pic_intr(vcpu)
5820 : kvm_arch_interrupt_allowed(vcpu));
5821 }
5822
5823 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5824 {
5825 struct kvm_run *kvm_run = vcpu->run;
5826
5827 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5828 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5829 kvm_run->cr8 = kvm_get_cr8(vcpu);
5830 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5831 if (!irqchip_in_kernel(vcpu->kvm))
5832 kvm_run->ready_for_interrupt_injection =
5833 kvm_arch_interrupt_allowed(vcpu) &&
5834 !kvm_cpu_has_interrupt(vcpu) &&
5835 !kvm_event_needs_reinjection(vcpu);
5836 else if (!pic_in_kernel(vcpu->kvm))
5837 kvm_run->ready_for_interrupt_injection =
5838 kvm_apic_accept_pic_intr(vcpu) &&
5839 !kvm_cpu_has_interrupt(vcpu);
5840 else
5841 kvm_run->ready_for_interrupt_injection = 1;
5842 }
5843
5844 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5845 {
5846 int max_irr, tpr;
5847
5848 if (!kvm_x86_ops->update_cr8_intercept)
5849 return;
5850
5851 if (!vcpu->arch.apic)
5852 return;
5853
5854 if (!vcpu->arch.apic->vapic_addr)
5855 max_irr = kvm_lapic_find_highest_irr(vcpu);
5856 else
5857 max_irr = -1;
5858
5859 if (max_irr != -1)
5860 max_irr >>= 4;
5861
5862 tpr = kvm_lapic_get_cr8(vcpu);
5863
5864 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5865 }
5866
5867 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5868 {
5869 int r;
5870
5871 /* try to reinject previous events if any */
5872 if (vcpu->arch.exception.pending) {
5873 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5874 vcpu->arch.exception.has_error_code,
5875 vcpu->arch.exception.error_code);
5876
5877 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5878 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5879 X86_EFLAGS_RF);
5880
5881 if (vcpu->arch.exception.nr == DB_VECTOR &&
5882 (vcpu->arch.dr7 & DR7_GD)) {
5883 vcpu->arch.dr7 &= ~DR7_GD;
5884 kvm_update_dr7(vcpu);
5885 }
5886
5887 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5888 vcpu->arch.exception.has_error_code,
5889 vcpu->arch.exception.error_code,
5890 vcpu->arch.exception.reinject);
5891 return 0;
5892 }
5893
5894 if (vcpu->arch.nmi_injected) {
5895 kvm_x86_ops->set_nmi(vcpu);
5896 return 0;
5897 }
5898
5899 if (vcpu->arch.interrupt.pending) {
5900 kvm_x86_ops->set_irq(vcpu);
5901 return 0;
5902 }
5903
5904 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5905 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5906 if (r != 0)
5907 return r;
5908 }
5909
5910 /* try to inject new event if pending */
5911 if (vcpu->arch.nmi_pending) {
5912 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5913 --vcpu->arch.nmi_pending;
5914 vcpu->arch.nmi_injected = true;
5915 kvm_x86_ops->set_nmi(vcpu);
5916 }
5917 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5918 /*
5919 * Because interrupts can be injected asynchronously, we are
5920 * calling check_nested_events again here to avoid a race condition.
5921 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5922 * proposal and current concerns. Perhaps we should be setting
5923 * KVM_REQ_EVENT only on certain events and not unconditionally?
5924 */
5925 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5926 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5927 if (r != 0)
5928 return r;
5929 }
5930 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5931 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5932 false);
5933 kvm_x86_ops->set_irq(vcpu);
5934 }
5935 }
5936 return 0;
5937 }
5938
5939 static void process_nmi(struct kvm_vcpu *vcpu)
5940 {
5941 unsigned limit = 2;
5942
5943 /*
5944 * x86 is limited to one NMI running, and one NMI pending after it.
5945 * If an NMI is already in progress, limit further NMIs to just one.
5946 * Otherwise, allow two (and we'll inject the first one immediately).
5947 */
5948 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5949 limit = 1;
5950
5951 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5952 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5953 kvm_make_request(KVM_REQ_EVENT, vcpu);
5954 }
5955
5956 #define put_smstate(type, buf, offset, val) \
5957 *(type *)((buf) + (offset) - 0x7e00) = val
5958
5959 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5960 {
5961 u32 flags = 0;
5962 flags |= seg->g << 23;
5963 flags |= seg->db << 22;
5964 flags |= seg->l << 21;
5965 flags |= seg->avl << 20;
5966 flags |= seg->present << 15;
5967 flags |= seg->dpl << 13;
5968 flags |= seg->s << 12;
5969 flags |= seg->type << 8;
5970 return flags;
5971 }
5972
5973 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5974 {
5975 struct kvm_segment seg;
5976 int offset;
5977
5978 kvm_get_segment(vcpu, &seg, n);
5979 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5980
5981 if (n < 3)
5982 offset = 0x7f84 + n * 12;
5983 else
5984 offset = 0x7f2c + (n - 3) * 12;
5985
5986 put_smstate(u32, buf, offset + 8, seg.base);
5987 put_smstate(u32, buf, offset + 4, seg.limit);
5988 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5989 }
5990
5991 #ifdef CONFIG_X86_64
5992 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5993 {
5994 struct kvm_segment seg;
5995 int offset;
5996 u16 flags;
5997
5998 kvm_get_segment(vcpu, &seg, n);
5999 offset = 0x7e00 + n * 16;
6000
6001 flags = process_smi_get_segment_flags(&seg) >> 8;
6002 put_smstate(u16, buf, offset, seg.selector);
6003 put_smstate(u16, buf, offset + 2, flags);
6004 put_smstate(u32, buf, offset + 4, seg.limit);
6005 put_smstate(u64, buf, offset + 8, seg.base);
6006 }
6007 #endif
6008
6009 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6010 {
6011 struct desc_ptr dt;
6012 struct kvm_segment seg;
6013 unsigned long val;
6014 int i;
6015
6016 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6017 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6018 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6019 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6020
6021 for (i = 0; i < 8; i++)
6022 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6023
6024 kvm_get_dr(vcpu, 6, &val);
6025 put_smstate(u32, buf, 0x7fcc, (u32)val);
6026 kvm_get_dr(vcpu, 7, &val);
6027 put_smstate(u32, buf, 0x7fc8, (u32)val);
6028
6029 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6030 put_smstate(u32, buf, 0x7fc4, seg.selector);
6031 put_smstate(u32, buf, 0x7f64, seg.base);
6032 put_smstate(u32, buf, 0x7f60, seg.limit);
6033 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6034
6035 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6036 put_smstate(u32, buf, 0x7fc0, seg.selector);
6037 put_smstate(u32, buf, 0x7f80, seg.base);
6038 put_smstate(u32, buf, 0x7f7c, seg.limit);
6039 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6040
6041 kvm_x86_ops->get_gdt(vcpu, &dt);
6042 put_smstate(u32, buf, 0x7f74, dt.address);
6043 put_smstate(u32, buf, 0x7f70, dt.size);
6044
6045 kvm_x86_ops->get_idt(vcpu, &dt);
6046 put_smstate(u32, buf, 0x7f58, dt.address);
6047 put_smstate(u32, buf, 0x7f54, dt.size);
6048
6049 for (i = 0; i < 6; i++)
6050 process_smi_save_seg_32(vcpu, buf, i);
6051
6052 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6053
6054 /* revision id */
6055 put_smstate(u32, buf, 0x7efc, 0x00020000);
6056 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6057 }
6058
6059 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6060 {
6061 #ifdef CONFIG_X86_64
6062 struct desc_ptr dt;
6063 struct kvm_segment seg;
6064 unsigned long val;
6065 int i;
6066
6067 for (i = 0; i < 16; i++)
6068 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6069
6070 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6071 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6072
6073 kvm_get_dr(vcpu, 6, &val);
6074 put_smstate(u64, buf, 0x7f68, val);
6075 kvm_get_dr(vcpu, 7, &val);
6076 put_smstate(u64, buf, 0x7f60, val);
6077
6078 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6079 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6080 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6081
6082 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6083
6084 /* revision id */
6085 put_smstate(u32, buf, 0x7efc, 0x00020064);
6086
6087 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6088
6089 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6090 put_smstate(u16, buf, 0x7e90, seg.selector);
6091 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6092 put_smstate(u32, buf, 0x7e94, seg.limit);
6093 put_smstate(u64, buf, 0x7e98, seg.base);
6094
6095 kvm_x86_ops->get_idt(vcpu, &dt);
6096 put_smstate(u32, buf, 0x7e84, dt.size);
6097 put_smstate(u64, buf, 0x7e88, dt.address);
6098
6099 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6100 put_smstate(u16, buf, 0x7e70, seg.selector);
6101 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6102 put_smstate(u32, buf, 0x7e74, seg.limit);
6103 put_smstate(u64, buf, 0x7e78, seg.base);
6104
6105 kvm_x86_ops->get_gdt(vcpu, &dt);
6106 put_smstate(u32, buf, 0x7e64, dt.size);
6107 put_smstate(u64, buf, 0x7e68, dt.address);
6108
6109 for (i = 0; i < 6; i++)
6110 process_smi_save_seg_64(vcpu, buf, i);
6111 #else
6112 WARN_ON_ONCE(1);
6113 #endif
6114 }
6115
6116 static void process_smi(struct kvm_vcpu *vcpu)
6117 {
6118 struct kvm_segment cs, ds;
6119 struct desc_ptr dt;
6120 char buf[512];
6121 u32 cr0;
6122
6123 if (is_smm(vcpu)) {
6124 vcpu->arch.smi_pending = true;
6125 return;
6126 }
6127
6128 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6129 vcpu->arch.hflags |= HF_SMM_MASK;
6130 memset(buf, 0, 512);
6131 if (guest_cpuid_has_longmode(vcpu))
6132 process_smi_save_state_64(vcpu, buf);
6133 else
6134 process_smi_save_state_32(vcpu, buf);
6135
6136 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6137
6138 if (kvm_x86_ops->get_nmi_mask(vcpu))
6139 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6140 else
6141 kvm_x86_ops->set_nmi_mask(vcpu, true);
6142
6143 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6144 kvm_rip_write(vcpu, 0x8000);
6145
6146 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6147 kvm_x86_ops->set_cr0(vcpu, cr0);
6148 vcpu->arch.cr0 = cr0;
6149
6150 kvm_x86_ops->set_cr4(vcpu, 0);
6151
6152 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6153 dt.address = dt.size = 0;
6154 kvm_x86_ops->set_idt(vcpu, &dt);
6155
6156 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6157
6158 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6159 cs.base = vcpu->arch.smbase;
6160
6161 ds.selector = 0;
6162 ds.base = 0;
6163
6164 cs.limit = ds.limit = 0xffffffff;
6165 cs.type = ds.type = 0x3;
6166 cs.dpl = ds.dpl = 0;
6167 cs.db = ds.db = 0;
6168 cs.s = ds.s = 1;
6169 cs.l = ds.l = 0;
6170 cs.g = ds.g = 1;
6171 cs.avl = ds.avl = 0;
6172 cs.present = ds.present = 1;
6173 cs.unusable = ds.unusable = 0;
6174 cs.padding = ds.padding = 0;
6175
6176 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6177 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6178 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6182
6183 if (guest_cpuid_has_longmode(vcpu))
6184 kvm_x86_ops->set_efer(vcpu, 0);
6185
6186 kvm_update_cpuid(vcpu);
6187 kvm_mmu_reset_context(vcpu);
6188 }
6189
6190 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6191 {
6192 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6193 return;
6194
6195 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
6196
6197 if (irqchip_split(vcpu->kvm))
6198 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6199 else
6200 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
6201 kvm_x86_ops->load_eoi_exitmap(vcpu);
6202 }
6203
6204 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6205 {
6206 ++vcpu->stat.tlb_flush;
6207 kvm_x86_ops->tlb_flush(vcpu);
6208 }
6209
6210 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6211 {
6212 struct page *page = NULL;
6213
6214 if (!lapic_in_kernel(vcpu))
6215 return;
6216
6217 if (!kvm_x86_ops->set_apic_access_page_addr)
6218 return;
6219
6220 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6221 if (is_error_page(page))
6222 return;
6223 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6224
6225 /*
6226 * Do not pin apic access page in memory, the MMU notifier
6227 * will call us again if it is migrated or swapped out.
6228 */
6229 put_page(page);
6230 }
6231 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6232
6233 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6234 unsigned long address)
6235 {
6236 /*
6237 * The physical address of apic access page is stored in the VMCS.
6238 * Update it when it becomes invalid.
6239 */
6240 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6241 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6242 }
6243
6244 /*
6245 * Returns 1 to let vcpu_run() continue the guest execution loop without
6246 * exiting to the userspace. Otherwise, the value will be returned to the
6247 * userspace.
6248 */
6249 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6250 {
6251 int r;
6252 bool req_int_win = !lapic_in_kernel(vcpu) &&
6253 vcpu->run->request_interrupt_window;
6254 bool req_immediate_exit = false;
6255
6256 if (vcpu->requests) {
6257 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6258 kvm_mmu_unload(vcpu);
6259 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6260 __kvm_migrate_timers(vcpu);
6261 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6262 kvm_gen_update_masterclock(vcpu->kvm);
6263 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6264 kvm_gen_kvmclock_update(vcpu);
6265 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6266 r = kvm_guest_time_update(vcpu);
6267 if (unlikely(r))
6268 goto out;
6269 }
6270 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6271 kvm_mmu_sync_roots(vcpu);
6272 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6273 kvm_vcpu_flush_tlb(vcpu);
6274 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6275 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6276 r = 0;
6277 goto out;
6278 }
6279 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6280 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6281 r = 0;
6282 goto out;
6283 }
6284 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6285 vcpu->fpu_active = 0;
6286 kvm_x86_ops->fpu_deactivate(vcpu);
6287 }
6288 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6289 /* Page is swapped out. Do synthetic halt */
6290 vcpu->arch.apf.halted = true;
6291 r = 1;
6292 goto out;
6293 }
6294 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6295 record_steal_time(vcpu);
6296 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6297 process_smi(vcpu);
6298 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6299 process_nmi(vcpu);
6300 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6301 kvm_pmu_handle_event(vcpu);
6302 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6303 kvm_pmu_deliver_pmi(vcpu);
6304 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6305 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6306 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6307 (void *) vcpu->arch.eoi_exit_bitmap)) {
6308 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6309 vcpu->run->eoi.vector =
6310 vcpu->arch.pending_ioapic_eoi;
6311 r = 0;
6312 goto out;
6313 }
6314 }
6315 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6316 vcpu_scan_ioapic(vcpu);
6317 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6318 kvm_vcpu_reload_apic_access_page(vcpu);
6319 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6320 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6321 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6322 r = 0;
6323 goto out;
6324 }
6325 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6326 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6327 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6328 r = 0;
6329 goto out;
6330 }
6331 }
6332
6333 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6334 kvm_apic_accept_events(vcpu);
6335 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6336 r = 1;
6337 goto out;
6338 }
6339
6340 if (inject_pending_event(vcpu, req_int_win) != 0)
6341 req_immediate_exit = true;
6342 /* enable NMI/IRQ window open exits if needed */
6343 else if (vcpu->arch.nmi_pending)
6344 kvm_x86_ops->enable_nmi_window(vcpu);
6345 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6346 kvm_x86_ops->enable_irq_window(vcpu);
6347
6348 if (kvm_lapic_enabled(vcpu)) {
6349 /*
6350 * Update architecture specific hints for APIC
6351 * virtual interrupt delivery.
6352 */
6353 if (kvm_x86_ops->hwapic_irr_update)
6354 kvm_x86_ops->hwapic_irr_update(vcpu,
6355 kvm_lapic_find_highest_irr(vcpu));
6356 update_cr8_intercept(vcpu);
6357 kvm_lapic_sync_to_vapic(vcpu);
6358 }
6359 }
6360
6361 r = kvm_mmu_reload(vcpu);
6362 if (unlikely(r)) {
6363 goto cancel_injection;
6364 }
6365
6366 preempt_disable();
6367
6368 kvm_x86_ops->prepare_guest_switch(vcpu);
6369 if (vcpu->fpu_active)
6370 kvm_load_guest_fpu(vcpu);
6371 kvm_load_guest_xcr0(vcpu);
6372
6373 vcpu->mode = IN_GUEST_MODE;
6374
6375 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6376
6377 /* We should set ->mode before check ->requests,
6378 * see the comment in make_all_cpus_request.
6379 */
6380 smp_mb__after_srcu_read_unlock();
6381
6382 local_irq_disable();
6383
6384 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6385 || need_resched() || signal_pending(current)) {
6386 vcpu->mode = OUTSIDE_GUEST_MODE;
6387 smp_wmb();
6388 local_irq_enable();
6389 preempt_enable();
6390 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6391 r = 1;
6392 goto cancel_injection;
6393 }
6394
6395 if (req_immediate_exit)
6396 smp_send_reschedule(vcpu->cpu);
6397
6398 __kvm_guest_enter();
6399
6400 if (unlikely(vcpu->arch.switch_db_regs)) {
6401 set_debugreg(0, 7);
6402 set_debugreg(vcpu->arch.eff_db[0], 0);
6403 set_debugreg(vcpu->arch.eff_db[1], 1);
6404 set_debugreg(vcpu->arch.eff_db[2], 2);
6405 set_debugreg(vcpu->arch.eff_db[3], 3);
6406 set_debugreg(vcpu->arch.dr6, 6);
6407 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6408 }
6409
6410 trace_kvm_entry(vcpu->vcpu_id);
6411 wait_lapic_expire(vcpu);
6412 kvm_x86_ops->run(vcpu);
6413
6414 /*
6415 * Do this here before restoring debug registers on the host. And
6416 * since we do this before handling the vmexit, a DR access vmexit
6417 * can (a) read the correct value of the debug registers, (b) set
6418 * KVM_DEBUGREG_WONT_EXIT again.
6419 */
6420 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6421 int i;
6422
6423 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6424 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6425 for (i = 0; i < KVM_NR_DB_REGS; i++)
6426 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6427 }
6428
6429 /*
6430 * If the guest has used debug registers, at least dr7
6431 * will be disabled while returning to the host.
6432 * If we don't have active breakpoints in the host, we don't
6433 * care about the messed up debug address registers. But if
6434 * we have some of them active, restore the old state.
6435 */
6436 if (hw_breakpoint_active())
6437 hw_breakpoint_restore();
6438
6439 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6440 rdtsc());
6441
6442 vcpu->mode = OUTSIDE_GUEST_MODE;
6443 smp_wmb();
6444
6445 /* Interrupt is enabled by handle_external_intr() */
6446 kvm_x86_ops->handle_external_intr(vcpu);
6447
6448 ++vcpu->stat.exits;
6449
6450 /*
6451 * We must have an instruction between local_irq_enable() and
6452 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6453 * the interrupt shadow. The stat.exits increment will do nicely.
6454 * But we need to prevent reordering, hence this barrier():
6455 */
6456 barrier();
6457
6458 kvm_guest_exit();
6459
6460 preempt_enable();
6461
6462 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6463
6464 /*
6465 * Profile KVM exit RIPs:
6466 */
6467 if (unlikely(prof_on == KVM_PROFILING)) {
6468 unsigned long rip = kvm_rip_read(vcpu);
6469 profile_hit(KVM_PROFILING, (void *)rip);
6470 }
6471
6472 if (unlikely(vcpu->arch.tsc_always_catchup))
6473 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6474
6475 if (vcpu->arch.apic_attention)
6476 kvm_lapic_sync_from_vapic(vcpu);
6477
6478 r = kvm_x86_ops->handle_exit(vcpu);
6479 return r;
6480
6481 cancel_injection:
6482 kvm_x86_ops->cancel_injection(vcpu);
6483 if (unlikely(vcpu->arch.apic_attention))
6484 kvm_lapic_sync_from_vapic(vcpu);
6485 out:
6486 return r;
6487 }
6488
6489 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6490 {
6491 if (!kvm_arch_vcpu_runnable(vcpu)) {
6492 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6493 kvm_vcpu_block(vcpu);
6494 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6495 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6496 return 1;
6497 }
6498
6499 kvm_apic_accept_events(vcpu);
6500 switch(vcpu->arch.mp_state) {
6501 case KVM_MP_STATE_HALTED:
6502 vcpu->arch.pv.pv_unhalted = false;
6503 vcpu->arch.mp_state =
6504 KVM_MP_STATE_RUNNABLE;
6505 case KVM_MP_STATE_RUNNABLE:
6506 vcpu->arch.apf.halted = false;
6507 break;
6508 case KVM_MP_STATE_INIT_RECEIVED:
6509 break;
6510 default:
6511 return -EINTR;
6512 break;
6513 }
6514 return 1;
6515 }
6516
6517 static int vcpu_run(struct kvm_vcpu *vcpu)
6518 {
6519 int r;
6520 struct kvm *kvm = vcpu->kvm;
6521
6522 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6523
6524 for (;;) {
6525 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6526 !vcpu->arch.apf.halted)
6527 r = vcpu_enter_guest(vcpu);
6528 else
6529 r = vcpu_block(kvm, vcpu);
6530 if (r <= 0)
6531 break;
6532
6533 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6534 if (kvm_cpu_has_pending_timer(vcpu))
6535 kvm_inject_pending_timer_irqs(vcpu);
6536
6537 if (dm_request_for_irq_injection(vcpu)) {
6538 r = 0;
6539 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6540 ++vcpu->stat.request_irq_exits;
6541 break;
6542 }
6543
6544 kvm_check_async_pf_completion(vcpu);
6545
6546 if (signal_pending(current)) {
6547 r = -EINTR;
6548 vcpu->run->exit_reason = KVM_EXIT_INTR;
6549 ++vcpu->stat.signal_exits;
6550 break;
6551 }
6552 if (need_resched()) {
6553 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6554 cond_resched();
6555 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6556 }
6557 }
6558
6559 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6560
6561 return r;
6562 }
6563
6564 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6565 {
6566 int r;
6567 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6568 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6569 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6570 if (r != EMULATE_DONE)
6571 return 0;
6572 return 1;
6573 }
6574
6575 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6576 {
6577 BUG_ON(!vcpu->arch.pio.count);
6578
6579 return complete_emulated_io(vcpu);
6580 }
6581
6582 /*
6583 * Implements the following, as a state machine:
6584 *
6585 * read:
6586 * for each fragment
6587 * for each mmio piece in the fragment
6588 * write gpa, len
6589 * exit
6590 * copy data
6591 * execute insn
6592 *
6593 * write:
6594 * for each fragment
6595 * for each mmio piece in the fragment
6596 * write gpa, len
6597 * copy data
6598 * exit
6599 */
6600 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6601 {
6602 struct kvm_run *run = vcpu->run;
6603 struct kvm_mmio_fragment *frag;
6604 unsigned len;
6605
6606 BUG_ON(!vcpu->mmio_needed);
6607
6608 /* Complete previous fragment */
6609 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6610 len = min(8u, frag->len);
6611 if (!vcpu->mmio_is_write)
6612 memcpy(frag->data, run->mmio.data, len);
6613
6614 if (frag->len <= 8) {
6615 /* Switch to the next fragment. */
6616 frag++;
6617 vcpu->mmio_cur_fragment++;
6618 } else {
6619 /* Go forward to the next mmio piece. */
6620 frag->data += len;
6621 frag->gpa += len;
6622 frag->len -= len;
6623 }
6624
6625 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6626 vcpu->mmio_needed = 0;
6627
6628 /* FIXME: return into emulator if single-stepping. */
6629 if (vcpu->mmio_is_write)
6630 return 1;
6631 vcpu->mmio_read_completed = 1;
6632 return complete_emulated_io(vcpu);
6633 }
6634
6635 run->exit_reason = KVM_EXIT_MMIO;
6636 run->mmio.phys_addr = frag->gpa;
6637 if (vcpu->mmio_is_write)
6638 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6639 run->mmio.len = min(8u, frag->len);
6640 run->mmio.is_write = vcpu->mmio_is_write;
6641 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6642 return 0;
6643 }
6644
6645
6646 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6647 {
6648 struct fpu *fpu = &current->thread.fpu;
6649 int r;
6650 sigset_t sigsaved;
6651
6652 fpu__activate_curr(fpu);
6653
6654 if (vcpu->sigset_active)
6655 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6656
6657 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6658 kvm_vcpu_block(vcpu);
6659 kvm_apic_accept_events(vcpu);
6660 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6661 r = -EAGAIN;
6662 goto out;
6663 }
6664
6665 /* re-sync apic's tpr */
6666 if (!lapic_in_kernel(vcpu)) {
6667 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6668 r = -EINVAL;
6669 goto out;
6670 }
6671 }
6672
6673 if (unlikely(vcpu->arch.complete_userspace_io)) {
6674 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6675 vcpu->arch.complete_userspace_io = NULL;
6676 r = cui(vcpu);
6677 if (r <= 0)
6678 goto out;
6679 } else
6680 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6681
6682 r = vcpu_run(vcpu);
6683
6684 out:
6685 post_kvm_run_save(vcpu);
6686 if (vcpu->sigset_active)
6687 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6688
6689 return r;
6690 }
6691
6692 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6693 {
6694 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6695 /*
6696 * We are here if userspace calls get_regs() in the middle of
6697 * instruction emulation. Registers state needs to be copied
6698 * back from emulation context to vcpu. Userspace shouldn't do
6699 * that usually, but some bad designed PV devices (vmware
6700 * backdoor interface) need this to work
6701 */
6702 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6703 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6704 }
6705 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6706 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6707 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6708 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6709 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6710 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6711 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6712 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6713 #ifdef CONFIG_X86_64
6714 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6715 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6716 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6717 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6718 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6719 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6720 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6721 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6722 #endif
6723
6724 regs->rip = kvm_rip_read(vcpu);
6725 regs->rflags = kvm_get_rflags(vcpu);
6726
6727 return 0;
6728 }
6729
6730 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6731 {
6732 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6733 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6734
6735 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6736 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6737 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6738 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6739 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6740 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6741 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6742 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6743 #ifdef CONFIG_X86_64
6744 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6745 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6746 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6747 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6748 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6749 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6750 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6751 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6752 #endif
6753
6754 kvm_rip_write(vcpu, regs->rip);
6755 kvm_set_rflags(vcpu, regs->rflags);
6756
6757 vcpu->arch.exception.pending = false;
6758
6759 kvm_make_request(KVM_REQ_EVENT, vcpu);
6760
6761 return 0;
6762 }
6763
6764 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6765 {
6766 struct kvm_segment cs;
6767
6768 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6769 *db = cs.db;
6770 *l = cs.l;
6771 }
6772 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6773
6774 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6775 struct kvm_sregs *sregs)
6776 {
6777 struct desc_ptr dt;
6778
6779 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6780 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6781 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6782 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6783 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6784 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6785
6786 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6787 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6788
6789 kvm_x86_ops->get_idt(vcpu, &dt);
6790 sregs->idt.limit = dt.size;
6791 sregs->idt.base = dt.address;
6792 kvm_x86_ops->get_gdt(vcpu, &dt);
6793 sregs->gdt.limit = dt.size;
6794 sregs->gdt.base = dt.address;
6795
6796 sregs->cr0 = kvm_read_cr0(vcpu);
6797 sregs->cr2 = vcpu->arch.cr2;
6798 sregs->cr3 = kvm_read_cr3(vcpu);
6799 sregs->cr4 = kvm_read_cr4(vcpu);
6800 sregs->cr8 = kvm_get_cr8(vcpu);
6801 sregs->efer = vcpu->arch.efer;
6802 sregs->apic_base = kvm_get_apic_base(vcpu);
6803
6804 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6805
6806 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6807 set_bit(vcpu->arch.interrupt.nr,
6808 (unsigned long *)sregs->interrupt_bitmap);
6809
6810 return 0;
6811 }
6812
6813 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6814 struct kvm_mp_state *mp_state)
6815 {
6816 kvm_apic_accept_events(vcpu);
6817 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6818 vcpu->arch.pv.pv_unhalted)
6819 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6820 else
6821 mp_state->mp_state = vcpu->arch.mp_state;
6822
6823 return 0;
6824 }
6825
6826 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6827 struct kvm_mp_state *mp_state)
6828 {
6829 if (!kvm_vcpu_has_lapic(vcpu) &&
6830 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6831 return -EINVAL;
6832
6833 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6834 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6835 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6836 } else
6837 vcpu->arch.mp_state = mp_state->mp_state;
6838 kvm_make_request(KVM_REQ_EVENT, vcpu);
6839 return 0;
6840 }
6841
6842 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6843 int reason, bool has_error_code, u32 error_code)
6844 {
6845 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6846 int ret;
6847
6848 init_emulate_ctxt(vcpu);
6849
6850 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6851 has_error_code, error_code);
6852
6853 if (ret)
6854 return EMULATE_FAIL;
6855
6856 kvm_rip_write(vcpu, ctxt->eip);
6857 kvm_set_rflags(vcpu, ctxt->eflags);
6858 kvm_make_request(KVM_REQ_EVENT, vcpu);
6859 return EMULATE_DONE;
6860 }
6861 EXPORT_SYMBOL_GPL(kvm_task_switch);
6862
6863 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6864 struct kvm_sregs *sregs)
6865 {
6866 struct msr_data apic_base_msr;
6867 int mmu_reset_needed = 0;
6868 int pending_vec, max_bits, idx;
6869 struct desc_ptr dt;
6870
6871 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6872 return -EINVAL;
6873
6874 dt.size = sregs->idt.limit;
6875 dt.address = sregs->idt.base;
6876 kvm_x86_ops->set_idt(vcpu, &dt);
6877 dt.size = sregs->gdt.limit;
6878 dt.address = sregs->gdt.base;
6879 kvm_x86_ops->set_gdt(vcpu, &dt);
6880
6881 vcpu->arch.cr2 = sregs->cr2;
6882 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6883 vcpu->arch.cr3 = sregs->cr3;
6884 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6885
6886 kvm_set_cr8(vcpu, sregs->cr8);
6887
6888 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6889 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6890 apic_base_msr.data = sregs->apic_base;
6891 apic_base_msr.host_initiated = true;
6892 kvm_set_apic_base(vcpu, &apic_base_msr);
6893
6894 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6895 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6896 vcpu->arch.cr0 = sregs->cr0;
6897
6898 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6899 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6900 if (sregs->cr4 & X86_CR4_OSXSAVE)
6901 kvm_update_cpuid(vcpu);
6902
6903 idx = srcu_read_lock(&vcpu->kvm->srcu);
6904 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6905 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6906 mmu_reset_needed = 1;
6907 }
6908 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6909
6910 if (mmu_reset_needed)
6911 kvm_mmu_reset_context(vcpu);
6912
6913 max_bits = KVM_NR_INTERRUPTS;
6914 pending_vec = find_first_bit(
6915 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6916 if (pending_vec < max_bits) {
6917 kvm_queue_interrupt(vcpu, pending_vec, false);
6918 pr_debug("Set back pending irq %d\n", pending_vec);
6919 }
6920
6921 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6922 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6923 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6924 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6925 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6926 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6927
6928 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6929 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6930
6931 update_cr8_intercept(vcpu);
6932
6933 /* Older userspace won't unhalt the vcpu on reset. */
6934 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6935 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6936 !is_protmode(vcpu))
6937 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6938
6939 kvm_make_request(KVM_REQ_EVENT, vcpu);
6940
6941 return 0;
6942 }
6943
6944 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6945 struct kvm_guest_debug *dbg)
6946 {
6947 unsigned long rflags;
6948 int i, r;
6949
6950 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6951 r = -EBUSY;
6952 if (vcpu->arch.exception.pending)
6953 goto out;
6954 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6955 kvm_queue_exception(vcpu, DB_VECTOR);
6956 else
6957 kvm_queue_exception(vcpu, BP_VECTOR);
6958 }
6959
6960 /*
6961 * Read rflags as long as potentially injected trace flags are still
6962 * filtered out.
6963 */
6964 rflags = kvm_get_rflags(vcpu);
6965
6966 vcpu->guest_debug = dbg->control;
6967 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6968 vcpu->guest_debug = 0;
6969
6970 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6971 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6972 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6973 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6974 } else {
6975 for (i = 0; i < KVM_NR_DB_REGS; i++)
6976 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6977 }
6978 kvm_update_dr7(vcpu);
6979
6980 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6981 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6982 get_segment_base(vcpu, VCPU_SREG_CS);
6983
6984 /*
6985 * Trigger an rflags update that will inject or remove the trace
6986 * flags.
6987 */
6988 kvm_set_rflags(vcpu, rflags);
6989
6990 kvm_x86_ops->update_db_bp_intercept(vcpu);
6991
6992 r = 0;
6993
6994 out:
6995
6996 return r;
6997 }
6998
6999 /*
7000 * Translate a guest virtual address to a guest physical address.
7001 */
7002 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7003 struct kvm_translation *tr)
7004 {
7005 unsigned long vaddr = tr->linear_address;
7006 gpa_t gpa;
7007 int idx;
7008
7009 idx = srcu_read_lock(&vcpu->kvm->srcu);
7010 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7011 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7012 tr->physical_address = gpa;
7013 tr->valid = gpa != UNMAPPED_GVA;
7014 tr->writeable = 1;
7015 tr->usermode = 0;
7016
7017 return 0;
7018 }
7019
7020 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7021 {
7022 struct fxregs_state *fxsave =
7023 &vcpu->arch.guest_fpu.state.fxsave;
7024
7025 memcpy(fpu->fpr, fxsave->st_space, 128);
7026 fpu->fcw = fxsave->cwd;
7027 fpu->fsw = fxsave->swd;
7028 fpu->ftwx = fxsave->twd;
7029 fpu->last_opcode = fxsave->fop;
7030 fpu->last_ip = fxsave->rip;
7031 fpu->last_dp = fxsave->rdp;
7032 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7033
7034 return 0;
7035 }
7036
7037 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7038 {
7039 struct fxregs_state *fxsave =
7040 &vcpu->arch.guest_fpu.state.fxsave;
7041
7042 memcpy(fxsave->st_space, fpu->fpr, 128);
7043 fxsave->cwd = fpu->fcw;
7044 fxsave->swd = fpu->fsw;
7045 fxsave->twd = fpu->ftwx;
7046 fxsave->fop = fpu->last_opcode;
7047 fxsave->rip = fpu->last_ip;
7048 fxsave->rdp = fpu->last_dp;
7049 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7050
7051 return 0;
7052 }
7053
7054 static void fx_init(struct kvm_vcpu *vcpu)
7055 {
7056 fpstate_init(&vcpu->arch.guest_fpu.state);
7057 if (cpu_has_xsaves)
7058 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7059 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7060
7061 /*
7062 * Ensure guest xcr0 is valid for loading
7063 */
7064 vcpu->arch.xcr0 = XSTATE_FP;
7065
7066 vcpu->arch.cr0 |= X86_CR0_ET;
7067 }
7068
7069 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7070 {
7071 if (vcpu->guest_fpu_loaded)
7072 return;
7073
7074 /*
7075 * Restore all possible states in the guest,
7076 * and assume host would use all available bits.
7077 * Guest xcr0 would be loaded later.
7078 */
7079 kvm_put_guest_xcr0(vcpu);
7080 vcpu->guest_fpu_loaded = 1;
7081 __kernel_fpu_begin();
7082 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7083 trace_kvm_fpu(1);
7084 }
7085
7086 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7087 {
7088 kvm_put_guest_xcr0(vcpu);
7089
7090 if (!vcpu->guest_fpu_loaded) {
7091 vcpu->fpu_counter = 0;
7092 return;
7093 }
7094
7095 vcpu->guest_fpu_loaded = 0;
7096 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7097 __kernel_fpu_end();
7098 ++vcpu->stat.fpu_reload;
7099 /*
7100 * If using eager FPU mode, or if the guest is a frequent user
7101 * of the FPU, just leave the FPU active for next time.
7102 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7103 * the FPU in bursts will revert to loading it on demand.
7104 */
7105 if (!vcpu->arch.eager_fpu) {
7106 if (++vcpu->fpu_counter < 5)
7107 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7108 }
7109 trace_kvm_fpu(0);
7110 }
7111
7112 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7113 {
7114 kvmclock_reset(vcpu);
7115
7116 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7117 kvm_x86_ops->vcpu_free(vcpu);
7118 }
7119
7120 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7121 unsigned int id)
7122 {
7123 struct kvm_vcpu *vcpu;
7124
7125 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7126 printk_once(KERN_WARNING
7127 "kvm: SMP vm created on host with unstable TSC; "
7128 "guest TSC will not be reliable\n");
7129
7130 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7131
7132 return vcpu;
7133 }
7134
7135 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7136 {
7137 int r;
7138
7139 kvm_vcpu_mtrr_init(vcpu);
7140 r = vcpu_load(vcpu);
7141 if (r)
7142 return r;
7143 kvm_vcpu_reset(vcpu, false);
7144 kvm_mmu_setup(vcpu);
7145 vcpu_put(vcpu);
7146 return r;
7147 }
7148
7149 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7150 {
7151 struct msr_data msr;
7152 struct kvm *kvm = vcpu->kvm;
7153
7154 if (vcpu_load(vcpu))
7155 return;
7156 msr.data = 0x0;
7157 msr.index = MSR_IA32_TSC;
7158 msr.host_initiated = true;
7159 kvm_write_tsc(vcpu, &msr);
7160 vcpu_put(vcpu);
7161
7162 if (!kvmclock_periodic_sync)
7163 return;
7164
7165 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7166 KVMCLOCK_SYNC_PERIOD);
7167 }
7168
7169 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7170 {
7171 int r;
7172 vcpu->arch.apf.msr_val = 0;
7173
7174 r = vcpu_load(vcpu);
7175 BUG_ON(r);
7176 kvm_mmu_unload(vcpu);
7177 vcpu_put(vcpu);
7178
7179 kvm_x86_ops->vcpu_free(vcpu);
7180 }
7181
7182 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7183 {
7184 vcpu->arch.hflags = 0;
7185
7186 atomic_set(&vcpu->arch.nmi_queued, 0);
7187 vcpu->arch.nmi_pending = 0;
7188 vcpu->arch.nmi_injected = false;
7189 kvm_clear_interrupt_queue(vcpu);
7190 kvm_clear_exception_queue(vcpu);
7191
7192 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7193 kvm_update_dr0123(vcpu);
7194 vcpu->arch.dr6 = DR6_INIT;
7195 kvm_update_dr6(vcpu);
7196 vcpu->arch.dr7 = DR7_FIXED_1;
7197 kvm_update_dr7(vcpu);
7198
7199 vcpu->arch.cr2 = 0;
7200
7201 kvm_make_request(KVM_REQ_EVENT, vcpu);
7202 vcpu->arch.apf.msr_val = 0;
7203 vcpu->arch.st.msr_val = 0;
7204
7205 kvmclock_reset(vcpu);
7206
7207 kvm_clear_async_pf_completion_queue(vcpu);
7208 kvm_async_pf_hash_reset(vcpu);
7209 vcpu->arch.apf.halted = false;
7210
7211 if (!init_event) {
7212 kvm_pmu_reset(vcpu);
7213 vcpu->arch.smbase = 0x30000;
7214 }
7215
7216 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7217 vcpu->arch.regs_avail = ~0;
7218 vcpu->arch.regs_dirty = ~0;
7219
7220 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7221 }
7222
7223 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7224 {
7225 struct kvm_segment cs;
7226
7227 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7228 cs.selector = vector << 8;
7229 cs.base = vector << 12;
7230 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7231 kvm_rip_write(vcpu, 0);
7232 }
7233
7234 int kvm_arch_hardware_enable(void)
7235 {
7236 struct kvm *kvm;
7237 struct kvm_vcpu *vcpu;
7238 int i;
7239 int ret;
7240 u64 local_tsc;
7241 u64 max_tsc = 0;
7242 bool stable, backwards_tsc = false;
7243
7244 kvm_shared_msr_cpu_online();
7245 ret = kvm_x86_ops->hardware_enable();
7246 if (ret != 0)
7247 return ret;
7248
7249 local_tsc = rdtsc();
7250 stable = !check_tsc_unstable();
7251 list_for_each_entry(kvm, &vm_list, vm_list) {
7252 kvm_for_each_vcpu(i, vcpu, kvm) {
7253 if (!stable && vcpu->cpu == smp_processor_id())
7254 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7255 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7256 backwards_tsc = true;
7257 if (vcpu->arch.last_host_tsc > max_tsc)
7258 max_tsc = vcpu->arch.last_host_tsc;
7259 }
7260 }
7261 }
7262
7263 /*
7264 * Sometimes, even reliable TSCs go backwards. This happens on
7265 * platforms that reset TSC during suspend or hibernate actions, but
7266 * maintain synchronization. We must compensate. Fortunately, we can
7267 * detect that condition here, which happens early in CPU bringup,
7268 * before any KVM threads can be running. Unfortunately, we can't
7269 * bring the TSCs fully up to date with real time, as we aren't yet far
7270 * enough into CPU bringup that we know how much real time has actually
7271 * elapsed; our helper function, get_kernel_ns() will be using boot
7272 * variables that haven't been updated yet.
7273 *
7274 * So we simply find the maximum observed TSC above, then record the
7275 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7276 * the adjustment will be applied. Note that we accumulate
7277 * adjustments, in case multiple suspend cycles happen before some VCPU
7278 * gets a chance to run again. In the event that no KVM threads get a
7279 * chance to run, we will miss the entire elapsed period, as we'll have
7280 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7281 * loose cycle time. This isn't too big a deal, since the loss will be
7282 * uniform across all VCPUs (not to mention the scenario is extremely
7283 * unlikely). It is possible that a second hibernate recovery happens
7284 * much faster than a first, causing the observed TSC here to be
7285 * smaller; this would require additional padding adjustment, which is
7286 * why we set last_host_tsc to the local tsc observed here.
7287 *
7288 * N.B. - this code below runs only on platforms with reliable TSC,
7289 * as that is the only way backwards_tsc is set above. Also note
7290 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7291 * have the same delta_cyc adjustment applied if backwards_tsc
7292 * is detected. Note further, this adjustment is only done once,
7293 * as we reset last_host_tsc on all VCPUs to stop this from being
7294 * called multiple times (one for each physical CPU bringup).
7295 *
7296 * Platforms with unreliable TSCs don't have to deal with this, they
7297 * will be compensated by the logic in vcpu_load, which sets the TSC to
7298 * catchup mode. This will catchup all VCPUs to real time, but cannot
7299 * guarantee that they stay in perfect synchronization.
7300 */
7301 if (backwards_tsc) {
7302 u64 delta_cyc = max_tsc - local_tsc;
7303 backwards_tsc_observed = true;
7304 list_for_each_entry(kvm, &vm_list, vm_list) {
7305 kvm_for_each_vcpu(i, vcpu, kvm) {
7306 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7307 vcpu->arch.last_host_tsc = local_tsc;
7308 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7309 }
7310
7311 /*
7312 * We have to disable TSC offset matching.. if you were
7313 * booting a VM while issuing an S4 host suspend....
7314 * you may have some problem. Solving this issue is
7315 * left as an exercise to the reader.
7316 */
7317 kvm->arch.last_tsc_nsec = 0;
7318 kvm->arch.last_tsc_write = 0;
7319 }
7320
7321 }
7322 return 0;
7323 }
7324
7325 void kvm_arch_hardware_disable(void)
7326 {
7327 kvm_x86_ops->hardware_disable();
7328 drop_user_return_notifiers();
7329 }
7330
7331 int kvm_arch_hardware_setup(void)
7332 {
7333 int r;
7334
7335 r = kvm_x86_ops->hardware_setup();
7336 if (r != 0)
7337 return r;
7338
7339 kvm_init_msr_list();
7340 return 0;
7341 }
7342
7343 void kvm_arch_hardware_unsetup(void)
7344 {
7345 kvm_x86_ops->hardware_unsetup();
7346 }
7347
7348 void kvm_arch_check_processor_compat(void *rtn)
7349 {
7350 kvm_x86_ops->check_processor_compatibility(rtn);
7351 }
7352
7353 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7354 {
7355 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7356 }
7357 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7358
7359 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7360 {
7361 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7362 }
7363
7364 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7365 {
7366 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7367 }
7368
7369 struct static_key kvm_no_apic_vcpu __read_mostly;
7370
7371 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7372 {
7373 struct page *page;
7374 struct kvm *kvm;
7375 int r;
7376
7377 BUG_ON(vcpu->kvm == NULL);
7378 kvm = vcpu->kvm;
7379
7380 vcpu->arch.pv.pv_unhalted = false;
7381 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7382 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7383 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7384 else
7385 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7386
7387 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7388 if (!page) {
7389 r = -ENOMEM;
7390 goto fail;
7391 }
7392 vcpu->arch.pio_data = page_address(page);
7393
7394 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7395
7396 r = kvm_mmu_create(vcpu);
7397 if (r < 0)
7398 goto fail_free_pio_data;
7399
7400 if (irqchip_in_kernel(kvm)) {
7401 r = kvm_create_lapic(vcpu);
7402 if (r < 0)
7403 goto fail_mmu_destroy;
7404 } else
7405 static_key_slow_inc(&kvm_no_apic_vcpu);
7406
7407 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7408 GFP_KERNEL);
7409 if (!vcpu->arch.mce_banks) {
7410 r = -ENOMEM;
7411 goto fail_free_lapic;
7412 }
7413 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7414
7415 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7416 r = -ENOMEM;
7417 goto fail_free_mce_banks;
7418 }
7419
7420 fx_init(vcpu);
7421
7422 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7423 vcpu->arch.pv_time_enabled = false;
7424
7425 vcpu->arch.guest_supported_xcr0 = 0;
7426 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7427
7428 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7429
7430 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7431
7432 kvm_async_pf_hash_reset(vcpu);
7433 kvm_pmu_init(vcpu);
7434
7435 vcpu->arch.pending_external_vector = -1;
7436
7437 return 0;
7438
7439 fail_free_mce_banks:
7440 kfree(vcpu->arch.mce_banks);
7441 fail_free_lapic:
7442 kvm_free_lapic(vcpu);
7443 fail_mmu_destroy:
7444 kvm_mmu_destroy(vcpu);
7445 fail_free_pio_data:
7446 free_page((unsigned long)vcpu->arch.pio_data);
7447 fail:
7448 return r;
7449 }
7450
7451 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7452 {
7453 int idx;
7454
7455 kvm_pmu_destroy(vcpu);
7456 kfree(vcpu->arch.mce_banks);
7457 kvm_free_lapic(vcpu);
7458 idx = srcu_read_lock(&vcpu->kvm->srcu);
7459 kvm_mmu_destroy(vcpu);
7460 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7461 free_page((unsigned long)vcpu->arch.pio_data);
7462 if (!lapic_in_kernel(vcpu))
7463 static_key_slow_dec(&kvm_no_apic_vcpu);
7464 }
7465
7466 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7467 {
7468 kvm_x86_ops->sched_in(vcpu, cpu);
7469 }
7470
7471 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7472 {
7473 if (type)
7474 return -EINVAL;
7475
7476 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7477 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7478 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7479 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7480 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7481
7482 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7483 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7484 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7485 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7486 &kvm->arch.irq_sources_bitmap);
7487
7488 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7489 mutex_init(&kvm->arch.apic_map_lock);
7490 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7491
7492 pvclock_update_vm_gtod_copy(kvm);
7493
7494 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7495 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7496
7497 return 0;
7498 }
7499
7500 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7501 {
7502 int r;
7503 r = vcpu_load(vcpu);
7504 BUG_ON(r);
7505 kvm_mmu_unload(vcpu);
7506 vcpu_put(vcpu);
7507 }
7508
7509 static void kvm_free_vcpus(struct kvm *kvm)
7510 {
7511 unsigned int i;
7512 struct kvm_vcpu *vcpu;
7513
7514 /*
7515 * Unpin any mmu pages first.
7516 */
7517 kvm_for_each_vcpu(i, vcpu, kvm) {
7518 kvm_clear_async_pf_completion_queue(vcpu);
7519 kvm_unload_vcpu_mmu(vcpu);
7520 }
7521 kvm_for_each_vcpu(i, vcpu, kvm)
7522 kvm_arch_vcpu_free(vcpu);
7523
7524 mutex_lock(&kvm->lock);
7525 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7526 kvm->vcpus[i] = NULL;
7527
7528 atomic_set(&kvm->online_vcpus, 0);
7529 mutex_unlock(&kvm->lock);
7530 }
7531
7532 void kvm_arch_sync_events(struct kvm *kvm)
7533 {
7534 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7535 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7536 kvm_free_all_assigned_devices(kvm);
7537 kvm_free_pit(kvm);
7538 }
7539
7540 int __x86_set_memory_region(struct kvm *kvm,
7541 const struct kvm_userspace_memory_region *mem)
7542 {
7543 int i, r;
7544
7545 /* Called with kvm->slots_lock held. */
7546 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7547
7548 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7549 struct kvm_userspace_memory_region m = *mem;
7550
7551 m.slot |= i << 16;
7552 r = __kvm_set_memory_region(kvm, &m);
7553 if (r < 0)
7554 return r;
7555 }
7556
7557 return 0;
7558 }
7559 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7560
7561 int x86_set_memory_region(struct kvm *kvm,
7562 const struct kvm_userspace_memory_region *mem)
7563 {
7564 int r;
7565
7566 mutex_lock(&kvm->slots_lock);
7567 r = __x86_set_memory_region(kvm, mem);
7568 mutex_unlock(&kvm->slots_lock);
7569
7570 return r;
7571 }
7572 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7573
7574 void kvm_arch_destroy_vm(struct kvm *kvm)
7575 {
7576 if (current->mm == kvm->mm) {
7577 /*
7578 * Free memory regions allocated on behalf of userspace,
7579 * unless the the memory map has changed due to process exit
7580 * or fd copying.
7581 */
7582 struct kvm_userspace_memory_region mem;
7583 memset(&mem, 0, sizeof(mem));
7584 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7585 x86_set_memory_region(kvm, &mem);
7586
7587 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7588 x86_set_memory_region(kvm, &mem);
7589
7590 mem.slot = TSS_PRIVATE_MEMSLOT;
7591 x86_set_memory_region(kvm, &mem);
7592 }
7593 kvm_iommu_unmap_guest(kvm);
7594 kfree(kvm->arch.vpic);
7595 kfree(kvm->arch.vioapic);
7596 kvm_free_vcpus(kvm);
7597 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7598 }
7599
7600 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7601 struct kvm_memory_slot *dont)
7602 {
7603 int i;
7604
7605 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7606 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7607 kvfree(free->arch.rmap[i]);
7608 free->arch.rmap[i] = NULL;
7609 }
7610 if (i == 0)
7611 continue;
7612
7613 if (!dont || free->arch.lpage_info[i - 1] !=
7614 dont->arch.lpage_info[i - 1]) {
7615 kvfree(free->arch.lpage_info[i - 1]);
7616 free->arch.lpage_info[i - 1] = NULL;
7617 }
7618 }
7619 }
7620
7621 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7622 unsigned long npages)
7623 {
7624 int i;
7625
7626 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7627 unsigned long ugfn;
7628 int lpages;
7629 int level = i + 1;
7630
7631 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7632 slot->base_gfn, level) + 1;
7633
7634 slot->arch.rmap[i] =
7635 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7636 if (!slot->arch.rmap[i])
7637 goto out_free;
7638 if (i == 0)
7639 continue;
7640
7641 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7642 sizeof(*slot->arch.lpage_info[i - 1]));
7643 if (!slot->arch.lpage_info[i - 1])
7644 goto out_free;
7645
7646 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7647 slot->arch.lpage_info[i - 1][0].write_count = 1;
7648 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7649 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7650 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7651 /*
7652 * If the gfn and userspace address are not aligned wrt each
7653 * other, or if explicitly asked to, disable large page
7654 * support for this slot
7655 */
7656 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7657 !kvm_largepages_enabled()) {
7658 unsigned long j;
7659
7660 for (j = 0; j < lpages; ++j)
7661 slot->arch.lpage_info[i - 1][j].write_count = 1;
7662 }
7663 }
7664
7665 return 0;
7666
7667 out_free:
7668 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7669 kvfree(slot->arch.rmap[i]);
7670 slot->arch.rmap[i] = NULL;
7671 if (i == 0)
7672 continue;
7673
7674 kvfree(slot->arch.lpage_info[i - 1]);
7675 slot->arch.lpage_info[i - 1] = NULL;
7676 }
7677 return -ENOMEM;
7678 }
7679
7680 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7681 {
7682 /*
7683 * memslots->generation has been incremented.
7684 * mmio generation may have reached its maximum value.
7685 */
7686 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7687 }
7688
7689 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7690 struct kvm_memory_slot *memslot,
7691 const struct kvm_userspace_memory_region *mem,
7692 enum kvm_mr_change change)
7693 {
7694 /*
7695 * Only private memory slots need to be mapped here since
7696 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7697 */
7698 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7699 unsigned long userspace_addr;
7700
7701 /*
7702 * MAP_SHARED to prevent internal slot pages from being moved
7703 * by fork()/COW.
7704 */
7705 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7706 PROT_READ | PROT_WRITE,
7707 MAP_SHARED | MAP_ANONYMOUS, 0);
7708
7709 if (IS_ERR((void *)userspace_addr))
7710 return PTR_ERR((void *)userspace_addr);
7711
7712 memslot->userspace_addr = userspace_addr;
7713 }
7714
7715 return 0;
7716 }
7717
7718 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7719 struct kvm_memory_slot *new)
7720 {
7721 /* Still write protect RO slot */
7722 if (new->flags & KVM_MEM_READONLY) {
7723 kvm_mmu_slot_remove_write_access(kvm, new);
7724 return;
7725 }
7726
7727 /*
7728 * Call kvm_x86_ops dirty logging hooks when they are valid.
7729 *
7730 * kvm_x86_ops->slot_disable_log_dirty is called when:
7731 *
7732 * - KVM_MR_CREATE with dirty logging is disabled
7733 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7734 *
7735 * The reason is, in case of PML, we need to set D-bit for any slots
7736 * with dirty logging disabled in order to eliminate unnecessary GPA
7737 * logging in PML buffer (and potential PML buffer full VMEXT). This
7738 * guarantees leaving PML enabled during guest's lifetime won't have
7739 * any additonal overhead from PML when guest is running with dirty
7740 * logging disabled for memory slots.
7741 *
7742 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7743 * to dirty logging mode.
7744 *
7745 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7746 *
7747 * In case of write protect:
7748 *
7749 * Write protect all pages for dirty logging.
7750 *
7751 * All the sptes including the large sptes which point to this
7752 * slot are set to readonly. We can not create any new large
7753 * spte on this slot until the end of the logging.
7754 *
7755 * See the comments in fast_page_fault().
7756 */
7757 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7758 if (kvm_x86_ops->slot_enable_log_dirty)
7759 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7760 else
7761 kvm_mmu_slot_remove_write_access(kvm, new);
7762 } else {
7763 if (kvm_x86_ops->slot_disable_log_dirty)
7764 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7765 }
7766 }
7767
7768 void kvm_arch_commit_memory_region(struct kvm *kvm,
7769 const struct kvm_userspace_memory_region *mem,
7770 const struct kvm_memory_slot *old,
7771 const struct kvm_memory_slot *new,
7772 enum kvm_mr_change change)
7773 {
7774 int nr_mmu_pages = 0;
7775
7776 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7777 int ret;
7778
7779 ret = vm_munmap(old->userspace_addr,
7780 old->npages * PAGE_SIZE);
7781 if (ret < 0)
7782 printk(KERN_WARNING
7783 "kvm_vm_ioctl_set_memory_region: "
7784 "failed to munmap memory\n");
7785 }
7786
7787 if (!kvm->arch.n_requested_mmu_pages)
7788 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7789
7790 if (nr_mmu_pages)
7791 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7792
7793 /*
7794 * Dirty logging tracks sptes in 4k granularity, meaning that large
7795 * sptes have to be split. If live migration is successful, the guest
7796 * in the source machine will be destroyed and large sptes will be
7797 * created in the destination. However, if the guest continues to run
7798 * in the source machine (for example if live migration fails), small
7799 * sptes will remain around and cause bad performance.
7800 *
7801 * Scan sptes if dirty logging has been stopped, dropping those
7802 * which can be collapsed into a single large-page spte. Later
7803 * page faults will create the large-page sptes.
7804 */
7805 if ((change != KVM_MR_DELETE) &&
7806 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7807 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7808 kvm_mmu_zap_collapsible_sptes(kvm, new);
7809
7810 /*
7811 * Set up write protection and/or dirty logging for the new slot.
7812 *
7813 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7814 * been zapped so no dirty logging staff is needed for old slot. For
7815 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7816 * new and it's also covered when dealing with the new slot.
7817 *
7818 * FIXME: const-ify all uses of struct kvm_memory_slot.
7819 */
7820 if (change != KVM_MR_DELETE)
7821 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7822 }
7823
7824 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7825 {
7826 kvm_mmu_invalidate_zap_all_pages(kvm);
7827 }
7828
7829 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7830 struct kvm_memory_slot *slot)
7831 {
7832 kvm_mmu_invalidate_zap_all_pages(kvm);
7833 }
7834
7835 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7836 {
7837 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7838 kvm_x86_ops->check_nested_events(vcpu, false);
7839
7840 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7841 !vcpu->arch.apf.halted)
7842 || !list_empty_careful(&vcpu->async_pf.done)
7843 || kvm_apic_has_events(vcpu)
7844 || vcpu->arch.pv.pv_unhalted
7845 || atomic_read(&vcpu->arch.nmi_queued) ||
7846 (kvm_arch_interrupt_allowed(vcpu) &&
7847 kvm_cpu_has_interrupt(vcpu));
7848 }
7849
7850 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7851 {
7852 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7853 }
7854
7855 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7856 {
7857 return kvm_x86_ops->interrupt_allowed(vcpu);
7858 }
7859
7860 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7861 {
7862 if (is_64_bit_mode(vcpu))
7863 return kvm_rip_read(vcpu);
7864 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7865 kvm_rip_read(vcpu));
7866 }
7867 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7868
7869 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7870 {
7871 return kvm_get_linear_rip(vcpu) == linear_rip;
7872 }
7873 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7874
7875 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7876 {
7877 unsigned long rflags;
7878
7879 rflags = kvm_x86_ops->get_rflags(vcpu);
7880 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7881 rflags &= ~X86_EFLAGS_TF;
7882 return rflags;
7883 }
7884 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7885
7886 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7887 {
7888 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7889 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7890 rflags |= X86_EFLAGS_TF;
7891 kvm_x86_ops->set_rflags(vcpu, rflags);
7892 }
7893
7894 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7895 {
7896 __kvm_set_rflags(vcpu, rflags);
7897 kvm_make_request(KVM_REQ_EVENT, vcpu);
7898 }
7899 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7900
7901 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7902 {
7903 int r;
7904
7905 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7906 work->wakeup_all)
7907 return;
7908
7909 r = kvm_mmu_reload(vcpu);
7910 if (unlikely(r))
7911 return;
7912
7913 if (!vcpu->arch.mmu.direct_map &&
7914 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7915 return;
7916
7917 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7918 }
7919
7920 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7921 {
7922 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7923 }
7924
7925 static inline u32 kvm_async_pf_next_probe(u32 key)
7926 {
7927 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7928 }
7929
7930 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7931 {
7932 u32 key = kvm_async_pf_hash_fn(gfn);
7933
7934 while (vcpu->arch.apf.gfns[key] != ~0)
7935 key = kvm_async_pf_next_probe(key);
7936
7937 vcpu->arch.apf.gfns[key] = gfn;
7938 }
7939
7940 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7941 {
7942 int i;
7943 u32 key = kvm_async_pf_hash_fn(gfn);
7944
7945 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7946 (vcpu->arch.apf.gfns[key] != gfn &&
7947 vcpu->arch.apf.gfns[key] != ~0); i++)
7948 key = kvm_async_pf_next_probe(key);
7949
7950 return key;
7951 }
7952
7953 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7954 {
7955 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7956 }
7957
7958 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7959 {
7960 u32 i, j, k;
7961
7962 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7963 while (true) {
7964 vcpu->arch.apf.gfns[i] = ~0;
7965 do {
7966 j = kvm_async_pf_next_probe(j);
7967 if (vcpu->arch.apf.gfns[j] == ~0)
7968 return;
7969 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7970 /*
7971 * k lies cyclically in ]i,j]
7972 * | i.k.j |
7973 * |....j i.k.| or |.k..j i...|
7974 */
7975 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7976 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7977 i = j;
7978 }
7979 }
7980
7981 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7982 {
7983
7984 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7985 sizeof(val));
7986 }
7987
7988 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7989 struct kvm_async_pf *work)
7990 {
7991 struct x86_exception fault;
7992
7993 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7994 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7995
7996 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7997 (vcpu->arch.apf.send_user_only &&
7998 kvm_x86_ops->get_cpl(vcpu) == 0))
7999 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8000 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8001 fault.vector = PF_VECTOR;
8002 fault.error_code_valid = true;
8003 fault.error_code = 0;
8004 fault.nested_page_fault = false;
8005 fault.address = work->arch.token;
8006 kvm_inject_page_fault(vcpu, &fault);
8007 }
8008 }
8009
8010 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8011 struct kvm_async_pf *work)
8012 {
8013 struct x86_exception fault;
8014
8015 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8016 if (work->wakeup_all)
8017 work->arch.token = ~0; /* broadcast wakeup */
8018 else
8019 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8020
8021 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8022 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8023 fault.vector = PF_VECTOR;
8024 fault.error_code_valid = true;
8025 fault.error_code = 0;
8026 fault.nested_page_fault = false;
8027 fault.address = work->arch.token;
8028 kvm_inject_page_fault(vcpu, &fault);
8029 }
8030 vcpu->arch.apf.halted = false;
8031 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8032 }
8033
8034 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8035 {
8036 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8037 return true;
8038 else
8039 return !kvm_event_needs_reinjection(vcpu) &&
8040 kvm_x86_ops->interrupt_allowed(vcpu);
8041 }
8042
8043 void kvm_arch_start_assignment(struct kvm *kvm)
8044 {
8045 atomic_inc(&kvm->arch.assigned_device_count);
8046 }
8047 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8048
8049 void kvm_arch_end_assignment(struct kvm *kvm)
8050 {
8051 atomic_dec(&kvm->arch.assigned_device_count);
8052 }
8053 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8054
8055 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8056 {
8057 return atomic_read(&kvm->arch.assigned_device_count);
8058 }
8059 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8060
8061 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8062 {
8063 atomic_inc(&kvm->arch.noncoherent_dma_count);
8064 }
8065 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8066
8067 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8068 {
8069 atomic_dec(&kvm->arch.noncoherent_dma_count);
8070 }
8071 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8072
8073 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8074 {
8075 return atomic_read(&kvm->arch.noncoherent_dma_count);
8076 }
8077 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8078
8079 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8080 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8081 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8082 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8083 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8084 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8085 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8086 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8087 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8088 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8089 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8090 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8091 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8092 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8093 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8094 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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