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KVM: x86: Sync DR7 on KVM_SET_DEBUGREGS
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 return;
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256 return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261 {
262 /* TODO: reserve bits check */
263 kvm_lapic_set_base(vcpu, data);
264 }
265 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
267 asmlinkage void kvm_spurious_fault(void)
268 {
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271 }
272 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
274 #define EXCPT_BENIGN 0
275 #define EXCPT_CONTRIBUTORY 1
276 #define EXCPT_PF 2
277
278 static int exception_class(int vector)
279 {
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293 }
294
295 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
298 {
299 u32 prev_nr;
300 int class1, class2;
301
302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
310 vcpu->arch.exception.reinject = reinject;
311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335 }
336
337 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338 {
339 kvm_multiple_exception(vcpu, nr, false, 0, false);
340 }
341 EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
343 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344 {
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346 }
347 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
349 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
350 {
351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355 }
356 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
357
358 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360 ++vcpu->stat.pf_guest;
361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
363 }
364 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
365
366 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
367 {
368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
370 else
371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
372 }
373
374 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375 {
376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
378 }
379 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
381 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382 {
383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
384 }
385 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
387 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388 {
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390 }
391 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
393 /*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
398 {
399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
403 }
404 EXPORT_SYMBOL_GPL(kvm_require_cpl);
405
406 /*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414 {
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426 }
427 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
429 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431 {
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434 }
435
436 /*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
439 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
440 {
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
446
447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
455 if (is_present_gpte(pdpte[i]) &&
456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
468 out:
469
470 return ret;
471 }
472 EXPORT_SYMBOL_GPL(load_pdptrs);
473
474 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475 {
476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
477 bool changed = true;
478 int offset;
479 gfn_t gfn;
480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
493 if (r < 0)
494 goto out;
495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
496 out:
497
498 return changed;
499 }
500
501 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
502 {
503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
507 cr0 |= X86_CR0_ET;
508
509 #ifdef CONFIG_X86_64
510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
512 #endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
515
516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
518
519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523 #ifdef CONFIG_X86_64
524 if ((vcpu->arch.efer & EFER_LME)) {
525 int cs_db, cs_l;
526
527 if (!is_pae(vcpu))
528 return 1;
529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
530 if (cs_l)
531 return 1;
532 } else
533 #endif
534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
535 kvm_read_cr3(vcpu)))
536 return 1;
537 }
538
539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
542 kvm_x86_ops->set_cr0(vcpu, cr0);
543
544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
545 kvm_clear_async_pf_completion_queue(vcpu);
546 kvm_async_pf_hash_reset(vcpu);
547 }
548
549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
551 return 0;
552 }
553 EXPORT_SYMBOL_GPL(kvm_set_cr0);
554
555 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
556 {
557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
558 }
559 EXPORT_SYMBOL_GPL(kvm_lmsw);
560
561 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562 {
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569 }
570
571 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572 {
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578 }
579
580 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581 {
582 u64 xcr0;
583 u64 valid_bits;
584
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
587 return 1;
588 xcr0 = xcr;
589 if (!(xcr0 & XSTATE_FP))
590 return 1;
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592 return 1;
593
594 /*
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
598 */
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
601 return 1;
602
603 kvm_put_guest_xcr0(vcpu);
604 vcpu->arch.xcr0 = xcr0;
605 return 0;
606 }
607
608 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609 {
610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
612 kvm_inject_gp(vcpu, 0);
613 return 1;
614 }
615 return 0;
616 }
617 EXPORT_SYMBOL_GPL(kvm_set_xcr);
618
619 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
620 {
621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
624 if (cr4 & CR4_RESERVED_BITS)
625 return 1;
626
627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628 return 1;
629
630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631 return 1;
632
633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
634 return 1;
635
636 if (is_long_mode(vcpu)) {
637 if (!(cr4 & X86_CR4_PAE))
638 return 1;
639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
643 return 1;
644
645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
647 return 1;
648
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651 return 1;
652 }
653
654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
655 return 1;
656
657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
659 kvm_mmu_reset_context(vcpu);
660
661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
662 kvm_update_cpuid(vcpu);
663
664 return 0;
665 }
666 EXPORT_SYMBOL_GPL(kvm_set_cr4);
667
668 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
669 {
670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
671 kvm_mmu_sync_roots(vcpu);
672 kvm_mmu_flush_tlb(vcpu);
673 return 0;
674 }
675
676 if (is_long_mode(vcpu)) {
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679 return 1;
680 } else
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 return 1;
683 } else {
684 if (is_pae(vcpu)) {
685 if (cr3 & CR3_PAE_RESERVED_BITS)
686 return 1;
687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
689 return 1;
690 }
691 /*
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
694 */
695 }
696
697 vcpu->arch.cr3 = cr3;
698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
699 kvm_mmu_new_cr3(vcpu);
700 return 0;
701 }
702 EXPORT_SYMBOL_GPL(kvm_set_cr3);
703
704 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
705 {
706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
711 vcpu->arch.cr8 = cr8;
712 return 0;
713 }
714 EXPORT_SYMBOL_GPL(kvm_set_cr8);
715
716 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
717 {
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
721 return vcpu->arch.cr8;
722 }
723 EXPORT_SYMBOL_GPL(kvm_get_cr8);
724
725 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726 {
727 unsigned long dr7;
728
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
731 else
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735 }
736
737 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
738 {
739 switch (dr) {
740 case 0 ... 3:
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
744 break;
745 case 4:
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
748 /* fall through */
749 case 6:
750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753 break;
754 case 5:
755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756 return 1; /* #UD */
757 /* fall through */
758 default: /* 7 */
759 if (val & 0xffffffff00000000ULL)
760 return -1; /* #GP */
761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
762 kvm_update_dr7(vcpu);
763 break;
764 }
765
766 return 0;
767 }
768
769 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770 {
771 int res;
772
773 res = __kvm_set_dr(vcpu, dr, val);
774 if (res > 0)
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 else if (res < 0)
777 kvm_inject_gp(vcpu, 0);
778
779 return res;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_dr);
782
783 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
784 {
785 switch (dr) {
786 case 0 ... 3:
787 *val = vcpu->arch.db[dr];
788 break;
789 case 4:
790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
791 return 1;
792 /* fall through */
793 case 6:
794 *val = vcpu->arch.dr6;
795 break;
796 case 5:
797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
798 return 1;
799 /* fall through */
800 default: /* 7 */
801 *val = vcpu->arch.dr7;
802 break;
803 }
804
805 return 0;
806 }
807
808 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 {
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
812 return 1;
813 }
814 return 0;
815 }
816 EXPORT_SYMBOL_GPL(kvm_get_dr);
817
818 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819 {
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821 u64 data;
822 int err;
823
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825 if (err)
826 return err;
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829 return err;
830 }
831 EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
833 /*
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 *
837 * This list is modified at module load time to reflect the
838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
840 */
841
842 #define KVM_SAVE_MSRS_BEGIN 12
843 static u32 msrs_to_save[] = {
844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
847 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
848 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
849 MSR_KVM_PV_EOI_EN,
850 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
851 MSR_STAR,
852 #ifdef CONFIG_X86_64
853 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
854 #endif
855 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
856 MSR_IA32_FEATURE_CONTROL
857 };
858
859 static unsigned num_msrs_to_save;
860
861 static const u32 emulated_msrs[] = {
862 MSR_IA32_TSC_ADJUST,
863 MSR_IA32_TSCDEADLINE,
864 MSR_IA32_MISC_ENABLE,
865 MSR_IA32_MCG_STATUS,
866 MSR_IA32_MCG_CTL,
867 };
868
869 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
870 {
871 if (efer & efer_reserved_bits)
872 return false;
873
874 if (efer & EFER_FFXSR) {
875 struct kvm_cpuid_entry2 *feat;
876
877 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
878 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
879 return false;
880 }
881
882 if (efer & EFER_SVME) {
883 struct kvm_cpuid_entry2 *feat;
884
885 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
886 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
887 return false;
888 }
889
890 return true;
891 }
892 EXPORT_SYMBOL_GPL(kvm_valid_efer);
893
894 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
895 {
896 u64 old_efer = vcpu->arch.efer;
897
898 if (!kvm_valid_efer(vcpu, efer))
899 return 1;
900
901 if (is_paging(vcpu)
902 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
903 return 1;
904
905 efer &= ~EFER_LMA;
906 efer |= vcpu->arch.efer & EFER_LMA;
907
908 kvm_x86_ops->set_efer(vcpu, efer);
909
910 /* Update reserved bits */
911 if ((efer ^ old_efer) & EFER_NX)
912 kvm_mmu_reset_context(vcpu);
913
914 return 0;
915 }
916
917 void kvm_enable_efer_bits(u64 mask)
918 {
919 efer_reserved_bits &= ~mask;
920 }
921 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
922
923
924 /*
925 * Writes msr value into into the appropriate "register".
926 * Returns 0 on success, non-0 otherwise.
927 * Assumes vcpu_load() was already called.
928 */
929 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
930 {
931 return kvm_x86_ops->set_msr(vcpu, msr);
932 }
933
934 /*
935 * Adapt set_msr() to msr_io()'s calling convention
936 */
937 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
938 {
939 struct msr_data msr;
940
941 msr.data = *data;
942 msr.index = index;
943 msr.host_initiated = true;
944 return kvm_set_msr(vcpu, &msr);
945 }
946
947 #ifdef CONFIG_X86_64
948 struct pvclock_gtod_data {
949 seqcount_t seq;
950
951 struct { /* extract of a clocksource struct */
952 int vclock_mode;
953 cycle_t cycle_last;
954 cycle_t mask;
955 u32 mult;
956 u32 shift;
957 } clock;
958
959 /* open coded 'struct timespec' */
960 u64 monotonic_time_snsec;
961 time_t monotonic_time_sec;
962 };
963
964 static struct pvclock_gtod_data pvclock_gtod_data;
965
966 static void update_pvclock_gtod(struct timekeeper *tk)
967 {
968 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
969
970 write_seqcount_begin(&vdata->seq);
971
972 /* copy pvclock gtod data */
973 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
974 vdata->clock.cycle_last = tk->clock->cycle_last;
975 vdata->clock.mask = tk->clock->mask;
976 vdata->clock.mult = tk->mult;
977 vdata->clock.shift = tk->shift;
978
979 vdata->monotonic_time_sec = tk->xtime_sec
980 + tk->wall_to_monotonic.tv_sec;
981 vdata->monotonic_time_snsec = tk->xtime_nsec
982 + (tk->wall_to_monotonic.tv_nsec
983 << tk->shift);
984 while (vdata->monotonic_time_snsec >=
985 (((u64)NSEC_PER_SEC) << tk->shift)) {
986 vdata->monotonic_time_snsec -=
987 ((u64)NSEC_PER_SEC) << tk->shift;
988 vdata->monotonic_time_sec++;
989 }
990
991 write_seqcount_end(&vdata->seq);
992 }
993 #endif
994
995
996 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
997 {
998 int version;
999 int r;
1000 struct pvclock_wall_clock wc;
1001 struct timespec boot;
1002
1003 if (!wall_clock)
1004 return;
1005
1006 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1007 if (r)
1008 return;
1009
1010 if (version & 1)
1011 ++version; /* first time write, random junk */
1012
1013 ++version;
1014
1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1016
1017 /*
1018 * The guest calculates current wall clock time by adding
1019 * system time (updated by kvm_guest_time_update below) to the
1020 * wall clock specified here. guest system time equals host
1021 * system time for us, thus we must fill in host boot time here.
1022 */
1023 getboottime(&boot);
1024
1025 if (kvm->arch.kvmclock_offset) {
1026 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1027 boot = timespec_sub(boot, ts);
1028 }
1029 wc.sec = boot.tv_sec;
1030 wc.nsec = boot.tv_nsec;
1031 wc.version = version;
1032
1033 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1034
1035 version++;
1036 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1037 }
1038
1039 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1040 {
1041 uint32_t quotient, remainder;
1042
1043 /* Don't try to replace with do_div(), this one calculates
1044 * "(dividend << 32) / divisor" */
1045 __asm__ ( "divl %4"
1046 : "=a" (quotient), "=d" (remainder)
1047 : "0" (0), "1" (dividend), "r" (divisor) );
1048 return quotient;
1049 }
1050
1051 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1052 s8 *pshift, u32 *pmultiplier)
1053 {
1054 uint64_t scaled64;
1055 int32_t shift = 0;
1056 uint64_t tps64;
1057 uint32_t tps32;
1058
1059 tps64 = base_khz * 1000LL;
1060 scaled64 = scaled_khz * 1000LL;
1061 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1062 tps64 >>= 1;
1063 shift--;
1064 }
1065
1066 tps32 = (uint32_t)tps64;
1067 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1068 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1069 scaled64 >>= 1;
1070 else
1071 tps32 <<= 1;
1072 shift++;
1073 }
1074
1075 *pshift = shift;
1076 *pmultiplier = div_frac(scaled64, tps32);
1077
1078 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1079 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1080 }
1081
1082 static inline u64 get_kernel_ns(void)
1083 {
1084 struct timespec ts;
1085
1086 WARN_ON(preemptible());
1087 ktime_get_ts(&ts);
1088 monotonic_to_bootbased(&ts);
1089 return timespec_to_ns(&ts);
1090 }
1091
1092 #ifdef CONFIG_X86_64
1093 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1094 #endif
1095
1096 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1097 unsigned long max_tsc_khz;
1098
1099 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1100 {
1101 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1102 vcpu->arch.virtual_tsc_shift);
1103 }
1104
1105 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1106 {
1107 u64 v = (u64)khz * (1000000 + ppm);
1108 do_div(v, 1000000);
1109 return v;
1110 }
1111
1112 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1113 {
1114 u32 thresh_lo, thresh_hi;
1115 int use_scaling = 0;
1116
1117 /* tsc_khz can be zero if TSC calibration fails */
1118 if (this_tsc_khz == 0)
1119 return;
1120
1121 /* Compute a scale to convert nanoseconds in TSC cycles */
1122 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1123 &vcpu->arch.virtual_tsc_shift,
1124 &vcpu->arch.virtual_tsc_mult);
1125 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1126
1127 /*
1128 * Compute the variation in TSC rate which is acceptable
1129 * within the range of tolerance and decide if the
1130 * rate being applied is within that bounds of the hardware
1131 * rate. If so, no scaling or compensation need be done.
1132 */
1133 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1134 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1135 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1136 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1137 use_scaling = 1;
1138 }
1139 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1140 }
1141
1142 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1143 {
1144 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1145 vcpu->arch.virtual_tsc_mult,
1146 vcpu->arch.virtual_tsc_shift);
1147 tsc += vcpu->arch.this_tsc_write;
1148 return tsc;
1149 }
1150
1151 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1152 {
1153 #ifdef CONFIG_X86_64
1154 bool vcpus_matched;
1155 bool do_request = false;
1156 struct kvm_arch *ka = &vcpu->kvm->arch;
1157 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1158
1159 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1160 atomic_read(&vcpu->kvm->online_vcpus));
1161
1162 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1163 if (!ka->use_master_clock)
1164 do_request = 1;
1165
1166 if (!vcpus_matched && ka->use_master_clock)
1167 do_request = 1;
1168
1169 if (do_request)
1170 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1171
1172 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1173 atomic_read(&vcpu->kvm->online_vcpus),
1174 ka->use_master_clock, gtod->clock.vclock_mode);
1175 #endif
1176 }
1177
1178 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1179 {
1180 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1181 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1182 }
1183
1184 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1185 {
1186 struct kvm *kvm = vcpu->kvm;
1187 u64 offset, ns, elapsed;
1188 unsigned long flags;
1189 s64 usdiff;
1190 bool matched;
1191 u64 data = msr->data;
1192
1193 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1194 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1195 ns = get_kernel_ns();
1196 elapsed = ns - kvm->arch.last_tsc_nsec;
1197
1198 if (vcpu->arch.virtual_tsc_khz) {
1199 int faulted = 0;
1200
1201 /* n.b - signed multiplication and division required */
1202 usdiff = data - kvm->arch.last_tsc_write;
1203 #ifdef CONFIG_X86_64
1204 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1205 #else
1206 /* do_div() only does unsigned */
1207 asm("1: idivl %[divisor]\n"
1208 "2: xor %%edx, %%edx\n"
1209 " movl $0, %[faulted]\n"
1210 "3:\n"
1211 ".section .fixup,\"ax\"\n"
1212 "4: movl $1, %[faulted]\n"
1213 " jmp 3b\n"
1214 ".previous\n"
1215
1216 _ASM_EXTABLE(1b, 4b)
1217
1218 : "=A"(usdiff), [faulted] "=r" (faulted)
1219 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1220
1221 #endif
1222 do_div(elapsed, 1000);
1223 usdiff -= elapsed;
1224 if (usdiff < 0)
1225 usdiff = -usdiff;
1226
1227 /* idivl overflow => difference is larger than USEC_PER_SEC */
1228 if (faulted)
1229 usdiff = USEC_PER_SEC;
1230 } else
1231 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1232
1233 /*
1234 * Special case: TSC write with a small delta (1 second) of virtual
1235 * cycle time against real time is interpreted as an attempt to
1236 * synchronize the CPU.
1237 *
1238 * For a reliable TSC, we can match TSC offsets, and for an unstable
1239 * TSC, we add elapsed time in this computation. We could let the
1240 * compensation code attempt to catch up if we fall behind, but
1241 * it's better to try to match offsets from the beginning.
1242 */
1243 if (usdiff < USEC_PER_SEC &&
1244 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1245 if (!check_tsc_unstable()) {
1246 offset = kvm->arch.cur_tsc_offset;
1247 pr_debug("kvm: matched tsc offset for %llu\n", data);
1248 } else {
1249 u64 delta = nsec_to_cycles(vcpu, elapsed);
1250 data += delta;
1251 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1252 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1253 }
1254 matched = true;
1255 } else {
1256 /*
1257 * We split periods of matched TSC writes into generations.
1258 * For each generation, we track the original measured
1259 * nanosecond time, offset, and write, so if TSCs are in
1260 * sync, we can match exact offset, and if not, we can match
1261 * exact software computation in compute_guest_tsc()
1262 *
1263 * These values are tracked in kvm->arch.cur_xxx variables.
1264 */
1265 kvm->arch.cur_tsc_generation++;
1266 kvm->arch.cur_tsc_nsec = ns;
1267 kvm->arch.cur_tsc_write = data;
1268 kvm->arch.cur_tsc_offset = offset;
1269 matched = false;
1270 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1271 kvm->arch.cur_tsc_generation, data);
1272 }
1273
1274 /*
1275 * We also track th most recent recorded KHZ, write and time to
1276 * allow the matching interval to be extended at each write.
1277 */
1278 kvm->arch.last_tsc_nsec = ns;
1279 kvm->arch.last_tsc_write = data;
1280 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1281
1282 vcpu->arch.last_guest_tsc = data;
1283
1284 /* Keep track of which generation this VCPU has synchronized to */
1285 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1286 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1287 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1288
1289 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1290 update_ia32_tsc_adjust_msr(vcpu, offset);
1291 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1292 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1293
1294 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1295 if (matched)
1296 kvm->arch.nr_vcpus_matched_tsc++;
1297 else
1298 kvm->arch.nr_vcpus_matched_tsc = 0;
1299
1300 kvm_track_tsc_matching(vcpu);
1301 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1302 }
1303
1304 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1305
1306 #ifdef CONFIG_X86_64
1307
1308 static cycle_t read_tsc(void)
1309 {
1310 cycle_t ret;
1311 u64 last;
1312
1313 /*
1314 * Empirically, a fence (of type that depends on the CPU)
1315 * before rdtsc is enough to ensure that rdtsc is ordered
1316 * with respect to loads. The various CPU manuals are unclear
1317 * as to whether rdtsc can be reordered with later loads,
1318 * but no one has ever seen it happen.
1319 */
1320 rdtsc_barrier();
1321 ret = (cycle_t)vget_cycles();
1322
1323 last = pvclock_gtod_data.clock.cycle_last;
1324
1325 if (likely(ret >= last))
1326 return ret;
1327
1328 /*
1329 * GCC likes to generate cmov here, but this branch is extremely
1330 * predictable (it's just a funciton of time and the likely is
1331 * very likely) and there's a data dependence, so force GCC
1332 * to generate a branch instead. I don't barrier() because
1333 * we don't actually need a barrier, and if this function
1334 * ever gets inlined it will generate worse code.
1335 */
1336 asm volatile ("");
1337 return last;
1338 }
1339
1340 static inline u64 vgettsc(cycle_t *cycle_now)
1341 {
1342 long v;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 *cycle_now = read_tsc();
1346
1347 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1348 return v * gtod->clock.mult;
1349 }
1350
1351 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1352 {
1353 unsigned long seq;
1354 u64 ns;
1355 int mode;
1356 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1357
1358 ts->tv_nsec = 0;
1359 do {
1360 seq = read_seqcount_begin(&gtod->seq);
1361 mode = gtod->clock.vclock_mode;
1362 ts->tv_sec = gtod->monotonic_time_sec;
1363 ns = gtod->monotonic_time_snsec;
1364 ns += vgettsc(cycle_now);
1365 ns >>= gtod->clock.shift;
1366 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1367 timespec_add_ns(ts, ns);
1368
1369 return mode;
1370 }
1371
1372 /* returns true if host is using tsc clocksource */
1373 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1374 {
1375 struct timespec ts;
1376
1377 /* checked again under seqlock below */
1378 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1379 return false;
1380
1381 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1382 return false;
1383
1384 monotonic_to_bootbased(&ts);
1385 *kernel_ns = timespec_to_ns(&ts);
1386
1387 return true;
1388 }
1389 #endif
1390
1391 /*
1392 *
1393 * Assuming a stable TSC across physical CPUS, and a stable TSC
1394 * across virtual CPUs, the following condition is possible.
1395 * Each numbered line represents an event visible to both
1396 * CPUs at the next numbered event.
1397 *
1398 * "timespecX" represents host monotonic time. "tscX" represents
1399 * RDTSC value.
1400 *
1401 * VCPU0 on CPU0 | VCPU1 on CPU1
1402 *
1403 * 1. read timespec0,tsc0
1404 * 2. | timespec1 = timespec0 + N
1405 * | tsc1 = tsc0 + M
1406 * 3. transition to guest | transition to guest
1407 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1408 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1409 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1410 *
1411 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1412 *
1413 * - ret0 < ret1
1414 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1415 * ...
1416 * - 0 < N - M => M < N
1417 *
1418 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1419 * always the case (the difference between two distinct xtime instances
1420 * might be smaller then the difference between corresponding TSC reads,
1421 * when updating guest vcpus pvclock areas).
1422 *
1423 * To avoid that problem, do not allow visibility of distinct
1424 * system_timestamp/tsc_timestamp values simultaneously: use a master
1425 * copy of host monotonic time values. Update that master copy
1426 * in lockstep.
1427 *
1428 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1429 *
1430 */
1431
1432 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1433 {
1434 #ifdef CONFIG_X86_64
1435 struct kvm_arch *ka = &kvm->arch;
1436 int vclock_mode;
1437 bool host_tsc_clocksource, vcpus_matched;
1438
1439 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1440 atomic_read(&kvm->online_vcpus));
1441
1442 /*
1443 * If the host uses TSC clock, then passthrough TSC as stable
1444 * to the guest.
1445 */
1446 host_tsc_clocksource = kvm_get_time_and_clockread(
1447 &ka->master_kernel_ns,
1448 &ka->master_cycle_now);
1449
1450 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1451
1452 if (ka->use_master_clock)
1453 atomic_set(&kvm_guest_has_master_clock, 1);
1454
1455 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1456 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1457 vcpus_matched);
1458 #endif
1459 }
1460
1461 static void kvm_gen_update_masterclock(struct kvm *kvm)
1462 {
1463 #ifdef CONFIG_X86_64
1464 int i;
1465 struct kvm_vcpu *vcpu;
1466 struct kvm_arch *ka = &kvm->arch;
1467
1468 spin_lock(&ka->pvclock_gtod_sync_lock);
1469 kvm_make_mclock_inprogress_request(kvm);
1470 /* no guest entries from this point */
1471 pvclock_update_vm_gtod_copy(kvm);
1472
1473 kvm_for_each_vcpu(i, vcpu, kvm)
1474 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1475
1476 /* guest entries allowed */
1477 kvm_for_each_vcpu(i, vcpu, kvm)
1478 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1479
1480 spin_unlock(&ka->pvclock_gtod_sync_lock);
1481 #endif
1482 }
1483
1484 static int kvm_guest_time_update(struct kvm_vcpu *v)
1485 {
1486 unsigned long flags, this_tsc_khz;
1487 struct kvm_vcpu_arch *vcpu = &v->arch;
1488 struct kvm_arch *ka = &v->kvm->arch;
1489 s64 kernel_ns;
1490 u64 tsc_timestamp, host_tsc;
1491 struct pvclock_vcpu_time_info guest_hv_clock;
1492 u8 pvclock_flags;
1493 bool use_master_clock;
1494
1495 kernel_ns = 0;
1496 host_tsc = 0;
1497
1498 /*
1499 * If the host uses TSC clock, then passthrough TSC as stable
1500 * to the guest.
1501 */
1502 spin_lock(&ka->pvclock_gtod_sync_lock);
1503 use_master_clock = ka->use_master_clock;
1504 if (use_master_clock) {
1505 host_tsc = ka->master_cycle_now;
1506 kernel_ns = ka->master_kernel_ns;
1507 }
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
1509
1510 /* Keep irq disabled to prevent changes to the clock */
1511 local_irq_save(flags);
1512 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1513 if (unlikely(this_tsc_khz == 0)) {
1514 local_irq_restore(flags);
1515 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1516 return 1;
1517 }
1518 if (!use_master_clock) {
1519 host_tsc = native_read_tsc();
1520 kernel_ns = get_kernel_ns();
1521 }
1522
1523 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1524
1525 /*
1526 * We may have to catch up the TSC to match elapsed wall clock
1527 * time for two reasons, even if kvmclock is used.
1528 * 1) CPU could have been running below the maximum TSC rate
1529 * 2) Broken TSC compensation resets the base at each VCPU
1530 * entry to avoid unknown leaps of TSC even when running
1531 * again on the same CPU. This may cause apparent elapsed
1532 * time to disappear, and the guest to stand still or run
1533 * very slowly.
1534 */
1535 if (vcpu->tsc_catchup) {
1536 u64 tsc = compute_guest_tsc(v, kernel_ns);
1537 if (tsc > tsc_timestamp) {
1538 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1539 tsc_timestamp = tsc;
1540 }
1541 }
1542
1543 local_irq_restore(flags);
1544
1545 if (!vcpu->pv_time_enabled)
1546 return 0;
1547
1548 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1549 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1550 &vcpu->hv_clock.tsc_shift,
1551 &vcpu->hv_clock.tsc_to_system_mul);
1552 vcpu->hw_tsc_khz = this_tsc_khz;
1553 }
1554
1555 /* With all the info we got, fill in the values */
1556 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1557 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1558 vcpu->last_kernel_ns = kernel_ns;
1559 vcpu->last_guest_tsc = tsc_timestamp;
1560
1561 /*
1562 * The interface expects us to write an even number signaling that the
1563 * update is finished. Since the guest won't see the intermediate
1564 * state, we just increase by 2 at the end.
1565 */
1566 vcpu->hv_clock.version += 2;
1567
1568 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1569 &guest_hv_clock, sizeof(guest_hv_clock))))
1570 return 0;
1571
1572 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1573 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1574
1575 if (vcpu->pvclock_set_guest_stopped_request) {
1576 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1577 vcpu->pvclock_set_guest_stopped_request = false;
1578 }
1579
1580 /* If the host uses TSC clocksource, then it is stable */
1581 if (use_master_clock)
1582 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1583
1584 vcpu->hv_clock.flags = pvclock_flags;
1585
1586 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1587 &vcpu->hv_clock,
1588 sizeof(vcpu->hv_clock));
1589 return 0;
1590 }
1591
1592 /*
1593 * kvmclock updates which are isolated to a given vcpu, such as
1594 * vcpu->cpu migration, should not allow system_timestamp from
1595 * the rest of the vcpus to remain static. Otherwise ntp frequency
1596 * correction applies to one vcpu's system_timestamp but not
1597 * the others.
1598 *
1599 * So in those cases, request a kvmclock update for all vcpus.
1600 * The worst case for a remote vcpu to update its kvmclock
1601 * is then bounded by maximum nohz sleep latency.
1602 */
1603
1604 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1605 {
1606 int i;
1607 struct kvm *kvm = v->kvm;
1608 struct kvm_vcpu *vcpu;
1609
1610 kvm_for_each_vcpu(i, vcpu, kvm) {
1611 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1612 kvm_vcpu_kick(vcpu);
1613 }
1614 }
1615
1616 static bool msr_mtrr_valid(unsigned msr)
1617 {
1618 switch (msr) {
1619 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1620 case MSR_MTRRfix64K_00000:
1621 case MSR_MTRRfix16K_80000:
1622 case MSR_MTRRfix16K_A0000:
1623 case MSR_MTRRfix4K_C0000:
1624 case MSR_MTRRfix4K_C8000:
1625 case MSR_MTRRfix4K_D0000:
1626 case MSR_MTRRfix4K_D8000:
1627 case MSR_MTRRfix4K_E0000:
1628 case MSR_MTRRfix4K_E8000:
1629 case MSR_MTRRfix4K_F0000:
1630 case MSR_MTRRfix4K_F8000:
1631 case MSR_MTRRdefType:
1632 case MSR_IA32_CR_PAT:
1633 return true;
1634 case 0x2f8:
1635 return true;
1636 }
1637 return false;
1638 }
1639
1640 static bool valid_pat_type(unsigned t)
1641 {
1642 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1643 }
1644
1645 static bool valid_mtrr_type(unsigned t)
1646 {
1647 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1648 }
1649
1650 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1651 {
1652 int i;
1653
1654 if (!msr_mtrr_valid(msr))
1655 return false;
1656
1657 if (msr == MSR_IA32_CR_PAT) {
1658 for (i = 0; i < 8; i++)
1659 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1660 return false;
1661 return true;
1662 } else if (msr == MSR_MTRRdefType) {
1663 if (data & ~0xcff)
1664 return false;
1665 return valid_mtrr_type(data & 0xff);
1666 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1667 for (i = 0; i < 8 ; i++)
1668 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1669 return false;
1670 return true;
1671 }
1672
1673 /* variable MTRRs */
1674 return valid_mtrr_type(data & 0xff);
1675 }
1676
1677 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1678 {
1679 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1680
1681 if (!mtrr_valid(vcpu, msr, data))
1682 return 1;
1683
1684 if (msr == MSR_MTRRdefType) {
1685 vcpu->arch.mtrr_state.def_type = data;
1686 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1687 } else if (msr == MSR_MTRRfix64K_00000)
1688 p[0] = data;
1689 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1690 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1691 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1692 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1693 else if (msr == MSR_IA32_CR_PAT)
1694 vcpu->arch.pat = data;
1695 else { /* Variable MTRRs */
1696 int idx, is_mtrr_mask;
1697 u64 *pt;
1698
1699 idx = (msr - 0x200) / 2;
1700 is_mtrr_mask = msr - 0x200 - 2 * idx;
1701 if (!is_mtrr_mask)
1702 pt =
1703 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1704 else
1705 pt =
1706 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1707 *pt = data;
1708 }
1709
1710 kvm_mmu_reset_context(vcpu);
1711 return 0;
1712 }
1713
1714 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1715 {
1716 u64 mcg_cap = vcpu->arch.mcg_cap;
1717 unsigned bank_num = mcg_cap & 0xff;
1718
1719 switch (msr) {
1720 case MSR_IA32_MCG_STATUS:
1721 vcpu->arch.mcg_status = data;
1722 break;
1723 case MSR_IA32_MCG_CTL:
1724 if (!(mcg_cap & MCG_CTL_P))
1725 return 1;
1726 if (data != 0 && data != ~(u64)0)
1727 return -1;
1728 vcpu->arch.mcg_ctl = data;
1729 break;
1730 default:
1731 if (msr >= MSR_IA32_MC0_CTL &&
1732 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1733 u32 offset = msr - MSR_IA32_MC0_CTL;
1734 /* only 0 or all 1s can be written to IA32_MCi_CTL
1735 * some Linux kernels though clear bit 10 in bank 4 to
1736 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1737 * this to avoid an uncatched #GP in the guest
1738 */
1739 if ((offset & 0x3) == 0 &&
1740 data != 0 && (data | (1 << 10)) != ~(u64)0)
1741 return -1;
1742 vcpu->arch.mce_banks[offset] = data;
1743 break;
1744 }
1745 return 1;
1746 }
1747 return 0;
1748 }
1749
1750 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1751 {
1752 struct kvm *kvm = vcpu->kvm;
1753 int lm = is_long_mode(vcpu);
1754 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1755 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1756 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1757 : kvm->arch.xen_hvm_config.blob_size_32;
1758 u32 page_num = data & ~PAGE_MASK;
1759 u64 page_addr = data & PAGE_MASK;
1760 u8 *page;
1761 int r;
1762
1763 r = -E2BIG;
1764 if (page_num >= blob_size)
1765 goto out;
1766 r = -ENOMEM;
1767 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1768 if (IS_ERR(page)) {
1769 r = PTR_ERR(page);
1770 goto out;
1771 }
1772 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1773 goto out_free;
1774 r = 0;
1775 out_free:
1776 kfree(page);
1777 out:
1778 return r;
1779 }
1780
1781 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1782 {
1783 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1784 }
1785
1786 static bool kvm_hv_msr_partition_wide(u32 msr)
1787 {
1788 bool r = false;
1789 switch (msr) {
1790 case HV_X64_MSR_GUEST_OS_ID:
1791 case HV_X64_MSR_HYPERCALL:
1792 case HV_X64_MSR_REFERENCE_TSC:
1793 case HV_X64_MSR_TIME_REF_COUNT:
1794 r = true;
1795 break;
1796 }
1797
1798 return r;
1799 }
1800
1801 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1802 {
1803 struct kvm *kvm = vcpu->kvm;
1804
1805 switch (msr) {
1806 case HV_X64_MSR_GUEST_OS_ID:
1807 kvm->arch.hv_guest_os_id = data;
1808 /* setting guest os id to zero disables hypercall page */
1809 if (!kvm->arch.hv_guest_os_id)
1810 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1811 break;
1812 case HV_X64_MSR_HYPERCALL: {
1813 u64 gfn;
1814 unsigned long addr;
1815 u8 instructions[4];
1816
1817 /* if guest os id is not set hypercall should remain disabled */
1818 if (!kvm->arch.hv_guest_os_id)
1819 break;
1820 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1821 kvm->arch.hv_hypercall = data;
1822 break;
1823 }
1824 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1825 addr = gfn_to_hva(kvm, gfn);
1826 if (kvm_is_error_hva(addr))
1827 return 1;
1828 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1829 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1830 if (__copy_to_user((void __user *)addr, instructions, 4))
1831 return 1;
1832 kvm->arch.hv_hypercall = data;
1833 break;
1834 }
1835 case HV_X64_MSR_REFERENCE_TSC: {
1836 u64 gfn;
1837 HV_REFERENCE_TSC_PAGE tsc_ref;
1838 memset(&tsc_ref, 0, sizeof(tsc_ref));
1839 kvm->arch.hv_tsc_page = data;
1840 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1841 break;
1842 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1843 if (kvm_write_guest(kvm, data,
1844 &tsc_ref, sizeof(tsc_ref)))
1845 return 1;
1846 mark_page_dirty(kvm, gfn);
1847 break;
1848 }
1849 default:
1850 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1851 "data 0x%llx\n", msr, data);
1852 return 1;
1853 }
1854 return 0;
1855 }
1856
1857 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858 {
1859 switch (msr) {
1860 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1861 unsigned long addr;
1862
1863 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1864 vcpu->arch.hv_vapic = data;
1865 break;
1866 }
1867 addr = gfn_to_hva(vcpu->kvm, data >>
1868 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1869 if (kvm_is_error_hva(addr))
1870 return 1;
1871 if (__clear_user((void __user *)addr, PAGE_SIZE))
1872 return 1;
1873 vcpu->arch.hv_vapic = data;
1874 break;
1875 }
1876 case HV_X64_MSR_EOI:
1877 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1878 case HV_X64_MSR_ICR:
1879 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1880 case HV_X64_MSR_TPR:
1881 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1882 default:
1883 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1884 "data 0x%llx\n", msr, data);
1885 return 1;
1886 }
1887
1888 return 0;
1889 }
1890
1891 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1892 {
1893 gpa_t gpa = data & ~0x3f;
1894
1895 /* Bits 2:5 are reserved, Should be zero */
1896 if (data & 0x3c)
1897 return 1;
1898
1899 vcpu->arch.apf.msr_val = data;
1900
1901 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1902 kvm_clear_async_pf_completion_queue(vcpu);
1903 kvm_async_pf_hash_reset(vcpu);
1904 return 0;
1905 }
1906
1907 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1908 sizeof(u32)))
1909 return 1;
1910
1911 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1912 kvm_async_pf_wakeup_all(vcpu);
1913 return 0;
1914 }
1915
1916 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1917 {
1918 vcpu->arch.pv_time_enabled = false;
1919 }
1920
1921 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1922 {
1923 u64 delta;
1924
1925 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1926 return;
1927
1928 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1929 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1930 vcpu->arch.st.accum_steal = delta;
1931 }
1932
1933 static void record_steal_time(struct kvm_vcpu *vcpu)
1934 {
1935 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1936 return;
1937
1938 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1939 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1940 return;
1941
1942 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1943 vcpu->arch.st.steal.version += 2;
1944 vcpu->arch.st.accum_steal = 0;
1945
1946 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1947 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1948 }
1949
1950 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1951 {
1952 bool pr = false;
1953 u32 msr = msr_info->index;
1954 u64 data = msr_info->data;
1955
1956 switch (msr) {
1957 case MSR_AMD64_NB_CFG:
1958 case MSR_IA32_UCODE_REV:
1959 case MSR_IA32_UCODE_WRITE:
1960 case MSR_VM_HSAVE_PA:
1961 case MSR_AMD64_PATCH_LOADER:
1962 case MSR_AMD64_BU_CFG2:
1963 break;
1964
1965 case MSR_EFER:
1966 return set_efer(vcpu, data);
1967 case MSR_K7_HWCR:
1968 data &= ~(u64)0x40; /* ignore flush filter disable */
1969 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1970 data &= ~(u64)0x8; /* ignore TLB cache disable */
1971 if (data != 0) {
1972 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1973 data);
1974 return 1;
1975 }
1976 break;
1977 case MSR_FAM10H_MMIO_CONF_BASE:
1978 if (data != 0) {
1979 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1980 "0x%llx\n", data);
1981 return 1;
1982 }
1983 break;
1984 case MSR_IA32_DEBUGCTLMSR:
1985 if (!data) {
1986 /* We support the non-activated case already */
1987 break;
1988 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1989 /* Values other than LBR and BTF are vendor-specific,
1990 thus reserved and should throw a #GP */
1991 return 1;
1992 }
1993 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1994 __func__, data);
1995 break;
1996 case 0x200 ... 0x2ff:
1997 return set_msr_mtrr(vcpu, msr, data);
1998 case MSR_IA32_APICBASE:
1999 kvm_set_apic_base(vcpu, data);
2000 break;
2001 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2002 return kvm_x2apic_msr_write(vcpu, msr, data);
2003 case MSR_IA32_TSCDEADLINE:
2004 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2005 break;
2006 case MSR_IA32_TSC_ADJUST:
2007 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2008 if (!msr_info->host_initiated) {
2009 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2010 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2011 }
2012 vcpu->arch.ia32_tsc_adjust_msr = data;
2013 }
2014 break;
2015 case MSR_IA32_MISC_ENABLE:
2016 vcpu->arch.ia32_misc_enable_msr = data;
2017 break;
2018 case MSR_KVM_WALL_CLOCK_NEW:
2019 case MSR_KVM_WALL_CLOCK:
2020 vcpu->kvm->arch.wall_clock = data;
2021 kvm_write_wall_clock(vcpu->kvm, data);
2022 break;
2023 case MSR_KVM_SYSTEM_TIME_NEW:
2024 case MSR_KVM_SYSTEM_TIME: {
2025 u64 gpa_offset;
2026 kvmclock_reset(vcpu);
2027
2028 vcpu->arch.time = data;
2029 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2030
2031 /* we verify if the enable bit is set... */
2032 if (!(data & 1))
2033 break;
2034
2035 gpa_offset = data & ~(PAGE_MASK | 1);
2036
2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2038 &vcpu->arch.pv_time, data & ~1ULL,
2039 sizeof(struct pvclock_vcpu_time_info)))
2040 vcpu->arch.pv_time_enabled = false;
2041 else
2042 vcpu->arch.pv_time_enabled = true;
2043
2044 break;
2045 }
2046 case MSR_KVM_ASYNC_PF_EN:
2047 if (kvm_pv_enable_async_pf(vcpu, data))
2048 return 1;
2049 break;
2050 case MSR_KVM_STEAL_TIME:
2051
2052 if (unlikely(!sched_info_on()))
2053 return 1;
2054
2055 if (data & KVM_STEAL_RESERVED_MASK)
2056 return 1;
2057
2058 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2059 data & KVM_STEAL_VALID_BITS,
2060 sizeof(struct kvm_steal_time)))
2061 return 1;
2062
2063 vcpu->arch.st.msr_val = data;
2064
2065 if (!(data & KVM_MSR_ENABLED))
2066 break;
2067
2068 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2069
2070 preempt_disable();
2071 accumulate_steal_time(vcpu);
2072 preempt_enable();
2073
2074 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2075
2076 break;
2077 case MSR_KVM_PV_EOI_EN:
2078 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2079 return 1;
2080 break;
2081
2082 case MSR_IA32_MCG_CTL:
2083 case MSR_IA32_MCG_STATUS:
2084 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2085 return set_msr_mce(vcpu, msr, data);
2086
2087 /* Performance counters are not protected by a CPUID bit,
2088 * so we should check all of them in the generic path for the sake of
2089 * cross vendor migration.
2090 * Writing a zero into the event select MSRs disables them,
2091 * which we perfectly emulate ;-). Any other value should be at least
2092 * reported, some guests depend on them.
2093 */
2094 case MSR_K7_EVNTSEL0:
2095 case MSR_K7_EVNTSEL1:
2096 case MSR_K7_EVNTSEL2:
2097 case MSR_K7_EVNTSEL3:
2098 if (data != 0)
2099 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2100 "0x%x data 0x%llx\n", msr, data);
2101 break;
2102 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2103 * so we ignore writes to make it happy.
2104 */
2105 case MSR_K7_PERFCTR0:
2106 case MSR_K7_PERFCTR1:
2107 case MSR_K7_PERFCTR2:
2108 case MSR_K7_PERFCTR3:
2109 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2110 "0x%x data 0x%llx\n", msr, data);
2111 break;
2112 case MSR_P6_PERFCTR0:
2113 case MSR_P6_PERFCTR1:
2114 pr = true;
2115 case MSR_P6_EVNTSEL0:
2116 case MSR_P6_EVNTSEL1:
2117 if (kvm_pmu_msr(vcpu, msr))
2118 return kvm_pmu_set_msr(vcpu, msr_info);
2119
2120 if (pr || data != 0)
2121 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2122 "0x%x data 0x%llx\n", msr, data);
2123 break;
2124 case MSR_K7_CLK_CTL:
2125 /*
2126 * Ignore all writes to this no longer documented MSR.
2127 * Writes are only relevant for old K7 processors,
2128 * all pre-dating SVM, but a recommended workaround from
2129 * AMD for these chips. It is possible to specify the
2130 * affected processor models on the command line, hence
2131 * the need to ignore the workaround.
2132 */
2133 break;
2134 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2135 if (kvm_hv_msr_partition_wide(msr)) {
2136 int r;
2137 mutex_lock(&vcpu->kvm->lock);
2138 r = set_msr_hyperv_pw(vcpu, msr, data);
2139 mutex_unlock(&vcpu->kvm->lock);
2140 return r;
2141 } else
2142 return set_msr_hyperv(vcpu, msr, data);
2143 break;
2144 case MSR_IA32_BBL_CR_CTL3:
2145 /* Drop writes to this legacy MSR -- see rdmsr
2146 * counterpart for further detail.
2147 */
2148 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2149 break;
2150 case MSR_AMD64_OSVW_ID_LENGTH:
2151 if (!guest_cpuid_has_osvw(vcpu))
2152 return 1;
2153 vcpu->arch.osvw.length = data;
2154 break;
2155 case MSR_AMD64_OSVW_STATUS:
2156 if (!guest_cpuid_has_osvw(vcpu))
2157 return 1;
2158 vcpu->arch.osvw.status = data;
2159 break;
2160 default:
2161 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2162 return xen_hvm_config(vcpu, data);
2163 if (kvm_pmu_msr(vcpu, msr))
2164 return kvm_pmu_set_msr(vcpu, msr_info);
2165 if (!ignore_msrs) {
2166 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2167 msr, data);
2168 return 1;
2169 } else {
2170 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2171 msr, data);
2172 break;
2173 }
2174 }
2175 return 0;
2176 }
2177 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2178
2179
2180 /*
2181 * Reads an msr value (of 'msr_index') into 'pdata'.
2182 * Returns 0 on success, non-0 otherwise.
2183 * Assumes vcpu_load() was already called.
2184 */
2185 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2186 {
2187 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2188 }
2189
2190 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2191 {
2192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2193
2194 if (!msr_mtrr_valid(msr))
2195 return 1;
2196
2197 if (msr == MSR_MTRRdefType)
2198 *pdata = vcpu->arch.mtrr_state.def_type +
2199 (vcpu->arch.mtrr_state.enabled << 10);
2200 else if (msr == MSR_MTRRfix64K_00000)
2201 *pdata = p[0];
2202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2203 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2205 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2206 else if (msr == MSR_IA32_CR_PAT)
2207 *pdata = vcpu->arch.pat;
2208 else { /* Variable MTRRs */
2209 int idx, is_mtrr_mask;
2210 u64 *pt;
2211
2212 idx = (msr - 0x200) / 2;
2213 is_mtrr_mask = msr - 0x200 - 2 * idx;
2214 if (!is_mtrr_mask)
2215 pt =
2216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2217 else
2218 pt =
2219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2220 *pdata = *pt;
2221 }
2222
2223 return 0;
2224 }
2225
2226 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2227 {
2228 u64 data;
2229 u64 mcg_cap = vcpu->arch.mcg_cap;
2230 unsigned bank_num = mcg_cap & 0xff;
2231
2232 switch (msr) {
2233 case MSR_IA32_P5_MC_ADDR:
2234 case MSR_IA32_P5_MC_TYPE:
2235 data = 0;
2236 break;
2237 case MSR_IA32_MCG_CAP:
2238 data = vcpu->arch.mcg_cap;
2239 break;
2240 case MSR_IA32_MCG_CTL:
2241 if (!(mcg_cap & MCG_CTL_P))
2242 return 1;
2243 data = vcpu->arch.mcg_ctl;
2244 break;
2245 case MSR_IA32_MCG_STATUS:
2246 data = vcpu->arch.mcg_status;
2247 break;
2248 default:
2249 if (msr >= MSR_IA32_MC0_CTL &&
2250 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2251 u32 offset = msr - MSR_IA32_MC0_CTL;
2252 data = vcpu->arch.mce_banks[offset];
2253 break;
2254 }
2255 return 1;
2256 }
2257 *pdata = data;
2258 return 0;
2259 }
2260
2261 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2262 {
2263 u64 data = 0;
2264 struct kvm *kvm = vcpu->kvm;
2265
2266 switch (msr) {
2267 case HV_X64_MSR_GUEST_OS_ID:
2268 data = kvm->arch.hv_guest_os_id;
2269 break;
2270 case HV_X64_MSR_HYPERCALL:
2271 data = kvm->arch.hv_hypercall;
2272 break;
2273 case HV_X64_MSR_TIME_REF_COUNT: {
2274 data =
2275 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2276 break;
2277 }
2278 case HV_X64_MSR_REFERENCE_TSC:
2279 data = kvm->arch.hv_tsc_page;
2280 break;
2281 default:
2282 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2283 return 1;
2284 }
2285
2286 *pdata = data;
2287 return 0;
2288 }
2289
2290 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2291 {
2292 u64 data = 0;
2293
2294 switch (msr) {
2295 case HV_X64_MSR_VP_INDEX: {
2296 int r;
2297 struct kvm_vcpu *v;
2298 kvm_for_each_vcpu(r, v, vcpu->kvm)
2299 if (v == vcpu)
2300 data = r;
2301 break;
2302 }
2303 case HV_X64_MSR_EOI:
2304 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2305 case HV_X64_MSR_ICR:
2306 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2307 case HV_X64_MSR_TPR:
2308 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2309 case HV_X64_MSR_APIC_ASSIST_PAGE:
2310 data = vcpu->arch.hv_vapic;
2311 break;
2312 default:
2313 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2314 return 1;
2315 }
2316 *pdata = data;
2317 return 0;
2318 }
2319
2320 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321 {
2322 u64 data;
2323
2324 switch (msr) {
2325 case MSR_IA32_PLATFORM_ID:
2326 case MSR_IA32_EBL_CR_POWERON:
2327 case MSR_IA32_DEBUGCTLMSR:
2328 case MSR_IA32_LASTBRANCHFROMIP:
2329 case MSR_IA32_LASTBRANCHTOIP:
2330 case MSR_IA32_LASTINTFROMIP:
2331 case MSR_IA32_LASTINTTOIP:
2332 case MSR_K8_SYSCFG:
2333 case MSR_K7_HWCR:
2334 case MSR_VM_HSAVE_PA:
2335 case MSR_K7_EVNTSEL0:
2336 case MSR_K7_PERFCTR0:
2337 case MSR_K8_INT_PENDING_MSG:
2338 case MSR_AMD64_NB_CFG:
2339 case MSR_FAM10H_MMIO_CONF_BASE:
2340 case MSR_AMD64_BU_CFG2:
2341 data = 0;
2342 break;
2343 case MSR_P6_PERFCTR0:
2344 case MSR_P6_PERFCTR1:
2345 case MSR_P6_EVNTSEL0:
2346 case MSR_P6_EVNTSEL1:
2347 if (kvm_pmu_msr(vcpu, msr))
2348 return kvm_pmu_get_msr(vcpu, msr, pdata);
2349 data = 0;
2350 break;
2351 case MSR_IA32_UCODE_REV:
2352 data = 0x100000000ULL;
2353 break;
2354 case MSR_MTRRcap:
2355 data = 0x500 | KVM_NR_VAR_MTRR;
2356 break;
2357 case 0x200 ... 0x2ff:
2358 return get_msr_mtrr(vcpu, msr, pdata);
2359 case 0xcd: /* fsb frequency */
2360 data = 3;
2361 break;
2362 /*
2363 * MSR_EBC_FREQUENCY_ID
2364 * Conservative value valid for even the basic CPU models.
2365 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2366 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2367 * and 266MHz for model 3, or 4. Set Core Clock
2368 * Frequency to System Bus Frequency Ratio to 1 (bits
2369 * 31:24) even though these are only valid for CPU
2370 * models > 2, however guests may end up dividing or
2371 * multiplying by zero otherwise.
2372 */
2373 case MSR_EBC_FREQUENCY_ID:
2374 data = 1 << 24;
2375 break;
2376 case MSR_IA32_APICBASE:
2377 data = kvm_get_apic_base(vcpu);
2378 break;
2379 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2380 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2381 break;
2382 case MSR_IA32_TSCDEADLINE:
2383 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2384 break;
2385 case MSR_IA32_TSC_ADJUST:
2386 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2387 break;
2388 case MSR_IA32_MISC_ENABLE:
2389 data = vcpu->arch.ia32_misc_enable_msr;
2390 break;
2391 case MSR_IA32_PERF_STATUS:
2392 /* TSC increment by tick */
2393 data = 1000ULL;
2394 /* CPU multiplier */
2395 data |= (((uint64_t)4ULL) << 40);
2396 break;
2397 case MSR_EFER:
2398 data = vcpu->arch.efer;
2399 break;
2400 case MSR_KVM_WALL_CLOCK:
2401 case MSR_KVM_WALL_CLOCK_NEW:
2402 data = vcpu->kvm->arch.wall_clock;
2403 break;
2404 case MSR_KVM_SYSTEM_TIME:
2405 case MSR_KVM_SYSTEM_TIME_NEW:
2406 data = vcpu->arch.time;
2407 break;
2408 case MSR_KVM_ASYNC_PF_EN:
2409 data = vcpu->arch.apf.msr_val;
2410 break;
2411 case MSR_KVM_STEAL_TIME:
2412 data = vcpu->arch.st.msr_val;
2413 break;
2414 case MSR_KVM_PV_EOI_EN:
2415 data = vcpu->arch.pv_eoi.msr_val;
2416 break;
2417 case MSR_IA32_P5_MC_ADDR:
2418 case MSR_IA32_P5_MC_TYPE:
2419 case MSR_IA32_MCG_CAP:
2420 case MSR_IA32_MCG_CTL:
2421 case MSR_IA32_MCG_STATUS:
2422 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2423 return get_msr_mce(vcpu, msr, pdata);
2424 case MSR_K7_CLK_CTL:
2425 /*
2426 * Provide expected ramp-up count for K7. All other
2427 * are set to zero, indicating minimum divisors for
2428 * every field.
2429 *
2430 * This prevents guest kernels on AMD host with CPU
2431 * type 6, model 8 and higher from exploding due to
2432 * the rdmsr failing.
2433 */
2434 data = 0x20000000;
2435 break;
2436 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2437 if (kvm_hv_msr_partition_wide(msr)) {
2438 int r;
2439 mutex_lock(&vcpu->kvm->lock);
2440 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2441 mutex_unlock(&vcpu->kvm->lock);
2442 return r;
2443 } else
2444 return get_msr_hyperv(vcpu, msr, pdata);
2445 break;
2446 case MSR_IA32_BBL_CR_CTL3:
2447 /* This legacy MSR exists but isn't fully documented in current
2448 * silicon. It is however accessed by winxp in very narrow
2449 * scenarios where it sets bit #19, itself documented as
2450 * a "reserved" bit. Best effort attempt to source coherent
2451 * read data here should the balance of the register be
2452 * interpreted by the guest:
2453 *
2454 * L2 cache control register 3: 64GB range, 256KB size,
2455 * enabled, latency 0x1, configured
2456 */
2457 data = 0xbe702111;
2458 break;
2459 case MSR_AMD64_OSVW_ID_LENGTH:
2460 if (!guest_cpuid_has_osvw(vcpu))
2461 return 1;
2462 data = vcpu->arch.osvw.length;
2463 break;
2464 case MSR_AMD64_OSVW_STATUS:
2465 if (!guest_cpuid_has_osvw(vcpu))
2466 return 1;
2467 data = vcpu->arch.osvw.status;
2468 break;
2469 default:
2470 if (kvm_pmu_msr(vcpu, msr))
2471 return kvm_pmu_get_msr(vcpu, msr, pdata);
2472 if (!ignore_msrs) {
2473 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2474 return 1;
2475 } else {
2476 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2477 data = 0;
2478 }
2479 break;
2480 }
2481 *pdata = data;
2482 return 0;
2483 }
2484 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2485
2486 /*
2487 * Read or write a bunch of msrs. All parameters are kernel addresses.
2488 *
2489 * @return number of msrs set successfully.
2490 */
2491 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2492 struct kvm_msr_entry *entries,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data))
2495 {
2496 int i, idx;
2497
2498 idx = srcu_read_lock(&vcpu->kvm->srcu);
2499 for (i = 0; i < msrs->nmsrs; ++i)
2500 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2501 break;
2502 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2503
2504 return i;
2505 }
2506
2507 /*
2508 * Read or write a bunch of msrs. Parameters are user addresses.
2509 *
2510 * @return number of msrs set successfully.
2511 */
2512 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2513 int (*do_msr)(struct kvm_vcpu *vcpu,
2514 unsigned index, u64 *data),
2515 int writeback)
2516 {
2517 struct kvm_msrs msrs;
2518 struct kvm_msr_entry *entries;
2519 int r, n;
2520 unsigned size;
2521
2522 r = -EFAULT;
2523 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2524 goto out;
2525
2526 r = -E2BIG;
2527 if (msrs.nmsrs >= MAX_IO_MSRS)
2528 goto out;
2529
2530 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2531 entries = memdup_user(user_msrs->entries, size);
2532 if (IS_ERR(entries)) {
2533 r = PTR_ERR(entries);
2534 goto out;
2535 }
2536
2537 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2538 if (r < 0)
2539 goto out_free;
2540
2541 r = -EFAULT;
2542 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2543 goto out_free;
2544
2545 r = n;
2546
2547 out_free:
2548 kfree(entries);
2549 out:
2550 return r;
2551 }
2552
2553 int kvm_dev_ioctl_check_extension(long ext)
2554 {
2555 int r;
2556
2557 switch (ext) {
2558 case KVM_CAP_IRQCHIP:
2559 case KVM_CAP_HLT:
2560 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2561 case KVM_CAP_SET_TSS_ADDR:
2562 case KVM_CAP_EXT_CPUID:
2563 case KVM_CAP_EXT_EMUL_CPUID:
2564 case KVM_CAP_CLOCKSOURCE:
2565 case KVM_CAP_PIT:
2566 case KVM_CAP_NOP_IO_DELAY:
2567 case KVM_CAP_MP_STATE:
2568 case KVM_CAP_SYNC_MMU:
2569 case KVM_CAP_USER_NMI:
2570 case KVM_CAP_REINJECT_CONTROL:
2571 case KVM_CAP_IRQ_INJECT_STATUS:
2572 case KVM_CAP_IRQFD:
2573 case KVM_CAP_IOEVENTFD:
2574 case KVM_CAP_PIT2:
2575 case KVM_CAP_PIT_STATE2:
2576 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2577 case KVM_CAP_XEN_HVM:
2578 case KVM_CAP_ADJUST_CLOCK:
2579 case KVM_CAP_VCPU_EVENTS:
2580 case KVM_CAP_HYPERV:
2581 case KVM_CAP_HYPERV_VAPIC:
2582 case KVM_CAP_HYPERV_SPIN:
2583 case KVM_CAP_PCI_SEGMENT:
2584 case KVM_CAP_DEBUGREGS:
2585 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2586 case KVM_CAP_XSAVE:
2587 case KVM_CAP_ASYNC_PF:
2588 case KVM_CAP_GET_TSC_KHZ:
2589 case KVM_CAP_KVMCLOCK_CTRL:
2590 case KVM_CAP_READONLY_MEM:
2591 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2592 case KVM_CAP_ASSIGN_DEV_IRQ:
2593 case KVM_CAP_PCI_2_3:
2594 case KVM_CAP_HYPERV_TIME:
2595 #endif
2596 r = 1;
2597 break;
2598 case KVM_CAP_COALESCED_MMIO:
2599 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2600 break;
2601 case KVM_CAP_VAPIC:
2602 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2603 break;
2604 case KVM_CAP_NR_VCPUS:
2605 r = KVM_SOFT_MAX_VCPUS;
2606 break;
2607 case KVM_CAP_MAX_VCPUS:
2608 r = KVM_MAX_VCPUS;
2609 break;
2610 case KVM_CAP_NR_MEMSLOTS:
2611 r = KVM_USER_MEM_SLOTS;
2612 break;
2613 case KVM_CAP_PV_MMU: /* obsolete */
2614 r = 0;
2615 break;
2616 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2617 case KVM_CAP_IOMMU:
2618 r = iommu_present(&pci_bus_type);
2619 break;
2620 #endif
2621 case KVM_CAP_MCE:
2622 r = KVM_MAX_MCE_BANKS;
2623 break;
2624 case KVM_CAP_XCRS:
2625 r = cpu_has_xsave;
2626 break;
2627 case KVM_CAP_TSC_CONTROL:
2628 r = kvm_has_tsc_control;
2629 break;
2630 case KVM_CAP_TSC_DEADLINE_TIMER:
2631 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2632 break;
2633 default:
2634 r = 0;
2635 break;
2636 }
2637 return r;
2638
2639 }
2640
2641 long kvm_arch_dev_ioctl(struct file *filp,
2642 unsigned int ioctl, unsigned long arg)
2643 {
2644 void __user *argp = (void __user *)arg;
2645 long r;
2646
2647 switch (ioctl) {
2648 case KVM_GET_MSR_INDEX_LIST: {
2649 struct kvm_msr_list __user *user_msr_list = argp;
2650 struct kvm_msr_list msr_list;
2651 unsigned n;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2655 goto out;
2656 n = msr_list.nmsrs;
2657 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2658 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2659 goto out;
2660 r = -E2BIG;
2661 if (n < msr_list.nmsrs)
2662 goto out;
2663 r = -EFAULT;
2664 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2665 num_msrs_to_save * sizeof(u32)))
2666 goto out;
2667 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2668 &emulated_msrs,
2669 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2670 goto out;
2671 r = 0;
2672 break;
2673 }
2674 case KVM_GET_SUPPORTED_CPUID:
2675 case KVM_GET_EMULATED_CPUID: {
2676 struct kvm_cpuid2 __user *cpuid_arg = argp;
2677 struct kvm_cpuid2 cpuid;
2678
2679 r = -EFAULT;
2680 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2681 goto out;
2682
2683 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2684 ioctl);
2685 if (r)
2686 goto out;
2687
2688 r = -EFAULT;
2689 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
2694 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2695 u64 mce_cap;
2696
2697 mce_cap = KVM_MCE_CAP_SUPPORTED;
2698 r = -EFAULT;
2699 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2700 goto out;
2701 r = 0;
2702 break;
2703 }
2704 default:
2705 r = -EINVAL;
2706 }
2707 out:
2708 return r;
2709 }
2710
2711 static void wbinvd_ipi(void *garbage)
2712 {
2713 wbinvd();
2714 }
2715
2716 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717 {
2718 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2719 }
2720
2721 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2722 {
2723 /* Address WBINVD may be executed by guest */
2724 if (need_emulate_wbinvd(vcpu)) {
2725 if (kvm_x86_ops->has_wbinvd_exit())
2726 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2727 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2728 smp_call_function_single(vcpu->cpu,
2729 wbinvd_ipi, NULL, 1);
2730 }
2731
2732 kvm_x86_ops->vcpu_load(vcpu, cpu);
2733
2734 /* Apply any externally detected TSC adjustments (due to suspend) */
2735 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2736 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2737 vcpu->arch.tsc_offset_adjustment = 0;
2738 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2739 }
2740
2741 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2742 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2743 native_read_tsc() - vcpu->arch.last_host_tsc;
2744 if (tsc_delta < 0)
2745 mark_tsc_unstable("KVM discovered backwards TSC");
2746 if (check_tsc_unstable()) {
2747 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2748 vcpu->arch.last_guest_tsc);
2749 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2750 vcpu->arch.tsc_catchup = 1;
2751 }
2752 /*
2753 * On a host with synchronized TSC, there is no need to update
2754 * kvmclock on vcpu->cpu migration
2755 */
2756 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2757 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2758 if (vcpu->cpu != cpu)
2759 kvm_migrate_timers(vcpu);
2760 vcpu->cpu = cpu;
2761 }
2762
2763 accumulate_steal_time(vcpu);
2764 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2765 }
2766
2767 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2768 {
2769 kvm_x86_ops->vcpu_put(vcpu);
2770 kvm_put_guest_fpu(vcpu);
2771 vcpu->arch.last_host_tsc = native_read_tsc();
2772 }
2773
2774 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2775 struct kvm_lapic_state *s)
2776 {
2777 kvm_x86_ops->sync_pir_to_irr(vcpu);
2778 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2779
2780 return 0;
2781 }
2782
2783 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2784 struct kvm_lapic_state *s)
2785 {
2786 kvm_apic_post_state_restore(vcpu, s);
2787 update_cr8_intercept(vcpu);
2788
2789 return 0;
2790 }
2791
2792 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2793 struct kvm_interrupt *irq)
2794 {
2795 if (irq->irq >= KVM_NR_INTERRUPTS)
2796 return -EINVAL;
2797 if (irqchip_in_kernel(vcpu->kvm))
2798 return -ENXIO;
2799
2800 kvm_queue_interrupt(vcpu, irq->irq, false);
2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
2802
2803 return 0;
2804 }
2805
2806 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2807 {
2808 kvm_inject_nmi(vcpu);
2809
2810 return 0;
2811 }
2812
2813 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2814 struct kvm_tpr_access_ctl *tac)
2815 {
2816 if (tac->flags)
2817 return -EINVAL;
2818 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2819 return 0;
2820 }
2821
2822 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2823 u64 mcg_cap)
2824 {
2825 int r;
2826 unsigned bank_num = mcg_cap & 0xff, bank;
2827
2828 r = -EINVAL;
2829 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2830 goto out;
2831 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2832 goto out;
2833 r = 0;
2834 vcpu->arch.mcg_cap = mcg_cap;
2835 /* Init IA32_MCG_CTL to all 1s */
2836 if (mcg_cap & MCG_CTL_P)
2837 vcpu->arch.mcg_ctl = ~(u64)0;
2838 /* Init IA32_MCi_CTL to all 1s */
2839 for (bank = 0; bank < bank_num; bank++)
2840 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2841 out:
2842 return r;
2843 }
2844
2845 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2846 struct kvm_x86_mce *mce)
2847 {
2848 u64 mcg_cap = vcpu->arch.mcg_cap;
2849 unsigned bank_num = mcg_cap & 0xff;
2850 u64 *banks = vcpu->arch.mce_banks;
2851
2852 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2853 return -EINVAL;
2854 /*
2855 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2856 * reporting is disabled
2857 */
2858 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2859 vcpu->arch.mcg_ctl != ~(u64)0)
2860 return 0;
2861 banks += 4 * mce->bank;
2862 /*
2863 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2864 * reporting is disabled for the bank
2865 */
2866 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2867 return 0;
2868 if (mce->status & MCI_STATUS_UC) {
2869 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2870 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2871 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2872 return 0;
2873 }
2874 if (banks[1] & MCI_STATUS_VAL)
2875 mce->status |= MCI_STATUS_OVER;
2876 banks[2] = mce->addr;
2877 banks[3] = mce->misc;
2878 vcpu->arch.mcg_status = mce->mcg_status;
2879 banks[1] = mce->status;
2880 kvm_queue_exception(vcpu, MC_VECTOR);
2881 } else if (!(banks[1] & MCI_STATUS_VAL)
2882 || !(banks[1] & MCI_STATUS_UC)) {
2883 if (banks[1] & MCI_STATUS_VAL)
2884 mce->status |= MCI_STATUS_OVER;
2885 banks[2] = mce->addr;
2886 banks[3] = mce->misc;
2887 banks[1] = mce->status;
2888 } else
2889 banks[1] |= MCI_STATUS_OVER;
2890 return 0;
2891 }
2892
2893 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2894 struct kvm_vcpu_events *events)
2895 {
2896 process_nmi(vcpu);
2897 events->exception.injected =
2898 vcpu->arch.exception.pending &&
2899 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2900 events->exception.nr = vcpu->arch.exception.nr;
2901 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2902 events->exception.pad = 0;
2903 events->exception.error_code = vcpu->arch.exception.error_code;
2904
2905 events->interrupt.injected =
2906 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2907 events->interrupt.nr = vcpu->arch.interrupt.nr;
2908 events->interrupt.soft = 0;
2909 events->interrupt.shadow =
2910 kvm_x86_ops->get_interrupt_shadow(vcpu,
2911 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2912
2913 events->nmi.injected = vcpu->arch.nmi_injected;
2914 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2915 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2916 events->nmi.pad = 0;
2917
2918 events->sipi_vector = 0; /* never valid when reporting to user space */
2919
2920 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2921 | KVM_VCPUEVENT_VALID_SHADOW);
2922 memset(&events->reserved, 0, sizeof(events->reserved));
2923 }
2924
2925 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927 {
2928 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2929 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2930 | KVM_VCPUEVENT_VALID_SHADOW))
2931 return -EINVAL;
2932
2933 process_nmi(vcpu);
2934 vcpu->arch.exception.pending = events->exception.injected;
2935 vcpu->arch.exception.nr = events->exception.nr;
2936 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2937 vcpu->arch.exception.error_code = events->exception.error_code;
2938
2939 vcpu->arch.interrupt.pending = events->interrupt.injected;
2940 vcpu->arch.interrupt.nr = events->interrupt.nr;
2941 vcpu->arch.interrupt.soft = events->interrupt.soft;
2942 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2943 kvm_x86_ops->set_interrupt_shadow(vcpu,
2944 events->interrupt.shadow);
2945
2946 vcpu->arch.nmi_injected = events->nmi.injected;
2947 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2948 vcpu->arch.nmi_pending = events->nmi.pending;
2949 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2950
2951 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2952 kvm_vcpu_has_lapic(vcpu))
2953 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2954
2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
2956
2957 return 0;
2958 }
2959
2960 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2961 struct kvm_debugregs *dbgregs)
2962 {
2963 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2964 dbgregs->dr6 = vcpu->arch.dr6;
2965 dbgregs->dr7 = vcpu->arch.dr7;
2966 dbgregs->flags = 0;
2967 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2968 }
2969
2970 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2971 struct kvm_debugregs *dbgregs)
2972 {
2973 if (dbgregs->flags)
2974 return -EINVAL;
2975
2976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2977 vcpu->arch.dr6 = dbgregs->dr6;
2978 vcpu->arch.dr7 = dbgregs->dr7;
2979 kvm_update_dr7(vcpu);
2980
2981 return 0;
2982 }
2983
2984 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2985 struct kvm_xsave *guest_xsave)
2986 {
2987 if (cpu_has_xsave) {
2988 memcpy(guest_xsave->region,
2989 &vcpu->arch.guest_fpu.state->xsave,
2990 vcpu->arch.guest_xstate_size);
2991 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
2992 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
2993 } else {
2994 memcpy(guest_xsave->region,
2995 &vcpu->arch.guest_fpu.state->fxsave,
2996 sizeof(struct i387_fxsave_struct));
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2998 XSTATE_FPSSE;
2999 }
3000 }
3001
3002 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3003 struct kvm_xsave *guest_xsave)
3004 {
3005 u64 xstate_bv =
3006 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3007
3008 if (cpu_has_xsave) {
3009 /*
3010 * Here we allow setting states that are not present in
3011 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3012 * with old userspace.
3013 */
3014 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3015 return -EINVAL;
3016 if (xstate_bv & ~host_xcr0)
3017 return -EINVAL;
3018 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3019 guest_xsave->region, vcpu->arch.guest_xstate_size);
3020 } else {
3021 if (xstate_bv & ~XSTATE_FPSSE)
3022 return -EINVAL;
3023 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3024 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3025 }
3026 return 0;
3027 }
3028
3029 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031 {
3032 if (!cpu_has_xsave) {
3033 guest_xcrs->nr_xcrs = 0;
3034 return;
3035 }
3036
3037 guest_xcrs->nr_xcrs = 1;
3038 guest_xcrs->flags = 0;
3039 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3040 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3041 }
3042
3043 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3044 struct kvm_xcrs *guest_xcrs)
3045 {
3046 int i, r = 0;
3047
3048 if (!cpu_has_xsave)
3049 return -EINVAL;
3050
3051 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3052 return -EINVAL;
3053
3054 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3055 /* Only support XCR0 currently */
3056 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3057 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3058 guest_xcrs->xcrs[i].value);
3059 break;
3060 }
3061 if (r)
3062 r = -EINVAL;
3063 return r;
3064 }
3065
3066 /*
3067 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3068 * stopped by the hypervisor. This function will be called from the host only.
3069 * EINVAL is returned when the host attempts to set the flag for a guest that
3070 * does not support pv clocks.
3071 */
3072 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3073 {
3074 if (!vcpu->arch.pv_time_enabled)
3075 return -EINVAL;
3076 vcpu->arch.pvclock_set_guest_stopped_request = true;
3077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3078 return 0;
3079 }
3080
3081 long kvm_arch_vcpu_ioctl(struct file *filp,
3082 unsigned int ioctl, unsigned long arg)
3083 {
3084 struct kvm_vcpu *vcpu = filp->private_data;
3085 void __user *argp = (void __user *)arg;
3086 int r;
3087 union {
3088 struct kvm_lapic_state *lapic;
3089 struct kvm_xsave *xsave;
3090 struct kvm_xcrs *xcrs;
3091 void *buffer;
3092 } u;
3093
3094 u.buffer = NULL;
3095 switch (ioctl) {
3096 case KVM_GET_LAPIC: {
3097 r = -EINVAL;
3098 if (!vcpu->arch.apic)
3099 goto out;
3100 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3101
3102 r = -ENOMEM;
3103 if (!u.lapic)
3104 goto out;
3105 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3106 if (r)
3107 goto out;
3108 r = -EFAULT;
3109 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3110 goto out;
3111 r = 0;
3112 break;
3113 }
3114 case KVM_SET_LAPIC: {
3115 r = -EINVAL;
3116 if (!vcpu->arch.apic)
3117 goto out;
3118 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3119 if (IS_ERR(u.lapic))
3120 return PTR_ERR(u.lapic);
3121
3122 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3123 break;
3124 }
3125 case KVM_INTERRUPT: {
3126 struct kvm_interrupt irq;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&irq, argp, sizeof irq))
3130 goto out;
3131 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3132 break;
3133 }
3134 case KVM_NMI: {
3135 r = kvm_vcpu_ioctl_nmi(vcpu);
3136 break;
3137 }
3138 case KVM_SET_CPUID: {
3139 struct kvm_cpuid __user *cpuid_arg = argp;
3140 struct kvm_cpuid cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3146 break;
3147 }
3148 case KVM_SET_CPUID2: {
3149 struct kvm_cpuid2 __user *cpuid_arg = argp;
3150 struct kvm_cpuid2 cpuid;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 goto out;
3155 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3156 cpuid_arg->entries);
3157 break;
3158 }
3159 case KVM_GET_CPUID2: {
3160 struct kvm_cpuid2 __user *cpuid_arg = argp;
3161 struct kvm_cpuid2 cpuid;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3165 goto out;
3166 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3167 cpuid_arg->entries);
3168 if (r)
3169 goto out;
3170 r = -EFAULT;
3171 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3172 goto out;
3173 r = 0;
3174 break;
3175 }
3176 case KVM_GET_MSRS:
3177 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3178 break;
3179 case KVM_SET_MSRS:
3180 r = msr_io(vcpu, argp, do_set_msr, 0);
3181 break;
3182 case KVM_TPR_ACCESS_REPORTING: {
3183 struct kvm_tpr_access_ctl tac;
3184
3185 r = -EFAULT;
3186 if (copy_from_user(&tac, argp, sizeof tac))
3187 goto out;
3188 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3189 if (r)
3190 goto out;
3191 r = -EFAULT;
3192 if (copy_to_user(argp, &tac, sizeof tac))
3193 goto out;
3194 r = 0;
3195 break;
3196 };
3197 case KVM_SET_VAPIC_ADDR: {
3198 struct kvm_vapic_addr va;
3199
3200 r = -EINVAL;
3201 if (!irqchip_in_kernel(vcpu->kvm))
3202 goto out;
3203 r = -EFAULT;
3204 if (copy_from_user(&va, argp, sizeof va))
3205 goto out;
3206 r = 0;
3207 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3208 break;
3209 }
3210 case KVM_X86_SETUP_MCE: {
3211 u64 mcg_cap;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3215 goto out;
3216 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3217 break;
3218 }
3219 case KVM_X86_SET_MCE: {
3220 struct kvm_x86_mce mce;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&mce, argp, sizeof mce))
3224 goto out;
3225 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3226 break;
3227 }
3228 case KVM_GET_VCPU_EVENTS: {
3229 struct kvm_vcpu_events events;
3230
3231 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3232
3233 r = -EFAULT;
3234 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3235 break;
3236 r = 0;
3237 break;
3238 }
3239 case KVM_SET_VCPU_EVENTS: {
3240 struct kvm_vcpu_events events;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3247 break;
3248 }
3249 case KVM_GET_DEBUGREGS: {
3250 struct kvm_debugregs dbgregs;
3251
3252 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3253
3254 r = -EFAULT;
3255 if (copy_to_user(argp, &dbgregs,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258 r = 0;
3259 break;
3260 }
3261 case KVM_SET_DEBUGREGS: {
3262 struct kvm_debugregs dbgregs;
3263
3264 r = -EFAULT;
3265 if (copy_from_user(&dbgregs, argp,
3266 sizeof(struct kvm_debugregs)))
3267 break;
3268
3269 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3270 break;
3271 }
3272 case KVM_GET_XSAVE: {
3273 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3274 r = -ENOMEM;
3275 if (!u.xsave)
3276 break;
3277
3278 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3279
3280 r = -EFAULT;
3281 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XSAVE: {
3287 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3288 if (IS_ERR(u.xsave))
3289 return PTR_ERR(u.xsave);
3290
3291 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3292 break;
3293 }
3294 case KVM_GET_XCRS: {
3295 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3296 r = -ENOMEM;
3297 if (!u.xcrs)
3298 break;
3299
3300 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3301
3302 r = -EFAULT;
3303 if (copy_to_user(argp, u.xcrs,
3304 sizeof(struct kvm_xcrs)))
3305 break;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_SET_XCRS: {
3310 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3311 if (IS_ERR(u.xcrs))
3312 return PTR_ERR(u.xcrs);
3313
3314 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3315 break;
3316 }
3317 case KVM_SET_TSC_KHZ: {
3318 u32 user_tsc_khz;
3319
3320 r = -EINVAL;
3321 user_tsc_khz = (u32)arg;
3322
3323 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3324 goto out;
3325
3326 if (user_tsc_khz == 0)
3327 user_tsc_khz = tsc_khz;
3328
3329 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3330
3331 r = 0;
3332 goto out;
3333 }
3334 case KVM_GET_TSC_KHZ: {
3335 r = vcpu->arch.virtual_tsc_khz;
3336 goto out;
3337 }
3338 case KVM_KVMCLOCK_CTRL: {
3339 r = kvm_set_guest_paused(vcpu);
3340 goto out;
3341 }
3342 default:
3343 r = -EINVAL;
3344 }
3345 out:
3346 kfree(u.buffer);
3347 return r;
3348 }
3349
3350 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3351 {
3352 return VM_FAULT_SIGBUS;
3353 }
3354
3355 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3356 {
3357 int ret;
3358
3359 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3360 return -EINVAL;
3361 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3362 return ret;
3363 }
3364
3365 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3366 u64 ident_addr)
3367 {
3368 kvm->arch.ept_identity_map_addr = ident_addr;
3369 return 0;
3370 }
3371
3372 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3373 u32 kvm_nr_mmu_pages)
3374 {
3375 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3376 return -EINVAL;
3377
3378 mutex_lock(&kvm->slots_lock);
3379
3380 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3381 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3382
3383 mutex_unlock(&kvm->slots_lock);
3384 return 0;
3385 }
3386
3387 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3388 {
3389 return kvm->arch.n_max_mmu_pages;
3390 }
3391
3392 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3393 {
3394 int r;
3395
3396 r = 0;
3397 switch (chip->chip_id) {
3398 case KVM_IRQCHIP_PIC_MASTER:
3399 memcpy(&chip->chip.pic,
3400 &pic_irqchip(kvm)->pics[0],
3401 sizeof(struct kvm_pic_state));
3402 break;
3403 case KVM_IRQCHIP_PIC_SLAVE:
3404 memcpy(&chip->chip.pic,
3405 &pic_irqchip(kvm)->pics[1],
3406 sizeof(struct kvm_pic_state));
3407 break;
3408 case KVM_IRQCHIP_IOAPIC:
3409 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3410 break;
3411 default:
3412 r = -EINVAL;
3413 break;
3414 }
3415 return r;
3416 }
3417
3418 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3419 {
3420 int r;
3421
3422 r = 0;
3423 switch (chip->chip_id) {
3424 case KVM_IRQCHIP_PIC_MASTER:
3425 spin_lock(&pic_irqchip(kvm)->lock);
3426 memcpy(&pic_irqchip(kvm)->pics[0],
3427 &chip->chip.pic,
3428 sizeof(struct kvm_pic_state));
3429 spin_unlock(&pic_irqchip(kvm)->lock);
3430 break;
3431 case KVM_IRQCHIP_PIC_SLAVE:
3432 spin_lock(&pic_irqchip(kvm)->lock);
3433 memcpy(&pic_irqchip(kvm)->pics[1],
3434 &chip->chip.pic,
3435 sizeof(struct kvm_pic_state));
3436 spin_unlock(&pic_irqchip(kvm)->lock);
3437 break;
3438 case KVM_IRQCHIP_IOAPIC:
3439 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3440 break;
3441 default:
3442 r = -EINVAL;
3443 break;
3444 }
3445 kvm_pic_update_irq(pic_irqchip(kvm));
3446 return r;
3447 }
3448
3449 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450 {
3451 int r = 0;
3452
3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3454 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3456 return r;
3457 }
3458
3459 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3460 {
3461 int r = 0;
3462
3463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3464 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3465 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3466 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3467 return r;
3468 }
3469
3470 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3471 {
3472 int r = 0;
3473
3474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3475 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3476 sizeof(ps->channels));
3477 ps->flags = kvm->arch.vpit->pit_state.flags;
3478 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3479 memset(&ps->reserved, 0, sizeof(ps->reserved));
3480 return r;
3481 }
3482
3483 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3484 {
3485 int r = 0, start = 0;
3486 u32 prev_legacy, cur_legacy;
3487 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3488 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3489 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3490 if (!prev_legacy && cur_legacy)
3491 start = 1;
3492 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3493 sizeof(kvm->arch.vpit->pit_state.channels));
3494 kvm->arch.vpit->pit_state.flags = ps->flags;
3495 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3497 return r;
3498 }
3499
3500 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3501 struct kvm_reinject_control *control)
3502 {
3503 if (!kvm->arch.vpit)
3504 return -ENXIO;
3505 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3506 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3507 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3508 return 0;
3509 }
3510
3511 /**
3512 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3513 * @kvm: kvm instance
3514 * @log: slot id and address to which we copy the log
3515 *
3516 * We need to keep it in mind that VCPU threads can write to the bitmap
3517 * concurrently. So, to avoid losing data, we keep the following order for
3518 * each bit:
3519 *
3520 * 1. Take a snapshot of the bit and clear it if needed.
3521 * 2. Write protect the corresponding page.
3522 * 3. Flush TLB's if needed.
3523 * 4. Copy the snapshot to the userspace.
3524 *
3525 * Between 2 and 3, the guest may write to the page using the remaining TLB
3526 * entry. This is not a problem because the page will be reported dirty at
3527 * step 4 using the snapshot taken before and step 3 ensures that successive
3528 * writes will be logged for the next call.
3529 */
3530 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3531 {
3532 int r;
3533 struct kvm_memory_slot *memslot;
3534 unsigned long n, i;
3535 unsigned long *dirty_bitmap;
3536 unsigned long *dirty_bitmap_buffer;
3537 bool is_dirty = false;
3538
3539 mutex_lock(&kvm->slots_lock);
3540
3541 r = -EINVAL;
3542 if (log->slot >= KVM_USER_MEM_SLOTS)
3543 goto out;
3544
3545 memslot = id_to_memslot(kvm->memslots, log->slot);
3546
3547 dirty_bitmap = memslot->dirty_bitmap;
3548 r = -ENOENT;
3549 if (!dirty_bitmap)
3550 goto out;
3551
3552 n = kvm_dirty_bitmap_bytes(memslot);
3553
3554 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3555 memset(dirty_bitmap_buffer, 0, n);
3556
3557 spin_lock(&kvm->mmu_lock);
3558
3559 for (i = 0; i < n / sizeof(long); i++) {
3560 unsigned long mask;
3561 gfn_t offset;
3562
3563 if (!dirty_bitmap[i])
3564 continue;
3565
3566 is_dirty = true;
3567
3568 mask = xchg(&dirty_bitmap[i], 0);
3569 dirty_bitmap_buffer[i] = mask;
3570
3571 offset = i * BITS_PER_LONG;
3572 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3573 }
3574 if (is_dirty)
3575 kvm_flush_remote_tlbs(kvm);
3576
3577 spin_unlock(&kvm->mmu_lock);
3578
3579 r = -EFAULT;
3580 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3581 goto out;
3582
3583 r = 0;
3584 out:
3585 mutex_unlock(&kvm->slots_lock);
3586 return r;
3587 }
3588
3589 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3590 bool line_status)
3591 {
3592 if (!irqchip_in_kernel(kvm))
3593 return -ENXIO;
3594
3595 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3596 irq_event->irq, irq_event->level,
3597 line_status);
3598 return 0;
3599 }
3600
3601 long kvm_arch_vm_ioctl(struct file *filp,
3602 unsigned int ioctl, unsigned long arg)
3603 {
3604 struct kvm *kvm = filp->private_data;
3605 void __user *argp = (void __user *)arg;
3606 int r = -ENOTTY;
3607 /*
3608 * This union makes it completely explicit to gcc-3.x
3609 * that these two variables' stack usage should be
3610 * combined, not added together.
3611 */
3612 union {
3613 struct kvm_pit_state ps;
3614 struct kvm_pit_state2 ps2;
3615 struct kvm_pit_config pit_config;
3616 } u;
3617
3618 switch (ioctl) {
3619 case KVM_SET_TSS_ADDR:
3620 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3621 break;
3622 case KVM_SET_IDENTITY_MAP_ADDR: {
3623 u64 ident_addr;
3624
3625 r = -EFAULT;
3626 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3627 goto out;
3628 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3629 break;
3630 }
3631 case KVM_SET_NR_MMU_PAGES:
3632 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3633 break;
3634 case KVM_GET_NR_MMU_PAGES:
3635 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3636 break;
3637 case KVM_CREATE_IRQCHIP: {
3638 struct kvm_pic *vpic;
3639
3640 mutex_lock(&kvm->lock);
3641 r = -EEXIST;
3642 if (kvm->arch.vpic)
3643 goto create_irqchip_unlock;
3644 r = -EINVAL;
3645 if (atomic_read(&kvm->online_vcpus))
3646 goto create_irqchip_unlock;
3647 r = -ENOMEM;
3648 vpic = kvm_create_pic(kvm);
3649 if (vpic) {
3650 r = kvm_ioapic_init(kvm);
3651 if (r) {
3652 mutex_lock(&kvm->slots_lock);
3653 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3654 &vpic->dev_master);
3655 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3656 &vpic->dev_slave);
3657 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3658 &vpic->dev_eclr);
3659 mutex_unlock(&kvm->slots_lock);
3660 kfree(vpic);
3661 goto create_irqchip_unlock;
3662 }
3663 } else
3664 goto create_irqchip_unlock;
3665 smp_wmb();
3666 kvm->arch.vpic = vpic;
3667 smp_wmb();
3668 r = kvm_setup_default_irq_routing(kvm);
3669 if (r) {
3670 mutex_lock(&kvm->slots_lock);
3671 mutex_lock(&kvm->irq_lock);
3672 kvm_ioapic_destroy(kvm);
3673 kvm_destroy_pic(kvm);
3674 mutex_unlock(&kvm->irq_lock);
3675 mutex_unlock(&kvm->slots_lock);
3676 }
3677 create_irqchip_unlock:
3678 mutex_unlock(&kvm->lock);
3679 break;
3680 }
3681 case KVM_CREATE_PIT:
3682 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3683 goto create_pit;
3684 case KVM_CREATE_PIT2:
3685 r = -EFAULT;
3686 if (copy_from_user(&u.pit_config, argp,
3687 sizeof(struct kvm_pit_config)))
3688 goto out;
3689 create_pit:
3690 mutex_lock(&kvm->slots_lock);
3691 r = -EEXIST;
3692 if (kvm->arch.vpit)
3693 goto create_pit_unlock;
3694 r = -ENOMEM;
3695 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3696 if (kvm->arch.vpit)
3697 r = 0;
3698 create_pit_unlock:
3699 mutex_unlock(&kvm->slots_lock);
3700 break;
3701 case KVM_GET_IRQCHIP: {
3702 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3703 struct kvm_irqchip *chip;
3704
3705 chip = memdup_user(argp, sizeof(*chip));
3706 if (IS_ERR(chip)) {
3707 r = PTR_ERR(chip);
3708 goto out;
3709 }
3710
3711 r = -ENXIO;
3712 if (!irqchip_in_kernel(kvm))
3713 goto get_irqchip_out;
3714 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3715 if (r)
3716 goto get_irqchip_out;
3717 r = -EFAULT;
3718 if (copy_to_user(argp, chip, sizeof *chip))
3719 goto get_irqchip_out;
3720 r = 0;
3721 get_irqchip_out:
3722 kfree(chip);
3723 break;
3724 }
3725 case KVM_SET_IRQCHIP: {
3726 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3727 struct kvm_irqchip *chip;
3728
3729 chip = memdup_user(argp, sizeof(*chip));
3730 if (IS_ERR(chip)) {
3731 r = PTR_ERR(chip);
3732 goto out;
3733 }
3734
3735 r = -ENXIO;
3736 if (!irqchip_in_kernel(kvm))
3737 goto set_irqchip_out;
3738 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3739 if (r)
3740 goto set_irqchip_out;
3741 r = 0;
3742 set_irqchip_out:
3743 kfree(chip);
3744 break;
3745 }
3746 case KVM_GET_PIT: {
3747 r = -EFAULT;
3748 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3749 goto out;
3750 r = -ENXIO;
3751 if (!kvm->arch.vpit)
3752 goto out;
3753 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3754 if (r)
3755 goto out;
3756 r = -EFAULT;
3757 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3758 goto out;
3759 r = 0;
3760 break;
3761 }
3762 case KVM_SET_PIT: {
3763 r = -EFAULT;
3764 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3765 goto out;
3766 r = -ENXIO;
3767 if (!kvm->arch.vpit)
3768 goto out;
3769 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3770 break;
3771 }
3772 case KVM_GET_PIT2: {
3773 r = -ENXIO;
3774 if (!kvm->arch.vpit)
3775 goto out;
3776 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3777 if (r)
3778 goto out;
3779 r = -EFAULT;
3780 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3781 goto out;
3782 r = 0;
3783 break;
3784 }
3785 case KVM_SET_PIT2: {
3786 r = -EFAULT;
3787 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3788 goto out;
3789 r = -ENXIO;
3790 if (!kvm->arch.vpit)
3791 goto out;
3792 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3793 break;
3794 }
3795 case KVM_REINJECT_CONTROL: {
3796 struct kvm_reinject_control control;
3797 r = -EFAULT;
3798 if (copy_from_user(&control, argp, sizeof(control)))
3799 goto out;
3800 r = kvm_vm_ioctl_reinject(kvm, &control);
3801 break;
3802 }
3803 case KVM_XEN_HVM_CONFIG: {
3804 r = -EFAULT;
3805 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3806 sizeof(struct kvm_xen_hvm_config)))
3807 goto out;
3808 r = -EINVAL;
3809 if (kvm->arch.xen_hvm_config.flags)
3810 goto out;
3811 r = 0;
3812 break;
3813 }
3814 case KVM_SET_CLOCK: {
3815 struct kvm_clock_data user_ns;
3816 u64 now_ns;
3817 s64 delta;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3821 goto out;
3822
3823 r = -EINVAL;
3824 if (user_ns.flags)
3825 goto out;
3826
3827 r = 0;
3828 local_irq_disable();
3829 now_ns = get_kernel_ns();
3830 delta = user_ns.clock - now_ns;
3831 local_irq_enable();
3832 kvm->arch.kvmclock_offset = delta;
3833 kvm_gen_update_masterclock(kvm);
3834 break;
3835 }
3836 case KVM_GET_CLOCK: {
3837 struct kvm_clock_data user_ns;
3838 u64 now_ns;
3839
3840 local_irq_disable();
3841 now_ns = get_kernel_ns();
3842 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3843 local_irq_enable();
3844 user_ns.flags = 0;
3845 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3846
3847 r = -EFAULT;
3848 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3849 goto out;
3850 r = 0;
3851 break;
3852 }
3853
3854 default:
3855 ;
3856 }
3857 out:
3858 return r;
3859 }
3860
3861 static void kvm_init_msr_list(void)
3862 {
3863 u32 dummy[2];
3864 unsigned i, j;
3865
3866 /* skip the first msrs in the list. KVM-specific */
3867 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3868 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3869 continue;
3870 if (j < i)
3871 msrs_to_save[j] = msrs_to_save[i];
3872 j++;
3873 }
3874 num_msrs_to_save = j;
3875 }
3876
3877 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3878 const void *v)
3879 {
3880 int handled = 0;
3881 int n;
3882
3883 do {
3884 n = min(len, 8);
3885 if (!(vcpu->arch.apic &&
3886 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3887 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3888 break;
3889 handled += n;
3890 addr += n;
3891 len -= n;
3892 v += n;
3893 } while (len);
3894
3895 return handled;
3896 }
3897
3898 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3899 {
3900 int handled = 0;
3901 int n;
3902
3903 do {
3904 n = min(len, 8);
3905 if (!(vcpu->arch.apic &&
3906 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3907 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3908 break;
3909 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3910 handled += n;
3911 addr += n;
3912 len -= n;
3913 v += n;
3914 } while (len);
3915
3916 return handled;
3917 }
3918
3919 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3920 struct kvm_segment *var, int seg)
3921 {
3922 kvm_x86_ops->set_segment(vcpu, var, seg);
3923 }
3924
3925 void kvm_get_segment(struct kvm_vcpu *vcpu,
3926 struct kvm_segment *var, int seg)
3927 {
3928 kvm_x86_ops->get_segment(vcpu, var, seg);
3929 }
3930
3931 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3932 {
3933 gpa_t t_gpa;
3934 struct x86_exception exception;
3935
3936 BUG_ON(!mmu_is_nested(vcpu));
3937
3938 /* NPT walks are always user-walks */
3939 access |= PFERR_USER_MASK;
3940 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3941
3942 return t_gpa;
3943 }
3944
3945 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3946 struct x86_exception *exception)
3947 {
3948 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3949 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3950 }
3951
3952 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3953 struct x86_exception *exception)
3954 {
3955 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3956 access |= PFERR_FETCH_MASK;
3957 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3958 }
3959
3960 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3961 struct x86_exception *exception)
3962 {
3963 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3964 access |= PFERR_WRITE_MASK;
3965 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3966 }
3967
3968 /* uses this to access any guest's mapped memory without checking CPL */
3969 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3970 struct x86_exception *exception)
3971 {
3972 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3973 }
3974
3975 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3976 struct kvm_vcpu *vcpu, u32 access,
3977 struct x86_exception *exception)
3978 {
3979 void *data = val;
3980 int r = X86EMUL_CONTINUE;
3981
3982 while (bytes) {
3983 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3984 exception);
3985 unsigned offset = addr & (PAGE_SIZE-1);
3986 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3987 int ret;
3988
3989 if (gpa == UNMAPPED_GVA)
3990 return X86EMUL_PROPAGATE_FAULT;
3991 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3992 if (ret < 0) {
3993 r = X86EMUL_IO_NEEDED;
3994 goto out;
3995 }
3996
3997 bytes -= toread;
3998 data += toread;
3999 addr += toread;
4000 }
4001 out:
4002 return r;
4003 }
4004
4005 /* used for instruction fetching */
4006 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4007 gva_t addr, void *val, unsigned int bytes,
4008 struct x86_exception *exception)
4009 {
4010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4011 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4012
4013 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4014 access | PFERR_FETCH_MASK,
4015 exception);
4016 }
4017
4018 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4019 gva_t addr, void *val, unsigned int bytes,
4020 struct x86_exception *exception)
4021 {
4022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4023 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4024
4025 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4026 exception);
4027 }
4028 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4029
4030 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4031 gva_t addr, void *val, unsigned int bytes,
4032 struct x86_exception *exception)
4033 {
4034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4035 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4036 }
4037
4038 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4039 gva_t addr, void *val,
4040 unsigned int bytes,
4041 struct x86_exception *exception)
4042 {
4043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4044 void *data = val;
4045 int r = X86EMUL_CONTINUE;
4046
4047 while (bytes) {
4048 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4049 PFERR_WRITE_MASK,
4050 exception);
4051 unsigned offset = addr & (PAGE_SIZE-1);
4052 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4053 int ret;
4054
4055 if (gpa == UNMAPPED_GVA)
4056 return X86EMUL_PROPAGATE_FAULT;
4057 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4058 if (ret < 0) {
4059 r = X86EMUL_IO_NEEDED;
4060 goto out;
4061 }
4062
4063 bytes -= towrite;
4064 data += towrite;
4065 addr += towrite;
4066 }
4067 out:
4068 return r;
4069 }
4070 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4071
4072 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4073 gpa_t *gpa, struct x86_exception *exception,
4074 bool write)
4075 {
4076 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4077 | (write ? PFERR_WRITE_MASK : 0);
4078
4079 if (vcpu_match_mmio_gva(vcpu, gva)
4080 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4081 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4082 (gva & (PAGE_SIZE - 1));
4083 trace_vcpu_match_mmio(gva, *gpa, write, false);
4084 return 1;
4085 }
4086
4087 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4088
4089 if (*gpa == UNMAPPED_GVA)
4090 return -1;
4091
4092 /* For APIC access vmexit */
4093 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4094 return 1;
4095
4096 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4097 trace_vcpu_match_mmio(gva, *gpa, write, true);
4098 return 1;
4099 }
4100
4101 return 0;
4102 }
4103
4104 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4105 const void *val, int bytes)
4106 {
4107 int ret;
4108
4109 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4110 if (ret < 0)
4111 return 0;
4112 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4113 return 1;
4114 }
4115
4116 struct read_write_emulator_ops {
4117 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4118 int bytes);
4119 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes);
4121 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4122 int bytes, void *val);
4123 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4124 void *val, int bytes);
4125 bool write;
4126 };
4127
4128 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4129 {
4130 if (vcpu->mmio_read_completed) {
4131 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4132 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4133 vcpu->mmio_read_completed = 0;
4134 return 1;
4135 }
4136
4137 return 0;
4138 }
4139
4140 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4141 void *val, int bytes)
4142 {
4143 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4144 }
4145
4146 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4147 void *val, int bytes)
4148 {
4149 return emulator_write_phys(vcpu, gpa, val, bytes);
4150 }
4151
4152 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4153 {
4154 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4155 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4156 }
4157
4158 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4159 void *val, int bytes)
4160 {
4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4162 return X86EMUL_IO_NEEDED;
4163 }
4164
4165 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4166 void *val, int bytes)
4167 {
4168 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4169
4170 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4171 return X86EMUL_CONTINUE;
4172 }
4173
4174 static const struct read_write_emulator_ops read_emultor = {
4175 .read_write_prepare = read_prepare,
4176 .read_write_emulate = read_emulate,
4177 .read_write_mmio = vcpu_mmio_read,
4178 .read_write_exit_mmio = read_exit_mmio,
4179 };
4180
4181 static const struct read_write_emulator_ops write_emultor = {
4182 .read_write_emulate = write_emulate,
4183 .read_write_mmio = write_mmio,
4184 .read_write_exit_mmio = write_exit_mmio,
4185 .write = true,
4186 };
4187
4188 static int emulator_read_write_onepage(unsigned long addr, void *val,
4189 unsigned int bytes,
4190 struct x86_exception *exception,
4191 struct kvm_vcpu *vcpu,
4192 const struct read_write_emulator_ops *ops)
4193 {
4194 gpa_t gpa;
4195 int handled, ret;
4196 bool write = ops->write;
4197 struct kvm_mmio_fragment *frag;
4198
4199 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4200
4201 if (ret < 0)
4202 return X86EMUL_PROPAGATE_FAULT;
4203
4204 /* For APIC access vmexit */
4205 if (ret)
4206 goto mmio;
4207
4208 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4209 return X86EMUL_CONTINUE;
4210
4211 mmio:
4212 /*
4213 * Is this MMIO handled locally?
4214 */
4215 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4216 if (handled == bytes)
4217 return X86EMUL_CONTINUE;
4218
4219 gpa += handled;
4220 bytes -= handled;
4221 val += handled;
4222
4223 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4224 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4225 frag->gpa = gpa;
4226 frag->data = val;
4227 frag->len = bytes;
4228 return X86EMUL_CONTINUE;
4229 }
4230
4231 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4232 void *val, unsigned int bytes,
4233 struct x86_exception *exception,
4234 const struct read_write_emulator_ops *ops)
4235 {
4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4237 gpa_t gpa;
4238 int rc;
4239
4240 if (ops->read_write_prepare &&
4241 ops->read_write_prepare(vcpu, val, bytes))
4242 return X86EMUL_CONTINUE;
4243
4244 vcpu->mmio_nr_fragments = 0;
4245
4246 /* Crossing a page boundary? */
4247 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4248 int now;
4249
4250 now = -addr & ~PAGE_MASK;
4251 rc = emulator_read_write_onepage(addr, val, now, exception,
4252 vcpu, ops);
4253
4254 if (rc != X86EMUL_CONTINUE)
4255 return rc;
4256 addr += now;
4257 val += now;
4258 bytes -= now;
4259 }
4260
4261 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4262 vcpu, ops);
4263 if (rc != X86EMUL_CONTINUE)
4264 return rc;
4265
4266 if (!vcpu->mmio_nr_fragments)
4267 return rc;
4268
4269 gpa = vcpu->mmio_fragments[0].gpa;
4270
4271 vcpu->mmio_needed = 1;
4272 vcpu->mmio_cur_fragment = 0;
4273
4274 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4275 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4276 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4277 vcpu->run->mmio.phys_addr = gpa;
4278
4279 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4280 }
4281
4282 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr,
4284 void *val,
4285 unsigned int bytes,
4286 struct x86_exception *exception)
4287 {
4288 return emulator_read_write(ctxt, addr, val, bytes,
4289 exception, &read_emultor);
4290 }
4291
4292 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4293 unsigned long addr,
4294 const void *val,
4295 unsigned int bytes,
4296 struct x86_exception *exception)
4297 {
4298 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4299 exception, &write_emultor);
4300 }
4301
4302 #define CMPXCHG_TYPE(t, ptr, old, new) \
4303 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4304
4305 #ifdef CONFIG_X86_64
4306 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4307 #else
4308 # define CMPXCHG64(ptr, old, new) \
4309 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4310 #endif
4311
4312 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
4314 const void *old,
4315 const void *new,
4316 unsigned int bytes,
4317 struct x86_exception *exception)
4318 {
4319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4320 gpa_t gpa;
4321 struct page *page;
4322 char *kaddr;
4323 bool exchanged;
4324
4325 /* guests cmpxchg8b have to be emulated atomically */
4326 if (bytes > 8 || (bytes & (bytes - 1)))
4327 goto emul_write;
4328
4329 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4330
4331 if (gpa == UNMAPPED_GVA ||
4332 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4333 goto emul_write;
4334
4335 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4336 goto emul_write;
4337
4338 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4339 if (is_error_page(page))
4340 goto emul_write;
4341
4342 kaddr = kmap_atomic(page);
4343 kaddr += offset_in_page(gpa);
4344 switch (bytes) {
4345 case 1:
4346 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4347 break;
4348 case 2:
4349 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4350 break;
4351 case 4:
4352 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4353 break;
4354 case 8:
4355 exchanged = CMPXCHG64(kaddr, old, new);
4356 break;
4357 default:
4358 BUG();
4359 }
4360 kunmap_atomic(kaddr);
4361 kvm_release_page_dirty(page);
4362
4363 if (!exchanged)
4364 return X86EMUL_CMPXCHG_FAILED;
4365
4366 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4367
4368 return X86EMUL_CONTINUE;
4369
4370 emul_write:
4371 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4372
4373 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4374 }
4375
4376 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4377 {
4378 /* TODO: String I/O for in kernel device */
4379 int r;
4380
4381 if (vcpu->arch.pio.in)
4382 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4383 vcpu->arch.pio.size, pd);
4384 else
4385 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4386 vcpu->arch.pio.port, vcpu->arch.pio.size,
4387 pd);
4388 return r;
4389 }
4390
4391 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4392 unsigned short port, void *val,
4393 unsigned int count, bool in)
4394 {
4395 trace_kvm_pio(!in, port, size, count);
4396
4397 vcpu->arch.pio.port = port;
4398 vcpu->arch.pio.in = in;
4399 vcpu->arch.pio.count = count;
4400 vcpu->arch.pio.size = size;
4401
4402 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4403 vcpu->arch.pio.count = 0;
4404 return 1;
4405 }
4406
4407 vcpu->run->exit_reason = KVM_EXIT_IO;
4408 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4409 vcpu->run->io.size = size;
4410 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4411 vcpu->run->io.count = count;
4412 vcpu->run->io.port = port;
4413
4414 return 0;
4415 }
4416
4417 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4418 int size, unsigned short port, void *val,
4419 unsigned int count)
4420 {
4421 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4422 int ret;
4423
4424 if (vcpu->arch.pio.count)
4425 goto data_avail;
4426
4427 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4428 if (ret) {
4429 data_avail:
4430 memcpy(val, vcpu->arch.pio_data, size * count);
4431 vcpu->arch.pio.count = 0;
4432 return 1;
4433 }
4434
4435 return 0;
4436 }
4437
4438 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4439 int size, unsigned short port,
4440 const void *val, unsigned int count)
4441 {
4442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4443
4444 memcpy(vcpu->arch.pio_data, val, size * count);
4445 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4446 }
4447
4448 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4449 {
4450 return kvm_x86_ops->get_segment_base(vcpu, seg);
4451 }
4452
4453 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4454 {
4455 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4456 }
4457
4458 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4459 {
4460 if (!need_emulate_wbinvd(vcpu))
4461 return X86EMUL_CONTINUE;
4462
4463 if (kvm_x86_ops->has_wbinvd_exit()) {
4464 int cpu = get_cpu();
4465
4466 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4467 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4468 wbinvd_ipi, NULL, 1);
4469 put_cpu();
4470 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4471 } else
4472 wbinvd();
4473 return X86EMUL_CONTINUE;
4474 }
4475 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4476
4477 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4478 {
4479 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4480 }
4481
4482 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4483 {
4484 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4485 }
4486
4487 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4488 {
4489
4490 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4491 }
4492
4493 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4494 {
4495 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4496 }
4497
4498 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4499 {
4500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4501 unsigned long value;
4502
4503 switch (cr) {
4504 case 0:
4505 value = kvm_read_cr0(vcpu);
4506 break;
4507 case 2:
4508 value = vcpu->arch.cr2;
4509 break;
4510 case 3:
4511 value = kvm_read_cr3(vcpu);
4512 break;
4513 case 4:
4514 value = kvm_read_cr4(vcpu);
4515 break;
4516 case 8:
4517 value = kvm_get_cr8(vcpu);
4518 break;
4519 default:
4520 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4521 return 0;
4522 }
4523
4524 return value;
4525 }
4526
4527 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4528 {
4529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4530 int res = 0;
4531
4532 switch (cr) {
4533 case 0:
4534 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4535 break;
4536 case 2:
4537 vcpu->arch.cr2 = val;
4538 break;
4539 case 3:
4540 res = kvm_set_cr3(vcpu, val);
4541 break;
4542 case 4:
4543 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4544 break;
4545 case 8:
4546 res = kvm_set_cr8(vcpu, val);
4547 break;
4548 default:
4549 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4550 res = -1;
4551 }
4552
4553 return res;
4554 }
4555
4556 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4557 {
4558 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4559 }
4560
4561 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4562 {
4563 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4564 }
4565
4566 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4567 {
4568 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4569 }
4570
4571 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4572 {
4573 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4574 }
4575
4576 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4577 {
4578 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4579 }
4580
4581 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4582 {
4583 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4584 }
4585
4586 static unsigned long emulator_get_cached_segment_base(
4587 struct x86_emulate_ctxt *ctxt, int seg)
4588 {
4589 return get_segment_base(emul_to_vcpu(ctxt), seg);
4590 }
4591
4592 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4593 struct desc_struct *desc, u32 *base3,
4594 int seg)
4595 {
4596 struct kvm_segment var;
4597
4598 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4599 *selector = var.selector;
4600
4601 if (var.unusable) {
4602 memset(desc, 0, sizeof(*desc));
4603 return false;
4604 }
4605
4606 if (var.g)
4607 var.limit >>= 12;
4608 set_desc_limit(desc, var.limit);
4609 set_desc_base(desc, (unsigned long)var.base);
4610 #ifdef CONFIG_X86_64
4611 if (base3)
4612 *base3 = var.base >> 32;
4613 #endif
4614 desc->type = var.type;
4615 desc->s = var.s;
4616 desc->dpl = var.dpl;
4617 desc->p = var.present;
4618 desc->avl = var.avl;
4619 desc->l = var.l;
4620 desc->d = var.db;
4621 desc->g = var.g;
4622
4623 return true;
4624 }
4625
4626 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4627 struct desc_struct *desc, u32 base3,
4628 int seg)
4629 {
4630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4631 struct kvm_segment var;
4632
4633 var.selector = selector;
4634 var.base = get_desc_base(desc);
4635 #ifdef CONFIG_X86_64
4636 var.base |= ((u64)base3) << 32;
4637 #endif
4638 var.limit = get_desc_limit(desc);
4639 if (desc->g)
4640 var.limit = (var.limit << 12) | 0xfff;
4641 var.type = desc->type;
4642 var.present = desc->p;
4643 var.dpl = desc->dpl;
4644 var.db = desc->d;
4645 var.s = desc->s;
4646 var.l = desc->l;
4647 var.g = desc->g;
4648 var.avl = desc->avl;
4649 var.present = desc->p;
4650 var.unusable = !var.present;
4651 var.padding = 0;
4652
4653 kvm_set_segment(vcpu, &var, seg);
4654 return;
4655 }
4656
4657 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4658 u32 msr_index, u64 *pdata)
4659 {
4660 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4661 }
4662
4663 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4664 u32 msr_index, u64 data)
4665 {
4666 struct msr_data msr;
4667
4668 msr.data = data;
4669 msr.index = msr_index;
4670 msr.host_initiated = false;
4671 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4672 }
4673
4674 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4675 u32 pmc, u64 *pdata)
4676 {
4677 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4678 }
4679
4680 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4681 {
4682 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4683 }
4684
4685 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4686 {
4687 preempt_disable();
4688 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4689 /*
4690 * CR0.TS may reference the host fpu state, not the guest fpu state,
4691 * so it may be clear at this point.
4692 */
4693 clts();
4694 }
4695
4696 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4697 {
4698 preempt_enable();
4699 }
4700
4701 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4702 struct x86_instruction_info *info,
4703 enum x86_intercept_stage stage)
4704 {
4705 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4706 }
4707
4708 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4709 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4710 {
4711 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4712 }
4713
4714 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4715 {
4716 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4717 }
4718
4719 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4720 {
4721 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4722 }
4723
4724 static const struct x86_emulate_ops emulate_ops = {
4725 .read_gpr = emulator_read_gpr,
4726 .write_gpr = emulator_write_gpr,
4727 .read_std = kvm_read_guest_virt_system,
4728 .write_std = kvm_write_guest_virt_system,
4729 .fetch = kvm_fetch_guest_virt,
4730 .read_emulated = emulator_read_emulated,
4731 .write_emulated = emulator_write_emulated,
4732 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4733 .invlpg = emulator_invlpg,
4734 .pio_in_emulated = emulator_pio_in_emulated,
4735 .pio_out_emulated = emulator_pio_out_emulated,
4736 .get_segment = emulator_get_segment,
4737 .set_segment = emulator_set_segment,
4738 .get_cached_segment_base = emulator_get_cached_segment_base,
4739 .get_gdt = emulator_get_gdt,
4740 .get_idt = emulator_get_idt,
4741 .set_gdt = emulator_set_gdt,
4742 .set_idt = emulator_set_idt,
4743 .get_cr = emulator_get_cr,
4744 .set_cr = emulator_set_cr,
4745 .set_rflags = emulator_set_rflags,
4746 .cpl = emulator_get_cpl,
4747 .get_dr = emulator_get_dr,
4748 .set_dr = emulator_set_dr,
4749 .set_msr = emulator_set_msr,
4750 .get_msr = emulator_get_msr,
4751 .read_pmc = emulator_read_pmc,
4752 .halt = emulator_halt,
4753 .wbinvd = emulator_wbinvd,
4754 .fix_hypercall = emulator_fix_hypercall,
4755 .get_fpu = emulator_get_fpu,
4756 .put_fpu = emulator_put_fpu,
4757 .intercept = emulator_intercept,
4758 .get_cpuid = emulator_get_cpuid,
4759 };
4760
4761 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4762 {
4763 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4764 /*
4765 * an sti; sti; sequence only disable interrupts for the first
4766 * instruction. So, if the last instruction, be it emulated or
4767 * not, left the system with the INT_STI flag enabled, it
4768 * means that the last instruction is an sti. We should not
4769 * leave the flag on in this case. The same goes for mov ss
4770 */
4771 if (!(int_shadow & mask))
4772 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4773 }
4774
4775 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4776 {
4777 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4778 if (ctxt->exception.vector == PF_VECTOR)
4779 kvm_propagate_fault(vcpu, &ctxt->exception);
4780 else if (ctxt->exception.error_code_valid)
4781 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4782 ctxt->exception.error_code);
4783 else
4784 kvm_queue_exception(vcpu, ctxt->exception.vector);
4785 }
4786
4787 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4788 {
4789 memset(&ctxt->opcode_len, 0,
4790 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4791
4792 ctxt->fetch.start = 0;
4793 ctxt->fetch.end = 0;
4794 ctxt->io_read.pos = 0;
4795 ctxt->io_read.end = 0;
4796 ctxt->mem_read.pos = 0;
4797 ctxt->mem_read.end = 0;
4798 }
4799
4800 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4801 {
4802 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4803 int cs_db, cs_l;
4804
4805 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4806
4807 ctxt->eflags = kvm_get_rflags(vcpu);
4808 ctxt->eip = kvm_rip_read(vcpu);
4809 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4810 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4811 cs_l ? X86EMUL_MODE_PROT64 :
4812 cs_db ? X86EMUL_MODE_PROT32 :
4813 X86EMUL_MODE_PROT16;
4814 ctxt->guest_mode = is_guest_mode(vcpu);
4815
4816 init_decode_cache(ctxt);
4817 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4818 }
4819
4820 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4821 {
4822 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4823 int ret;
4824
4825 init_emulate_ctxt(vcpu);
4826
4827 ctxt->op_bytes = 2;
4828 ctxt->ad_bytes = 2;
4829 ctxt->_eip = ctxt->eip + inc_eip;
4830 ret = emulate_int_real(ctxt, irq);
4831
4832 if (ret != X86EMUL_CONTINUE)
4833 return EMULATE_FAIL;
4834
4835 ctxt->eip = ctxt->_eip;
4836 kvm_rip_write(vcpu, ctxt->eip);
4837 kvm_set_rflags(vcpu, ctxt->eflags);
4838
4839 if (irq == NMI_VECTOR)
4840 vcpu->arch.nmi_pending = 0;
4841 else
4842 vcpu->arch.interrupt.pending = false;
4843
4844 return EMULATE_DONE;
4845 }
4846 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4847
4848 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4849 {
4850 int r = EMULATE_DONE;
4851
4852 ++vcpu->stat.insn_emulation_fail;
4853 trace_kvm_emulate_insn_failed(vcpu);
4854 if (!is_guest_mode(vcpu)) {
4855 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4856 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4857 vcpu->run->internal.ndata = 0;
4858 r = EMULATE_FAIL;
4859 }
4860 kvm_queue_exception(vcpu, UD_VECTOR);
4861
4862 return r;
4863 }
4864
4865 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4866 bool write_fault_to_shadow_pgtable,
4867 int emulation_type)
4868 {
4869 gpa_t gpa = cr2;
4870 pfn_t pfn;
4871
4872 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4873 return false;
4874
4875 if (!vcpu->arch.mmu.direct_map) {
4876 /*
4877 * Write permission should be allowed since only
4878 * write access need to be emulated.
4879 */
4880 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4881
4882 /*
4883 * If the mapping is invalid in guest, let cpu retry
4884 * it to generate fault.
4885 */
4886 if (gpa == UNMAPPED_GVA)
4887 return true;
4888 }
4889
4890 /*
4891 * Do not retry the unhandleable instruction if it faults on the
4892 * readonly host memory, otherwise it will goto a infinite loop:
4893 * retry instruction -> write #PF -> emulation fail -> retry
4894 * instruction -> ...
4895 */
4896 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4897
4898 /*
4899 * If the instruction failed on the error pfn, it can not be fixed,
4900 * report the error to userspace.
4901 */
4902 if (is_error_noslot_pfn(pfn))
4903 return false;
4904
4905 kvm_release_pfn_clean(pfn);
4906
4907 /* The instructions are well-emulated on direct mmu. */
4908 if (vcpu->arch.mmu.direct_map) {
4909 unsigned int indirect_shadow_pages;
4910
4911 spin_lock(&vcpu->kvm->mmu_lock);
4912 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4913 spin_unlock(&vcpu->kvm->mmu_lock);
4914
4915 if (indirect_shadow_pages)
4916 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4917
4918 return true;
4919 }
4920
4921 /*
4922 * if emulation was due to access to shadowed page table
4923 * and it failed try to unshadow page and re-enter the
4924 * guest to let CPU execute the instruction.
4925 */
4926 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4927
4928 /*
4929 * If the access faults on its page table, it can not
4930 * be fixed by unprotecting shadow page and it should
4931 * be reported to userspace.
4932 */
4933 return !write_fault_to_shadow_pgtable;
4934 }
4935
4936 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4937 unsigned long cr2, int emulation_type)
4938 {
4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4940 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4941
4942 last_retry_eip = vcpu->arch.last_retry_eip;
4943 last_retry_addr = vcpu->arch.last_retry_addr;
4944
4945 /*
4946 * If the emulation is caused by #PF and it is non-page_table
4947 * writing instruction, it means the VM-EXIT is caused by shadow
4948 * page protected, we can zap the shadow page and retry this
4949 * instruction directly.
4950 *
4951 * Note: if the guest uses a non-page-table modifying instruction
4952 * on the PDE that points to the instruction, then we will unmap
4953 * the instruction and go to an infinite loop. So, we cache the
4954 * last retried eip and the last fault address, if we meet the eip
4955 * and the address again, we can break out of the potential infinite
4956 * loop.
4957 */
4958 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4959
4960 if (!(emulation_type & EMULTYPE_RETRY))
4961 return false;
4962
4963 if (x86_page_table_writing_insn(ctxt))
4964 return false;
4965
4966 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4967 return false;
4968
4969 vcpu->arch.last_retry_eip = ctxt->eip;
4970 vcpu->arch.last_retry_addr = cr2;
4971
4972 if (!vcpu->arch.mmu.direct_map)
4973 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4974
4975 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4976
4977 return true;
4978 }
4979
4980 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4981 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4982
4983 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4984 unsigned long *db)
4985 {
4986 u32 dr6 = 0;
4987 int i;
4988 u32 enable, rwlen;
4989
4990 enable = dr7;
4991 rwlen = dr7 >> 16;
4992 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4993 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4994 dr6 |= (1 << i);
4995 return dr6;
4996 }
4997
4998 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4999 {
5000 struct kvm_run *kvm_run = vcpu->run;
5001
5002 /*
5003 * Use the "raw" value to see if TF was passed to the processor.
5004 * Note that the new value of the flags has not been saved yet.
5005 *
5006 * This is correct even for TF set by the guest, because "the
5007 * processor will not generate this exception after the instruction
5008 * that sets the TF flag".
5009 */
5010 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5011
5012 if (unlikely(rflags & X86_EFLAGS_TF)) {
5013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5014 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5015 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5016 kvm_run->debug.arch.exception = DB_VECTOR;
5017 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5018 *r = EMULATE_USER_EXIT;
5019 } else {
5020 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5021 /*
5022 * "Certain debug exceptions may clear bit 0-3. The
5023 * remaining contents of the DR6 register are never
5024 * cleared by the processor".
5025 */
5026 vcpu->arch.dr6 &= ~15;
5027 vcpu->arch.dr6 |= DR6_BS;
5028 kvm_queue_exception(vcpu, DB_VECTOR);
5029 }
5030 }
5031 }
5032
5033 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5034 {
5035 struct kvm_run *kvm_run = vcpu->run;
5036 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5037 u32 dr6 = 0;
5038
5039 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5040 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5041 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5042 vcpu->arch.guest_debug_dr7,
5043 vcpu->arch.eff_db);
5044
5045 if (dr6 != 0) {
5046 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5047 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5048 get_segment_base(vcpu, VCPU_SREG_CS);
5049
5050 kvm_run->debug.arch.exception = DB_VECTOR;
5051 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5052 *r = EMULATE_USER_EXIT;
5053 return true;
5054 }
5055 }
5056
5057 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5058 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5059 vcpu->arch.dr7,
5060 vcpu->arch.db);
5061
5062 if (dr6 != 0) {
5063 vcpu->arch.dr6 &= ~15;
5064 vcpu->arch.dr6 |= dr6;
5065 kvm_queue_exception(vcpu, DB_VECTOR);
5066 *r = EMULATE_DONE;
5067 return true;
5068 }
5069 }
5070
5071 return false;
5072 }
5073
5074 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5075 unsigned long cr2,
5076 int emulation_type,
5077 void *insn,
5078 int insn_len)
5079 {
5080 int r;
5081 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5082 bool writeback = true;
5083 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5084
5085 /*
5086 * Clear write_fault_to_shadow_pgtable here to ensure it is
5087 * never reused.
5088 */
5089 vcpu->arch.write_fault_to_shadow_pgtable = false;
5090 kvm_clear_exception_queue(vcpu);
5091
5092 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5093 init_emulate_ctxt(vcpu);
5094
5095 /*
5096 * We will reenter on the same instruction since
5097 * we do not set complete_userspace_io. This does not
5098 * handle watchpoints yet, those would be handled in
5099 * the emulate_ops.
5100 */
5101 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5102 return r;
5103
5104 ctxt->interruptibility = 0;
5105 ctxt->have_exception = false;
5106 ctxt->perm_ok = false;
5107
5108 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5109
5110 r = x86_decode_insn(ctxt, insn, insn_len);
5111
5112 trace_kvm_emulate_insn_start(vcpu);
5113 ++vcpu->stat.insn_emulation;
5114 if (r != EMULATION_OK) {
5115 if (emulation_type & EMULTYPE_TRAP_UD)
5116 return EMULATE_FAIL;
5117 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5118 emulation_type))
5119 return EMULATE_DONE;
5120 if (emulation_type & EMULTYPE_SKIP)
5121 return EMULATE_FAIL;
5122 return handle_emulation_failure(vcpu);
5123 }
5124 }
5125
5126 if (emulation_type & EMULTYPE_SKIP) {
5127 kvm_rip_write(vcpu, ctxt->_eip);
5128 return EMULATE_DONE;
5129 }
5130
5131 if (retry_instruction(ctxt, cr2, emulation_type))
5132 return EMULATE_DONE;
5133
5134 /* this is needed for vmware backdoor interface to work since it
5135 changes registers values during IO operation */
5136 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5137 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5138 emulator_invalidate_register_cache(ctxt);
5139 }
5140
5141 restart:
5142 r = x86_emulate_insn(ctxt);
5143
5144 if (r == EMULATION_INTERCEPTED)
5145 return EMULATE_DONE;
5146
5147 if (r == EMULATION_FAILED) {
5148 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5149 emulation_type))
5150 return EMULATE_DONE;
5151
5152 return handle_emulation_failure(vcpu);
5153 }
5154
5155 if (ctxt->have_exception) {
5156 inject_emulated_exception(vcpu);
5157 r = EMULATE_DONE;
5158 } else if (vcpu->arch.pio.count) {
5159 if (!vcpu->arch.pio.in) {
5160 /* FIXME: return into emulator if single-stepping. */
5161 vcpu->arch.pio.count = 0;
5162 } else {
5163 writeback = false;
5164 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5165 }
5166 r = EMULATE_USER_EXIT;
5167 } else if (vcpu->mmio_needed) {
5168 if (!vcpu->mmio_is_write)
5169 writeback = false;
5170 r = EMULATE_USER_EXIT;
5171 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5172 } else if (r == EMULATION_RESTART)
5173 goto restart;
5174 else
5175 r = EMULATE_DONE;
5176
5177 if (writeback) {
5178 toggle_interruptibility(vcpu, ctxt->interruptibility);
5179 kvm_make_request(KVM_REQ_EVENT, vcpu);
5180 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5181 kvm_rip_write(vcpu, ctxt->eip);
5182 if (r == EMULATE_DONE)
5183 kvm_vcpu_check_singlestep(vcpu, &r);
5184 kvm_set_rflags(vcpu, ctxt->eflags);
5185 } else
5186 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5187
5188 return r;
5189 }
5190 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5191
5192 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5193 {
5194 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5195 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5196 size, port, &val, 1);
5197 /* do not return to emulator after return from userspace */
5198 vcpu->arch.pio.count = 0;
5199 return ret;
5200 }
5201 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5202
5203 static void tsc_bad(void *info)
5204 {
5205 __this_cpu_write(cpu_tsc_khz, 0);
5206 }
5207
5208 static void tsc_khz_changed(void *data)
5209 {
5210 struct cpufreq_freqs *freq = data;
5211 unsigned long khz = 0;
5212
5213 if (data)
5214 khz = freq->new;
5215 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5216 khz = cpufreq_quick_get(raw_smp_processor_id());
5217 if (!khz)
5218 khz = tsc_khz;
5219 __this_cpu_write(cpu_tsc_khz, khz);
5220 }
5221
5222 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5223 void *data)
5224 {
5225 struct cpufreq_freqs *freq = data;
5226 struct kvm *kvm;
5227 struct kvm_vcpu *vcpu;
5228 int i, send_ipi = 0;
5229
5230 /*
5231 * We allow guests to temporarily run on slowing clocks,
5232 * provided we notify them after, or to run on accelerating
5233 * clocks, provided we notify them before. Thus time never
5234 * goes backwards.
5235 *
5236 * However, we have a problem. We can't atomically update
5237 * the frequency of a given CPU from this function; it is
5238 * merely a notifier, which can be called from any CPU.
5239 * Changing the TSC frequency at arbitrary points in time
5240 * requires a recomputation of local variables related to
5241 * the TSC for each VCPU. We must flag these local variables
5242 * to be updated and be sure the update takes place with the
5243 * new frequency before any guests proceed.
5244 *
5245 * Unfortunately, the combination of hotplug CPU and frequency
5246 * change creates an intractable locking scenario; the order
5247 * of when these callouts happen is undefined with respect to
5248 * CPU hotplug, and they can race with each other. As such,
5249 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5250 * undefined; you can actually have a CPU frequency change take
5251 * place in between the computation of X and the setting of the
5252 * variable. To protect against this problem, all updates of
5253 * the per_cpu tsc_khz variable are done in an interrupt
5254 * protected IPI, and all callers wishing to update the value
5255 * must wait for a synchronous IPI to complete (which is trivial
5256 * if the caller is on the CPU already). This establishes the
5257 * necessary total order on variable updates.
5258 *
5259 * Note that because a guest time update may take place
5260 * anytime after the setting of the VCPU's request bit, the
5261 * correct TSC value must be set before the request. However,
5262 * to ensure the update actually makes it to any guest which
5263 * starts running in hardware virtualization between the set
5264 * and the acquisition of the spinlock, we must also ping the
5265 * CPU after setting the request bit.
5266 *
5267 */
5268
5269 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5270 return 0;
5271 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5272 return 0;
5273
5274 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5275
5276 spin_lock(&kvm_lock);
5277 list_for_each_entry(kvm, &vm_list, vm_list) {
5278 kvm_for_each_vcpu(i, vcpu, kvm) {
5279 if (vcpu->cpu != freq->cpu)
5280 continue;
5281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5282 if (vcpu->cpu != smp_processor_id())
5283 send_ipi = 1;
5284 }
5285 }
5286 spin_unlock(&kvm_lock);
5287
5288 if (freq->old < freq->new && send_ipi) {
5289 /*
5290 * We upscale the frequency. Must make the guest
5291 * doesn't see old kvmclock values while running with
5292 * the new frequency, otherwise we risk the guest sees
5293 * time go backwards.
5294 *
5295 * In case we update the frequency for another cpu
5296 * (which might be in guest context) send an interrupt
5297 * to kick the cpu out of guest context. Next time
5298 * guest context is entered kvmclock will be updated,
5299 * so the guest will not see stale values.
5300 */
5301 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5302 }
5303 return 0;
5304 }
5305
5306 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5307 .notifier_call = kvmclock_cpufreq_notifier
5308 };
5309
5310 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5311 unsigned long action, void *hcpu)
5312 {
5313 unsigned int cpu = (unsigned long)hcpu;
5314
5315 switch (action) {
5316 case CPU_ONLINE:
5317 case CPU_DOWN_FAILED:
5318 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5319 break;
5320 case CPU_DOWN_PREPARE:
5321 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5322 break;
5323 }
5324 return NOTIFY_OK;
5325 }
5326
5327 static struct notifier_block kvmclock_cpu_notifier_block = {
5328 .notifier_call = kvmclock_cpu_notifier,
5329 .priority = -INT_MAX
5330 };
5331
5332 static void kvm_timer_init(void)
5333 {
5334 int cpu;
5335
5336 max_tsc_khz = tsc_khz;
5337 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5338 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5339 #ifdef CONFIG_CPU_FREQ
5340 struct cpufreq_policy policy;
5341 memset(&policy, 0, sizeof(policy));
5342 cpu = get_cpu();
5343 cpufreq_get_policy(&policy, cpu);
5344 if (policy.cpuinfo.max_freq)
5345 max_tsc_khz = policy.cpuinfo.max_freq;
5346 put_cpu();
5347 #endif
5348 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5349 CPUFREQ_TRANSITION_NOTIFIER);
5350 }
5351 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5352 for_each_online_cpu(cpu)
5353 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5354 }
5355
5356 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5357
5358 int kvm_is_in_guest(void)
5359 {
5360 return __this_cpu_read(current_vcpu) != NULL;
5361 }
5362
5363 static int kvm_is_user_mode(void)
5364 {
5365 int user_mode = 3;
5366
5367 if (__this_cpu_read(current_vcpu))
5368 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5369
5370 return user_mode != 0;
5371 }
5372
5373 static unsigned long kvm_get_guest_ip(void)
5374 {
5375 unsigned long ip = 0;
5376
5377 if (__this_cpu_read(current_vcpu))
5378 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5379
5380 return ip;
5381 }
5382
5383 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5384 .is_in_guest = kvm_is_in_guest,
5385 .is_user_mode = kvm_is_user_mode,
5386 .get_guest_ip = kvm_get_guest_ip,
5387 };
5388
5389 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5390 {
5391 __this_cpu_write(current_vcpu, vcpu);
5392 }
5393 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5394
5395 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5396 {
5397 __this_cpu_write(current_vcpu, NULL);
5398 }
5399 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5400
5401 static void kvm_set_mmio_spte_mask(void)
5402 {
5403 u64 mask;
5404 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5405
5406 /*
5407 * Set the reserved bits and the present bit of an paging-structure
5408 * entry to generate page fault with PFER.RSV = 1.
5409 */
5410 /* Mask the reserved physical address bits. */
5411 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5412
5413 /* Bit 62 is always reserved for 32bit host. */
5414 mask |= 0x3ull << 62;
5415
5416 /* Set the present bit. */
5417 mask |= 1ull;
5418
5419 #ifdef CONFIG_X86_64
5420 /*
5421 * If reserved bit is not supported, clear the present bit to disable
5422 * mmio page fault.
5423 */
5424 if (maxphyaddr == 52)
5425 mask &= ~1ull;
5426 #endif
5427
5428 kvm_mmu_set_mmio_spte_mask(mask);
5429 }
5430
5431 #ifdef CONFIG_X86_64
5432 static void pvclock_gtod_update_fn(struct work_struct *work)
5433 {
5434 struct kvm *kvm;
5435
5436 struct kvm_vcpu *vcpu;
5437 int i;
5438
5439 spin_lock(&kvm_lock);
5440 list_for_each_entry(kvm, &vm_list, vm_list)
5441 kvm_for_each_vcpu(i, vcpu, kvm)
5442 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5443 atomic_set(&kvm_guest_has_master_clock, 0);
5444 spin_unlock(&kvm_lock);
5445 }
5446
5447 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5448
5449 /*
5450 * Notification about pvclock gtod data update.
5451 */
5452 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5453 void *priv)
5454 {
5455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5456 struct timekeeper *tk = priv;
5457
5458 update_pvclock_gtod(tk);
5459
5460 /* disable master clock if host does not trust, or does not
5461 * use, TSC clocksource
5462 */
5463 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5464 atomic_read(&kvm_guest_has_master_clock) != 0)
5465 queue_work(system_long_wq, &pvclock_gtod_work);
5466
5467 return 0;
5468 }
5469
5470 static struct notifier_block pvclock_gtod_notifier = {
5471 .notifier_call = pvclock_gtod_notify,
5472 };
5473 #endif
5474
5475 int kvm_arch_init(void *opaque)
5476 {
5477 int r;
5478 struct kvm_x86_ops *ops = opaque;
5479
5480 if (kvm_x86_ops) {
5481 printk(KERN_ERR "kvm: already loaded the other module\n");
5482 r = -EEXIST;
5483 goto out;
5484 }
5485
5486 if (!ops->cpu_has_kvm_support()) {
5487 printk(KERN_ERR "kvm: no hardware support\n");
5488 r = -EOPNOTSUPP;
5489 goto out;
5490 }
5491 if (ops->disabled_by_bios()) {
5492 printk(KERN_ERR "kvm: disabled by bios\n");
5493 r = -EOPNOTSUPP;
5494 goto out;
5495 }
5496
5497 r = -ENOMEM;
5498 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5499 if (!shared_msrs) {
5500 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5501 goto out;
5502 }
5503
5504 r = kvm_mmu_module_init();
5505 if (r)
5506 goto out_free_percpu;
5507
5508 kvm_set_mmio_spte_mask();
5509 kvm_init_msr_list();
5510
5511 kvm_x86_ops = ops;
5512 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5513 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5514
5515 kvm_timer_init();
5516
5517 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5518
5519 if (cpu_has_xsave)
5520 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5521
5522 kvm_lapic_init();
5523 #ifdef CONFIG_X86_64
5524 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5525 #endif
5526
5527 return 0;
5528
5529 out_free_percpu:
5530 free_percpu(shared_msrs);
5531 out:
5532 return r;
5533 }
5534
5535 void kvm_arch_exit(void)
5536 {
5537 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5538
5539 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5540 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5541 CPUFREQ_TRANSITION_NOTIFIER);
5542 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5543 #ifdef CONFIG_X86_64
5544 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5545 #endif
5546 kvm_x86_ops = NULL;
5547 kvm_mmu_module_exit();
5548 free_percpu(shared_msrs);
5549 }
5550
5551 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5552 {
5553 ++vcpu->stat.halt_exits;
5554 if (irqchip_in_kernel(vcpu->kvm)) {
5555 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5556 return 1;
5557 } else {
5558 vcpu->run->exit_reason = KVM_EXIT_HLT;
5559 return 0;
5560 }
5561 }
5562 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5563
5564 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5565 {
5566 u64 param, ingpa, outgpa, ret;
5567 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5568 bool fast, longmode;
5569 int cs_db, cs_l;
5570
5571 /*
5572 * hypercall generates UD from non zero cpl and real mode
5573 * per HYPER-V spec
5574 */
5575 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5576 kvm_queue_exception(vcpu, UD_VECTOR);
5577 return 0;
5578 }
5579
5580 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5581 longmode = is_long_mode(vcpu) && cs_l == 1;
5582
5583 if (!longmode) {
5584 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5585 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5586 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5587 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5588 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5589 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5590 }
5591 #ifdef CONFIG_X86_64
5592 else {
5593 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5594 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5595 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5596 }
5597 #endif
5598
5599 code = param & 0xffff;
5600 fast = (param >> 16) & 0x1;
5601 rep_cnt = (param >> 32) & 0xfff;
5602 rep_idx = (param >> 48) & 0xfff;
5603
5604 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5605
5606 switch (code) {
5607 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5608 kvm_vcpu_on_spin(vcpu);
5609 break;
5610 default:
5611 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5612 break;
5613 }
5614
5615 ret = res | (((u64)rep_done & 0xfff) << 32);
5616 if (longmode) {
5617 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5618 } else {
5619 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5620 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5621 }
5622
5623 return 1;
5624 }
5625
5626 /*
5627 * kvm_pv_kick_cpu_op: Kick a vcpu.
5628 *
5629 * @apicid - apicid of vcpu to be kicked.
5630 */
5631 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5632 {
5633 struct kvm_lapic_irq lapic_irq;
5634
5635 lapic_irq.shorthand = 0;
5636 lapic_irq.dest_mode = 0;
5637 lapic_irq.dest_id = apicid;
5638
5639 lapic_irq.delivery_mode = APIC_DM_REMRD;
5640 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5641 }
5642
5643 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5644 {
5645 unsigned long nr, a0, a1, a2, a3, ret;
5646 int r = 1;
5647
5648 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5649 return kvm_hv_hypercall(vcpu);
5650
5651 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5652 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5653 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5654 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5655 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5656
5657 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5658
5659 if (!is_long_mode(vcpu)) {
5660 nr &= 0xFFFFFFFF;
5661 a0 &= 0xFFFFFFFF;
5662 a1 &= 0xFFFFFFFF;
5663 a2 &= 0xFFFFFFFF;
5664 a3 &= 0xFFFFFFFF;
5665 }
5666
5667 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5668 ret = -KVM_EPERM;
5669 goto out;
5670 }
5671
5672 switch (nr) {
5673 case KVM_HC_VAPIC_POLL_IRQ:
5674 ret = 0;
5675 break;
5676 case KVM_HC_KICK_CPU:
5677 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5678 ret = 0;
5679 break;
5680 default:
5681 ret = -KVM_ENOSYS;
5682 break;
5683 }
5684 out:
5685 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5686 ++vcpu->stat.hypercalls;
5687 return r;
5688 }
5689 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5690
5691 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5692 {
5693 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5694 char instruction[3];
5695 unsigned long rip = kvm_rip_read(vcpu);
5696
5697 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5698
5699 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5700 }
5701
5702 /*
5703 * Check if userspace requested an interrupt window, and that the
5704 * interrupt window is open.
5705 *
5706 * No need to exit to userspace if we already have an interrupt queued.
5707 */
5708 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5709 {
5710 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5711 vcpu->run->request_interrupt_window &&
5712 kvm_arch_interrupt_allowed(vcpu));
5713 }
5714
5715 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5716 {
5717 struct kvm_run *kvm_run = vcpu->run;
5718
5719 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5720 kvm_run->cr8 = kvm_get_cr8(vcpu);
5721 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5722 if (irqchip_in_kernel(vcpu->kvm))
5723 kvm_run->ready_for_interrupt_injection = 1;
5724 else
5725 kvm_run->ready_for_interrupt_injection =
5726 kvm_arch_interrupt_allowed(vcpu) &&
5727 !kvm_cpu_has_interrupt(vcpu) &&
5728 !kvm_event_needs_reinjection(vcpu);
5729 }
5730
5731 static int vapic_enter(struct kvm_vcpu *vcpu)
5732 {
5733 struct kvm_lapic *apic = vcpu->arch.apic;
5734 struct page *page;
5735
5736 if (!apic || !apic->vapic_addr)
5737 return 0;
5738
5739 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5740 if (is_error_page(page))
5741 return -EFAULT;
5742
5743 vcpu->arch.apic->vapic_page = page;
5744 return 0;
5745 }
5746
5747 static void vapic_exit(struct kvm_vcpu *vcpu)
5748 {
5749 struct kvm_lapic *apic = vcpu->arch.apic;
5750 int idx;
5751
5752 if (!apic || !apic->vapic_addr)
5753 return;
5754
5755 idx = srcu_read_lock(&vcpu->kvm->srcu);
5756 kvm_release_page_dirty(apic->vapic_page);
5757 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5758 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5759 }
5760
5761 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5762 {
5763 int max_irr, tpr;
5764
5765 if (!kvm_x86_ops->update_cr8_intercept)
5766 return;
5767
5768 if (!vcpu->arch.apic)
5769 return;
5770
5771 if (!vcpu->arch.apic->vapic_addr)
5772 max_irr = kvm_lapic_find_highest_irr(vcpu);
5773 else
5774 max_irr = -1;
5775
5776 if (max_irr != -1)
5777 max_irr >>= 4;
5778
5779 tpr = kvm_lapic_get_cr8(vcpu);
5780
5781 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5782 }
5783
5784 static void inject_pending_event(struct kvm_vcpu *vcpu)
5785 {
5786 /* try to reinject previous events if any */
5787 if (vcpu->arch.exception.pending) {
5788 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5789 vcpu->arch.exception.has_error_code,
5790 vcpu->arch.exception.error_code);
5791 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5792 vcpu->arch.exception.has_error_code,
5793 vcpu->arch.exception.error_code,
5794 vcpu->arch.exception.reinject);
5795 return;
5796 }
5797
5798 if (vcpu->arch.nmi_injected) {
5799 kvm_x86_ops->set_nmi(vcpu);
5800 return;
5801 }
5802
5803 if (vcpu->arch.interrupt.pending) {
5804 kvm_x86_ops->set_irq(vcpu);
5805 return;
5806 }
5807
5808 /* try to inject new event if pending */
5809 if (vcpu->arch.nmi_pending) {
5810 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5811 --vcpu->arch.nmi_pending;
5812 vcpu->arch.nmi_injected = true;
5813 kvm_x86_ops->set_nmi(vcpu);
5814 }
5815 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5816 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5817 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5818 false);
5819 kvm_x86_ops->set_irq(vcpu);
5820 }
5821 }
5822 }
5823
5824 static void process_nmi(struct kvm_vcpu *vcpu)
5825 {
5826 unsigned limit = 2;
5827
5828 /*
5829 * x86 is limited to one NMI running, and one NMI pending after it.
5830 * If an NMI is already in progress, limit further NMIs to just one.
5831 * Otherwise, allow two (and we'll inject the first one immediately).
5832 */
5833 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5834 limit = 1;
5835
5836 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5837 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5838 kvm_make_request(KVM_REQ_EVENT, vcpu);
5839 }
5840
5841 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5842 {
5843 u64 eoi_exit_bitmap[4];
5844 u32 tmr[8];
5845
5846 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5847 return;
5848
5849 memset(eoi_exit_bitmap, 0, 32);
5850 memset(tmr, 0, 32);
5851
5852 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5853 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5854 kvm_apic_update_tmr(vcpu, tmr);
5855 }
5856
5857 /*
5858 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5859 * exiting to the userspace. Otherwise, the value will be returned to the
5860 * userspace.
5861 */
5862 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5863 {
5864 int r;
5865 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5866 vcpu->run->request_interrupt_window;
5867 bool req_immediate_exit = false;
5868
5869 if (vcpu->requests) {
5870 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5871 kvm_mmu_unload(vcpu);
5872 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5873 __kvm_migrate_timers(vcpu);
5874 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5875 kvm_gen_update_masterclock(vcpu->kvm);
5876 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5877 kvm_gen_kvmclock_update(vcpu);
5878 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5879 r = kvm_guest_time_update(vcpu);
5880 if (unlikely(r))
5881 goto out;
5882 }
5883 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5884 kvm_mmu_sync_roots(vcpu);
5885 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5886 kvm_x86_ops->tlb_flush(vcpu);
5887 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5888 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5889 r = 0;
5890 goto out;
5891 }
5892 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5893 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5894 r = 0;
5895 goto out;
5896 }
5897 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5898 vcpu->fpu_active = 0;
5899 kvm_x86_ops->fpu_deactivate(vcpu);
5900 }
5901 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5902 /* Page is swapped out. Do synthetic halt */
5903 vcpu->arch.apf.halted = true;
5904 r = 1;
5905 goto out;
5906 }
5907 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5908 record_steal_time(vcpu);
5909 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5910 process_nmi(vcpu);
5911 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5912 kvm_handle_pmu_event(vcpu);
5913 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5914 kvm_deliver_pmi(vcpu);
5915 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5916 vcpu_scan_ioapic(vcpu);
5917 }
5918
5919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5920 kvm_apic_accept_events(vcpu);
5921 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5922 r = 1;
5923 goto out;
5924 }
5925
5926 inject_pending_event(vcpu);
5927
5928 /* enable NMI/IRQ window open exits if needed */
5929 if (vcpu->arch.nmi_pending)
5930 req_immediate_exit =
5931 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5932 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5933 req_immediate_exit =
5934 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5935
5936 if (kvm_lapic_enabled(vcpu)) {
5937 /*
5938 * Update architecture specific hints for APIC
5939 * virtual interrupt delivery.
5940 */
5941 if (kvm_x86_ops->hwapic_irr_update)
5942 kvm_x86_ops->hwapic_irr_update(vcpu,
5943 kvm_lapic_find_highest_irr(vcpu));
5944 update_cr8_intercept(vcpu);
5945 kvm_lapic_sync_to_vapic(vcpu);
5946 }
5947 }
5948
5949 r = kvm_mmu_reload(vcpu);
5950 if (unlikely(r)) {
5951 goto cancel_injection;
5952 }
5953
5954 preempt_disable();
5955
5956 kvm_x86_ops->prepare_guest_switch(vcpu);
5957 if (vcpu->fpu_active)
5958 kvm_load_guest_fpu(vcpu);
5959 kvm_load_guest_xcr0(vcpu);
5960
5961 vcpu->mode = IN_GUEST_MODE;
5962
5963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5964
5965 /* We should set ->mode before check ->requests,
5966 * see the comment in make_all_cpus_request.
5967 */
5968 smp_mb__after_srcu_read_unlock();
5969
5970 local_irq_disable();
5971
5972 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5973 || need_resched() || signal_pending(current)) {
5974 vcpu->mode = OUTSIDE_GUEST_MODE;
5975 smp_wmb();
5976 local_irq_enable();
5977 preempt_enable();
5978 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5979 r = 1;
5980 goto cancel_injection;
5981 }
5982
5983 if (req_immediate_exit)
5984 smp_send_reschedule(vcpu->cpu);
5985
5986 kvm_guest_enter();
5987
5988 if (unlikely(vcpu->arch.switch_db_regs)) {
5989 set_debugreg(0, 7);
5990 set_debugreg(vcpu->arch.eff_db[0], 0);
5991 set_debugreg(vcpu->arch.eff_db[1], 1);
5992 set_debugreg(vcpu->arch.eff_db[2], 2);
5993 set_debugreg(vcpu->arch.eff_db[3], 3);
5994 }
5995
5996 trace_kvm_entry(vcpu->vcpu_id);
5997 kvm_x86_ops->run(vcpu);
5998
5999 /*
6000 * If the guest has used debug registers, at least dr7
6001 * will be disabled while returning to the host.
6002 * If we don't have active breakpoints in the host, we don't
6003 * care about the messed up debug address registers. But if
6004 * we have some of them active, restore the old state.
6005 */
6006 if (hw_breakpoint_active())
6007 hw_breakpoint_restore();
6008
6009 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6010 native_read_tsc());
6011
6012 vcpu->mode = OUTSIDE_GUEST_MODE;
6013 smp_wmb();
6014
6015 /* Interrupt is enabled by handle_external_intr() */
6016 kvm_x86_ops->handle_external_intr(vcpu);
6017
6018 ++vcpu->stat.exits;
6019
6020 /*
6021 * We must have an instruction between local_irq_enable() and
6022 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6023 * the interrupt shadow. The stat.exits increment will do nicely.
6024 * But we need to prevent reordering, hence this barrier():
6025 */
6026 barrier();
6027
6028 kvm_guest_exit();
6029
6030 preempt_enable();
6031
6032 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6033
6034 /*
6035 * Profile KVM exit RIPs:
6036 */
6037 if (unlikely(prof_on == KVM_PROFILING)) {
6038 unsigned long rip = kvm_rip_read(vcpu);
6039 profile_hit(KVM_PROFILING, (void *)rip);
6040 }
6041
6042 if (unlikely(vcpu->arch.tsc_always_catchup))
6043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6044
6045 if (vcpu->arch.apic_attention)
6046 kvm_lapic_sync_from_vapic(vcpu);
6047
6048 r = kvm_x86_ops->handle_exit(vcpu);
6049 return r;
6050
6051 cancel_injection:
6052 kvm_x86_ops->cancel_injection(vcpu);
6053 if (unlikely(vcpu->arch.apic_attention))
6054 kvm_lapic_sync_from_vapic(vcpu);
6055 out:
6056 return r;
6057 }
6058
6059
6060 static int __vcpu_run(struct kvm_vcpu *vcpu)
6061 {
6062 int r;
6063 struct kvm *kvm = vcpu->kvm;
6064
6065 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6066 r = vapic_enter(vcpu);
6067 if (r) {
6068 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6069 return r;
6070 }
6071
6072 r = 1;
6073 while (r > 0) {
6074 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6075 !vcpu->arch.apf.halted)
6076 r = vcpu_enter_guest(vcpu);
6077 else {
6078 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6079 kvm_vcpu_block(vcpu);
6080 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6081 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6082 kvm_apic_accept_events(vcpu);
6083 switch(vcpu->arch.mp_state) {
6084 case KVM_MP_STATE_HALTED:
6085 vcpu->arch.pv.pv_unhalted = false;
6086 vcpu->arch.mp_state =
6087 KVM_MP_STATE_RUNNABLE;
6088 case KVM_MP_STATE_RUNNABLE:
6089 vcpu->arch.apf.halted = false;
6090 break;
6091 case KVM_MP_STATE_INIT_RECEIVED:
6092 break;
6093 default:
6094 r = -EINTR;
6095 break;
6096 }
6097 }
6098 }
6099
6100 if (r <= 0)
6101 break;
6102
6103 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6104 if (kvm_cpu_has_pending_timer(vcpu))
6105 kvm_inject_pending_timer_irqs(vcpu);
6106
6107 if (dm_request_for_irq_injection(vcpu)) {
6108 r = -EINTR;
6109 vcpu->run->exit_reason = KVM_EXIT_INTR;
6110 ++vcpu->stat.request_irq_exits;
6111 }
6112
6113 kvm_check_async_pf_completion(vcpu);
6114
6115 if (signal_pending(current)) {
6116 r = -EINTR;
6117 vcpu->run->exit_reason = KVM_EXIT_INTR;
6118 ++vcpu->stat.signal_exits;
6119 }
6120 if (need_resched()) {
6121 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6122 cond_resched();
6123 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6124 }
6125 }
6126
6127 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6128
6129 vapic_exit(vcpu);
6130
6131 return r;
6132 }
6133
6134 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6135 {
6136 int r;
6137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6138 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6139 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6140 if (r != EMULATE_DONE)
6141 return 0;
6142 return 1;
6143 }
6144
6145 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6146 {
6147 BUG_ON(!vcpu->arch.pio.count);
6148
6149 return complete_emulated_io(vcpu);
6150 }
6151
6152 /*
6153 * Implements the following, as a state machine:
6154 *
6155 * read:
6156 * for each fragment
6157 * for each mmio piece in the fragment
6158 * write gpa, len
6159 * exit
6160 * copy data
6161 * execute insn
6162 *
6163 * write:
6164 * for each fragment
6165 * for each mmio piece in the fragment
6166 * write gpa, len
6167 * copy data
6168 * exit
6169 */
6170 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6171 {
6172 struct kvm_run *run = vcpu->run;
6173 struct kvm_mmio_fragment *frag;
6174 unsigned len;
6175
6176 BUG_ON(!vcpu->mmio_needed);
6177
6178 /* Complete previous fragment */
6179 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6180 len = min(8u, frag->len);
6181 if (!vcpu->mmio_is_write)
6182 memcpy(frag->data, run->mmio.data, len);
6183
6184 if (frag->len <= 8) {
6185 /* Switch to the next fragment. */
6186 frag++;
6187 vcpu->mmio_cur_fragment++;
6188 } else {
6189 /* Go forward to the next mmio piece. */
6190 frag->data += len;
6191 frag->gpa += len;
6192 frag->len -= len;
6193 }
6194
6195 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6196 vcpu->mmio_needed = 0;
6197
6198 /* FIXME: return into emulator if single-stepping. */
6199 if (vcpu->mmio_is_write)
6200 return 1;
6201 vcpu->mmio_read_completed = 1;
6202 return complete_emulated_io(vcpu);
6203 }
6204
6205 run->exit_reason = KVM_EXIT_MMIO;
6206 run->mmio.phys_addr = frag->gpa;
6207 if (vcpu->mmio_is_write)
6208 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6209 run->mmio.len = min(8u, frag->len);
6210 run->mmio.is_write = vcpu->mmio_is_write;
6211 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6212 return 0;
6213 }
6214
6215
6216 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6217 {
6218 int r;
6219 sigset_t sigsaved;
6220
6221 if (!tsk_used_math(current) && init_fpu(current))
6222 return -ENOMEM;
6223
6224 if (vcpu->sigset_active)
6225 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6226
6227 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6228 kvm_vcpu_block(vcpu);
6229 kvm_apic_accept_events(vcpu);
6230 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6231 r = -EAGAIN;
6232 goto out;
6233 }
6234
6235 /* re-sync apic's tpr */
6236 if (!irqchip_in_kernel(vcpu->kvm)) {
6237 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6238 r = -EINVAL;
6239 goto out;
6240 }
6241 }
6242
6243 if (unlikely(vcpu->arch.complete_userspace_io)) {
6244 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6245 vcpu->arch.complete_userspace_io = NULL;
6246 r = cui(vcpu);
6247 if (r <= 0)
6248 goto out;
6249 } else
6250 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6251
6252 r = __vcpu_run(vcpu);
6253
6254 out:
6255 post_kvm_run_save(vcpu);
6256 if (vcpu->sigset_active)
6257 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6258
6259 return r;
6260 }
6261
6262 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6263 {
6264 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6265 /*
6266 * We are here if userspace calls get_regs() in the middle of
6267 * instruction emulation. Registers state needs to be copied
6268 * back from emulation context to vcpu. Userspace shouldn't do
6269 * that usually, but some bad designed PV devices (vmware
6270 * backdoor interface) need this to work
6271 */
6272 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6273 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6274 }
6275 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6276 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6277 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6278 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6279 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6280 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6281 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6282 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6283 #ifdef CONFIG_X86_64
6284 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6285 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6286 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6287 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6288 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6289 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6290 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6291 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6292 #endif
6293
6294 regs->rip = kvm_rip_read(vcpu);
6295 regs->rflags = kvm_get_rflags(vcpu);
6296
6297 return 0;
6298 }
6299
6300 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6301 {
6302 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6303 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6304
6305 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6306 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6307 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6308 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6309 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6310 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6311 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6312 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6313 #ifdef CONFIG_X86_64
6314 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6315 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6316 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6317 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6318 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6319 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6320 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6321 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6322 #endif
6323
6324 kvm_rip_write(vcpu, regs->rip);
6325 kvm_set_rflags(vcpu, regs->rflags);
6326
6327 vcpu->arch.exception.pending = false;
6328
6329 kvm_make_request(KVM_REQ_EVENT, vcpu);
6330
6331 return 0;
6332 }
6333
6334 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6335 {
6336 struct kvm_segment cs;
6337
6338 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6339 *db = cs.db;
6340 *l = cs.l;
6341 }
6342 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6343
6344 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6345 struct kvm_sregs *sregs)
6346 {
6347 struct desc_ptr dt;
6348
6349 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6350 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6351 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6352 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6353 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6354 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6355
6356 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6357 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6358
6359 kvm_x86_ops->get_idt(vcpu, &dt);
6360 sregs->idt.limit = dt.size;
6361 sregs->idt.base = dt.address;
6362 kvm_x86_ops->get_gdt(vcpu, &dt);
6363 sregs->gdt.limit = dt.size;
6364 sregs->gdt.base = dt.address;
6365
6366 sregs->cr0 = kvm_read_cr0(vcpu);
6367 sregs->cr2 = vcpu->arch.cr2;
6368 sregs->cr3 = kvm_read_cr3(vcpu);
6369 sregs->cr4 = kvm_read_cr4(vcpu);
6370 sregs->cr8 = kvm_get_cr8(vcpu);
6371 sregs->efer = vcpu->arch.efer;
6372 sregs->apic_base = kvm_get_apic_base(vcpu);
6373
6374 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6375
6376 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6377 set_bit(vcpu->arch.interrupt.nr,
6378 (unsigned long *)sregs->interrupt_bitmap);
6379
6380 return 0;
6381 }
6382
6383 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6384 struct kvm_mp_state *mp_state)
6385 {
6386 kvm_apic_accept_events(vcpu);
6387 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6388 vcpu->arch.pv.pv_unhalted)
6389 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6390 else
6391 mp_state->mp_state = vcpu->arch.mp_state;
6392
6393 return 0;
6394 }
6395
6396 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6397 struct kvm_mp_state *mp_state)
6398 {
6399 if (!kvm_vcpu_has_lapic(vcpu) &&
6400 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6401 return -EINVAL;
6402
6403 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6404 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6405 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6406 } else
6407 vcpu->arch.mp_state = mp_state->mp_state;
6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
6409 return 0;
6410 }
6411
6412 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6413 int reason, bool has_error_code, u32 error_code)
6414 {
6415 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6416 int ret;
6417
6418 init_emulate_ctxt(vcpu);
6419
6420 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6421 has_error_code, error_code);
6422
6423 if (ret)
6424 return EMULATE_FAIL;
6425
6426 kvm_rip_write(vcpu, ctxt->eip);
6427 kvm_set_rflags(vcpu, ctxt->eflags);
6428 kvm_make_request(KVM_REQ_EVENT, vcpu);
6429 return EMULATE_DONE;
6430 }
6431 EXPORT_SYMBOL_GPL(kvm_task_switch);
6432
6433 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6434 struct kvm_sregs *sregs)
6435 {
6436 int mmu_reset_needed = 0;
6437 int pending_vec, max_bits, idx;
6438 struct desc_ptr dt;
6439
6440 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6441 return -EINVAL;
6442
6443 dt.size = sregs->idt.limit;
6444 dt.address = sregs->idt.base;
6445 kvm_x86_ops->set_idt(vcpu, &dt);
6446 dt.size = sregs->gdt.limit;
6447 dt.address = sregs->gdt.base;
6448 kvm_x86_ops->set_gdt(vcpu, &dt);
6449
6450 vcpu->arch.cr2 = sregs->cr2;
6451 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6452 vcpu->arch.cr3 = sregs->cr3;
6453 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6454
6455 kvm_set_cr8(vcpu, sregs->cr8);
6456
6457 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6458 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6459 kvm_set_apic_base(vcpu, sregs->apic_base);
6460
6461 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6462 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6463 vcpu->arch.cr0 = sregs->cr0;
6464
6465 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6466 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6467 if (sregs->cr4 & X86_CR4_OSXSAVE)
6468 kvm_update_cpuid(vcpu);
6469
6470 idx = srcu_read_lock(&vcpu->kvm->srcu);
6471 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6472 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6473 mmu_reset_needed = 1;
6474 }
6475 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6476
6477 if (mmu_reset_needed)
6478 kvm_mmu_reset_context(vcpu);
6479
6480 max_bits = KVM_NR_INTERRUPTS;
6481 pending_vec = find_first_bit(
6482 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6483 if (pending_vec < max_bits) {
6484 kvm_queue_interrupt(vcpu, pending_vec, false);
6485 pr_debug("Set back pending irq %d\n", pending_vec);
6486 }
6487
6488 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6489 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6490 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6491 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6492 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6493 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6494
6495 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6496 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6497
6498 update_cr8_intercept(vcpu);
6499
6500 /* Older userspace won't unhalt the vcpu on reset. */
6501 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6502 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6503 !is_protmode(vcpu))
6504 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6505
6506 kvm_make_request(KVM_REQ_EVENT, vcpu);
6507
6508 return 0;
6509 }
6510
6511 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6512 struct kvm_guest_debug *dbg)
6513 {
6514 unsigned long rflags;
6515 int i, r;
6516
6517 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6518 r = -EBUSY;
6519 if (vcpu->arch.exception.pending)
6520 goto out;
6521 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6522 kvm_queue_exception(vcpu, DB_VECTOR);
6523 else
6524 kvm_queue_exception(vcpu, BP_VECTOR);
6525 }
6526
6527 /*
6528 * Read rflags as long as potentially injected trace flags are still
6529 * filtered out.
6530 */
6531 rflags = kvm_get_rflags(vcpu);
6532
6533 vcpu->guest_debug = dbg->control;
6534 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6535 vcpu->guest_debug = 0;
6536
6537 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6538 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6539 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6540 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6541 } else {
6542 for (i = 0; i < KVM_NR_DB_REGS; i++)
6543 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6544 }
6545 kvm_update_dr7(vcpu);
6546
6547 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6548 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6549 get_segment_base(vcpu, VCPU_SREG_CS);
6550
6551 /*
6552 * Trigger an rflags update that will inject or remove the trace
6553 * flags.
6554 */
6555 kvm_set_rflags(vcpu, rflags);
6556
6557 kvm_x86_ops->update_db_bp_intercept(vcpu);
6558
6559 r = 0;
6560
6561 out:
6562
6563 return r;
6564 }
6565
6566 /*
6567 * Translate a guest virtual address to a guest physical address.
6568 */
6569 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6570 struct kvm_translation *tr)
6571 {
6572 unsigned long vaddr = tr->linear_address;
6573 gpa_t gpa;
6574 int idx;
6575
6576 idx = srcu_read_lock(&vcpu->kvm->srcu);
6577 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6578 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6579 tr->physical_address = gpa;
6580 tr->valid = gpa != UNMAPPED_GVA;
6581 tr->writeable = 1;
6582 tr->usermode = 0;
6583
6584 return 0;
6585 }
6586
6587 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6588 {
6589 struct i387_fxsave_struct *fxsave =
6590 &vcpu->arch.guest_fpu.state->fxsave;
6591
6592 memcpy(fpu->fpr, fxsave->st_space, 128);
6593 fpu->fcw = fxsave->cwd;
6594 fpu->fsw = fxsave->swd;
6595 fpu->ftwx = fxsave->twd;
6596 fpu->last_opcode = fxsave->fop;
6597 fpu->last_ip = fxsave->rip;
6598 fpu->last_dp = fxsave->rdp;
6599 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6600
6601 return 0;
6602 }
6603
6604 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6605 {
6606 struct i387_fxsave_struct *fxsave =
6607 &vcpu->arch.guest_fpu.state->fxsave;
6608
6609 memcpy(fxsave->st_space, fpu->fpr, 128);
6610 fxsave->cwd = fpu->fcw;
6611 fxsave->swd = fpu->fsw;
6612 fxsave->twd = fpu->ftwx;
6613 fxsave->fop = fpu->last_opcode;
6614 fxsave->rip = fpu->last_ip;
6615 fxsave->rdp = fpu->last_dp;
6616 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6617
6618 return 0;
6619 }
6620
6621 int fx_init(struct kvm_vcpu *vcpu)
6622 {
6623 int err;
6624
6625 err = fpu_alloc(&vcpu->arch.guest_fpu);
6626 if (err)
6627 return err;
6628
6629 fpu_finit(&vcpu->arch.guest_fpu);
6630
6631 /*
6632 * Ensure guest xcr0 is valid for loading
6633 */
6634 vcpu->arch.xcr0 = XSTATE_FP;
6635
6636 vcpu->arch.cr0 |= X86_CR0_ET;
6637
6638 return 0;
6639 }
6640 EXPORT_SYMBOL_GPL(fx_init);
6641
6642 static void fx_free(struct kvm_vcpu *vcpu)
6643 {
6644 fpu_free(&vcpu->arch.guest_fpu);
6645 }
6646
6647 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6648 {
6649 if (vcpu->guest_fpu_loaded)
6650 return;
6651
6652 /*
6653 * Restore all possible states in the guest,
6654 * and assume host would use all available bits.
6655 * Guest xcr0 would be loaded later.
6656 */
6657 kvm_put_guest_xcr0(vcpu);
6658 vcpu->guest_fpu_loaded = 1;
6659 __kernel_fpu_begin();
6660 fpu_restore_checking(&vcpu->arch.guest_fpu);
6661 trace_kvm_fpu(1);
6662 }
6663
6664 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6665 {
6666 kvm_put_guest_xcr0(vcpu);
6667
6668 if (!vcpu->guest_fpu_loaded)
6669 return;
6670
6671 vcpu->guest_fpu_loaded = 0;
6672 fpu_save_init(&vcpu->arch.guest_fpu);
6673 __kernel_fpu_end();
6674 ++vcpu->stat.fpu_reload;
6675 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6676 trace_kvm_fpu(0);
6677 }
6678
6679 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6680 {
6681 kvmclock_reset(vcpu);
6682
6683 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6684 fx_free(vcpu);
6685 kvm_x86_ops->vcpu_free(vcpu);
6686 }
6687
6688 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6689 unsigned int id)
6690 {
6691 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6692 printk_once(KERN_WARNING
6693 "kvm: SMP vm created on host with unstable TSC; "
6694 "guest TSC will not be reliable\n");
6695 return kvm_x86_ops->vcpu_create(kvm, id);
6696 }
6697
6698 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6699 {
6700 int r;
6701
6702 vcpu->arch.mtrr_state.have_fixed = 1;
6703 r = vcpu_load(vcpu);
6704 if (r)
6705 return r;
6706 kvm_vcpu_reset(vcpu);
6707 kvm_mmu_setup(vcpu);
6708 vcpu_put(vcpu);
6709
6710 return r;
6711 }
6712
6713 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6714 {
6715 int r;
6716 struct msr_data msr;
6717
6718 r = vcpu_load(vcpu);
6719 if (r)
6720 return r;
6721 msr.data = 0x0;
6722 msr.index = MSR_IA32_TSC;
6723 msr.host_initiated = true;
6724 kvm_write_tsc(vcpu, &msr);
6725 vcpu_put(vcpu);
6726
6727 return r;
6728 }
6729
6730 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6731 {
6732 int r;
6733 vcpu->arch.apf.msr_val = 0;
6734
6735 r = vcpu_load(vcpu);
6736 BUG_ON(r);
6737 kvm_mmu_unload(vcpu);
6738 vcpu_put(vcpu);
6739
6740 fx_free(vcpu);
6741 kvm_x86_ops->vcpu_free(vcpu);
6742 }
6743
6744 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6745 {
6746 atomic_set(&vcpu->arch.nmi_queued, 0);
6747 vcpu->arch.nmi_pending = 0;
6748 vcpu->arch.nmi_injected = false;
6749
6750 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6751 vcpu->arch.dr6 = DR6_FIXED_1;
6752 vcpu->arch.dr7 = DR7_FIXED_1;
6753 kvm_update_dr7(vcpu);
6754
6755 kvm_make_request(KVM_REQ_EVENT, vcpu);
6756 vcpu->arch.apf.msr_val = 0;
6757 vcpu->arch.st.msr_val = 0;
6758
6759 kvmclock_reset(vcpu);
6760
6761 kvm_clear_async_pf_completion_queue(vcpu);
6762 kvm_async_pf_hash_reset(vcpu);
6763 vcpu->arch.apf.halted = false;
6764
6765 kvm_pmu_reset(vcpu);
6766
6767 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6768 vcpu->arch.regs_avail = ~0;
6769 vcpu->arch.regs_dirty = ~0;
6770
6771 kvm_x86_ops->vcpu_reset(vcpu);
6772 }
6773
6774 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6775 {
6776 struct kvm_segment cs;
6777
6778 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6779 cs.selector = vector << 8;
6780 cs.base = vector << 12;
6781 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6782 kvm_rip_write(vcpu, 0);
6783 }
6784
6785 int kvm_arch_hardware_enable(void *garbage)
6786 {
6787 struct kvm *kvm;
6788 struct kvm_vcpu *vcpu;
6789 int i;
6790 int ret;
6791 u64 local_tsc;
6792 u64 max_tsc = 0;
6793 bool stable, backwards_tsc = false;
6794
6795 kvm_shared_msr_cpu_online();
6796 ret = kvm_x86_ops->hardware_enable(garbage);
6797 if (ret != 0)
6798 return ret;
6799
6800 local_tsc = native_read_tsc();
6801 stable = !check_tsc_unstable();
6802 list_for_each_entry(kvm, &vm_list, vm_list) {
6803 kvm_for_each_vcpu(i, vcpu, kvm) {
6804 if (!stable && vcpu->cpu == smp_processor_id())
6805 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6806 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6807 backwards_tsc = true;
6808 if (vcpu->arch.last_host_tsc > max_tsc)
6809 max_tsc = vcpu->arch.last_host_tsc;
6810 }
6811 }
6812 }
6813
6814 /*
6815 * Sometimes, even reliable TSCs go backwards. This happens on
6816 * platforms that reset TSC during suspend or hibernate actions, but
6817 * maintain synchronization. We must compensate. Fortunately, we can
6818 * detect that condition here, which happens early in CPU bringup,
6819 * before any KVM threads can be running. Unfortunately, we can't
6820 * bring the TSCs fully up to date with real time, as we aren't yet far
6821 * enough into CPU bringup that we know how much real time has actually
6822 * elapsed; our helper function, get_kernel_ns() will be using boot
6823 * variables that haven't been updated yet.
6824 *
6825 * So we simply find the maximum observed TSC above, then record the
6826 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6827 * the adjustment will be applied. Note that we accumulate
6828 * adjustments, in case multiple suspend cycles happen before some VCPU
6829 * gets a chance to run again. In the event that no KVM threads get a
6830 * chance to run, we will miss the entire elapsed period, as we'll have
6831 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6832 * loose cycle time. This isn't too big a deal, since the loss will be
6833 * uniform across all VCPUs (not to mention the scenario is extremely
6834 * unlikely). It is possible that a second hibernate recovery happens
6835 * much faster than a first, causing the observed TSC here to be
6836 * smaller; this would require additional padding adjustment, which is
6837 * why we set last_host_tsc to the local tsc observed here.
6838 *
6839 * N.B. - this code below runs only on platforms with reliable TSC,
6840 * as that is the only way backwards_tsc is set above. Also note
6841 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6842 * have the same delta_cyc adjustment applied if backwards_tsc
6843 * is detected. Note further, this adjustment is only done once,
6844 * as we reset last_host_tsc on all VCPUs to stop this from being
6845 * called multiple times (one for each physical CPU bringup).
6846 *
6847 * Platforms with unreliable TSCs don't have to deal with this, they
6848 * will be compensated by the logic in vcpu_load, which sets the TSC to
6849 * catchup mode. This will catchup all VCPUs to real time, but cannot
6850 * guarantee that they stay in perfect synchronization.
6851 */
6852 if (backwards_tsc) {
6853 u64 delta_cyc = max_tsc - local_tsc;
6854 list_for_each_entry(kvm, &vm_list, vm_list) {
6855 kvm_for_each_vcpu(i, vcpu, kvm) {
6856 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6857 vcpu->arch.last_host_tsc = local_tsc;
6858 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6859 &vcpu->requests);
6860 }
6861
6862 /*
6863 * We have to disable TSC offset matching.. if you were
6864 * booting a VM while issuing an S4 host suspend....
6865 * you may have some problem. Solving this issue is
6866 * left as an exercise to the reader.
6867 */
6868 kvm->arch.last_tsc_nsec = 0;
6869 kvm->arch.last_tsc_write = 0;
6870 }
6871
6872 }
6873 return 0;
6874 }
6875
6876 void kvm_arch_hardware_disable(void *garbage)
6877 {
6878 kvm_x86_ops->hardware_disable(garbage);
6879 drop_user_return_notifiers(garbage);
6880 }
6881
6882 int kvm_arch_hardware_setup(void)
6883 {
6884 return kvm_x86_ops->hardware_setup();
6885 }
6886
6887 void kvm_arch_hardware_unsetup(void)
6888 {
6889 kvm_x86_ops->hardware_unsetup();
6890 }
6891
6892 void kvm_arch_check_processor_compat(void *rtn)
6893 {
6894 kvm_x86_ops->check_processor_compatibility(rtn);
6895 }
6896
6897 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6898 {
6899 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6900 }
6901
6902 struct static_key kvm_no_apic_vcpu __read_mostly;
6903
6904 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6905 {
6906 struct page *page;
6907 struct kvm *kvm;
6908 int r;
6909
6910 BUG_ON(vcpu->kvm == NULL);
6911 kvm = vcpu->kvm;
6912
6913 vcpu->arch.pv.pv_unhalted = false;
6914 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6915 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6916 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6917 else
6918 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6919
6920 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6921 if (!page) {
6922 r = -ENOMEM;
6923 goto fail;
6924 }
6925 vcpu->arch.pio_data = page_address(page);
6926
6927 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6928
6929 r = kvm_mmu_create(vcpu);
6930 if (r < 0)
6931 goto fail_free_pio_data;
6932
6933 if (irqchip_in_kernel(kvm)) {
6934 r = kvm_create_lapic(vcpu);
6935 if (r < 0)
6936 goto fail_mmu_destroy;
6937 } else
6938 static_key_slow_inc(&kvm_no_apic_vcpu);
6939
6940 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6941 GFP_KERNEL);
6942 if (!vcpu->arch.mce_banks) {
6943 r = -ENOMEM;
6944 goto fail_free_lapic;
6945 }
6946 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6947
6948 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6949 r = -ENOMEM;
6950 goto fail_free_mce_banks;
6951 }
6952
6953 r = fx_init(vcpu);
6954 if (r)
6955 goto fail_free_wbinvd_dirty_mask;
6956
6957 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6958 vcpu->arch.pv_time_enabled = false;
6959
6960 vcpu->arch.guest_supported_xcr0 = 0;
6961 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
6962
6963 kvm_async_pf_hash_reset(vcpu);
6964 kvm_pmu_init(vcpu);
6965
6966 return 0;
6967 fail_free_wbinvd_dirty_mask:
6968 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6969 fail_free_mce_banks:
6970 kfree(vcpu->arch.mce_banks);
6971 fail_free_lapic:
6972 kvm_free_lapic(vcpu);
6973 fail_mmu_destroy:
6974 kvm_mmu_destroy(vcpu);
6975 fail_free_pio_data:
6976 free_page((unsigned long)vcpu->arch.pio_data);
6977 fail:
6978 return r;
6979 }
6980
6981 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6982 {
6983 int idx;
6984
6985 kvm_pmu_destroy(vcpu);
6986 kfree(vcpu->arch.mce_banks);
6987 kvm_free_lapic(vcpu);
6988 idx = srcu_read_lock(&vcpu->kvm->srcu);
6989 kvm_mmu_destroy(vcpu);
6990 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6991 free_page((unsigned long)vcpu->arch.pio_data);
6992 if (!irqchip_in_kernel(vcpu->kvm))
6993 static_key_slow_dec(&kvm_no_apic_vcpu);
6994 }
6995
6996 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6997 {
6998 if (type)
6999 return -EINVAL;
7000
7001 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7002 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7003 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7004 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7005
7006 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7007 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7008 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7009 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7010 &kvm->arch.irq_sources_bitmap);
7011
7012 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7013 mutex_init(&kvm->arch.apic_map_lock);
7014 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7015
7016 pvclock_update_vm_gtod_copy(kvm);
7017
7018 return 0;
7019 }
7020
7021 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7022 {
7023 int r;
7024 r = vcpu_load(vcpu);
7025 BUG_ON(r);
7026 kvm_mmu_unload(vcpu);
7027 vcpu_put(vcpu);
7028 }
7029
7030 static void kvm_free_vcpus(struct kvm *kvm)
7031 {
7032 unsigned int i;
7033 struct kvm_vcpu *vcpu;
7034
7035 /*
7036 * Unpin any mmu pages first.
7037 */
7038 kvm_for_each_vcpu(i, vcpu, kvm) {
7039 kvm_clear_async_pf_completion_queue(vcpu);
7040 kvm_unload_vcpu_mmu(vcpu);
7041 }
7042 kvm_for_each_vcpu(i, vcpu, kvm)
7043 kvm_arch_vcpu_free(vcpu);
7044
7045 mutex_lock(&kvm->lock);
7046 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7047 kvm->vcpus[i] = NULL;
7048
7049 atomic_set(&kvm->online_vcpus, 0);
7050 mutex_unlock(&kvm->lock);
7051 }
7052
7053 void kvm_arch_sync_events(struct kvm *kvm)
7054 {
7055 kvm_free_all_assigned_devices(kvm);
7056 kvm_free_pit(kvm);
7057 }
7058
7059 void kvm_arch_destroy_vm(struct kvm *kvm)
7060 {
7061 if (current->mm == kvm->mm) {
7062 /*
7063 * Free memory regions allocated on behalf of userspace,
7064 * unless the the memory map has changed due to process exit
7065 * or fd copying.
7066 */
7067 struct kvm_userspace_memory_region mem;
7068 memset(&mem, 0, sizeof(mem));
7069 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071
7072 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7073 kvm_set_memory_region(kvm, &mem);
7074
7075 mem.slot = TSS_PRIVATE_MEMSLOT;
7076 kvm_set_memory_region(kvm, &mem);
7077 }
7078 kvm_iommu_unmap_guest(kvm);
7079 kfree(kvm->arch.vpic);
7080 kfree(kvm->arch.vioapic);
7081 kvm_free_vcpus(kvm);
7082 if (kvm->arch.apic_access_page)
7083 put_page(kvm->arch.apic_access_page);
7084 if (kvm->arch.ept_identity_pagetable)
7085 put_page(kvm->arch.ept_identity_pagetable);
7086 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7087 }
7088
7089 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7090 struct kvm_memory_slot *dont)
7091 {
7092 int i;
7093
7094 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7095 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7096 kvm_kvfree(free->arch.rmap[i]);
7097 free->arch.rmap[i] = NULL;
7098 }
7099 if (i == 0)
7100 continue;
7101
7102 if (!dont || free->arch.lpage_info[i - 1] !=
7103 dont->arch.lpage_info[i - 1]) {
7104 kvm_kvfree(free->arch.lpage_info[i - 1]);
7105 free->arch.lpage_info[i - 1] = NULL;
7106 }
7107 }
7108 }
7109
7110 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7111 unsigned long npages)
7112 {
7113 int i;
7114
7115 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7116 unsigned long ugfn;
7117 int lpages;
7118 int level = i + 1;
7119
7120 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7121 slot->base_gfn, level) + 1;
7122
7123 slot->arch.rmap[i] =
7124 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7125 if (!slot->arch.rmap[i])
7126 goto out_free;
7127 if (i == 0)
7128 continue;
7129
7130 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7131 sizeof(*slot->arch.lpage_info[i - 1]));
7132 if (!slot->arch.lpage_info[i - 1])
7133 goto out_free;
7134
7135 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7136 slot->arch.lpage_info[i - 1][0].write_count = 1;
7137 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7138 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7139 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7140 /*
7141 * If the gfn and userspace address are not aligned wrt each
7142 * other, or if explicitly asked to, disable large page
7143 * support for this slot
7144 */
7145 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7146 !kvm_largepages_enabled()) {
7147 unsigned long j;
7148
7149 for (j = 0; j < lpages; ++j)
7150 slot->arch.lpage_info[i - 1][j].write_count = 1;
7151 }
7152 }
7153
7154 return 0;
7155
7156 out_free:
7157 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7158 kvm_kvfree(slot->arch.rmap[i]);
7159 slot->arch.rmap[i] = NULL;
7160 if (i == 0)
7161 continue;
7162
7163 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7164 slot->arch.lpage_info[i - 1] = NULL;
7165 }
7166 return -ENOMEM;
7167 }
7168
7169 void kvm_arch_memslots_updated(struct kvm *kvm)
7170 {
7171 /*
7172 * memslots->generation has been incremented.
7173 * mmio generation may have reached its maximum value.
7174 */
7175 kvm_mmu_invalidate_mmio_sptes(kvm);
7176 }
7177
7178 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7179 struct kvm_memory_slot *memslot,
7180 struct kvm_userspace_memory_region *mem,
7181 enum kvm_mr_change change)
7182 {
7183 /*
7184 * Only private memory slots need to be mapped here since
7185 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7186 */
7187 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7188 unsigned long userspace_addr;
7189
7190 /*
7191 * MAP_SHARED to prevent internal slot pages from being moved
7192 * by fork()/COW.
7193 */
7194 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7195 PROT_READ | PROT_WRITE,
7196 MAP_SHARED | MAP_ANONYMOUS, 0);
7197
7198 if (IS_ERR((void *)userspace_addr))
7199 return PTR_ERR((void *)userspace_addr);
7200
7201 memslot->userspace_addr = userspace_addr;
7202 }
7203
7204 return 0;
7205 }
7206
7207 void kvm_arch_commit_memory_region(struct kvm *kvm,
7208 struct kvm_userspace_memory_region *mem,
7209 const struct kvm_memory_slot *old,
7210 enum kvm_mr_change change)
7211 {
7212
7213 int nr_mmu_pages = 0;
7214
7215 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7216 int ret;
7217
7218 ret = vm_munmap(old->userspace_addr,
7219 old->npages * PAGE_SIZE);
7220 if (ret < 0)
7221 printk(KERN_WARNING
7222 "kvm_vm_ioctl_set_memory_region: "
7223 "failed to munmap memory\n");
7224 }
7225
7226 if (!kvm->arch.n_requested_mmu_pages)
7227 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7228
7229 if (nr_mmu_pages)
7230 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7231 /*
7232 * Write protect all pages for dirty logging.
7233 * Existing largepage mappings are destroyed here and new ones will
7234 * not be created until the end of the logging.
7235 */
7236 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7237 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7238 }
7239
7240 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7241 {
7242 kvm_mmu_invalidate_zap_all_pages(kvm);
7243 }
7244
7245 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7246 struct kvm_memory_slot *slot)
7247 {
7248 kvm_mmu_invalidate_zap_all_pages(kvm);
7249 }
7250
7251 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7252 {
7253 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7254 !vcpu->arch.apf.halted)
7255 || !list_empty_careful(&vcpu->async_pf.done)
7256 || kvm_apic_has_events(vcpu)
7257 || vcpu->arch.pv.pv_unhalted
7258 || atomic_read(&vcpu->arch.nmi_queued) ||
7259 (kvm_arch_interrupt_allowed(vcpu) &&
7260 kvm_cpu_has_interrupt(vcpu));
7261 }
7262
7263 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7264 {
7265 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7266 }
7267
7268 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7269 {
7270 return kvm_x86_ops->interrupt_allowed(vcpu);
7271 }
7272
7273 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7274 {
7275 unsigned long current_rip = kvm_rip_read(vcpu) +
7276 get_segment_base(vcpu, VCPU_SREG_CS);
7277
7278 return current_rip == linear_rip;
7279 }
7280 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7281
7282 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7283 {
7284 unsigned long rflags;
7285
7286 rflags = kvm_x86_ops->get_rflags(vcpu);
7287 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7288 rflags &= ~X86_EFLAGS_TF;
7289 return rflags;
7290 }
7291 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7292
7293 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7294 {
7295 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7296 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7297 rflags |= X86_EFLAGS_TF;
7298 kvm_x86_ops->set_rflags(vcpu, rflags);
7299 kvm_make_request(KVM_REQ_EVENT, vcpu);
7300 }
7301 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7302
7303 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7304 {
7305 int r;
7306
7307 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7308 work->wakeup_all)
7309 return;
7310
7311 r = kvm_mmu_reload(vcpu);
7312 if (unlikely(r))
7313 return;
7314
7315 if (!vcpu->arch.mmu.direct_map &&
7316 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7317 return;
7318
7319 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7320 }
7321
7322 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7323 {
7324 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7325 }
7326
7327 static inline u32 kvm_async_pf_next_probe(u32 key)
7328 {
7329 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7330 }
7331
7332 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7333 {
7334 u32 key = kvm_async_pf_hash_fn(gfn);
7335
7336 while (vcpu->arch.apf.gfns[key] != ~0)
7337 key = kvm_async_pf_next_probe(key);
7338
7339 vcpu->arch.apf.gfns[key] = gfn;
7340 }
7341
7342 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7343 {
7344 int i;
7345 u32 key = kvm_async_pf_hash_fn(gfn);
7346
7347 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7348 (vcpu->arch.apf.gfns[key] != gfn &&
7349 vcpu->arch.apf.gfns[key] != ~0); i++)
7350 key = kvm_async_pf_next_probe(key);
7351
7352 return key;
7353 }
7354
7355 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7356 {
7357 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7358 }
7359
7360 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7361 {
7362 u32 i, j, k;
7363
7364 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7365 while (true) {
7366 vcpu->arch.apf.gfns[i] = ~0;
7367 do {
7368 j = kvm_async_pf_next_probe(j);
7369 if (vcpu->arch.apf.gfns[j] == ~0)
7370 return;
7371 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7372 /*
7373 * k lies cyclically in ]i,j]
7374 * | i.k.j |
7375 * |....j i.k.| or |.k..j i...|
7376 */
7377 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7378 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7379 i = j;
7380 }
7381 }
7382
7383 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7384 {
7385
7386 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7387 sizeof(val));
7388 }
7389
7390 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7391 struct kvm_async_pf *work)
7392 {
7393 struct x86_exception fault;
7394
7395 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7396 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7397
7398 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7399 (vcpu->arch.apf.send_user_only &&
7400 kvm_x86_ops->get_cpl(vcpu) == 0))
7401 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7402 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7403 fault.vector = PF_VECTOR;
7404 fault.error_code_valid = true;
7405 fault.error_code = 0;
7406 fault.nested_page_fault = false;
7407 fault.address = work->arch.token;
7408 kvm_inject_page_fault(vcpu, &fault);
7409 }
7410 }
7411
7412 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7413 struct kvm_async_pf *work)
7414 {
7415 struct x86_exception fault;
7416
7417 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7418 if (work->wakeup_all)
7419 work->arch.token = ~0; /* broadcast wakeup */
7420 else
7421 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7422
7423 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7424 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7425 fault.vector = PF_VECTOR;
7426 fault.error_code_valid = true;
7427 fault.error_code = 0;
7428 fault.nested_page_fault = false;
7429 fault.address = work->arch.token;
7430 kvm_inject_page_fault(vcpu, &fault);
7431 }
7432 vcpu->arch.apf.halted = false;
7433 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7434 }
7435
7436 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7437 {
7438 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7439 return true;
7440 else
7441 return !kvm_event_needs_reinjection(vcpu) &&
7442 kvm_x86_ops->interrupt_allowed(vcpu);
7443 }
7444
7445 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7446 {
7447 atomic_inc(&kvm->arch.noncoherent_dma_count);
7448 }
7449 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7450
7451 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7452 {
7453 atomic_dec(&kvm->arch.noncoherent_dma_count);
7454 }
7455 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7456
7457 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7458 {
7459 return atomic_read(&kvm->arch.noncoherent_dma_count);
7460 }
7461 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7462
7463 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7464 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7465 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7466 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7467 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7468 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7469 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7470 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7471 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7472 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7473 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7474 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7475 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
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