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KVM: ignore reads from AMDs C1E enabled MSR
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include <linux/kvm_host.h>
22 #include "irq.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "x86.h"
28
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
32 #include <linux/fs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #define CREATE_TRACE_POINTS
41 #include "trace.h"
42
43 #include <asm/uaccess.h>
44 #include <asm/msr.h>
45 #include <asm/desc.h>
46 #include <asm/mtrr.h>
47 #include <asm/mce.h>
48
49 #define MAX_IO_MSRS 256
50 #define CR0_RESERVED_BITS \
51 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
52 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
53 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
54 #define CR4_RESERVED_BITS \
55 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
56 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
57 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
58 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
59
60 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
61
62 #define KVM_MAX_MCE_BANKS 32
63 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
64
65 /* EFER defaults:
66 * - enable syscall per default because its emulated by KVM
67 * - enable LME and LMA per default on 64 bit KVM
68 */
69 #ifdef CONFIG_X86_64
70 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
71 #else
72 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
73 #endif
74
75 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
76 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
77
78 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
79 struct kvm_cpuid_entry2 __user *entries);
80 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
81 u32 function, u32 index);
82
83 struct kvm_x86_ops *kvm_x86_ops;
84 EXPORT_SYMBOL_GPL(kvm_x86_ops);
85
86 struct kvm_stats_debugfs_item debugfs_entries[] = {
87 { "pf_fixed", VCPU_STAT(pf_fixed) },
88 { "pf_guest", VCPU_STAT(pf_guest) },
89 { "tlb_flush", VCPU_STAT(tlb_flush) },
90 { "invlpg", VCPU_STAT(invlpg) },
91 { "exits", VCPU_STAT(exits) },
92 { "io_exits", VCPU_STAT(io_exits) },
93 { "mmio_exits", VCPU_STAT(mmio_exits) },
94 { "signal_exits", VCPU_STAT(signal_exits) },
95 { "irq_window", VCPU_STAT(irq_window_exits) },
96 { "nmi_window", VCPU_STAT(nmi_window_exits) },
97 { "halt_exits", VCPU_STAT(halt_exits) },
98 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
99 { "hypercalls", VCPU_STAT(hypercalls) },
100 { "request_irq", VCPU_STAT(request_irq_exits) },
101 { "irq_exits", VCPU_STAT(irq_exits) },
102 { "host_state_reload", VCPU_STAT(host_state_reload) },
103 { "efer_reload", VCPU_STAT(efer_reload) },
104 { "fpu_reload", VCPU_STAT(fpu_reload) },
105 { "insn_emulation", VCPU_STAT(insn_emulation) },
106 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
107 { "irq_injections", VCPU_STAT(irq_injections) },
108 { "nmi_injections", VCPU_STAT(nmi_injections) },
109 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
110 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
111 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
112 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
113 { "mmu_flooded", VM_STAT(mmu_flooded) },
114 { "mmu_recycled", VM_STAT(mmu_recycled) },
115 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
116 { "mmu_unsync", VM_STAT(mmu_unsync) },
117 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
118 { "largepages", VM_STAT(lpages) },
119 { NULL }
120 };
121
122 unsigned long segment_base(u16 selector)
123 {
124 struct descriptor_table gdt;
125 struct desc_struct *d;
126 unsigned long table_base;
127 unsigned long v;
128
129 if (selector == 0)
130 return 0;
131
132 asm("sgdt %0" : "=m"(gdt));
133 table_base = gdt.base;
134
135 if (selector & 4) { /* from ldt */
136 u16 ldt_selector;
137
138 asm("sldt %0" : "=g"(ldt_selector));
139 table_base = segment_base(ldt_selector);
140 }
141 d = (struct desc_struct *)(table_base + (selector & ~7));
142 v = d->base0 | ((unsigned long)d->base1 << 16) |
143 ((unsigned long)d->base2 << 24);
144 #ifdef CONFIG_X86_64
145 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
146 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
147 #endif
148 return v;
149 }
150 EXPORT_SYMBOL_GPL(segment_base);
151
152 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
153 {
154 if (irqchip_in_kernel(vcpu->kvm))
155 return vcpu->arch.apic_base;
156 else
157 return vcpu->arch.apic_base;
158 }
159 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
160
161 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
162 {
163 /* TODO: reserve bits check */
164 if (irqchip_in_kernel(vcpu->kvm))
165 kvm_lapic_set_base(vcpu, data);
166 else
167 vcpu->arch.apic_base = data;
168 }
169 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
170
171 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
172 {
173 WARN_ON(vcpu->arch.exception.pending);
174 vcpu->arch.exception.pending = true;
175 vcpu->arch.exception.has_error_code = false;
176 vcpu->arch.exception.nr = nr;
177 }
178 EXPORT_SYMBOL_GPL(kvm_queue_exception);
179
180 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
181 u32 error_code)
182 {
183 ++vcpu->stat.pf_guest;
184
185 if (vcpu->arch.exception.pending) {
186 switch(vcpu->arch.exception.nr) {
187 case DF_VECTOR:
188 /* triple fault -> shutdown */
189 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
190 return;
191 case PF_VECTOR:
192 vcpu->arch.exception.nr = DF_VECTOR;
193 vcpu->arch.exception.error_code = 0;
194 return;
195 default:
196 /* replace previous exception with a new one in a hope
197 that instruction re-execution will regenerate lost
198 exception */
199 vcpu->arch.exception.pending = false;
200 break;
201 }
202 }
203 vcpu->arch.cr2 = addr;
204 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
205 }
206
207 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
208 {
209 vcpu->arch.nmi_pending = 1;
210 }
211 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
212
213 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
214 {
215 WARN_ON(vcpu->arch.exception.pending);
216 vcpu->arch.exception.pending = true;
217 vcpu->arch.exception.has_error_code = true;
218 vcpu->arch.exception.nr = nr;
219 vcpu->arch.exception.error_code = error_code;
220 }
221 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
222
223 static void __queue_exception(struct kvm_vcpu *vcpu)
224 {
225 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
226 vcpu->arch.exception.has_error_code,
227 vcpu->arch.exception.error_code);
228 }
229
230 /*
231 * Load the pae pdptrs. Return true is they are all valid.
232 */
233 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
234 {
235 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
236 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
237 int i;
238 int ret;
239 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
240
241 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
242 offset * sizeof(u64), sizeof(pdpte));
243 if (ret < 0) {
244 ret = 0;
245 goto out;
246 }
247 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
248 if (is_present_gpte(pdpte[i]) &&
249 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
250 ret = 0;
251 goto out;
252 }
253 }
254 ret = 1;
255
256 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
257 __set_bit(VCPU_EXREG_PDPTR,
258 (unsigned long *)&vcpu->arch.regs_avail);
259 __set_bit(VCPU_EXREG_PDPTR,
260 (unsigned long *)&vcpu->arch.regs_dirty);
261 out:
262
263 return ret;
264 }
265 EXPORT_SYMBOL_GPL(load_pdptrs);
266
267 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
268 {
269 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
270 bool changed = true;
271 int r;
272
273 if (is_long_mode(vcpu) || !is_pae(vcpu))
274 return false;
275
276 if (!test_bit(VCPU_EXREG_PDPTR,
277 (unsigned long *)&vcpu->arch.regs_avail))
278 return true;
279
280 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
281 if (r < 0)
282 goto out;
283 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
284 out:
285
286 return changed;
287 }
288
289 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
290 {
291 if (cr0 & CR0_RESERVED_BITS) {
292 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
293 cr0, vcpu->arch.cr0);
294 kvm_inject_gp(vcpu, 0);
295 return;
296 }
297
298 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
299 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
300 kvm_inject_gp(vcpu, 0);
301 return;
302 }
303
304 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
305 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
306 "and a clear PE flag\n");
307 kvm_inject_gp(vcpu, 0);
308 return;
309 }
310
311 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
312 #ifdef CONFIG_X86_64
313 if ((vcpu->arch.shadow_efer & EFER_LME)) {
314 int cs_db, cs_l;
315
316 if (!is_pae(vcpu)) {
317 printk(KERN_DEBUG "set_cr0: #GP, start paging "
318 "in long mode while PAE is disabled\n");
319 kvm_inject_gp(vcpu, 0);
320 return;
321 }
322 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
323 if (cs_l) {
324 printk(KERN_DEBUG "set_cr0: #GP, start paging "
325 "in long mode while CS.L == 1\n");
326 kvm_inject_gp(vcpu, 0);
327 return;
328
329 }
330 } else
331 #endif
332 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
333 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
334 "reserved bits\n");
335 kvm_inject_gp(vcpu, 0);
336 return;
337 }
338
339 }
340
341 kvm_x86_ops->set_cr0(vcpu, cr0);
342 vcpu->arch.cr0 = cr0;
343
344 kvm_mmu_reset_context(vcpu);
345 return;
346 }
347 EXPORT_SYMBOL_GPL(kvm_set_cr0);
348
349 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
350 {
351 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
352 }
353 EXPORT_SYMBOL_GPL(kvm_lmsw);
354
355 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
356 {
357 unsigned long old_cr4 = vcpu->arch.cr4;
358 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
359
360 if (cr4 & CR4_RESERVED_BITS) {
361 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
362 kvm_inject_gp(vcpu, 0);
363 return;
364 }
365
366 if (is_long_mode(vcpu)) {
367 if (!(cr4 & X86_CR4_PAE)) {
368 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
369 "in long mode\n");
370 kvm_inject_gp(vcpu, 0);
371 return;
372 }
373 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
374 && ((cr4 ^ old_cr4) & pdptr_bits)
375 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
376 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
377 kvm_inject_gp(vcpu, 0);
378 return;
379 }
380
381 if (cr4 & X86_CR4_VMXE) {
382 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
383 kvm_inject_gp(vcpu, 0);
384 return;
385 }
386 kvm_x86_ops->set_cr4(vcpu, cr4);
387 vcpu->arch.cr4 = cr4;
388 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
389 kvm_mmu_reset_context(vcpu);
390 }
391 EXPORT_SYMBOL_GPL(kvm_set_cr4);
392
393 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
394 {
395 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
396 kvm_mmu_sync_roots(vcpu);
397 kvm_mmu_flush_tlb(vcpu);
398 return;
399 }
400
401 if (is_long_mode(vcpu)) {
402 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
403 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
404 kvm_inject_gp(vcpu, 0);
405 return;
406 }
407 } else {
408 if (is_pae(vcpu)) {
409 if (cr3 & CR3_PAE_RESERVED_BITS) {
410 printk(KERN_DEBUG
411 "set_cr3: #GP, reserved bits\n");
412 kvm_inject_gp(vcpu, 0);
413 return;
414 }
415 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
416 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
417 "reserved bits\n");
418 kvm_inject_gp(vcpu, 0);
419 return;
420 }
421 }
422 /*
423 * We don't check reserved bits in nonpae mode, because
424 * this isn't enforced, and VMware depends on this.
425 */
426 }
427
428 /*
429 * Does the new cr3 value map to physical memory? (Note, we
430 * catch an invalid cr3 even in real-mode, because it would
431 * cause trouble later on when we turn on paging anyway.)
432 *
433 * A real CPU would silently accept an invalid cr3 and would
434 * attempt to use it - with largely undefined (and often hard
435 * to debug) behavior on the guest side.
436 */
437 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
438 kvm_inject_gp(vcpu, 0);
439 else {
440 vcpu->arch.cr3 = cr3;
441 vcpu->arch.mmu.new_cr3(vcpu);
442 }
443 }
444 EXPORT_SYMBOL_GPL(kvm_set_cr3);
445
446 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
447 {
448 if (cr8 & CR8_RESERVED_BITS) {
449 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
450 kvm_inject_gp(vcpu, 0);
451 return;
452 }
453 if (irqchip_in_kernel(vcpu->kvm))
454 kvm_lapic_set_tpr(vcpu, cr8);
455 else
456 vcpu->arch.cr8 = cr8;
457 }
458 EXPORT_SYMBOL_GPL(kvm_set_cr8);
459
460 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
461 {
462 if (irqchip_in_kernel(vcpu->kvm))
463 return kvm_lapic_get_cr8(vcpu);
464 else
465 return vcpu->arch.cr8;
466 }
467 EXPORT_SYMBOL_GPL(kvm_get_cr8);
468
469 static inline u32 bit(int bitno)
470 {
471 return 1 << (bitno & 31);
472 }
473
474 /*
475 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
476 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
477 *
478 * This list is modified at module load time to reflect the
479 * capabilities of the host cpu.
480 */
481 static u32 msrs_to_save[] = {
482 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
483 MSR_K6_STAR,
484 #ifdef CONFIG_X86_64
485 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
486 #endif
487 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
488 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
489 };
490
491 static unsigned num_msrs_to_save;
492
493 static u32 emulated_msrs[] = {
494 MSR_IA32_MISC_ENABLE,
495 };
496
497 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
498 {
499 if (efer & efer_reserved_bits) {
500 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
501 efer);
502 kvm_inject_gp(vcpu, 0);
503 return;
504 }
505
506 if (is_paging(vcpu)
507 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
508 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
509 kvm_inject_gp(vcpu, 0);
510 return;
511 }
512
513 if (efer & EFER_FFXSR) {
514 struct kvm_cpuid_entry2 *feat;
515
516 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
517 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
518 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
519 kvm_inject_gp(vcpu, 0);
520 return;
521 }
522 }
523
524 if (efer & EFER_SVME) {
525 struct kvm_cpuid_entry2 *feat;
526
527 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
528 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
529 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
530 kvm_inject_gp(vcpu, 0);
531 return;
532 }
533 }
534
535 kvm_x86_ops->set_efer(vcpu, efer);
536
537 efer &= ~EFER_LMA;
538 efer |= vcpu->arch.shadow_efer & EFER_LMA;
539
540 vcpu->arch.shadow_efer = efer;
541
542 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
543 kvm_mmu_reset_context(vcpu);
544 }
545
546 void kvm_enable_efer_bits(u64 mask)
547 {
548 efer_reserved_bits &= ~mask;
549 }
550 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
551
552
553 /*
554 * Writes msr value into into the appropriate "register".
555 * Returns 0 on success, non-0 otherwise.
556 * Assumes vcpu_load() was already called.
557 */
558 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
559 {
560 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
561 }
562
563 /*
564 * Adapt set_msr() to msr_io()'s calling convention
565 */
566 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
567 {
568 return kvm_set_msr(vcpu, index, *data);
569 }
570
571 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
572 {
573 static int version;
574 struct pvclock_wall_clock wc;
575 struct timespec now, sys, boot;
576
577 if (!wall_clock)
578 return;
579
580 version++;
581
582 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
583
584 /*
585 * The guest calculates current wall clock time by adding
586 * system time (updated by kvm_write_guest_time below) to the
587 * wall clock specified here. guest system time equals host
588 * system time for us, thus we must fill in host boot time here.
589 */
590 now = current_kernel_time();
591 ktime_get_ts(&sys);
592 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
593
594 wc.sec = boot.tv_sec;
595 wc.nsec = boot.tv_nsec;
596 wc.version = version;
597
598 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
599
600 version++;
601 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
602 }
603
604 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
605 {
606 uint32_t quotient, remainder;
607
608 /* Don't try to replace with do_div(), this one calculates
609 * "(dividend << 32) / divisor" */
610 __asm__ ( "divl %4"
611 : "=a" (quotient), "=d" (remainder)
612 : "0" (0), "1" (dividend), "r" (divisor) );
613 return quotient;
614 }
615
616 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
617 {
618 uint64_t nsecs = 1000000000LL;
619 int32_t shift = 0;
620 uint64_t tps64;
621 uint32_t tps32;
622
623 tps64 = tsc_khz * 1000LL;
624 while (tps64 > nsecs*2) {
625 tps64 >>= 1;
626 shift--;
627 }
628
629 tps32 = (uint32_t)tps64;
630 while (tps32 <= (uint32_t)nsecs) {
631 tps32 <<= 1;
632 shift++;
633 }
634
635 hv_clock->tsc_shift = shift;
636 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
637
638 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
639 __func__, tsc_khz, hv_clock->tsc_shift,
640 hv_clock->tsc_to_system_mul);
641 }
642
643 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
644
645 static void kvm_write_guest_time(struct kvm_vcpu *v)
646 {
647 struct timespec ts;
648 unsigned long flags;
649 struct kvm_vcpu_arch *vcpu = &v->arch;
650 void *shared_kaddr;
651 unsigned long this_tsc_khz;
652
653 if ((!vcpu->time_page))
654 return;
655
656 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
657 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
658 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
659 vcpu->hv_clock_tsc_khz = this_tsc_khz;
660 }
661 put_cpu_var(cpu_tsc_khz);
662
663 /* Keep irq disabled to prevent changes to the clock */
664 local_irq_save(flags);
665 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
666 ktime_get_ts(&ts);
667 local_irq_restore(flags);
668
669 /* With all the info we got, fill in the values */
670
671 vcpu->hv_clock.system_time = ts.tv_nsec +
672 (NSEC_PER_SEC * (u64)ts.tv_sec);
673 /*
674 * The interface expects us to write an even number signaling that the
675 * update is finished. Since the guest won't see the intermediate
676 * state, we just increase by 2 at the end.
677 */
678 vcpu->hv_clock.version += 2;
679
680 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
681
682 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
683 sizeof(vcpu->hv_clock));
684
685 kunmap_atomic(shared_kaddr, KM_USER0);
686
687 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
688 }
689
690 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
691 {
692 struct kvm_vcpu_arch *vcpu = &v->arch;
693
694 if (!vcpu->time_page)
695 return 0;
696 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
697 return 1;
698 }
699
700 static bool msr_mtrr_valid(unsigned msr)
701 {
702 switch (msr) {
703 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
704 case MSR_MTRRfix64K_00000:
705 case MSR_MTRRfix16K_80000:
706 case MSR_MTRRfix16K_A0000:
707 case MSR_MTRRfix4K_C0000:
708 case MSR_MTRRfix4K_C8000:
709 case MSR_MTRRfix4K_D0000:
710 case MSR_MTRRfix4K_D8000:
711 case MSR_MTRRfix4K_E0000:
712 case MSR_MTRRfix4K_E8000:
713 case MSR_MTRRfix4K_F0000:
714 case MSR_MTRRfix4K_F8000:
715 case MSR_MTRRdefType:
716 case MSR_IA32_CR_PAT:
717 return true;
718 case 0x2f8:
719 return true;
720 }
721 return false;
722 }
723
724 static bool valid_pat_type(unsigned t)
725 {
726 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
727 }
728
729 static bool valid_mtrr_type(unsigned t)
730 {
731 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
732 }
733
734 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
735 {
736 int i;
737
738 if (!msr_mtrr_valid(msr))
739 return false;
740
741 if (msr == MSR_IA32_CR_PAT) {
742 for (i = 0; i < 8; i++)
743 if (!valid_pat_type((data >> (i * 8)) & 0xff))
744 return false;
745 return true;
746 } else if (msr == MSR_MTRRdefType) {
747 if (data & ~0xcff)
748 return false;
749 return valid_mtrr_type(data & 0xff);
750 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
751 for (i = 0; i < 8 ; i++)
752 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
753 return false;
754 return true;
755 }
756
757 /* variable MTRRs */
758 return valid_mtrr_type(data & 0xff);
759 }
760
761 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
762 {
763 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
764
765 if (!mtrr_valid(vcpu, msr, data))
766 return 1;
767
768 if (msr == MSR_MTRRdefType) {
769 vcpu->arch.mtrr_state.def_type = data;
770 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
771 } else if (msr == MSR_MTRRfix64K_00000)
772 p[0] = data;
773 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
774 p[1 + msr - MSR_MTRRfix16K_80000] = data;
775 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
776 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
777 else if (msr == MSR_IA32_CR_PAT)
778 vcpu->arch.pat = data;
779 else { /* Variable MTRRs */
780 int idx, is_mtrr_mask;
781 u64 *pt;
782
783 idx = (msr - 0x200) / 2;
784 is_mtrr_mask = msr - 0x200 - 2 * idx;
785 if (!is_mtrr_mask)
786 pt =
787 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
788 else
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
791 *pt = data;
792 }
793
794 kvm_mmu_reset_context(vcpu);
795 return 0;
796 }
797
798 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
799 {
800 u64 mcg_cap = vcpu->arch.mcg_cap;
801 unsigned bank_num = mcg_cap & 0xff;
802
803 switch (msr) {
804 case MSR_IA32_MCG_STATUS:
805 vcpu->arch.mcg_status = data;
806 break;
807 case MSR_IA32_MCG_CTL:
808 if (!(mcg_cap & MCG_CTL_P))
809 return 1;
810 if (data != 0 && data != ~(u64)0)
811 return -1;
812 vcpu->arch.mcg_ctl = data;
813 break;
814 default:
815 if (msr >= MSR_IA32_MC0_CTL &&
816 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
817 u32 offset = msr - MSR_IA32_MC0_CTL;
818 /* only 0 or all 1s can be written to IA32_MCi_CTL */
819 if ((offset & 0x3) == 0 &&
820 data != 0 && data != ~(u64)0)
821 return -1;
822 vcpu->arch.mce_banks[offset] = data;
823 break;
824 }
825 return 1;
826 }
827 return 0;
828 }
829
830 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
831 {
832 switch (msr) {
833 case MSR_EFER:
834 set_efer(vcpu, data);
835 break;
836 case MSR_K7_HWCR:
837 data &= ~(u64)0x40; /* ignore flush filter disable */
838 if (data != 0) {
839 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
840 data);
841 return 1;
842 }
843 break;
844 case MSR_IA32_DEBUGCTLMSR:
845 if (!data) {
846 /* We support the non-activated case already */
847 break;
848 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
849 /* Values other than LBR and BTF are vendor-specific,
850 thus reserved and should throw a #GP */
851 return 1;
852 }
853 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
854 __func__, data);
855 break;
856 case MSR_IA32_UCODE_REV:
857 case MSR_IA32_UCODE_WRITE:
858 case MSR_VM_HSAVE_PA:
859 break;
860 case 0x200 ... 0x2ff:
861 return set_msr_mtrr(vcpu, msr, data);
862 case MSR_IA32_APICBASE:
863 kvm_set_apic_base(vcpu, data);
864 break;
865 case MSR_IA32_MISC_ENABLE:
866 vcpu->arch.ia32_misc_enable_msr = data;
867 break;
868 case MSR_KVM_WALL_CLOCK:
869 vcpu->kvm->arch.wall_clock = data;
870 kvm_write_wall_clock(vcpu->kvm, data);
871 break;
872 case MSR_KVM_SYSTEM_TIME: {
873 if (vcpu->arch.time_page) {
874 kvm_release_page_dirty(vcpu->arch.time_page);
875 vcpu->arch.time_page = NULL;
876 }
877
878 vcpu->arch.time = data;
879
880 /* we verify if the enable bit is set... */
881 if (!(data & 1))
882 break;
883
884 /* ...but clean it before doing the actual write */
885 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
886
887 vcpu->arch.time_page =
888 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
889
890 if (is_error_page(vcpu->arch.time_page)) {
891 kvm_release_page_clean(vcpu->arch.time_page);
892 vcpu->arch.time_page = NULL;
893 }
894
895 kvm_request_guest_time_update(vcpu);
896 break;
897 }
898 case MSR_IA32_MCG_CTL:
899 case MSR_IA32_MCG_STATUS:
900 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
901 return set_msr_mce(vcpu, msr, data);
902
903 /* Performance counters are not protected by a CPUID bit,
904 * so we should check all of them in the generic path for the sake of
905 * cross vendor migration.
906 * Writing a zero into the event select MSRs disables them,
907 * which we perfectly emulate ;-). Any other value should be at least
908 * reported, some guests depend on them.
909 */
910 case MSR_P6_EVNTSEL0:
911 case MSR_P6_EVNTSEL1:
912 case MSR_K7_EVNTSEL0:
913 case MSR_K7_EVNTSEL1:
914 case MSR_K7_EVNTSEL2:
915 case MSR_K7_EVNTSEL3:
916 if (data != 0)
917 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
918 "0x%x data 0x%llx\n", msr, data);
919 break;
920 /* at least RHEL 4 unconditionally writes to the perfctr registers,
921 * so we ignore writes to make it happy.
922 */
923 case MSR_P6_PERFCTR0:
924 case MSR_P6_PERFCTR1:
925 case MSR_K7_PERFCTR0:
926 case MSR_K7_PERFCTR1:
927 case MSR_K7_PERFCTR2:
928 case MSR_K7_PERFCTR3:
929 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
930 "0x%x data 0x%llx\n", msr, data);
931 break;
932 default:
933 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
934 return 1;
935 }
936 return 0;
937 }
938 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
939
940
941 /*
942 * Reads an msr value (of 'msr_index') into 'pdata'.
943 * Returns 0 on success, non-0 otherwise.
944 * Assumes vcpu_load() was already called.
945 */
946 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
947 {
948 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
949 }
950
951 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
952 {
953 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
954
955 if (!msr_mtrr_valid(msr))
956 return 1;
957
958 if (msr == MSR_MTRRdefType)
959 *pdata = vcpu->arch.mtrr_state.def_type +
960 (vcpu->arch.mtrr_state.enabled << 10);
961 else if (msr == MSR_MTRRfix64K_00000)
962 *pdata = p[0];
963 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
964 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
965 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
966 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
967 else if (msr == MSR_IA32_CR_PAT)
968 *pdata = vcpu->arch.pat;
969 else { /* Variable MTRRs */
970 int idx, is_mtrr_mask;
971 u64 *pt;
972
973 idx = (msr - 0x200) / 2;
974 is_mtrr_mask = msr - 0x200 - 2 * idx;
975 if (!is_mtrr_mask)
976 pt =
977 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
978 else
979 pt =
980 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
981 *pdata = *pt;
982 }
983
984 return 0;
985 }
986
987 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
988 {
989 u64 data;
990 u64 mcg_cap = vcpu->arch.mcg_cap;
991 unsigned bank_num = mcg_cap & 0xff;
992
993 switch (msr) {
994 case MSR_IA32_P5_MC_ADDR:
995 case MSR_IA32_P5_MC_TYPE:
996 data = 0;
997 break;
998 case MSR_IA32_MCG_CAP:
999 data = vcpu->arch.mcg_cap;
1000 break;
1001 case MSR_IA32_MCG_CTL:
1002 if (!(mcg_cap & MCG_CTL_P))
1003 return 1;
1004 data = vcpu->arch.mcg_ctl;
1005 break;
1006 case MSR_IA32_MCG_STATUS:
1007 data = vcpu->arch.mcg_status;
1008 break;
1009 default:
1010 if (msr >= MSR_IA32_MC0_CTL &&
1011 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1012 u32 offset = msr - MSR_IA32_MC0_CTL;
1013 data = vcpu->arch.mce_banks[offset];
1014 break;
1015 }
1016 return 1;
1017 }
1018 *pdata = data;
1019 return 0;
1020 }
1021
1022 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1023 {
1024 u64 data;
1025
1026 switch (msr) {
1027 case MSR_IA32_PLATFORM_ID:
1028 case MSR_IA32_UCODE_REV:
1029 case MSR_IA32_EBL_CR_POWERON:
1030 case MSR_IA32_DEBUGCTLMSR:
1031 case MSR_IA32_LASTBRANCHFROMIP:
1032 case MSR_IA32_LASTBRANCHTOIP:
1033 case MSR_IA32_LASTINTFROMIP:
1034 case MSR_IA32_LASTINTTOIP:
1035 case MSR_K8_SYSCFG:
1036 case MSR_K7_HWCR:
1037 case MSR_VM_HSAVE_PA:
1038 case MSR_P6_EVNTSEL0:
1039 case MSR_P6_EVNTSEL1:
1040 case MSR_K7_EVNTSEL0:
1041 case MSR_K8_INT_PENDING_MSG:
1042 data = 0;
1043 break;
1044 case MSR_MTRRcap:
1045 data = 0x500 | KVM_NR_VAR_MTRR;
1046 break;
1047 case 0x200 ... 0x2ff:
1048 return get_msr_mtrr(vcpu, msr, pdata);
1049 case 0xcd: /* fsb frequency */
1050 data = 3;
1051 break;
1052 case MSR_IA32_APICBASE:
1053 data = kvm_get_apic_base(vcpu);
1054 break;
1055 case MSR_IA32_MISC_ENABLE:
1056 data = vcpu->arch.ia32_misc_enable_msr;
1057 break;
1058 case MSR_IA32_PERF_STATUS:
1059 /* TSC increment by tick */
1060 data = 1000ULL;
1061 /* CPU multiplier */
1062 data |= (((uint64_t)4ULL) << 40);
1063 break;
1064 case MSR_EFER:
1065 data = vcpu->arch.shadow_efer;
1066 break;
1067 case MSR_KVM_WALL_CLOCK:
1068 data = vcpu->kvm->arch.wall_clock;
1069 break;
1070 case MSR_KVM_SYSTEM_TIME:
1071 data = vcpu->arch.time;
1072 break;
1073 case MSR_IA32_P5_MC_ADDR:
1074 case MSR_IA32_P5_MC_TYPE:
1075 case MSR_IA32_MCG_CAP:
1076 case MSR_IA32_MCG_CTL:
1077 case MSR_IA32_MCG_STATUS:
1078 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1079 return get_msr_mce(vcpu, msr, pdata);
1080 default:
1081 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1082 return 1;
1083 }
1084 *pdata = data;
1085 return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1088
1089 /*
1090 * Read or write a bunch of msrs. All parameters are kernel addresses.
1091 *
1092 * @return number of msrs set successfully.
1093 */
1094 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1095 struct kvm_msr_entry *entries,
1096 int (*do_msr)(struct kvm_vcpu *vcpu,
1097 unsigned index, u64 *data))
1098 {
1099 int i;
1100
1101 vcpu_load(vcpu);
1102
1103 down_read(&vcpu->kvm->slots_lock);
1104 for (i = 0; i < msrs->nmsrs; ++i)
1105 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1106 break;
1107 up_read(&vcpu->kvm->slots_lock);
1108
1109 vcpu_put(vcpu);
1110
1111 return i;
1112 }
1113
1114 /*
1115 * Read or write a bunch of msrs. Parameters are user addresses.
1116 *
1117 * @return number of msrs set successfully.
1118 */
1119 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1120 int (*do_msr)(struct kvm_vcpu *vcpu,
1121 unsigned index, u64 *data),
1122 int writeback)
1123 {
1124 struct kvm_msrs msrs;
1125 struct kvm_msr_entry *entries;
1126 int r, n;
1127 unsigned size;
1128
1129 r = -EFAULT;
1130 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1131 goto out;
1132
1133 r = -E2BIG;
1134 if (msrs.nmsrs >= MAX_IO_MSRS)
1135 goto out;
1136
1137 r = -ENOMEM;
1138 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1139 entries = vmalloc(size);
1140 if (!entries)
1141 goto out;
1142
1143 r = -EFAULT;
1144 if (copy_from_user(entries, user_msrs->entries, size))
1145 goto out_free;
1146
1147 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1148 if (r < 0)
1149 goto out_free;
1150
1151 r = -EFAULT;
1152 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1153 goto out_free;
1154
1155 r = n;
1156
1157 out_free:
1158 vfree(entries);
1159 out:
1160 return r;
1161 }
1162
1163 int kvm_dev_ioctl_check_extension(long ext)
1164 {
1165 int r;
1166
1167 switch (ext) {
1168 case KVM_CAP_IRQCHIP:
1169 case KVM_CAP_HLT:
1170 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1171 case KVM_CAP_SET_TSS_ADDR:
1172 case KVM_CAP_EXT_CPUID:
1173 case KVM_CAP_CLOCKSOURCE:
1174 case KVM_CAP_PIT:
1175 case KVM_CAP_NOP_IO_DELAY:
1176 case KVM_CAP_MP_STATE:
1177 case KVM_CAP_SYNC_MMU:
1178 case KVM_CAP_REINJECT_CONTROL:
1179 case KVM_CAP_IRQ_INJECT_STATUS:
1180 case KVM_CAP_ASSIGN_DEV_IRQ:
1181 case KVM_CAP_IRQFD:
1182 case KVM_CAP_PIT2:
1183 r = 1;
1184 break;
1185 case KVM_CAP_COALESCED_MMIO:
1186 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1187 break;
1188 case KVM_CAP_VAPIC:
1189 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1190 break;
1191 case KVM_CAP_NR_VCPUS:
1192 r = KVM_MAX_VCPUS;
1193 break;
1194 case KVM_CAP_NR_MEMSLOTS:
1195 r = KVM_MEMORY_SLOTS;
1196 break;
1197 case KVM_CAP_PV_MMU:
1198 r = !tdp_enabled;
1199 break;
1200 case KVM_CAP_IOMMU:
1201 r = iommu_found();
1202 break;
1203 case KVM_CAP_MCE:
1204 r = KVM_MAX_MCE_BANKS;
1205 break;
1206 default:
1207 r = 0;
1208 break;
1209 }
1210 return r;
1211
1212 }
1213
1214 long kvm_arch_dev_ioctl(struct file *filp,
1215 unsigned int ioctl, unsigned long arg)
1216 {
1217 void __user *argp = (void __user *)arg;
1218 long r;
1219
1220 switch (ioctl) {
1221 case KVM_GET_MSR_INDEX_LIST: {
1222 struct kvm_msr_list __user *user_msr_list = argp;
1223 struct kvm_msr_list msr_list;
1224 unsigned n;
1225
1226 r = -EFAULT;
1227 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1228 goto out;
1229 n = msr_list.nmsrs;
1230 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1231 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1232 goto out;
1233 r = -E2BIG;
1234 if (n < msr_list.nmsrs)
1235 goto out;
1236 r = -EFAULT;
1237 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1238 num_msrs_to_save * sizeof(u32)))
1239 goto out;
1240 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1241 &emulated_msrs,
1242 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1243 goto out;
1244 r = 0;
1245 break;
1246 }
1247 case KVM_GET_SUPPORTED_CPUID: {
1248 struct kvm_cpuid2 __user *cpuid_arg = argp;
1249 struct kvm_cpuid2 cpuid;
1250
1251 r = -EFAULT;
1252 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1253 goto out;
1254 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1255 cpuid_arg->entries);
1256 if (r)
1257 goto out;
1258
1259 r = -EFAULT;
1260 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1261 goto out;
1262 r = 0;
1263 break;
1264 }
1265 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1266 u64 mce_cap;
1267
1268 mce_cap = KVM_MCE_CAP_SUPPORTED;
1269 r = -EFAULT;
1270 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1271 goto out;
1272 r = 0;
1273 break;
1274 }
1275 default:
1276 r = -EINVAL;
1277 }
1278 out:
1279 return r;
1280 }
1281
1282 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1283 {
1284 kvm_x86_ops->vcpu_load(vcpu, cpu);
1285 kvm_request_guest_time_update(vcpu);
1286 }
1287
1288 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1289 {
1290 kvm_x86_ops->vcpu_put(vcpu);
1291 kvm_put_guest_fpu(vcpu);
1292 }
1293
1294 static int is_efer_nx(void)
1295 {
1296 unsigned long long efer = 0;
1297
1298 rdmsrl_safe(MSR_EFER, &efer);
1299 return efer & EFER_NX;
1300 }
1301
1302 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1303 {
1304 int i;
1305 struct kvm_cpuid_entry2 *e, *entry;
1306
1307 entry = NULL;
1308 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1309 e = &vcpu->arch.cpuid_entries[i];
1310 if (e->function == 0x80000001) {
1311 entry = e;
1312 break;
1313 }
1314 }
1315 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1316 entry->edx &= ~(1 << 20);
1317 printk(KERN_INFO "kvm: guest NX capability removed\n");
1318 }
1319 }
1320
1321 /* when an old userspace process fills a new kernel module */
1322 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1323 struct kvm_cpuid *cpuid,
1324 struct kvm_cpuid_entry __user *entries)
1325 {
1326 int r, i;
1327 struct kvm_cpuid_entry *cpuid_entries;
1328
1329 r = -E2BIG;
1330 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1331 goto out;
1332 r = -ENOMEM;
1333 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1334 if (!cpuid_entries)
1335 goto out;
1336 r = -EFAULT;
1337 if (copy_from_user(cpuid_entries, entries,
1338 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1339 goto out_free;
1340 for (i = 0; i < cpuid->nent; i++) {
1341 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1342 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1343 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1344 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1345 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1346 vcpu->arch.cpuid_entries[i].index = 0;
1347 vcpu->arch.cpuid_entries[i].flags = 0;
1348 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1349 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1350 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1351 }
1352 vcpu->arch.cpuid_nent = cpuid->nent;
1353 cpuid_fix_nx_cap(vcpu);
1354 r = 0;
1355
1356 out_free:
1357 vfree(cpuid_entries);
1358 out:
1359 return r;
1360 }
1361
1362 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1363 struct kvm_cpuid2 *cpuid,
1364 struct kvm_cpuid_entry2 __user *entries)
1365 {
1366 int r;
1367
1368 r = -E2BIG;
1369 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1370 goto out;
1371 r = -EFAULT;
1372 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1373 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1374 goto out;
1375 vcpu->arch.cpuid_nent = cpuid->nent;
1376 return 0;
1377
1378 out:
1379 return r;
1380 }
1381
1382 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1383 struct kvm_cpuid2 *cpuid,
1384 struct kvm_cpuid_entry2 __user *entries)
1385 {
1386 int r;
1387
1388 r = -E2BIG;
1389 if (cpuid->nent < vcpu->arch.cpuid_nent)
1390 goto out;
1391 r = -EFAULT;
1392 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1393 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1394 goto out;
1395 return 0;
1396
1397 out:
1398 cpuid->nent = vcpu->arch.cpuid_nent;
1399 return r;
1400 }
1401
1402 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1403 u32 index)
1404 {
1405 entry->function = function;
1406 entry->index = index;
1407 cpuid_count(entry->function, entry->index,
1408 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1409 entry->flags = 0;
1410 }
1411
1412 #define F(x) bit(X86_FEATURE_##x)
1413
1414 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1415 u32 index, int *nent, int maxnent)
1416 {
1417 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1418 #ifdef CONFIG_X86_64
1419 unsigned f_lm = F(LM);
1420 #else
1421 unsigned f_lm = 0;
1422 #endif
1423
1424 /* cpuid 1.edx */
1425 const u32 kvm_supported_word0_x86_features =
1426 F(FPU) | F(VME) | F(DE) | F(PSE) |
1427 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1428 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1429 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1430 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1431 0 /* Reserved, DS, ACPI */ | F(MMX) |
1432 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1433 0 /* HTT, TM, Reserved, PBE */;
1434 /* cpuid 0x80000001.edx */
1435 const u32 kvm_supported_word1_x86_features =
1436 F(FPU) | F(VME) | F(DE) | F(PSE) |
1437 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1438 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1439 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1440 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1441 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1442 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1443 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1444 /* cpuid 1.ecx */
1445 const u32 kvm_supported_word4_x86_features =
1446 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1447 0 /* DS-CPL, VMX, SMX, EST */ |
1448 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1449 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1450 0 /* Reserved, DCA */ | F(XMM4_1) |
1451 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1452 0 /* Reserved, XSAVE, OSXSAVE */;
1453 /* cpuid 0x80000001.ecx */
1454 const u32 kvm_supported_word6_x86_features =
1455 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1456 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1457 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1458 0 /* SKINIT */ | 0 /* WDT */;
1459
1460 /* all calls to cpuid_count() should be made on the same cpu */
1461 get_cpu();
1462 do_cpuid_1_ent(entry, function, index);
1463 ++*nent;
1464
1465 switch (function) {
1466 case 0:
1467 entry->eax = min(entry->eax, (u32)0xb);
1468 break;
1469 case 1:
1470 entry->edx &= kvm_supported_word0_x86_features;
1471 entry->ecx &= kvm_supported_word4_x86_features;
1472 break;
1473 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1474 * may return different values. This forces us to get_cpu() before
1475 * issuing the first command, and also to emulate this annoying behavior
1476 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1477 case 2: {
1478 int t, times = entry->eax & 0xff;
1479
1480 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1481 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1482 for (t = 1; t < times && *nent < maxnent; ++t) {
1483 do_cpuid_1_ent(&entry[t], function, 0);
1484 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1485 ++*nent;
1486 }
1487 break;
1488 }
1489 /* function 4 and 0xb have additional index. */
1490 case 4: {
1491 int i, cache_type;
1492
1493 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1494 /* read more entries until cache_type is zero */
1495 for (i = 1; *nent < maxnent; ++i) {
1496 cache_type = entry[i - 1].eax & 0x1f;
1497 if (!cache_type)
1498 break;
1499 do_cpuid_1_ent(&entry[i], function, i);
1500 entry[i].flags |=
1501 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1502 ++*nent;
1503 }
1504 break;
1505 }
1506 case 0xb: {
1507 int i, level_type;
1508
1509 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1510 /* read more entries until level_type is zero */
1511 for (i = 1; *nent < maxnent; ++i) {
1512 level_type = entry[i - 1].ecx & 0xff00;
1513 if (!level_type)
1514 break;
1515 do_cpuid_1_ent(&entry[i], function, i);
1516 entry[i].flags |=
1517 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1518 ++*nent;
1519 }
1520 break;
1521 }
1522 case 0x80000000:
1523 entry->eax = min(entry->eax, 0x8000001a);
1524 break;
1525 case 0x80000001:
1526 entry->edx &= kvm_supported_word1_x86_features;
1527 entry->ecx &= kvm_supported_word6_x86_features;
1528 break;
1529 }
1530 put_cpu();
1531 }
1532
1533 #undef F
1534
1535 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1536 struct kvm_cpuid_entry2 __user *entries)
1537 {
1538 struct kvm_cpuid_entry2 *cpuid_entries;
1539 int limit, nent = 0, r = -E2BIG;
1540 u32 func;
1541
1542 if (cpuid->nent < 1)
1543 goto out;
1544 r = -ENOMEM;
1545 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1546 if (!cpuid_entries)
1547 goto out;
1548
1549 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1550 limit = cpuid_entries[0].eax;
1551 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1552 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1553 &nent, cpuid->nent);
1554 r = -E2BIG;
1555 if (nent >= cpuid->nent)
1556 goto out_free;
1557
1558 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1559 limit = cpuid_entries[nent - 1].eax;
1560 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1561 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1562 &nent, cpuid->nent);
1563 r = -E2BIG;
1564 if (nent >= cpuid->nent)
1565 goto out_free;
1566
1567 r = -EFAULT;
1568 if (copy_to_user(entries, cpuid_entries,
1569 nent * sizeof(struct kvm_cpuid_entry2)))
1570 goto out_free;
1571 cpuid->nent = nent;
1572 r = 0;
1573
1574 out_free:
1575 vfree(cpuid_entries);
1576 out:
1577 return r;
1578 }
1579
1580 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1581 struct kvm_lapic_state *s)
1582 {
1583 vcpu_load(vcpu);
1584 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1585 vcpu_put(vcpu);
1586
1587 return 0;
1588 }
1589
1590 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1591 struct kvm_lapic_state *s)
1592 {
1593 vcpu_load(vcpu);
1594 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1595 kvm_apic_post_state_restore(vcpu);
1596 vcpu_put(vcpu);
1597
1598 return 0;
1599 }
1600
1601 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1602 struct kvm_interrupt *irq)
1603 {
1604 if (irq->irq < 0 || irq->irq >= 256)
1605 return -EINVAL;
1606 if (irqchip_in_kernel(vcpu->kvm))
1607 return -ENXIO;
1608 vcpu_load(vcpu);
1609
1610 kvm_queue_interrupt(vcpu, irq->irq, false);
1611
1612 vcpu_put(vcpu);
1613
1614 return 0;
1615 }
1616
1617 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1618 {
1619 vcpu_load(vcpu);
1620 kvm_inject_nmi(vcpu);
1621 vcpu_put(vcpu);
1622
1623 return 0;
1624 }
1625
1626 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1627 struct kvm_tpr_access_ctl *tac)
1628 {
1629 if (tac->flags)
1630 return -EINVAL;
1631 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1632 return 0;
1633 }
1634
1635 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1636 u64 mcg_cap)
1637 {
1638 int r;
1639 unsigned bank_num = mcg_cap & 0xff, bank;
1640
1641 r = -EINVAL;
1642 if (!bank_num)
1643 goto out;
1644 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1645 goto out;
1646 r = 0;
1647 vcpu->arch.mcg_cap = mcg_cap;
1648 /* Init IA32_MCG_CTL to all 1s */
1649 if (mcg_cap & MCG_CTL_P)
1650 vcpu->arch.mcg_ctl = ~(u64)0;
1651 /* Init IA32_MCi_CTL to all 1s */
1652 for (bank = 0; bank < bank_num; bank++)
1653 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1654 out:
1655 return r;
1656 }
1657
1658 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1659 struct kvm_x86_mce *mce)
1660 {
1661 u64 mcg_cap = vcpu->arch.mcg_cap;
1662 unsigned bank_num = mcg_cap & 0xff;
1663 u64 *banks = vcpu->arch.mce_banks;
1664
1665 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1666 return -EINVAL;
1667 /*
1668 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1669 * reporting is disabled
1670 */
1671 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1672 vcpu->arch.mcg_ctl != ~(u64)0)
1673 return 0;
1674 banks += 4 * mce->bank;
1675 /*
1676 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1677 * reporting is disabled for the bank
1678 */
1679 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1680 return 0;
1681 if (mce->status & MCI_STATUS_UC) {
1682 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1683 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1684 printk(KERN_DEBUG "kvm: set_mce: "
1685 "injects mce exception while "
1686 "previous one is in progress!\n");
1687 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1688 return 0;
1689 }
1690 if (banks[1] & MCI_STATUS_VAL)
1691 mce->status |= MCI_STATUS_OVER;
1692 banks[2] = mce->addr;
1693 banks[3] = mce->misc;
1694 vcpu->arch.mcg_status = mce->mcg_status;
1695 banks[1] = mce->status;
1696 kvm_queue_exception(vcpu, MC_VECTOR);
1697 } else if (!(banks[1] & MCI_STATUS_VAL)
1698 || !(banks[1] & MCI_STATUS_UC)) {
1699 if (banks[1] & MCI_STATUS_VAL)
1700 mce->status |= MCI_STATUS_OVER;
1701 banks[2] = mce->addr;
1702 banks[3] = mce->misc;
1703 banks[1] = mce->status;
1704 } else
1705 banks[1] |= MCI_STATUS_OVER;
1706 return 0;
1707 }
1708
1709 long kvm_arch_vcpu_ioctl(struct file *filp,
1710 unsigned int ioctl, unsigned long arg)
1711 {
1712 struct kvm_vcpu *vcpu = filp->private_data;
1713 void __user *argp = (void __user *)arg;
1714 int r;
1715 struct kvm_lapic_state *lapic = NULL;
1716
1717 switch (ioctl) {
1718 case KVM_GET_LAPIC: {
1719 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1720
1721 r = -ENOMEM;
1722 if (!lapic)
1723 goto out;
1724 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1725 if (r)
1726 goto out;
1727 r = -EFAULT;
1728 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1729 goto out;
1730 r = 0;
1731 break;
1732 }
1733 case KVM_SET_LAPIC: {
1734 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1735 r = -ENOMEM;
1736 if (!lapic)
1737 goto out;
1738 r = -EFAULT;
1739 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1740 goto out;
1741 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1742 if (r)
1743 goto out;
1744 r = 0;
1745 break;
1746 }
1747 case KVM_INTERRUPT: {
1748 struct kvm_interrupt irq;
1749
1750 r = -EFAULT;
1751 if (copy_from_user(&irq, argp, sizeof irq))
1752 goto out;
1753 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1754 if (r)
1755 goto out;
1756 r = 0;
1757 break;
1758 }
1759 case KVM_NMI: {
1760 r = kvm_vcpu_ioctl_nmi(vcpu);
1761 if (r)
1762 goto out;
1763 r = 0;
1764 break;
1765 }
1766 case KVM_SET_CPUID: {
1767 struct kvm_cpuid __user *cpuid_arg = argp;
1768 struct kvm_cpuid cpuid;
1769
1770 r = -EFAULT;
1771 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1772 goto out;
1773 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1774 if (r)
1775 goto out;
1776 break;
1777 }
1778 case KVM_SET_CPUID2: {
1779 struct kvm_cpuid2 __user *cpuid_arg = argp;
1780 struct kvm_cpuid2 cpuid;
1781
1782 r = -EFAULT;
1783 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1784 goto out;
1785 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1786 cpuid_arg->entries);
1787 if (r)
1788 goto out;
1789 break;
1790 }
1791 case KVM_GET_CPUID2: {
1792 struct kvm_cpuid2 __user *cpuid_arg = argp;
1793 struct kvm_cpuid2 cpuid;
1794
1795 r = -EFAULT;
1796 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1797 goto out;
1798 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1799 cpuid_arg->entries);
1800 if (r)
1801 goto out;
1802 r = -EFAULT;
1803 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1804 goto out;
1805 r = 0;
1806 break;
1807 }
1808 case KVM_GET_MSRS:
1809 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1810 break;
1811 case KVM_SET_MSRS:
1812 r = msr_io(vcpu, argp, do_set_msr, 0);
1813 break;
1814 case KVM_TPR_ACCESS_REPORTING: {
1815 struct kvm_tpr_access_ctl tac;
1816
1817 r = -EFAULT;
1818 if (copy_from_user(&tac, argp, sizeof tac))
1819 goto out;
1820 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1821 if (r)
1822 goto out;
1823 r = -EFAULT;
1824 if (copy_to_user(argp, &tac, sizeof tac))
1825 goto out;
1826 r = 0;
1827 break;
1828 };
1829 case KVM_SET_VAPIC_ADDR: {
1830 struct kvm_vapic_addr va;
1831
1832 r = -EINVAL;
1833 if (!irqchip_in_kernel(vcpu->kvm))
1834 goto out;
1835 r = -EFAULT;
1836 if (copy_from_user(&va, argp, sizeof va))
1837 goto out;
1838 r = 0;
1839 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1840 break;
1841 }
1842 case KVM_X86_SETUP_MCE: {
1843 u64 mcg_cap;
1844
1845 r = -EFAULT;
1846 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1847 goto out;
1848 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1849 break;
1850 }
1851 case KVM_X86_SET_MCE: {
1852 struct kvm_x86_mce mce;
1853
1854 r = -EFAULT;
1855 if (copy_from_user(&mce, argp, sizeof mce))
1856 goto out;
1857 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1858 break;
1859 }
1860 default:
1861 r = -EINVAL;
1862 }
1863 out:
1864 kfree(lapic);
1865 return r;
1866 }
1867
1868 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1869 {
1870 int ret;
1871
1872 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1873 return -1;
1874 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1875 return ret;
1876 }
1877
1878 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1879 u32 kvm_nr_mmu_pages)
1880 {
1881 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1882 return -EINVAL;
1883
1884 down_write(&kvm->slots_lock);
1885 spin_lock(&kvm->mmu_lock);
1886
1887 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
1888 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1889
1890 spin_unlock(&kvm->mmu_lock);
1891 up_write(&kvm->slots_lock);
1892 return 0;
1893 }
1894
1895 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1896 {
1897 return kvm->arch.n_alloc_mmu_pages;
1898 }
1899
1900 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1901 {
1902 int i;
1903 struct kvm_mem_alias *alias;
1904
1905 for (i = 0; i < kvm->arch.naliases; ++i) {
1906 alias = &kvm->arch.aliases[i];
1907 if (gfn >= alias->base_gfn
1908 && gfn < alias->base_gfn + alias->npages)
1909 return alias->target_gfn + gfn - alias->base_gfn;
1910 }
1911 return gfn;
1912 }
1913
1914 /*
1915 * Set a new alias region. Aliases map a portion of physical memory into
1916 * another portion. This is useful for memory windows, for example the PC
1917 * VGA region.
1918 */
1919 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1920 struct kvm_memory_alias *alias)
1921 {
1922 int r, n;
1923 struct kvm_mem_alias *p;
1924
1925 r = -EINVAL;
1926 /* General sanity checks */
1927 if (alias->memory_size & (PAGE_SIZE - 1))
1928 goto out;
1929 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1930 goto out;
1931 if (alias->slot >= KVM_ALIAS_SLOTS)
1932 goto out;
1933 if (alias->guest_phys_addr + alias->memory_size
1934 < alias->guest_phys_addr)
1935 goto out;
1936 if (alias->target_phys_addr + alias->memory_size
1937 < alias->target_phys_addr)
1938 goto out;
1939
1940 down_write(&kvm->slots_lock);
1941 spin_lock(&kvm->mmu_lock);
1942
1943 p = &kvm->arch.aliases[alias->slot];
1944 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1945 p->npages = alias->memory_size >> PAGE_SHIFT;
1946 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1947
1948 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
1949 if (kvm->arch.aliases[n - 1].npages)
1950 break;
1951 kvm->arch.naliases = n;
1952
1953 spin_unlock(&kvm->mmu_lock);
1954 kvm_mmu_zap_all(kvm);
1955
1956 up_write(&kvm->slots_lock);
1957
1958 return 0;
1959
1960 out:
1961 return r;
1962 }
1963
1964 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1965 {
1966 int r;
1967
1968 r = 0;
1969 switch (chip->chip_id) {
1970 case KVM_IRQCHIP_PIC_MASTER:
1971 memcpy(&chip->chip.pic,
1972 &pic_irqchip(kvm)->pics[0],
1973 sizeof(struct kvm_pic_state));
1974 break;
1975 case KVM_IRQCHIP_PIC_SLAVE:
1976 memcpy(&chip->chip.pic,
1977 &pic_irqchip(kvm)->pics[1],
1978 sizeof(struct kvm_pic_state));
1979 break;
1980 case KVM_IRQCHIP_IOAPIC:
1981 memcpy(&chip->chip.ioapic,
1982 ioapic_irqchip(kvm),
1983 sizeof(struct kvm_ioapic_state));
1984 break;
1985 default:
1986 r = -EINVAL;
1987 break;
1988 }
1989 return r;
1990 }
1991
1992 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1993 {
1994 int r;
1995
1996 r = 0;
1997 switch (chip->chip_id) {
1998 case KVM_IRQCHIP_PIC_MASTER:
1999 spin_lock(&pic_irqchip(kvm)->lock);
2000 memcpy(&pic_irqchip(kvm)->pics[0],
2001 &chip->chip.pic,
2002 sizeof(struct kvm_pic_state));
2003 spin_unlock(&pic_irqchip(kvm)->lock);
2004 break;
2005 case KVM_IRQCHIP_PIC_SLAVE:
2006 spin_lock(&pic_irqchip(kvm)->lock);
2007 memcpy(&pic_irqchip(kvm)->pics[1],
2008 &chip->chip.pic,
2009 sizeof(struct kvm_pic_state));
2010 spin_unlock(&pic_irqchip(kvm)->lock);
2011 break;
2012 case KVM_IRQCHIP_IOAPIC:
2013 mutex_lock(&kvm->irq_lock);
2014 memcpy(ioapic_irqchip(kvm),
2015 &chip->chip.ioapic,
2016 sizeof(struct kvm_ioapic_state));
2017 mutex_unlock(&kvm->irq_lock);
2018 break;
2019 default:
2020 r = -EINVAL;
2021 break;
2022 }
2023 kvm_pic_update_irq(pic_irqchip(kvm));
2024 return r;
2025 }
2026
2027 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2028 {
2029 int r = 0;
2030
2031 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2032 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2033 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2034 return r;
2035 }
2036
2037 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2038 {
2039 int r = 0;
2040
2041 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2042 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2043 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
2044 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2045 return r;
2046 }
2047
2048 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2049 struct kvm_reinject_control *control)
2050 {
2051 if (!kvm->arch.vpit)
2052 return -ENXIO;
2053 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2054 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2055 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2056 return 0;
2057 }
2058
2059 /*
2060 * Get (and clear) the dirty memory log for a memory slot.
2061 */
2062 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2063 struct kvm_dirty_log *log)
2064 {
2065 int r;
2066 int n;
2067 struct kvm_memory_slot *memslot;
2068 int is_dirty = 0;
2069
2070 down_write(&kvm->slots_lock);
2071
2072 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2073 if (r)
2074 goto out;
2075
2076 /* If nothing is dirty, don't bother messing with page tables. */
2077 if (is_dirty) {
2078 spin_lock(&kvm->mmu_lock);
2079 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2080 spin_unlock(&kvm->mmu_lock);
2081 kvm_flush_remote_tlbs(kvm);
2082 memslot = &kvm->memslots[log->slot];
2083 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2084 memset(memslot->dirty_bitmap, 0, n);
2085 }
2086 r = 0;
2087 out:
2088 up_write(&kvm->slots_lock);
2089 return r;
2090 }
2091
2092 long kvm_arch_vm_ioctl(struct file *filp,
2093 unsigned int ioctl, unsigned long arg)
2094 {
2095 struct kvm *kvm = filp->private_data;
2096 void __user *argp = (void __user *)arg;
2097 int r = -EINVAL;
2098 /*
2099 * This union makes it completely explicit to gcc-3.x
2100 * that these two variables' stack usage should be
2101 * combined, not added together.
2102 */
2103 union {
2104 struct kvm_pit_state ps;
2105 struct kvm_memory_alias alias;
2106 struct kvm_pit_config pit_config;
2107 } u;
2108
2109 switch (ioctl) {
2110 case KVM_SET_TSS_ADDR:
2111 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2112 if (r < 0)
2113 goto out;
2114 break;
2115 case KVM_SET_MEMORY_REGION: {
2116 struct kvm_memory_region kvm_mem;
2117 struct kvm_userspace_memory_region kvm_userspace_mem;
2118
2119 r = -EFAULT;
2120 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2121 goto out;
2122 kvm_userspace_mem.slot = kvm_mem.slot;
2123 kvm_userspace_mem.flags = kvm_mem.flags;
2124 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2125 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2126 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2127 if (r)
2128 goto out;
2129 break;
2130 }
2131 case KVM_SET_NR_MMU_PAGES:
2132 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2133 if (r)
2134 goto out;
2135 break;
2136 case KVM_GET_NR_MMU_PAGES:
2137 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2138 break;
2139 case KVM_SET_MEMORY_ALIAS:
2140 r = -EFAULT;
2141 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2142 goto out;
2143 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2144 if (r)
2145 goto out;
2146 break;
2147 case KVM_CREATE_IRQCHIP:
2148 r = -ENOMEM;
2149 kvm->arch.vpic = kvm_create_pic(kvm);
2150 if (kvm->arch.vpic) {
2151 r = kvm_ioapic_init(kvm);
2152 if (r) {
2153 kfree(kvm->arch.vpic);
2154 kvm->arch.vpic = NULL;
2155 goto out;
2156 }
2157 } else
2158 goto out;
2159 r = kvm_setup_default_irq_routing(kvm);
2160 if (r) {
2161 kfree(kvm->arch.vpic);
2162 kfree(kvm->arch.vioapic);
2163 goto out;
2164 }
2165 break;
2166 case KVM_CREATE_PIT:
2167 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2168 goto create_pit;
2169 case KVM_CREATE_PIT2:
2170 r = -EFAULT;
2171 if (copy_from_user(&u.pit_config, argp,
2172 sizeof(struct kvm_pit_config)))
2173 goto out;
2174 create_pit:
2175 mutex_lock(&kvm->lock);
2176 r = -EEXIST;
2177 if (kvm->arch.vpit)
2178 goto create_pit_unlock;
2179 r = -ENOMEM;
2180 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2181 if (kvm->arch.vpit)
2182 r = 0;
2183 create_pit_unlock:
2184 mutex_unlock(&kvm->lock);
2185 break;
2186 case KVM_IRQ_LINE_STATUS:
2187 case KVM_IRQ_LINE: {
2188 struct kvm_irq_level irq_event;
2189
2190 r = -EFAULT;
2191 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2192 goto out;
2193 if (irqchip_in_kernel(kvm)) {
2194 __s32 status;
2195 mutex_lock(&kvm->irq_lock);
2196 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2197 irq_event.irq, irq_event.level);
2198 mutex_unlock(&kvm->irq_lock);
2199 if (ioctl == KVM_IRQ_LINE_STATUS) {
2200 irq_event.status = status;
2201 if (copy_to_user(argp, &irq_event,
2202 sizeof irq_event))
2203 goto out;
2204 }
2205 r = 0;
2206 }
2207 break;
2208 }
2209 case KVM_GET_IRQCHIP: {
2210 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2211 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2212
2213 r = -ENOMEM;
2214 if (!chip)
2215 goto out;
2216 r = -EFAULT;
2217 if (copy_from_user(chip, argp, sizeof *chip))
2218 goto get_irqchip_out;
2219 r = -ENXIO;
2220 if (!irqchip_in_kernel(kvm))
2221 goto get_irqchip_out;
2222 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2223 if (r)
2224 goto get_irqchip_out;
2225 r = -EFAULT;
2226 if (copy_to_user(argp, chip, sizeof *chip))
2227 goto get_irqchip_out;
2228 r = 0;
2229 get_irqchip_out:
2230 kfree(chip);
2231 if (r)
2232 goto out;
2233 break;
2234 }
2235 case KVM_SET_IRQCHIP: {
2236 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2237 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2238
2239 r = -ENOMEM;
2240 if (!chip)
2241 goto out;
2242 r = -EFAULT;
2243 if (copy_from_user(chip, argp, sizeof *chip))
2244 goto set_irqchip_out;
2245 r = -ENXIO;
2246 if (!irqchip_in_kernel(kvm))
2247 goto set_irqchip_out;
2248 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2249 if (r)
2250 goto set_irqchip_out;
2251 r = 0;
2252 set_irqchip_out:
2253 kfree(chip);
2254 if (r)
2255 goto out;
2256 break;
2257 }
2258 case KVM_GET_PIT: {
2259 r = -EFAULT;
2260 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2261 goto out;
2262 r = -ENXIO;
2263 if (!kvm->arch.vpit)
2264 goto out;
2265 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2266 if (r)
2267 goto out;
2268 r = -EFAULT;
2269 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2270 goto out;
2271 r = 0;
2272 break;
2273 }
2274 case KVM_SET_PIT: {
2275 r = -EFAULT;
2276 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2277 goto out;
2278 r = -ENXIO;
2279 if (!kvm->arch.vpit)
2280 goto out;
2281 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2282 if (r)
2283 goto out;
2284 r = 0;
2285 break;
2286 }
2287 case KVM_REINJECT_CONTROL: {
2288 struct kvm_reinject_control control;
2289 r = -EFAULT;
2290 if (copy_from_user(&control, argp, sizeof(control)))
2291 goto out;
2292 r = kvm_vm_ioctl_reinject(kvm, &control);
2293 if (r)
2294 goto out;
2295 r = 0;
2296 break;
2297 }
2298 default:
2299 ;
2300 }
2301 out:
2302 return r;
2303 }
2304
2305 static void kvm_init_msr_list(void)
2306 {
2307 u32 dummy[2];
2308 unsigned i, j;
2309
2310 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2311 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2312 continue;
2313 if (j < i)
2314 msrs_to_save[j] = msrs_to_save[i];
2315 j++;
2316 }
2317 num_msrs_to_save = j;
2318 }
2319
2320 /*
2321 * Only apic need an MMIO device hook, so shortcut now..
2322 */
2323 static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
2324 gpa_t addr, int len,
2325 int is_write)
2326 {
2327 struct kvm_io_device *dev;
2328
2329 if (vcpu->arch.apic) {
2330 dev = &vcpu->arch.apic->dev;
2331 if (kvm_iodevice_in_range(dev, addr, len, is_write))
2332 return dev;
2333 }
2334 return NULL;
2335 }
2336
2337
2338 static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
2339 gpa_t addr, int len,
2340 int is_write)
2341 {
2342 struct kvm_io_device *dev;
2343
2344 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
2345 if (dev == NULL)
2346 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2347 is_write);
2348 return dev;
2349 }
2350
2351 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2352 struct kvm_vcpu *vcpu)
2353 {
2354 void *data = val;
2355 int r = X86EMUL_CONTINUE;
2356
2357 while (bytes) {
2358 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2359 unsigned offset = addr & (PAGE_SIZE-1);
2360 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2361 int ret;
2362
2363 if (gpa == UNMAPPED_GVA) {
2364 r = X86EMUL_PROPAGATE_FAULT;
2365 goto out;
2366 }
2367 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2368 if (ret < 0) {
2369 r = X86EMUL_UNHANDLEABLE;
2370 goto out;
2371 }
2372
2373 bytes -= toread;
2374 data += toread;
2375 addr += toread;
2376 }
2377 out:
2378 return r;
2379 }
2380
2381 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2382 struct kvm_vcpu *vcpu)
2383 {
2384 void *data = val;
2385 int r = X86EMUL_CONTINUE;
2386
2387 while (bytes) {
2388 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2389 unsigned offset = addr & (PAGE_SIZE-1);
2390 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2391 int ret;
2392
2393 if (gpa == UNMAPPED_GVA) {
2394 r = X86EMUL_PROPAGATE_FAULT;
2395 goto out;
2396 }
2397 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2398 if (ret < 0) {
2399 r = X86EMUL_UNHANDLEABLE;
2400 goto out;
2401 }
2402
2403 bytes -= towrite;
2404 data += towrite;
2405 addr += towrite;
2406 }
2407 out:
2408 return r;
2409 }
2410
2411
2412 static int emulator_read_emulated(unsigned long addr,
2413 void *val,
2414 unsigned int bytes,
2415 struct kvm_vcpu *vcpu)
2416 {
2417 struct kvm_io_device *mmio_dev;
2418 gpa_t gpa;
2419
2420 if (vcpu->mmio_read_completed) {
2421 memcpy(val, vcpu->mmio_data, bytes);
2422 vcpu->mmio_read_completed = 0;
2423 return X86EMUL_CONTINUE;
2424 }
2425
2426 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2427
2428 /* For APIC access vmexit */
2429 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2430 goto mmio;
2431
2432 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2433 == X86EMUL_CONTINUE)
2434 return X86EMUL_CONTINUE;
2435 if (gpa == UNMAPPED_GVA)
2436 return X86EMUL_PROPAGATE_FAULT;
2437
2438 mmio:
2439 /*
2440 * Is this MMIO handled locally?
2441 */
2442 mutex_lock(&vcpu->kvm->lock);
2443 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
2444 mutex_unlock(&vcpu->kvm->lock);
2445 if (mmio_dev) {
2446 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
2447 return X86EMUL_CONTINUE;
2448 }
2449
2450 vcpu->mmio_needed = 1;
2451 vcpu->mmio_phys_addr = gpa;
2452 vcpu->mmio_size = bytes;
2453 vcpu->mmio_is_write = 0;
2454
2455 return X86EMUL_UNHANDLEABLE;
2456 }
2457
2458 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2459 const void *val, int bytes)
2460 {
2461 int ret;
2462
2463 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2464 if (ret < 0)
2465 return 0;
2466 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2467 return 1;
2468 }
2469
2470 static int emulator_write_emulated_onepage(unsigned long addr,
2471 const void *val,
2472 unsigned int bytes,
2473 struct kvm_vcpu *vcpu)
2474 {
2475 struct kvm_io_device *mmio_dev;
2476 gpa_t gpa;
2477
2478 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2479
2480 if (gpa == UNMAPPED_GVA) {
2481 kvm_inject_page_fault(vcpu, addr, 2);
2482 return X86EMUL_PROPAGATE_FAULT;
2483 }
2484
2485 /* For APIC access vmexit */
2486 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2487 goto mmio;
2488
2489 if (emulator_write_phys(vcpu, gpa, val, bytes))
2490 return X86EMUL_CONTINUE;
2491
2492 mmio:
2493 /*
2494 * Is this MMIO handled locally?
2495 */
2496 mutex_lock(&vcpu->kvm->lock);
2497 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
2498 mutex_unlock(&vcpu->kvm->lock);
2499 if (mmio_dev) {
2500 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
2501 return X86EMUL_CONTINUE;
2502 }
2503
2504 vcpu->mmio_needed = 1;
2505 vcpu->mmio_phys_addr = gpa;
2506 vcpu->mmio_size = bytes;
2507 vcpu->mmio_is_write = 1;
2508 memcpy(vcpu->mmio_data, val, bytes);
2509
2510 return X86EMUL_CONTINUE;
2511 }
2512
2513 int emulator_write_emulated(unsigned long addr,
2514 const void *val,
2515 unsigned int bytes,
2516 struct kvm_vcpu *vcpu)
2517 {
2518 /* Crossing a page boundary? */
2519 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2520 int rc, now;
2521
2522 now = -addr & ~PAGE_MASK;
2523 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2524 if (rc != X86EMUL_CONTINUE)
2525 return rc;
2526 addr += now;
2527 val += now;
2528 bytes -= now;
2529 }
2530 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2531 }
2532 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2533
2534 static int emulator_cmpxchg_emulated(unsigned long addr,
2535 const void *old,
2536 const void *new,
2537 unsigned int bytes,
2538 struct kvm_vcpu *vcpu)
2539 {
2540 static int reported;
2541
2542 if (!reported) {
2543 reported = 1;
2544 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2545 }
2546 #ifndef CONFIG_X86_64
2547 /* guests cmpxchg8b have to be emulated atomically */
2548 if (bytes == 8) {
2549 gpa_t gpa;
2550 struct page *page;
2551 char *kaddr;
2552 u64 val;
2553
2554 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2555
2556 if (gpa == UNMAPPED_GVA ||
2557 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2558 goto emul_write;
2559
2560 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2561 goto emul_write;
2562
2563 val = *(u64 *)new;
2564
2565 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2566
2567 kaddr = kmap_atomic(page, KM_USER0);
2568 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2569 kunmap_atomic(kaddr, KM_USER0);
2570 kvm_release_page_dirty(page);
2571 }
2572 emul_write:
2573 #endif
2574
2575 return emulator_write_emulated(addr, new, bytes, vcpu);
2576 }
2577
2578 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2579 {
2580 return kvm_x86_ops->get_segment_base(vcpu, seg);
2581 }
2582
2583 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2584 {
2585 kvm_mmu_invlpg(vcpu, address);
2586 return X86EMUL_CONTINUE;
2587 }
2588
2589 int emulate_clts(struct kvm_vcpu *vcpu)
2590 {
2591 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2592 return X86EMUL_CONTINUE;
2593 }
2594
2595 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2596 {
2597 struct kvm_vcpu *vcpu = ctxt->vcpu;
2598
2599 switch (dr) {
2600 case 0 ... 3:
2601 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2602 return X86EMUL_CONTINUE;
2603 default:
2604 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2605 return X86EMUL_UNHANDLEABLE;
2606 }
2607 }
2608
2609 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2610 {
2611 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2612 int exception;
2613
2614 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2615 if (exception) {
2616 /* FIXME: better handling */
2617 return X86EMUL_UNHANDLEABLE;
2618 }
2619 return X86EMUL_CONTINUE;
2620 }
2621
2622 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2623 {
2624 u8 opcodes[4];
2625 unsigned long rip = kvm_rip_read(vcpu);
2626 unsigned long rip_linear;
2627
2628 if (!printk_ratelimit())
2629 return;
2630
2631 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2632
2633 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2634
2635 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2636 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2637 }
2638 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2639
2640 static struct x86_emulate_ops emulate_ops = {
2641 .read_std = kvm_read_guest_virt,
2642 .read_emulated = emulator_read_emulated,
2643 .write_emulated = emulator_write_emulated,
2644 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2645 };
2646
2647 static void cache_all_regs(struct kvm_vcpu *vcpu)
2648 {
2649 kvm_register_read(vcpu, VCPU_REGS_RAX);
2650 kvm_register_read(vcpu, VCPU_REGS_RSP);
2651 kvm_register_read(vcpu, VCPU_REGS_RIP);
2652 vcpu->arch.regs_dirty = ~0;
2653 }
2654
2655 int emulate_instruction(struct kvm_vcpu *vcpu,
2656 struct kvm_run *run,
2657 unsigned long cr2,
2658 u16 error_code,
2659 int emulation_type)
2660 {
2661 int r, shadow_mask;
2662 struct decode_cache *c;
2663
2664 kvm_clear_exception_queue(vcpu);
2665 vcpu->arch.mmio_fault_cr2 = cr2;
2666 /*
2667 * TODO: fix x86_emulate.c to use guest_read/write_register
2668 * instead of direct ->regs accesses, can save hundred cycles
2669 * on Intel for instructions that don't read/change RSP, for
2670 * for example.
2671 */
2672 cache_all_regs(vcpu);
2673
2674 vcpu->mmio_is_write = 0;
2675 vcpu->arch.pio.string = 0;
2676
2677 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
2678 int cs_db, cs_l;
2679 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2680
2681 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2682 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2683 vcpu->arch.emulate_ctxt.mode =
2684 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
2685 ? X86EMUL_MODE_REAL : cs_l
2686 ? X86EMUL_MODE_PROT64 : cs_db
2687 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2688
2689 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2690
2691 /* Only allow emulation of specific instructions on #UD
2692 * (namely VMMCALL, sysenter, sysexit, syscall)*/
2693 c = &vcpu->arch.emulate_ctxt.decode;
2694 if (emulation_type & EMULTYPE_TRAP_UD) {
2695 if (!c->twobyte)
2696 return EMULATE_FAIL;
2697 switch (c->b) {
2698 case 0x01: /* VMMCALL */
2699 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2700 return EMULATE_FAIL;
2701 break;
2702 case 0x34: /* sysenter */
2703 case 0x35: /* sysexit */
2704 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2705 return EMULATE_FAIL;
2706 break;
2707 case 0x05: /* syscall */
2708 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2709 return EMULATE_FAIL;
2710 break;
2711 default:
2712 return EMULATE_FAIL;
2713 }
2714
2715 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2716 return EMULATE_FAIL;
2717 }
2718
2719 ++vcpu->stat.insn_emulation;
2720 if (r) {
2721 ++vcpu->stat.insn_emulation_fail;
2722 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2723 return EMULATE_DONE;
2724 return EMULATE_FAIL;
2725 }
2726 }
2727
2728 if (emulation_type & EMULTYPE_SKIP) {
2729 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2730 return EMULATE_DONE;
2731 }
2732
2733 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2734 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2735
2736 if (r == 0)
2737 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
2738
2739 if (vcpu->arch.pio.string)
2740 return EMULATE_DO_MMIO;
2741
2742 if ((r || vcpu->mmio_is_write) && run) {
2743 run->exit_reason = KVM_EXIT_MMIO;
2744 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2745 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2746 run->mmio.len = vcpu->mmio_size;
2747 run->mmio.is_write = vcpu->mmio_is_write;
2748 }
2749
2750 if (r) {
2751 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2752 return EMULATE_DONE;
2753 if (!vcpu->mmio_needed) {
2754 kvm_report_emulation_failure(vcpu, "mmio");
2755 return EMULATE_FAIL;
2756 }
2757 return EMULATE_DO_MMIO;
2758 }
2759
2760 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
2761
2762 if (vcpu->mmio_is_write) {
2763 vcpu->mmio_needed = 0;
2764 return EMULATE_DO_MMIO;
2765 }
2766
2767 return EMULATE_DONE;
2768 }
2769 EXPORT_SYMBOL_GPL(emulate_instruction);
2770
2771 static int pio_copy_data(struct kvm_vcpu *vcpu)
2772 {
2773 void *p = vcpu->arch.pio_data;
2774 gva_t q = vcpu->arch.pio.guest_gva;
2775 unsigned bytes;
2776 int ret;
2777
2778 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2779 if (vcpu->arch.pio.in)
2780 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
2781 else
2782 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2783 return ret;
2784 }
2785
2786 int complete_pio(struct kvm_vcpu *vcpu)
2787 {
2788 struct kvm_pio_request *io = &vcpu->arch.pio;
2789 long delta;
2790 int r;
2791 unsigned long val;
2792
2793 if (!io->string) {
2794 if (io->in) {
2795 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2796 memcpy(&val, vcpu->arch.pio_data, io->size);
2797 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2798 }
2799 } else {
2800 if (io->in) {
2801 r = pio_copy_data(vcpu);
2802 if (r)
2803 return r;
2804 }
2805
2806 delta = 1;
2807 if (io->rep) {
2808 delta *= io->cur_count;
2809 /*
2810 * The size of the register should really depend on
2811 * current address size.
2812 */
2813 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2814 val -= delta;
2815 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
2816 }
2817 if (io->down)
2818 delta = -delta;
2819 delta *= io->size;
2820 if (io->in) {
2821 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2822 val += delta;
2823 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2824 } else {
2825 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2826 val += delta;
2827 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2828 }
2829 }
2830
2831 io->count -= io->cur_count;
2832 io->cur_count = 0;
2833
2834 return 0;
2835 }
2836
2837 static void kernel_pio(struct kvm_io_device *pio_dev,
2838 struct kvm_vcpu *vcpu,
2839 void *pd)
2840 {
2841 /* TODO: String I/O for in kernel device */
2842
2843 if (vcpu->arch.pio.in)
2844 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2845 vcpu->arch.pio.size,
2846 pd);
2847 else
2848 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2849 vcpu->arch.pio.size,
2850 pd);
2851 }
2852
2853 static void pio_string_write(struct kvm_io_device *pio_dev,
2854 struct kvm_vcpu *vcpu)
2855 {
2856 struct kvm_pio_request *io = &vcpu->arch.pio;
2857 void *pd = vcpu->arch.pio_data;
2858 int i;
2859
2860 for (i = 0; i < io->cur_count; i++) {
2861 kvm_iodevice_write(pio_dev, io->port,
2862 io->size,
2863 pd);
2864 pd += io->size;
2865 }
2866 }
2867
2868 static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
2869 gpa_t addr, int len,
2870 int is_write)
2871 {
2872 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
2873 }
2874
2875 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2876 int size, unsigned port)
2877 {
2878 struct kvm_io_device *pio_dev;
2879 unsigned long val;
2880
2881 vcpu->run->exit_reason = KVM_EXIT_IO;
2882 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2883 vcpu->run->io.size = vcpu->arch.pio.size = size;
2884 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2885 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2886 vcpu->run->io.port = vcpu->arch.pio.port = port;
2887 vcpu->arch.pio.in = in;
2888 vcpu->arch.pio.string = 0;
2889 vcpu->arch.pio.down = 0;
2890 vcpu->arch.pio.rep = 0;
2891
2892 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2893 size, 1);
2894
2895 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2896 memcpy(vcpu->arch.pio_data, &val, 4);
2897
2898 mutex_lock(&vcpu->kvm->lock);
2899 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
2900 mutex_unlock(&vcpu->kvm->lock);
2901 if (pio_dev) {
2902 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
2903 complete_pio(vcpu);
2904 return 1;
2905 }
2906 return 0;
2907 }
2908 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2909
2910 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2911 int size, unsigned long count, int down,
2912 gva_t address, int rep, unsigned port)
2913 {
2914 unsigned now, in_page;
2915 int ret = 0;
2916 struct kvm_io_device *pio_dev;
2917
2918 vcpu->run->exit_reason = KVM_EXIT_IO;
2919 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2920 vcpu->run->io.size = vcpu->arch.pio.size = size;
2921 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2922 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2923 vcpu->run->io.port = vcpu->arch.pio.port = port;
2924 vcpu->arch.pio.in = in;
2925 vcpu->arch.pio.string = 1;
2926 vcpu->arch.pio.down = down;
2927 vcpu->arch.pio.rep = rep;
2928
2929 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2930 size, count);
2931
2932 if (!count) {
2933 kvm_x86_ops->skip_emulated_instruction(vcpu);
2934 return 1;
2935 }
2936
2937 if (!down)
2938 in_page = PAGE_SIZE - offset_in_page(address);
2939 else
2940 in_page = offset_in_page(address) + size;
2941 now = min(count, (unsigned long)in_page / size);
2942 if (!now)
2943 now = 1;
2944 if (down) {
2945 /*
2946 * String I/O in reverse. Yuck. Kill the guest, fix later.
2947 */
2948 pr_unimpl(vcpu, "guest string pio down\n");
2949 kvm_inject_gp(vcpu, 0);
2950 return 1;
2951 }
2952 vcpu->run->io.count = now;
2953 vcpu->arch.pio.cur_count = now;
2954
2955 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
2956 kvm_x86_ops->skip_emulated_instruction(vcpu);
2957
2958 vcpu->arch.pio.guest_gva = address;
2959
2960 mutex_lock(&vcpu->kvm->lock);
2961 pio_dev = vcpu_find_pio_dev(vcpu, port,
2962 vcpu->arch.pio.cur_count,
2963 !vcpu->arch.pio.in);
2964 mutex_unlock(&vcpu->kvm->lock);
2965
2966 if (!vcpu->arch.pio.in) {
2967 /* string PIO write */
2968 ret = pio_copy_data(vcpu);
2969 if (ret == X86EMUL_PROPAGATE_FAULT) {
2970 kvm_inject_gp(vcpu, 0);
2971 return 1;
2972 }
2973 if (ret == 0 && pio_dev) {
2974 pio_string_write(pio_dev, vcpu);
2975 complete_pio(vcpu);
2976 if (vcpu->arch.pio.count == 0)
2977 ret = 1;
2978 }
2979 } else if (pio_dev)
2980 pr_unimpl(vcpu, "no string pio read support yet, "
2981 "port %x size %d count %ld\n",
2982 port, size, count);
2983
2984 return ret;
2985 }
2986 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2987
2988 static void bounce_off(void *info)
2989 {
2990 /* nothing */
2991 }
2992
2993 static unsigned int ref_freq;
2994 static unsigned long tsc_khz_ref;
2995
2996 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2997 void *data)
2998 {
2999 struct cpufreq_freqs *freq = data;
3000 struct kvm *kvm;
3001 struct kvm_vcpu *vcpu;
3002 int i, send_ipi = 0;
3003
3004 if (!ref_freq)
3005 ref_freq = freq->old;
3006
3007 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3008 return 0;
3009 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3010 return 0;
3011 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3012
3013 spin_lock(&kvm_lock);
3014 list_for_each_entry(kvm, &vm_list, vm_list) {
3015 kvm_for_each_vcpu(i, vcpu, kvm) {
3016 if (vcpu->cpu != freq->cpu)
3017 continue;
3018 if (!kvm_request_guest_time_update(vcpu))
3019 continue;
3020 if (vcpu->cpu != smp_processor_id())
3021 send_ipi++;
3022 }
3023 }
3024 spin_unlock(&kvm_lock);
3025
3026 if (freq->old < freq->new && send_ipi) {
3027 /*
3028 * We upscale the frequency. Must make the guest
3029 * doesn't see old kvmclock values while running with
3030 * the new frequency, otherwise we risk the guest sees
3031 * time go backwards.
3032 *
3033 * In case we update the frequency for another cpu
3034 * (which might be in guest context) send an interrupt
3035 * to kick the cpu out of guest context. Next time
3036 * guest context is entered kvmclock will be updated,
3037 * so the guest will not see stale values.
3038 */
3039 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3040 }
3041 return 0;
3042 }
3043
3044 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3045 .notifier_call = kvmclock_cpufreq_notifier
3046 };
3047
3048 int kvm_arch_init(void *opaque)
3049 {
3050 int r, cpu;
3051 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3052
3053 if (kvm_x86_ops) {
3054 printk(KERN_ERR "kvm: already loaded the other module\n");
3055 r = -EEXIST;
3056 goto out;
3057 }
3058
3059 if (!ops->cpu_has_kvm_support()) {
3060 printk(KERN_ERR "kvm: no hardware support\n");
3061 r = -EOPNOTSUPP;
3062 goto out;
3063 }
3064 if (ops->disabled_by_bios()) {
3065 printk(KERN_ERR "kvm: disabled by bios\n");
3066 r = -EOPNOTSUPP;
3067 goto out;
3068 }
3069
3070 r = kvm_mmu_module_init();
3071 if (r)
3072 goto out;
3073
3074 kvm_init_msr_list();
3075
3076 kvm_x86_ops = ops;
3077 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3078 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3079 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3080 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3081
3082 for_each_possible_cpu(cpu)
3083 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3084 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3085 tsc_khz_ref = tsc_khz;
3086 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3087 CPUFREQ_TRANSITION_NOTIFIER);
3088 }
3089
3090 return 0;
3091
3092 out:
3093 return r;
3094 }
3095
3096 void kvm_arch_exit(void)
3097 {
3098 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3099 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3100 CPUFREQ_TRANSITION_NOTIFIER);
3101 kvm_x86_ops = NULL;
3102 kvm_mmu_module_exit();
3103 }
3104
3105 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3106 {
3107 ++vcpu->stat.halt_exits;
3108 if (irqchip_in_kernel(vcpu->kvm)) {
3109 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3110 return 1;
3111 } else {
3112 vcpu->run->exit_reason = KVM_EXIT_HLT;
3113 return 0;
3114 }
3115 }
3116 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3117
3118 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3119 unsigned long a1)
3120 {
3121 if (is_long_mode(vcpu))
3122 return a0;
3123 else
3124 return a0 | ((gpa_t)a1 << 32);
3125 }
3126
3127 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3128 {
3129 unsigned long nr, a0, a1, a2, a3, ret;
3130 int r = 1;
3131
3132 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3133 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3134 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3135 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3136 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3137
3138 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3139
3140 if (!is_long_mode(vcpu)) {
3141 nr &= 0xFFFFFFFF;
3142 a0 &= 0xFFFFFFFF;
3143 a1 &= 0xFFFFFFFF;
3144 a2 &= 0xFFFFFFFF;
3145 a3 &= 0xFFFFFFFF;
3146 }
3147
3148 switch (nr) {
3149 case KVM_HC_VAPIC_POLL_IRQ:
3150 ret = 0;
3151 break;
3152 case KVM_HC_MMU_OP:
3153 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3154 break;
3155 default:
3156 ret = -KVM_ENOSYS;
3157 break;
3158 }
3159 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3160 ++vcpu->stat.hypercalls;
3161 return r;
3162 }
3163 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3164
3165 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3166 {
3167 char instruction[3];
3168 int ret = 0;
3169 unsigned long rip = kvm_rip_read(vcpu);
3170
3171
3172 /*
3173 * Blow out the MMU to ensure that no other VCPU has an active mapping
3174 * to ensure that the updated hypercall appears atomically across all
3175 * VCPUs.
3176 */
3177 kvm_mmu_zap_all(vcpu->kvm);
3178
3179 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3180 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3181 != X86EMUL_CONTINUE)
3182 ret = -EFAULT;
3183
3184 return ret;
3185 }
3186
3187 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3188 {
3189 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3190 }
3191
3192 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3193 {
3194 struct descriptor_table dt = { limit, base };
3195
3196 kvm_x86_ops->set_gdt(vcpu, &dt);
3197 }
3198
3199 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3200 {
3201 struct descriptor_table dt = { limit, base };
3202
3203 kvm_x86_ops->set_idt(vcpu, &dt);
3204 }
3205
3206 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3207 unsigned long *rflags)
3208 {
3209 kvm_lmsw(vcpu, msw);
3210 *rflags = kvm_x86_ops->get_rflags(vcpu);
3211 }
3212
3213 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3214 {
3215 unsigned long value;
3216
3217 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3218 switch (cr) {
3219 case 0:
3220 value = vcpu->arch.cr0;
3221 break;
3222 case 2:
3223 value = vcpu->arch.cr2;
3224 break;
3225 case 3:
3226 value = vcpu->arch.cr3;
3227 break;
3228 case 4:
3229 value = vcpu->arch.cr4;
3230 break;
3231 case 8:
3232 value = kvm_get_cr8(vcpu);
3233 break;
3234 default:
3235 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3236 return 0;
3237 }
3238
3239 return value;
3240 }
3241
3242 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3243 unsigned long *rflags)
3244 {
3245 switch (cr) {
3246 case 0:
3247 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3248 *rflags = kvm_x86_ops->get_rflags(vcpu);
3249 break;
3250 case 2:
3251 vcpu->arch.cr2 = val;
3252 break;
3253 case 3:
3254 kvm_set_cr3(vcpu, val);
3255 break;
3256 case 4:
3257 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3258 break;
3259 case 8:
3260 kvm_set_cr8(vcpu, val & 0xfUL);
3261 break;
3262 default:
3263 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3264 }
3265 }
3266
3267 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3268 {
3269 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3270 int j, nent = vcpu->arch.cpuid_nent;
3271
3272 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3273 /* when no next entry is found, the current entry[i] is reselected */
3274 for (j = i + 1; ; j = (j + 1) % nent) {
3275 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3276 if (ej->function == e->function) {
3277 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3278 return j;
3279 }
3280 }
3281 return 0; /* silence gcc, even though control never reaches here */
3282 }
3283
3284 /* find an entry with matching function, matching index (if needed), and that
3285 * should be read next (if it's stateful) */
3286 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3287 u32 function, u32 index)
3288 {
3289 if (e->function != function)
3290 return 0;
3291 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3292 return 0;
3293 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3294 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3295 return 0;
3296 return 1;
3297 }
3298
3299 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3300 u32 function, u32 index)
3301 {
3302 int i;
3303 struct kvm_cpuid_entry2 *best = NULL;
3304
3305 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3306 struct kvm_cpuid_entry2 *e;
3307
3308 e = &vcpu->arch.cpuid_entries[i];
3309 if (is_matching_cpuid_entry(e, function, index)) {
3310 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3311 move_to_next_stateful_cpuid_entry(vcpu, i);
3312 best = e;
3313 break;
3314 }
3315 /*
3316 * Both basic or both extended?
3317 */
3318 if (((e->function ^ function) & 0x80000000) == 0)
3319 if (!best || e->function > best->function)
3320 best = e;
3321 }
3322 return best;
3323 }
3324
3325 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3326 {
3327 struct kvm_cpuid_entry2 *best;
3328
3329 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3330 if (best)
3331 return best->eax & 0xff;
3332 return 36;
3333 }
3334
3335 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3336 {
3337 u32 function, index;
3338 struct kvm_cpuid_entry2 *best;
3339
3340 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3341 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3342 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3343 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3344 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3345 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3346 best = kvm_find_cpuid_entry(vcpu, function, index);
3347 if (best) {
3348 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3349 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3350 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3351 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3352 }
3353 kvm_x86_ops->skip_emulated_instruction(vcpu);
3354 trace_kvm_cpuid(function,
3355 kvm_register_read(vcpu, VCPU_REGS_RAX),
3356 kvm_register_read(vcpu, VCPU_REGS_RBX),
3357 kvm_register_read(vcpu, VCPU_REGS_RCX),
3358 kvm_register_read(vcpu, VCPU_REGS_RDX));
3359 }
3360 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3361
3362 /*
3363 * Check if userspace requested an interrupt window, and that the
3364 * interrupt window is open.
3365 *
3366 * No need to exit to userspace if we already have an interrupt queued.
3367 */
3368 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3369 struct kvm_run *kvm_run)
3370 {
3371 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3372 kvm_run->request_interrupt_window &&
3373 kvm_arch_interrupt_allowed(vcpu));
3374 }
3375
3376 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3377 struct kvm_run *kvm_run)
3378 {
3379 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3380 kvm_run->cr8 = kvm_get_cr8(vcpu);
3381 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3382 if (irqchip_in_kernel(vcpu->kvm))
3383 kvm_run->ready_for_interrupt_injection = 1;
3384 else
3385 kvm_run->ready_for_interrupt_injection =
3386 kvm_arch_interrupt_allowed(vcpu) &&
3387 !kvm_cpu_has_interrupt(vcpu) &&
3388 !kvm_event_needs_reinjection(vcpu);
3389 }
3390
3391 static void vapic_enter(struct kvm_vcpu *vcpu)
3392 {
3393 struct kvm_lapic *apic = vcpu->arch.apic;
3394 struct page *page;
3395
3396 if (!apic || !apic->vapic_addr)
3397 return;
3398
3399 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3400
3401 vcpu->arch.apic->vapic_page = page;
3402 }
3403
3404 static void vapic_exit(struct kvm_vcpu *vcpu)
3405 {
3406 struct kvm_lapic *apic = vcpu->arch.apic;
3407
3408 if (!apic || !apic->vapic_addr)
3409 return;
3410
3411 down_read(&vcpu->kvm->slots_lock);
3412 kvm_release_page_dirty(apic->vapic_page);
3413 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3414 up_read(&vcpu->kvm->slots_lock);
3415 }
3416
3417 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3418 {
3419 int max_irr, tpr;
3420
3421 if (!kvm_x86_ops->update_cr8_intercept)
3422 return;
3423
3424 if (!vcpu->arch.apic->vapic_addr)
3425 max_irr = kvm_lapic_find_highest_irr(vcpu);
3426 else
3427 max_irr = -1;
3428
3429 if (max_irr != -1)
3430 max_irr >>= 4;
3431
3432 tpr = kvm_lapic_get_cr8(vcpu);
3433
3434 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3435 }
3436
3437 static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3438 {
3439 /* try to reinject previous events if any */
3440 if (vcpu->arch.nmi_injected) {
3441 kvm_x86_ops->set_nmi(vcpu);
3442 return;
3443 }
3444
3445 if (vcpu->arch.interrupt.pending) {
3446 kvm_x86_ops->set_irq(vcpu);
3447 return;
3448 }
3449
3450 /* try to inject new event if pending */
3451 if (vcpu->arch.nmi_pending) {
3452 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3453 vcpu->arch.nmi_pending = false;
3454 vcpu->arch.nmi_injected = true;
3455 kvm_x86_ops->set_nmi(vcpu);
3456 }
3457 } else if (kvm_cpu_has_interrupt(vcpu)) {
3458 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3459 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3460 false);
3461 kvm_x86_ops->set_irq(vcpu);
3462 }
3463 }
3464 }
3465
3466 static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3467 {
3468 int r;
3469 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3470 kvm_run->request_interrupt_window;
3471
3472 if (vcpu->requests)
3473 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3474 kvm_mmu_unload(vcpu);
3475
3476 r = kvm_mmu_reload(vcpu);
3477 if (unlikely(r))
3478 goto out;
3479
3480 if (vcpu->requests) {
3481 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3482 __kvm_migrate_timers(vcpu);
3483 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3484 kvm_write_guest_time(vcpu);
3485 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3486 kvm_mmu_sync_roots(vcpu);
3487 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3488 kvm_x86_ops->tlb_flush(vcpu);
3489 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3490 &vcpu->requests)) {
3491 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3492 r = 0;
3493 goto out;
3494 }
3495 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3496 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3497 r = 0;
3498 goto out;
3499 }
3500 }
3501
3502 preempt_disable();
3503
3504 kvm_x86_ops->prepare_guest_switch(vcpu);
3505 kvm_load_guest_fpu(vcpu);
3506
3507 local_irq_disable();
3508
3509 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3510 smp_mb__after_clear_bit();
3511
3512 if (vcpu->requests || need_resched() || signal_pending(current)) {
3513 local_irq_enable();
3514 preempt_enable();
3515 r = 1;
3516 goto out;
3517 }
3518
3519 if (vcpu->arch.exception.pending)
3520 __queue_exception(vcpu);
3521 else
3522 inject_pending_irq(vcpu, kvm_run);
3523
3524 /* enable NMI/IRQ window open exits if needed */
3525 if (vcpu->arch.nmi_pending)
3526 kvm_x86_ops->enable_nmi_window(vcpu);
3527 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3528 kvm_x86_ops->enable_irq_window(vcpu);
3529
3530 if (kvm_lapic_enabled(vcpu)) {
3531 update_cr8_intercept(vcpu);
3532 kvm_lapic_sync_to_vapic(vcpu);
3533 }
3534
3535 up_read(&vcpu->kvm->slots_lock);
3536
3537 kvm_guest_enter();
3538
3539 get_debugreg(vcpu->arch.host_dr6, 6);
3540 get_debugreg(vcpu->arch.host_dr7, 7);
3541 if (unlikely(vcpu->arch.switch_db_regs)) {
3542 get_debugreg(vcpu->arch.host_db[0], 0);
3543 get_debugreg(vcpu->arch.host_db[1], 1);
3544 get_debugreg(vcpu->arch.host_db[2], 2);
3545 get_debugreg(vcpu->arch.host_db[3], 3);
3546
3547 set_debugreg(0, 7);
3548 set_debugreg(vcpu->arch.eff_db[0], 0);
3549 set_debugreg(vcpu->arch.eff_db[1], 1);
3550 set_debugreg(vcpu->arch.eff_db[2], 2);
3551 set_debugreg(vcpu->arch.eff_db[3], 3);
3552 }
3553
3554 trace_kvm_entry(vcpu->vcpu_id);
3555 kvm_x86_ops->run(vcpu, kvm_run);
3556
3557 if (unlikely(vcpu->arch.switch_db_regs)) {
3558 set_debugreg(0, 7);
3559 set_debugreg(vcpu->arch.host_db[0], 0);
3560 set_debugreg(vcpu->arch.host_db[1], 1);
3561 set_debugreg(vcpu->arch.host_db[2], 2);
3562 set_debugreg(vcpu->arch.host_db[3], 3);
3563 }
3564 set_debugreg(vcpu->arch.host_dr6, 6);
3565 set_debugreg(vcpu->arch.host_dr7, 7);
3566
3567 set_bit(KVM_REQ_KICK, &vcpu->requests);
3568 local_irq_enable();
3569
3570 ++vcpu->stat.exits;
3571
3572 /*
3573 * We must have an instruction between local_irq_enable() and
3574 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3575 * the interrupt shadow. The stat.exits increment will do nicely.
3576 * But we need to prevent reordering, hence this barrier():
3577 */
3578 barrier();
3579
3580 kvm_guest_exit();
3581
3582 preempt_enable();
3583
3584 down_read(&vcpu->kvm->slots_lock);
3585
3586 /*
3587 * Profile KVM exit RIPs:
3588 */
3589 if (unlikely(prof_on == KVM_PROFILING)) {
3590 unsigned long rip = kvm_rip_read(vcpu);
3591 profile_hit(KVM_PROFILING, (void *)rip);
3592 }
3593
3594
3595 kvm_lapic_sync_from_vapic(vcpu);
3596
3597 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
3598 out:
3599 return r;
3600 }
3601
3602
3603 static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3604 {
3605 int r;
3606
3607 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3608 pr_debug("vcpu %d received sipi with vector # %x\n",
3609 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3610 kvm_lapic_reset(vcpu);
3611 r = kvm_arch_vcpu_reset(vcpu);
3612 if (r)
3613 return r;
3614 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3615 }
3616
3617 down_read(&vcpu->kvm->slots_lock);
3618 vapic_enter(vcpu);
3619
3620 r = 1;
3621 while (r > 0) {
3622 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3623 r = vcpu_enter_guest(vcpu, kvm_run);
3624 else {
3625 up_read(&vcpu->kvm->slots_lock);
3626 kvm_vcpu_block(vcpu);
3627 down_read(&vcpu->kvm->slots_lock);
3628 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3629 {
3630 switch(vcpu->arch.mp_state) {
3631 case KVM_MP_STATE_HALTED:
3632 vcpu->arch.mp_state =
3633 KVM_MP_STATE_RUNNABLE;
3634 case KVM_MP_STATE_RUNNABLE:
3635 break;
3636 case KVM_MP_STATE_SIPI_RECEIVED:
3637 default:
3638 r = -EINTR;
3639 break;
3640 }
3641 }
3642 }
3643
3644 if (r <= 0)
3645 break;
3646
3647 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3648 if (kvm_cpu_has_pending_timer(vcpu))
3649 kvm_inject_pending_timer_irqs(vcpu);
3650
3651 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3652 r = -EINTR;
3653 kvm_run->exit_reason = KVM_EXIT_INTR;
3654 ++vcpu->stat.request_irq_exits;
3655 }
3656 if (signal_pending(current)) {
3657 r = -EINTR;
3658 kvm_run->exit_reason = KVM_EXIT_INTR;
3659 ++vcpu->stat.signal_exits;
3660 }
3661 if (need_resched()) {
3662 up_read(&vcpu->kvm->slots_lock);
3663 kvm_resched(vcpu);
3664 down_read(&vcpu->kvm->slots_lock);
3665 }
3666 }
3667
3668 up_read(&vcpu->kvm->slots_lock);
3669 post_kvm_run_save(vcpu, kvm_run);
3670
3671 vapic_exit(vcpu);
3672
3673 return r;
3674 }
3675
3676 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3677 {
3678 int r;
3679 sigset_t sigsaved;
3680
3681 vcpu_load(vcpu);
3682
3683 if (vcpu->sigset_active)
3684 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3685
3686 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
3687 kvm_vcpu_block(vcpu);
3688 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
3689 r = -EAGAIN;
3690 goto out;
3691 }
3692
3693 /* re-sync apic's tpr */
3694 if (!irqchip_in_kernel(vcpu->kvm))
3695 kvm_set_cr8(vcpu, kvm_run->cr8);
3696
3697 if (vcpu->arch.pio.cur_count) {
3698 r = complete_pio(vcpu);
3699 if (r)
3700 goto out;
3701 }
3702 #if CONFIG_HAS_IOMEM
3703 if (vcpu->mmio_needed) {
3704 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3705 vcpu->mmio_read_completed = 1;
3706 vcpu->mmio_needed = 0;
3707
3708 down_read(&vcpu->kvm->slots_lock);
3709 r = emulate_instruction(vcpu, kvm_run,
3710 vcpu->arch.mmio_fault_cr2, 0,
3711 EMULTYPE_NO_DECODE);
3712 up_read(&vcpu->kvm->slots_lock);
3713 if (r == EMULATE_DO_MMIO) {
3714 /*
3715 * Read-modify-write. Back to userspace.
3716 */
3717 r = 0;
3718 goto out;
3719 }
3720 }
3721 #endif
3722 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3723 kvm_register_write(vcpu, VCPU_REGS_RAX,
3724 kvm_run->hypercall.ret);
3725
3726 r = __vcpu_run(vcpu, kvm_run);
3727
3728 out:
3729 if (vcpu->sigset_active)
3730 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3731
3732 vcpu_put(vcpu);
3733 return r;
3734 }
3735
3736 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3737 {
3738 vcpu_load(vcpu);
3739
3740 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3741 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3742 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3743 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3744 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3745 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3746 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3747 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3748 #ifdef CONFIG_X86_64
3749 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3750 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3751 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3752 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3753 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3754 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3755 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3756 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
3757 #endif
3758
3759 regs->rip = kvm_rip_read(vcpu);
3760 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3761
3762 /*
3763 * Don't leak debug flags in case they were set for guest debugging
3764 */
3765 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3766 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3767
3768 vcpu_put(vcpu);
3769
3770 return 0;
3771 }
3772
3773 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3774 {
3775 vcpu_load(vcpu);
3776
3777 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3778 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3779 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3780 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3781 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3782 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3783 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3784 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
3785 #ifdef CONFIG_X86_64
3786 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3787 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3788 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3789 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3790 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3791 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3792 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3793 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3794
3795 #endif
3796
3797 kvm_rip_write(vcpu, regs->rip);
3798 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3799
3800
3801 vcpu->arch.exception.pending = false;
3802
3803 vcpu_put(vcpu);
3804
3805 return 0;
3806 }
3807
3808 void kvm_get_segment(struct kvm_vcpu *vcpu,
3809 struct kvm_segment *var, int seg)
3810 {
3811 kvm_x86_ops->get_segment(vcpu, var, seg);
3812 }
3813
3814 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3815 {
3816 struct kvm_segment cs;
3817
3818 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
3819 *db = cs.db;
3820 *l = cs.l;
3821 }
3822 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3823
3824 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3825 struct kvm_sregs *sregs)
3826 {
3827 struct descriptor_table dt;
3828
3829 vcpu_load(vcpu);
3830
3831 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3832 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3833 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3834 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3835 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3836 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3837
3838 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3839 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3840
3841 kvm_x86_ops->get_idt(vcpu, &dt);
3842 sregs->idt.limit = dt.limit;
3843 sregs->idt.base = dt.base;
3844 kvm_x86_ops->get_gdt(vcpu, &dt);
3845 sregs->gdt.limit = dt.limit;
3846 sregs->gdt.base = dt.base;
3847
3848 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3849 sregs->cr0 = vcpu->arch.cr0;
3850 sregs->cr2 = vcpu->arch.cr2;
3851 sregs->cr3 = vcpu->arch.cr3;
3852 sregs->cr4 = vcpu->arch.cr4;
3853 sregs->cr8 = kvm_get_cr8(vcpu);
3854 sregs->efer = vcpu->arch.shadow_efer;
3855 sregs->apic_base = kvm_get_apic_base(vcpu);
3856
3857 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
3858
3859 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
3860 set_bit(vcpu->arch.interrupt.nr,
3861 (unsigned long *)sregs->interrupt_bitmap);
3862
3863 vcpu_put(vcpu);
3864
3865 return 0;
3866 }
3867
3868 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3869 struct kvm_mp_state *mp_state)
3870 {
3871 vcpu_load(vcpu);
3872 mp_state->mp_state = vcpu->arch.mp_state;
3873 vcpu_put(vcpu);
3874 return 0;
3875 }
3876
3877 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3878 struct kvm_mp_state *mp_state)
3879 {
3880 vcpu_load(vcpu);
3881 vcpu->arch.mp_state = mp_state->mp_state;
3882 vcpu_put(vcpu);
3883 return 0;
3884 }
3885
3886 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3887 struct kvm_segment *var, int seg)
3888 {
3889 kvm_x86_ops->set_segment(vcpu, var, seg);
3890 }
3891
3892 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3893 struct kvm_segment *kvm_desct)
3894 {
3895 kvm_desct->base = seg_desc->base0;
3896 kvm_desct->base |= seg_desc->base1 << 16;
3897 kvm_desct->base |= seg_desc->base2 << 24;
3898 kvm_desct->limit = seg_desc->limit0;
3899 kvm_desct->limit |= seg_desc->limit << 16;
3900 if (seg_desc->g) {
3901 kvm_desct->limit <<= 12;
3902 kvm_desct->limit |= 0xfff;
3903 }
3904 kvm_desct->selector = selector;
3905 kvm_desct->type = seg_desc->type;
3906 kvm_desct->present = seg_desc->p;
3907 kvm_desct->dpl = seg_desc->dpl;
3908 kvm_desct->db = seg_desc->d;
3909 kvm_desct->s = seg_desc->s;
3910 kvm_desct->l = seg_desc->l;
3911 kvm_desct->g = seg_desc->g;
3912 kvm_desct->avl = seg_desc->avl;
3913 if (!selector)
3914 kvm_desct->unusable = 1;
3915 else
3916 kvm_desct->unusable = 0;
3917 kvm_desct->padding = 0;
3918 }
3919
3920 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3921 u16 selector,
3922 struct descriptor_table *dtable)
3923 {
3924 if (selector & 1 << 2) {
3925 struct kvm_segment kvm_seg;
3926
3927 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3928
3929 if (kvm_seg.unusable)
3930 dtable->limit = 0;
3931 else
3932 dtable->limit = kvm_seg.limit;
3933 dtable->base = kvm_seg.base;
3934 }
3935 else
3936 kvm_x86_ops->get_gdt(vcpu, dtable);
3937 }
3938
3939 /* allowed just for 8 bytes segments */
3940 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3941 struct desc_struct *seg_desc)
3942 {
3943 gpa_t gpa;
3944 struct descriptor_table dtable;
3945 u16 index = selector >> 3;
3946
3947 get_segment_descriptor_dtable(vcpu, selector, &dtable);
3948
3949 if (dtable.limit < index * 8 + 7) {
3950 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3951 return 1;
3952 }
3953 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3954 gpa += index * 8;
3955 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
3956 }
3957
3958 /* allowed just for 8 bytes segments */
3959 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3960 struct desc_struct *seg_desc)
3961 {
3962 gpa_t gpa;
3963 struct descriptor_table dtable;
3964 u16 index = selector >> 3;
3965
3966 get_segment_descriptor_dtable(vcpu, selector, &dtable);
3967
3968 if (dtable.limit < index * 8 + 7)
3969 return 1;
3970 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3971 gpa += index * 8;
3972 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
3973 }
3974
3975 static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3976 struct desc_struct *seg_desc)
3977 {
3978 u32 base_addr;
3979
3980 base_addr = seg_desc->base0;
3981 base_addr |= (seg_desc->base1 << 16);
3982 base_addr |= (seg_desc->base2 << 24);
3983
3984 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
3985 }
3986
3987 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3988 {
3989 struct kvm_segment kvm_seg;
3990
3991 kvm_get_segment(vcpu, &kvm_seg, seg);
3992 return kvm_seg.selector;
3993 }
3994
3995 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3996 u16 selector,
3997 struct kvm_segment *kvm_seg)
3998 {
3999 struct desc_struct seg_desc;
4000
4001 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4002 return 1;
4003 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4004 return 0;
4005 }
4006
4007 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
4008 {
4009 struct kvm_segment segvar = {
4010 .base = selector << 4,
4011 .limit = 0xffff,
4012 .selector = selector,
4013 .type = 3,
4014 .present = 1,
4015 .dpl = 3,
4016 .db = 0,
4017 .s = 1,
4018 .l = 0,
4019 .g = 0,
4020 .avl = 0,
4021 .unusable = 0,
4022 };
4023 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4024 return 0;
4025 }
4026
4027 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4028 int type_bits, int seg)
4029 {
4030 struct kvm_segment kvm_seg;
4031
4032 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4033 return kvm_load_realmode_segment(vcpu, selector, seg);
4034 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4035 return 1;
4036 kvm_seg.type |= type_bits;
4037
4038 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4039 seg != VCPU_SREG_LDTR)
4040 if (!kvm_seg.s)
4041 kvm_seg.unusable = 1;
4042
4043 kvm_set_segment(vcpu, &kvm_seg, seg);
4044 return 0;
4045 }
4046
4047 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4048 struct tss_segment_32 *tss)
4049 {
4050 tss->cr3 = vcpu->arch.cr3;
4051 tss->eip = kvm_rip_read(vcpu);
4052 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
4053 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4054 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4055 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4056 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4057 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4058 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4059 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4060 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4061 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4062 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4063 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4064 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4065 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4066 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4067 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4068 }
4069
4070 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4071 struct tss_segment_32 *tss)
4072 {
4073 kvm_set_cr3(vcpu, tss->cr3);
4074
4075 kvm_rip_write(vcpu, tss->eip);
4076 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4077
4078 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4079 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4080 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4081 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4082 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4083 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4084 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4085 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4086
4087 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4088 return 1;
4089
4090 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4091 return 1;
4092
4093 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4094 return 1;
4095
4096 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4097 return 1;
4098
4099 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4100 return 1;
4101
4102 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4103 return 1;
4104
4105 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4106 return 1;
4107 return 0;
4108 }
4109
4110 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4111 struct tss_segment_16 *tss)
4112 {
4113 tss->ip = kvm_rip_read(vcpu);
4114 tss->flag = kvm_x86_ops->get_rflags(vcpu);
4115 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4116 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4117 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4118 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4119 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4120 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4121 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4122 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4123
4124 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4125 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4126 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4127 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4128 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4129 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4130 }
4131
4132 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4133 struct tss_segment_16 *tss)
4134 {
4135 kvm_rip_write(vcpu, tss->ip);
4136 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
4137 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4138 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4139 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4140 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4141 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4142 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4143 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4144 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4145
4146 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4147 return 1;
4148
4149 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4150 return 1;
4151
4152 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4153 return 1;
4154
4155 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4156 return 1;
4157
4158 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4159 return 1;
4160 return 0;
4161 }
4162
4163 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4164 u16 old_tss_sel, u32 old_tss_base,
4165 struct desc_struct *nseg_desc)
4166 {
4167 struct tss_segment_16 tss_segment_16;
4168 int ret = 0;
4169
4170 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4171 sizeof tss_segment_16))
4172 goto out;
4173
4174 save_state_to_tss16(vcpu, &tss_segment_16);
4175
4176 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4177 sizeof tss_segment_16))
4178 goto out;
4179
4180 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4181 &tss_segment_16, sizeof tss_segment_16))
4182 goto out;
4183
4184 if (old_tss_sel != 0xffff) {
4185 tss_segment_16.prev_task_link = old_tss_sel;
4186
4187 if (kvm_write_guest(vcpu->kvm,
4188 get_tss_base_addr(vcpu, nseg_desc),
4189 &tss_segment_16.prev_task_link,
4190 sizeof tss_segment_16.prev_task_link))
4191 goto out;
4192 }
4193
4194 if (load_state_from_tss16(vcpu, &tss_segment_16))
4195 goto out;
4196
4197 ret = 1;
4198 out:
4199 return ret;
4200 }
4201
4202 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4203 u16 old_tss_sel, u32 old_tss_base,
4204 struct desc_struct *nseg_desc)
4205 {
4206 struct tss_segment_32 tss_segment_32;
4207 int ret = 0;
4208
4209 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4210 sizeof tss_segment_32))
4211 goto out;
4212
4213 save_state_to_tss32(vcpu, &tss_segment_32);
4214
4215 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4216 sizeof tss_segment_32))
4217 goto out;
4218
4219 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4220 &tss_segment_32, sizeof tss_segment_32))
4221 goto out;
4222
4223 if (old_tss_sel != 0xffff) {
4224 tss_segment_32.prev_task_link = old_tss_sel;
4225
4226 if (kvm_write_guest(vcpu->kvm,
4227 get_tss_base_addr(vcpu, nseg_desc),
4228 &tss_segment_32.prev_task_link,
4229 sizeof tss_segment_32.prev_task_link))
4230 goto out;
4231 }
4232
4233 if (load_state_from_tss32(vcpu, &tss_segment_32))
4234 goto out;
4235
4236 ret = 1;
4237 out:
4238 return ret;
4239 }
4240
4241 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4242 {
4243 struct kvm_segment tr_seg;
4244 struct desc_struct cseg_desc;
4245 struct desc_struct nseg_desc;
4246 int ret = 0;
4247 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4248 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4249
4250 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4251
4252 /* FIXME: Handle errors. Failure to read either TSS or their
4253 * descriptors should generate a pagefault.
4254 */
4255 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4256 goto out;
4257
4258 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4259 goto out;
4260
4261 if (reason != TASK_SWITCH_IRET) {
4262 int cpl;
4263
4264 cpl = kvm_x86_ops->get_cpl(vcpu);
4265 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4266 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4267 return 1;
4268 }
4269 }
4270
4271 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4272 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4273 return 1;
4274 }
4275
4276 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4277 cseg_desc.type &= ~(1 << 1); //clear the B flag
4278 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4279 }
4280
4281 if (reason == TASK_SWITCH_IRET) {
4282 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4283 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4284 }
4285
4286 /* set back link to prev task only if NT bit is set in eflags
4287 note that old_tss_sel is not used afetr this point */
4288 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4289 old_tss_sel = 0xffff;
4290
4291 /* set back link to prev task only if NT bit is set in eflags
4292 note that old_tss_sel is not used afetr this point */
4293 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4294 old_tss_sel = 0xffff;
4295
4296 if (nseg_desc.type & 8)
4297 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4298 old_tss_base, &nseg_desc);
4299 else
4300 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4301 old_tss_base, &nseg_desc);
4302
4303 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4304 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4305 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4306 }
4307
4308 if (reason != TASK_SWITCH_IRET) {
4309 nseg_desc.type |= (1 << 1);
4310 save_guest_segment_descriptor(vcpu, tss_selector,
4311 &nseg_desc);
4312 }
4313
4314 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4315 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4316 tr_seg.type = 11;
4317 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4318 out:
4319 return ret;
4320 }
4321 EXPORT_SYMBOL_GPL(kvm_task_switch);
4322
4323 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4324 struct kvm_sregs *sregs)
4325 {
4326 int mmu_reset_needed = 0;
4327 int pending_vec, max_bits;
4328 struct descriptor_table dt;
4329
4330 vcpu_load(vcpu);
4331
4332 dt.limit = sregs->idt.limit;
4333 dt.base = sregs->idt.base;
4334 kvm_x86_ops->set_idt(vcpu, &dt);
4335 dt.limit = sregs->gdt.limit;
4336 dt.base = sregs->gdt.base;
4337 kvm_x86_ops->set_gdt(vcpu, &dt);
4338
4339 vcpu->arch.cr2 = sregs->cr2;
4340 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4341
4342 down_read(&vcpu->kvm->slots_lock);
4343 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4344 vcpu->arch.cr3 = sregs->cr3;
4345 else
4346 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4347 up_read(&vcpu->kvm->slots_lock);
4348
4349 kvm_set_cr8(vcpu, sregs->cr8);
4350
4351 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4352 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4353 kvm_set_apic_base(vcpu, sregs->apic_base);
4354
4355 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4356
4357 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4358 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4359 vcpu->arch.cr0 = sregs->cr0;
4360
4361 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4362 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4363 if (!is_long_mode(vcpu) && is_pae(vcpu))
4364 load_pdptrs(vcpu, vcpu->arch.cr3);
4365
4366 if (mmu_reset_needed)
4367 kvm_mmu_reset_context(vcpu);
4368
4369 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4370 pending_vec = find_first_bit(
4371 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4372 if (pending_vec < max_bits) {
4373 kvm_queue_interrupt(vcpu, pending_vec, false);
4374 pr_debug("Set back pending irq %d\n", pending_vec);
4375 if (irqchip_in_kernel(vcpu->kvm))
4376 kvm_pic_clear_isr_ack(vcpu->kvm);
4377 }
4378
4379 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4380 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4381 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4382 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4383 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4384 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4385
4386 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4387 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4388
4389 /* Older userspace won't unhalt the vcpu on reset. */
4390 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4391 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4392 !(vcpu->arch.cr0 & X86_CR0_PE))
4393 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4394
4395 vcpu_put(vcpu);
4396
4397 return 0;
4398 }
4399
4400 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4401 struct kvm_guest_debug *dbg)
4402 {
4403 int i, r;
4404
4405 vcpu_load(vcpu);
4406
4407 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4408 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4409 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4410 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4411 vcpu->arch.switch_db_regs =
4412 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4413 } else {
4414 for (i = 0; i < KVM_NR_DB_REGS; i++)
4415 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4416 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4417 }
4418
4419 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4420
4421 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4422 kvm_queue_exception(vcpu, DB_VECTOR);
4423 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4424 kvm_queue_exception(vcpu, BP_VECTOR);
4425
4426 vcpu_put(vcpu);
4427
4428 return r;
4429 }
4430
4431 /*
4432 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4433 * we have asm/x86/processor.h
4434 */
4435 struct fxsave {
4436 u16 cwd;
4437 u16 swd;
4438 u16 twd;
4439 u16 fop;
4440 u64 rip;
4441 u64 rdp;
4442 u32 mxcsr;
4443 u32 mxcsr_mask;
4444 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4445 #ifdef CONFIG_X86_64
4446 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4447 #else
4448 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4449 #endif
4450 };
4451
4452 /*
4453 * Translate a guest virtual address to a guest physical address.
4454 */
4455 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4456 struct kvm_translation *tr)
4457 {
4458 unsigned long vaddr = tr->linear_address;
4459 gpa_t gpa;
4460
4461 vcpu_load(vcpu);
4462 down_read(&vcpu->kvm->slots_lock);
4463 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4464 up_read(&vcpu->kvm->slots_lock);
4465 tr->physical_address = gpa;
4466 tr->valid = gpa != UNMAPPED_GVA;
4467 tr->writeable = 1;
4468 tr->usermode = 0;
4469 vcpu_put(vcpu);
4470
4471 return 0;
4472 }
4473
4474 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4475 {
4476 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4477
4478 vcpu_load(vcpu);
4479
4480 memcpy(fpu->fpr, fxsave->st_space, 128);
4481 fpu->fcw = fxsave->cwd;
4482 fpu->fsw = fxsave->swd;
4483 fpu->ftwx = fxsave->twd;
4484 fpu->last_opcode = fxsave->fop;
4485 fpu->last_ip = fxsave->rip;
4486 fpu->last_dp = fxsave->rdp;
4487 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4488
4489 vcpu_put(vcpu);
4490
4491 return 0;
4492 }
4493
4494 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4495 {
4496 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4497
4498 vcpu_load(vcpu);
4499
4500 memcpy(fxsave->st_space, fpu->fpr, 128);
4501 fxsave->cwd = fpu->fcw;
4502 fxsave->swd = fpu->fsw;
4503 fxsave->twd = fpu->ftwx;
4504 fxsave->fop = fpu->last_opcode;
4505 fxsave->rip = fpu->last_ip;
4506 fxsave->rdp = fpu->last_dp;
4507 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4508
4509 vcpu_put(vcpu);
4510
4511 return 0;
4512 }
4513
4514 void fx_init(struct kvm_vcpu *vcpu)
4515 {
4516 unsigned after_mxcsr_mask;
4517
4518 /*
4519 * Touch the fpu the first time in non atomic context as if
4520 * this is the first fpu instruction the exception handler
4521 * will fire before the instruction returns and it'll have to
4522 * allocate ram with GFP_KERNEL.
4523 */
4524 if (!used_math())
4525 kvm_fx_save(&vcpu->arch.host_fx_image);
4526
4527 /* Initialize guest FPU by resetting ours and saving into guest's */
4528 preempt_disable();
4529 kvm_fx_save(&vcpu->arch.host_fx_image);
4530 kvm_fx_finit();
4531 kvm_fx_save(&vcpu->arch.guest_fx_image);
4532 kvm_fx_restore(&vcpu->arch.host_fx_image);
4533 preempt_enable();
4534
4535 vcpu->arch.cr0 |= X86_CR0_ET;
4536 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4537 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4538 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4539 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4540 }
4541 EXPORT_SYMBOL_GPL(fx_init);
4542
4543 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4544 {
4545 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4546 return;
4547
4548 vcpu->guest_fpu_loaded = 1;
4549 kvm_fx_save(&vcpu->arch.host_fx_image);
4550 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4551 }
4552 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4553
4554 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4555 {
4556 if (!vcpu->guest_fpu_loaded)
4557 return;
4558
4559 vcpu->guest_fpu_loaded = 0;
4560 kvm_fx_save(&vcpu->arch.guest_fx_image);
4561 kvm_fx_restore(&vcpu->arch.host_fx_image);
4562 ++vcpu->stat.fpu_reload;
4563 }
4564 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4565
4566 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4567 {
4568 if (vcpu->arch.time_page) {
4569 kvm_release_page_dirty(vcpu->arch.time_page);
4570 vcpu->arch.time_page = NULL;
4571 }
4572
4573 kvm_x86_ops->vcpu_free(vcpu);
4574 }
4575
4576 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4577 unsigned int id)
4578 {
4579 return kvm_x86_ops->vcpu_create(kvm, id);
4580 }
4581
4582 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4583 {
4584 int r;
4585
4586 /* We do fxsave: this must be aligned. */
4587 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4588
4589 vcpu->arch.mtrr_state.have_fixed = 1;
4590 vcpu_load(vcpu);
4591 r = kvm_arch_vcpu_reset(vcpu);
4592 if (r == 0)
4593 r = kvm_mmu_setup(vcpu);
4594 vcpu_put(vcpu);
4595 if (r < 0)
4596 goto free_vcpu;
4597
4598 return 0;
4599 free_vcpu:
4600 kvm_x86_ops->vcpu_free(vcpu);
4601 return r;
4602 }
4603
4604 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4605 {
4606 vcpu_load(vcpu);
4607 kvm_mmu_unload(vcpu);
4608 vcpu_put(vcpu);
4609
4610 kvm_x86_ops->vcpu_free(vcpu);
4611 }
4612
4613 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4614 {
4615 vcpu->arch.nmi_pending = false;
4616 vcpu->arch.nmi_injected = false;
4617
4618 vcpu->arch.switch_db_regs = 0;
4619 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4620 vcpu->arch.dr6 = DR6_FIXED_1;
4621 vcpu->arch.dr7 = DR7_FIXED_1;
4622
4623 return kvm_x86_ops->vcpu_reset(vcpu);
4624 }
4625
4626 void kvm_arch_hardware_enable(void *garbage)
4627 {
4628 kvm_x86_ops->hardware_enable(garbage);
4629 }
4630
4631 void kvm_arch_hardware_disable(void *garbage)
4632 {
4633 kvm_x86_ops->hardware_disable(garbage);
4634 }
4635
4636 int kvm_arch_hardware_setup(void)
4637 {
4638 return kvm_x86_ops->hardware_setup();
4639 }
4640
4641 void kvm_arch_hardware_unsetup(void)
4642 {
4643 kvm_x86_ops->hardware_unsetup();
4644 }
4645
4646 void kvm_arch_check_processor_compat(void *rtn)
4647 {
4648 kvm_x86_ops->check_processor_compatibility(rtn);
4649 }
4650
4651 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4652 {
4653 struct page *page;
4654 struct kvm *kvm;
4655 int r;
4656
4657 BUG_ON(vcpu->kvm == NULL);
4658 kvm = vcpu->kvm;
4659
4660 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4661 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
4662 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4663 else
4664 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
4665
4666 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4667 if (!page) {
4668 r = -ENOMEM;
4669 goto fail;
4670 }
4671 vcpu->arch.pio_data = page_address(page);
4672
4673 r = kvm_mmu_create(vcpu);
4674 if (r < 0)
4675 goto fail_free_pio_data;
4676
4677 if (irqchip_in_kernel(kvm)) {
4678 r = kvm_create_lapic(vcpu);
4679 if (r < 0)
4680 goto fail_mmu_destroy;
4681 }
4682
4683 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4684 GFP_KERNEL);
4685 if (!vcpu->arch.mce_banks) {
4686 r = -ENOMEM;
4687 goto fail_mmu_destroy;
4688 }
4689 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4690
4691 return 0;
4692
4693 fail_mmu_destroy:
4694 kvm_mmu_destroy(vcpu);
4695 fail_free_pio_data:
4696 free_page((unsigned long)vcpu->arch.pio_data);
4697 fail:
4698 return r;
4699 }
4700
4701 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4702 {
4703 kvm_free_lapic(vcpu);
4704 down_read(&vcpu->kvm->slots_lock);
4705 kvm_mmu_destroy(vcpu);
4706 up_read(&vcpu->kvm->slots_lock);
4707 free_page((unsigned long)vcpu->arch.pio_data);
4708 }
4709
4710 struct kvm *kvm_arch_create_vm(void)
4711 {
4712 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4713
4714 if (!kvm)
4715 return ERR_PTR(-ENOMEM);
4716
4717 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4718 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
4719
4720 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4721 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4722
4723 rdtscll(kvm->arch.vm_init_tsc);
4724
4725 return kvm;
4726 }
4727
4728 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4729 {
4730 vcpu_load(vcpu);
4731 kvm_mmu_unload(vcpu);
4732 vcpu_put(vcpu);
4733 }
4734
4735 static void kvm_free_vcpus(struct kvm *kvm)
4736 {
4737 unsigned int i;
4738 struct kvm_vcpu *vcpu;
4739
4740 /*
4741 * Unpin any mmu pages first.
4742 */
4743 kvm_for_each_vcpu(i, vcpu, kvm)
4744 kvm_unload_vcpu_mmu(vcpu);
4745 kvm_for_each_vcpu(i, vcpu, kvm)
4746 kvm_arch_vcpu_free(vcpu);
4747
4748 mutex_lock(&kvm->lock);
4749 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4750 kvm->vcpus[i] = NULL;
4751
4752 atomic_set(&kvm->online_vcpus, 0);
4753 mutex_unlock(&kvm->lock);
4754 }
4755
4756 void kvm_arch_sync_events(struct kvm *kvm)
4757 {
4758 kvm_free_all_assigned_devices(kvm);
4759 }
4760
4761 void kvm_arch_destroy_vm(struct kvm *kvm)
4762 {
4763 kvm_iommu_unmap_guest(kvm);
4764 kvm_free_pit(kvm);
4765 kfree(kvm->arch.vpic);
4766 kfree(kvm->arch.vioapic);
4767 kvm_free_vcpus(kvm);
4768 kvm_free_physmem(kvm);
4769 if (kvm->arch.apic_access_page)
4770 put_page(kvm->arch.apic_access_page);
4771 if (kvm->arch.ept_identity_pagetable)
4772 put_page(kvm->arch.ept_identity_pagetable);
4773 kfree(kvm);
4774 }
4775
4776 int kvm_arch_set_memory_region(struct kvm *kvm,
4777 struct kvm_userspace_memory_region *mem,
4778 struct kvm_memory_slot old,
4779 int user_alloc)
4780 {
4781 int npages = mem->memory_size >> PAGE_SHIFT;
4782 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4783
4784 /*To keep backward compatibility with older userspace,
4785 *x86 needs to hanlde !user_alloc case.
4786 */
4787 if (!user_alloc) {
4788 if (npages && !old.rmap) {
4789 unsigned long userspace_addr;
4790
4791 down_write(&current->mm->mmap_sem);
4792 userspace_addr = do_mmap(NULL, 0,
4793 npages * PAGE_SIZE,
4794 PROT_READ | PROT_WRITE,
4795 MAP_PRIVATE | MAP_ANONYMOUS,
4796 0);
4797 up_write(&current->mm->mmap_sem);
4798
4799 if (IS_ERR((void *)userspace_addr))
4800 return PTR_ERR((void *)userspace_addr);
4801
4802 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4803 spin_lock(&kvm->mmu_lock);
4804 memslot->userspace_addr = userspace_addr;
4805 spin_unlock(&kvm->mmu_lock);
4806 } else {
4807 if (!old.user_alloc && old.rmap) {
4808 int ret;
4809
4810 down_write(&current->mm->mmap_sem);
4811 ret = do_munmap(current->mm, old.userspace_addr,
4812 old.npages * PAGE_SIZE);
4813 up_write(&current->mm->mmap_sem);
4814 if (ret < 0)
4815 printk(KERN_WARNING
4816 "kvm_vm_ioctl_set_memory_region: "
4817 "failed to munmap memory\n");
4818 }
4819 }
4820 }
4821
4822 spin_lock(&kvm->mmu_lock);
4823 if (!kvm->arch.n_requested_mmu_pages) {
4824 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4825 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4826 }
4827
4828 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4829 spin_unlock(&kvm->mmu_lock);
4830 kvm_flush_remote_tlbs(kvm);
4831
4832 return 0;
4833 }
4834
4835 void kvm_arch_flush_shadow(struct kvm *kvm)
4836 {
4837 kvm_mmu_zap_all(kvm);
4838 kvm_reload_remote_mmus(kvm);
4839 }
4840
4841 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4842 {
4843 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4844 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4845 || vcpu->arch.nmi_pending;
4846 }
4847
4848 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4849 {
4850 int me;
4851 int cpu = vcpu->cpu;
4852
4853 if (waitqueue_active(&vcpu->wq)) {
4854 wake_up_interruptible(&vcpu->wq);
4855 ++vcpu->stat.halt_wakeup;
4856 }
4857
4858 me = get_cpu();
4859 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4860 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4861 smp_send_reschedule(cpu);
4862 put_cpu();
4863 }
4864
4865 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4866 {
4867 return kvm_x86_ops->interrupt_allowed(vcpu);
4868 }
4869
4870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4872 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4873 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4874 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux kernel - Deliverables
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