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Merge branch 'x86-headers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68
69 #define CREATE_TRACE_POINTS
70 #include "trace.h"
71
72 #define MAX_IO_MSRS 256
73 #define KVM_MAX_MCE_BANKS 32
74 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75
76 #define emul_to_vcpu(ctxt) \
77 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
78
79 /* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83 #ifdef CONFIG_X86_64
84 static
85 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 #else
87 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
88 #endif
89
90 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
91 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92
93 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
94 static void process_nmi(struct kvm_vcpu *vcpu);
95 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96
97 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
98 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99
100 static bool __read_mostly ignore_msrs = 0;
101 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102
103 unsigned int min_timer_period_us = 500;
104 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105
106 static bool __read_mostly kvmclock_periodic_sync = true;
107 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108
109 bool __read_mostly kvm_has_tsc_control;
110 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
111 u32 __read_mostly kvm_max_guest_tsc_khz;
112 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
113 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
114 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
115 u64 __read_mostly kvm_max_tsc_scaling_ratio;
116 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
117 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
118
119 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
120 static u32 __read_mostly tsc_tolerance_ppm = 250;
121 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122
123 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
124 unsigned int __read_mostly lapic_timer_advance_ns = 0;
125 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126
127 static bool __read_mostly vector_hashing = true;
128 module_param(vector_hashing, bool, S_IRUGO);
129
130 static bool __read_mostly backwards_tsc_observed = false;
131
132 #define KVM_NR_SHARED_MSRS 16
133
134 struct kvm_shared_msrs_global {
135 int nr;
136 u32 msrs[KVM_NR_SHARED_MSRS];
137 };
138
139 struct kvm_shared_msrs {
140 struct user_return_notifier urn;
141 bool registered;
142 struct kvm_shared_msr_values {
143 u64 host;
144 u64 curr;
145 } values[KVM_NR_SHARED_MSRS];
146 };
147
148 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
149 static struct kvm_shared_msrs __percpu *shared_msrs;
150
151 struct kvm_stats_debugfs_item debugfs_entries[] = {
152 { "pf_fixed", VCPU_STAT(pf_fixed) },
153 { "pf_guest", VCPU_STAT(pf_guest) },
154 { "tlb_flush", VCPU_STAT(tlb_flush) },
155 { "invlpg", VCPU_STAT(invlpg) },
156 { "exits", VCPU_STAT(exits) },
157 { "io_exits", VCPU_STAT(io_exits) },
158 { "mmio_exits", VCPU_STAT(mmio_exits) },
159 { "signal_exits", VCPU_STAT(signal_exits) },
160 { "irq_window", VCPU_STAT(irq_window_exits) },
161 { "nmi_window", VCPU_STAT(nmi_window_exits) },
162 { "halt_exits", VCPU_STAT(halt_exits) },
163 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
164 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
165 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
166 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
167 { "hypercalls", VCPU_STAT(hypercalls) },
168 { "request_irq", VCPU_STAT(request_irq_exits) },
169 { "irq_exits", VCPU_STAT(irq_exits) },
170 { "host_state_reload", VCPU_STAT(host_state_reload) },
171 { "efer_reload", VCPU_STAT(efer_reload) },
172 { "fpu_reload", VCPU_STAT(fpu_reload) },
173 { "insn_emulation", VCPU_STAT(insn_emulation) },
174 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
175 { "irq_injections", VCPU_STAT(irq_injections) },
176 { "nmi_injections", VCPU_STAT(nmi_injections) },
177 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
178 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
179 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
180 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
181 { "mmu_flooded", VM_STAT(mmu_flooded) },
182 { "mmu_recycled", VM_STAT(mmu_recycled) },
183 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
184 { "mmu_unsync", VM_STAT(mmu_unsync) },
185 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
186 { "largepages", VM_STAT(lpages) },
187 { NULL }
188 };
189
190 u64 __read_mostly host_xcr0;
191
192 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
193
194 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
195 {
196 int i;
197 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
198 vcpu->arch.apf.gfns[i] = ~0;
199 }
200
201 static void kvm_on_user_return(struct user_return_notifier *urn)
202 {
203 unsigned slot;
204 struct kvm_shared_msrs *locals
205 = container_of(urn, struct kvm_shared_msrs, urn);
206 struct kvm_shared_msr_values *values;
207
208 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
209 values = &locals->values[slot];
210 if (values->host != values->curr) {
211 wrmsrl(shared_msrs_global.msrs[slot], values->host);
212 values->curr = values->host;
213 }
214 }
215 locals->registered = false;
216 user_return_notifier_unregister(urn);
217 }
218
219 static void shared_msr_update(unsigned slot, u32 msr)
220 {
221 u64 value;
222 unsigned int cpu = smp_processor_id();
223 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
224
225 /* only read, and nobody should modify it at this time,
226 * so don't need lock */
227 if (slot >= shared_msrs_global.nr) {
228 printk(KERN_ERR "kvm: invalid MSR slot!");
229 return;
230 }
231 rdmsrl_safe(msr, &value);
232 smsr->values[slot].host = value;
233 smsr->values[slot].curr = value;
234 }
235
236 void kvm_define_shared_msr(unsigned slot, u32 msr)
237 {
238 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
239 shared_msrs_global.msrs[slot] = msr;
240 if (slot >= shared_msrs_global.nr)
241 shared_msrs_global.nr = slot + 1;
242 }
243 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
244
245 static void kvm_shared_msr_cpu_online(void)
246 {
247 unsigned i;
248
249 for (i = 0; i < shared_msrs_global.nr; ++i)
250 shared_msr_update(i, shared_msrs_global.msrs[i]);
251 }
252
253 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
254 {
255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
257 int err;
258
259 if (((value ^ smsr->values[slot].curr) & mask) == 0)
260 return 0;
261 smsr->values[slot].curr = value;
262 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
263 if (err)
264 return 1;
265
266 if (!smsr->registered) {
267 smsr->urn.on_user_return = kvm_on_user_return;
268 user_return_notifier_register(&smsr->urn);
269 smsr->registered = true;
270 }
271 return 0;
272 }
273 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
274
275 static void drop_user_return_notifiers(void)
276 {
277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
279
280 if (smsr->registered)
281 kvm_on_user_return(&smsr->urn);
282 }
283
284 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
285 {
286 return vcpu->arch.apic_base;
287 }
288 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
289
290 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
291 {
292 u64 old_state = vcpu->arch.apic_base &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 new_state = msr_info->data &
295 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
296 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
297 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
298
299 if (!msr_info->host_initiated &&
300 ((msr_info->data & reserved_bits) != 0 ||
301 new_state == X2APIC_ENABLE ||
302 (new_state == MSR_IA32_APICBASE_ENABLE &&
303 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
304 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
305 old_state == 0)))
306 return 1;
307
308 kvm_lapic_set_base(vcpu, msr_info->data);
309 return 0;
310 }
311 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
312
313 asmlinkage __visible void kvm_spurious_fault(void)
314 {
315 /* Fault while not rebooting. We want the trace. */
316 BUG();
317 }
318 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
319
320 #define EXCPT_BENIGN 0
321 #define EXCPT_CONTRIBUTORY 1
322 #define EXCPT_PF 2
323
324 static int exception_class(int vector)
325 {
326 switch (vector) {
327 case PF_VECTOR:
328 return EXCPT_PF;
329 case DE_VECTOR:
330 case TS_VECTOR:
331 case NP_VECTOR:
332 case SS_VECTOR:
333 case GP_VECTOR:
334 return EXCPT_CONTRIBUTORY;
335 default:
336 break;
337 }
338 return EXCPT_BENIGN;
339 }
340
341 #define EXCPT_FAULT 0
342 #define EXCPT_TRAP 1
343 #define EXCPT_ABORT 2
344 #define EXCPT_INTERRUPT 3
345
346 static int exception_type(int vector)
347 {
348 unsigned int mask;
349
350 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
351 return EXCPT_INTERRUPT;
352
353 mask = 1 << vector;
354
355 /* #DB is trap, as instruction watchpoints are handled elsewhere */
356 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
357 return EXCPT_TRAP;
358
359 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
360 return EXCPT_ABORT;
361
362 /* Reserved exceptions will result in fault */
363 return EXCPT_FAULT;
364 }
365
366 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
367 unsigned nr, bool has_error, u32 error_code,
368 bool reinject)
369 {
370 u32 prev_nr;
371 int class1, class2;
372
373 kvm_make_request(KVM_REQ_EVENT, vcpu);
374
375 if (!vcpu->arch.exception.pending) {
376 queue:
377 if (has_error && !is_protmode(vcpu))
378 has_error = false;
379 vcpu->arch.exception.pending = true;
380 vcpu->arch.exception.has_error_code = has_error;
381 vcpu->arch.exception.nr = nr;
382 vcpu->arch.exception.error_code = error_code;
383 vcpu->arch.exception.reinject = reinject;
384 return;
385 }
386
387 /* to check exception */
388 prev_nr = vcpu->arch.exception.nr;
389 if (prev_nr == DF_VECTOR) {
390 /* triple fault -> shutdown */
391 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
392 return;
393 }
394 class1 = exception_class(prev_nr);
395 class2 = exception_class(nr);
396 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
397 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
398 /* generate double fault per SDM Table 5-5 */
399 vcpu->arch.exception.pending = true;
400 vcpu->arch.exception.has_error_code = true;
401 vcpu->arch.exception.nr = DF_VECTOR;
402 vcpu->arch.exception.error_code = 0;
403 } else
404 /* replace previous exception with a new one in a hope
405 that instruction re-execution will regenerate lost
406 exception */
407 goto queue;
408 }
409
410 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
411 {
412 kvm_multiple_exception(vcpu, nr, false, 0, false);
413 }
414 EXPORT_SYMBOL_GPL(kvm_queue_exception);
415
416 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417 {
418 kvm_multiple_exception(vcpu, nr, false, 0, true);
419 }
420 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
421
422 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
423 {
424 if (err)
425 kvm_inject_gp(vcpu, 0);
426 else
427 kvm_x86_ops->skip_emulated_instruction(vcpu);
428 }
429 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
430
431 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
432 {
433 ++vcpu->stat.pf_guest;
434 vcpu->arch.cr2 = fault->address;
435 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
436 }
437 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
438
439 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
440 {
441 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
442 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
443 else
444 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
445
446 return fault->nested_page_fault;
447 }
448
449 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
450 {
451 atomic_inc(&vcpu->arch.nmi_queued);
452 kvm_make_request(KVM_REQ_NMI, vcpu);
453 }
454 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
455
456 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
457 {
458 kvm_multiple_exception(vcpu, nr, true, error_code, false);
459 }
460 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
461
462 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463 {
464 kvm_multiple_exception(vcpu, nr, true, error_code, true);
465 }
466 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
467
468 /*
469 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
470 * a #GP and return false.
471 */
472 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
473 {
474 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
475 return true;
476 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
477 return false;
478 }
479 EXPORT_SYMBOL_GPL(kvm_require_cpl);
480
481 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
482 {
483 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
484 return true;
485
486 kvm_queue_exception(vcpu, UD_VECTOR);
487 return false;
488 }
489 EXPORT_SYMBOL_GPL(kvm_require_dr);
490
491 /*
492 * This function will be used to read from the physical memory of the currently
493 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
494 * can read from guest physical or from the guest's guest physical memory.
495 */
496 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
497 gfn_t ngfn, void *data, int offset, int len,
498 u32 access)
499 {
500 struct x86_exception exception;
501 gfn_t real_gfn;
502 gpa_t ngpa;
503
504 ngpa = gfn_to_gpa(ngfn);
505 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
506 if (real_gfn == UNMAPPED_GVA)
507 return -EFAULT;
508
509 real_gfn = gpa_to_gfn(real_gfn);
510
511 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
512 }
513 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
514
515 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
516 void *data, int offset, int len, u32 access)
517 {
518 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
519 data, offset, len, access);
520 }
521
522 /*
523 * Load the pae pdptrs. Return true is they are all valid.
524 */
525 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
526 {
527 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
528 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
529 int i;
530 int ret;
531 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
532
533 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
534 offset * sizeof(u64), sizeof(pdpte),
535 PFERR_USER_MASK|PFERR_WRITE_MASK);
536 if (ret < 0) {
537 ret = 0;
538 goto out;
539 }
540 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
541 if (is_present_gpte(pdpte[i]) &&
542 (pdpte[i] &
543 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
544 ret = 0;
545 goto out;
546 }
547 }
548 ret = 1;
549
550 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_avail);
553 __set_bit(VCPU_EXREG_PDPTR,
554 (unsigned long *)&vcpu->arch.regs_dirty);
555 out:
556
557 return ret;
558 }
559 EXPORT_SYMBOL_GPL(load_pdptrs);
560
561 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
562 {
563 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
564 bool changed = true;
565 int offset;
566 gfn_t gfn;
567 int r;
568
569 if (is_long_mode(vcpu) || !is_pae(vcpu))
570 return false;
571
572 if (!test_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail))
574 return true;
575
576 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
577 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
578 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
579 PFERR_USER_MASK | PFERR_WRITE_MASK);
580 if (r < 0)
581 goto out;
582 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
583 out:
584
585 return changed;
586 }
587
588 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
589 {
590 unsigned long old_cr0 = kvm_read_cr0(vcpu);
591 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
592
593 cr0 |= X86_CR0_ET;
594
595 #ifdef CONFIG_X86_64
596 if (cr0 & 0xffffffff00000000UL)
597 return 1;
598 #endif
599
600 cr0 &= ~CR0_RESERVED_BITS;
601
602 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
603 return 1;
604
605 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
606 return 1;
607
608 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
609 #ifdef CONFIG_X86_64
610 if ((vcpu->arch.efer & EFER_LME)) {
611 int cs_db, cs_l;
612
613 if (!is_pae(vcpu))
614 return 1;
615 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
616 if (cs_l)
617 return 1;
618 } else
619 #endif
620 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
621 kvm_read_cr3(vcpu)))
622 return 1;
623 }
624
625 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
626 return 1;
627
628 kvm_x86_ops->set_cr0(vcpu, cr0);
629
630 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
631 kvm_clear_async_pf_completion_queue(vcpu);
632 kvm_async_pf_hash_reset(vcpu);
633 }
634
635 if ((cr0 ^ old_cr0) & update_bits)
636 kvm_mmu_reset_context(vcpu);
637
638 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
639 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
640 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
641 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
642
643 return 0;
644 }
645 EXPORT_SYMBOL_GPL(kvm_set_cr0);
646
647 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
648 {
649 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
650 }
651 EXPORT_SYMBOL_GPL(kvm_lmsw);
652
653 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
654 {
655 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
656 !vcpu->guest_xcr0_loaded) {
657 /* kvm_set_xcr() also depends on this */
658 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
659 vcpu->guest_xcr0_loaded = 1;
660 }
661 }
662
663 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
664 {
665 if (vcpu->guest_xcr0_loaded) {
666 if (vcpu->arch.xcr0 != host_xcr0)
667 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
668 vcpu->guest_xcr0_loaded = 0;
669 }
670 }
671
672 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
673 {
674 u64 xcr0 = xcr;
675 u64 old_xcr0 = vcpu->arch.xcr0;
676 u64 valid_bits;
677
678 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
679 if (index != XCR_XFEATURE_ENABLED_MASK)
680 return 1;
681 if (!(xcr0 & XFEATURE_MASK_FP))
682 return 1;
683 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
684 return 1;
685
686 /*
687 * Do not allow the guest to set bits that we do not support
688 * saving. However, xcr0 bit 0 is always set, even if the
689 * emulated CPU does not support XSAVE (see fx_init).
690 */
691 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
692 if (xcr0 & ~valid_bits)
693 return 1;
694
695 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
696 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
697 return 1;
698
699 if (xcr0 & XFEATURE_MASK_AVX512) {
700 if (!(xcr0 & XFEATURE_MASK_YMM))
701 return 1;
702 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
703 return 1;
704 }
705 vcpu->arch.xcr0 = xcr0;
706
707 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
708 kvm_update_cpuid(vcpu);
709 return 0;
710 }
711
712 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
713 {
714 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
715 __kvm_set_xcr(vcpu, index, xcr)) {
716 kvm_inject_gp(vcpu, 0);
717 return 1;
718 }
719 return 0;
720 }
721 EXPORT_SYMBOL_GPL(kvm_set_xcr);
722
723 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
724 {
725 unsigned long old_cr4 = kvm_read_cr4(vcpu);
726 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
727 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
728
729 if (cr4 & CR4_RESERVED_BITS)
730 return 1;
731
732 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
733 return 1;
734
735 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
736 return 1;
737
738 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
739 return 1;
740
741 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
742 return 1;
743
744 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
745 return 1;
746
747 if (is_long_mode(vcpu)) {
748 if (!(cr4 & X86_CR4_PAE))
749 return 1;
750 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
751 && ((cr4 ^ old_cr4) & pdptr_bits)
752 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
753 kvm_read_cr3(vcpu)))
754 return 1;
755
756 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
757 if (!guest_cpuid_has_pcid(vcpu))
758 return 1;
759
760 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
761 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
762 return 1;
763 }
764
765 if (kvm_x86_ops->set_cr4(vcpu, cr4))
766 return 1;
767
768 if (((cr4 ^ old_cr4) & pdptr_bits) ||
769 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
770 kvm_mmu_reset_context(vcpu);
771
772 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
773 kvm_update_cpuid(vcpu);
774
775 return 0;
776 }
777 EXPORT_SYMBOL_GPL(kvm_set_cr4);
778
779 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
780 {
781 #ifdef CONFIG_X86_64
782 cr3 &= ~CR3_PCID_INVD;
783 #endif
784
785 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
786 kvm_mmu_sync_roots(vcpu);
787 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
788 return 0;
789 }
790
791 if (is_long_mode(vcpu)) {
792 if (cr3 & CR3_L_MODE_RESERVED_BITS)
793 return 1;
794 } else if (is_pae(vcpu) && is_paging(vcpu) &&
795 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
796 return 1;
797
798 vcpu->arch.cr3 = cr3;
799 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
800 kvm_mmu_new_cr3(vcpu);
801 return 0;
802 }
803 EXPORT_SYMBOL_GPL(kvm_set_cr3);
804
805 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
806 {
807 if (cr8 & CR8_RESERVED_BITS)
808 return 1;
809 if (lapic_in_kernel(vcpu))
810 kvm_lapic_set_tpr(vcpu, cr8);
811 else
812 vcpu->arch.cr8 = cr8;
813 return 0;
814 }
815 EXPORT_SYMBOL_GPL(kvm_set_cr8);
816
817 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
818 {
819 if (lapic_in_kernel(vcpu))
820 return kvm_lapic_get_cr8(vcpu);
821 else
822 return vcpu->arch.cr8;
823 }
824 EXPORT_SYMBOL_GPL(kvm_get_cr8);
825
826 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
827 {
828 int i;
829
830 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
831 for (i = 0; i < KVM_NR_DB_REGS; i++)
832 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
833 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
834 }
835 }
836
837 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
838 {
839 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
840 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
841 }
842
843 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
844 {
845 unsigned long dr7;
846
847 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
848 dr7 = vcpu->arch.guest_debug_dr7;
849 else
850 dr7 = vcpu->arch.dr7;
851 kvm_x86_ops->set_dr7(vcpu, dr7);
852 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
853 if (dr7 & DR7_BP_EN_MASK)
854 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
855 }
856
857 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
858 {
859 u64 fixed = DR6_FIXED_1;
860
861 if (!guest_cpuid_has_rtm(vcpu))
862 fixed |= DR6_RTM;
863 return fixed;
864 }
865
866 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
867 {
868 switch (dr) {
869 case 0 ... 3:
870 vcpu->arch.db[dr] = val;
871 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
872 vcpu->arch.eff_db[dr] = val;
873 break;
874 case 4:
875 /* fall through */
876 case 6:
877 if (val & 0xffffffff00000000ULL)
878 return -1; /* #GP */
879 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
880 kvm_update_dr6(vcpu);
881 break;
882 case 5:
883 /* fall through */
884 default: /* 7 */
885 if (val & 0xffffffff00000000ULL)
886 return -1; /* #GP */
887 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
888 kvm_update_dr7(vcpu);
889 break;
890 }
891
892 return 0;
893 }
894
895 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
896 {
897 if (__kvm_set_dr(vcpu, dr, val)) {
898 kvm_inject_gp(vcpu, 0);
899 return 1;
900 }
901 return 0;
902 }
903 EXPORT_SYMBOL_GPL(kvm_set_dr);
904
905 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
906 {
907 switch (dr) {
908 case 0 ... 3:
909 *val = vcpu->arch.db[dr];
910 break;
911 case 4:
912 /* fall through */
913 case 6:
914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
915 *val = vcpu->arch.dr6;
916 else
917 *val = kvm_x86_ops->get_dr6(vcpu);
918 break;
919 case 5:
920 /* fall through */
921 default: /* 7 */
922 *val = vcpu->arch.dr7;
923 break;
924 }
925 return 0;
926 }
927 EXPORT_SYMBOL_GPL(kvm_get_dr);
928
929 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
930 {
931 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
932 u64 data;
933 int err;
934
935 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
936 if (err)
937 return err;
938 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
939 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
940 return err;
941 }
942 EXPORT_SYMBOL_GPL(kvm_rdpmc);
943
944 /*
945 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
946 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
947 *
948 * This list is modified at module load time to reflect the
949 * capabilities of the host cpu. This capabilities test skips MSRs that are
950 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
951 * may depend on host virtualization features rather than host cpu features.
952 */
953
954 static u32 msrs_to_save[] = {
955 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
956 MSR_STAR,
957 #ifdef CONFIG_X86_64
958 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
959 #endif
960 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
961 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
962 };
963
964 static unsigned num_msrs_to_save;
965
966 static u32 emulated_msrs[] = {
967 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
968 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
969 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
970 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
971 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
972 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
973 HV_X64_MSR_RESET,
974 HV_X64_MSR_VP_INDEX,
975 HV_X64_MSR_VP_RUNTIME,
976 HV_X64_MSR_SCONTROL,
977 HV_X64_MSR_STIMER0_CONFIG,
978 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
979 MSR_KVM_PV_EOI_EN,
980
981 MSR_IA32_TSC_ADJUST,
982 MSR_IA32_TSCDEADLINE,
983 MSR_IA32_MISC_ENABLE,
984 MSR_IA32_MCG_STATUS,
985 MSR_IA32_MCG_CTL,
986 MSR_IA32_SMBASE,
987 };
988
989 static unsigned num_emulated_msrs;
990
991 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
992 {
993 if (efer & efer_reserved_bits)
994 return false;
995
996 if (efer & EFER_FFXSR) {
997 struct kvm_cpuid_entry2 *feat;
998
999 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1000 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1001 return false;
1002 }
1003
1004 if (efer & EFER_SVME) {
1005 struct kvm_cpuid_entry2 *feat;
1006
1007 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1008 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1009 return false;
1010 }
1011
1012 return true;
1013 }
1014 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1015
1016 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1017 {
1018 u64 old_efer = vcpu->arch.efer;
1019
1020 if (!kvm_valid_efer(vcpu, efer))
1021 return 1;
1022
1023 if (is_paging(vcpu)
1024 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1025 return 1;
1026
1027 efer &= ~EFER_LMA;
1028 efer |= vcpu->arch.efer & EFER_LMA;
1029
1030 kvm_x86_ops->set_efer(vcpu, efer);
1031
1032 /* Update reserved bits */
1033 if ((efer ^ old_efer) & EFER_NX)
1034 kvm_mmu_reset_context(vcpu);
1035
1036 return 0;
1037 }
1038
1039 void kvm_enable_efer_bits(u64 mask)
1040 {
1041 efer_reserved_bits &= ~mask;
1042 }
1043 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1044
1045 /*
1046 * Writes msr value into into the appropriate "register".
1047 * Returns 0 on success, non-0 otherwise.
1048 * Assumes vcpu_load() was already called.
1049 */
1050 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1051 {
1052 switch (msr->index) {
1053 case MSR_FS_BASE:
1054 case MSR_GS_BASE:
1055 case MSR_KERNEL_GS_BASE:
1056 case MSR_CSTAR:
1057 case MSR_LSTAR:
1058 if (is_noncanonical_address(msr->data))
1059 return 1;
1060 break;
1061 case MSR_IA32_SYSENTER_EIP:
1062 case MSR_IA32_SYSENTER_ESP:
1063 /*
1064 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1065 * non-canonical address is written on Intel but not on
1066 * AMD (which ignores the top 32-bits, because it does
1067 * not implement 64-bit SYSENTER).
1068 *
1069 * 64-bit code should hence be able to write a non-canonical
1070 * value on AMD. Making the address canonical ensures that
1071 * vmentry does not fail on Intel after writing a non-canonical
1072 * value, and that something deterministic happens if the guest
1073 * invokes 64-bit SYSENTER.
1074 */
1075 msr->data = get_canonical(msr->data);
1076 }
1077 return kvm_x86_ops->set_msr(vcpu, msr);
1078 }
1079 EXPORT_SYMBOL_GPL(kvm_set_msr);
1080
1081 /*
1082 * Adapt set_msr() to msr_io()'s calling convention
1083 */
1084 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085 {
1086 struct msr_data msr;
1087 int r;
1088
1089 msr.index = index;
1090 msr.host_initiated = true;
1091 r = kvm_get_msr(vcpu, &msr);
1092 if (r)
1093 return r;
1094
1095 *data = msr.data;
1096 return 0;
1097 }
1098
1099 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1100 {
1101 struct msr_data msr;
1102
1103 msr.data = *data;
1104 msr.index = index;
1105 msr.host_initiated = true;
1106 return kvm_set_msr(vcpu, &msr);
1107 }
1108
1109 #ifdef CONFIG_X86_64
1110 struct pvclock_gtod_data {
1111 seqcount_t seq;
1112
1113 struct { /* extract of a clocksource struct */
1114 int vclock_mode;
1115 cycle_t cycle_last;
1116 cycle_t mask;
1117 u32 mult;
1118 u32 shift;
1119 } clock;
1120
1121 u64 boot_ns;
1122 u64 nsec_base;
1123 };
1124
1125 static struct pvclock_gtod_data pvclock_gtod_data;
1126
1127 static void update_pvclock_gtod(struct timekeeper *tk)
1128 {
1129 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1130 u64 boot_ns;
1131
1132 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1133
1134 write_seqcount_begin(&vdata->seq);
1135
1136 /* copy pvclock gtod data */
1137 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1138 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1139 vdata->clock.mask = tk->tkr_mono.mask;
1140 vdata->clock.mult = tk->tkr_mono.mult;
1141 vdata->clock.shift = tk->tkr_mono.shift;
1142
1143 vdata->boot_ns = boot_ns;
1144 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1145
1146 write_seqcount_end(&vdata->seq);
1147 }
1148 #endif
1149
1150 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1151 {
1152 /*
1153 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1154 * vcpu_enter_guest. This function is only called from
1155 * the physical CPU that is running vcpu.
1156 */
1157 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1158 }
1159
1160 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1161 {
1162 int version;
1163 int r;
1164 struct pvclock_wall_clock wc;
1165 struct timespec boot;
1166
1167 if (!wall_clock)
1168 return;
1169
1170 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1171 if (r)
1172 return;
1173
1174 if (version & 1)
1175 ++version; /* first time write, random junk */
1176
1177 ++version;
1178
1179 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1180 return;
1181
1182 /*
1183 * The guest calculates current wall clock time by adding
1184 * system time (updated by kvm_guest_time_update below) to the
1185 * wall clock specified here. guest system time equals host
1186 * system time for us, thus we must fill in host boot time here.
1187 */
1188 getboottime(&boot);
1189
1190 if (kvm->arch.kvmclock_offset) {
1191 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1192 boot = timespec_sub(boot, ts);
1193 }
1194 wc.sec = boot.tv_sec;
1195 wc.nsec = boot.tv_nsec;
1196 wc.version = version;
1197
1198 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1199
1200 version++;
1201 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1202 }
1203
1204 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1205 {
1206 do_shl32_div32(dividend, divisor);
1207 return dividend;
1208 }
1209
1210 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1211 s8 *pshift, u32 *pmultiplier)
1212 {
1213 uint64_t scaled64;
1214 int32_t shift = 0;
1215 uint64_t tps64;
1216 uint32_t tps32;
1217
1218 tps64 = base_hz;
1219 scaled64 = scaled_hz;
1220 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1221 tps64 >>= 1;
1222 shift--;
1223 }
1224
1225 tps32 = (uint32_t)tps64;
1226 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1227 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1228 scaled64 >>= 1;
1229 else
1230 tps32 <<= 1;
1231 shift++;
1232 }
1233
1234 *pshift = shift;
1235 *pmultiplier = div_frac(scaled64, tps32);
1236
1237 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1238 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1239 }
1240
1241 #ifdef CONFIG_X86_64
1242 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1243 #endif
1244
1245 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1246 static unsigned long max_tsc_khz;
1247
1248 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1249 {
1250 u64 v = (u64)khz * (1000000 + ppm);
1251 do_div(v, 1000000);
1252 return v;
1253 }
1254
1255 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1256 {
1257 u64 ratio;
1258
1259 /* Guest TSC same frequency as host TSC? */
1260 if (!scale) {
1261 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1262 return 0;
1263 }
1264
1265 /* TSC scaling supported? */
1266 if (!kvm_has_tsc_control) {
1267 if (user_tsc_khz > tsc_khz) {
1268 vcpu->arch.tsc_catchup = 1;
1269 vcpu->arch.tsc_always_catchup = 1;
1270 return 0;
1271 } else {
1272 WARN(1, "user requested TSC rate below hardware speed\n");
1273 return -1;
1274 }
1275 }
1276
1277 /* TSC scaling required - calculate ratio */
1278 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1279 user_tsc_khz, tsc_khz);
1280
1281 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1282 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1283 user_tsc_khz);
1284 return -1;
1285 }
1286
1287 vcpu->arch.tsc_scaling_ratio = ratio;
1288 return 0;
1289 }
1290
1291 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1292 {
1293 u32 thresh_lo, thresh_hi;
1294 int use_scaling = 0;
1295
1296 /* tsc_khz can be zero if TSC calibration fails */
1297 if (user_tsc_khz == 0) {
1298 /* set tsc_scaling_ratio to a safe value */
1299 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1300 return -1;
1301 }
1302
1303 /* Compute a scale to convert nanoseconds in TSC cycles */
1304 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1305 &vcpu->arch.virtual_tsc_shift,
1306 &vcpu->arch.virtual_tsc_mult);
1307 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1308
1309 /*
1310 * Compute the variation in TSC rate which is acceptable
1311 * within the range of tolerance and decide if the
1312 * rate being applied is within that bounds of the hardware
1313 * rate. If so, no scaling or compensation need be done.
1314 */
1315 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1316 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1317 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1318 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1319 use_scaling = 1;
1320 }
1321 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1322 }
1323
1324 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1325 {
1326 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1327 vcpu->arch.virtual_tsc_mult,
1328 vcpu->arch.virtual_tsc_shift);
1329 tsc += vcpu->arch.this_tsc_write;
1330 return tsc;
1331 }
1332
1333 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1334 {
1335 #ifdef CONFIG_X86_64
1336 bool vcpus_matched;
1337 struct kvm_arch *ka = &vcpu->kvm->arch;
1338 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1339
1340 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1341 atomic_read(&vcpu->kvm->online_vcpus));
1342
1343 /*
1344 * Once the masterclock is enabled, always perform request in
1345 * order to update it.
1346 *
1347 * In order to enable masterclock, the host clocksource must be TSC
1348 * and the vcpus need to have matched TSCs. When that happens,
1349 * perform request to enable masterclock.
1350 */
1351 if (ka->use_master_clock ||
1352 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1353 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1354
1355 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1356 atomic_read(&vcpu->kvm->online_vcpus),
1357 ka->use_master_clock, gtod->clock.vclock_mode);
1358 #endif
1359 }
1360
1361 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1362 {
1363 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1364 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1365 }
1366
1367 /*
1368 * Multiply tsc by a fixed point number represented by ratio.
1369 *
1370 * The most significant 64-N bits (mult) of ratio represent the
1371 * integral part of the fixed point number; the remaining N bits
1372 * (frac) represent the fractional part, ie. ratio represents a fixed
1373 * point number (mult + frac * 2^(-N)).
1374 *
1375 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1376 */
1377 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1378 {
1379 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1380 }
1381
1382 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1383 {
1384 u64 _tsc = tsc;
1385 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1386
1387 if (ratio != kvm_default_tsc_scaling_ratio)
1388 _tsc = __scale_tsc(ratio, tsc);
1389
1390 return _tsc;
1391 }
1392 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1393
1394 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1395 {
1396 u64 tsc;
1397
1398 tsc = kvm_scale_tsc(vcpu, rdtsc());
1399
1400 return target_tsc - tsc;
1401 }
1402
1403 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1404 {
1405 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1406 }
1407 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1408
1409 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1410 {
1411 struct kvm *kvm = vcpu->kvm;
1412 u64 offset, ns, elapsed;
1413 unsigned long flags;
1414 s64 usdiff;
1415 bool matched;
1416 bool already_matched;
1417 u64 data = msr->data;
1418
1419 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1420 offset = kvm_compute_tsc_offset(vcpu, data);
1421 ns = get_kernel_ns();
1422 elapsed = ns - kvm->arch.last_tsc_nsec;
1423
1424 if (vcpu->arch.virtual_tsc_khz) {
1425 int faulted = 0;
1426
1427 /* n.b - signed multiplication and division required */
1428 usdiff = data - kvm->arch.last_tsc_write;
1429 #ifdef CONFIG_X86_64
1430 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1431 #else
1432 /* do_div() only does unsigned */
1433 asm("1: idivl %[divisor]\n"
1434 "2: xor %%edx, %%edx\n"
1435 " movl $0, %[faulted]\n"
1436 "3:\n"
1437 ".section .fixup,\"ax\"\n"
1438 "4: movl $1, %[faulted]\n"
1439 " jmp 3b\n"
1440 ".previous\n"
1441
1442 _ASM_EXTABLE(1b, 4b)
1443
1444 : "=A"(usdiff), [faulted] "=r" (faulted)
1445 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1446
1447 #endif
1448 do_div(elapsed, 1000);
1449 usdiff -= elapsed;
1450 if (usdiff < 0)
1451 usdiff = -usdiff;
1452
1453 /* idivl overflow => difference is larger than USEC_PER_SEC */
1454 if (faulted)
1455 usdiff = USEC_PER_SEC;
1456 } else
1457 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1458
1459 /*
1460 * Special case: TSC write with a small delta (1 second) of virtual
1461 * cycle time against real time is interpreted as an attempt to
1462 * synchronize the CPU.
1463 *
1464 * For a reliable TSC, we can match TSC offsets, and for an unstable
1465 * TSC, we add elapsed time in this computation. We could let the
1466 * compensation code attempt to catch up if we fall behind, but
1467 * it's better to try to match offsets from the beginning.
1468 */
1469 if (usdiff < USEC_PER_SEC &&
1470 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1471 if (!check_tsc_unstable()) {
1472 offset = kvm->arch.cur_tsc_offset;
1473 pr_debug("kvm: matched tsc offset for %llu\n", data);
1474 } else {
1475 u64 delta = nsec_to_cycles(vcpu, elapsed);
1476 data += delta;
1477 offset = kvm_compute_tsc_offset(vcpu, data);
1478 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1479 }
1480 matched = true;
1481 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1482 } else {
1483 /*
1484 * We split periods of matched TSC writes into generations.
1485 * For each generation, we track the original measured
1486 * nanosecond time, offset, and write, so if TSCs are in
1487 * sync, we can match exact offset, and if not, we can match
1488 * exact software computation in compute_guest_tsc()
1489 *
1490 * These values are tracked in kvm->arch.cur_xxx variables.
1491 */
1492 kvm->arch.cur_tsc_generation++;
1493 kvm->arch.cur_tsc_nsec = ns;
1494 kvm->arch.cur_tsc_write = data;
1495 kvm->arch.cur_tsc_offset = offset;
1496 matched = false;
1497 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1498 kvm->arch.cur_tsc_generation, data);
1499 }
1500
1501 /*
1502 * We also track th most recent recorded KHZ, write and time to
1503 * allow the matching interval to be extended at each write.
1504 */
1505 kvm->arch.last_tsc_nsec = ns;
1506 kvm->arch.last_tsc_write = data;
1507 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1508
1509 vcpu->arch.last_guest_tsc = data;
1510
1511 /* Keep track of which generation this VCPU has synchronized to */
1512 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1513 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1514 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1515
1516 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1517 update_ia32_tsc_adjust_msr(vcpu, offset);
1518 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1519 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1520
1521 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1522 if (!matched) {
1523 kvm->arch.nr_vcpus_matched_tsc = 0;
1524 } else if (!already_matched) {
1525 kvm->arch.nr_vcpus_matched_tsc++;
1526 }
1527
1528 kvm_track_tsc_matching(vcpu);
1529 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1530 }
1531
1532 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1533
1534 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1535 s64 adjustment)
1536 {
1537 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1538 }
1539
1540 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1541 {
1542 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1543 WARN_ON(adjustment < 0);
1544 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1545 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1546 }
1547
1548 #ifdef CONFIG_X86_64
1549
1550 static cycle_t read_tsc(void)
1551 {
1552 cycle_t ret = (cycle_t)rdtsc_ordered();
1553 u64 last = pvclock_gtod_data.clock.cycle_last;
1554
1555 if (likely(ret >= last))
1556 return ret;
1557
1558 /*
1559 * GCC likes to generate cmov here, but this branch is extremely
1560 * predictable (it's just a function of time and the likely is
1561 * very likely) and there's a data dependence, so force GCC
1562 * to generate a branch instead. I don't barrier() because
1563 * we don't actually need a barrier, and if this function
1564 * ever gets inlined it will generate worse code.
1565 */
1566 asm volatile ("");
1567 return last;
1568 }
1569
1570 static inline u64 vgettsc(cycle_t *cycle_now)
1571 {
1572 long v;
1573 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1574
1575 *cycle_now = read_tsc();
1576
1577 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1578 return v * gtod->clock.mult;
1579 }
1580
1581 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1582 {
1583 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1584 unsigned long seq;
1585 int mode;
1586 u64 ns;
1587
1588 do {
1589 seq = read_seqcount_begin(&gtod->seq);
1590 mode = gtod->clock.vclock_mode;
1591 ns = gtod->nsec_base;
1592 ns += vgettsc(cycle_now);
1593 ns >>= gtod->clock.shift;
1594 ns += gtod->boot_ns;
1595 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1596 *t = ns;
1597
1598 return mode;
1599 }
1600
1601 /* returns true if host is using tsc clocksource */
1602 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1603 {
1604 /* checked again under seqlock below */
1605 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1606 return false;
1607
1608 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1609 }
1610 #endif
1611
1612 /*
1613 *
1614 * Assuming a stable TSC across physical CPUS, and a stable TSC
1615 * across virtual CPUs, the following condition is possible.
1616 * Each numbered line represents an event visible to both
1617 * CPUs at the next numbered event.
1618 *
1619 * "timespecX" represents host monotonic time. "tscX" represents
1620 * RDTSC value.
1621 *
1622 * VCPU0 on CPU0 | VCPU1 on CPU1
1623 *
1624 * 1. read timespec0,tsc0
1625 * 2. | timespec1 = timespec0 + N
1626 * | tsc1 = tsc0 + M
1627 * 3. transition to guest | transition to guest
1628 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1629 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1630 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1631 *
1632 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1633 *
1634 * - ret0 < ret1
1635 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1636 * ...
1637 * - 0 < N - M => M < N
1638 *
1639 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1640 * always the case (the difference between two distinct xtime instances
1641 * might be smaller then the difference between corresponding TSC reads,
1642 * when updating guest vcpus pvclock areas).
1643 *
1644 * To avoid that problem, do not allow visibility of distinct
1645 * system_timestamp/tsc_timestamp values simultaneously: use a master
1646 * copy of host monotonic time values. Update that master copy
1647 * in lockstep.
1648 *
1649 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1650 *
1651 */
1652
1653 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1654 {
1655 #ifdef CONFIG_X86_64
1656 struct kvm_arch *ka = &kvm->arch;
1657 int vclock_mode;
1658 bool host_tsc_clocksource, vcpus_matched;
1659
1660 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1661 atomic_read(&kvm->online_vcpus));
1662
1663 /*
1664 * If the host uses TSC clock, then passthrough TSC as stable
1665 * to the guest.
1666 */
1667 host_tsc_clocksource = kvm_get_time_and_clockread(
1668 &ka->master_kernel_ns,
1669 &ka->master_cycle_now);
1670
1671 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1672 && !backwards_tsc_observed
1673 && !ka->boot_vcpu_runs_old_kvmclock;
1674
1675 if (ka->use_master_clock)
1676 atomic_set(&kvm_guest_has_master_clock, 1);
1677
1678 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1679 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1680 vcpus_matched);
1681 #endif
1682 }
1683
1684 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1685 {
1686 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1687 }
1688
1689 static void kvm_gen_update_masterclock(struct kvm *kvm)
1690 {
1691 #ifdef CONFIG_X86_64
1692 int i;
1693 struct kvm_vcpu *vcpu;
1694 struct kvm_arch *ka = &kvm->arch;
1695
1696 spin_lock(&ka->pvclock_gtod_sync_lock);
1697 kvm_make_mclock_inprogress_request(kvm);
1698 /* no guest entries from this point */
1699 pvclock_update_vm_gtod_copy(kvm);
1700
1701 kvm_for_each_vcpu(i, vcpu, kvm)
1702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1703
1704 /* guest entries allowed */
1705 kvm_for_each_vcpu(i, vcpu, kvm)
1706 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1707
1708 spin_unlock(&ka->pvclock_gtod_sync_lock);
1709 #endif
1710 }
1711
1712 static int kvm_guest_time_update(struct kvm_vcpu *v)
1713 {
1714 unsigned long flags, tgt_tsc_khz;
1715 struct kvm_vcpu_arch *vcpu = &v->arch;
1716 struct kvm_arch *ka = &v->kvm->arch;
1717 s64 kernel_ns;
1718 u64 tsc_timestamp, host_tsc;
1719 struct pvclock_vcpu_time_info guest_hv_clock;
1720 u8 pvclock_flags;
1721 bool use_master_clock;
1722
1723 kernel_ns = 0;
1724 host_tsc = 0;
1725
1726 /*
1727 * If the host uses TSC clock, then passthrough TSC as stable
1728 * to the guest.
1729 */
1730 spin_lock(&ka->pvclock_gtod_sync_lock);
1731 use_master_clock = ka->use_master_clock;
1732 if (use_master_clock) {
1733 host_tsc = ka->master_cycle_now;
1734 kernel_ns = ka->master_kernel_ns;
1735 }
1736 spin_unlock(&ka->pvclock_gtod_sync_lock);
1737
1738 /* Keep irq disabled to prevent changes to the clock */
1739 local_irq_save(flags);
1740 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1741 if (unlikely(tgt_tsc_khz == 0)) {
1742 local_irq_restore(flags);
1743 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1744 return 1;
1745 }
1746 if (!use_master_clock) {
1747 host_tsc = rdtsc();
1748 kernel_ns = get_kernel_ns();
1749 }
1750
1751 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1752
1753 /*
1754 * We may have to catch up the TSC to match elapsed wall clock
1755 * time for two reasons, even if kvmclock is used.
1756 * 1) CPU could have been running below the maximum TSC rate
1757 * 2) Broken TSC compensation resets the base at each VCPU
1758 * entry to avoid unknown leaps of TSC even when running
1759 * again on the same CPU. This may cause apparent elapsed
1760 * time to disappear, and the guest to stand still or run
1761 * very slowly.
1762 */
1763 if (vcpu->tsc_catchup) {
1764 u64 tsc = compute_guest_tsc(v, kernel_ns);
1765 if (tsc > tsc_timestamp) {
1766 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1767 tsc_timestamp = tsc;
1768 }
1769 }
1770
1771 local_irq_restore(flags);
1772
1773 if (!vcpu->pv_time_enabled)
1774 return 0;
1775
1776 if (kvm_has_tsc_control)
1777 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1778
1779 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1780 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1781 &vcpu->hv_clock.tsc_shift,
1782 &vcpu->hv_clock.tsc_to_system_mul);
1783 vcpu->hw_tsc_khz = tgt_tsc_khz;
1784 }
1785
1786 /* With all the info we got, fill in the values */
1787 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1788 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1789 vcpu->last_guest_tsc = tsc_timestamp;
1790
1791 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1792 &guest_hv_clock, sizeof(guest_hv_clock))))
1793 return 0;
1794
1795 /* This VCPU is paused, but it's legal for a guest to read another
1796 * VCPU's kvmclock, so we really have to follow the specification where
1797 * it says that version is odd if data is being modified, and even after
1798 * it is consistent.
1799 *
1800 * Version field updates must be kept separate. This is because
1801 * kvm_write_guest_cached might use a "rep movs" instruction, and
1802 * writes within a string instruction are weakly ordered. So there
1803 * are three writes overall.
1804 *
1805 * As a small optimization, only write the version field in the first
1806 * and third write. The vcpu->pv_time cache is still valid, because the
1807 * version field is the first in the struct.
1808 */
1809 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1810
1811 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1812 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1813 &vcpu->hv_clock,
1814 sizeof(vcpu->hv_clock.version));
1815
1816 smp_wmb();
1817
1818 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1819 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1820
1821 if (vcpu->pvclock_set_guest_stopped_request) {
1822 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1823 vcpu->pvclock_set_guest_stopped_request = false;
1824 }
1825
1826 /* If the host uses TSC clocksource, then it is stable */
1827 if (use_master_clock)
1828 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1829
1830 vcpu->hv_clock.flags = pvclock_flags;
1831
1832 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1833
1834 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1835 &vcpu->hv_clock,
1836 sizeof(vcpu->hv_clock));
1837
1838 smp_wmb();
1839
1840 vcpu->hv_clock.version++;
1841 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1842 &vcpu->hv_clock,
1843 sizeof(vcpu->hv_clock.version));
1844 return 0;
1845 }
1846
1847 /*
1848 * kvmclock updates which are isolated to a given vcpu, such as
1849 * vcpu->cpu migration, should not allow system_timestamp from
1850 * the rest of the vcpus to remain static. Otherwise ntp frequency
1851 * correction applies to one vcpu's system_timestamp but not
1852 * the others.
1853 *
1854 * So in those cases, request a kvmclock update for all vcpus.
1855 * We need to rate-limit these requests though, as they can
1856 * considerably slow guests that have a large number of vcpus.
1857 * The time for a remote vcpu to update its kvmclock is bound
1858 * by the delay we use to rate-limit the updates.
1859 */
1860
1861 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1862
1863 static void kvmclock_update_fn(struct work_struct *work)
1864 {
1865 int i;
1866 struct delayed_work *dwork = to_delayed_work(work);
1867 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1868 kvmclock_update_work);
1869 struct kvm *kvm = container_of(ka, struct kvm, arch);
1870 struct kvm_vcpu *vcpu;
1871
1872 kvm_for_each_vcpu(i, vcpu, kvm) {
1873 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1874 kvm_vcpu_kick(vcpu);
1875 }
1876 }
1877
1878 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1879 {
1880 struct kvm *kvm = v->kvm;
1881
1882 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1883 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1884 KVMCLOCK_UPDATE_DELAY);
1885 }
1886
1887 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1888
1889 static void kvmclock_sync_fn(struct work_struct *work)
1890 {
1891 struct delayed_work *dwork = to_delayed_work(work);
1892 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1893 kvmclock_sync_work);
1894 struct kvm *kvm = container_of(ka, struct kvm, arch);
1895
1896 if (!kvmclock_periodic_sync)
1897 return;
1898
1899 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1900 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1901 KVMCLOCK_SYNC_PERIOD);
1902 }
1903
1904 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1905 {
1906 u64 mcg_cap = vcpu->arch.mcg_cap;
1907 unsigned bank_num = mcg_cap & 0xff;
1908
1909 switch (msr) {
1910 case MSR_IA32_MCG_STATUS:
1911 vcpu->arch.mcg_status = data;
1912 break;
1913 case MSR_IA32_MCG_CTL:
1914 if (!(mcg_cap & MCG_CTL_P))
1915 return 1;
1916 if (data != 0 && data != ~(u64)0)
1917 return -1;
1918 vcpu->arch.mcg_ctl = data;
1919 break;
1920 default:
1921 if (msr >= MSR_IA32_MC0_CTL &&
1922 msr < MSR_IA32_MCx_CTL(bank_num)) {
1923 u32 offset = msr - MSR_IA32_MC0_CTL;
1924 /* only 0 or all 1s can be written to IA32_MCi_CTL
1925 * some Linux kernels though clear bit 10 in bank 4 to
1926 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1927 * this to avoid an uncatched #GP in the guest
1928 */
1929 if ((offset & 0x3) == 0 &&
1930 data != 0 && (data | (1 << 10)) != ~(u64)0)
1931 return -1;
1932 vcpu->arch.mce_banks[offset] = data;
1933 break;
1934 }
1935 return 1;
1936 }
1937 return 0;
1938 }
1939
1940 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1941 {
1942 struct kvm *kvm = vcpu->kvm;
1943 int lm = is_long_mode(vcpu);
1944 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1945 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1946 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1947 : kvm->arch.xen_hvm_config.blob_size_32;
1948 u32 page_num = data & ~PAGE_MASK;
1949 u64 page_addr = data & PAGE_MASK;
1950 u8 *page;
1951 int r;
1952
1953 r = -E2BIG;
1954 if (page_num >= blob_size)
1955 goto out;
1956 r = -ENOMEM;
1957 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1958 if (IS_ERR(page)) {
1959 r = PTR_ERR(page);
1960 goto out;
1961 }
1962 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1963 goto out_free;
1964 r = 0;
1965 out_free:
1966 kfree(page);
1967 out:
1968 return r;
1969 }
1970
1971 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1972 {
1973 gpa_t gpa = data & ~0x3f;
1974
1975 /* Bits 2:5 are reserved, Should be zero */
1976 if (data & 0x3c)
1977 return 1;
1978
1979 vcpu->arch.apf.msr_val = data;
1980
1981 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1982 kvm_clear_async_pf_completion_queue(vcpu);
1983 kvm_async_pf_hash_reset(vcpu);
1984 return 0;
1985 }
1986
1987 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1988 sizeof(u32)))
1989 return 1;
1990
1991 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1992 kvm_async_pf_wakeup_all(vcpu);
1993 return 0;
1994 }
1995
1996 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1997 {
1998 vcpu->arch.pv_time_enabled = false;
1999 }
2000
2001 static void record_steal_time(struct kvm_vcpu *vcpu)
2002 {
2003 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2004 return;
2005
2006 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2007 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2008 return;
2009
2010 if (vcpu->arch.st.steal.version & 1)
2011 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2012
2013 vcpu->arch.st.steal.version += 1;
2014
2015 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2017
2018 smp_wmb();
2019
2020 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2021 vcpu->arch.st.last_steal;
2022 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2023
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2026
2027 smp_wmb();
2028
2029 vcpu->arch.st.steal.version += 1;
2030
2031 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2032 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2033 }
2034
2035 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2036 {
2037 bool pr = false;
2038 u32 msr = msr_info->index;
2039 u64 data = msr_info->data;
2040
2041 switch (msr) {
2042 case MSR_AMD64_NB_CFG:
2043 case MSR_IA32_UCODE_REV:
2044 case MSR_IA32_UCODE_WRITE:
2045 case MSR_VM_HSAVE_PA:
2046 case MSR_AMD64_PATCH_LOADER:
2047 case MSR_AMD64_BU_CFG2:
2048 break;
2049
2050 case MSR_EFER:
2051 return set_efer(vcpu, data);
2052 case MSR_K7_HWCR:
2053 data &= ~(u64)0x40; /* ignore flush filter disable */
2054 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2055 data &= ~(u64)0x8; /* ignore TLB cache disable */
2056 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2057 if (data != 0) {
2058 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2059 data);
2060 return 1;
2061 }
2062 break;
2063 case MSR_FAM10H_MMIO_CONF_BASE:
2064 if (data != 0) {
2065 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2066 "0x%llx\n", data);
2067 return 1;
2068 }
2069 break;
2070 case MSR_IA32_DEBUGCTLMSR:
2071 if (!data) {
2072 /* We support the non-activated case already */
2073 break;
2074 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2075 /* Values other than LBR and BTF are vendor-specific,
2076 thus reserved and should throw a #GP */
2077 return 1;
2078 }
2079 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2080 __func__, data);
2081 break;
2082 case 0x200 ... 0x2ff:
2083 return kvm_mtrr_set_msr(vcpu, msr, data);
2084 case MSR_IA32_APICBASE:
2085 return kvm_set_apic_base(vcpu, msr_info);
2086 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2087 return kvm_x2apic_msr_write(vcpu, msr, data);
2088 case MSR_IA32_TSCDEADLINE:
2089 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2090 break;
2091 case MSR_IA32_TSC_ADJUST:
2092 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2093 if (!msr_info->host_initiated) {
2094 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2095 adjust_tsc_offset_guest(vcpu, adj);
2096 }
2097 vcpu->arch.ia32_tsc_adjust_msr = data;
2098 }
2099 break;
2100 case MSR_IA32_MISC_ENABLE:
2101 vcpu->arch.ia32_misc_enable_msr = data;
2102 break;
2103 case MSR_IA32_SMBASE:
2104 if (!msr_info->host_initiated)
2105 return 1;
2106 vcpu->arch.smbase = data;
2107 break;
2108 case MSR_KVM_WALL_CLOCK_NEW:
2109 case MSR_KVM_WALL_CLOCK:
2110 vcpu->kvm->arch.wall_clock = data;
2111 kvm_write_wall_clock(vcpu->kvm, data);
2112 break;
2113 case MSR_KVM_SYSTEM_TIME_NEW:
2114 case MSR_KVM_SYSTEM_TIME: {
2115 u64 gpa_offset;
2116 struct kvm_arch *ka = &vcpu->kvm->arch;
2117
2118 kvmclock_reset(vcpu);
2119
2120 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2121 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2122
2123 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2124 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2125 &vcpu->requests);
2126
2127 ka->boot_vcpu_runs_old_kvmclock = tmp;
2128 }
2129
2130 vcpu->arch.time = data;
2131 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2132
2133 /* we verify if the enable bit is set... */
2134 if (!(data & 1))
2135 break;
2136
2137 gpa_offset = data & ~(PAGE_MASK | 1);
2138
2139 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2140 &vcpu->arch.pv_time, data & ~1ULL,
2141 sizeof(struct pvclock_vcpu_time_info)))
2142 vcpu->arch.pv_time_enabled = false;
2143 else
2144 vcpu->arch.pv_time_enabled = true;
2145
2146 break;
2147 }
2148 case MSR_KVM_ASYNC_PF_EN:
2149 if (kvm_pv_enable_async_pf(vcpu, data))
2150 return 1;
2151 break;
2152 case MSR_KVM_STEAL_TIME:
2153
2154 if (unlikely(!sched_info_on()))
2155 return 1;
2156
2157 if (data & KVM_STEAL_RESERVED_MASK)
2158 return 1;
2159
2160 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2161 data & KVM_STEAL_VALID_BITS,
2162 sizeof(struct kvm_steal_time)))
2163 return 1;
2164
2165 vcpu->arch.st.msr_val = data;
2166
2167 if (!(data & KVM_MSR_ENABLED))
2168 break;
2169
2170 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2171
2172 break;
2173 case MSR_KVM_PV_EOI_EN:
2174 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2175 return 1;
2176 break;
2177
2178 case MSR_IA32_MCG_CTL:
2179 case MSR_IA32_MCG_STATUS:
2180 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2181 return set_msr_mce(vcpu, msr, data);
2182
2183 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2184 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2185 pr = true; /* fall through */
2186 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2187 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2188 if (kvm_pmu_is_valid_msr(vcpu, msr))
2189 return kvm_pmu_set_msr(vcpu, msr_info);
2190
2191 if (pr || data != 0)
2192 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2193 "0x%x data 0x%llx\n", msr, data);
2194 break;
2195 case MSR_K7_CLK_CTL:
2196 /*
2197 * Ignore all writes to this no longer documented MSR.
2198 * Writes are only relevant for old K7 processors,
2199 * all pre-dating SVM, but a recommended workaround from
2200 * AMD for these chips. It is possible to specify the
2201 * affected processor models on the command line, hence
2202 * the need to ignore the workaround.
2203 */
2204 break;
2205 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2206 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2207 case HV_X64_MSR_CRASH_CTL:
2208 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2209 return kvm_hv_set_msr_common(vcpu, msr, data,
2210 msr_info->host_initiated);
2211 case MSR_IA32_BBL_CR_CTL3:
2212 /* Drop writes to this legacy MSR -- see rdmsr
2213 * counterpart for further detail.
2214 */
2215 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2216 break;
2217 case MSR_AMD64_OSVW_ID_LENGTH:
2218 if (!guest_cpuid_has_osvw(vcpu))
2219 return 1;
2220 vcpu->arch.osvw.length = data;
2221 break;
2222 case MSR_AMD64_OSVW_STATUS:
2223 if (!guest_cpuid_has_osvw(vcpu))
2224 return 1;
2225 vcpu->arch.osvw.status = data;
2226 break;
2227 default:
2228 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2229 return xen_hvm_config(vcpu, data);
2230 if (kvm_pmu_is_valid_msr(vcpu, msr))
2231 return kvm_pmu_set_msr(vcpu, msr_info);
2232 if (!ignore_msrs) {
2233 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2234 msr, data);
2235 return 1;
2236 } else {
2237 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2238 msr, data);
2239 break;
2240 }
2241 }
2242 return 0;
2243 }
2244 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2245
2246
2247 /*
2248 * Reads an msr value (of 'msr_index') into 'pdata'.
2249 * Returns 0 on success, non-0 otherwise.
2250 * Assumes vcpu_load() was already called.
2251 */
2252 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2253 {
2254 return kvm_x86_ops->get_msr(vcpu, msr);
2255 }
2256 EXPORT_SYMBOL_GPL(kvm_get_msr);
2257
2258 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2259 {
2260 u64 data;
2261 u64 mcg_cap = vcpu->arch.mcg_cap;
2262 unsigned bank_num = mcg_cap & 0xff;
2263
2264 switch (msr) {
2265 case MSR_IA32_P5_MC_ADDR:
2266 case MSR_IA32_P5_MC_TYPE:
2267 data = 0;
2268 break;
2269 case MSR_IA32_MCG_CAP:
2270 data = vcpu->arch.mcg_cap;
2271 break;
2272 case MSR_IA32_MCG_CTL:
2273 if (!(mcg_cap & MCG_CTL_P))
2274 return 1;
2275 data = vcpu->arch.mcg_ctl;
2276 break;
2277 case MSR_IA32_MCG_STATUS:
2278 data = vcpu->arch.mcg_status;
2279 break;
2280 default:
2281 if (msr >= MSR_IA32_MC0_CTL &&
2282 msr < MSR_IA32_MCx_CTL(bank_num)) {
2283 u32 offset = msr - MSR_IA32_MC0_CTL;
2284 data = vcpu->arch.mce_banks[offset];
2285 break;
2286 }
2287 return 1;
2288 }
2289 *pdata = data;
2290 return 0;
2291 }
2292
2293 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2294 {
2295 switch (msr_info->index) {
2296 case MSR_IA32_PLATFORM_ID:
2297 case MSR_IA32_EBL_CR_POWERON:
2298 case MSR_IA32_DEBUGCTLMSR:
2299 case MSR_IA32_LASTBRANCHFROMIP:
2300 case MSR_IA32_LASTBRANCHTOIP:
2301 case MSR_IA32_LASTINTFROMIP:
2302 case MSR_IA32_LASTINTTOIP:
2303 case MSR_K8_SYSCFG:
2304 case MSR_K8_TSEG_ADDR:
2305 case MSR_K8_TSEG_MASK:
2306 case MSR_K7_HWCR:
2307 case MSR_VM_HSAVE_PA:
2308 case MSR_K8_INT_PENDING_MSG:
2309 case MSR_AMD64_NB_CFG:
2310 case MSR_FAM10H_MMIO_CONF_BASE:
2311 case MSR_AMD64_BU_CFG2:
2312 case MSR_IA32_PERF_CTL:
2313 msr_info->data = 0;
2314 break;
2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2321 msr_info->data = 0;
2322 break;
2323 case MSR_IA32_UCODE_REV:
2324 msr_info->data = 0x100000000ULL;
2325 break;
2326 case MSR_MTRRcap:
2327 case 0x200 ... 0x2ff:
2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2329 case 0xcd: /* fsb frequency */
2330 msr_info->data = 3;
2331 break;
2332 /*
2333 * MSR_EBC_FREQUENCY_ID
2334 * Conservative value valid for even the basic CPU models.
2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2337 * and 266MHz for model 3, or 4. Set Core Clock
2338 * Frequency to System Bus Frequency Ratio to 1 (bits
2339 * 31:24) even though these are only valid for CPU
2340 * models > 2, however guests may end up dividing or
2341 * multiplying by zero otherwise.
2342 */
2343 case MSR_EBC_FREQUENCY_ID:
2344 msr_info->data = 1 << 24;
2345 break;
2346 case MSR_IA32_APICBASE:
2347 msr_info->data = kvm_get_apic_base(vcpu);
2348 break;
2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2351 break;
2352 case MSR_IA32_TSCDEADLINE:
2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2354 break;
2355 case MSR_IA32_TSC_ADJUST:
2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2357 break;
2358 case MSR_IA32_MISC_ENABLE:
2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2360 break;
2361 case MSR_IA32_SMBASE:
2362 if (!msr_info->host_initiated)
2363 return 1;
2364 msr_info->data = vcpu->arch.smbase;
2365 break;
2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
2368 msr_info->data = 1000ULL;
2369 /* CPU multiplier */
2370 msr_info->data |= (((uint64_t)4ULL) << 40);
2371 break;
2372 case MSR_EFER:
2373 msr_info->data = vcpu->arch.efer;
2374 break;
2375 case MSR_KVM_WALL_CLOCK:
2376 case MSR_KVM_WALL_CLOCK_NEW:
2377 msr_info->data = vcpu->kvm->arch.wall_clock;
2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
2380 case MSR_KVM_SYSTEM_TIME_NEW:
2381 msr_info->data = vcpu->arch.time;
2382 break;
2383 case MSR_KVM_ASYNC_PF_EN:
2384 msr_info->data = vcpu->arch.apf.msr_val;
2385 break;
2386 case MSR_KVM_STEAL_TIME:
2387 msr_info->data = vcpu->arch.st.msr_val;
2388 break;
2389 case MSR_KVM_PV_EOI_EN:
2390 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2391 break;
2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
2409 msr_info->data = 0x20000000;
2410 break;
2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2413 case HV_X64_MSR_CRASH_CTL:
2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2415 return kvm_hv_get_msr_common(vcpu,
2416 msr_info->index, &msr_info->data);
2417 break;
2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* This legacy MSR exists but isn't fully documented in current
2420 * silicon. It is however accessed by winxp in very narrow
2421 * scenarios where it sets bit #19, itself documented as
2422 * a "reserved" bit. Best effort attempt to source coherent
2423 * read data here should the balance of the register be
2424 * interpreted by the guest:
2425 *
2426 * L2 cache control register 3: 64GB range, 256KB size,
2427 * enabled, latency 0x1, configured
2428 */
2429 msr_info->data = 0xbe702111;
2430 break;
2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
2434 msr_info->data = vcpu->arch.osvw.length;
2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
2439 msr_info->data = vcpu->arch.osvw.status;
2440 break;
2441 default:
2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2444 if (!ignore_msrs) {
2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2446 return 1;
2447 } else {
2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2449 msr_info->data = 0;
2450 }
2451 break;
2452 }
2453 return 0;
2454 }
2455 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2456
2457 /*
2458 * Read or write a bunch of msrs. All parameters are kernel addresses.
2459 *
2460 * @return number of msrs set successfully.
2461 */
2462 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2463 struct kvm_msr_entry *entries,
2464 int (*do_msr)(struct kvm_vcpu *vcpu,
2465 unsigned index, u64 *data))
2466 {
2467 int i, idx;
2468
2469 idx = srcu_read_lock(&vcpu->kvm->srcu);
2470 for (i = 0; i < msrs->nmsrs; ++i)
2471 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2472 break;
2473 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2474
2475 return i;
2476 }
2477
2478 /*
2479 * Read or write a bunch of msrs. Parameters are user addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2484 int (*do_msr)(struct kvm_vcpu *vcpu,
2485 unsigned index, u64 *data),
2486 int writeback)
2487 {
2488 struct kvm_msrs msrs;
2489 struct kvm_msr_entry *entries;
2490 int r, n;
2491 unsigned size;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2495 goto out;
2496
2497 r = -E2BIG;
2498 if (msrs.nmsrs >= MAX_IO_MSRS)
2499 goto out;
2500
2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2502 entries = memdup_user(user_msrs->entries, size);
2503 if (IS_ERR(entries)) {
2504 r = PTR_ERR(entries);
2505 goto out;
2506 }
2507
2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2509 if (r < 0)
2510 goto out_free;
2511
2512 r = -EFAULT;
2513 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 goto out_free;
2515
2516 r = n;
2517
2518 out_free:
2519 kfree(entries);
2520 out:
2521 return r;
2522 }
2523
2524 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2525 {
2526 int r;
2527
2528 switch (ext) {
2529 case KVM_CAP_IRQCHIP:
2530 case KVM_CAP_HLT:
2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2532 case KVM_CAP_SET_TSS_ADDR:
2533 case KVM_CAP_EXT_CPUID:
2534 case KVM_CAP_EXT_EMUL_CPUID:
2535 case KVM_CAP_CLOCKSOURCE:
2536 case KVM_CAP_PIT:
2537 case KVM_CAP_NOP_IO_DELAY:
2538 case KVM_CAP_MP_STATE:
2539 case KVM_CAP_SYNC_MMU:
2540 case KVM_CAP_USER_NMI:
2541 case KVM_CAP_REINJECT_CONTROL:
2542 case KVM_CAP_IRQ_INJECT_STATUS:
2543 case KVM_CAP_IOEVENTFD:
2544 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2545 case KVM_CAP_PIT2:
2546 case KVM_CAP_PIT_STATE2:
2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2548 case KVM_CAP_XEN_HVM:
2549 case KVM_CAP_ADJUST_CLOCK:
2550 case KVM_CAP_VCPU_EVENTS:
2551 case KVM_CAP_HYPERV:
2552 case KVM_CAP_HYPERV_VAPIC:
2553 case KVM_CAP_HYPERV_SPIN:
2554 case KVM_CAP_HYPERV_SYNIC:
2555 case KVM_CAP_PCI_SEGMENT:
2556 case KVM_CAP_DEBUGREGS:
2557 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2558 case KVM_CAP_XSAVE:
2559 case KVM_CAP_ASYNC_PF:
2560 case KVM_CAP_GET_TSC_KHZ:
2561 case KVM_CAP_KVMCLOCK_CTRL:
2562 case KVM_CAP_READONLY_MEM:
2563 case KVM_CAP_HYPERV_TIME:
2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2565 case KVM_CAP_TSC_DEADLINE_TIMER:
2566 case KVM_CAP_ENABLE_CAP_VM:
2567 case KVM_CAP_DISABLE_QUIRKS:
2568 case KVM_CAP_SET_BOOT_CPU_ID:
2569 case KVM_CAP_SPLIT_IRQCHIP:
2570 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2571 case KVM_CAP_ASSIGN_DEV_IRQ:
2572 case KVM_CAP_PCI_2_3:
2573 #endif
2574 r = 1;
2575 break;
2576 case KVM_CAP_X86_SMM:
2577 /* SMBASE is usually relocated above 1M on modern chipsets,
2578 * and SMM handlers might indeed rely on 4G segment limits,
2579 * so do not report SMM to be available if real mode is
2580 * emulated via vm86 mode. Still, do not go to great lengths
2581 * to avoid userspace's usage of the feature, because it is a
2582 * fringe case that is not enabled except via specific settings
2583 * of the module parameters.
2584 */
2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2586 break;
2587 case KVM_CAP_COALESCED_MMIO:
2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2589 break;
2590 case KVM_CAP_VAPIC:
2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2592 break;
2593 case KVM_CAP_NR_VCPUS:
2594 r = KVM_SOFT_MAX_VCPUS;
2595 break;
2596 case KVM_CAP_MAX_VCPUS:
2597 r = KVM_MAX_VCPUS;
2598 break;
2599 case KVM_CAP_NR_MEMSLOTS:
2600 r = KVM_USER_MEM_SLOTS;
2601 break;
2602 case KVM_CAP_PV_MMU: /* obsolete */
2603 r = 0;
2604 break;
2605 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2606 case KVM_CAP_IOMMU:
2607 r = iommu_present(&pci_bus_type);
2608 break;
2609 #endif
2610 case KVM_CAP_MCE:
2611 r = KVM_MAX_MCE_BANKS;
2612 break;
2613 case KVM_CAP_XCRS:
2614 r = boot_cpu_has(X86_FEATURE_XSAVE);
2615 break;
2616 case KVM_CAP_TSC_CONTROL:
2617 r = kvm_has_tsc_control;
2618 break;
2619 default:
2620 r = 0;
2621 break;
2622 }
2623 return r;
2624
2625 }
2626
2627 long kvm_arch_dev_ioctl(struct file *filp,
2628 unsigned int ioctl, unsigned long arg)
2629 {
2630 void __user *argp = (void __user *)arg;
2631 long r;
2632
2633 switch (ioctl) {
2634 case KVM_GET_MSR_INDEX_LIST: {
2635 struct kvm_msr_list __user *user_msr_list = argp;
2636 struct kvm_msr_list msr_list;
2637 unsigned n;
2638
2639 r = -EFAULT;
2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2641 goto out;
2642 n = msr_list.nmsrs;
2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2645 goto out;
2646 r = -E2BIG;
2647 if (n < msr_list.nmsrs)
2648 goto out;
2649 r = -EFAULT;
2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2651 num_msrs_to_save * sizeof(u32)))
2652 goto out;
2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2654 &emulated_msrs,
2655 num_emulated_msrs * sizeof(u32)))
2656 goto out;
2657 r = 0;
2658 break;
2659 }
2660 case KVM_GET_SUPPORTED_CPUID:
2661 case KVM_GET_EMULATED_CPUID: {
2662 struct kvm_cpuid2 __user *cpuid_arg = argp;
2663 struct kvm_cpuid2 cpuid;
2664
2665 r = -EFAULT;
2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2667 goto out;
2668
2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2670 ioctl);
2671 if (r)
2672 goto out;
2673
2674 r = -EFAULT;
2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2676 goto out;
2677 r = 0;
2678 break;
2679 }
2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2681 u64 mce_cap;
2682
2683 mce_cap = KVM_MCE_CAP_SUPPORTED;
2684 r = -EFAULT;
2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
2690 default:
2691 r = -EINVAL;
2692 }
2693 out:
2694 return r;
2695 }
2696
2697 static void wbinvd_ipi(void *garbage)
2698 {
2699 wbinvd();
2700 }
2701
2702 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2703 {
2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2705 }
2706
2707 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2708 {
2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2710 }
2711
2712 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2713 {
2714 /* Address WBINVD may be executed by guest */
2715 if (need_emulate_wbinvd(vcpu)) {
2716 if (kvm_x86_ops->has_wbinvd_exit())
2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2719 smp_call_function_single(vcpu->cpu,
2720 wbinvd_ipi, NULL, 1);
2721 }
2722
2723 kvm_x86_ops->vcpu_load(vcpu, cpu);
2724
2725 /* Apply any externally detected TSC adjustments (due to suspend) */
2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2728 vcpu->arch.tsc_offset_adjustment = 0;
2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2730 }
2731
2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2734 rdtsc() - vcpu->arch.last_host_tsc;
2735 if (tsc_delta < 0)
2736 mark_tsc_unstable("KVM discovered backwards TSC");
2737 if (check_tsc_unstable()) {
2738 u64 offset = kvm_compute_tsc_offset(vcpu,
2739 vcpu->arch.last_guest_tsc);
2740 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2741 vcpu->arch.tsc_catchup = 1;
2742 }
2743 /*
2744 * On a host with synchronized TSC, there is no need to update
2745 * kvmclock on vcpu->cpu migration
2746 */
2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2749 if (vcpu->cpu != cpu)
2750 kvm_migrate_timers(vcpu);
2751 vcpu->cpu = cpu;
2752 }
2753
2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2755 }
2756
2757 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2758 {
2759 kvm_x86_ops->vcpu_put(vcpu);
2760 kvm_put_guest_fpu(vcpu);
2761 vcpu->arch.last_host_tsc = rdtsc();
2762 }
2763
2764 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2765 struct kvm_lapic_state *s)
2766 {
2767 if (vcpu->arch.apicv_active)
2768 kvm_x86_ops->sync_pir_to_irr(vcpu);
2769
2770 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2771
2772 return 0;
2773 }
2774
2775 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2776 struct kvm_lapic_state *s)
2777 {
2778 kvm_apic_post_state_restore(vcpu, s);
2779 update_cr8_intercept(vcpu);
2780
2781 return 0;
2782 }
2783
2784 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2785 {
2786 return (!lapic_in_kernel(vcpu) ||
2787 kvm_apic_accept_pic_intr(vcpu));
2788 }
2789
2790 /*
2791 * if userspace requested an interrupt window, check that the
2792 * interrupt window is open.
2793 *
2794 * No need to exit to userspace if we already have an interrupt queued.
2795 */
2796 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2797 {
2798 return kvm_arch_interrupt_allowed(vcpu) &&
2799 !kvm_cpu_has_interrupt(vcpu) &&
2800 !kvm_event_needs_reinjection(vcpu) &&
2801 kvm_cpu_accept_dm_intr(vcpu);
2802 }
2803
2804 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2805 struct kvm_interrupt *irq)
2806 {
2807 if (irq->irq >= KVM_NR_INTERRUPTS)
2808 return -EINVAL;
2809
2810 if (!irqchip_in_kernel(vcpu->kvm)) {
2811 kvm_queue_interrupt(vcpu, irq->irq, false);
2812 kvm_make_request(KVM_REQ_EVENT, vcpu);
2813 return 0;
2814 }
2815
2816 /*
2817 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2818 * fail for in-kernel 8259.
2819 */
2820 if (pic_in_kernel(vcpu->kvm))
2821 return -ENXIO;
2822
2823 if (vcpu->arch.pending_external_vector != -1)
2824 return -EEXIST;
2825
2826 vcpu->arch.pending_external_vector = irq->irq;
2827 kvm_make_request(KVM_REQ_EVENT, vcpu);
2828 return 0;
2829 }
2830
2831 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2832 {
2833 kvm_inject_nmi(vcpu);
2834
2835 return 0;
2836 }
2837
2838 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2839 {
2840 kvm_make_request(KVM_REQ_SMI, vcpu);
2841
2842 return 0;
2843 }
2844
2845 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2846 struct kvm_tpr_access_ctl *tac)
2847 {
2848 if (tac->flags)
2849 return -EINVAL;
2850 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2851 return 0;
2852 }
2853
2854 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2855 u64 mcg_cap)
2856 {
2857 int r;
2858 unsigned bank_num = mcg_cap & 0xff, bank;
2859
2860 r = -EINVAL;
2861 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2862 goto out;
2863 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2864 goto out;
2865 r = 0;
2866 vcpu->arch.mcg_cap = mcg_cap;
2867 /* Init IA32_MCG_CTL to all 1s */
2868 if (mcg_cap & MCG_CTL_P)
2869 vcpu->arch.mcg_ctl = ~(u64)0;
2870 /* Init IA32_MCi_CTL to all 1s */
2871 for (bank = 0; bank < bank_num; bank++)
2872 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2873 out:
2874 return r;
2875 }
2876
2877 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2878 struct kvm_x86_mce *mce)
2879 {
2880 u64 mcg_cap = vcpu->arch.mcg_cap;
2881 unsigned bank_num = mcg_cap & 0xff;
2882 u64 *banks = vcpu->arch.mce_banks;
2883
2884 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2885 return -EINVAL;
2886 /*
2887 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2888 * reporting is disabled
2889 */
2890 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2891 vcpu->arch.mcg_ctl != ~(u64)0)
2892 return 0;
2893 banks += 4 * mce->bank;
2894 /*
2895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2896 * reporting is disabled for the bank
2897 */
2898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2899 return 0;
2900 if (mce->status & MCI_STATUS_UC) {
2901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2902 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2903 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2904 return 0;
2905 }
2906 if (banks[1] & MCI_STATUS_VAL)
2907 mce->status |= MCI_STATUS_OVER;
2908 banks[2] = mce->addr;
2909 banks[3] = mce->misc;
2910 vcpu->arch.mcg_status = mce->mcg_status;
2911 banks[1] = mce->status;
2912 kvm_queue_exception(vcpu, MC_VECTOR);
2913 } else if (!(banks[1] & MCI_STATUS_VAL)
2914 || !(banks[1] & MCI_STATUS_UC)) {
2915 if (banks[1] & MCI_STATUS_VAL)
2916 mce->status |= MCI_STATUS_OVER;
2917 banks[2] = mce->addr;
2918 banks[3] = mce->misc;
2919 banks[1] = mce->status;
2920 } else
2921 banks[1] |= MCI_STATUS_OVER;
2922 return 0;
2923 }
2924
2925 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927 {
2928 process_nmi(vcpu);
2929 events->exception.injected =
2930 vcpu->arch.exception.pending &&
2931 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2932 events->exception.nr = vcpu->arch.exception.nr;
2933 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2934 events->exception.pad = 0;
2935 events->exception.error_code = vcpu->arch.exception.error_code;
2936
2937 events->interrupt.injected =
2938 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2939 events->interrupt.nr = vcpu->arch.interrupt.nr;
2940 events->interrupt.soft = 0;
2941 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2942
2943 events->nmi.injected = vcpu->arch.nmi_injected;
2944 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2945 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2946 events->nmi.pad = 0;
2947
2948 events->sipi_vector = 0; /* never valid when reporting to user space */
2949
2950 events->smi.smm = is_smm(vcpu);
2951 events->smi.pending = vcpu->arch.smi_pending;
2952 events->smi.smm_inside_nmi =
2953 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2954 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2955
2956 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2957 | KVM_VCPUEVENT_VALID_SHADOW
2958 | KVM_VCPUEVENT_VALID_SMM);
2959 memset(&events->reserved, 0, sizeof(events->reserved));
2960 }
2961
2962 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964 {
2965 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2966 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2967 | KVM_VCPUEVENT_VALID_SHADOW
2968 | KVM_VCPUEVENT_VALID_SMM))
2969 return -EINVAL;
2970
2971 if (events->exception.injected &&
2972 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2973 return -EINVAL;
2974
2975 process_nmi(vcpu);
2976 vcpu->arch.exception.pending = events->exception.injected;
2977 vcpu->arch.exception.nr = events->exception.nr;
2978 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2979 vcpu->arch.exception.error_code = events->exception.error_code;
2980
2981 vcpu->arch.interrupt.pending = events->interrupt.injected;
2982 vcpu->arch.interrupt.nr = events->interrupt.nr;
2983 vcpu->arch.interrupt.soft = events->interrupt.soft;
2984 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2985 kvm_x86_ops->set_interrupt_shadow(vcpu,
2986 events->interrupt.shadow);
2987
2988 vcpu->arch.nmi_injected = events->nmi.injected;
2989 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2990 vcpu->arch.nmi_pending = events->nmi.pending;
2991 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2992
2993 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2994 lapic_in_kernel(vcpu))
2995 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2996
2997 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2998 if (events->smi.smm)
2999 vcpu->arch.hflags |= HF_SMM_MASK;
3000 else
3001 vcpu->arch.hflags &= ~HF_SMM_MASK;
3002 vcpu->arch.smi_pending = events->smi.pending;
3003 if (events->smi.smm_inside_nmi)
3004 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3005 else
3006 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3007 if (lapic_in_kernel(vcpu)) {
3008 if (events->smi.latched_init)
3009 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3010 else
3011 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3012 }
3013 }
3014
3015 kvm_make_request(KVM_REQ_EVENT, vcpu);
3016
3017 return 0;
3018 }
3019
3020 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3021 struct kvm_debugregs *dbgregs)
3022 {
3023 unsigned long val;
3024
3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3026 kvm_get_dr(vcpu, 6, &val);
3027 dbgregs->dr6 = val;
3028 dbgregs->dr7 = vcpu->arch.dr7;
3029 dbgregs->flags = 0;
3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3031 }
3032
3033 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3034 struct kvm_debugregs *dbgregs)
3035 {
3036 if (dbgregs->flags)
3037 return -EINVAL;
3038
3039 if (dbgregs->dr6 & ~0xffffffffull)
3040 return -EINVAL;
3041 if (dbgregs->dr7 & ~0xffffffffull)
3042 return -EINVAL;
3043
3044 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3045 kvm_update_dr0123(vcpu);
3046 vcpu->arch.dr6 = dbgregs->dr6;
3047 kvm_update_dr6(vcpu);
3048 vcpu->arch.dr7 = dbgregs->dr7;
3049 kvm_update_dr7(vcpu);
3050
3051 return 0;
3052 }
3053
3054 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3055
3056 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3057 {
3058 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3059 u64 xstate_bv = xsave->header.xfeatures;
3060 u64 valid;
3061
3062 /*
3063 * Copy legacy XSAVE area, to avoid complications with CPUID
3064 * leaves 0 and 1 in the loop below.
3065 */
3066 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3067
3068 /* Set XSTATE_BV */
3069 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3070
3071 /*
3072 * Copy each region from the possibly compacted offset to the
3073 * non-compacted offset.
3074 */
3075 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3076 while (valid) {
3077 u64 feature = valid & -valid;
3078 int index = fls64(feature) - 1;
3079 void *src = get_xsave_addr(xsave, feature);
3080
3081 if (src) {
3082 u32 size, offset, ecx, edx;
3083 cpuid_count(XSTATE_CPUID, index,
3084 &size, &offset, &ecx, &edx);
3085 memcpy(dest + offset, src, size);
3086 }
3087
3088 valid -= feature;
3089 }
3090 }
3091
3092 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3093 {
3094 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3095 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3096 u64 valid;
3097
3098 /*
3099 * Copy legacy XSAVE area, to avoid complications with CPUID
3100 * leaves 0 and 1 in the loop below.
3101 */
3102 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3103
3104 /* Set XSTATE_BV and possibly XCOMP_BV. */
3105 xsave->header.xfeatures = xstate_bv;
3106 if (boot_cpu_has(X86_FEATURE_XSAVES))
3107 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3108
3109 /*
3110 * Copy each region from the non-compacted offset to the
3111 * possibly compacted offset.
3112 */
3113 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3114 while (valid) {
3115 u64 feature = valid & -valid;
3116 int index = fls64(feature) - 1;
3117 void *dest = get_xsave_addr(xsave, feature);
3118
3119 if (dest) {
3120 u32 size, offset, ecx, edx;
3121 cpuid_count(XSTATE_CPUID, index,
3122 &size, &offset, &ecx, &edx);
3123 memcpy(dest, src + offset, size);
3124 }
3125
3126 valid -= feature;
3127 }
3128 }
3129
3130 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3131 struct kvm_xsave *guest_xsave)
3132 {
3133 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3134 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3135 fill_xsave((u8 *) guest_xsave->region, vcpu);
3136 } else {
3137 memcpy(guest_xsave->region,
3138 &vcpu->arch.guest_fpu.state.fxsave,
3139 sizeof(struct fxregs_state));
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3141 XFEATURE_MASK_FPSSE;
3142 }
3143 }
3144
3145 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3146 struct kvm_xsave *guest_xsave)
3147 {
3148 u64 xstate_bv =
3149 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3150
3151 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3152 /*
3153 * Here we allow setting states that are not present in
3154 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3155 * with old userspace.
3156 */
3157 if (xstate_bv & ~kvm_supported_xcr0())
3158 return -EINVAL;
3159 load_xsave(vcpu, (u8 *)guest_xsave->region);
3160 } else {
3161 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3162 return -EINVAL;
3163 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3164 guest_xsave->region, sizeof(struct fxregs_state));
3165 }
3166 return 0;
3167 }
3168
3169 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3170 struct kvm_xcrs *guest_xcrs)
3171 {
3172 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3173 guest_xcrs->nr_xcrs = 0;
3174 return;
3175 }
3176
3177 guest_xcrs->nr_xcrs = 1;
3178 guest_xcrs->flags = 0;
3179 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3180 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3181 }
3182
3183 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3184 struct kvm_xcrs *guest_xcrs)
3185 {
3186 int i, r = 0;
3187
3188 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3189 return -EINVAL;
3190
3191 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3192 return -EINVAL;
3193
3194 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3195 /* Only support XCR0 currently */
3196 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3197 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3198 guest_xcrs->xcrs[i].value);
3199 break;
3200 }
3201 if (r)
3202 r = -EINVAL;
3203 return r;
3204 }
3205
3206 /*
3207 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3208 * stopped by the hypervisor. This function will be called from the host only.
3209 * EINVAL is returned when the host attempts to set the flag for a guest that
3210 * does not support pv clocks.
3211 */
3212 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3213 {
3214 if (!vcpu->arch.pv_time_enabled)
3215 return -EINVAL;
3216 vcpu->arch.pvclock_set_guest_stopped_request = true;
3217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3218 return 0;
3219 }
3220
3221 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3222 struct kvm_enable_cap *cap)
3223 {
3224 if (cap->flags)
3225 return -EINVAL;
3226
3227 switch (cap->cap) {
3228 case KVM_CAP_HYPERV_SYNIC:
3229 return kvm_hv_activate_synic(vcpu);
3230 default:
3231 return -EINVAL;
3232 }
3233 }
3234
3235 long kvm_arch_vcpu_ioctl(struct file *filp,
3236 unsigned int ioctl, unsigned long arg)
3237 {
3238 struct kvm_vcpu *vcpu = filp->private_data;
3239 void __user *argp = (void __user *)arg;
3240 int r;
3241 union {
3242 struct kvm_lapic_state *lapic;
3243 struct kvm_xsave *xsave;
3244 struct kvm_xcrs *xcrs;
3245 void *buffer;
3246 } u;
3247
3248 u.buffer = NULL;
3249 switch (ioctl) {
3250 case KVM_GET_LAPIC: {
3251 r = -EINVAL;
3252 if (!lapic_in_kernel(vcpu))
3253 goto out;
3254 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3255
3256 r = -ENOMEM;
3257 if (!u.lapic)
3258 goto out;
3259 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3260 if (r)
3261 goto out;
3262 r = -EFAULT;
3263 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3264 goto out;
3265 r = 0;
3266 break;
3267 }
3268 case KVM_SET_LAPIC: {
3269 r = -EINVAL;
3270 if (!lapic_in_kernel(vcpu))
3271 goto out;
3272 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3273 if (IS_ERR(u.lapic))
3274 return PTR_ERR(u.lapic);
3275
3276 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3277 break;
3278 }
3279 case KVM_INTERRUPT: {
3280 struct kvm_interrupt irq;
3281
3282 r = -EFAULT;
3283 if (copy_from_user(&irq, argp, sizeof irq))
3284 goto out;
3285 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3286 break;
3287 }
3288 case KVM_NMI: {
3289 r = kvm_vcpu_ioctl_nmi(vcpu);
3290 break;
3291 }
3292 case KVM_SMI: {
3293 r = kvm_vcpu_ioctl_smi(vcpu);
3294 break;
3295 }
3296 case KVM_SET_CPUID: {
3297 struct kvm_cpuid __user *cpuid_arg = argp;
3298 struct kvm_cpuid cpuid;
3299
3300 r = -EFAULT;
3301 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3302 goto out;
3303 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3304 break;
3305 }
3306 case KVM_SET_CPUID2: {
3307 struct kvm_cpuid2 __user *cpuid_arg = argp;
3308 struct kvm_cpuid2 cpuid;
3309
3310 r = -EFAULT;
3311 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3312 goto out;
3313 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3314 cpuid_arg->entries);
3315 break;
3316 }
3317 case KVM_GET_CPUID2: {
3318 struct kvm_cpuid2 __user *cpuid_arg = argp;
3319 struct kvm_cpuid2 cpuid;
3320
3321 r = -EFAULT;
3322 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3323 goto out;
3324 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3325 cpuid_arg->entries);
3326 if (r)
3327 goto out;
3328 r = -EFAULT;
3329 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3330 goto out;
3331 r = 0;
3332 break;
3333 }
3334 case KVM_GET_MSRS:
3335 r = msr_io(vcpu, argp, do_get_msr, 1);
3336 break;
3337 case KVM_SET_MSRS:
3338 r = msr_io(vcpu, argp, do_set_msr, 0);
3339 break;
3340 case KVM_TPR_ACCESS_REPORTING: {
3341 struct kvm_tpr_access_ctl tac;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&tac, argp, sizeof tac))
3345 goto out;
3346 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3347 if (r)
3348 goto out;
3349 r = -EFAULT;
3350 if (copy_to_user(argp, &tac, sizeof tac))
3351 goto out;
3352 r = 0;
3353 break;
3354 };
3355 case KVM_SET_VAPIC_ADDR: {
3356 struct kvm_vapic_addr va;
3357
3358 r = -EINVAL;
3359 if (!lapic_in_kernel(vcpu))
3360 goto out;
3361 r = -EFAULT;
3362 if (copy_from_user(&va, argp, sizeof va))
3363 goto out;
3364 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3365 break;
3366 }
3367 case KVM_X86_SETUP_MCE: {
3368 u64 mcg_cap;
3369
3370 r = -EFAULT;
3371 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3372 goto out;
3373 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3374 break;
3375 }
3376 case KVM_X86_SET_MCE: {
3377 struct kvm_x86_mce mce;
3378
3379 r = -EFAULT;
3380 if (copy_from_user(&mce, argp, sizeof mce))
3381 goto out;
3382 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3383 break;
3384 }
3385 case KVM_GET_VCPU_EVENTS: {
3386 struct kvm_vcpu_events events;
3387
3388 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3389
3390 r = -EFAULT;
3391 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3392 break;
3393 r = 0;
3394 break;
3395 }
3396 case KVM_SET_VCPU_EVENTS: {
3397 struct kvm_vcpu_events events;
3398
3399 r = -EFAULT;
3400 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3401 break;
3402
3403 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3404 break;
3405 }
3406 case KVM_GET_DEBUGREGS: {
3407 struct kvm_debugregs dbgregs;
3408
3409 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3410
3411 r = -EFAULT;
3412 if (copy_to_user(argp, &dbgregs,
3413 sizeof(struct kvm_debugregs)))
3414 break;
3415 r = 0;
3416 break;
3417 }
3418 case KVM_SET_DEBUGREGS: {
3419 struct kvm_debugregs dbgregs;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&dbgregs, argp,
3423 sizeof(struct kvm_debugregs)))
3424 break;
3425
3426 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3427 break;
3428 }
3429 case KVM_GET_XSAVE: {
3430 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3431 r = -ENOMEM;
3432 if (!u.xsave)
3433 break;
3434
3435 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3436
3437 r = -EFAULT;
3438 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3439 break;
3440 r = 0;
3441 break;
3442 }
3443 case KVM_SET_XSAVE: {
3444 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3445 if (IS_ERR(u.xsave))
3446 return PTR_ERR(u.xsave);
3447
3448 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3449 break;
3450 }
3451 case KVM_GET_XCRS: {
3452 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3453 r = -ENOMEM;
3454 if (!u.xcrs)
3455 break;
3456
3457 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3458
3459 r = -EFAULT;
3460 if (copy_to_user(argp, u.xcrs,
3461 sizeof(struct kvm_xcrs)))
3462 break;
3463 r = 0;
3464 break;
3465 }
3466 case KVM_SET_XCRS: {
3467 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3468 if (IS_ERR(u.xcrs))
3469 return PTR_ERR(u.xcrs);
3470
3471 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3472 break;
3473 }
3474 case KVM_SET_TSC_KHZ: {
3475 u32 user_tsc_khz;
3476
3477 r = -EINVAL;
3478 user_tsc_khz = (u32)arg;
3479
3480 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3481 goto out;
3482
3483 if (user_tsc_khz == 0)
3484 user_tsc_khz = tsc_khz;
3485
3486 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3487 r = 0;
3488
3489 goto out;
3490 }
3491 case KVM_GET_TSC_KHZ: {
3492 r = vcpu->arch.virtual_tsc_khz;
3493 goto out;
3494 }
3495 case KVM_KVMCLOCK_CTRL: {
3496 r = kvm_set_guest_paused(vcpu);
3497 goto out;
3498 }
3499 case KVM_ENABLE_CAP: {
3500 struct kvm_enable_cap cap;
3501
3502 r = -EFAULT;
3503 if (copy_from_user(&cap, argp, sizeof(cap)))
3504 goto out;
3505 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3506 break;
3507 }
3508 default:
3509 r = -EINVAL;
3510 }
3511 out:
3512 kfree(u.buffer);
3513 return r;
3514 }
3515
3516 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3517 {
3518 return VM_FAULT_SIGBUS;
3519 }
3520
3521 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3522 {
3523 int ret;
3524
3525 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3526 return -EINVAL;
3527 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3528 return ret;
3529 }
3530
3531 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3532 u64 ident_addr)
3533 {
3534 kvm->arch.ept_identity_map_addr = ident_addr;
3535 return 0;
3536 }
3537
3538 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3539 u32 kvm_nr_mmu_pages)
3540 {
3541 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3542 return -EINVAL;
3543
3544 mutex_lock(&kvm->slots_lock);
3545
3546 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3547 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3548
3549 mutex_unlock(&kvm->slots_lock);
3550 return 0;
3551 }
3552
3553 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3554 {
3555 return kvm->arch.n_max_mmu_pages;
3556 }
3557
3558 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3559 {
3560 int r;
3561
3562 r = 0;
3563 switch (chip->chip_id) {
3564 case KVM_IRQCHIP_PIC_MASTER:
3565 memcpy(&chip->chip.pic,
3566 &pic_irqchip(kvm)->pics[0],
3567 sizeof(struct kvm_pic_state));
3568 break;
3569 case KVM_IRQCHIP_PIC_SLAVE:
3570 memcpy(&chip->chip.pic,
3571 &pic_irqchip(kvm)->pics[1],
3572 sizeof(struct kvm_pic_state));
3573 break;
3574 case KVM_IRQCHIP_IOAPIC:
3575 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3576 break;
3577 default:
3578 r = -EINVAL;
3579 break;
3580 }
3581 return r;
3582 }
3583
3584 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3585 {
3586 int r;
3587
3588 r = 0;
3589 switch (chip->chip_id) {
3590 case KVM_IRQCHIP_PIC_MASTER:
3591 spin_lock(&pic_irqchip(kvm)->lock);
3592 memcpy(&pic_irqchip(kvm)->pics[0],
3593 &chip->chip.pic,
3594 sizeof(struct kvm_pic_state));
3595 spin_unlock(&pic_irqchip(kvm)->lock);
3596 break;
3597 case KVM_IRQCHIP_PIC_SLAVE:
3598 spin_lock(&pic_irqchip(kvm)->lock);
3599 memcpy(&pic_irqchip(kvm)->pics[1],
3600 &chip->chip.pic,
3601 sizeof(struct kvm_pic_state));
3602 spin_unlock(&pic_irqchip(kvm)->lock);
3603 break;
3604 case KVM_IRQCHIP_IOAPIC:
3605 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3606 break;
3607 default:
3608 r = -EINVAL;
3609 break;
3610 }
3611 kvm_pic_update_irq(pic_irqchip(kvm));
3612 return r;
3613 }
3614
3615 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3616 {
3617 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3618
3619 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3620
3621 mutex_lock(&kps->lock);
3622 memcpy(ps, &kps->channels, sizeof(*ps));
3623 mutex_unlock(&kps->lock);
3624 return 0;
3625 }
3626
3627 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3628 {
3629 int i;
3630 struct kvm_pit *pit = kvm->arch.vpit;
3631
3632 mutex_lock(&pit->pit_state.lock);
3633 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3634 for (i = 0; i < 3; i++)
3635 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3636 mutex_unlock(&pit->pit_state.lock);
3637 return 0;
3638 }
3639
3640 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3641 {
3642 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3643 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3644 sizeof(ps->channels));
3645 ps->flags = kvm->arch.vpit->pit_state.flags;
3646 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3647 memset(&ps->reserved, 0, sizeof(ps->reserved));
3648 return 0;
3649 }
3650
3651 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3652 {
3653 int start = 0;
3654 int i;
3655 u32 prev_legacy, cur_legacy;
3656 struct kvm_pit *pit = kvm->arch.vpit;
3657
3658 mutex_lock(&pit->pit_state.lock);
3659 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3660 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3661 if (!prev_legacy && cur_legacy)
3662 start = 1;
3663 memcpy(&pit->pit_state.channels, &ps->channels,
3664 sizeof(pit->pit_state.channels));
3665 pit->pit_state.flags = ps->flags;
3666 for (i = 0; i < 3; i++)
3667 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3668 start && i == 0);
3669 mutex_unlock(&pit->pit_state.lock);
3670 return 0;
3671 }
3672
3673 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3674 struct kvm_reinject_control *control)
3675 {
3676 struct kvm_pit *pit = kvm->arch.vpit;
3677
3678 if (!pit)
3679 return -ENXIO;
3680
3681 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3682 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3683 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3684 */
3685 mutex_lock(&pit->pit_state.lock);
3686 kvm_pit_set_reinject(pit, control->pit_reinject);
3687 mutex_unlock(&pit->pit_state.lock);
3688
3689 return 0;
3690 }
3691
3692 /**
3693 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3694 * @kvm: kvm instance
3695 * @log: slot id and address to which we copy the log
3696 *
3697 * Steps 1-4 below provide general overview of dirty page logging. See
3698 * kvm_get_dirty_log_protect() function description for additional details.
3699 *
3700 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3701 * always flush the TLB (step 4) even if previous step failed and the dirty
3702 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3703 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3704 * writes will be marked dirty for next log read.
3705 *
3706 * 1. Take a snapshot of the bit and clear it if needed.
3707 * 2. Write protect the corresponding page.
3708 * 3. Copy the snapshot to the userspace.
3709 * 4. Flush TLB's if needed.
3710 */
3711 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3712 {
3713 bool is_dirty = false;
3714 int r;
3715
3716 mutex_lock(&kvm->slots_lock);
3717
3718 /*
3719 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3720 */
3721 if (kvm_x86_ops->flush_log_dirty)
3722 kvm_x86_ops->flush_log_dirty(kvm);
3723
3724 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3725
3726 /*
3727 * All the TLBs can be flushed out of mmu lock, see the comments in
3728 * kvm_mmu_slot_remove_write_access().
3729 */
3730 lockdep_assert_held(&kvm->slots_lock);
3731 if (is_dirty)
3732 kvm_flush_remote_tlbs(kvm);
3733
3734 mutex_unlock(&kvm->slots_lock);
3735 return r;
3736 }
3737
3738 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3739 bool line_status)
3740 {
3741 if (!irqchip_in_kernel(kvm))
3742 return -ENXIO;
3743
3744 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3745 irq_event->irq, irq_event->level,
3746 line_status);
3747 return 0;
3748 }
3749
3750 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3751 struct kvm_enable_cap *cap)
3752 {
3753 int r;
3754
3755 if (cap->flags)
3756 return -EINVAL;
3757
3758 switch (cap->cap) {
3759 case KVM_CAP_DISABLE_QUIRKS:
3760 kvm->arch.disabled_quirks = cap->args[0];
3761 r = 0;
3762 break;
3763 case KVM_CAP_SPLIT_IRQCHIP: {
3764 mutex_lock(&kvm->lock);
3765 r = -EINVAL;
3766 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3767 goto split_irqchip_unlock;
3768 r = -EEXIST;
3769 if (irqchip_in_kernel(kvm))
3770 goto split_irqchip_unlock;
3771 if (atomic_read(&kvm->online_vcpus))
3772 goto split_irqchip_unlock;
3773 r = kvm_setup_empty_irq_routing(kvm);
3774 if (r)
3775 goto split_irqchip_unlock;
3776 /* Pairs with irqchip_in_kernel. */
3777 smp_wmb();
3778 kvm->arch.irqchip_split = true;
3779 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3780 r = 0;
3781 split_irqchip_unlock:
3782 mutex_unlock(&kvm->lock);
3783 break;
3784 }
3785 default:
3786 r = -EINVAL;
3787 break;
3788 }
3789 return r;
3790 }
3791
3792 long kvm_arch_vm_ioctl(struct file *filp,
3793 unsigned int ioctl, unsigned long arg)
3794 {
3795 struct kvm *kvm = filp->private_data;
3796 void __user *argp = (void __user *)arg;
3797 int r = -ENOTTY;
3798 /*
3799 * This union makes it completely explicit to gcc-3.x
3800 * that these two variables' stack usage should be
3801 * combined, not added together.
3802 */
3803 union {
3804 struct kvm_pit_state ps;
3805 struct kvm_pit_state2 ps2;
3806 struct kvm_pit_config pit_config;
3807 } u;
3808
3809 switch (ioctl) {
3810 case KVM_SET_TSS_ADDR:
3811 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3812 break;
3813 case KVM_SET_IDENTITY_MAP_ADDR: {
3814 u64 ident_addr;
3815
3816 r = -EFAULT;
3817 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3818 goto out;
3819 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3820 break;
3821 }
3822 case KVM_SET_NR_MMU_PAGES:
3823 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3824 break;
3825 case KVM_GET_NR_MMU_PAGES:
3826 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3827 break;
3828 case KVM_CREATE_IRQCHIP: {
3829 struct kvm_pic *vpic;
3830
3831 mutex_lock(&kvm->lock);
3832 r = -EEXIST;
3833 if (kvm->arch.vpic)
3834 goto create_irqchip_unlock;
3835 r = -EINVAL;
3836 if (atomic_read(&kvm->online_vcpus))
3837 goto create_irqchip_unlock;
3838 r = -ENOMEM;
3839 vpic = kvm_create_pic(kvm);
3840 if (vpic) {
3841 r = kvm_ioapic_init(kvm);
3842 if (r) {
3843 mutex_lock(&kvm->slots_lock);
3844 kvm_destroy_pic(vpic);
3845 mutex_unlock(&kvm->slots_lock);
3846 goto create_irqchip_unlock;
3847 }
3848 } else
3849 goto create_irqchip_unlock;
3850 r = kvm_setup_default_irq_routing(kvm);
3851 if (r) {
3852 mutex_lock(&kvm->slots_lock);
3853 mutex_lock(&kvm->irq_lock);
3854 kvm_ioapic_destroy(kvm);
3855 kvm_destroy_pic(vpic);
3856 mutex_unlock(&kvm->irq_lock);
3857 mutex_unlock(&kvm->slots_lock);
3858 goto create_irqchip_unlock;
3859 }
3860 /* Write kvm->irq_routing before kvm->arch.vpic. */
3861 smp_wmb();
3862 kvm->arch.vpic = vpic;
3863 create_irqchip_unlock:
3864 mutex_unlock(&kvm->lock);
3865 break;
3866 }
3867 case KVM_CREATE_PIT:
3868 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3869 goto create_pit;
3870 case KVM_CREATE_PIT2:
3871 r = -EFAULT;
3872 if (copy_from_user(&u.pit_config, argp,
3873 sizeof(struct kvm_pit_config)))
3874 goto out;
3875 create_pit:
3876 mutex_lock(&kvm->slots_lock);
3877 r = -EEXIST;
3878 if (kvm->arch.vpit)
3879 goto create_pit_unlock;
3880 r = -ENOMEM;
3881 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3882 if (kvm->arch.vpit)
3883 r = 0;
3884 create_pit_unlock:
3885 mutex_unlock(&kvm->slots_lock);
3886 break;
3887 case KVM_GET_IRQCHIP: {
3888 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3889 struct kvm_irqchip *chip;
3890
3891 chip = memdup_user(argp, sizeof(*chip));
3892 if (IS_ERR(chip)) {
3893 r = PTR_ERR(chip);
3894 goto out;
3895 }
3896
3897 r = -ENXIO;
3898 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3899 goto get_irqchip_out;
3900 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3901 if (r)
3902 goto get_irqchip_out;
3903 r = -EFAULT;
3904 if (copy_to_user(argp, chip, sizeof *chip))
3905 goto get_irqchip_out;
3906 r = 0;
3907 get_irqchip_out:
3908 kfree(chip);
3909 break;
3910 }
3911 case KVM_SET_IRQCHIP: {
3912 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3913 struct kvm_irqchip *chip;
3914
3915 chip = memdup_user(argp, sizeof(*chip));
3916 if (IS_ERR(chip)) {
3917 r = PTR_ERR(chip);
3918 goto out;
3919 }
3920
3921 r = -ENXIO;
3922 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3923 goto set_irqchip_out;
3924 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3925 if (r)
3926 goto set_irqchip_out;
3927 r = 0;
3928 set_irqchip_out:
3929 kfree(chip);
3930 break;
3931 }
3932 case KVM_GET_PIT: {
3933 r = -EFAULT;
3934 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3935 goto out;
3936 r = -ENXIO;
3937 if (!kvm->arch.vpit)
3938 goto out;
3939 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3940 if (r)
3941 goto out;
3942 r = -EFAULT;
3943 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3944 goto out;
3945 r = 0;
3946 break;
3947 }
3948 case KVM_SET_PIT: {
3949 r = -EFAULT;
3950 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3951 goto out;
3952 r = -ENXIO;
3953 if (!kvm->arch.vpit)
3954 goto out;
3955 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3956 break;
3957 }
3958 case KVM_GET_PIT2: {
3959 r = -ENXIO;
3960 if (!kvm->arch.vpit)
3961 goto out;
3962 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3963 if (r)
3964 goto out;
3965 r = -EFAULT;
3966 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3967 goto out;
3968 r = 0;
3969 break;
3970 }
3971 case KVM_SET_PIT2: {
3972 r = -EFAULT;
3973 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3974 goto out;
3975 r = -ENXIO;
3976 if (!kvm->arch.vpit)
3977 goto out;
3978 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3979 break;
3980 }
3981 case KVM_REINJECT_CONTROL: {
3982 struct kvm_reinject_control control;
3983 r = -EFAULT;
3984 if (copy_from_user(&control, argp, sizeof(control)))
3985 goto out;
3986 r = kvm_vm_ioctl_reinject(kvm, &control);
3987 break;
3988 }
3989 case KVM_SET_BOOT_CPU_ID:
3990 r = 0;
3991 mutex_lock(&kvm->lock);
3992 if (atomic_read(&kvm->online_vcpus) != 0)
3993 r = -EBUSY;
3994 else
3995 kvm->arch.bsp_vcpu_id = arg;
3996 mutex_unlock(&kvm->lock);
3997 break;
3998 case KVM_XEN_HVM_CONFIG: {
3999 r = -EFAULT;
4000 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4001 sizeof(struct kvm_xen_hvm_config)))
4002 goto out;
4003 r = -EINVAL;
4004 if (kvm->arch.xen_hvm_config.flags)
4005 goto out;
4006 r = 0;
4007 break;
4008 }
4009 case KVM_SET_CLOCK: {
4010 struct kvm_clock_data user_ns;
4011 u64 now_ns;
4012 s64 delta;
4013
4014 r = -EFAULT;
4015 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4016 goto out;
4017
4018 r = -EINVAL;
4019 if (user_ns.flags)
4020 goto out;
4021
4022 r = 0;
4023 local_irq_disable();
4024 now_ns = get_kernel_ns();
4025 delta = user_ns.clock - now_ns;
4026 local_irq_enable();
4027 kvm->arch.kvmclock_offset = delta;
4028 kvm_gen_update_masterclock(kvm);
4029 break;
4030 }
4031 case KVM_GET_CLOCK: {
4032 struct kvm_clock_data user_ns;
4033 u64 now_ns;
4034
4035 local_irq_disable();
4036 now_ns = get_kernel_ns();
4037 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4038 local_irq_enable();
4039 user_ns.flags = 0;
4040 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4041
4042 r = -EFAULT;
4043 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4044 goto out;
4045 r = 0;
4046 break;
4047 }
4048 case KVM_ENABLE_CAP: {
4049 struct kvm_enable_cap cap;
4050
4051 r = -EFAULT;
4052 if (copy_from_user(&cap, argp, sizeof(cap)))
4053 goto out;
4054 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4055 break;
4056 }
4057 default:
4058 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4059 }
4060 out:
4061 return r;
4062 }
4063
4064 static void kvm_init_msr_list(void)
4065 {
4066 u32 dummy[2];
4067 unsigned i, j;
4068
4069 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4070 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4071 continue;
4072
4073 /*
4074 * Even MSRs that are valid in the host may not be exposed
4075 * to the guests in some cases.
4076 */
4077 switch (msrs_to_save[i]) {
4078 case MSR_IA32_BNDCFGS:
4079 if (!kvm_x86_ops->mpx_supported())
4080 continue;
4081 break;
4082 case MSR_TSC_AUX:
4083 if (!kvm_x86_ops->rdtscp_supported())
4084 continue;
4085 break;
4086 default:
4087 break;
4088 }
4089
4090 if (j < i)
4091 msrs_to_save[j] = msrs_to_save[i];
4092 j++;
4093 }
4094 num_msrs_to_save = j;
4095
4096 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4097 switch (emulated_msrs[i]) {
4098 case MSR_IA32_SMBASE:
4099 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4100 continue;
4101 break;
4102 default:
4103 break;
4104 }
4105
4106 if (j < i)
4107 emulated_msrs[j] = emulated_msrs[i];
4108 j++;
4109 }
4110 num_emulated_msrs = j;
4111 }
4112
4113 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4114 const void *v)
4115 {
4116 int handled = 0;
4117 int n;
4118
4119 do {
4120 n = min(len, 8);
4121 if (!(lapic_in_kernel(vcpu) &&
4122 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4123 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4124 break;
4125 handled += n;
4126 addr += n;
4127 len -= n;
4128 v += n;
4129 } while (len);
4130
4131 return handled;
4132 }
4133
4134 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4135 {
4136 int handled = 0;
4137 int n;
4138
4139 do {
4140 n = min(len, 8);
4141 if (!(lapic_in_kernel(vcpu) &&
4142 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4143 addr, n, v))
4144 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4145 break;
4146 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4147 handled += n;
4148 addr += n;
4149 len -= n;
4150 v += n;
4151 } while (len);
4152
4153 return handled;
4154 }
4155
4156 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4157 struct kvm_segment *var, int seg)
4158 {
4159 kvm_x86_ops->set_segment(vcpu, var, seg);
4160 }
4161
4162 void kvm_get_segment(struct kvm_vcpu *vcpu,
4163 struct kvm_segment *var, int seg)
4164 {
4165 kvm_x86_ops->get_segment(vcpu, var, seg);
4166 }
4167
4168 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4169 struct x86_exception *exception)
4170 {
4171 gpa_t t_gpa;
4172
4173 BUG_ON(!mmu_is_nested(vcpu));
4174
4175 /* NPT walks are always user-walks */
4176 access |= PFERR_USER_MASK;
4177 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4178
4179 return t_gpa;
4180 }
4181
4182 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4183 struct x86_exception *exception)
4184 {
4185 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4186 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4187 }
4188
4189 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4190 struct x86_exception *exception)
4191 {
4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4193 access |= PFERR_FETCH_MASK;
4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4195 }
4196
4197 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4198 struct x86_exception *exception)
4199 {
4200 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4201 access |= PFERR_WRITE_MASK;
4202 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4203 }
4204
4205 /* uses this to access any guest's mapped memory without checking CPL */
4206 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4207 struct x86_exception *exception)
4208 {
4209 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4210 }
4211
4212 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4213 struct kvm_vcpu *vcpu, u32 access,
4214 struct x86_exception *exception)
4215 {
4216 void *data = val;
4217 int r = X86EMUL_CONTINUE;
4218
4219 while (bytes) {
4220 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4221 exception);
4222 unsigned offset = addr & (PAGE_SIZE-1);
4223 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4224 int ret;
4225
4226 if (gpa == UNMAPPED_GVA)
4227 return X86EMUL_PROPAGATE_FAULT;
4228 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4229 offset, toread);
4230 if (ret < 0) {
4231 r = X86EMUL_IO_NEEDED;
4232 goto out;
4233 }
4234
4235 bytes -= toread;
4236 data += toread;
4237 addr += toread;
4238 }
4239 out:
4240 return r;
4241 }
4242
4243 /* used for instruction fetching */
4244 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4245 gva_t addr, void *val, unsigned int bytes,
4246 struct x86_exception *exception)
4247 {
4248 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4249 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4250 unsigned offset;
4251 int ret;
4252
4253 /* Inline kvm_read_guest_virt_helper for speed. */
4254 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4255 exception);
4256 if (unlikely(gpa == UNMAPPED_GVA))
4257 return X86EMUL_PROPAGATE_FAULT;
4258
4259 offset = addr & (PAGE_SIZE-1);
4260 if (WARN_ON(offset + bytes > PAGE_SIZE))
4261 bytes = (unsigned)PAGE_SIZE - offset;
4262 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4263 offset, bytes);
4264 if (unlikely(ret < 0))
4265 return X86EMUL_IO_NEEDED;
4266
4267 return X86EMUL_CONTINUE;
4268 }
4269
4270 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4271 gva_t addr, void *val, unsigned int bytes,
4272 struct x86_exception *exception)
4273 {
4274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4275 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4276
4277 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4278 exception);
4279 }
4280 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4281
4282 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4283 gva_t addr, void *val, unsigned int bytes,
4284 struct x86_exception *exception)
4285 {
4286 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4287 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4288 }
4289
4290 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4291 unsigned long addr, void *val, unsigned int bytes)
4292 {
4293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4294 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4295
4296 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4297 }
4298
4299 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4300 gva_t addr, void *val,
4301 unsigned int bytes,
4302 struct x86_exception *exception)
4303 {
4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4305 void *data = val;
4306 int r = X86EMUL_CONTINUE;
4307
4308 while (bytes) {
4309 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4310 PFERR_WRITE_MASK,
4311 exception);
4312 unsigned offset = addr & (PAGE_SIZE-1);
4313 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4314 int ret;
4315
4316 if (gpa == UNMAPPED_GVA)
4317 return X86EMUL_PROPAGATE_FAULT;
4318 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4319 if (ret < 0) {
4320 r = X86EMUL_IO_NEEDED;
4321 goto out;
4322 }
4323
4324 bytes -= towrite;
4325 data += towrite;
4326 addr += towrite;
4327 }
4328 out:
4329 return r;
4330 }
4331 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4332
4333 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4334 gpa_t *gpa, struct x86_exception *exception,
4335 bool write)
4336 {
4337 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4338 | (write ? PFERR_WRITE_MASK : 0);
4339
4340 /*
4341 * currently PKRU is only applied to ept enabled guest so
4342 * there is no pkey in EPT page table for L1 guest or EPT
4343 * shadow page table for L2 guest.
4344 */
4345 if (vcpu_match_mmio_gva(vcpu, gva)
4346 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4347 vcpu->arch.access, 0, access)) {
4348 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4349 (gva & (PAGE_SIZE - 1));
4350 trace_vcpu_match_mmio(gva, *gpa, write, false);
4351 return 1;
4352 }
4353
4354 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4355
4356 if (*gpa == UNMAPPED_GVA)
4357 return -1;
4358
4359 /* For APIC access vmexit */
4360 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4361 return 1;
4362
4363 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4364 trace_vcpu_match_mmio(gva, *gpa, write, true);
4365 return 1;
4366 }
4367
4368 return 0;
4369 }
4370
4371 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 const void *val, int bytes)
4373 {
4374 int ret;
4375
4376 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4377 if (ret < 0)
4378 return 0;
4379 kvm_page_track_write(vcpu, gpa, val, bytes);
4380 return 1;
4381 }
4382
4383 struct read_write_emulator_ops {
4384 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4385 int bytes);
4386 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4387 void *val, int bytes);
4388 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 int bytes, void *val);
4390 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4391 void *val, int bytes);
4392 bool write;
4393 };
4394
4395 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4396 {
4397 if (vcpu->mmio_read_completed) {
4398 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4399 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4400 vcpu->mmio_read_completed = 0;
4401 return 1;
4402 }
4403
4404 return 0;
4405 }
4406
4407 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4409 {
4410 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4411 }
4412
4413 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4415 {
4416 return emulator_write_phys(vcpu, gpa, val, bytes);
4417 }
4418
4419 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4420 {
4421 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4422 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4423 }
4424
4425 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4426 void *val, int bytes)
4427 {
4428 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4429 return X86EMUL_IO_NEEDED;
4430 }
4431
4432 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4433 void *val, int bytes)
4434 {
4435 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4436
4437 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4438 return X86EMUL_CONTINUE;
4439 }
4440
4441 static const struct read_write_emulator_ops read_emultor = {
4442 .read_write_prepare = read_prepare,
4443 .read_write_emulate = read_emulate,
4444 .read_write_mmio = vcpu_mmio_read,
4445 .read_write_exit_mmio = read_exit_mmio,
4446 };
4447
4448 static const struct read_write_emulator_ops write_emultor = {
4449 .read_write_emulate = write_emulate,
4450 .read_write_mmio = write_mmio,
4451 .read_write_exit_mmio = write_exit_mmio,
4452 .write = true,
4453 };
4454
4455 static int emulator_read_write_onepage(unsigned long addr, void *val,
4456 unsigned int bytes,
4457 struct x86_exception *exception,
4458 struct kvm_vcpu *vcpu,
4459 const struct read_write_emulator_ops *ops)
4460 {
4461 gpa_t gpa;
4462 int handled, ret;
4463 bool write = ops->write;
4464 struct kvm_mmio_fragment *frag;
4465
4466 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4467
4468 if (ret < 0)
4469 return X86EMUL_PROPAGATE_FAULT;
4470
4471 /* For APIC access vmexit */
4472 if (ret)
4473 goto mmio;
4474
4475 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4476 return X86EMUL_CONTINUE;
4477
4478 mmio:
4479 /*
4480 * Is this MMIO handled locally?
4481 */
4482 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4483 if (handled == bytes)
4484 return X86EMUL_CONTINUE;
4485
4486 gpa += handled;
4487 bytes -= handled;
4488 val += handled;
4489
4490 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4491 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4492 frag->gpa = gpa;
4493 frag->data = val;
4494 frag->len = bytes;
4495 return X86EMUL_CONTINUE;
4496 }
4497
4498 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4499 unsigned long addr,
4500 void *val, unsigned int bytes,
4501 struct x86_exception *exception,
4502 const struct read_write_emulator_ops *ops)
4503 {
4504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4505 gpa_t gpa;
4506 int rc;
4507
4508 if (ops->read_write_prepare &&
4509 ops->read_write_prepare(vcpu, val, bytes))
4510 return X86EMUL_CONTINUE;
4511
4512 vcpu->mmio_nr_fragments = 0;
4513
4514 /* Crossing a page boundary? */
4515 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4516 int now;
4517
4518 now = -addr & ~PAGE_MASK;
4519 rc = emulator_read_write_onepage(addr, val, now, exception,
4520 vcpu, ops);
4521
4522 if (rc != X86EMUL_CONTINUE)
4523 return rc;
4524 addr += now;
4525 if (ctxt->mode != X86EMUL_MODE_PROT64)
4526 addr = (u32)addr;
4527 val += now;
4528 bytes -= now;
4529 }
4530
4531 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4532 vcpu, ops);
4533 if (rc != X86EMUL_CONTINUE)
4534 return rc;
4535
4536 if (!vcpu->mmio_nr_fragments)
4537 return rc;
4538
4539 gpa = vcpu->mmio_fragments[0].gpa;
4540
4541 vcpu->mmio_needed = 1;
4542 vcpu->mmio_cur_fragment = 0;
4543
4544 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4545 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4546 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4547 vcpu->run->mmio.phys_addr = gpa;
4548
4549 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4550 }
4551
4552 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4553 unsigned long addr,
4554 void *val,
4555 unsigned int bytes,
4556 struct x86_exception *exception)
4557 {
4558 return emulator_read_write(ctxt, addr, val, bytes,
4559 exception, &read_emultor);
4560 }
4561
4562 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4563 unsigned long addr,
4564 const void *val,
4565 unsigned int bytes,
4566 struct x86_exception *exception)
4567 {
4568 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4569 exception, &write_emultor);
4570 }
4571
4572 #define CMPXCHG_TYPE(t, ptr, old, new) \
4573 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4574
4575 #ifdef CONFIG_X86_64
4576 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4577 #else
4578 # define CMPXCHG64(ptr, old, new) \
4579 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4580 #endif
4581
4582 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4583 unsigned long addr,
4584 const void *old,
4585 const void *new,
4586 unsigned int bytes,
4587 struct x86_exception *exception)
4588 {
4589 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4590 gpa_t gpa;
4591 struct page *page;
4592 char *kaddr;
4593 bool exchanged;
4594
4595 /* guests cmpxchg8b have to be emulated atomically */
4596 if (bytes > 8 || (bytes & (bytes - 1)))
4597 goto emul_write;
4598
4599 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4600
4601 if (gpa == UNMAPPED_GVA ||
4602 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4603 goto emul_write;
4604
4605 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4606 goto emul_write;
4607
4608 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4609 if (is_error_page(page))
4610 goto emul_write;
4611
4612 kaddr = kmap_atomic(page);
4613 kaddr += offset_in_page(gpa);
4614 switch (bytes) {
4615 case 1:
4616 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4617 break;
4618 case 2:
4619 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4620 break;
4621 case 4:
4622 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4623 break;
4624 case 8:
4625 exchanged = CMPXCHG64(kaddr, old, new);
4626 break;
4627 default:
4628 BUG();
4629 }
4630 kunmap_atomic(kaddr);
4631 kvm_release_page_dirty(page);
4632
4633 if (!exchanged)
4634 return X86EMUL_CMPXCHG_FAILED;
4635
4636 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4637 kvm_page_track_write(vcpu, gpa, new, bytes);
4638
4639 return X86EMUL_CONTINUE;
4640
4641 emul_write:
4642 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4643
4644 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4645 }
4646
4647 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4648 {
4649 /* TODO: String I/O for in kernel device */
4650 int r;
4651
4652 if (vcpu->arch.pio.in)
4653 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4654 vcpu->arch.pio.size, pd);
4655 else
4656 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4657 vcpu->arch.pio.port, vcpu->arch.pio.size,
4658 pd);
4659 return r;
4660 }
4661
4662 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4663 unsigned short port, void *val,
4664 unsigned int count, bool in)
4665 {
4666 vcpu->arch.pio.port = port;
4667 vcpu->arch.pio.in = in;
4668 vcpu->arch.pio.count = count;
4669 vcpu->arch.pio.size = size;
4670
4671 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4672 vcpu->arch.pio.count = 0;
4673 return 1;
4674 }
4675
4676 vcpu->run->exit_reason = KVM_EXIT_IO;
4677 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4678 vcpu->run->io.size = size;
4679 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4680 vcpu->run->io.count = count;
4681 vcpu->run->io.port = port;
4682
4683 return 0;
4684 }
4685
4686 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4687 int size, unsigned short port, void *val,
4688 unsigned int count)
4689 {
4690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4691 int ret;
4692
4693 if (vcpu->arch.pio.count)
4694 goto data_avail;
4695
4696 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4697 if (ret) {
4698 data_avail:
4699 memcpy(val, vcpu->arch.pio_data, size * count);
4700 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4701 vcpu->arch.pio.count = 0;
4702 return 1;
4703 }
4704
4705 return 0;
4706 }
4707
4708 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4709 int size, unsigned short port,
4710 const void *val, unsigned int count)
4711 {
4712 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4713
4714 memcpy(vcpu->arch.pio_data, val, size * count);
4715 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4716 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4717 }
4718
4719 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4720 {
4721 return kvm_x86_ops->get_segment_base(vcpu, seg);
4722 }
4723
4724 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4725 {
4726 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4727 }
4728
4729 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4730 {
4731 if (!need_emulate_wbinvd(vcpu))
4732 return X86EMUL_CONTINUE;
4733
4734 if (kvm_x86_ops->has_wbinvd_exit()) {
4735 int cpu = get_cpu();
4736
4737 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4738 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4739 wbinvd_ipi, NULL, 1);
4740 put_cpu();
4741 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4742 } else
4743 wbinvd();
4744 return X86EMUL_CONTINUE;
4745 }
4746
4747 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4748 {
4749 kvm_x86_ops->skip_emulated_instruction(vcpu);
4750 return kvm_emulate_wbinvd_noskip(vcpu);
4751 }
4752 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4753
4754
4755
4756 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4757 {
4758 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4759 }
4760
4761 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4762 unsigned long *dest)
4763 {
4764 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4765 }
4766
4767 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4768 unsigned long value)
4769 {
4770
4771 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4772 }
4773
4774 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4775 {
4776 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4777 }
4778
4779 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4780 {
4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782 unsigned long value;
4783
4784 switch (cr) {
4785 case 0:
4786 value = kvm_read_cr0(vcpu);
4787 break;
4788 case 2:
4789 value = vcpu->arch.cr2;
4790 break;
4791 case 3:
4792 value = kvm_read_cr3(vcpu);
4793 break;
4794 case 4:
4795 value = kvm_read_cr4(vcpu);
4796 break;
4797 case 8:
4798 value = kvm_get_cr8(vcpu);
4799 break;
4800 default:
4801 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4802 return 0;
4803 }
4804
4805 return value;
4806 }
4807
4808 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4809 {
4810 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4811 int res = 0;
4812
4813 switch (cr) {
4814 case 0:
4815 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4816 break;
4817 case 2:
4818 vcpu->arch.cr2 = val;
4819 break;
4820 case 3:
4821 res = kvm_set_cr3(vcpu, val);
4822 break;
4823 case 4:
4824 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4825 break;
4826 case 8:
4827 res = kvm_set_cr8(vcpu, val);
4828 break;
4829 default:
4830 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4831 res = -1;
4832 }
4833
4834 return res;
4835 }
4836
4837 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4838 {
4839 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4840 }
4841
4842 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4843 {
4844 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4845 }
4846
4847 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4848 {
4849 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4850 }
4851
4852 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4853 {
4854 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4855 }
4856
4857 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4858 {
4859 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4860 }
4861
4862 static unsigned long emulator_get_cached_segment_base(
4863 struct x86_emulate_ctxt *ctxt, int seg)
4864 {
4865 return get_segment_base(emul_to_vcpu(ctxt), seg);
4866 }
4867
4868 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4869 struct desc_struct *desc, u32 *base3,
4870 int seg)
4871 {
4872 struct kvm_segment var;
4873
4874 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4875 *selector = var.selector;
4876
4877 if (var.unusable) {
4878 memset(desc, 0, sizeof(*desc));
4879 return false;
4880 }
4881
4882 if (var.g)
4883 var.limit >>= 12;
4884 set_desc_limit(desc, var.limit);
4885 set_desc_base(desc, (unsigned long)var.base);
4886 #ifdef CONFIG_X86_64
4887 if (base3)
4888 *base3 = var.base >> 32;
4889 #endif
4890 desc->type = var.type;
4891 desc->s = var.s;
4892 desc->dpl = var.dpl;
4893 desc->p = var.present;
4894 desc->avl = var.avl;
4895 desc->l = var.l;
4896 desc->d = var.db;
4897 desc->g = var.g;
4898
4899 return true;
4900 }
4901
4902 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4903 struct desc_struct *desc, u32 base3,
4904 int seg)
4905 {
4906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4907 struct kvm_segment var;
4908
4909 var.selector = selector;
4910 var.base = get_desc_base(desc);
4911 #ifdef CONFIG_X86_64
4912 var.base |= ((u64)base3) << 32;
4913 #endif
4914 var.limit = get_desc_limit(desc);
4915 if (desc->g)
4916 var.limit = (var.limit << 12) | 0xfff;
4917 var.type = desc->type;
4918 var.dpl = desc->dpl;
4919 var.db = desc->d;
4920 var.s = desc->s;
4921 var.l = desc->l;
4922 var.g = desc->g;
4923 var.avl = desc->avl;
4924 var.present = desc->p;
4925 var.unusable = !var.present;
4926 var.padding = 0;
4927
4928 kvm_set_segment(vcpu, &var, seg);
4929 return;
4930 }
4931
4932 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4933 u32 msr_index, u64 *pdata)
4934 {
4935 struct msr_data msr;
4936 int r;
4937
4938 msr.index = msr_index;
4939 msr.host_initiated = false;
4940 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4941 if (r)
4942 return r;
4943
4944 *pdata = msr.data;
4945 return 0;
4946 }
4947
4948 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4949 u32 msr_index, u64 data)
4950 {
4951 struct msr_data msr;
4952
4953 msr.data = data;
4954 msr.index = msr_index;
4955 msr.host_initiated = false;
4956 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4957 }
4958
4959 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4960 {
4961 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4962
4963 return vcpu->arch.smbase;
4964 }
4965
4966 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4967 {
4968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4969
4970 vcpu->arch.smbase = smbase;
4971 }
4972
4973 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4974 u32 pmc)
4975 {
4976 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4977 }
4978
4979 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4980 u32 pmc, u64 *pdata)
4981 {
4982 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4983 }
4984
4985 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4986 {
4987 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4988 }
4989
4990 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4991 {
4992 preempt_disable();
4993 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4994 /*
4995 * CR0.TS may reference the host fpu state, not the guest fpu state,
4996 * so it may be clear at this point.
4997 */
4998 clts();
4999 }
5000
5001 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5002 {
5003 preempt_enable();
5004 }
5005
5006 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5007 struct x86_instruction_info *info,
5008 enum x86_intercept_stage stage)
5009 {
5010 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5011 }
5012
5013 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5014 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5015 {
5016 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5017 }
5018
5019 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5020 {
5021 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5022 }
5023
5024 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5025 {
5026 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5027 }
5028
5029 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5030 {
5031 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5032 }
5033
5034 static const struct x86_emulate_ops emulate_ops = {
5035 .read_gpr = emulator_read_gpr,
5036 .write_gpr = emulator_write_gpr,
5037 .read_std = kvm_read_guest_virt_system,
5038 .write_std = kvm_write_guest_virt_system,
5039 .read_phys = kvm_read_guest_phys_system,
5040 .fetch = kvm_fetch_guest_virt,
5041 .read_emulated = emulator_read_emulated,
5042 .write_emulated = emulator_write_emulated,
5043 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5044 .invlpg = emulator_invlpg,
5045 .pio_in_emulated = emulator_pio_in_emulated,
5046 .pio_out_emulated = emulator_pio_out_emulated,
5047 .get_segment = emulator_get_segment,
5048 .set_segment = emulator_set_segment,
5049 .get_cached_segment_base = emulator_get_cached_segment_base,
5050 .get_gdt = emulator_get_gdt,
5051 .get_idt = emulator_get_idt,
5052 .set_gdt = emulator_set_gdt,
5053 .set_idt = emulator_set_idt,
5054 .get_cr = emulator_get_cr,
5055 .set_cr = emulator_set_cr,
5056 .cpl = emulator_get_cpl,
5057 .get_dr = emulator_get_dr,
5058 .set_dr = emulator_set_dr,
5059 .get_smbase = emulator_get_smbase,
5060 .set_smbase = emulator_set_smbase,
5061 .set_msr = emulator_set_msr,
5062 .get_msr = emulator_get_msr,
5063 .check_pmc = emulator_check_pmc,
5064 .read_pmc = emulator_read_pmc,
5065 .halt = emulator_halt,
5066 .wbinvd = emulator_wbinvd,
5067 .fix_hypercall = emulator_fix_hypercall,
5068 .get_fpu = emulator_get_fpu,
5069 .put_fpu = emulator_put_fpu,
5070 .intercept = emulator_intercept,
5071 .get_cpuid = emulator_get_cpuid,
5072 .set_nmi_mask = emulator_set_nmi_mask,
5073 };
5074
5075 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5076 {
5077 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5078 /*
5079 * an sti; sti; sequence only disable interrupts for the first
5080 * instruction. So, if the last instruction, be it emulated or
5081 * not, left the system with the INT_STI flag enabled, it
5082 * means that the last instruction is an sti. We should not
5083 * leave the flag on in this case. The same goes for mov ss
5084 */
5085 if (int_shadow & mask)
5086 mask = 0;
5087 if (unlikely(int_shadow || mask)) {
5088 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5089 if (!mask)
5090 kvm_make_request(KVM_REQ_EVENT, vcpu);
5091 }
5092 }
5093
5094 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5095 {
5096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5097 if (ctxt->exception.vector == PF_VECTOR)
5098 return kvm_propagate_fault(vcpu, &ctxt->exception);
5099
5100 if (ctxt->exception.error_code_valid)
5101 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5102 ctxt->exception.error_code);
5103 else
5104 kvm_queue_exception(vcpu, ctxt->exception.vector);
5105 return false;
5106 }
5107
5108 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5109 {
5110 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5111 int cs_db, cs_l;
5112
5113 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5114
5115 ctxt->eflags = kvm_get_rflags(vcpu);
5116 ctxt->eip = kvm_rip_read(vcpu);
5117 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5118 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5119 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5120 cs_db ? X86EMUL_MODE_PROT32 :
5121 X86EMUL_MODE_PROT16;
5122 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5123 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5124 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5125 ctxt->emul_flags = vcpu->arch.hflags;
5126
5127 init_decode_cache(ctxt);
5128 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5129 }
5130
5131 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5132 {
5133 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5134 int ret;
5135
5136 init_emulate_ctxt(vcpu);
5137
5138 ctxt->op_bytes = 2;
5139 ctxt->ad_bytes = 2;
5140 ctxt->_eip = ctxt->eip + inc_eip;
5141 ret = emulate_int_real(ctxt, irq);
5142
5143 if (ret != X86EMUL_CONTINUE)
5144 return EMULATE_FAIL;
5145
5146 ctxt->eip = ctxt->_eip;
5147 kvm_rip_write(vcpu, ctxt->eip);
5148 kvm_set_rflags(vcpu, ctxt->eflags);
5149
5150 if (irq == NMI_VECTOR)
5151 vcpu->arch.nmi_pending = 0;
5152 else
5153 vcpu->arch.interrupt.pending = false;
5154
5155 return EMULATE_DONE;
5156 }
5157 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5158
5159 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5160 {
5161 int r = EMULATE_DONE;
5162
5163 ++vcpu->stat.insn_emulation_fail;
5164 trace_kvm_emulate_insn_failed(vcpu);
5165 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5166 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5167 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5168 vcpu->run->internal.ndata = 0;
5169 r = EMULATE_FAIL;
5170 }
5171 kvm_queue_exception(vcpu, UD_VECTOR);
5172
5173 return r;
5174 }
5175
5176 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5177 bool write_fault_to_shadow_pgtable,
5178 int emulation_type)
5179 {
5180 gpa_t gpa = cr2;
5181 kvm_pfn_t pfn;
5182
5183 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5184 return false;
5185
5186 if (!vcpu->arch.mmu.direct_map) {
5187 /*
5188 * Write permission should be allowed since only
5189 * write access need to be emulated.
5190 */
5191 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5192
5193 /*
5194 * If the mapping is invalid in guest, let cpu retry
5195 * it to generate fault.
5196 */
5197 if (gpa == UNMAPPED_GVA)
5198 return true;
5199 }
5200
5201 /*
5202 * Do not retry the unhandleable instruction if it faults on the
5203 * readonly host memory, otherwise it will goto a infinite loop:
5204 * retry instruction -> write #PF -> emulation fail -> retry
5205 * instruction -> ...
5206 */
5207 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5208
5209 /*
5210 * If the instruction failed on the error pfn, it can not be fixed,
5211 * report the error to userspace.
5212 */
5213 if (is_error_noslot_pfn(pfn))
5214 return false;
5215
5216 kvm_release_pfn_clean(pfn);
5217
5218 /* The instructions are well-emulated on direct mmu. */
5219 if (vcpu->arch.mmu.direct_map) {
5220 unsigned int indirect_shadow_pages;
5221
5222 spin_lock(&vcpu->kvm->mmu_lock);
5223 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5224 spin_unlock(&vcpu->kvm->mmu_lock);
5225
5226 if (indirect_shadow_pages)
5227 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5228
5229 return true;
5230 }
5231
5232 /*
5233 * if emulation was due to access to shadowed page table
5234 * and it failed try to unshadow page and re-enter the
5235 * guest to let CPU execute the instruction.
5236 */
5237 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5238
5239 /*
5240 * If the access faults on its page table, it can not
5241 * be fixed by unprotecting shadow page and it should
5242 * be reported to userspace.
5243 */
5244 return !write_fault_to_shadow_pgtable;
5245 }
5246
5247 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5248 unsigned long cr2, int emulation_type)
5249 {
5250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5251 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5252
5253 last_retry_eip = vcpu->arch.last_retry_eip;
5254 last_retry_addr = vcpu->arch.last_retry_addr;
5255
5256 /*
5257 * If the emulation is caused by #PF and it is non-page_table
5258 * writing instruction, it means the VM-EXIT is caused by shadow
5259 * page protected, we can zap the shadow page and retry this
5260 * instruction directly.
5261 *
5262 * Note: if the guest uses a non-page-table modifying instruction
5263 * on the PDE that points to the instruction, then we will unmap
5264 * the instruction and go to an infinite loop. So, we cache the
5265 * last retried eip and the last fault address, if we meet the eip
5266 * and the address again, we can break out of the potential infinite
5267 * loop.
5268 */
5269 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5270
5271 if (!(emulation_type & EMULTYPE_RETRY))
5272 return false;
5273
5274 if (x86_page_table_writing_insn(ctxt))
5275 return false;
5276
5277 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5278 return false;
5279
5280 vcpu->arch.last_retry_eip = ctxt->eip;
5281 vcpu->arch.last_retry_addr = cr2;
5282
5283 if (!vcpu->arch.mmu.direct_map)
5284 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5285
5286 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5287
5288 return true;
5289 }
5290
5291 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5292 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5293
5294 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5295 {
5296 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5297 /* This is a good place to trace that we are exiting SMM. */
5298 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5299
5300 if (unlikely(vcpu->arch.smi_pending)) {
5301 kvm_make_request(KVM_REQ_SMI, vcpu);
5302 vcpu->arch.smi_pending = 0;
5303 } else {
5304 /* Process a latched INIT, if any. */
5305 kvm_make_request(KVM_REQ_EVENT, vcpu);
5306 }
5307 }
5308
5309 kvm_mmu_reset_context(vcpu);
5310 }
5311
5312 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5313 {
5314 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5315
5316 vcpu->arch.hflags = emul_flags;
5317
5318 if (changed & HF_SMM_MASK)
5319 kvm_smm_changed(vcpu);
5320 }
5321
5322 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5323 unsigned long *db)
5324 {
5325 u32 dr6 = 0;
5326 int i;
5327 u32 enable, rwlen;
5328
5329 enable = dr7;
5330 rwlen = dr7 >> 16;
5331 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5332 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5333 dr6 |= (1 << i);
5334 return dr6;
5335 }
5336
5337 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5338 {
5339 struct kvm_run *kvm_run = vcpu->run;
5340
5341 /*
5342 * rflags is the old, "raw" value of the flags. The new value has
5343 * not been saved yet.
5344 *
5345 * This is correct even for TF set by the guest, because "the
5346 * processor will not generate this exception after the instruction
5347 * that sets the TF flag".
5348 */
5349 if (unlikely(rflags & X86_EFLAGS_TF)) {
5350 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5351 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5352 DR6_RTM;
5353 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5354 kvm_run->debug.arch.exception = DB_VECTOR;
5355 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5356 *r = EMULATE_USER_EXIT;
5357 } else {
5358 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5359 /*
5360 * "Certain debug exceptions may clear bit 0-3. The
5361 * remaining contents of the DR6 register are never
5362 * cleared by the processor".
5363 */
5364 vcpu->arch.dr6 &= ~15;
5365 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5366 kvm_queue_exception(vcpu, DB_VECTOR);
5367 }
5368 }
5369 }
5370
5371 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5372 {
5373 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5374 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5375 struct kvm_run *kvm_run = vcpu->run;
5376 unsigned long eip = kvm_get_linear_rip(vcpu);
5377 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5378 vcpu->arch.guest_debug_dr7,
5379 vcpu->arch.eff_db);
5380
5381 if (dr6 != 0) {
5382 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5383 kvm_run->debug.arch.pc = eip;
5384 kvm_run->debug.arch.exception = DB_VECTOR;
5385 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5386 *r = EMULATE_USER_EXIT;
5387 return true;
5388 }
5389 }
5390
5391 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5392 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5393 unsigned long eip = kvm_get_linear_rip(vcpu);
5394 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5395 vcpu->arch.dr7,
5396 vcpu->arch.db);
5397
5398 if (dr6 != 0) {
5399 vcpu->arch.dr6 &= ~15;
5400 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5401 kvm_queue_exception(vcpu, DB_VECTOR);
5402 *r = EMULATE_DONE;
5403 return true;
5404 }
5405 }
5406
5407 return false;
5408 }
5409
5410 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5411 unsigned long cr2,
5412 int emulation_type,
5413 void *insn,
5414 int insn_len)
5415 {
5416 int r;
5417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5418 bool writeback = true;
5419 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5420
5421 /*
5422 * Clear write_fault_to_shadow_pgtable here to ensure it is
5423 * never reused.
5424 */
5425 vcpu->arch.write_fault_to_shadow_pgtable = false;
5426 kvm_clear_exception_queue(vcpu);
5427
5428 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5429 init_emulate_ctxt(vcpu);
5430
5431 /*
5432 * We will reenter on the same instruction since
5433 * we do not set complete_userspace_io. This does not
5434 * handle watchpoints yet, those would be handled in
5435 * the emulate_ops.
5436 */
5437 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5438 return r;
5439
5440 ctxt->interruptibility = 0;
5441 ctxt->have_exception = false;
5442 ctxt->exception.vector = -1;
5443 ctxt->perm_ok = false;
5444
5445 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5446
5447 r = x86_decode_insn(ctxt, insn, insn_len);
5448
5449 trace_kvm_emulate_insn_start(vcpu);
5450 ++vcpu->stat.insn_emulation;
5451 if (r != EMULATION_OK) {
5452 if (emulation_type & EMULTYPE_TRAP_UD)
5453 return EMULATE_FAIL;
5454 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5455 emulation_type))
5456 return EMULATE_DONE;
5457 if (emulation_type & EMULTYPE_SKIP)
5458 return EMULATE_FAIL;
5459 return handle_emulation_failure(vcpu);
5460 }
5461 }
5462
5463 if (emulation_type & EMULTYPE_SKIP) {
5464 kvm_rip_write(vcpu, ctxt->_eip);
5465 if (ctxt->eflags & X86_EFLAGS_RF)
5466 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5467 return EMULATE_DONE;
5468 }
5469
5470 if (retry_instruction(ctxt, cr2, emulation_type))
5471 return EMULATE_DONE;
5472
5473 /* this is needed for vmware backdoor interface to work since it
5474 changes registers values during IO operation */
5475 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5476 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5477 emulator_invalidate_register_cache(ctxt);
5478 }
5479
5480 restart:
5481 r = x86_emulate_insn(ctxt);
5482
5483 if (r == EMULATION_INTERCEPTED)
5484 return EMULATE_DONE;
5485
5486 if (r == EMULATION_FAILED) {
5487 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5488 emulation_type))
5489 return EMULATE_DONE;
5490
5491 return handle_emulation_failure(vcpu);
5492 }
5493
5494 if (ctxt->have_exception) {
5495 r = EMULATE_DONE;
5496 if (inject_emulated_exception(vcpu))
5497 return r;
5498 } else if (vcpu->arch.pio.count) {
5499 if (!vcpu->arch.pio.in) {
5500 /* FIXME: return into emulator if single-stepping. */
5501 vcpu->arch.pio.count = 0;
5502 } else {
5503 writeback = false;
5504 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5505 }
5506 r = EMULATE_USER_EXIT;
5507 } else if (vcpu->mmio_needed) {
5508 if (!vcpu->mmio_is_write)
5509 writeback = false;
5510 r = EMULATE_USER_EXIT;
5511 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5512 } else if (r == EMULATION_RESTART)
5513 goto restart;
5514 else
5515 r = EMULATE_DONE;
5516
5517 if (writeback) {
5518 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5519 toggle_interruptibility(vcpu, ctxt->interruptibility);
5520 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5521 if (vcpu->arch.hflags != ctxt->emul_flags)
5522 kvm_set_hflags(vcpu, ctxt->emul_flags);
5523 kvm_rip_write(vcpu, ctxt->eip);
5524 if (r == EMULATE_DONE)
5525 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5526 if (!ctxt->have_exception ||
5527 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5528 __kvm_set_rflags(vcpu, ctxt->eflags);
5529
5530 /*
5531 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5532 * do nothing, and it will be requested again as soon as
5533 * the shadow expires. But we still need to check here,
5534 * because POPF has no interrupt shadow.
5535 */
5536 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5537 kvm_make_request(KVM_REQ_EVENT, vcpu);
5538 } else
5539 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5540
5541 return r;
5542 }
5543 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5544
5545 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5546 {
5547 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5548 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5549 size, port, &val, 1);
5550 /* do not return to emulator after return from userspace */
5551 vcpu->arch.pio.count = 0;
5552 return ret;
5553 }
5554 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5555
5556 static int kvmclock_cpu_down_prep(unsigned int cpu)
5557 {
5558 __this_cpu_write(cpu_tsc_khz, 0);
5559 return 0;
5560 }
5561
5562 static void tsc_khz_changed(void *data)
5563 {
5564 struct cpufreq_freqs *freq = data;
5565 unsigned long khz = 0;
5566
5567 if (data)
5568 khz = freq->new;
5569 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5570 khz = cpufreq_quick_get(raw_smp_processor_id());
5571 if (!khz)
5572 khz = tsc_khz;
5573 __this_cpu_write(cpu_tsc_khz, khz);
5574 }
5575
5576 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5577 void *data)
5578 {
5579 struct cpufreq_freqs *freq = data;
5580 struct kvm *kvm;
5581 struct kvm_vcpu *vcpu;
5582 int i, send_ipi = 0;
5583
5584 /*
5585 * We allow guests to temporarily run on slowing clocks,
5586 * provided we notify them after, or to run on accelerating
5587 * clocks, provided we notify them before. Thus time never
5588 * goes backwards.
5589 *
5590 * However, we have a problem. We can't atomically update
5591 * the frequency of a given CPU from this function; it is
5592 * merely a notifier, which can be called from any CPU.
5593 * Changing the TSC frequency at arbitrary points in time
5594 * requires a recomputation of local variables related to
5595 * the TSC for each VCPU. We must flag these local variables
5596 * to be updated and be sure the update takes place with the
5597 * new frequency before any guests proceed.
5598 *
5599 * Unfortunately, the combination of hotplug CPU and frequency
5600 * change creates an intractable locking scenario; the order
5601 * of when these callouts happen is undefined with respect to
5602 * CPU hotplug, and they can race with each other. As such,
5603 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5604 * undefined; you can actually have a CPU frequency change take
5605 * place in between the computation of X and the setting of the
5606 * variable. To protect against this problem, all updates of
5607 * the per_cpu tsc_khz variable are done in an interrupt
5608 * protected IPI, and all callers wishing to update the value
5609 * must wait for a synchronous IPI to complete (which is trivial
5610 * if the caller is on the CPU already). This establishes the
5611 * necessary total order on variable updates.
5612 *
5613 * Note that because a guest time update may take place
5614 * anytime after the setting of the VCPU's request bit, the
5615 * correct TSC value must be set before the request. However,
5616 * to ensure the update actually makes it to any guest which
5617 * starts running in hardware virtualization between the set
5618 * and the acquisition of the spinlock, we must also ping the
5619 * CPU after setting the request bit.
5620 *
5621 */
5622
5623 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5624 return 0;
5625 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5626 return 0;
5627
5628 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5629
5630 spin_lock(&kvm_lock);
5631 list_for_each_entry(kvm, &vm_list, vm_list) {
5632 kvm_for_each_vcpu(i, vcpu, kvm) {
5633 if (vcpu->cpu != freq->cpu)
5634 continue;
5635 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5636 if (vcpu->cpu != smp_processor_id())
5637 send_ipi = 1;
5638 }
5639 }
5640 spin_unlock(&kvm_lock);
5641
5642 if (freq->old < freq->new && send_ipi) {
5643 /*
5644 * We upscale the frequency. Must make the guest
5645 * doesn't see old kvmclock values while running with
5646 * the new frequency, otherwise we risk the guest sees
5647 * time go backwards.
5648 *
5649 * In case we update the frequency for another cpu
5650 * (which might be in guest context) send an interrupt
5651 * to kick the cpu out of guest context. Next time
5652 * guest context is entered kvmclock will be updated,
5653 * so the guest will not see stale values.
5654 */
5655 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5656 }
5657 return 0;
5658 }
5659
5660 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5661 .notifier_call = kvmclock_cpufreq_notifier
5662 };
5663
5664 static int kvmclock_cpu_online(unsigned int cpu)
5665 {
5666 tsc_khz_changed(NULL);
5667 return 0;
5668 }
5669
5670 static void kvm_timer_init(void)
5671 {
5672 int cpu;
5673
5674 max_tsc_khz = tsc_khz;
5675
5676 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5677 #ifdef CONFIG_CPU_FREQ
5678 struct cpufreq_policy policy;
5679 memset(&policy, 0, sizeof(policy));
5680 cpu = get_cpu();
5681 cpufreq_get_policy(&policy, cpu);
5682 if (policy.cpuinfo.max_freq)
5683 max_tsc_khz = policy.cpuinfo.max_freq;
5684 put_cpu();
5685 #endif
5686 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5687 CPUFREQ_TRANSITION_NOTIFIER);
5688 }
5689 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5690
5691 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5692 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5693 }
5694
5695 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5696
5697 int kvm_is_in_guest(void)
5698 {
5699 return __this_cpu_read(current_vcpu) != NULL;
5700 }
5701
5702 static int kvm_is_user_mode(void)
5703 {
5704 int user_mode = 3;
5705
5706 if (__this_cpu_read(current_vcpu))
5707 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5708
5709 return user_mode != 0;
5710 }
5711
5712 static unsigned long kvm_get_guest_ip(void)
5713 {
5714 unsigned long ip = 0;
5715
5716 if (__this_cpu_read(current_vcpu))
5717 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5718
5719 return ip;
5720 }
5721
5722 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5723 .is_in_guest = kvm_is_in_guest,
5724 .is_user_mode = kvm_is_user_mode,
5725 .get_guest_ip = kvm_get_guest_ip,
5726 };
5727
5728 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5729 {
5730 __this_cpu_write(current_vcpu, vcpu);
5731 }
5732 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5733
5734 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5735 {
5736 __this_cpu_write(current_vcpu, NULL);
5737 }
5738 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5739
5740 static void kvm_set_mmio_spte_mask(void)
5741 {
5742 u64 mask;
5743 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5744
5745 /*
5746 * Set the reserved bits and the present bit of an paging-structure
5747 * entry to generate page fault with PFER.RSV = 1.
5748 */
5749 /* Mask the reserved physical address bits. */
5750 mask = rsvd_bits(maxphyaddr, 51);
5751
5752 /* Bit 62 is always reserved for 32bit host. */
5753 mask |= 0x3ull << 62;
5754
5755 /* Set the present bit. */
5756 mask |= 1ull;
5757
5758 #ifdef CONFIG_X86_64
5759 /*
5760 * If reserved bit is not supported, clear the present bit to disable
5761 * mmio page fault.
5762 */
5763 if (maxphyaddr == 52)
5764 mask &= ~1ull;
5765 #endif
5766
5767 kvm_mmu_set_mmio_spte_mask(mask);
5768 }
5769
5770 #ifdef CONFIG_X86_64
5771 static void pvclock_gtod_update_fn(struct work_struct *work)
5772 {
5773 struct kvm *kvm;
5774
5775 struct kvm_vcpu *vcpu;
5776 int i;
5777
5778 spin_lock(&kvm_lock);
5779 list_for_each_entry(kvm, &vm_list, vm_list)
5780 kvm_for_each_vcpu(i, vcpu, kvm)
5781 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5782 atomic_set(&kvm_guest_has_master_clock, 0);
5783 spin_unlock(&kvm_lock);
5784 }
5785
5786 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5787
5788 /*
5789 * Notification about pvclock gtod data update.
5790 */
5791 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5792 void *priv)
5793 {
5794 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5795 struct timekeeper *tk = priv;
5796
5797 update_pvclock_gtod(tk);
5798
5799 /* disable master clock if host does not trust, or does not
5800 * use, TSC clocksource
5801 */
5802 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5803 atomic_read(&kvm_guest_has_master_clock) != 0)
5804 queue_work(system_long_wq, &pvclock_gtod_work);
5805
5806 return 0;
5807 }
5808
5809 static struct notifier_block pvclock_gtod_notifier = {
5810 .notifier_call = pvclock_gtod_notify,
5811 };
5812 #endif
5813
5814 int kvm_arch_init(void *opaque)
5815 {
5816 int r;
5817 struct kvm_x86_ops *ops = opaque;
5818
5819 if (kvm_x86_ops) {
5820 printk(KERN_ERR "kvm: already loaded the other module\n");
5821 r = -EEXIST;
5822 goto out;
5823 }
5824
5825 if (!ops->cpu_has_kvm_support()) {
5826 printk(KERN_ERR "kvm: no hardware support\n");
5827 r = -EOPNOTSUPP;
5828 goto out;
5829 }
5830 if (ops->disabled_by_bios()) {
5831 printk(KERN_ERR "kvm: disabled by bios\n");
5832 r = -EOPNOTSUPP;
5833 goto out;
5834 }
5835
5836 r = -ENOMEM;
5837 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5838 if (!shared_msrs) {
5839 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5840 goto out;
5841 }
5842
5843 r = kvm_mmu_module_init();
5844 if (r)
5845 goto out_free_percpu;
5846
5847 kvm_set_mmio_spte_mask();
5848
5849 kvm_x86_ops = ops;
5850
5851 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5852 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5853
5854 kvm_timer_init();
5855
5856 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5857
5858 if (boot_cpu_has(X86_FEATURE_XSAVE))
5859 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5860
5861 kvm_lapic_init();
5862 #ifdef CONFIG_X86_64
5863 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5864 #endif
5865
5866 return 0;
5867
5868 out_free_percpu:
5869 free_percpu(shared_msrs);
5870 out:
5871 return r;
5872 }
5873
5874 void kvm_arch_exit(void)
5875 {
5876 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5877
5878 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5879 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5880 CPUFREQ_TRANSITION_NOTIFIER);
5881 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
5882 #ifdef CONFIG_X86_64
5883 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5884 #endif
5885 kvm_x86_ops = NULL;
5886 kvm_mmu_module_exit();
5887 free_percpu(shared_msrs);
5888 }
5889
5890 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5891 {
5892 ++vcpu->stat.halt_exits;
5893 if (lapic_in_kernel(vcpu)) {
5894 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5895 return 1;
5896 } else {
5897 vcpu->run->exit_reason = KVM_EXIT_HLT;
5898 return 0;
5899 }
5900 }
5901 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5902
5903 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5904 {
5905 kvm_x86_ops->skip_emulated_instruction(vcpu);
5906 return kvm_vcpu_halt(vcpu);
5907 }
5908 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5909
5910 /*
5911 * kvm_pv_kick_cpu_op: Kick a vcpu.
5912 *
5913 * @apicid - apicid of vcpu to be kicked.
5914 */
5915 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5916 {
5917 struct kvm_lapic_irq lapic_irq;
5918
5919 lapic_irq.shorthand = 0;
5920 lapic_irq.dest_mode = 0;
5921 lapic_irq.dest_id = apicid;
5922 lapic_irq.msi_redir_hint = false;
5923
5924 lapic_irq.delivery_mode = APIC_DM_REMRD;
5925 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5926 }
5927
5928 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5929 {
5930 vcpu->arch.apicv_active = false;
5931 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5932 }
5933
5934 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5935 {
5936 unsigned long nr, a0, a1, a2, a3, ret;
5937 int op_64_bit, r = 1;
5938
5939 kvm_x86_ops->skip_emulated_instruction(vcpu);
5940
5941 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5942 return kvm_hv_hypercall(vcpu);
5943
5944 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5945 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5946 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5947 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5948 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5949
5950 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5951
5952 op_64_bit = is_64_bit_mode(vcpu);
5953 if (!op_64_bit) {
5954 nr &= 0xFFFFFFFF;
5955 a0 &= 0xFFFFFFFF;
5956 a1 &= 0xFFFFFFFF;
5957 a2 &= 0xFFFFFFFF;
5958 a3 &= 0xFFFFFFFF;
5959 }
5960
5961 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5962 ret = -KVM_EPERM;
5963 goto out;
5964 }
5965
5966 switch (nr) {
5967 case KVM_HC_VAPIC_POLL_IRQ:
5968 ret = 0;
5969 break;
5970 case KVM_HC_KICK_CPU:
5971 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5972 ret = 0;
5973 break;
5974 default:
5975 ret = -KVM_ENOSYS;
5976 break;
5977 }
5978 out:
5979 if (!op_64_bit)
5980 ret = (u32)ret;
5981 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5982 ++vcpu->stat.hypercalls;
5983 return r;
5984 }
5985 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5986
5987 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5988 {
5989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5990 char instruction[3];
5991 unsigned long rip = kvm_rip_read(vcpu);
5992
5993 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5994
5995 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5996 }
5997
5998 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5999 {
6000 return vcpu->run->request_interrupt_window &&
6001 likely(!pic_in_kernel(vcpu->kvm));
6002 }
6003
6004 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6005 {
6006 struct kvm_run *kvm_run = vcpu->run;
6007
6008 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6009 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6010 kvm_run->cr8 = kvm_get_cr8(vcpu);
6011 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6012 kvm_run->ready_for_interrupt_injection =
6013 pic_in_kernel(vcpu->kvm) ||
6014 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6015 }
6016
6017 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6018 {
6019 int max_irr, tpr;
6020
6021 if (!kvm_x86_ops->update_cr8_intercept)
6022 return;
6023
6024 if (!lapic_in_kernel(vcpu))
6025 return;
6026
6027 if (vcpu->arch.apicv_active)
6028 return;
6029
6030 if (!vcpu->arch.apic->vapic_addr)
6031 max_irr = kvm_lapic_find_highest_irr(vcpu);
6032 else
6033 max_irr = -1;
6034
6035 if (max_irr != -1)
6036 max_irr >>= 4;
6037
6038 tpr = kvm_lapic_get_cr8(vcpu);
6039
6040 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6041 }
6042
6043 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6044 {
6045 int r;
6046
6047 /* try to reinject previous events if any */
6048 if (vcpu->arch.exception.pending) {
6049 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6050 vcpu->arch.exception.has_error_code,
6051 vcpu->arch.exception.error_code);
6052
6053 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6054 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6055 X86_EFLAGS_RF);
6056
6057 if (vcpu->arch.exception.nr == DB_VECTOR &&
6058 (vcpu->arch.dr7 & DR7_GD)) {
6059 vcpu->arch.dr7 &= ~DR7_GD;
6060 kvm_update_dr7(vcpu);
6061 }
6062
6063 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6064 vcpu->arch.exception.has_error_code,
6065 vcpu->arch.exception.error_code,
6066 vcpu->arch.exception.reinject);
6067 return 0;
6068 }
6069
6070 if (vcpu->arch.nmi_injected) {
6071 kvm_x86_ops->set_nmi(vcpu);
6072 return 0;
6073 }
6074
6075 if (vcpu->arch.interrupt.pending) {
6076 kvm_x86_ops->set_irq(vcpu);
6077 return 0;
6078 }
6079
6080 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6081 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6082 if (r != 0)
6083 return r;
6084 }
6085
6086 /* try to inject new event if pending */
6087 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6088 --vcpu->arch.nmi_pending;
6089 vcpu->arch.nmi_injected = true;
6090 kvm_x86_ops->set_nmi(vcpu);
6091 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6092 /*
6093 * Because interrupts can be injected asynchronously, we are
6094 * calling check_nested_events again here to avoid a race condition.
6095 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6096 * proposal and current concerns. Perhaps we should be setting
6097 * KVM_REQ_EVENT only on certain events and not unconditionally?
6098 */
6099 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6100 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6101 if (r != 0)
6102 return r;
6103 }
6104 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6105 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6106 false);
6107 kvm_x86_ops->set_irq(vcpu);
6108 }
6109 }
6110 return 0;
6111 }
6112
6113 static void process_nmi(struct kvm_vcpu *vcpu)
6114 {
6115 unsigned limit = 2;
6116
6117 /*
6118 * x86 is limited to one NMI running, and one NMI pending after it.
6119 * If an NMI is already in progress, limit further NMIs to just one.
6120 * Otherwise, allow two (and we'll inject the first one immediately).
6121 */
6122 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6123 limit = 1;
6124
6125 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6126 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6127 kvm_make_request(KVM_REQ_EVENT, vcpu);
6128 }
6129
6130 #define put_smstate(type, buf, offset, val) \
6131 *(type *)((buf) + (offset) - 0x7e00) = val
6132
6133 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6134 {
6135 u32 flags = 0;
6136 flags |= seg->g << 23;
6137 flags |= seg->db << 22;
6138 flags |= seg->l << 21;
6139 flags |= seg->avl << 20;
6140 flags |= seg->present << 15;
6141 flags |= seg->dpl << 13;
6142 flags |= seg->s << 12;
6143 flags |= seg->type << 8;
6144 return flags;
6145 }
6146
6147 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6148 {
6149 struct kvm_segment seg;
6150 int offset;
6151
6152 kvm_get_segment(vcpu, &seg, n);
6153 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6154
6155 if (n < 3)
6156 offset = 0x7f84 + n * 12;
6157 else
6158 offset = 0x7f2c + (n - 3) * 12;
6159
6160 put_smstate(u32, buf, offset + 8, seg.base);
6161 put_smstate(u32, buf, offset + 4, seg.limit);
6162 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6163 }
6164
6165 #ifdef CONFIG_X86_64
6166 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6167 {
6168 struct kvm_segment seg;
6169 int offset;
6170 u16 flags;
6171
6172 kvm_get_segment(vcpu, &seg, n);
6173 offset = 0x7e00 + n * 16;
6174
6175 flags = process_smi_get_segment_flags(&seg) >> 8;
6176 put_smstate(u16, buf, offset, seg.selector);
6177 put_smstate(u16, buf, offset + 2, flags);
6178 put_smstate(u32, buf, offset + 4, seg.limit);
6179 put_smstate(u64, buf, offset + 8, seg.base);
6180 }
6181 #endif
6182
6183 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6184 {
6185 struct desc_ptr dt;
6186 struct kvm_segment seg;
6187 unsigned long val;
6188 int i;
6189
6190 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6191 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6192 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6193 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6194
6195 for (i = 0; i < 8; i++)
6196 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6197
6198 kvm_get_dr(vcpu, 6, &val);
6199 put_smstate(u32, buf, 0x7fcc, (u32)val);
6200 kvm_get_dr(vcpu, 7, &val);
6201 put_smstate(u32, buf, 0x7fc8, (u32)val);
6202
6203 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6204 put_smstate(u32, buf, 0x7fc4, seg.selector);
6205 put_smstate(u32, buf, 0x7f64, seg.base);
6206 put_smstate(u32, buf, 0x7f60, seg.limit);
6207 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6208
6209 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6210 put_smstate(u32, buf, 0x7fc0, seg.selector);
6211 put_smstate(u32, buf, 0x7f80, seg.base);
6212 put_smstate(u32, buf, 0x7f7c, seg.limit);
6213 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6214
6215 kvm_x86_ops->get_gdt(vcpu, &dt);
6216 put_smstate(u32, buf, 0x7f74, dt.address);
6217 put_smstate(u32, buf, 0x7f70, dt.size);
6218
6219 kvm_x86_ops->get_idt(vcpu, &dt);
6220 put_smstate(u32, buf, 0x7f58, dt.address);
6221 put_smstate(u32, buf, 0x7f54, dt.size);
6222
6223 for (i = 0; i < 6; i++)
6224 process_smi_save_seg_32(vcpu, buf, i);
6225
6226 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6227
6228 /* revision id */
6229 put_smstate(u32, buf, 0x7efc, 0x00020000);
6230 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6231 }
6232
6233 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6234 {
6235 #ifdef CONFIG_X86_64
6236 struct desc_ptr dt;
6237 struct kvm_segment seg;
6238 unsigned long val;
6239 int i;
6240
6241 for (i = 0; i < 16; i++)
6242 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6243
6244 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6245 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6246
6247 kvm_get_dr(vcpu, 6, &val);
6248 put_smstate(u64, buf, 0x7f68, val);
6249 kvm_get_dr(vcpu, 7, &val);
6250 put_smstate(u64, buf, 0x7f60, val);
6251
6252 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6253 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6254 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6255
6256 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6257
6258 /* revision id */
6259 put_smstate(u32, buf, 0x7efc, 0x00020064);
6260
6261 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6262
6263 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6264 put_smstate(u16, buf, 0x7e90, seg.selector);
6265 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6266 put_smstate(u32, buf, 0x7e94, seg.limit);
6267 put_smstate(u64, buf, 0x7e98, seg.base);
6268
6269 kvm_x86_ops->get_idt(vcpu, &dt);
6270 put_smstate(u32, buf, 0x7e84, dt.size);
6271 put_smstate(u64, buf, 0x7e88, dt.address);
6272
6273 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6274 put_smstate(u16, buf, 0x7e70, seg.selector);
6275 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6276 put_smstate(u32, buf, 0x7e74, seg.limit);
6277 put_smstate(u64, buf, 0x7e78, seg.base);
6278
6279 kvm_x86_ops->get_gdt(vcpu, &dt);
6280 put_smstate(u32, buf, 0x7e64, dt.size);
6281 put_smstate(u64, buf, 0x7e68, dt.address);
6282
6283 for (i = 0; i < 6; i++)
6284 process_smi_save_seg_64(vcpu, buf, i);
6285 #else
6286 WARN_ON_ONCE(1);
6287 #endif
6288 }
6289
6290 static void process_smi(struct kvm_vcpu *vcpu)
6291 {
6292 struct kvm_segment cs, ds;
6293 struct desc_ptr dt;
6294 char buf[512];
6295 u32 cr0;
6296
6297 if (is_smm(vcpu)) {
6298 vcpu->arch.smi_pending = true;
6299 return;
6300 }
6301
6302 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6303 vcpu->arch.hflags |= HF_SMM_MASK;
6304 memset(buf, 0, 512);
6305 if (guest_cpuid_has_longmode(vcpu))
6306 process_smi_save_state_64(vcpu, buf);
6307 else
6308 process_smi_save_state_32(vcpu, buf);
6309
6310 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6311
6312 if (kvm_x86_ops->get_nmi_mask(vcpu))
6313 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6314 else
6315 kvm_x86_ops->set_nmi_mask(vcpu, true);
6316
6317 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6318 kvm_rip_write(vcpu, 0x8000);
6319
6320 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6321 kvm_x86_ops->set_cr0(vcpu, cr0);
6322 vcpu->arch.cr0 = cr0;
6323
6324 kvm_x86_ops->set_cr4(vcpu, 0);
6325
6326 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6327 dt.address = dt.size = 0;
6328 kvm_x86_ops->set_idt(vcpu, &dt);
6329
6330 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6331
6332 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6333 cs.base = vcpu->arch.smbase;
6334
6335 ds.selector = 0;
6336 ds.base = 0;
6337
6338 cs.limit = ds.limit = 0xffffffff;
6339 cs.type = ds.type = 0x3;
6340 cs.dpl = ds.dpl = 0;
6341 cs.db = ds.db = 0;
6342 cs.s = ds.s = 1;
6343 cs.l = ds.l = 0;
6344 cs.g = ds.g = 1;
6345 cs.avl = ds.avl = 0;
6346 cs.present = ds.present = 1;
6347 cs.unusable = ds.unusable = 0;
6348 cs.padding = ds.padding = 0;
6349
6350 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6351 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6352 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6353 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6354 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6355 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6356
6357 if (guest_cpuid_has_longmode(vcpu))
6358 kvm_x86_ops->set_efer(vcpu, 0);
6359
6360 kvm_update_cpuid(vcpu);
6361 kvm_mmu_reset_context(vcpu);
6362 }
6363
6364 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6365 {
6366 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6367 }
6368
6369 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6370 {
6371 u64 eoi_exit_bitmap[4];
6372
6373 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6374 return;
6375
6376 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6377
6378 if (irqchip_split(vcpu->kvm))
6379 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6380 else {
6381 if (vcpu->arch.apicv_active)
6382 kvm_x86_ops->sync_pir_to_irr(vcpu);
6383 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6384 }
6385 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6386 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6387 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6388 }
6389
6390 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6391 {
6392 ++vcpu->stat.tlb_flush;
6393 kvm_x86_ops->tlb_flush(vcpu);
6394 }
6395
6396 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6397 {
6398 struct page *page = NULL;
6399
6400 if (!lapic_in_kernel(vcpu))
6401 return;
6402
6403 if (!kvm_x86_ops->set_apic_access_page_addr)
6404 return;
6405
6406 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6407 if (is_error_page(page))
6408 return;
6409 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6410
6411 /*
6412 * Do not pin apic access page in memory, the MMU notifier
6413 * will call us again if it is migrated or swapped out.
6414 */
6415 put_page(page);
6416 }
6417 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6418
6419 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6420 unsigned long address)
6421 {
6422 /*
6423 * The physical address of apic access page is stored in the VMCS.
6424 * Update it when it becomes invalid.
6425 */
6426 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6427 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6428 }
6429
6430 /*
6431 * Returns 1 to let vcpu_run() continue the guest execution loop without
6432 * exiting to the userspace. Otherwise, the value will be returned to the
6433 * userspace.
6434 */
6435 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6436 {
6437 int r;
6438 bool req_int_win =
6439 dm_request_for_irq_injection(vcpu) &&
6440 kvm_cpu_accept_dm_intr(vcpu);
6441
6442 bool req_immediate_exit = false;
6443
6444 if (vcpu->requests) {
6445 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6446 kvm_mmu_unload(vcpu);
6447 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6448 __kvm_migrate_timers(vcpu);
6449 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6450 kvm_gen_update_masterclock(vcpu->kvm);
6451 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6452 kvm_gen_kvmclock_update(vcpu);
6453 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6454 r = kvm_guest_time_update(vcpu);
6455 if (unlikely(r))
6456 goto out;
6457 }
6458 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6459 kvm_mmu_sync_roots(vcpu);
6460 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6461 kvm_vcpu_flush_tlb(vcpu);
6462 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6463 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6464 r = 0;
6465 goto out;
6466 }
6467 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6468 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6469 r = 0;
6470 goto out;
6471 }
6472 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6473 vcpu->fpu_active = 0;
6474 kvm_x86_ops->fpu_deactivate(vcpu);
6475 }
6476 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6477 /* Page is swapped out. Do synthetic halt */
6478 vcpu->arch.apf.halted = true;
6479 r = 1;
6480 goto out;
6481 }
6482 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6483 record_steal_time(vcpu);
6484 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6485 process_smi(vcpu);
6486 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6487 process_nmi(vcpu);
6488 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6489 kvm_pmu_handle_event(vcpu);
6490 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6491 kvm_pmu_deliver_pmi(vcpu);
6492 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6493 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6494 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6495 vcpu->arch.ioapic_handled_vectors)) {
6496 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6497 vcpu->run->eoi.vector =
6498 vcpu->arch.pending_ioapic_eoi;
6499 r = 0;
6500 goto out;
6501 }
6502 }
6503 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6504 vcpu_scan_ioapic(vcpu);
6505 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6506 kvm_vcpu_reload_apic_access_page(vcpu);
6507 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6508 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6509 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6510 r = 0;
6511 goto out;
6512 }
6513 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6514 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6515 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6516 r = 0;
6517 goto out;
6518 }
6519 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6520 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6521 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6522 r = 0;
6523 goto out;
6524 }
6525
6526 /*
6527 * KVM_REQ_HV_STIMER has to be processed after
6528 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6529 * depend on the guest clock being up-to-date
6530 */
6531 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6532 kvm_hv_process_stimers(vcpu);
6533 }
6534
6535 /*
6536 * KVM_REQ_EVENT is not set when posted interrupts are set by
6537 * VT-d hardware, so we have to update RVI unconditionally.
6538 */
6539 if (kvm_lapic_enabled(vcpu)) {
6540 /*
6541 * Update architecture specific hints for APIC
6542 * virtual interrupt delivery.
6543 */
6544 if (vcpu->arch.apicv_active)
6545 kvm_x86_ops->hwapic_irr_update(vcpu,
6546 kvm_lapic_find_highest_irr(vcpu));
6547 }
6548
6549 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6550 kvm_apic_accept_events(vcpu);
6551 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6552 r = 1;
6553 goto out;
6554 }
6555
6556 if (inject_pending_event(vcpu, req_int_win) != 0)
6557 req_immediate_exit = true;
6558 /* enable NMI/IRQ window open exits if needed */
6559 else {
6560 if (vcpu->arch.nmi_pending)
6561 kvm_x86_ops->enable_nmi_window(vcpu);
6562 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6563 kvm_x86_ops->enable_irq_window(vcpu);
6564 }
6565
6566 if (kvm_lapic_enabled(vcpu)) {
6567 update_cr8_intercept(vcpu);
6568 kvm_lapic_sync_to_vapic(vcpu);
6569 }
6570 }
6571
6572 r = kvm_mmu_reload(vcpu);
6573 if (unlikely(r)) {
6574 goto cancel_injection;
6575 }
6576
6577 preempt_disable();
6578
6579 kvm_x86_ops->prepare_guest_switch(vcpu);
6580 if (vcpu->fpu_active)
6581 kvm_load_guest_fpu(vcpu);
6582 vcpu->mode = IN_GUEST_MODE;
6583
6584 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6585
6586 /*
6587 * We should set ->mode before check ->requests,
6588 * Please see the comment in kvm_make_all_cpus_request.
6589 * This also orders the write to mode from any reads
6590 * to the page tables done while the VCPU is running.
6591 * Please see the comment in kvm_flush_remote_tlbs.
6592 */
6593 smp_mb__after_srcu_read_unlock();
6594
6595 local_irq_disable();
6596
6597 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6598 || need_resched() || signal_pending(current)) {
6599 vcpu->mode = OUTSIDE_GUEST_MODE;
6600 smp_wmb();
6601 local_irq_enable();
6602 preempt_enable();
6603 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6604 r = 1;
6605 goto cancel_injection;
6606 }
6607
6608 kvm_load_guest_xcr0(vcpu);
6609
6610 if (req_immediate_exit)
6611 smp_send_reschedule(vcpu->cpu);
6612
6613 trace_kvm_entry(vcpu->vcpu_id);
6614 wait_lapic_expire(vcpu);
6615 __kvm_guest_enter();
6616
6617 if (unlikely(vcpu->arch.switch_db_regs)) {
6618 set_debugreg(0, 7);
6619 set_debugreg(vcpu->arch.eff_db[0], 0);
6620 set_debugreg(vcpu->arch.eff_db[1], 1);
6621 set_debugreg(vcpu->arch.eff_db[2], 2);
6622 set_debugreg(vcpu->arch.eff_db[3], 3);
6623 set_debugreg(vcpu->arch.dr6, 6);
6624 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6625 }
6626
6627 kvm_x86_ops->run(vcpu);
6628
6629 /*
6630 * Do this here before restoring debug registers on the host. And
6631 * since we do this before handling the vmexit, a DR access vmexit
6632 * can (a) read the correct value of the debug registers, (b) set
6633 * KVM_DEBUGREG_WONT_EXIT again.
6634 */
6635 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6636 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6637 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6638 kvm_update_dr0123(vcpu);
6639 kvm_update_dr6(vcpu);
6640 kvm_update_dr7(vcpu);
6641 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6642 }
6643
6644 /*
6645 * If the guest has used debug registers, at least dr7
6646 * will be disabled while returning to the host.
6647 * If we don't have active breakpoints in the host, we don't
6648 * care about the messed up debug address registers. But if
6649 * we have some of them active, restore the old state.
6650 */
6651 if (hw_breakpoint_active())
6652 hw_breakpoint_restore();
6653
6654 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6655
6656 vcpu->mode = OUTSIDE_GUEST_MODE;
6657 smp_wmb();
6658
6659 kvm_put_guest_xcr0(vcpu);
6660
6661 /* Interrupt is enabled by handle_external_intr() */
6662 kvm_x86_ops->handle_external_intr(vcpu);
6663
6664 ++vcpu->stat.exits;
6665
6666 /*
6667 * We must have an instruction between local_irq_enable() and
6668 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6669 * the interrupt shadow. The stat.exits increment will do nicely.
6670 * But we need to prevent reordering, hence this barrier():
6671 */
6672 barrier();
6673
6674 kvm_guest_exit();
6675
6676 preempt_enable();
6677
6678 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6679
6680 /*
6681 * Profile KVM exit RIPs:
6682 */
6683 if (unlikely(prof_on == KVM_PROFILING)) {
6684 unsigned long rip = kvm_rip_read(vcpu);
6685 profile_hit(KVM_PROFILING, (void *)rip);
6686 }
6687
6688 if (unlikely(vcpu->arch.tsc_always_catchup))
6689 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6690
6691 if (vcpu->arch.apic_attention)
6692 kvm_lapic_sync_from_vapic(vcpu);
6693
6694 r = kvm_x86_ops->handle_exit(vcpu);
6695 return r;
6696
6697 cancel_injection:
6698 kvm_x86_ops->cancel_injection(vcpu);
6699 if (unlikely(vcpu->arch.apic_attention))
6700 kvm_lapic_sync_from_vapic(vcpu);
6701 out:
6702 return r;
6703 }
6704
6705 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6706 {
6707 if (!kvm_arch_vcpu_runnable(vcpu) &&
6708 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6709 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6710 kvm_vcpu_block(vcpu);
6711 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6712
6713 if (kvm_x86_ops->post_block)
6714 kvm_x86_ops->post_block(vcpu);
6715
6716 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6717 return 1;
6718 }
6719
6720 kvm_apic_accept_events(vcpu);
6721 switch(vcpu->arch.mp_state) {
6722 case KVM_MP_STATE_HALTED:
6723 vcpu->arch.pv.pv_unhalted = false;
6724 vcpu->arch.mp_state =
6725 KVM_MP_STATE_RUNNABLE;
6726 case KVM_MP_STATE_RUNNABLE:
6727 vcpu->arch.apf.halted = false;
6728 break;
6729 case KVM_MP_STATE_INIT_RECEIVED:
6730 break;
6731 default:
6732 return -EINTR;
6733 break;
6734 }
6735 return 1;
6736 }
6737
6738 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6739 {
6740 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6741 !vcpu->arch.apf.halted);
6742 }
6743
6744 static int vcpu_run(struct kvm_vcpu *vcpu)
6745 {
6746 int r;
6747 struct kvm *kvm = vcpu->kvm;
6748
6749 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6750
6751 for (;;) {
6752 if (kvm_vcpu_running(vcpu)) {
6753 r = vcpu_enter_guest(vcpu);
6754 } else {
6755 r = vcpu_block(kvm, vcpu);
6756 }
6757
6758 if (r <= 0)
6759 break;
6760
6761 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6762 if (kvm_cpu_has_pending_timer(vcpu))
6763 kvm_inject_pending_timer_irqs(vcpu);
6764
6765 if (dm_request_for_irq_injection(vcpu) &&
6766 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6767 r = 0;
6768 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6769 ++vcpu->stat.request_irq_exits;
6770 break;
6771 }
6772
6773 kvm_check_async_pf_completion(vcpu);
6774
6775 if (signal_pending(current)) {
6776 r = -EINTR;
6777 vcpu->run->exit_reason = KVM_EXIT_INTR;
6778 ++vcpu->stat.signal_exits;
6779 break;
6780 }
6781 if (need_resched()) {
6782 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6783 cond_resched();
6784 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6785 }
6786 }
6787
6788 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6789
6790 return r;
6791 }
6792
6793 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6794 {
6795 int r;
6796 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6797 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6798 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6799 if (r != EMULATE_DONE)
6800 return 0;
6801 return 1;
6802 }
6803
6804 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6805 {
6806 BUG_ON(!vcpu->arch.pio.count);
6807
6808 return complete_emulated_io(vcpu);
6809 }
6810
6811 /*
6812 * Implements the following, as a state machine:
6813 *
6814 * read:
6815 * for each fragment
6816 * for each mmio piece in the fragment
6817 * write gpa, len
6818 * exit
6819 * copy data
6820 * execute insn
6821 *
6822 * write:
6823 * for each fragment
6824 * for each mmio piece in the fragment
6825 * write gpa, len
6826 * copy data
6827 * exit
6828 */
6829 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6830 {
6831 struct kvm_run *run = vcpu->run;
6832 struct kvm_mmio_fragment *frag;
6833 unsigned len;
6834
6835 BUG_ON(!vcpu->mmio_needed);
6836
6837 /* Complete previous fragment */
6838 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6839 len = min(8u, frag->len);
6840 if (!vcpu->mmio_is_write)
6841 memcpy(frag->data, run->mmio.data, len);
6842
6843 if (frag->len <= 8) {
6844 /* Switch to the next fragment. */
6845 frag++;
6846 vcpu->mmio_cur_fragment++;
6847 } else {
6848 /* Go forward to the next mmio piece. */
6849 frag->data += len;
6850 frag->gpa += len;
6851 frag->len -= len;
6852 }
6853
6854 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6855 vcpu->mmio_needed = 0;
6856
6857 /* FIXME: return into emulator if single-stepping. */
6858 if (vcpu->mmio_is_write)
6859 return 1;
6860 vcpu->mmio_read_completed = 1;
6861 return complete_emulated_io(vcpu);
6862 }
6863
6864 run->exit_reason = KVM_EXIT_MMIO;
6865 run->mmio.phys_addr = frag->gpa;
6866 if (vcpu->mmio_is_write)
6867 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6868 run->mmio.len = min(8u, frag->len);
6869 run->mmio.is_write = vcpu->mmio_is_write;
6870 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6871 return 0;
6872 }
6873
6874
6875 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6876 {
6877 struct fpu *fpu = &current->thread.fpu;
6878 int r;
6879 sigset_t sigsaved;
6880
6881 fpu__activate_curr(fpu);
6882
6883 if (vcpu->sigset_active)
6884 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6885
6886 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6887 kvm_vcpu_block(vcpu);
6888 kvm_apic_accept_events(vcpu);
6889 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6890 r = -EAGAIN;
6891 goto out;
6892 }
6893
6894 /* re-sync apic's tpr */
6895 if (!lapic_in_kernel(vcpu)) {
6896 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6897 r = -EINVAL;
6898 goto out;
6899 }
6900 }
6901
6902 if (unlikely(vcpu->arch.complete_userspace_io)) {
6903 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6904 vcpu->arch.complete_userspace_io = NULL;
6905 r = cui(vcpu);
6906 if (r <= 0)
6907 goto out;
6908 } else
6909 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6910
6911 r = vcpu_run(vcpu);
6912
6913 out:
6914 post_kvm_run_save(vcpu);
6915 if (vcpu->sigset_active)
6916 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6917
6918 return r;
6919 }
6920
6921 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6922 {
6923 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6924 /*
6925 * We are here if userspace calls get_regs() in the middle of
6926 * instruction emulation. Registers state needs to be copied
6927 * back from emulation context to vcpu. Userspace shouldn't do
6928 * that usually, but some bad designed PV devices (vmware
6929 * backdoor interface) need this to work
6930 */
6931 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6932 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6933 }
6934 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6935 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6936 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6937 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6938 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6939 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6940 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6941 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6942 #ifdef CONFIG_X86_64
6943 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6944 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6945 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6946 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6947 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6948 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6949 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6950 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6951 #endif
6952
6953 regs->rip = kvm_rip_read(vcpu);
6954 regs->rflags = kvm_get_rflags(vcpu);
6955
6956 return 0;
6957 }
6958
6959 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6960 {
6961 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6962 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6963
6964 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6965 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6966 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6967 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6968 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6969 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6970 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6971 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6972 #ifdef CONFIG_X86_64
6973 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6974 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6975 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6976 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6977 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6978 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6979 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6980 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6981 #endif
6982
6983 kvm_rip_write(vcpu, regs->rip);
6984 kvm_set_rflags(vcpu, regs->rflags);
6985
6986 vcpu->arch.exception.pending = false;
6987
6988 kvm_make_request(KVM_REQ_EVENT, vcpu);
6989
6990 return 0;
6991 }
6992
6993 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6994 {
6995 struct kvm_segment cs;
6996
6997 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6998 *db = cs.db;
6999 *l = cs.l;
7000 }
7001 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7002
7003 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7004 struct kvm_sregs *sregs)
7005 {
7006 struct desc_ptr dt;
7007
7008 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7009 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7010 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7011 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7012 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7013 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7014
7015 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7016 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7017
7018 kvm_x86_ops->get_idt(vcpu, &dt);
7019 sregs->idt.limit = dt.size;
7020 sregs->idt.base = dt.address;
7021 kvm_x86_ops->get_gdt(vcpu, &dt);
7022 sregs->gdt.limit = dt.size;
7023 sregs->gdt.base = dt.address;
7024
7025 sregs->cr0 = kvm_read_cr0(vcpu);
7026 sregs->cr2 = vcpu->arch.cr2;
7027 sregs->cr3 = kvm_read_cr3(vcpu);
7028 sregs->cr4 = kvm_read_cr4(vcpu);
7029 sregs->cr8 = kvm_get_cr8(vcpu);
7030 sregs->efer = vcpu->arch.efer;
7031 sregs->apic_base = kvm_get_apic_base(vcpu);
7032
7033 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7034
7035 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7036 set_bit(vcpu->arch.interrupt.nr,
7037 (unsigned long *)sregs->interrupt_bitmap);
7038
7039 return 0;
7040 }
7041
7042 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7043 struct kvm_mp_state *mp_state)
7044 {
7045 kvm_apic_accept_events(vcpu);
7046 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7047 vcpu->arch.pv.pv_unhalted)
7048 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7049 else
7050 mp_state->mp_state = vcpu->arch.mp_state;
7051
7052 return 0;
7053 }
7054
7055 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7056 struct kvm_mp_state *mp_state)
7057 {
7058 if (!lapic_in_kernel(vcpu) &&
7059 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7060 return -EINVAL;
7061
7062 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7063 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7064 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7065 } else
7066 vcpu->arch.mp_state = mp_state->mp_state;
7067 kvm_make_request(KVM_REQ_EVENT, vcpu);
7068 return 0;
7069 }
7070
7071 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7072 int reason, bool has_error_code, u32 error_code)
7073 {
7074 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7075 int ret;
7076
7077 init_emulate_ctxt(vcpu);
7078
7079 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7080 has_error_code, error_code);
7081
7082 if (ret)
7083 return EMULATE_FAIL;
7084
7085 kvm_rip_write(vcpu, ctxt->eip);
7086 kvm_set_rflags(vcpu, ctxt->eflags);
7087 kvm_make_request(KVM_REQ_EVENT, vcpu);
7088 return EMULATE_DONE;
7089 }
7090 EXPORT_SYMBOL_GPL(kvm_task_switch);
7091
7092 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7093 struct kvm_sregs *sregs)
7094 {
7095 struct msr_data apic_base_msr;
7096 int mmu_reset_needed = 0;
7097 int pending_vec, max_bits, idx;
7098 struct desc_ptr dt;
7099
7100 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7101 return -EINVAL;
7102
7103 dt.size = sregs->idt.limit;
7104 dt.address = sregs->idt.base;
7105 kvm_x86_ops->set_idt(vcpu, &dt);
7106 dt.size = sregs->gdt.limit;
7107 dt.address = sregs->gdt.base;
7108 kvm_x86_ops->set_gdt(vcpu, &dt);
7109
7110 vcpu->arch.cr2 = sregs->cr2;
7111 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7112 vcpu->arch.cr3 = sregs->cr3;
7113 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7114
7115 kvm_set_cr8(vcpu, sregs->cr8);
7116
7117 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7118 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7119 apic_base_msr.data = sregs->apic_base;
7120 apic_base_msr.host_initiated = true;
7121 kvm_set_apic_base(vcpu, &apic_base_msr);
7122
7123 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7124 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7125 vcpu->arch.cr0 = sregs->cr0;
7126
7127 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7128 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7129 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7130 kvm_update_cpuid(vcpu);
7131
7132 idx = srcu_read_lock(&vcpu->kvm->srcu);
7133 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7134 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7135 mmu_reset_needed = 1;
7136 }
7137 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7138
7139 if (mmu_reset_needed)
7140 kvm_mmu_reset_context(vcpu);
7141
7142 max_bits = KVM_NR_INTERRUPTS;
7143 pending_vec = find_first_bit(
7144 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7145 if (pending_vec < max_bits) {
7146 kvm_queue_interrupt(vcpu, pending_vec, false);
7147 pr_debug("Set back pending irq %d\n", pending_vec);
7148 }
7149
7150 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7151 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7152 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7153 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7154 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7155 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7156
7157 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7158 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7159
7160 update_cr8_intercept(vcpu);
7161
7162 /* Older userspace won't unhalt the vcpu on reset. */
7163 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7164 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7165 !is_protmode(vcpu))
7166 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7167
7168 kvm_make_request(KVM_REQ_EVENT, vcpu);
7169
7170 return 0;
7171 }
7172
7173 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7174 struct kvm_guest_debug *dbg)
7175 {
7176 unsigned long rflags;
7177 int i, r;
7178
7179 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7180 r = -EBUSY;
7181 if (vcpu->arch.exception.pending)
7182 goto out;
7183 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7184 kvm_queue_exception(vcpu, DB_VECTOR);
7185 else
7186 kvm_queue_exception(vcpu, BP_VECTOR);
7187 }
7188
7189 /*
7190 * Read rflags as long as potentially injected trace flags are still
7191 * filtered out.
7192 */
7193 rflags = kvm_get_rflags(vcpu);
7194
7195 vcpu->guest_debug = dbg->control;
7196 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7197 vcpu->guest_debug = 0;
7198
7199 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7200 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7201 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7202 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7203 } else {
7204 for (i = 0; i < KVM_NR_DB_REGS; i++)
7205 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7206 }
7207 kvm_update_dr7(vcpu);
7208
7209 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7210 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7211 get_segment_base(vcpu, VCPU_SREG_CS);
7212
7213 /*
7214 * Trigger an rflags update that will inject or remove the trace
7215 * flags.
7216 */
7217 kvm_set_rflags(vcpu, rflags);
7218
7219 kvm_x86_ops->update_bp_intercept(vcpu);
7220
7221 r = 0;
7222
7223 out:
7224
7225 return r;
7226 }
7227
7228 /*
7229 * Translate a guest virtual address to a guest physical address.
7230 */
7231 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7232 struct kvm_translation *tr)
7233 {
7234 unsigned long vaddr = tr->linear_address;
7235 gpa_t gpa;
7236 int idx;
7237
7238 idx = srcu_read_lock(&vcpu->kvm->srcu);
7239 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7240 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7241 tr->physical_address = gpa;
7242 tr->valid = gpa != UNMAPPED_GVA;
7243 tr->writeable = 1;
7244 tr->usermode = 0;
7245
7246 return 0;
7247 }
7248
7249 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7250 {
7251 struct fxregs_state *fxsave =
7252 &vcpu->arch.guest_fpu.state.fxsave;
7253
7254 memcpy(fpu->fpr, fxsave->st_space, 128);
7255 fpu->fcw = fxsave->cwd;
7256 fpu->fsw = fxsave->swd;
7257 fpu->ftwx = fxsave->twd;
7258 fpu->last_opcode = fxsave->fop;
7259 fpu->last_ip = fxsave->rip;
7260 fpu->last_dp = fxsave->rdp;
7261 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7262
7263 return 0;
7264 }
7265
7266 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7267 {
7268 struct fxregs_state *fxsave =
7269 &vcpu->arch.guest_fpu.state.fxsave;
7270
7271 memcpy(fxsave->st_space, fpu->fpr, 128);
7272 fxsave->cwd = fpu->fcw;
7273 fxsave->swd = fpu->fsw;
7274 fxsave->twd = fpu->ftwx;
7275 fxsave->fop = fpu->last_opcode;
7276 fxsave->rip = fpu->last_ip;
7277 fxsave->rdp = fpu->last_dp;
7278 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7279
7280 return 0;
7281 }
7282
7283 static void fx_init(struct kvm_vcpu *vcpu)
7284 {
7285 fpstate_init(&vcpu->arch.guest_fpu.state);
7286 if (boot_cpu_has(X86_FEATURE_XSAVES))
7287 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7288 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7289
7290 /*
7291 * Ensure guest xcr0 is valid for loading
7292 */
7293 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7294
7295 vcpu->arch.cr0 |= X86_CR0_ET;
7296 }
7297
7298 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7299 {
7300 if (vcpu->guest_fpu_loaded)
7301 return;
7302
7303 /*
7304 * Restore all possible states in the guest,
7305 * and assume host would use all available bits.
7306 * Guest xcr0 would be loaded later.
7307 */
7308 vcpu->guest_fpu_loaded = 1;
7309 __kernel_fpu_begin();
7310 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7311 trace_kvm_fpu(1);
7312 }
7313
7314 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7315 {
7316 if (!vcpu->guest_fpu_loaded) {
7317 vcpu->fpu_counter = 0;
7318 return;
7319 }
7320
7321 vcpu->guest_fpu_loaded = 0;
7322 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7323 __kernel_fpu_end();
7324 ++vcpu->stat.fpu_reload;
7325 /*
7326 * If using eager FPU mode, or if the guest is a frequent user
7327 * of the FPU, just leave the FPU active for next time.
7328 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7329 * the FPU in bursts will revert to loading it on demand.
7330 */
7331 if (!use_eager_fpu()) {
7332 if (++vcpu->fpu_counter < 5)
7333 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7334 }
7335 trace_kvm_fpu(0);
7336 }
7337
7338 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7339 {
7340 kvmclock_reset(vcpu);
7341
7342 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7343 kvm_x86_ops->vcpu_free(vcpu);
7344 }
7345
7346 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7347 unsigned int id)
7348 {
7349 struct kvm_vcpu *vcpu;
7350
7351 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7352 printk_once(KERN_WARNING
7353 "kvm: SMP vm created on host with unstable TSC; "
7354 "guest TSC will not be reliable\n");
7355
7356 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7357
7358 return vcpu;
7359 }
7360
7361 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7362 {
7363 int r;
7364
7365 kvm_vcpu_mtrr_init(vcpu);
7366 r = vcpu_load(vcpu);
7367 if (r)
7368 return r;
7369 kvm_vcpu_reset(vcpu, false);
7370 kvm_mmu_setup(vcpu);
7371 vcpu_put(vcpu);
7372 return r;
7373 }
7374
7375 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7376 {
7377 struct msr_data msr;
7378 struct kvm *kvm = vcpu->kvm;
7379
7380 if (vcpu_load(vcpu))
7381 return;
7382 msr.data = 0x0;
7383 msr.index = MSR_IA32_TSC;
7384 msr.host_initiated = true;
7385 kvm_write_tsc(vcpu, &msr);
7386 vcpu_put(vcpu);
7387
7388 if (!kvmclock_periodic_sync)
7389 return;
7390
7391 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7392 KVMCLOCK_SYNC_PERIOD);
7393 }
7394
7395 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7396 {
7397 int r;
7398 vcpu->arch.apf.msr_val = 0;
7399
7400 r = vcpu_load(vcpu);
7401 BUG_ON(r);
7402 kvm_mmu_unload(vcpu);
7403 vcpu_put(vcpu);
7404
7405 kvm_x86_ops->vcpu_free(vcpu);
7406 }
7407
7408 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7409 {
7410 vcpu->arch.hflags = 0;
7411
7412 atomic_set(&vcpu->arch.nmi_queued, 0);
7413 vcpu->arch.nmi_pending = 0;
7414 vcpu->arch.nmi_injected = false;
7415 kvm_clear_interrupt_queue(vcpu);
7416 kvm_clear_exception_queue(vcpu);
7417
7418 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7419 kvm_update_dr0123(vcpu);
7420 vcpu->arch.dr6 = DR6_INIT;
7421 kvm_update_dr6(vcpu);
7422 vcpu->arch.dr7 = DR7_FIXED_1;
7423 kvm_update_dr7(vcpu);
7424
7425 vcpu->arch.cr2 = 0;
7426
7427 kvm_make_request(KVM_REQ_EVENT, vcpu);
7428 vcpu->arch.apf.msr_val = 0;
7429 vcpu->arch.st.msr_val = 0;
7430
7431 kvmclock_reset(vcpu);
7432
7433 kvm_clear_async_pf_completion_queue(vcpu);
7434 kvm_async_pf_hash_reset(vcpu);
7435 vcpu->arch.apf.halted = false;
7436
7437 if (!init_event) {
7438 kvm_pmu_reset(vcpu);
7439 vcpu->arch.smbase = 0x30000;
7440 }
7441
7442 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7443 vcpu->arch.regs_avail = ~0;
7444 vcpu->arch.regs_dirty = ~0;
7445
7446 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7447 }
7448
7449 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7450 {
7451 struct kvm_segment cs;
7452
7453 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7454 cs.selector = vector << 8;
7455 cs.base = vector << 12;
7456 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7457 kvm_rip_write(vcpu, 0);
7458 }
7459
7460 int kvm_arch_hardware_enable(void)
7461 {
7462 struct kvm *kvm;
7463 struct kvm_vcpu *vcpu;
7464 int i;
7465 int ret;
7466 u64 local_tsc;
7467 u64 max_tsc = 0;
7468 bool stable, backwards_tsc = false;
7469
7470 kvm_shared_msr_cpu_online();
7471 ret = kvm_x86_ops->hardware_enable();
7472 if (ret != 0)
7473 return ret;
7474
7475 local_tsc = rdtsc();
7476 stable = !check_tsc_unstable();
7477 list_for_each_entry(kvm, &vm_list, vm_list) {
7478 kvm_for_each_vcpu(i, vcpu, kvm) {
7479 if (!stable && vcpu->cpu == smp_processor_id())
7480 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7481 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7482 backwards_tsc = true;
7483 if (vcpu->arch.last_host_tsc > max_tsc)
7484 max_tsc = vcpu->arch.last_host_tsc;
7485 }
7486 }
7487 }
7488
7489 /*
7490 * Sometimes, even reliable TSCs go backwards. This happens on
7491 * platforms that reset TSC during suspend or hibernate actions, but
7492 * maintain synchronization. We must compensate. Fortunately, we can
7493 * detect that condition here, which happens early in CPU bringup,
7494 * before any KVM threads can be running. Unfortunately, we can't
7495 * bring the TSCs fully up to date with real time, as we aren't yet far
7496 * enough into CPU bringup that we know how much real time has actually
7497 * elapsed; our helper function, get_kernel_ns() will be using boot
7498 * variables that haven't been updated yet.
7499 *
7500 * So we simply find the maximum observed TSC above, then record the
7501 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7502 * the adjustment will be applied. Note that we accumulate
7503 * adjustments, in case multiple suspend cycles happen before some VCPU
7504 * gets a chance to run again. In the event that no KVM threads get a
7505 * chance to run, we will miss the entire elapsed period, as we'll have
7506 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7507 * loose cycle time. This isn't too big a deal, since the loss will be
7508 * uniform across all VCPUs (not to mention the scenario is extremely
7509 * unlikely). It is possible that a second hibernate recovery happens
7510 * much faster than a first, causing the observed TSC here to be
7511 * smaller; this would require additional padding adjustment, which is
7512 * why we set last_host_tsc to the local tsc observed here.
7513 *
7514 * N.B. - this code below runs only on platforms with reliable TSC,
7515 * as that is the only way backwards_tsc is set above. Also note
7516 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7517 * have the same delta_cyc adjustment applied if backwards_tsc
7518 * is detected. Note further, this adjustment is only done once,
7519 * as we reset last_host_tsc on all VCPUs to stop this from being
7520 * called multiple times (one for each physical CPU bringup).
7521 *
7522 * Platforms with unreliable TSCs don't have to deal with this, they
7523 * will be compensated by the logic in vcpu_load, which sets the TSC to
7524 * catchup mode. This will catchup all VCPUs to real time, but cannot
7525 * guarantee that they stay in perfect synchronization.
7526 */
7527 if (backwards_tsc) {
7528 u64 delta_cyc = max_tsc - local_tsc;
7529 backwards_tsc_observed = true;
7530 list_for_each_entry(kvm, &vm_list, vm_list) {
7531 kvm_for_each_vcpu(i, vcpu, kvm) {
7532 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7533 vcpu->arch.last_host_tsc = local_tsc;
7534 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7535 }
7536
7537 /*
7538 * We have to disable TSC offset matching.. if you were
7539 * booting a VM while issuing an S4 host suspend....
7540 * you may have some problem. Solving this issue is
7541 * left as an exercise to the reader.
7542 */
7543 kvm->arch.last_tsc_nsec = 0;
7544 kvm->arch.last_tsc_write = 0;
7545 }
7546
7547 }
7548 return 0;
7549 }
7550
7551 void kvm_arch_hardware_disable(void)
7552 {
7553 kvm_x86_ops->hardware_disable();
7554 drop_user_return_notifiers();
7555 }
7556
7557 int kvm_arch_hardware_setup(void)
7558 {
7559 int r;
7560
7561 r = kvm_x86_ops->hardware_setup();
7562 if (r != 0)
7563 return r;
7564
7565 if (kvm_has_tsc_control) {
7566 /*
7567 * Make sure the user can only configure tsc_khz values that
7568 * fit into a signed integer.
7569 * A min value is not calculated needed because it will always
7570 * be 1 on all machines.
7571 */
7572 u64 max = min(0x7fffffffULL,
7573 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7574 kvm_max_guest_tsc_khz = max;
7575
7576 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7577 }
7578
7579 kvm_init_msr_list();
7580 return 0;
7581 }
7582
7583 void kvm_arch_hardware_unsetup(void)
7584 {
7585 kvm_x86_ops->hardware_unsetup();
7586 }
7587
7588 void kvm_arch_check_processor_compat(void *rtn)
7589 {
7590 kvm_x86_ops->check_processor_compatibility(rtn);
7591 }
7592
7593 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7594 {
7595 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7596 }
7597 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7598
7599 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7600 {
7601 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7602 }
7603
7604 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7605 {
7606 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7607 }
7608
7609 struct static_key kvm_no_apic_vcpu __read_mostly;
7610 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7611
7612 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7613 {
7614 struct page *page;
7615 struct kvm *kvm;
7616 int r;
7617
7618 BUG_ON(vcpu->kvm == NULL);
7619 kvm = vcpu->kvm;
7620
7621 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7622 vcpu->arch.pv.pv_unhalted = false;
7623 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7624 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7626 else
7627 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7628
7629 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7630 if (!page) {
7631 r = -ENOMEM;
7632 goto fail;
7633 }
7634 vcpu->arch.pio_data = page_address(page);
7635
7636 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7637
7638 r = kvm_mmu_create(vcpu);
7639 if (r < 0)
7640 goto fail_free_pio_data;
7641
7642 if (irqchip_in_kernel(kvm)) {
7643 r = kvm_create_lapic(vcpu);
7644 if (r < 0)
7645 goto fail_mmu_destroy;
7646 } else
7647 static_key_slow_inc(&kvm_no_apic_vcpu);
7648
7649 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7650 GFP_KERNEL);
7651 if (!vcpu->arch.mce_banks) {
7652 r = -ENOMEM;
7653 goto fail_free_lapic;
7654 }
7655 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7656
7657 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7658 r = -ENOMEM;
7659 goto fail_free_mce_banks;
7660 }
7661
7662 fx_init(vcpu);
7663
7664 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7665 vcpu->arch.pv_time_enabled = false;
7666
7667 vcpu->arch.guest_supported_xcr0 = 0;
7668 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7669
7670 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7671
7672 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7673
7674 kvm_async_pf_hash_reset(vcpu);
7675 kvm_pmu_init(vcpu);
7676
7677 vcpu->arch.pending_external_vector = -1;
7678
7679 kvm_hv_vcpu_init(vcpu);
7680
7681 return 0;
7682
7683 fail_free_mce_banks:
7684 kfree(vcpu->arch.mce_banks);
7685 fail_free_lapic:
7686 kvm_free_lapic(vcpu);
7687 fail_mmu_destroy:
7688 kvm_mmu_destroy(vcpu);
7689 fail_free_pio_data:
7690 free_page((unsigned long)vcpu->arch.pio_data);
7691 fail:
7692 return r;
7693 }
7694
7695 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7696 {
7697 int idx;
7698
7699 kvm_hv_vcpu_uninit(vcpu);
7700 kvm_pmu_destroy(vcpu);
7701 kfree(vcpu->arch.mce_banks);
7702 kvm_free_lapic(vcpu);
7703 idx = srcu_read_lock(&vcpu->kvm->srcu);
7704 kvm_mmu_destroy(vcpu);
7705 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7706 free_page((unsigned long)vcpu->arch.pio_data);
7707 if (!lapic_in_kernel(vcpu))
7708 static_key_slow_dec(&kvm_no_apic_vcpu);
7709 }
7710
7711 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7712 {
7713 kvm_x86_ops->sched_in(vcpu, cpu);
7714 }
7715
7716 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7717 {
7718 if (type)
7719 return -EINVAL;
7720
7721 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7722 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7723 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7724 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7725 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7726
7727 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7728 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7729 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7730 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7731 &kvm->arch.irq_sources_bitmap);
7732
7733 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7734 mutex_init(&kvm->arch.apic_map_lock);
7735 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7736
7737 pvclock_update_vm_gtod_copy(kvm);
7738
7739 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7740 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7741
7742 kvm_page_track_init(kvm);
7743 kvm_mmu_init_vm(kvm);
7744
7745 if (kvm_x86_ops->vm_init)
7746 return kvm_x86_ops->vm_init(kvm);
7747
7748 return 0;
7749 }
7750
7751 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7752 {
7753 int r;
7754 r = vcpu_load(vcpu);
7755 BUG_ON(r);
7756 kvm_mmu_unload(vcpu);
7757 vcpu_put(vcpu);
7758 }
7759
7760 static void kvm_free_vcpus(struct kvm *kvm)
7761 {
7762 unsigned int i;
7763 struct kvm_vcpu *vcpu;
7764
7765 /*
7766 * Unpin any mmu pages first.
7767 */
7768 kvm_for_each_vcpu(i, vcpu, kvm) {
7769 kvm_clear_async_pf_completion_queue(vcpu);
7770 kvm_unload_vcpu_mmu(vcpu);
7771 }
7772 kvm_for_each_vcpu(i, vcpu, kvm)
7773 kvm_arch_vcpu_free(vcpu);
7774
7775 mutex_lock(&kvm->lock);
7776 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7777 kvm->vcpus[i] = NULL;
7778
7779 atomic_set(&kvm->online_vcpus, 0);
7780 mutex_unlock(&kvm->lock);
7781 }
7782
7783 void kvm_arch_sync_events(struct kvm *kvm)
7784 {
7785 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7786 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7787 kvm_free_all_assigned_devices(kvm);
7788 kvm_free_pit(kvm);
7789 }
7790
7791 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7792 {
7793 int i, r;
7794 unsigned long hva;
7795 struct kvm_memslots *slots = kvm_memslots(kvm);
7796 struct kvm_memory_slot *slot, old;
7797
7798 /* Called with kvm->slots_lock held. */
7799 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7800 return -EINVAL;
7801
7802 slot = id_to_memslot(slots, id);
7803 if (size) {
7804 if (slot->npages)
7805 return -EEXIST;
7806
7807 /*
7808 * MAP_SHARED to prevent internal slot pages from being moved
7809 * by fork()/COW.
7810 */
7811 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7812 MAP_SHARED | MAP_ANONYMOUS, 0);
7813 if (IS_ERR((void *)hva))
7814 return PTR_ERR((void *)hva);
7815 } else {
7816 if (!slot->npages)
7817 return 0;
7818
7819 hva = 0;
7820 }
7821
7822 old = *slot;
7823 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7824 struct kvm_userspace_memory_region m;
7825
7826 m.slot = id | (i << 16);
7827 m.flags = 0;
7828 m.guest_phys_addr = gpa;
7829 m.userspace_addr = hva;
7830 m.memory_size = size;
7831 r = __kvm_set_memory_region(kvm, &m);
7832 if (r < 0)
7833 return r;
7834 }
7835
7836 if (!size) {
7837 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7838 WARN_ON(r < 0);
7839 }
7840
7841 return 0;
7842 }
7843 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7844
7845 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7846 {
7847 int r;
7848
7849 mutex_lock(&kvm->slots_lock);
7850 r = __x86_set_memory_region(kvm, id, gpa, size);
7851 mutex_unlock(&kvm->slots_lock);
7852
7853 return r;
7854 }
7855 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7856
7857 void kvm_arch_destroy_vm(struct kvm *kvm)
7858 {
7859 if (current->mm == kvm->mm) {
7860 /*
7861 * Free memory regions allocated on behalf of userspace,
7862 * unless the the memory map has changed due to process exit
7863 * or fd copying.
7864 */
7865 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7866 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7867 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7868 }
7869 if (kvm_x86_ops->vm_destroy)
7870 kvm_x86_ops->vm_destroy(kvm);
7871 kvm_iommu_unmap_guest(kvm);
7872 kfree(kvm->arch.vpic);
7873 kfree(kvm->arch.vioapic);
7874 kvm_free_vcpus(kvm);
7875 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7876 kvm_mmu_uninit_vm(kvm);
7877 }
7878
7879 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7880 struct kvm_memory_slot *dont)
7881 {
7882 int i;
7883
7884 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7885 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7886 kvfree(free->arch.rmap[i]);
7887 free->arch.rmap[i] = NULL;
7888 }
7889 if (i == 0)
7890 continue;
7891
7892 if (!dont || free->arch.lpage_info[i - 1] !=
7893 dont->arch.lpage_info[i - 1]) {
7894 kvfree(free->arch.lpage_info[i - 1]);
7895 free->arch.lpage_info[i - 1] = NULL;
7896 }
7897 }
7898
7899 kvm_page_track_free_memslot(free, dont);
7900 }
7901
7902 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7903 unsigned long npages)
7904 {
7905 int i;
7906
7907 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7908 struct kvm_lpage_info *linfo;
7909 unsigned long ugfn;
7910 int lpages;
7911 int level = i + 1;
7912
7913 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7914 slot->base_gfn, level) + 1;
7915
7916 slot->arch.rmap[i] =
7917 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7918 if (!slot->arch.rmap[i])
7919 goto out_free;
7920 if (i == 0)
7921 continue;
7922
7923 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7924 if (!linfo)
7925 goto out_free;
7926
7927 slot->arch.lpage_info[i - 1] = linfo;
7928
7929 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7930 linfo[0].disallow_lpage = 1;
7931 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7932 linfo[lpages - 1].disallow_lpage = 1;
7933 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7934 /*
7935 * If the gfn and userspace address are not aligned wrt each
7936 * other, or if explicitly asked to, disable large page
7937 * support for this slot
7938 */
7939 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7940 !kvm_largepages_enabled()) {
7941 unsigned long j;
7942
7943 for (j = 0; j < lpages; ++j)
7944 linfo[j].disallow_lpage = 1;
7945 }
7946 }
7947
7948 if (kvm_page_track_create_memslot(slot, npages))
7949 goto out_free;
7950
7951 return 0;
7952
7953 out_free:
7954 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7955 kvfree(slot->arch.rmap[i]);
7956 slot->arch.rmap[i] = NULL;
7957 if (i == 0)
7958 continue;
7959
7960 kvfree(slot->arch.lpage_info[i - 1]);
7961 slot->arch.lpage_info[i - 1] = NULL;
7962 }
7963 return -ENOMEM;
7964 }
7965
7966 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7967 {
7968 /*
7969 * memslots->generation has been incremented.
7970 * mmio generation may have reached its maximum value.
7971 */
7972 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7973 }
7974
7975 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7976 struct kvm_memory_slot *memslot,
7977 const struct kvm_userspace_memory_region *mem,
7978 enum kvm_mr_change change)
7979 {
7980 return 0;
7981 }
7982
7983 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7984 struct kvm_memory_slot *new)
7985 {
7986 /* Still write protect RO slot */
7987 if (new->flags & KVM_MEM_READONLY) {
7988 kvm_mmu_slot_remove_write_access(kvm, new);
7989 return;
7990 }
7991
7992 /*
7993 * Call kvm_x86_ops dirty logging hooks when they are valid.
7994 *
7995 * kvm_x86_ops->slot_disable_log_dirty is called when:
7996 *
7997 * - KVM_MR_CREATE with dirty logging is disabled
7998 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7999 *
8000 * The reason is, in case of PML, we need to set D-bit for any slots
8001 * with dirty logging disabled in order to eliminate unnecessary GPA
8002 * logging in PML buffer (and potential PML buffer full VMEXT). This
8003 * guarantees leaving PML enabled during guest's lifetime won't have
8004 * any additonal overhead from PML when guest is running with dirty
8005 * logging disabled for memory slots.
8006 *
8007 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8008 * to dirty logging mode.
8009 *
8010 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8011 *
8012 * In case of write protect:
8013 *
8014 * Write protect all pages for dirty logging.
8015 *
8016 * All the sptes including the large sptes which point to this
8017 * slot are set to readonly. We can not create any new large
8018 * spte on this slot until the end of the logging.
8019 *
8020 * See the comments in fast_page_fault().
8021 */
8022 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8023 if (kvm_x86_ops->slot_enable_log_dirty)
8024 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8025 else
8026 kvm_mmu_slot_remove_write_access(kvm, new);
8027 } else {
8028 if (kvm_x86_ops->slot_disable_log_dirty)
8029 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8030 }
8031 }
8032
8033 void kvm_arch_commit_memory_region(struct kvm *kvm,
8034 const struct kvm_userspace_memory_region *mem,
8035 const struct kvm_memory_slot *old,
8036 const struct kvm_memory_slot *new,
8037 enum kvm_mr_change change)
8038 {
8039 int nr_mmu_pages = 0;
8040
8041 if (!kvm->arch.n_requested_mmu_pages)
8042 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8043
8044 if (nr_mmu_pages)
8045 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8046
8047 /*
8048 * Dirty logging tracks sptes in 4k granularity, meaning that large
8049 * sptes have to be split. If live migration is successful, the guest
8050 * in the source machine will be destroyed and large sptes will be
8051 * created in the destination. However, if the guest continues to run
8052 * in the source machine (for example if live migration fails), small
8053 * sptes will remain around and cause bad performance.
8054 *
8055 * Scan sptes if dirty logging has been stopped, dropping those
8056 * which can be collapsed into a single large-page spte. Later
8057 * page faults will create the large-page sptes.
8058 */
8059 if ((change != KVM_MR_DELETE) &&
8060 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8061 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8062 kvm_mmu_zap_collapsible_sptes(kvm, new);
8063
8064 /*
8065 * Set up write protection and/or dirty logging for the new slot.
8066 *
8067 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8068 * been zapped so no dirty logging staff is needed for old slot. For
8069 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8070 * new and it's also covered when dealing with the new slot.
8071 *
8072 * FIXME: const-ify all uses of struct kvm_memory_slot.
8073 */
8074 if (change != KVM_MR_DELETE)
8075 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8076 }
8077
8078 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8079 {
8080 kvm_mmu_invalidate_zap_all_pages(kvm);
8081 }
8082
8083 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8084 struct kvm_memory_slot *slot)
8085 {
8086 kvm_mmu_invalidate_zap_all_pages(kvm);
8087 }
8088
8089 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8090 {
8091 if (!list_empty_careful(&vcpu->async_pf.done))
8092 return true;
8093
8094 if (kvm_apic_has_events(vcpu))
8095 return true;
8096
8097 if (vcpu->arch.pv.pv_unhalted)
8098 return true;
8099
8100 if (atomic_read(&vcpu->arch.nmi_queued))
8101 return true;
8102
8103 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8104 return true;
8105
8106 if (kvm_arch_interrupt_allowed(vcpu) &&
8107 kvm_cpu_has_interrupt(vcpu))
8108 return true;
8109
8110 if (kvm_hv_has_stimer_pending(vcpu))
8111 return true;
8112
8113 return false;
8114 }
8115
8116 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8117 {
8118 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8119 kvm_x86_ops->check_nested_events(vcpu, false);
8120
8121 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8122 }
8123
8124 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8125 {
8126 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8127 }
8128
8129 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8130 {
8131 return kvm_x86_ops->interrupt_allowed(vcpu);
8132 }
8133
8134 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8135 {
8136 if (is_64_bit_mode(vcpu))
8137 return kvm_rip_read(vcpu);
8138 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8139 kvm_rip_read(vcpu));
8140 }
8141 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8142
8143 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8144 {
8145 return kvm_get_linear_rip(vcpu) == linear_rip;
8146 }
8147 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8148
8149 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8150 {
8151 unsigned long rflags;
8152
8153 rflags = kvm_x86_ops->get_rflags(vcpu);
8154 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8155 rflags &= ~X86_EFLAGS_TF;
8156 return rflags;
8157 }
8158 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8159
8160 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8161 {
8162 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8163 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8164 rflags |= X86_EFLAGS_TF;
8165 kvm_x86_ops->set_rflags(vcpu, rflags);
8166 }
8167
8168 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8169 {
8170 __kvm_set_rflags(vcpu, rflags);
8171 kvm_make_request(KVM_REQ_EVENT, vcpu);
8172 }
8173 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8174
8175 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8176 {
8177 int r;
8178
8179 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8180 work->wakeup_all)
8181 return;
8182
8183 r = kvm_mmu_reload(vcpu);
8184 if (unlikely(r))
8185 return;
8186
8187 if (!vcpu->arch.mmu.direct_map &&
8188 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8189 return;
8190
8191 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8192 }
8193
8194 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8195 {
8196 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8197 }
8198
8199 static inline u32 kvm_async_pf_next_probe(u32 key)
8200 {
8201 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8202 }
8203
8204 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8205 {
8206 u32 key = kvm_async_pf_hash_fn(gfn);
8207
8208 while (vcpu->arch.apf.gfns[key] != ~0)
8209 key = kvm_async_pf_next_probe(key);
8210
8211 vcpu->arch.apf.gfns[key] = gfn;
8212 }
8213
8214 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8215 {
8216 int i;
8217 u32 key = kvm_async_pf_hash_fn(gfn);
8218
8219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8220 (vcpu->arch.apf.gfns[key] != gfn &&
8221 vcpu->arch.apf.gfns[key] != ~0); i++)
8222 key = kvm_async_pf_next_probe(key);
8223
8224 return key;
8225 }
8226
8227 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8228 {
8229 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8230 }
8231
8232 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8233 {
8234 u32 i, j, k;
8235
8236 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8237 while (true) {
8238 vcpu->arch.apf.gfns[i] = ~0;
8239 do {
8240 j = kvm_async_pf_next_probe(j);
8241 if (vcpu->arch.apf.gfns[j] == ~0)
8242 return;
8243 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8244 /*
8245 * k lies cyclically in ]i,j]
8246 * | i.k.j |
8247 * |....j i.k.| or |.k..j i...|
8248 */
8249 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8250 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8251 i = j;
8252 }
8253 }
8254
8255 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8256 {
8257
8258 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8259 sizeof(val));
8260 }
8261
8262 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8263 struct kvm_async_pf *work)
8264 {
8265 struct x86_exception fault;
8266
8267 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8268 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8269
8270 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8271 (vcpu->arch.apf.send_user_only &&
8272 kvm_x86_ops->get_cpl(vcpu) == 0))
8273 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8274 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8275 fault.vector = PF_VECTOR;
8276 fault.error_code_valid = true;
8277 fault.error_code = 0;
8278 fault.nested_page_fault = false;
8279 fault.address = work->arch.token;
8280 kvm_inject_page_fault(vcpu, &fault);
8281 }
8282 }
8283
8284 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8285 struct kvm_async_pf *work)
8286 {
8287 struct x86_exception fault;
8288
8289 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8290 if (work->wakeup_all)
8291 work->arch.token = ~0; /* broadcast wakeup */
8292 else
8293 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8294
8295 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8296 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8297 fault.vector = PF_VECTOR;
8298 fault.error_code_valid = true;
8299 fault.error_code = 0;
8300 fault.nested_page_fault = false;
8301 fault.address = work->arch.token;
8302 kvm_inject_page_fault(vcpu, &fault);
8303 }
8304 vcpu->arch.apf.halted = false;
8305 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8306 }
8307
8308 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8309 {
8310 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8311 return true;
8312 else
8313 return !kvm_event_needs_reinjection(vcpu) &&
8314 kvm_x86_ops->interrupt_allowed(vcpu);
8315 }
8316
8317 void kvm_arch_start_assignment(struct kvm *kvm)
8318 {
8319 atomic_inc(&kvm->arch.assigned_device_count);
8320 }
8321 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8322
8323 void kvm_arch_end_assignment(struct kvm *kvm)
8324 {
8325 atomic_dec(&kvm->arch.assigned_device_count);
8326 }
8327 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8328
8329 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8330 {
8331 return atomic_read(&kvm->arch.assigned_device_count);
8332 }
8333 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8334
8335 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8336 {
8337 atomic_inc(&kvm->arch.noncoherent_dma_count);
8338 }
8339 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8340
8341 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8342 {
8343 atomic_dec(&kvm->arch.noncoherent_dma_count);
8344 }
8345 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8346
8347 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8348 {
8349 return atomic_read(&kvm->arch.noncoherent_dma_count);
8350 }
8351 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8352
8353 bool kvm_arch_has_irq_bypass(void)
8354 {
8355 return kvm_x86_ops->update_pi_irte != NULL;
8356 }
8357
8358 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8359 struct irq_bypass_producer *prod)
8360 {
8361 struct kvm_kernel_irqfd *irqfd =
8362 container_of(cons, struct kvm_kernel_irqfd, consumer);
8363
8364 irqfd->producer = prod;
8365
8366 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8367 prod->irq, irqfd->gsi, 1);
8368 }
8369
8370 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8371 struct irq_bypass_producer *prod)
8372 {
8373 int ret;
8374 struct kvm_kernel_irqfd *irqfd =
8375 container_of(cons, struct kvm_kernel_irqfd, consumer);
8376
8377 WARN_ON(irqfd->producer != prod);
8378 irqfd->producer = NULL;
8379
8380 /*
8381 * When producer of consumer is unregistered, we change back to
8382 * remapped mode, so we can re-use the current implementation
8383 * when the irq is masked/disabed or the consumer side (KVM
8384 * int this case doesn't want to receive the interrupts.
8385 */
8386 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8387 if (ret)
8388 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8389 " fails: %d\n", irqfd->consumer.token, ret);
8390 }
8391
8392 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8393 uint32_t guest_irq, bool set)
8394 {
8395 if (!kvm_x86_ops->update_pi_irte)
8396 return -EINVAL;
8397
8398 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8399 }
8400
8401 bool kvm_vector_hashing_enabled(void)
8402 {
8403 return vector_hashing;
8404 }
8405 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8406
8407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux kernel - Deliverables
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