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KVM: x86 emulator: access GPRs on demand
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107 int nr;
108 u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136 { "hypercalls", VCPU_STAT(hypercalls) },
137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144 { "irq_injections", VCPU_STAT(irq_injections) },
145 { "nmi_injections", VCPU_STAT(nmi_injections) },
146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153 { "mmu_unsync", VM_STAT(mmu_unsync) },
154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155 { "largepages", VM_STAT(lpages) },
156 { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172 unsigned slot;
173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
175 struct kvm_shared_msr_values *values;
176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190 struct kvm_shared_msrs *smsr;
191 u64 value;
192
193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217 unsigned i;
218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
220 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
228 return;
229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249 return vcpu->arch.apic_base;
250 }
251 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254 {
255 /* TODO: reserve bits check */
256 kvm_lapic_set_base(vcpu, data);
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
260 #define EXCPT_BENIGN 0
261 #define EXCPT_CONTRIBUTORY 1
262 #define EXCPT_PF 2
263
264 static int exception_class(int vector)
265 {
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279 }
280
281 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
284 {
285 u32 prev_nr;
286 int class1, class2;
287
288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
296 vcpu->arch.exception.reinject = reinject;
297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321 }
322
323 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324 {
325 kvm_multiple_exception(vcpu, nr, false, 0, false);
326 }
327 EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
329 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332 }
333 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
335 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
336 {
337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341 }
342 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
343
344 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
345 {
346 ++vcpu->stat.pf_guest;
347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
349 }
350 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
351
352 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
353 {
354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
356 else
357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
358 }
359
360 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361 {
362 atomic_inc(&vcpu->arch.nmi_queued);
363 kvm_make_request(KVM_REQ_NMI, vcpu);
364 }
365 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
367 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368 {
369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
370 }
371 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
373 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376 }
377 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
379 /*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
384 {
385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
389 }
390 EXPORT_SYMBOL_GPL(kvm_require_cpl);
391
392 /*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400 {
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412 }
413 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
415 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417 {
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420 }
421
422 /*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
425 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
426 {
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
432
433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
441 if (is_present_gpte(pdpte[i]) &&
442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
454 out:
455
456 return ret;
457 }
458 EXPORT_SYMBOL_GPL(load_pdptrs);
459
460 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461 {
462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
463 bool changed = true;
464 int offset;
465 gfn_t gfn;
466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
479 if (r < 0)
480 goto out;
481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
482 out:
483
484 return changed;
485 }
486
487 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
488 {
489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
493 cr0 |= X86_CR0_ET;
494
495 #ifdef CONFIG_X86_64
496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
498 #endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
501
502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
504
505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509 #ifdef CONFIG_X86_64
510 if ((vcpu->arch.efer & EFER_LME)) {
511 int cs_db, cs_l;
512
513 if (!is_pae(vcpu))
514 return 1;
515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
516 if (cs_l)
517 return 1;
518 } else
519 #endif
520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
521 kvm_read_cr3(vcpu)))
522 return 1;
523 }
524
525 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526 return 1;
527
528 kvm_x86_ops->set_cr0(vcpu, cr0);
529
530 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
531 kvm_clear_async_pf_completion_queue(vcpu);
532 kvm_async_pf_hash_reset(vcpu);
533 }
534
535 if ((cr0 ^ old_cr0) & update_bits)
536 kvm_mmu_reset_context(vcpu);
537 return 0;
538 }
539 EXPORT_SYMBOL_GPL(kvm_set_cr0);
540
541 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
542 {
543 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
544 }
545 EXPORT_SYMBOL_GPL(kvm_lmsw);
546
547 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548 {
549 u64 xcr0;
550
551 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
552 if (index != XCR_XFEATURE_ENABLED_MASK)
553 return 1;
554 xcr0 = xcr;
555 if (kvm_x86_ops->get_cpl(vcpu) != 0)
556 return 1;
557 if (!(xcr0 & XSTATE_FP))
558 return 1;
559 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560 return 1;
561 if (xcr0 & ~host_xcr0)
562 return 1;
563 vcpu->arch.xcr0 = xcr0;
564 vcpu->guest_xcr0_loaded = 0;
565 return 0;
566 }
567
568 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569 {
570 if (__kvm_set_xcr(vcpu, index, xcr)) {
571 kvm_inject_gp(vcpu, 0);
572 return 1;
573 }
574 return 0;
575 }
576 EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
578 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
579 {
580 unsigned long old_cr4 = kvm_read_cr4(vcpu);
581 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582 X86_CR4_PAE | X86_CR4_SMEP;
583 if (cr4 & CR4_RESERVED_BITS)
584 return 1;
585
586 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587 return 1;
588
589 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590 return 1;
591
592 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593 return 1;
594
595 if (is_long_mode(vcpu)) {
596 if (!(cr4 & X86_CR4_PAE))
597 return 1;
598 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599 && ((cr4 ^ old_cr4) & pdptr_bits)
600 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601 kvm_read_cr3(vcpu)))
602 return 1;
603
604 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605 if (!guest_cpuid_has_pcid(vcpu))
606 return 1;
607
608 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610 return 1;
611 }
612
613 if (kvm_x86_ops->set_cr4(vcpu, cr4))
614 return 1;
615
616 if (((cr4 ^ old_cr4) & pdptr_bits) ||
617 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
618 kvm_mmu_reset_context(vcpu);
619
620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
621 kvm_update_cpuid(vcpu);
622
623 return 0;
624 }
625 EXPORT_SYMBOL_GPL(kvm_set_cr4);
626
627 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
628 {
629 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
630 kvm_mmu_sync_roots(vcpu);
631 kvm_mmu_flush_tlb(vcpu);
632 return 0;
633 }
634
635 if (is_long_mode(vcpu)) {
636 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638 return 1;
639 } else
640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
642 } else {
643 if (is_pae(vcpu)) {
644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
648 return 1;
649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
666 return 1;
667 vcpu->arch.cr3 = cr3;
668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671 }
672 EXPORT_SYMBOL_GPL(kvm_set_cr3);
673
674 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675 {
676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
681 vcpu->arch.cr8 = cr8;
682 return 0;
683 }
684 EXPORT_SYMBOL_GPL(kvm_set_cr8);
685
686 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
687 {
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
691 return vcpu->arch.cr8;
692 }
693 EXPORT_SYMBOL_GPL(kvm_get_cr8);
694
695 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
696 {
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
706 /* fall through */
707 case 6:
708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
715 /* fall through */
716 default: /* 7 */
717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728 }
729
730 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731 {
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_dr);
743
744 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
745 {
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
752 return 1;
753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
759 return 1;
760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767 }
768
769 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770 {
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776 }
777 EXPORT_SYMBOL_GPL(kvm_get_dr);
778
779 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780 {
781 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782 u64 data;
783 int err;
784
785 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786 if (err)
787 return err;
788 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790 return err;
791 }
792 EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
794 /*
795 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797 *
798 * This list is modified at module load time to reflect the
799 * capabilities of the host cpu. This capabilities test skips MSRs that are
800 * kvm-specific. Those are put in the beginning of the list.
801 */
802
803 #define KVM_SAVE_MSRS_BEGIN 10
804 static u32 msrs_to_save[] = {
805 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
806 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
807 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
808 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
809 MSR_KVM_PV_EOI_EN,
810 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
811 MSR_STAR,
812 #ifdef CONFIG_X86_64
813 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814 #endif
815 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
816 };
817
818 static unsigned num_msrs_to_save;
819
820 static u32 emulated_msrs[] = {
821 MSR_IA32_TSCDEADLINE,
822 MSR_IA32_MISC_ENABLE,
823 MSR_IA32_MCG_STATUS,
824 MSR_IA32_MCG_CTL,
825 };
826
827 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
828 {
829 u64 old_efer = vcpu->arch.efer;
830
831 if (efer & efer_reserved_bits)
832 return 1;
833
834 if (is_paging(vcpu)
835 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836 return 1;
837
838 if (efer & EFER_FFXSR) {
839 struct kvm_cpuid_entry2 *feat;
840
841 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
842 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843 return 1;
844 }
845
846 if (efer & EFER_SVME) {
847 struct kvm_cpuid_entry2 *feat;
848
849 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
850 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851 return 1;
852 }
853
854 efer &= ~EFER_LMA;
855 efer |= vcpu->arch.efer & EFER_LMA;
856
857 kvm_x86_ops->set_efer(vcpu, efer);
858
859 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
860
861 /* Update reserved bits */
862 if ((efer ^ old_efer) & EFER_NX)
863 kvm_mmu_reset_context(vcpu);
864
865 return 0;
866 }
867
868 void kvm_enable_efer_bits(u64 mask)
869 {
870 efer_reserved_bits &= ~mask;
871 }
872 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
875 /*
876 * Writes msr value into into the appropriate "register".
877 * Returns 0 on success, non-0 otherwise.
878 * Assumes vcpu_load() was already called.
879 */
880 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881 {
882 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883 }
884
885 /*
886 * Adapt set_msr() to msr_io()'s calling convention
887 */
888 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889 {
890 return kvm_set_msr(vcpu, index, *data);
891 }
892
893 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894 {
895 int version;
896 int r;
897 struct pvclock_wall_clock wc;
898 struct timespec boot;
899
900 if (!wall_clock)
901 return;
902
903 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904 if (r)
905 return;
906
907 if (version & 1)
908 ++version; /* first time write, random junk */
909
910 ++version;
911
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
914 /*
915 * The guest calculates current wall clock time by adding
916 * system time (updated by kvm_guest_time_update below) to the
917 * wall clock specified here. guest system time equals host
918 * system time for us, thus we must fill in host boot time here.
919 */
920 getboottime(&boot);
921
922 if (kvm->arch.kvmclock_offset) {
923 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924 boot = timespec_sub(boot, ts);
925 }
926 wc.sec = boot.tv_sec;
927 wc.nsec = boot.tv_nsec;
928 wc.version = version;
929
930 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932 version++;
933 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
934 }
935
936 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937 {
938 uint32_t quotient, remainder;
939
940 /* Don't try to replace with do_div(), this one calculates
941 * "(dividend << 32) / divisor" */
942 __asm__ ( "divl %4"
943 : "=a" (quotient), "=d" (remainder)
944 : "0" (0), "1" (dividend), "r" (divisor) );
945 return quotient;
946 }
947
948 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949 s8 *pshift, u32 *pmultiplier)
950 {
951 uint64_t scaled64;
952 int32_t shift = 0;
953 uint64_t tps64;
954 uint32_t tps32;
955
956 tps64 = base_khz * 1000LL;
957 scaled64 = scaled_khz * 1000LL;
958 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
959 tps64 >>= 1;
960 shift--;
961 }
962
963 tps32 = (uint32_t)tps64;
964 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
966 scaled64 >>= 1;
967 else
968 tps32 <<= 1;
969 shift++;
970 }
971
972 *pshift = shift;
973 *pmultiplier = div_frac(scaled64, tps32);
974
975 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976 __func__, base_khz, scaled_khz, shift, *pmultiplier);
977 }
978
979 static inline u64 get_kernel_ns(void)
980 {
981 struct timespec ts;
982
983 WARN_ON(preemptible());
984 ktime_get_ts(&ts);
985 monotonic_to_bootbased(&ts);
986 return timespec_to_ns(&ts);
987 }
988
989 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
990 unsigned long max_tsc_khz;
991
992 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
993 {
994 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995 vcpu->arch.virtual_tsc_shift);
996 }
997
998 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
999 {
1000 u64 v = (u64)khz * (1000000 + ppm);
1001 do_div(v, 1000000);
1002 return v;
1003 }
1004
1005 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1006 {
1007 u32 thresh_lo, thresh_hi;
1008 int use_scaling = 0;
1009
1010 /* Compute a scale to convert nanoseconds in TSC cycles */
1011 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1012 &vcpu->arch.virtual_tsc_shift,
1013 &vcpu->arch.virtual_tsc_mult);
1014 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016 /*
1017 * Compute the variation in TSC rate which is acceptable
1018 * within the range of tolerance and decide if the
1019 * rate being applied is within that bounds of the hardware
1020 * rate. If so, no scaling or compensation need be done.
1021 */
1022 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026 use_scaling = 1;
1027 }
1028 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1029 }
1030
1031 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032 {
1033 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1034 vcpu->arch.virtual_tsc_mult,
1035 vcpu->arch.virtual_tsc_shift);
1036 tsc += vcpu->arch.this_tsc_write;
1037 return tsc;
1038 }
1039
1040 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041 {
1042 struct kvm *kvm = vcpu->kvm;
1043 u64 offset, ns, elapsed;
1044 unsigned long flags;
1045 s64 usdiff;
1046
1047 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1048 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1049 ns = get_kernel_ns();
1050 elapsed = ns - kvm->arch.last_tsc_nsec;
1051
1052 /* n.b - signed multiplication and division required */
1053 usdiff = data - kvm->arch.last_tsc_write;
1054 #ifdef CONFIG_X86_64
1055 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1056 #else
1057 /* do_div() only does unsigned */
1058 asm("idivl %2; xor %%edx, %%edx"
1059 : "=A"(usdiff)
1060 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1061 #endif
1062 do_div(elapsed, 1000);
1063 usdiff -= elapsed;
1064 if (usdiff < 0)
1065 usdiff = -usdiff;
1066
1067 /*
1068 * Special case: TSC write with a small delta (1 second) of virtual
1069 * cycle time against real time is interpreted as an attempt to
1070 * synchronize the CPU.
1071 *
1072 * For a reliable TSC, we can match TSC offsets, and for an unstable
1073 * TSC, we add elapsed time in this computation. We could let the
1074 * compensation code attempt to catch up if we fall behind, but
1075 * it's better to try to match offsets from the beginning.
1076 */
1077 if (usdiff < USEC_PER_SEC &&
1078 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1079 if (!check_tsc_unstable()) {
1080 offset = kvm->arch.cur_tsc_offset;
1081 pr_debug("kvm: matched tsc offset for %llu\n", data);
1082 } else {
1083 u64 delta = nsec_to_cycles(vcpu, elapsed);
1084 data += delta;
1085 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1086 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1087 }
1088 } else {
1089 /*
1090 * We split periods of matched TSC writes into generations.
1091 * For each generation, we track the original measured
1092 * nanosecond time, offset, and write, so if TSCs are in
1093 * sync, we can match exact offset, and if not, we can match
1094 * exact software computation in compute_guest_tsc()
1095 *
1096 * These values are tracked in kvm->arch.cur_xxx variables.
1097 */
1098 kvm->arch.cur_tsc_generation++;
1099 kvm->arch.cur_tsc_nsec = ns;
1100 kvm->arch.cur_tsc_write = data;
1101 kvm->arch.cur_tsc_offset = offset;
1102 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103 kvm->arch.cur_tsc_generation, data);
1104 }
1105
1106 /*
1107 * We also track th most recent recorded KHZ, write and time to
1108 * allow the matching interval to be extended at each write.
1109 */
1110 kvm->arch.last_tsc_nsec = ns;
1111 kvm->arch.last_tsc_write = data;
1112 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1113
1114 /* Reset of TSC must disable overshoot protection below */
1115 vcpu->arch.hv_clock.tsc_timestamp = 0;
1116 vcpu->arch.last_guest_tsc = data;
1117
1118 /* Keep track of which generation this VCPU has synchronized to */
1119 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1125 }
1126
1127 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
1129 static int kvm_guest_time_update(struct kvm_vcpu *v)
1130 {
1131 unsigned long flags;
1132 struct kvm_vcpu_arch *vcpu = &v->arch;
1133 void *shared_kaddr;
1134 unsigned long this_tsc_khz;
1135 s64 kernel_ns, max_kernel_ns;
1136 u64 tsc_timestamp;
1137 u8 pvclock_flags;
1138
1139 /* Keep irq disabled to prevent changes to the clock */
1140 local_irq_save(flags);
1141 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1142 kernel_ns = get_kernel_ns();
1143 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1144 if (unlikely(this_tsc_khz == 0)) {
1145 local_irq_restore(flags);
1146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1147 return 1;
1148 }
1149
1150 /*
1151 * We may have to catch up the TSC to match elapsed wall clock
1152 * time for two reasons, even if kvmclock is used.
1153 * 1) CPU could have been running below the maximum TSC rate
1154 * 2) Broken TSC compensation resets the base at each VCPU
1155 * entry to avoid unknown leaps of TSC even when running
1156 * again on the same CPU. This may cause apparent elapsed
1157 * time to disappear, and the guest to stand still or run
1158 * very slowly.
1159 */
1160 if (vcpu->tsc_catchup) {
1161 u64 tsc = compute_guest_tsc(v, kernel_ns);
1162 if (tsc > tsc_timestamp) {
1163 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1164 tsc_timestamp = tsc;
1165 }
1166 }
1167
1168 local_irq_restore(flags);
1169
1170 if (!vcpu->time_page)
1171 return 0;
1172
1173 /*
1174 * Time as measured by the TSC may go backwards when resetting the base
1175 * tsc_timestamp. The reason for this is that the TSC resolution is
1176 * higher than the resolution of the other clock scales. Thus, many
1177 * possible measurments of the TSC correspond to one measurement of any
1178 * other clock, and so a spread of values is possible. This is not a
1179 * problem for the computation of the nanosecond clock; with TSC rates
1180 * around 1GHZ, there can only be a few cycles which correspond to one
1181 * nanosecond value, and any path through this code will inevitably
1182 * take longer than that. However, with the kernel_ns value itself,
1183 * the precision may be much lower, down to HZ granularity. If the
1184 * first sampling of TSC against kernel_ns ends in the low part of the
1185 * range, and the second in the high end of the range, we can get:
1186 *
1187 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1188 *
1189 * As the sampling errors potentially range in the thousands of cycles,
1190 * it is possible such a time value has already been observed by the
1191 * guest. To protect against this, we must compute the system time as
1192 * observed by the guest and ensure the new system time is greater.
1193 */
1194 max_kernel_ns = 0;
1195 if (vcpu->hv_clock.tsc_timestamp) {
1196 max_kernel_ns = vcpu->last_guest_tsc -
1197 vcpu->hv_clock.tsc_timestamp;
1198 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1199 vcpu->hv_clock.tsc_to_system_mul,
1200 vcpu->hv_clock.tsc_shift);
1201 max_kernel_ns += vcpu->last_kernel_ns;
1202 }
1203
1204 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1205 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1206 &vcpu->hv_clock.tsc_shift,
1207 &vcpu->hv_clock.tsc_to_system_mul);
1208 vcpu->hw_tsc_khz = this_tsc_khz;
1209 }
1210
1211 if (max_kernel_ns > kernel_ns)
1212 kernel_ns = max_kernel_ns;
1213
1214 /* With all the info we got, fill in the values */
1215 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1216 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1217 vcpu->last_kernel_ns = kernel_ns;
1218 vcpu->last_guest_tsc = tsc_timestamp;
1219
1220 pvclock_flags = 0;
1221 if (vcpu->pvclock_set_guest_stopped_request) {
1222 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1223 vcpu->pvclock_set_guest_stopped_request = false;
1224 }
1225
1226 vcpu->hv_clock.flags = pvclock_flags;
1227
1228 /*
1229 * The interface expects us to write an even number signaling that the
1230 * update is finished. Since the guest won't see the intermediate
1231 * state, we just increase by 2 at the end.
1232 */
1233 vcpu->hv_clock.version += 2;
1234
1235 shared_kaddr = kmap_atomic(vcpu->time_page);
1236
1237 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1238 sizeof(vcpu->hv_clock));
1239
1240 kunmap_atomic(shared_kaddr);
1241
1242 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1243 return 0;
1244 }
1245
1246 static bool msr_mtrr_valid(unsigned msr)
1247 {
1248 switch (msr) {
1249 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1250 case MSR_MTRRfix64K_00000:
1251 case MSR_MTRRfix16K_80000:
1252 case MSR_MTRRfix16K_A0000:
1253 case MSR_MTRRfix4K_C0000:
1254 case MSR_MTRRfix4K_C8000:
1255 case MSR_MTRRfix4K_D0000:
1256 case MSR_MTRRfix4K_D8000:
1257 case MSR_MTRRfix4K_E0000:
1258 case MSR_MTRRfix4K_E8000:
1259 case MSR_MTRRfix4K_F0000:
1260 case MSR_MTRRfix4K_F8000:
1261 case MSR_MTRRdefType:
1262 case MSR_IA32_CR_PAT:
1263 return true;
1264 case 0x2f8:
1265 return true;
1266 }
1267 return false;
1268 }
1269
1270 static bool valid_pat_type(unsigned t)
1271 {
1272 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1273 }
1274
1275 static bool valid_mtrr_type(unsigned t)
1276 {
1277 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1278 }
1279
1280 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1281 {
1282 int i;
1283
1284 if (!msr_mtrr_valid(msr))
1285 return false;
1286
1287 if (msr == MSR_IA32_CR_PAT) {
1288 for (i = 0; i < 8; i++)
1289 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1290 return false;
1291 return true;
1292 } else if (msr == MSR_MTRRdefType) {
1293 if (data & ~0xcff)
1294 return false;
1295 return valid_mtrr_type(data & 0xff);
1296 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1297 for (i = 0; i < 8 ; i++)
1298 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1299 return false;
1300 return true;
1301 }
1302
1303 /* variable MTRRs */
1304 return valid_mtrr_type(data & 0xff);
1305 }
1306
1307 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1308 {
1309 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1310
1311 if (!mtrr_valid(vcpu, msr, data))
1312 return 1;
1313
1314 if (msr == MSR_MTRRdefType) {
1315 vcpu->arch.mtrr_state.def_type = data;
1316 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1317 } else if (msr == MSR_MTRRfix64K_00000)
1318 p[0] = data;
1319 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1320 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1321 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1322 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1323 else if (msr == MSR_IA32_CR_PAT)
1324 vcpu->arch.pat = data;
1325 else { /* Variable MTRRs */
1326 int idx, is_mtrr_mask;
1327 u64 *pt;
1328
1329 idx = (msr - 0x200) / 2;
1330 is_mtrr_mask = msr - 0x200 - 2 * idx;
1331 if (!is_mtrr_mask)
1332 pt =
1333 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1334 else
1335 pt =
1336 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1337 *pt = data;
1338 }
1339
1340 kvm_mmu_reset_context(vcpu);
1341 return 0;
1342 }
1343
1344 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1345 {
1346 u64 mcg_cap = vcpu->arch.mcg_cap;
1347 unsigned bank_num = mcg_cap & 0xff;
1348
1349 switch (msr) {
1350 case MSR_IA32_MCG_STATUS:
1351 vcpu->arch.mcg_status = data;
1352 break;
1353 case MSR_IA32_MCG_CTL:
1354 if (!(mcg_cap & MCG_CTL_P))
1355 return 1;
1356 if (data != 0 && data != ~(u64)0)
1357 return -1;
1358 vcpu->arch.mcg_ctl = data;
1359 break;
1360 default:
1361 if (msr >= MSR_IA32_MC0_CTL &&
1362 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1363 u32 offset = msr - MSR_IA32_MC0_CTL;
1364 /* only 0 or all 1s can be written to IA32_MCi_CTL
1365 * some Linux kernels though clear bit 10 in bank 4 to
1366 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1367 * this to avoid an uncatched #GP in the guest
1368 */
1369 if ((offset & 0x3) == 0 &&
1370 data != 0 && (data | (1 << 10)) != ~(u64)0)
1371 return -1;
1372 vcpu->arch.mce_banks[offset] = data;
1373 break;
1374 }
1375 return 1;
1376 }
1377 return 0;
1378 }
1379
1380 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1381 {
1382 struct kvm *kvm = vcpu->kvm;
1383 int lm = is_long_mode(vcpu);
1384 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1385 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1386 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1387 : kvm->arch.xen_hvm_config.blob_size_32;
1388 u32 page_num = data & ~PAGE_MASK;
1389 u64 page_addr = data & PAGE_MASK;
1390 u8 *page;
1391 int r;
1392
1393 r = -E2BIG;
1394 if (page_num >= blob_size)
1395 goto out;
1396 r = -ENOMEM;
1397 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1398 if (IS_ERR(page)) {
1399 r = PTR_ERR(page);
1400 goto out;
1401 }
1402 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1403 goto out_free;
1404 r = 0;
1405 out_free:
1406 kfree(page);
1407 out:
1408 return r;
1409 }
1410
1411 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1412 {
1413 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1414 }
1415
1416 static bool kvm_hv_msr_partition_wide(u32 msr)
1417 {
1418 bool r = false;
1419 switch (msr) {
1420 case HV_X64_MSR_GUEST_OS_ID:
1421 case HV_X64_MSR_HYPERCALL:
1422 r = true;
1423 break;
1424 }
1425
1426 return r;
1427 }
1428
1429 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1430 {
1431 struct kvm *kvm = vcpu->kvm;
1432
1433 switch (msr) {
1434 case HV_X64_MSR_GUEST_OS_ID:
1435 kvm->arch.hv_guest_os_id = data;
1436 /* setting guest os id to zero disables hypercall page */
1437 if (!kvm->arch.hv_guest_os_id)
1438 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1439 break;
1440 case HV_X64_MSR_HYPERCALL: {
1441 u64 gfn;
1442 unsigned long addr;
1443 u8 instructions[4];
1444
1445 /* if guest os id is not set hypercall should remain disabled */
1446 if (!kvm->arch.hv_guest_os_id)
1447 break;
1448 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1449 kvm->arch.hv_hypercall = data;
1450 break;
1451 }
1452 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1453 addr = gfn_to_hva(kvm, gfn);
1454 if (kvm_is_error_hva(addr))
1455 return 1;
1456 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1457 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1458 if (__copy_to_user((void __user *)addr, instructions, 4))
1459 return 1;
1460 kvm->arch.hv_hypercall = data;
1461 break;
1462 }
1463 default:
1464 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1465 "data 0x%llx\n", msr, data);
1466 return 1;
1467 }
1468 return 0;
1469 }
1470
1471 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1472 {
1473 switch (msr) {
1474 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1475 unsigned long addr;
1476
1477 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1478 vcpu->arch.hv_vapic = data;
1479 break;
1480 }
1481 addr = gfn_to_hva(vcpu->kvm, data >>
1482 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1483 if (kvm_is_error_hva(addr))
1484 return 1;
1485 if (__clear_user((void __user *)addr, PAGE_SIZE))
1486 return 1;
1487 vcpu->arch.hv_vapic = data;
1488 break;
1489 }
1490 case HV_X64_MSR_EOI:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1492 case HV_X64_MSR_ICR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1494 case HV_X64_MSR_TPR:
1495 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1496 default:
1497 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1498 "data 0x%llx\n", msr, data);
1499 return 1;
1500 }
1501
1502 return 0;
1503 }
1504
1505 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1506 {
1507 gpa_t gpa = data & ~0x3f;
1508
1509 /* Bits 2:5 are reserved, Should be zero */
1510 if (data & 0x3c)
1511 return 1;
1512
1513 vcpu->arch.apf.msr_val = data;
1514
1515 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1516 kvm_clear_async_pf_completion_queue(vcpu);
1517 kvm_async_pf_hash_reset(vcpu);
1518 return 0;
1519 }
1520
1521 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1522 return 1;
1523
1524 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1525 kvm_async_pf_wakeup_all(vcpu);
1526 return 0;
1527 }
1528
1529 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1530 {
1531 if (vcpu->arch.time_page) {
1532 kvm_release_page_dirty(vcpu->arch.time_page);
1533 vcpu->arch.time_page = NULL;
1534 }
1535 }
1536
1537 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1538 {
1539 u64 delta;
1540
1541 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542 return;
1543
1544 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1545 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1546 vcpu->arch.st.accum_steal = delta;
1547 }
1548
1549 static void record_steal_time(struct kvm_vcpu *vcpu)
1550 {
1551 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1552 return;
1553
1554 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1556 return;
1557
1558 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1559 vcpu->arch.st.steal.version += 2;
1560 vcpu->arch.st.accum_steal = 0;
1561
1562 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1563 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1564 }
1565
1566 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1567 {
1568 bool pr = false;
1569
1570 switch (msr) {
1571 case MSR_EFER:
1572 return set_efer(vcpu, data);
1573 case MSR_K7_HWCR:
1574 data &= ~(u64)0x40; /* ignore flush filter disable */
1575 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1576 data &= ~(u64)0x8; /* ignore TLB cache disable */
1577 if (data != 0) {
1578 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1579 data);
1580 return 1;
1581 }
1582 break;
1583 case MSR_FAM10H_MMIO_CONF_BASE:
1584 if (data != 0) {
1585 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1586 "0x%llx\n", data);
1587 return 1;
1588 }
1589 break;
1590 case MSR_AMD64_NB_CFG:
1591 break;
1592 case MSR_IA32_DEBUGCTLMSR:
1593 if (!data) {
1594 /* We support the non-activated case already */
1595 break;
1596 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1597 /* Values other than LBR and BTF are vendor-specific,
1598 thus reserved and should throw a #GP */
1599 return 1;
1600 }
1601 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1602 __func__, data);
1603 break;
1604 case MSR_IA32_UCODE_REV:
1605 case MSR_IA32_UCODE_WRITE:
1606 case MSR_VM_HSAVE_PA:
1607 case MSR_AMD64_PATCH_LOADER:
1608 break;
1609 case 0x200 ... 0x2ff:
1610 return set_msr_mtrr(vcpu, msr, data);
1611 case MSR_IA32_APICBASE:
1612 kvm_set_apic_base(vcpu, data);
1613 break;
1614 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1615 return kvm_x2apic_msr_write(vcpu, msr, data);
1616 case MSR_IA32_TSCDEADLINE:
1617 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1618 break;
1619 case MSR_IA32_MISC_ENABLE:
1620 vcpu->arch.ia32_misc_enable_msr = data;
1621 break;
1622 case MSR_KVM_WALL_CLOCK_NEW:
1623 case MSR_KVM_WALL_CLOCK:
1624 vcpu->kvm->arch.wall_clock = data;
1625 kvm_write_wall_clock(vcpu->kvm, data);
1626 break;
1627 case MSR_KVM_SYSTEM_TIME_NEW:
1628 case MSR_KVM_SYSTEM_TIME: {
1629 kvmclock_reset(vcpu);
1630
1631 vcpu->arch.time = data;
1632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1633
1634 /* we verify if the enable bit is set... */
1635 if (!(data & 1))
1636 break;
1637
1638 /* ...but clean it before doing the actual write */
1639 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1640
1641 vcpu->arch.time_page =
1642 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1643
1644 if (is_error_page(vcpu->arch.time_page))
1645 vcpu->arch.time_page = NULL;
1646
1647 break;
1648 }
1649 case MSR_KVM_ASYNC_PF_EN:
1650 if (kvm_pv_enable_async_pf(vcpu, data))
1651 return 1;
1652 break;
1653 case MSR_KVM_STEAL_TIME:
1654
1655 if (unlikely(!sched_info_on()))
1656 return 1;
1657
1658 if (data & KVM_STEAL_RESERVED_MASK)
1659 return 1;
1660
1661 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1662 data & KVM_STEAL_VALID_BITS))
1663 return 1;
1664
1665 vcpu->arch.st.msr_val = data;
1666
1667 if (!(data & KVM_MSR_ENABLED))
1668 break;
1669
1670 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1671
1672 preempt_disable();
1673 accumulate_steal_time(vcpu);
1674 preempt_enable();
1675
1676 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1677
1678 break;
1679 case MSR_KVM_PV_EOI_EN:
1680 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1681 return 1;
1682 break;
1683
1684 case MSR_IA32_MCG_CTL:
1685 case MSR_IA32_MCG_STATUS:
1686 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1687 return set_msr_mce(vcpu, msr, data);
1688
1689 /* Performance counters are not protected by a CPUID bit,
1690 * so we should check all of them in the generic path for the sake of
1691 * cross vendor migration.
1692 * Writing a zero into the event select MSRs disables them,
1693 * which we perfectly emulate ;-). Any other value should be at least
1694 * reported, some guests depend on them.
1695 */
1696 case MSR_K7_EVNTSEL0:
1697 case MSR_K7_EVNTSEL1:
1698 case MSR_K7_EVNTSEL2:
1699 case MSR_K7_EVNTSEL3:
1700 if (data != 0)
1701 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1702 "0x%x data 0x%llx\n", msr, data);
1703 break;
1704 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1705 * so we ignore writes to make it happy.
1706 */
1707 case MSR_K7_PERFCTR0:
1708 case MSR_K7_PERFCTR1:
1709 case MSR_K7_PERFCTR2:
1710 case MSR_K7_PERFCTR3:
1711 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1712 "0x%x data 0x%llx\n", msr, data);
1713 break;
1714 case MSR_P6_PERFCTR0:
1715 case MSR_P6_PERFCTR1:
1716 pr = true;
1717 case MSR_P6_EVNTSEL0:
1718 case MSR_P6_EVNTSEL1:
1719 if (kvm_pmu_msr(vcpu, msr))
1720 return kvm_pmu_set_msr(vcpu, msr, data);
1721
1722 if (pr || data != 0)
1723 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1724 "0x%x data 0x%llx\n", msr, data);
1725 break;
1726 case MSR_K7_CLK_CTL:
1727 /*
1728 * Ignore all writes to this no longer documented MSR.
1729 * Writes are only relevant for old K7 processors,
1730 * all pre-dating SVM, but a recommended workaround from
1731 * AMD for these chips. It is possible to specify the
1732 * affected processor models on the command line, hence
1733 * the need to ignore the workaround.
1734 */
1735 break;
1736 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1737 if (kvm_hv_msr_partition_wide(msr)) {
1738 int r;
1739 mutex_lock(&vcpu->kvm->lock);
1740 r = set_msr_hyperv_pw(vcpu, msr, data);
1741 mutex_unlock(&vcpu->kvm->lock);
1742 return r;
1743 } else
1744 return set_msr_hyperv(vcpu, msr, data);
1745 break;
1746 case MSR_IA32_BBL_CR_CTL3:
1747 /* Drop writes to this legacy MSR -- see rdmsr
1748 * counterpart for further detail.
1749 */
1750 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1751 break;
1752 case MSR_AMD64_OSVW_ID_LENGTH:
1753 if (!guest_cpuid_has_osvw(vcpu))
1754 return 1;
1755 vcpu->arch.osvw.length = data;
1756 break;
1757 case MSR_AMD64_OSVW_STATUS:
1758 if (!guest_cpuid_has_osvw(vcpu))
1759 return 1;
1760 vcpu->arch.osvw.status = data;
1761 break;
1762 default:
1763 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1764 return xen_hvm_config(vcpu, data);
1765 if (kvm_pmu_msr(vcpu, msr))
1766 return kvm_pmu_set_msr(vcpu, msr, data);
1767 if (!ignore_msrs) {
1768 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1769 msr, data);
1770 return 1;
1771 } else {
1772 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1773 msr, data);
1774 break;
1775 }
1776 }
1777 return 0;
1778 }
1779 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1780
1781
1782 /*
1783 * Reads an msr value (of 'msr_index') into 'pdata'.
1784 * Returns 0 on success, non-0 otherwise.
1785 * Assumes vcpu_load() was already called.
1786 */
1787 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1788 {
1789 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1790 }
1791
1792 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793 {
1794 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1795
1796 if (!msr_mtrr_valid(msr))
1797 return 1;
1798
1799 if (msr == MSR_MTRRdefType)
1800 *pdata = vcpu->arch.mtrr_state.def_type +
1801 (vcpu->arch.mtrr_state.enabled << 10);
1802 else if (msr == MSR_MTRRfix64K_00000)
1803 *pdata = p[0];
1804 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1805 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1806 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1807 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1808 else if (msr == MSR_IA32_CR_PAT)
1809 *pdata = vcpu->arch.pat;
1810 else { /* Variable MTRRs */
1811 int idx, is_mtrr_mask;
1812 u64 *pt;
1813
1814 idx = (msr - 0x200) / 2;
1815 is_mtrr_mask = msr - 0x200 - 2 * idx;
1816 if (!is_mtrr_mask)
1817 pt =
1818 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1819 else
1820 pt =
1821 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1822 *pdata = *pt;
1823 }
1824
1825 return 0;
1826 }
1827
1828 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1829 {
1830 u64 data;
1831 u64 mcg_cap = vcpu->arch.mcg_cap;
1832 unsigned bank_num = mcg_cap & 0xff;
1833
1834 switch (msr) {
1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
1837 data = 0;
1838 break;
1839 case MSR_IA32_MCG_CAP:
1840 data = vcpu->arch.mcg_cap;
1841 break;
1842 case MSR_IA32_MCG_CTL:
1843 if (!(mcg_cap & MCG_CTL_P))
1844 return 1;
1845 data = vcpu->arch.mcg_ctl;
1846 break;
1847 case MSR_IA32_MCG_STATUS:
1848 data = vcpu->arch.mcg_status;
1849 break;
1850 default:
1851 if (msr >= MSR_IA32_MC0_CTL &&
1852 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1853 u32 offset = msr - MSR_IA32_MC0_CTL;
1854 data = vcpu->arch.mce_banks[offset];
1855 break;
1856 }
1857 return 1;
1858 }
1859 *pdata = data;
1860 return 0;
1861 }
1862
1863 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1864 {
1865 u64 data = 0;
1866 struct kvm *kvm = vcpu->kvm;
1867
1868 switch (msr) {
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 data = kvm->arch.hv_guest_os_id;
1871 break;
1872 case HV_X64_MSR_HYPERCALL:
1873 data = kvm->arch.hv_hypercall;
1874 break;
1875 default:
1876 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1877 return 1;
1878 }
1879
1880 *pdata = data;
1881 return 0;
1882 }
1883
1884 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1885 {
1886 u64 data = 0;
1887
1888 switch (msr) {
1889 case HV_X64_MSR_VP_INDEX: {
1890 int r;
1891 struct kvm_vcpu *v;
1892 kvm_for_each_vcpu(r, v, vcpu->kvm)
1893 if (v == vcpu)
1894 data = r;
1895 break;
1896 }
1897 case HV_X64_MSR_EOI:
1898 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1899 case HV_X64_MSR_ICR:
1900 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1901 case HV_X64_MSR_TPR:
1902 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1903 case HV_X64_MSR_APIC_ASSIST_PAGE:
1904 data = vcpu->arch.hv_vapic;
1905 break;
1906 default:
1907 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1908 return 1;
1909 }
1910 *pdata = data;
1911 return 0;
1912 }
1913
1914 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1915 {
1916 u64 data;
1917
1918 switch (msr) {
1919 case MSR_IA32_PLATFORM_ID:
1920 case MSR_IA32_EBL_CR_POWERON:
1921 case MSR_IA32_DEBUGCTLMSR:
1922 case MSR_IA32_LASTBRANCHFROMIP:
1923 case MSR_IA32_LASTBRANCHTOIP:
1924 case MSR_IA32_LASTINTFROMIP:
1925 case MSR_IA32_LASTINTTOIP:
1926 case MSR_K8_SYSCFG:
1927 case MSR_K7_HWCR:
1928 case MSR_VM_HSAVE_PA:
1929 case MSR_K7_EVNTSEL0:
1930 case MSR_K7_PERFCTR0:
1931 case MSR_K8_INT_PENDING_MSG:
1932 case MSR_AMD64_NB_CFG:
1933 case MSR_FAM10H_MMIO_CONF_BASE:
1934 data = 0;
1935 break;
1936 case MSR_P6_PERFCTR0:
1937 case MSR_P6_PERFCTR1:
1938 case MSR_P6_EVNTSEL0:
1939 case MSR_P6_EVNTSEL1:
1940 if (kvm_pmu_msr(vcpu, msr))
1941 return kvm_pmu_get_msr(vcpu, msr, pdata);
1942 data = 0;
1943 break;
1944 case MSR_IA32_UCODE_REV:
1945 data = 0x100000000ULL;
1946 break;
1947 case MSR_MTRRcap:
1948 data = 0x500 | KVM_NR_VAR_MTRR;
1949 break;
1950 case 0x200 ... 0x2ff:
1951 return get_msr_mtrr(vcpu, msr, pdata);
1952 case 0xcd: /* fsb frequency */
1953 data = 3;
1954 break;
1955 /*
1956 * MSR_EBC_FREQUENCY_ID
1957 * Conservative value valid for even the basic CPU models.
1958 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1959 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1960 * and 266MHz for model 3, or 4. Set Core Clock
1961 * Frequency to System Bus Frequency Ratio to 1 (bits
1962 * 31:24) even though these are only valid for CPU
1963 * models > 2, however guests may end up dividing or
1964 * multiplying by zero otherwise.
1965 */
1966 case MSR_EBC_FREQUENCY_ID:
1967 data = 1 << 24;
1968 break;
1969 case MSR_IA32_APICBASE:
1970 data = kvm_get_apic_base(vcpu);
1971 break;
1972 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1973 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1974 break;
1975 case MSR_IA32_TSCDEADLINE:
1976 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1977 break;
1978 case MSR_IA32_MISC_ENABLE:
1979 data = vcpu->arch.ia32_misc_enable_msr;
1980 break;
1981 case MSR_IA32_PERF_STATUS:
1982 /* TSC increment by tick */
1983 data = 1000ULL;
1984 /* CPU multiplier */
1985 data |= (((uint64_t)4ULL) << 40);
1986 break;
1987 case MSR_EFER:
1988 data = vcpu->arch.efer;
1989 break;
1990 case MSR_KVM_WALL_CLOCK:
1991 case MSR_KVM_WALL_CLOCK_NEW:
1992 data = vcpu->kvm->arch.wall_clock;
1993 break;
1994 case MSR_KVM_SYSTEM_TIME:
1995 case MSR_KVM_SYSTEM_TIME_NEW:
1996 data = vcpu->arch.time;
1997 break;
1998 case MSR_KVM_ASYNC_PF_EN:
1999 data = vcpu->arch.apf.msr_val;
2000 break;
2001 case MSR_KVM_STEAL_TIME:
2002 data = vcpu->arch.st.msr_val;
2003 break;
2004 case MSR_IA32_P5_MC_ADDR:
2005 case MSR_IA32_P5_MC_TYPE:
2006 case MSR_IA32_MCG_CAP:
2007 case MSR_IA32_MCG_CTL:
2008 case MSR_IA32_MCG_STATUS:
2009 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2010 return get_msr_mce(vcpu, msr, pdata);
2011 case MSR_K7_CLK_CTL:
2012 /*
2013 * Provide expected ramp-up count for K7. All other
2014 * are set to zero, indicating minimum divisors for
2015 * every field.
2016 *
2017 * This prevents guest kernels on AMD host with CPU
2018 * type 6, model 8 and higher from exploding due to
2019 * the rdmsr failing.
2020 */
2021 data = 0x20000000;
2022 break;
2023 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2024 if (kvm_hv_msr_partition_wide(msr)) {
2025 int r;
2026 mutex_lock(&vcpu->kvm->lock);
2027 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2028 mutex_unlock(&vcpu->kvm->lock);
2029 return r;
2030 } else
2031 return get_msr_hyperv(vcpu, msr, pdata);
2032 break;
2033 case MSR_IA32_BBL_CR_CTL3:
2034 /* This legacy MSR exists but isn't fully documented in current
2035 * silicon. It is however accessed by winxp in very narrow
2036 * scenarios where it sets bit #19, itself documented as
2037 * a "reserved" bit. Best effort attempt to source coherent
2038 * read data here should the balance of the register be
2039 * interpreted by the guest:
2040 *
2041 * L2 cache control register 3: 64GB range, 256KB size,
2042 * enabled, latency 0x1, configured
2043 */
2044 data = 0xbe702111;
2045 break;
2046 case MSR_AMD64_OSVW_ID_LENGTH:
2047 if (!guest_cpuid_has_osvw(vcpu))
2048 return 1;
2049 data = vcpu->arch.osvw.length;
2050 break;
2051 case MSR_AMD64_OSVW_STATUS:
2052 if (!guest_cpuid_has_osvw(vcpu))
2053 return 1;
2054 data = vcpu->arch.osvw.status;
2055 break;
2056 default:
2057 if (kvm_pmu_msr(vcpu, msr))
2058 return kvm_pmu_get_msr(vcpu, msr, pdata);
2059 if (!ignore_msrs) {
2060 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2061 return 1;
2062 } else {
2063 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2064 data = 0;
2065 }
2066 break;
2067 }
2068 *pdata = data;
2069 return 0;
2070 }
2071 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2072
2073 /*
2074 * Read or write a bunch of msrs. All parameters are kernel addresses.
2075 *
2076 * @return number of msrs set successfully.
2077 */
2078 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2079 struct kvm_msr_entry *entries,
2080 int (*do_msr)(struct kvm_vcpu *vcpu,
2081 unsigned index, u64 *data))
2082 {
2083 int i, idx;
2084
2085 idx = srcu_read_lock(&vcpu->kvm->srcu);
2086 for (i = 0; i < msrs->nmsrs; ++i)
2087 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2088 break;
2089 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2090
2091 return i;
2092 }
2093
2094 /*
2095 * Read or write a bunch of msrs. Parameters are user addresses.
2096 *
2097 * @return number of msrs set successfully.
2098 */
2099 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2100 int (*do_msr)(struct kvm_vcpu *vcpu,
2101 unsigned index, u64 *data),
2102 int writeback)
2103 {
2104 struct kvm_msrs msrs;
2105 struct kvm_msr_entry *entries;
2106 int r, n;
2107 unsigned size;
2108
2109 r = -EFAULT;
2110 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2111 goto out;
2112
2113 r = -E2BIG;
2114 if (msrs.nmsrs >= MAX_IO_MSRS)
2115 goto out;
2116
2117 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2118 entries = memdup_user(user_msrs->entries, size);
2119 if (IS_ERR(entries)) {
2120 r = PTR_ERR(entries);
2121 goto out;
2122 }
2123
2124 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2125 if (r < 0)
2126 goto out_free;
2127
2128 r = -EFAULT;
2129 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2130 goto out_free;
2131
2132 r = n;
2133
2134 out_free:
2135 kfree(entries);
2136 out:
2137 return r;
2138 }
2139
2140 int kvm_dev_ioctl_check_extension(long ext)
2141 {
2142 int r;
2143
2144 switch (ext) {
2145 case KVM_CAP_IRQCHIP:
2146 case KVM_CAP_HLT:
2147 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2148 case KVM_CAP_SET_TSS_ADDR:
2149 case KVM_CAP_EXT_CPUID:
2150 case KVM_CAP_CLOCKSOURCE:
2151 case KVM_CAP_PIT:
2152 case KVM_CAP_NOP_IO_DELAY:
2153 case KVM_CAP_MP_STATE:
2154 case KVM_CAP_SYNC_MMU:
2155 case KVM_CAP_USER_NMI:
2156 case KVM_CAP_REINJECT_CONTROL:
2157 case KVM_CAP_IRQ_INJECT_STATUS:
2158 case KVM_CAP_ASSIGN_DEV_IRQ:
2159 case KVM_CAP_IRQFD:
2160 case KVM_CAP_IOEVENTFD:
2161 case KVM_CAP_PIT2:
2162 case KVM_CAP_PIT_STATE2:
2163 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2164 case KVM_CAP_XEN_HVM:
2165 case KVM_CAP_ADJUST_CLOCK:
2166 case KVM_CAP_VCPU_EVENTS:
2167 case KVM_CAP_HYPERV:
2168 case KVM_CAP_HYPERV_VAPIC:
2169 case KVM_CAP_HYPERV_SPIN:
2170 case KVM_CAP_PCI_SEGMENT:
2171 case KVM_CAP_DEBUGREGS:
2172 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2173 case KVM_CAP_XSAVE:
2174 case KVM_CAP_ASYNC_PF:
2175 case KVM_CAP_GET_TSC_KHZ:
2176 case KVM_CAP_PCI_2_3:
2177 case KVM_CAP_KVMCLOCK_CTRL:
2178 case KVM_CAP_READONLY_MEM:
2179 r = 1;
2180 break;
2181 case KVM_CAP_COALESCED_MMIO:
2182 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2183 break;
2184 case KVM_CAP_VAPIC:
2185 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2186 break;
2187 case KVM_CAP_NR_VCPUS:
2188 r = KVM_SOFT_MAX_VCPUS;
2189 break;
2190 case KVM_CAP_MAX_VCPUS:
2191 r = KVM_MAX_VCPUS;
2192 break;
2193 case KVM_CAP_NR_MEMSLOTS:
2194 r = KVM_MEMORY_SLOTS;
2195 break;
2196 case KVM_CAP_PV_MMU: /* obsolete */
2197 r = 0;
2198 break;
2199 case KVM_CAP_IOMMU:
2200 r = iommu_present(&pci_bus_type);
2201 break;
2202 case KVM_CAP_MCE:
2203 r = KVM_MAX_MCE_BANKS;
2204 break;
2205 case KVM_CAP_XCRS:
2206 r = cpu_has_xsave;
2207 break;
2208 case KVM_CAP_TSC_CONTROL:
2209 r = kvm_has_tsc_control;
2210 break;
2211 case KVM_CAP_TSC_DEADLINE_TIMER:
2212 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2213 break;
2214 default:
2215 r = 0;
2216 break;
2217 }
2218 return r;
2219
2220 }
2221
2222 long kvm_arch_dev_ioctl(struct file *filp,
2223 unsigned int ioctl, unsigned long arg)
2224 {
2225 void __user *argp = (void __user *)arg;
2226 long r;
2227
2228 switch (ioctl) {
2229 case KVM_GET_MSR_INDEX_LIST: {
2230 struct kvm_msr_list __user *user_msr_list = argp;
2231 struct kvm_msr_list msr_list;
2232 unsigned n;
2233
2234 r = -EFAULT;
2235 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2236 goto out;
2237 n = msr_list.nmsrs;
2238 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2239 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2240 goto out;
2241 r = -E2BIG;
2242 if (n < msr_list.nmsrs)
2243 goto out;
2244 r = -EFAULT;
2245 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2246 num_msrs_to_save * sizeof(u32)))
2247 goto out;
2248 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2249 &emulated_msrs,
2250 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2251 goto out;
2252 r = 0;
2253 break;
2254 }
2255 case KVM_GET_SUPPORTED_CPUID: {
2256 struct kvm_cpuid2 __user *cpuid_arg = argp;
2257 struct kvm_cpuid2 cpuid;
2258
2259 r = -EFAULT;
2260 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2261 goto out;
2262 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2263 cpuid_arg->entries);
2264 if (r)
2265 goto out;
2266
2267 r = -EFAULT;
2268 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2269 goto out;
2270 r = 0;
2271 break;
2272 }
2273 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2274 u64 mce_cap;
2275
2276 mce_cap = KVM_MCE_CAP_SUPPORTED;
2277 r = -EFAULT;
2278 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2279 goto out;
2280 r = 0;
2281 break;
2282 }
2283 default:
2284 r = -EINVAL;
2285 }
2286 out:
2287 return r;
2288 }
2289
2290 static void wbinvd_ipi(void *garbage)
2291 {
2292 wbinvd();
2293 }
2294
2295 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2296 {
2297 return vcpu->kvm->arch.iommu_domain &&
2298 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2299 }
2300
2301 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2302 {
2303 /* Address WBINVD may be executed by guest */
2304 if (need_emulate_wbinvd(vcpu)) {
2305 if (kvm_x86_ops->has_wbinvd_exit())
2306 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2307 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2308 smp_call_function_single(vcpu->cpu,
2309 wbinvd_ipi, NULL, 1);
2310 }
2311
2312 kvm_x86_ops->vcpu_load(vcpu, cpu);
2313
2314 /* Apply any externally detected TSC adjustments (due to suspend) */
2315 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2316 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2317 vcpu->arch.tsc_offset_adjustment = 0;
2318 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2319 }
2320
2321 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2322 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2323 native_read_tsc() - vcpu->arch.last_host_tsc;
2324 if (tsc_delta < 0)
2325 mark_tsc_unstable("KVM discovered backwards TSC");
2326 if (check_tsc_unstable()) {
2327 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2328 vcpu->arch.last_guest_tsc);
2329 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2330 vcpu->arch.tsc_catchup = 1;
2331 }
2332 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2333 if (vcpu->cpu != cpu)
2334 kvm_migrate_timers(vcpu);
2335 vcpu->cpu = cpu;
2336 }
2337
2338 accumulate_steal_time(vcpu);
2339 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2340 }
2341
2342 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2343 {
2344 kvm_x86_ops->vcpu_put(vcpu);
2345 kvm_put_guest_fpu(vcpu);
2346 vcpu->arch.last_host_tsc = native_read_tsc();
2347 }
2348
2349 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2350 struct kvm_lapic_state *s)
2351 {
2352 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2353
2354 return 0;
2355 }
2356
2357 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2358 struct kvm_lapic_state *s)
2359 {
2360 kvm_apic_post_state_restore(vcpu, s);
2361 update_cr8_intercept(vcpu);
2362
2363 return 0;
2364 }
2365
2366 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2367 struct kvm_interrupt *irq)
2368 {
2369 if (irq->irq < 0 || irq->irq >= 256)
2370 return -EINVAL;
2371 if (irqchip_in_kernel(vcpu->kvm))
2372 return -ENXIO;
2373
2374 kvm_queue_interrupt(vcpu, irq->irq, false);
2375 kvm_make_request(KVM_REQ_EVENT, vcpu);
2376
2377 return 0;
2378 }
2379
2380 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2381 {
2382 kvm_inject_nmi(vcpu);
2383
2384 return 0;
2385 }
2386
2387 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2388 struct kvm_tpr_access_ctl *tac)
2389 {
2390 if (tac->flags)
2391 return -EINVAL;
2392 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2393 return 0;
2394 }
2395
2396 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2397 u64 mcg_cap)
2398 {
2399 int r;
2400 unsigned bank_num = mcg_cap & 0xff, bank;
2401
2402 r = -EINVAL;
2403 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2404 goto out;
2405 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2406 goto out;
2407 r = 0;
2408 vcpu->arch.mcg_cap = mcg_cap;
2409 /* Init IA32_MCG_CTL to all 1s */
2410 if (mcg_cap & MCG_CTL_P)
2411 vcpu->arch.mcg_ctl = ~(u64)0;
2412 /* Init IA32_MCi_CTL to all 1s */
2413 for (bank = 0; bank < bank_num; bank++)
2414 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2415 out:
2416 return r;
2417 }
2418
2419 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2420 struct kvm_x86_mce *mce)
2421 {
2422 u64 mcg_cap = vcpu->arch.mcg_cap;
2423 unsigned bank_num = mcg_cap & 0xff;
2424 u64 *banks = vcpu->arch.mce_banks;
2425
2426 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2427 return -EINVAL;
2428 /*
2429 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2430 * reporting is disabled
2431 */
2432 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2433 vcpu->arch.mcg_ctl != ~(u64)0)
2434 return 0;
2435 banks += 4 * mce->bank;
2436 /*
2437 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2438 * reporting is disabled for the bank
2439 */
2440 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2441 return 0;
2442 if (mce->status & MCI_STATUS_UC) {
2443 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2444 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2445 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2446 return 0;
2447 }
2448 if (banks[1] & MCI_STATUS_VAL)
2449 mce->status |= MCI_STATUS_OVER;
2450 banks[2] = mce->addr;
2451 banks[3] = mce->misc;
2452 vcpu->arch.mcg_status = mce->mcg_status;
2453 banks[1] = mce->status;
2454 kvm_queue_exception(vcpu, MC_VECTOR);
2455 } else if (!(banks[1] & MCI_STATUS_VAL)
2456 || !(banks[1] & MCI_STATUS_UC)) {
2457 if (banks[1] & MCI_STATUS_VAL)
2458 mce->status |= MCI_STATUS_OVER;
2459 banks[2] = mce->addr;
2460 banks[3] = mce->misc;
2461 banks[1] = mce->status;
2462 } else
2463 banks[1] |= MCI_STATUS_OVER;
2464 return 0;
2465 }
2466
2467 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2468 struct kvm_vcpu_events *events)
2469 {
2470 process_nmi(vcpu);
2471 events->exception.injected =
2472 vcpu->arch.exception.pending &&
2473 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2474 events->exception.nr = vcpu->arch.exception.nr;
2475 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2476 events->exception.pad = 0;
2477 events->exception.error_code = vcpu->arch.exception.error_code;
2478
2479 events->interrupt.injected =
2480 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2481 events->interrupt.nr = vcpu->arch.interrupt.nr;
2482 events->interrupt.soft = 0;
2483 events->interrupt.shadow =
2484 kvm_x86_ops->get_interrupt_shadow(vcpu,
2485 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2486
2487 events->nmi.injected = vcpu->arch.nmi_injected;
2488 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2489 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2490 events->nmi.pad = 0;
2491
2492 events->sipi_vector = vcpu->arch.sipi_vector;
2493
2494 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2495 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2496 | KVM_VCPUEVENT_VALID_SHADOW);
2497 memset(&events->reserved, 0, sizeof(events->reserved));
2498 }
2499
2500 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2501 struct kvm_vcpu_events *events)
2502 {
2503 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2504 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2505 | KVM_VCPUEVENT_VALID_SHADOW))
2506 return -EINVAL;
2507
2508 process_nmi(vcpu);
2509 vcpu->arch.exception.pending = events->exception.injected;
2510 vcpu->arch.exception.nr = events->exception.nr;
2511 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2512 vcpu->arch.exception.error_code = events->exception.error_code;
2513
2514 vcpu->arch.interrupt.pending = events->interrupt.injected;
2515 vcpu->arch.interrupt.nr = events->interrupt.nr;
2516 vcpu->arch.interrupt.soft = events->interrupt.soft;
2517 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2518 kvm_x86_ops->set_interrupt_shadow(vcpu,
2519 events->interrupt.shadow);
2520
2521 vcpu->arch.nmi_injected = events->nmi.injected;
2522 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2523 vcpu->arch.nmi_pending = events->nmi.pending;
2524 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2525
2526 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2527 vcpu->arch.sipi_vector = events->sipi_vector;
2528
2529 kvm_make_request(KVM_REQ_EVENT, vcpu);
2530
2531 return 0;
2532 }
2533
2534 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2535 struct kvm_debugregs *dbgregs)
2536 {
2537 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2538 dbgregs->dr6 = vcpu->arch.dr6;
2539 dbgregs->dr7 = vcpu->arch.dr7;
2540 dbgregs->flags = 0;
2541 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2542 }
2543
2544 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2545 struct kvm_debugregs *dbgregs)
2546 {
2547 if (dbgregs->flags)
2548 return -EINVAL;
2549
2550 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2551 vcpu->arch.dr6 = dbgregs->dr6;
2552 vcpu->arch.dr7 = dbgregs->dr7;
2553
2554 return 0;
2555 }
2556
2557 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2558 struct kvm_xsave *guest_xsave)
2559 {
2560 if (cpu_has_xsave)
2561 memcpy(guest_xsave->region,
2562 &vcpu->arch.guest_fpu.state->xsave,
2563 xstate_size);
2564 else {
2565 memcpy(guest_xsave->region,
2566 &vcpu->arch.guest_fpu.state->fxsave,
2567 sizeof(struct i387_fxsave_struct));
2568 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2569 XSTATE_FPSSE;
2570 }
2571 }
2572
2573 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2574 struct kvm_xsave *guest_xsave)
2575 {
2576 u64 xstate_bv =
2577 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2578
2579 if (cpu_has_xsave)
2580 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2581 guest_xsave->region, xstate_size);
2582 else {
2583 if (xstate_bv & ~XSTATE_FPSSE)
2584 return -EINVAL;
2585 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2586 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2587 }
2588 return 0;
2589 }
2590
2591 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2592 struct kvm_xcrs *guest_xcrs)
2593 {
2594 if (!cpu_has_xsave) {
2595 guest_xcrs->nr_xcrs = 0;
2596 return;
2597 }
2598
2599 guest_xcrs->nr_xcrs = 1;
2600 guest_xcrs->flags = 0;
2601 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2602 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2603 }
2604
2605 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2606 struct kvm_xcrs *guest_xcrs)
2607 {
2608 int i, r = 0;
2609
2610 if (!cpu_has_xsave)
2611 return -EINVAL;
2612
2613 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2614 return -EINVAL;
2615
2616 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2617 /* Only support XCR0 currently */
2618 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2619 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2620 guest_xcrs->xcrs[0].value);
2621 break;
2622 }
2623 if (r)
2624 r = -EINVAL;
2625 return r;
2626 }
2627
2628 /*
2629 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2630 * stopped by the hypervisor. This function will be called from the host only.
2631 * EINVAL is returned when the host attempts to set the flag for a guest that
2632 * does not support pv clocks.
2633 */
2634 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2635 {
2636 if (!vcpu->arch.time_page)
2637 return -EINVAL;
2638 vcpu->arch.pvclock_set_guest_stopped_request = true;
2639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2640 return 0;
2641 }
2642
2643 long kvm_arch_vcpu_ioctl(struct file *filp,
2644 unsigned int ioctl, unsigned long arg)
2645 {
2646 struct kvm_vcpu *vcpu = filp->private_data;
2647 void __user *argp = (void __user *)arg;
2648 int r;
2649 union {
2650 struct kvm_lapic_state *lapic;
2651 struct kvm_xsave *xsave;
2652 struct kvm_xcrs *xcrs;
2653 void *buffer;
2654 } u;
2655
2656 u.buffer = NULL;
2657 switch (ioctl) {
2658 case KVM_GET_LAPIC: {
2659 r = -EINVAL;
2660 if (!vcpu->arch.apic)
2661 goto out;
2662 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2663
2664 r = -ENOMEM;
2665 if (!u.lapic)
2666 goto out;
2667 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2668 if (r)
2669 goto out;
2670 r = -EFAULT;
2671 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2672 goto out;
2673 r = 0;
2674 break;
2675 }
2676 case KVM_SET_LAPIC: {
2677 r = -EINVAL;
2678 if (!vcpu->arch.apic)
2679 goto out;
2680 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2681 if (IS_ERR(u.lapic)) {
2682 r = PTR_ERR(u.lapic);
2683 goto out;
2684 }
2685
2686 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2687 if (r)
2688 goto out;
2689 r = 0;
2690 break;
2691 }
2692 case KVM_INTERRUPT: {
2693 struct kvm_interrupt irq;
2694
2695 r = -EFAULT;
2696 if (copy_from_user(&irq, argp, sizeof irq))
2697 goto out;
2698 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2699 if (r)
2700 goto out;
2701 r = 0;
2702 break;
2703 }
2704 case KVM_NMI: {
2705 r = kvm_vcpu_ioctl_nmi(vcpu);
2706 if (r)
2707 goto out;
2708 r = 0;
2709 break;
2710 }
2711 case KVM_SET_CPUID: {
2712 struct kvm_cpuid __user *cpuid_arg = argp;
2713 struct kvm_cpuid cpuid;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717 goto out;
2718 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2719 if (r)
2720 goto out;
2721 break;
2722 }
2723 case KVM_SET_CPUID2: {
2724 struct kvm_cpuid2 __user *cpuid_arg = argp;
2725 struct kvm_cpuid2 cpuid;
2726
2727 r = -EFAULT;
2728 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2729 goto out;
2730 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2731 cpuid_arg->entries);
2732 if (r)
2733 goto out;
2734 break;
2735 }
2736 case KVM_GET_CPUID2: {
2737 struct kvm_cpuid2 __user *cpuid_arg = argp;
2738 struct kvm_cpuid2 cpuid;
2739
2740 r = -EFAULT;
2741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2742 goto out;
2743 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2744 cpuid_arg->entries);
2745 if (r)
2746 goto out;
2747 r = -EFAULT;
2748 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2749 goto out;
2750 r = 0;
2751 break;
2752 }
2753 case KVM_GET_MSRS:
2754 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2755 break;
2756 case KVM_SET_MSRS:
2757 r = msr_io(vcpu, argp, do_set_msr, 0);
2758 break;
2759 case KVM_TPR_ACCESS_REPORTING: {
2760 struct kvm_tpr_access_ctl tac;
2761
2762 r = -EFAULT;
2763 if (copy_from_user(&tac, argp, sizeof tac))
2764 goto out;
2765 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2766 if (r)
2767 goto out;
2768 r = -EFAULT;
2769 if (copy_to_user(argp, &tac, sizeof tac))
2770 goto out;
2771 r = 0;
2772 break;
2773 };
2774 case KVM_SET_VAPIC_ADDR: {
2775 struct kvm_vapic_addr va;
2776
2777 r = -EINVAL;
2778 if (!irqchip_in_kernel(vcpu->kvm))
2779 goto out;
2780 r = -EFAULT;
2781 if (copy_from_user(&va, argp, sizeof va))
2782 goto out;
2783 r = 0;
2784 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2785 break;
2786 }
2787 case KVM_X86_SETUP_MCE: {
2788 u64 mcg_cap;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2792 goto out;
2793 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2794 break;
2795 }
2796 case KVM_X86_SET_MCE: {
2797 struct kvm_x86_mce mce;
2798
2799 r = -EFAULT;
2800 if (copy_from_user(&mce, argp, sizeof mce))
2801 goto out;
2802 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2803 break;
2804 }
2805 case KVM_GET_VCPU_EVENTS: {
2806 struct kvm_vcpu_events events;
2807
2808 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2809
2810 r = -EFAULT;
2811 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2812 break;
2813 r = 0;
2814 break;
2815 }
2816 case KVM_SET_VCPU_EVENTS: {
2817 struct kvm_vcpu_events events;
2818
2819 r = -EFAULT;
2820 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2821 break;
2822
2823 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2824 break;
2825 }
2826 case KVM_GET_DEBUGREGS: {
2827 struct kvm_debugregs dbgregs;
2828
2829 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2830
2831 r = -EFAULT;
2832 if (copy_to_user(argp, &dbgregs,
2833 sizeof(struct kvm_debugregs)))
2834 break;
2835 r = 0;
2836 break;
2837 }
2838 case KVM_SET_DEBUGREGS: {
2839 struct kvm_debugregs dbgregs;
2840
2841 r = -EFAULT;
2842 if (copy_from_user(&dbgregs, argp,
2843 sizeof(struct kvm_debugregs)))
2844 break;
2845
2846 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2847 break;
2848 }
2849 case KVM_GET_XSAVE: {
2850 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2851 r = -ENOMEM;
2852 if (!u.xsave)
2853 break;
2854
2855 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2856
2857 r = -EFAULT;
2858 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2859 break;
2860 r = 0;
2861 break;
2862 }
2863 case KVM_SET_XSAVE: {
2864 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2865 if (IS_ERR(u.xsave)) {
2866 r = PTR_ERR(u.xsave);
2867 goto out;
2868 }
2869
2870 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2871 break;
2872 }
2873 case KVM_GET_XCRS: {
2874 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2875 r = -ENOMEM;
2876 if (!u.xcrs)
2877 break;
2878
2879 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2880
2881 r = -EFAULT;
2882 if (copy_to_user(argp, u.xcrs,
2883 sizeof(struct kvm_xcrs)))
2884 break;
2885 r = 0;
2886 break;
2887 }
2888 case KVM_SET_XCRS: {
2889 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2890 if (IS_ERR(u.xcrs)) {
2891 r = PTR_ERR(u.xcrs);
2892 goto out;
2893 }
2894
2895 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2896 break;
2897 }
2898 case KVM_SET_TSC_KHZ: {
2899 u32 user_tsc_khz;
2900
2901 r = -EINVAL;
2902 user_tsc_khz = (u32)arg;
2903
2904 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2905 goto out;
2906
2907 if (user_tsc_khz == 0)
2908 user_tsc_khz = tsc_khz;
2909
2910 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2911
2912 r = 0;
2913 goto out;
2914 }
2915 case KVM_GET_TSC_KHZ: {
2916 r = vcpu->arch.virtual_tsc_khz;
2917 goto out;
2918 }
2919 case KVM_KVMCLOCK_CTRL: {
2920 r = kvm_set_guest_paused(vcpu);
2921 goto out;
2922 }
2923 default:
2924 r = -EINVAL;
2925 }
2926 out:
2927 kfree(u.buffer);
2928 return r;
2929 }
2930
2931 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2932 {
2933 return VM_FAULT_SIGBUS;
2934 }
2935
2936 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2937 {
2938 int ret;
2939
2940 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2941 return -1;
2942 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2943 return ret;
2944 }
2945
2946 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2947 u64 ident_addr)
2948 {
2949 kvm->arch.ept_identity_map_addr = ident_addr;
2950 return 0;
2951 }
2952
2953 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2954 u32 kvm_nr_mmu_pages)
2955 {
2956 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2957 return -EINVAL;
2958
2959 mutex_lock(&kvm->slots_lock);
2960 spin_lock(&kvm->mmu_lock);
2961
2962 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2963 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2964
2965 spin_unlock(&kvm->mmu_lock);
2966 mutex_unlock(&kvm->slots_lock);
2967 return 0;
2968 }
2969
2970 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2971 {
2972 return kvm->arch.n_max_mmu_pages;
2973 }
2974
2975 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2976 {
2977 int r;
2978
2979 r = 0;
2980 switch (chip->chip_id) {
2981 case KVM_IRQCHIP_PIC_MASTER:
2982 memcpy(&chip->chip.pic,
2983 &pic_irqchip(kvm)->pics[0],
2984 sizeof(struct kvm_pic_state));
2985 break;
2986 case KVM_IRQCHIP_PIC_SLAVE:
2987 memcpy(&chip->chip.pic,
2988 &pic_irqchip(kvm)->pics[1],
2989 sizeof(struct kvm_pic_state));
2990 break;
2991 case KVM_IRQCHIP_IOAPIC:
2992 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2993 break;
2994 default:
2995 r = -EINVAL;
2996 break;
2997 }
2998 return r;
2999 }
3000
3001 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3002 {
3003 int r;
3004
3005 r = 0;
3006 switch (chip->chip_id) {
3007 case KVM_IRQCHIP_PIC_MASTER:
3008 spin_lock(&pic_irqchip(kvm)->lock);
3009 memcpy(&pic_irqchip(kvm)->pics[0],
3010 &chip->chip.pic,
3011 sizeof(struct kvm_pic_state));
3012 spin_unlock(&pic_irqchip(kvm)->lock);
3013 break;
3014 case KVM_IRQCHIP_PIC_SLAVE:
3015 spin_lock(&pic_irqchip(kvm)->lock);
3016 memcpy(&pic_irqchip(kvm)->pics[1],
3017 &chip->chip.pic,
3018 sizeof(struct kvm_pic_state));
3019 spin_unlock(&pic_irqchip(kvm)->lock);
3020 break;
3021 case KVM_IRQCHIP_IOAPIC:
3022 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3023 break;
3024 default:
3025 r = -EINVAL;
3026 break;
3027 }
3028 kvm_pic_update_irq(pic_irqchip(kvm));
3029 return r;
3030 }
3031
3032 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3033 {
3034 int r = 0;
3035
3036 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3037 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3038 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3039 return r;
3040 }
3041
3042 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3043 {
3044 int r = 0;
3045
3046 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3047 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3048 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3049 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3050 return r;
3051 }
3052
3053 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3054 {
3055 int r = 0;
3056
3057 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3058 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3059 sizeof(ps->channels));
3060 ps->flags = kvm->arch.vpit->pit_state.flags;
3061 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3062 memset(&ps->reserved, 0, sizeof(ps->reserved));
3063 return r;
3064 }
3065
3066 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3067 {
3068 int r = 0, start = 0;
3069 u32 prev_legacy, cur_legacy;
3070 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3071 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3072 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073 if (!prev_legacy && cur_legacy)
3074 start = 1;
3075 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3076 sizeof(kvm->arch.vpit->pit_state.channels));
3077 kvm->arch.vpit->pit_state.flags = ps->flags;
3078 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3079 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3080 return r;
3081 }
3082
3083 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3084 struct kvm_reinject_control *control)
3085 {
3086 if (!kvm->arch.vpit)
3087 return -ENXIO;
3088 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3089 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3090 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3091 return 0;
3092 }
3093
3094 /**
3095 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3096 * @kvm: kvm instance
3097 * @log: slot id and address to which we copy the log
3098 *
3099 * We need to keep it in mind that VCPU threads can write to the bitmap
3100 * concurrently. So, to avoid losing data, we keep the following order for
3101 * each bit:
3102 *
3103 * 1. Take a snapshot of the bit and clear it if needed.
3104 * 2. Write protect the corresponding page.
3105 * 3. Flush TLB's if needed.
3106 * 4. Copy the snapshot to the userspace.
3107 *
3108 * Between 2 and 3, the guest may write to the page using the remaining TLB
3109 * entry. This is not a problem because the page will be reported dirty at
3110 * step 4 using the snapshot taken before and step 3 ensures that successive
3111 * writes will be logged for the next call.
3112 */
3113 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3114 {
3115 int r;
3116 struct kvm_memory_slot *memslot;
3117 unsigned long n, i;
3118 unsigned long *dirty_bitmap;
3119 unsigned long *dirty_bitmap_buffer;
3120 bool is_dirty = false;
3121
3122 mutex_lock(&kvm->slots_lock);
3123
3124 r = -EINVAL;
3125 if (log->slot >= KVM_MEMORY_SLOTS)
3126 goto out;
3127
3128 memslot = id_to_memslot(kvm->memslots, log->slot);
3129
3130 dirty_bitmap = memslot->dirty_bitmap;
3131 r = -ENOENT;
3132 if (!dirty_bitmap)
3133 goto out;
3134
3135 n = kvm_dirty_bitmap_bytes(memslot);
3136
3137 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3138 memset(dirty_bitmap_buffer, 0, n);
3139
3140 spin_lock(&kvm->mmu_lock);
3141
3142 for (i = 0; i < n / sizeof(long); i++) {
3143 unsigned long mask;
3144 gfn_t offset;
3145
3146 if (!dirty_bitmap[i])
3147 continue;
3148
3149 is_dirty = true;
3150
3151 mask = xchg(&dirty_bitmap[i], 0);
3152 dirty_bitmap_buffer[i] = mask;
3153
3154 offset = i * BITS_PER_LONG;
3155 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3156 }
3157 if (is_dirty)
3158 kvm_flush_remote_tlbs(kvm);
3159
3160 spin_unlock(&kvm->mmu_lock);
3161
3162 r = -EFAULT;
3163 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3164 goto out;
3165
3166 r = 0;
3167 out:
3168 mutex_unlock(&kvm->slots_lock);
3169 return r;
3170 }
3171
3172 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3173 {
3174 if (!irqchip_in_kernel(kvm))
3175 return -ENXIO;
3176
3177 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3178 irq_event->irq, irq_event->level);
3179 return 0;
3180 }
3181
3182 long kvm_arch_vm_ioctl(struct file *filp,
3183 unsigned int ioctl, unsigned long arg)
3184 {
3185 struct kvm *kvm = filp->private_data;
3186 void __user *argp = (void __user *)arg;
3187 int r = -ENOTTY;
3188 /*
3189 * This union makes it completely explicit to gcc-3.x
3190 * that these two variables' stack usage should be
3191 * combined, not added together.
3192 */
3193 union {
3194 struct kvm_pit_state ps;
3195 struct kvm_pit_state2 ps2;
3196 struct kvm_pit_config pit_config;
3197 } u;
3198
3199 switch (ioctl) {
3200 case KVM_SET_TSS_ADDR:
3201 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3202 if (r < 0)
3203 goto out;
3204 break;
3205 case KVM_SET_IDENTITY_MAP_ADDR: {
3206 u64 ident_addr;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3210 goto out;
3211 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3212 if (r < 0)
3213 goto out;
3214 break;
3215 }
3216 case KVM_SET_NR_MMU_PAGES:
3217 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3218 if (r)
3219 goto out;
3220 break;
3221 case KVM_GET_NR_MMU_PAGES:
3222 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3223 break;
3224 case KVM_CREATE_IRQCHIP: {
3225 struct kvm_pic *vpic;
3226
3227 mutex_lock(&kvm->lock);
3228 r = -EEXIST;
3229 if (kvm->arch.vpic)
3230 goto create_irqchip_unlock;
3231 r = -EINVAL;
3232 if (atomic_read(&kvm->online_vcpus))
3233 goto create_irqchip_unlock;
3234 r = -ENOMEM;
3235 vpic = kvm_create_pic(kvm);
3236 if (vpic) {
3237 r = kvm_ioapic_init(kvm);
3238 if (r) {
3239 mutex_lock(&kvm->slots_lock);
3240 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3241 &vpic->dev_master);
3242 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3243 &vpic->dev_slave);
3244 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3245 &vpic->dev_eclr);
3246 mutex_unlock(&kvm->slots_lock);
3247 kfree(vpic);
3248 goto create_irqchip_unlock;
3249 }
3250 } else
3251 goto create_irqchip_unlock;
3252 smp_wmb();
3253 kvm->arch.vpic = vpic;
3254 smp_wmb();
3255 r = kvm_setup_default_irq_routing(kvm);
3256 if (r) {
3257 mutex_lock(&kvm->slots_lock);
3258 mutex_lock(&kvm->irq_lock);
3259 kvm_ioapic_destroy(kvm);
3260 kvm_destroy_pic(kvm);
3261 mutex_unlock(&kvm->irq_lock);
3262 mutex_unlock(&kvm->slots_lock);
3263 }
3264 create_irqchip_unlock:
3265 mutex_unlock(&kvm->lock);
3266 break;
3267 }
3268 case KVM_CREATE_PIT:
3269 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3270 goto create_pit;
3271 case KVM_CREATE_PIT2:
3272 r = -EFAULT;
3273 if (copy_from_user(&u.pit_config, argp,
3274 sizeof(struct kvm_pit_config)))
3275 goto out;
3276 create_pit:
3277 mutex_lock(&kvm->slots_lock);
3278 r = -EEXIST;
3279 if (kvm->arch.vpit)
3280 goto create_pit_unlock;
3281 r = -ENOMEM;
3282 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3283 if (kvm->arch.vpit)
3284 r = 0;
3285 create_pit_unlock:
3286 mutex_unlock(&kvm->slots_lock);
3287 break;
3288 case KVM_GET_IRQCHIP: {
3289 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3290 struct kvm_irqchip *chip;
3291
3292 chip = memdup_user(argp, sizeof(*chip));
3293 if (IS_ERR(chip)) {
3294 r = PTR_ERR(chip);
3295 goto out;
3296 }
3297
3298 r = -ENXIO;
3299 if (!irqchip_in_kernel(kvm))
3300 goto get_irqchip_out;
3301 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3302 if (r)
3303 goto get_irqchip_out;
3304 r = -EFAULT;
3305 if (copy_to_user(argp, chip, sizeof *chip))
3306 goto get_irqchip_out;
3307 r = 0;
3308 get_irqchip_out:
3309 kfree(chip);
3310 if (r)
3311 goto out;
3312 break;
3313 }
3314 case KVM_SET_IRQCHIP: {
3315 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3316 struct kvm_irqchip *chip;
3317
3318 chip = memdup_user(argp, sizeof(*chip));
3319 if (IS_ERR(chip)) {
3320 r = PTR_ERR(chip);
3321 goto out;
3322 }
3323
3324 r = -ENXIO;
3325 if (!irqchip_in_kernel(kvm))
3326 goto set_irqchip_out;
3327 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3328 if (r)
3329 goto set_irqchip_out;
3330 r = 0;
3331 set_irqchip_out:
3332 kfree(chip);
3333 if (r)
3334 goto out;
3335 break;
3336 }
3337 case KVM_GET_PIT: {
3338 r = -EFAULT;
3339 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3340 goto out;
3341 r = -ENXIO;
3342 if (!kvm->arch.vpit)
3343 goto out;
3344 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3345 if (r)
3346 goto out;
3347 r = -EFAULT;
3348 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3349 goto out;
3350 r = 0;
3351 break;
3352 }
3353 case KVM_SET_PIT: {
3354 r = -EFAULT;
3355 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3356 goto out;
3357 r = -ENXIO;
3358 if (!kvm->arch.vpit)
3359 goto out;
3360 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3361 if (r)
3362 goto out;
3363 r = 0;
3364 break;
3365 }
3366 case KVM_GET_PIT2: {
3367 r = -ENXIO;
3368 if (!kvm->arch.vpit)
3369 goto out;
3370 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3371 if (r)
3372 goto out;
3373 r = -EFAULT;
3374 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3375 goto out;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_PIT2: {
3380 r = -EFAULT;
3381 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3382 goto out;
3383 r = -ENXIO;
3384 if (!kvm->arch.vpit)
3385 goto out;
3386 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3387 if (r)
3388 goto out;
3389 r = 0;
3390 break;
3391 }
3392 case KVM_REINJECT_CONTROL: {
3393 struct kvm_reinject_control control;
3394 r = -EFAULT;
3395 if (copy_from_user(&control, argp, sizeof(control)))
3396 goto out;
3397 r = kvm_vm_ioctl_reinject(kvm, &control);
3398 if (r)
3399 goto out;
3400 r = 0;
3401 break;
3402 }
3403 case KVM_XEN_HVM_CONFIG: {
3404 r = -EFAULT;
3405 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3406 sizeof(struct kvm_xen_hvm_config)))
3407 goto out;
3408 r = -EINVAL;
3409 if (kvm->arch.xen_hvm_config.flags)
3410 goto out;
3411 r = 0;
3412 break;
3413 }
3414 case KVM_SET_CLOCK: {
3415 struct kvm_clock_data user_ns;
3416 u64 now_ns;
3417 s64 delta;
3418
3419 r = -EFAULT;
3420 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3421 goto out;
3422
3423 r = -EINVAL;
3424 if (user_ns.flags)
3425 goto out;
3426
3427 r = 0;
3428 local_irq_disable();
3429 now_ns = get_kernel_ns();
3430 delta = user_ns.clock - now_ns;
3431 local_irq_enable();
3432 kvm->arch.kvmclock_offset = delta;
3433 break;
3434 }
3435 case KVM_GET_CLOCK: {
3436 struct kvm_clock_data user_ns;
3437 u64 now_ns;
3438
3439 local_irq_disable();
3440 now_ns = get_kernel_ns();
3441 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3442 local_irq_enable();
3443 user_ns.flags = 0;
3444 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3445
3446 r = -EFAULT;
3447 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3448 goto out;
3449 r = 0;
3450 break;
3451 }
3452
3453 default:
3454 ;
3455 }
3456 out:
3457 return r;
3458 }
3459
3460 static void kvm_init_msr_list(void)
3461 {
3462 u32 dummy[2];
3463 unsigned i, j;
3464
3465 /* skip the first msrs in the list. KVM-specific */
3466 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3467 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3468 continue;
3469 if (j < i)
3470 msrs_to_save[j] = msrs_to_save[i];
3471 j++;
3472 }
3473 num_msrs_to_save = j;
3474 }
3475
3476 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3477 const void *v)
3478 {
3479 int handled = 0;
3480 int n;
3481
3482 do {
3483 n = min(len, 8);
3484 if (!(vcpu->arch.apic &&
3485 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3486 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3487 break;
3488 handled += n;
3489 addr += n;
3490 len -= n;
3491 v += n;
3492 } while (len);
3493
3494 return handled;
3495 }
3496
3497 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3498 {
3499 int handled = 0;
3500 int n;
3501
3502 do {
3503 n = min(len, 8);
3504 if (!(vcpu->arch.apic &&
3505 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3506 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3507 break;
3508 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3509 handled += n;
3510 addr += n;
3511 len -= n;
3512 v += n;
3513 } while (len);
3514
3515 return handled;
3516 }
3517
3518 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3519 struct kvm_segment *var, int seg)
3520 {
3521 kvm_x86_ops->set_segment(vcpu, var, seg);
3522 }
3523
3524 void kvm_get_segment(struct kvm_vcpu *vcpu,
3525 struct kvm_segment *var, int seg)
3526 {
3527 kvm_x86_ops->get_segment(vcpu, var, seg);
3528 }
3529
3530 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3531 {
3532 gpa_t t_gpa;
3533 struct x86_exception exception;
3534
3535 BUG_ON(!mmu_is_nested(vcpu));
3536
3537 /* NPT walks are always user-walks */
3538 access |= PFERR_USER_MASK;
3539 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3540
3541 return t_gpa;
3542 }
3543
3544 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3545 struct x86_exception *exception)
3546 {
3547 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3549 }
3550
3551 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3552 struct x86_exception *exception)
3553 {
3554 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3555 access |= PFERR_FETCH_MASK;
3556 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3557 }
3558
3559 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3560 struct x86_exception *exception)
3561 {
3562 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3563 access |= PFERR_WRITE_MASK;
3564 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3565 }
3566
3567 /* uses this to access any guest's mapped memory without checking CPL */
3568 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3569 struct x86_exception *exception)
3570 {
3571 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3572 }
3573
3574 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3575 struct kvm_vcpu *vcpu, u32 access,
3576 struct x86_exception *exception)
3577 {
3578 void *data = val;
3579 int r = X86EMUL_CONTINUE;
3580
3581 while (bytes) {
3582 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3583 exception);
3584 unsigned offset = addr & (PAGE_SIZE-1);
3585 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3586 int ret;
3587
3588 if (gpa == UNMAPPED_GVA)
3589 return X86EMUL_PROPAGATE_FAULT;
3590 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3591 if (ret < 0) {
3592 r = X86EMUL_IO_NEEDED;
3593 goto out;
3594 }
3595
3596 bytes -= toread;
3597 data += toread;
3598 addr += toread;
3599 }
3600 out:
3601 return r;
3602 }
3603
3604 /* used for instruction fetching */
3605 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3606 gva_t addr, void *val, unsigned int bytes,
3607 struct x86_exception *exception)
3608 {
3609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3610 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3611
3612 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3613 access | PFERR_FETCH_MASK,
3614 exception);
3615 }
3616
3617 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3618 gva_t addr, void *val, unsigned int bytes,
3619 struct x86_exception *exception)
3620 {
3621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3622 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3623
3624 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3625 exception);
3626 }
3627 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3628
3629 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3630 gva_t addr, void *val, unsigned int bytes,
3631 struct x86_exception *exception)
3632 {
3633 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3634 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3635 }
3636
3637 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3638 gva_t addr, void *val,
3639 unsigned int bytes,
3640 struct x86_exception *exception)
3641 {
3642 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3643 void *data = val;
3644 int r = X86EMUL_CONTINUE;
3645
3646 while (bytes) {
3647 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3648 PFERR_WRITE_MASK,
3649 exception);
3650 unsigned offset = addr & (PAGE_SIZE-1);
3651 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3652 int ret;
3653
3654 if (gpa == UNMAPPED_GVA)
3655 return X86EMUL_PROPAGATE_FAULT;
3656 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3657 if (ret < 0) {
3658 r = X86EMUL_IO_NEEDED;
3659 goto out;
3660 }
3661
3662 bytes -= towrite;
3663 data += towrite;
3664 addr += towrite;
3665 }
3666 out:
3667 return r;
3668 }
3669 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3670
3671 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3672 gpa_t *gpa, struct x86_exception *exception,
3673 bool write)
3674 {
3675 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3676
3677 if (vcpu_match_mmio_gva(vcpu, gva) &&
3678 check_write_user_access(vcpu, write, access,
3679 vcpu->arch.access)) {
3680 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3681 (gva & (PAGE_SIZE - 1));
3682 trace_vcpu_match_mmio(gva, *gpa, write, false);
3683 return 1;
3684 }
3685
3686 if (write)
3687 access |= PFERR_WRITE_MASK;
3688
3689 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3690
3691 if (*gpa == UNMAPPED_GVA)
3692 return -1;
3693
3694 /* For APIC access vmexit */
3695 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3696 return 1;
3697
3698 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3699 trace_vcpu_match_mmio(gva, *gpa, write, true);
3700 return 1;
3701 }
3702
3703 return 0;
3704 }
3705
3706 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3707 const void *val, int bytes)
3708 {
3709 int ret;
3710
3711 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3712 if (ret < 0)
3713 return 0;
3714 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3715 return 1;
3716 }
3717
3718 struct read_write_emulator_ops {
3719 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3720 int bytes);
3721 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes);
3723 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3724 int bytes, void *val);
3725 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3726 void *val, int bytes);
3727 bool write;
3728 };
3729
3730 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3731 {
3732 if (vcpu->mmio_read_completed) {
3733 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3734 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3735 vcpu->mmio_read_completed = 0;
3736 return 1;
3737 }
3738
3739 return 0;
3740 }
3741
3742 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3743 void *val, int bytes)
3744 {
3745 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3746 }
3747
3748 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3749 void *val, int bytes)
3750 {
3751 return emulator_write_phys(vcpu, gpa, val, bytes);
3752 }
3753
3754 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3755 {
3756 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3757 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3758 }
3759
3760 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761 void *val, int bytes)
3762 {
3763 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3764 return X86EMUL_IO_NEEDED;
3765 }
3766
3767 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3768 void *val, int bytes)
3769 {
3770 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3771
3772 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3773 return X86EMUL_CONTINUE;
3774 }
3775
3776 static struct read_write_emulator_ops read_emultor = {
3777 .read_write_prepare = read_prepare,
3778 .read_write_emulate = read_emulate,
3779 .read_write_mmio = vcpu_mmio_read,
3780 .read_write_exit_mmio = read_exit_mmio,
3781 };
3782
3783 static struct read_write_emulator_ops write_emultor = {
3784 .read_write_emulate = write_emulate,
3785 .read_write_mmio = write_mmio,
3786 .read_write_exit_mmio = write_exit_mmio,
3787 .write = true,
3788 };
3789
3790 static int emulator_read_write_onepage(unsigned long addr, void *val,
3791 unsigned int bytes,
3792 struct x86_exception *exception,
3793 struct kvm_vcpu *vcpu,
3794 struct read_write_emulator_ops *ops)
3795 {
3796 gpa_t gpa;
3797 int handled, ret;
3798 bool write = ops->write;
3799 struct kvm_mmio_fragment *frag;
3800
3801 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3802
3803 if (ret < 0)
3804 return X86EMUL_PROPAGATE_FAULT;
3805
3806 /* For APIC access vmexit */
3807 if (ret)
3808 goto mmio;
3809
3810 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3811 return X86EMUL_CONTINUE;
3812
3813 mmio:
3814 /*
3815 * Is this MMIO handled locally?
3816 */
3817 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3818 if (handled == bytes)
3819 return X86EMUL_CONTINUE;
3820
3821 gpa += handled;
3822 bytes -= handled;
3823 val += handled;
3824
3825 while (bytes) {
3826 unsigned now = min(bytes, 8U);
3827
3828 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3829 frag->gpa = gpa;
3830 frag->data = val;
3831 frag->len = now;
3832
3833 gpa += now;
3834 val += now;
3835 bytes -= now;
3836 }
3837 return X86EMUL_CONTINUE;
3838 }
3839
3840 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3841 void *val, unsigned int bytes,
3842 struct x86_exception *exception,
3843 struct read_write_emulator_ops *ops)
3844 {
3845 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3846 gpa_t gpa;
3847 int rc;
3848
3849 if (ops->read_write_prepare &&
3850 ops->read_write_prepare(vcpu, val, bytes))
3851 return X86EMUL_CONTINUE;
3852
3853 vcpu->mmio_nr_fragments = 0;
3854
3855 /* Crossing a page boundary? */
3856 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3857 int now;
3858
3859 now = -addr & ~PAGE_MASK;
3860 rc = emulator_read_write_onepage(addr, val, now, exception,
3861 vcpu, ops);
3862
3863 if (rc != X86EMUL_CONTINUE)
3864 return rc;
3865 addr += now;
3866 val += now;
3867 bytes -= now;
3868 }
3869
3870 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3871 vcpu, ops);
3872 if (rc != X86EMUL_CONTINUE)
3873 return rc;
3874
3875 if (!vcpu->mmio_nr_fragments)
3876 return rc;
3877
3878 gpa = vcpu->mmio_fragments[0].gpa;
3879
3880 vcpu->mmio_needed = 1;
3881 vcpu->mmio_cur_fragment = 0;
3882
3883 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3884 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3885 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3886 vcpu->run->mmio.phys_addr = gpa;
3887
3888 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3889 }
3890
3891 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3892 unsigned long addr,
3893 void *val,
3894 unsigned int bytes,
3895 struct x86_exception *exception)
3896 {
3897 return emulator_read_write(ctxt, addr, val, bytes,
3898 exception, &read_emultor);
3899 }
3900
3901 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3902 unsigned long addr,
3903 const void *val,
3904 unsigned int bytes,
3905 struct x86_exception *exception)
3906 {
3907 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3908 exception, &write_emultor);
3909 }
3910
3911 #define CMPXCHG_TYPE(t, ptr, old, new) \
3912 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3913
3914 #ifdef CONFIG_X86_64
3915 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3916 #else
3917 # define CMPXCHG64(ptr, old, new) \
3918 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3919 #endif
3920
3921 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3922 unsigned long addr,
3923 const void *old,
3924 const void *new,
3925 unsigned int bytes,
3926 struct x86_exception *exception)
3927 {
3928 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3929 gpa_t gpa;
3930 struct page *page;
3931 char *kaddr;
3932 bool exchanged;
3933
3934 /* guests cmpxchg8b have to be emulated atomically */
3935 if (bytes > 8 || (bytes & (bytes - 1)))
3936 goto emul_write;
3937
3938 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3939
3940 if (gpa == UNMAPPED_GVA ||
3941 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3942 goto emul_write;
3943
3944 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3945 goto emul_write;
3946
3947 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3948 if (is_error_page(page))
3949 goto emul_write;
3950
3951 kaddr = kmap_atomic(page);
3952 kaddr += offset_in_page(gpa);
3953 switch (bytes) {
3954 case 1:
3955 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3956 break;
3957 case 2:
3958 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3959 break;
3960 case 4:
3961 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3962 break;
3963 case 8:
3964 exchanged = CMPXCHG64(kaddr, old, new);
3965 break;
3966 default:
3967 BUG();
3968 }
3969 kunmap_atomic(kaddr);
3970 kvm_release_page_dirty(page);
3971
3972 if (!exchanged)
3973 return X86EMUL_CMPXCHG_FAILED;
3974
3975 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3976
3977 return X86EMUL_CONTINUE;
3978
3979 emul_write:
3980 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3981
3982 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3983 }
3984
3985 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3986 {
3987 /* TODO: String I/O for in kernel device */
3988 int r;
3989
3990 if (vcpu->arch.pio.in)
3991 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3992 vcpu->arch.pio.size, pd);
3993 else
3994 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3995 vcpu->arch.pio.port, vcpu->arch.pio.size,
3996 pd);
3997 return r;
3998 }
3999
4000 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4001 unsigned short port, void *val,
4002 unsigned int count, bool in)
4003 {
4004 trace_kvm_pio(!in, port, size, count);
4005
4006 vcpu->arch.pio.port = port;
4007 vcpu->arch.pio.in = in;
4008 vcpu->arch.pio.count = count;
4009 vcpu->arch.pio.size = size;
4010
4011 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4012 vcpu->arch.pio.count = 0;
4013 return 1;
4014 }
4015
4016 vcpu->run->exit_reason = KVM_EXIT_IO;
4017 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4018 vcpu->run->io.size = size;
4019 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4020 vcpu->run->io.count = count;
4021 vcpu->run->io.port = port;
4022
4023 return 0;
4024 }
4025
4026 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4027 int size, unsigned short port, void *val,
4028 unsigned int count)
4029 {
4030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4031 int ret;
4032
4033 if (vcpu->arch.pio.count)
4034 goto data_avail;
4035
4036 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4037 if (ret) {
4038 data_avail:
4039 memcpy(val, vcpu->arch.pio_data, size * count);
4040 vcpu->arch.pio.count = 0;
4041 return 1;
4042 }
4043
4044 return 0;
4045 }
4046
4047 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4048 int size, unsigned short port,
4049 const void *val, unsigned int count)
4050 {
4051 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4052
4053 memcpy(vcpu->arch.pio_data, val, size * count);
4054 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4055 }
4056
4057 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4058 {
4059 return kvm_x86_ops->get_segment_base(vcpu, seg);
4060 }
4061
4062 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4063 {
4064 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4065 }
4066
4067 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4068 {
4069 if (!need_emulate_wbinvd(vcpu))
4070 return X86EMUL_CONTINUE;
4071
4072 if (kvm_x86_ops->has_wbinvd_exit()) {
4073 int cpu = get_cpu();
4074
4075 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4076 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4077 wbinvd_ipi, NULL, 1);
4078 put_cpu();
4079 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4080 } else
4081 wbinvd();
4082 return X86EMUL_CONTINUE;
4083 }
4084 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4085
4086 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4087 {
4088 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4089 }
4090
4091 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4092 {
4093 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4094 }
4095
4096 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4097 {
4098
4099 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4100 }
4101
4102 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4103 {
4104 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4105 }
4106
4107 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4108 {
4109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4110 unsigned long value;
4111
4112 switch (cr) {
4113 case 0:
4114 value = kvm_read_cr0(vcpu);
4115 break;
4116 case 2:
4117 value = vcpu->arch.cr2;
4118 break;
4119 case 3:
4120 value = kvm_read_cr3(vcpu);
4121 break;
4122 case 4:
4123 value = kvm_read_cr4(vcpu);
4124 break;
4125 case 8:
4126 value = kvm_get_cr8(vcpu);
4127 break;
4128 default:
4129 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4130 return 0;
4131 }
4132
4133 return value;
4134 }
4135
4136 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4137 {
4138 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4139 int res = 0;
4140
4141 switch (cr) {
4142 case 0:
4143 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4144 break;
4145 case 2:
4146 vcpu->arch.cr2 = val;
4147 break;
4148 case 3:
4149 res = kvm_set_cr3(vcpu, val);
4150 break;
4151 case 4:
4152 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4153 break;
4154 case 8:
4155 res = kvm_set_cr8(vcpu, val);
4156 break;
4157 default:
4158 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4159 res = -1;
4160 }
4161
4162 return res;
4163 }
4164
4165 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4166 {
4167 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4168 }
4169
4170 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4171 {
4172 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4173 }
4174
4175 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4176 {
4177 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4178 }
4179
4180 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4181 {
4182 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4183 }
4184
4185 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4186 {
4187 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4188 }
4189
4190 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4191 {
4192 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4193 }
4194
4195 static unsigned long emulator_get_cached_segment_base(
4196 struct x86_emulate_ctxt *ctxt, int seg)
4197 {
4198 return get_segment_base(emul_to_vcpu(ctxt), seg);
4199 }
4200
4201 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4202 struct desc_struct *desc, u32 *base3,
4203 int seg)
4204 {
4205 struct kvm_segment var;
4206
4207 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4208 *selector = var.selector;
4209
4210 if (var.unusable)
4211 return false;
4212
4213 if (var.g)
4214 var.limit >>= 12;
4215 set_desc_limit(desc, var.limit);
4216 set_desc_base(desc, (unsigned long)var.base);
4217 #ifdef CONFIG_X86_64
4218 if (base3)
4219 *base3 = var.base >> 32;
4220 #endif
4221 desc->type = var.type;
4222 desc->s = var.s;
4223 desc->dpl = var.dpl;
4224 desc->p = var.present;
4225 desc->avl = var.avl;
4226 desc->l = var.l;
4227 desc->d = var.db;
4228 desc->g = var.g;
4229
4230 return true;
4231 }
4232
4233 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4234 struct desc_struct *desc, u32 base3,
4235 int seg)
4236 {
4237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4238 struct kvm_segment var;
4239
4240 var.selector = selector;
4241 var.base = get_desc_base(desc);
4242 #ifdef CONFIG_X86_64
4243 var.base |= ((u64)base3) << 32;
4244 #endif
4245 var.limit = get_desc_limit(desc);
4246 if (desc->g)
4247 var.limit = (var.limit << 12) | 0xfff;
4248 var.type = desc->type;
4249 var.present = desc->p;
4250 var.dpl = desc->dpl;
4251 var.db = desc->d;
4252 var.s = desc->s;
4253 var.l = desc->l;
4254 var.g = desc->g;
4255 var.avl = desc->avl;
4256 var.present = desc->p;
4257 var.unusable = !var.present;
4258 var.padding = 0;
4259
4260 kvm_set_segment(vcpu, &var, seg);
4261 return;
4262 }
4263
4264 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4265 u32 msr_index, u64 *pdata)
4266 {
4267 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4268 }
4269
4270 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4271 u32 msr_index, u64 data)
4272 {
4273 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4274 }
4275
4276 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4277 u32 pmc, u64 *pdata)
4278 {
4279 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4280 }
4281
4282 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4283 {
4284 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4285 }
4286
4287 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4288 {
4289 preempt_disable();
4290 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4291 /*
4292 * CR0.TS may reference the host fpu state, not the guest fpu state,
4293 * so it may be clear at this point.
4294 */
4295 clts();
4296 }
4297
4298 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4299 {
4300 preempt_enable();
4301 }
4302
4303 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4304 struct x86_instruction_info *info,
4305 enum x86_intercept_stage stage)
4306 {
4307 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4308 }
4309
4310 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4311 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4312 {
4313 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4314 }
4315
4316 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4317 {
4318 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4319 }
4320
4321 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4322 {
4323 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4324 }
4325
4326 static struct x86_emulate_ops emulate_ops = {
4327 .read_gpr = emulator_read_gpr,
4328 .write_gpr = emulator_write_gpr,
4329 .read_std = kvm_read_guest_virt_system,
4330 .write_std = kvm_write_guest_virt_system,
4331 .fetch = kvm_fetch_guest_virt,
4332 .read_emulated = emulator_read_emulated,
4333 .write_emulated = emulator_write_emulated,
4334 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4335 .invlpg = emulator_invlpg,
4336 .pio_in_emulated = emulator_pio_in_emulated,
4337 .pio_out_emulated = emulator_pio_out_emulated,
4338 .get_segment = emulator_get_segment,
4339 .set_segment = emulator_set_segment,
4340 .get_cached_segment_base = emulator_get_cached_segment_base,
4341 .get_gdt = emulator_get_gdt,
4342 .get_idt = emulator_get_idt,
4343 .set_gdt = emulator_set_gdt,
4344 .set_idt = emulator_set_idt,
4345 .get_cr = emulator_get_cr,
4346 .set_cr = emulator_set_cr,
4347 .set_rflags = emulator_set_rflags,
4348 .cpl = emulator_get_cpl,
4349 .get_dr = emulator_get_dr,
4350 .set_dr = emulator_set_dr,
4351 .set_msr = emulator_set_msr,
4352 .get_msr = emulator_get_msr,
4353 .read_pmc = emulator_read_pmc,
4354 .halt = emulator_halt,
4355 .wbinvd = emulator_wbinvd,
4356 .fix_hypercall = emulator_fix_hypercall,
4357 .get_fpu = emulator_get_fpu,
4358 .put_fpu = emulator_put_fpu,
4359 .intercept = emulator_intercept,
4360 .get_cpuid = emulator_get_cpuid,
4361 };
4362
4363 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4364 {
4365 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4366 /*
4367 * an sti; sti; sequence only disable interrupts for the first
4368 * instruction. So, if the last instruction, be it emulated or
4369 * not, left the system with the INT_STI flag enabled, it
4370 * means that the last instruction is an sti. We should not
4371 * leave the flag on in this case. The same goes for mov ss
4372 */
4373 if (!(int_shadow & mask))
4374 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4375 }
4376
4377 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4378 {
4379 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4380 if (ctxt->exception.vector == PF_VECTOR)
4381 kvm_propagate_fault(vcpu, &ctxt->exception);
4382 else if (ctxt->exception.error_code_valid)
4383 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4384 ctxt->exception.error_code);
4385 else
4386 kvm_queue_exception(vcpu, ctxt->exception.vector);
4387 }
4388
4389 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4390 {
4391 memset(&ctxt->twobyte, 0,
4392 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4393
4394 ctxt->fetch.start = 0;
4395 ctxt->fetch.end = 0;
4396 ctxt->io_read.pos = 0;
4397 ctxt->io_read.end = 0;
4398 ctxt->mem_read.pos = 0;
4399 ctxt->mem_read.end = 0;
4400 }
4401
4402 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4403 {
4404 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4405 int cs_db, cs_l;
4406
4407 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4408
4409 ctxt->eflags = kvm_get_rflags(vcpu);
4410 ctxt->eip = kvm_rip_read(vcpu);
4411 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4412 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4413 cs_l ? X86EMUL_MODE_PROT64 :
4414 cs_db ? X86EMUL_MODE_PROT32 :
4415 X86EMUL_MODE_PROT16;
4416 ctxt->guest_mode = is_guest_mode(vcpu);
4417
4418 init_decode_cache(ctxt);
4419 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4420 }
4421
4422 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4423 {
4424 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4425 int ret;
4426
4427 init_emulate_ctxt(vcpu);
4428
4429 ctxt->op_bytes = 2;
4430 ctxt->ad_bytes = 2;
4431 ctxt->_eip = ctxt->eip + inc_eip;
4432 ret = emulate_int_real(ctxt, irq);
4433
4434 if (ret != X86EMUL_CONTINUE)
4435 return EMULATE_FAIL;
4436
4437 ctxt->eip = ctxt->_eip;
4438 kvm_rip_write(vcpu, ctxt->eip);
4439 kvm_set_rflags(vcpu, ctxt->eflags);
4440
4441 if (irq == NMI_VECTOR)
4442 vcpu->arch.nmi_pending = 0;
4443 else
4444 vcpu->arch.interrupt.pending = false;
4445
4446 return EMULATE_DONE;
4447 }
4448 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4449
4450 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4451 {
4452 int r = EMULATE_DONE;
4453
4454 ++vcpu->stat.insn_emulation_fail;
4455 trace_kvm_emulate_insn_failed(vcpu);
4456 if (!is_guest_mode(vcpu)) {
4457 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4458 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4459 vcpu->run->internal.ndata = 0;
4460 r = EMULATE_FAIL;
4461 }
4462 kvm_queue_exception(vcpu, UD_VECTOR);
4463
4464 return r;
4465 }
4466
4467 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4468 {
4469 gpa_t gpa;
4470 pfn_t pfn;
4471
4472 if (tdp_enabled)
4473 return false;
4474
4475 /*
4476 * if emulation was due to access to shadowed page table
4477 * and it failed try to unshadow page and re-enter the
4478 * guest to let CPU execute the instruction.
4479 */
4480 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4481 return true;
4482
4483 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4484
4485 if (gpa == UNMAPPED_GVA)
4486 return true; /* let cpu generate fault */
4487
4488 /*
4489 * Do not retry the unhandleable instruction if it faults on the
4490 * readonly host memory, otherwise it will goto a infinite loop:
4491 * retry instruction -> write #PF -> emulation fail -> retry
4492 * instruction -> ...
4493 */
4494 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4495 if (!is_error_pfn(pfn)) {
4496 kvm_release_pfn_clean(pfn);
4497 return true;
4498 }
4499
4500 return false;
4501 }
4502
4503 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4504 unsigned long cr2, int emulation_type)
4505 {
4506 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4507 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4508
4509 last_retry_eip = vcpu->arch.last_retry_eip;
4510 last_retry_addr = vcpu->arch.last_retry_addr;
4511
4512 /*
4513 * If the emulation is caused by #PF and it is non-page_table
4514 * writing instruction, it means the VM-EXIT is caused by shadow
4515 * page protected, we can zap the shadow page and retry this
4516 * instruction directly.
4517 *
4518 * Note: if the guest uses a non-page-table modifying instruction
4519 * on the PDE that points to the instruction, then we will unmap
4520 * the instruction and go to an infinite loop. So, we cache the
4521 * last retried eip and the last fault address, if we meet the eip
4522 * and the address again, we can break out of the potential infinite
4523 * loop.
4524 */
4525 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4526
4527 if (!(emulation_type & EMULTYPE_RETRY))
4528 return false;
4529
4530 if (x86_page_table_writing_insn(ctxt))
4531 return false;
4532
4533 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4534 return false;
4535
4536 vcpu->arch.last_retry_eip = ctxt->eip;
4537 vcpu->arch.last_retry_addr = cr2;
4538
4539 if (!vcpu->arch.mmu.direct_map)
4540 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4541
4542 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4543
4544 return true;
4545 }
4546
4547 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4548 unsigned long cr2,
4549 int emulation_type,
4550 void *insn,
4551 int insn_len)
4552 {
4553 int r;
4554 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4555 bool writeback = true;
4556
4557 kvm_clear_exception_queue(vcpu);
4558
4559 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4560 init_emulate_ctxt(vcpu);
4561 ctxt->interruptibility = 0;
4562 ctxt->have_exception = false;
4563 ctxt->perm_ok = false;
4564
4565 ctxt->only_vendor_specific_insn
4566 = emulation_type & EMULTYPE_TRAP_UD;
4567
4568 r = x86_decode_insn(ctxt, insn, insn_len);
4569
4570 trace_kvm_emulate_insn_start(vcpu);
4571 ++vcpu->stat.insn_emulation;
4572 if (r != EMULATION_OK) {
4573 if (emulation_type & EMULTYPE_TRAP_UD)
4574 return EMULATE_FAIL;
4575 if (reexecute_instruction(vcpu, cr2))
4576 return EMULATE_DONE;
4577 if (emulation_type & EMULTYPE_SKIP)
4578 return EMULATE_FAIL;
4579 return handle_emulation_failure(vcpu);
4580 }
4581 }
4582
4583 if (emulation_type & EMULTYPE_SKIP) {
4584 kvm_rip_write(vcpu, ctxt->_eip);
4585 return EMULATE_DONE;
4586 }
4587
4588 if (retry_instruction(ctxt, cr2, emulation_type))
4589 return EMULATE_DONE;
4590
4591 /* this is needed for vmware backdoor interface to work since it
4592 changes registers values during IO operation */
4593 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4594 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4595 emulator_invalidate_register_cache(ctxt);
4596 }
4597
4598 restart:
4599 r = x86_emulate_insn(ctxt);
4600
4601 if (r == EMULATION_INTERCEPTED)
4602 return EMULATE_DONE;
4603
4604 if (r == EMULATION_FAILED) {
4605 if (reexecute_instruction(vcpu, cr2))
4606 return EMULATE_DONE;
4607
4608 return handle_emulation_failure(vcpu);
4609 }
4610
4611 if (ctxt->have_exception) {
4612 inject_emulated_exception(vcpu);
4613 r = EMULATE_DONE;
4614 } else if (vcpu->arch.pio.count) {
4615 if (!vcpu->arch.pio.in)
4616 vcpu->arch.pio.count = 0;
4617 else
4618 writeback = false;
4619 r = EMULATE_DO_MMIO;
4620 } else if (vcpu->mmio_needed) {
4621 if (!vcpu->mmio_is_write)
4622 writeback = false;
4623 r = EMULATE_DO_MMIO;
4624 } else if (r == EMULATION_RESTART)
4625 goto restart;
4626 else
4627 r = EMULATE_DONE;
4628
4629 if (writeback) {
4630 toggle_interruptibility(vcpu, ctxt->interruptibility);
4631 kvm_set_rflags(vcpu, ctxt->eflags);
4632 kvm_make_request(KVM_REQ_EVENT, vcpu);
4633 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4634 kvm_rip_write(vcpu, ctxt->eip);
4635 } else
4636 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4637
4638 return r;
4639 }
4640 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4641
4642 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4643 {
4644 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4645 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4646 size, port, &val, 1);
4647 /* do not return to emulator after return from userspace */
4648 vcpu->arch.pio.count = 0;
4649 return ret;
4650 }
4651 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4652
4653 static void tsc_bad(void *info)
4654 {
4655 __this_cpu_write(cpu_tsc_khz, 0);
4656 }
4657
4658 static void tsc_khz_changed(void *data)
4659 {
4660 struct cpufreq_freqs *freq = data;
4661 unsigned long khz = 0;
4662
4663 if (data)
4664 khz = freq->new;
4665 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4666 khz = cpufreq_quick_get(raw_smp_processor_id());
4667 if (!khz)
4668 khz = tsc_khz;
4669 __this_cpu_write(cpu_tsc_khz, khz);
4670 }
4671
4672 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4673 void *data)
4674 {
4675 struct cpufreq_freqs *freq = data;
4676 struct kvm *kvm;
4677 struct kvm_vcpu *vcpu;
4678 int i, send_ipi = 0;
4679
4680 /*
4681 * We allow guests to temporarily run on slowing clocks,
4682 * provided we notify them after, or to run on accelerating
4683 * clocks, provided we notify them before. Thus time never
4684 * goes backwards.
4685 *
4686 * However, we have a problem. We can't atomically update
4687 * the frequency of a given CPU from this function; it is
4688 * merely a notifier, which can be called from any CPU.
4689 * Changing the TSC frequency at arbitrary points in time
4690 * requires a recomputation of local variables related to
4691 * the TSC for each VCPU. We must flag these local variables
4692 * to be updated and be sure the update takes place with the
4693 * new frequency before any guests proceed.
4694 *
4695 * Unfortunately, the combination of hotplug CPU and frequency
4696 * change creates an intractable locking scenario; the order
4697 * of when these callouts happen is undefined with respect to
4698 * CPU hotplug, and they can race with each other. As such,
4699 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4700 * undefined; you can actually have a CPU frequency change take
4701 * place in between the computation of X and the setting of the
4702 * variable. To protect against this problem, all updates of
4703 * the per_cpu tsc_khz variable are done in an interrupt
4704 * protected IPI, and all callers wishing to update the value
4705 * must wait for a synchronous IPI to complete (which is trivial
4706 * if the caller is on the CPU already). This establishes the
4707 * necessary total order on variable updates.
4708 *
4709 * Note that because a guest time update may take place
4710 * anytime after the setting of the VCPU's request bit, the
4711 * correct TSC value must be set before the request. However,
4712 * to ensure the update actually makes it to any guest which
4713 * starts running in hardware virtualization between the set
4714 * and the acquisition of the spinlock, we must also ping the
4715 * CPU after setting the request bit.
4716 *
4717 */
4718
4719 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4720 return 0;
4721 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4722 return 0;
4723
4724 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4725
4726 raw_spin_lock(&kvm_lock);
4727 list_for_each_entry(kvm, &vm_list, vm_list) {
4728 kvm_for_each_vcpu(i, vcpu, kvm) {
4729 if (vcpu->cpu != freq->cpu)
4730 continue;
4731 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4732 if (vcpu->cpu != smp_processor_id())
4733 send_ipi = 1;
4734 }
4735 }
4736 raw_spin_unlock(&kvm_lock);
4737
4738 if (freq->old < freq->new && send_ipi) {
4739 /*
4740 * We upscale the frequency. Must make the guest
4741 * doesn't see old kvmclock values while running with
4742 * the new frequency, otherwise we risk the guest sees
4743 * time go backwards.
4744 *
4745 * In case we update the frequency for another cpu
4746 * (which might be in guest context) send an interrupt
4747 * to kick the cpu out of guest context. Next time
4748 * guest context is entered kvmclock will be updated,
4749 * so the guest will not see stale values.
4750 */
4751 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4752 }
4753 return 0;
4754 }
4755
4756 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4757 .notifier_call = kvmclock_cpufreq_notifier
4758 };
4759
4760 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4761 unsigned long action, void *hcpu)
4762 {
4763 unsigned int cpu = (unsigned long)hcpu;
4764
4765 switch (action) {
4766 case CPU_ONLINE:
4767 case CPU_DOWN_FAILED:
4768 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4769 break;
4770 case CPU_DOWN_PREPARE:
4771 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4772 break;
4773 }
4774 return NOTIFY_OK;
4775 }
4776
4777 static struct notifier_block kvmclock_cpu_notifier_block = {
4778 .notifier_call = kvmclock_cpu_notifier,
4779 .priority = -INT_MAX
4780 };
4781
4782 static void kvm_timer_init(void)
4783 {
4784 int cpu;
4785
4786 max_tsc_khz = tsc_khz;
4787 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4788 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4789 #ifdef CONFIG_CPU_FREQ
4790 struct cpufreq_policy policy;
4791 memset(&policy, 0, sizeof(policy));
4792 cpu = get_cpu();
4793 cpufreq_get_policy(&policy, cpu);
4794 if (policy.cpuinfo.max_freq)
4795 max_tsc_khz = policy.cpuinfo.max_freq;
4796 put_cpu();
4797 #endif
4798 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4799 CPUFREQ_TRANSITION_NOTIFIER);
4800 }
4801 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4802 for_each_online_cpu(cpu)
4803 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4804 }
4805
4806 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4807
4808 int kvm_is_in_guest(void)
4809 {
4810 return __this_cpu_read(current_vcpu) != NULL;
4811 }
4812
4813 static int kvm_is_user_mode(void)
4814 {
4815 int user_mode = 3;
4816
4817 if (__this_cpu_read(current_vcpu))
4818 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4819
4820 return user_mode != 0;
4821 }
4822
4823 static unsigned long kvm_get_guest_ip(void)
4824 {
4825 unsigned long ip = 0;
4826
4827 if (__this_cpu_read(current_vcpu))
4828 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4829
4830 return ip;
4831 }
4832
4833 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4834 .is_in_guest = kvm_is_in_guest,
4835 .is_user_mode = kvm_is_user_mode,
4836 .get_guest_ip = kvm_get_guest_ip,
4837 };
4838
4839 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4840 {
4841 __this_cpu_write(current_vcpu, vcpu);
4842 }
4843 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4844
4845 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4846 {
4847 __this_cpu_write(current_vcpu, NULL);
4848 }
4849 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4850
4851 static void kvm_set_mmio_spte_mask(void)
4852 {
4853 u64 mask;
4854 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4855
4856 /*
4857 * Set the reserved bits and the present bit of an paging-structure
4858 * entry to generate page fault with PFER.RSV = 1.
4859 */
4860 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4861 mask |= 1ull;
4862
4863 #ifdef CONFIG_X86_64
4864 /*
4865 * If reserved bit is not supported, clear the present bit to disable
4866 * mmio page fault.
4867 */
4868 if (maxphyaddr == 52)
4869 mask &= ~1ull;
4870 #endif
4871
4872 kvm_mmu_set_mmio_spte_mask(mask);
4873 }
4874
4875 int kvm_arch_init(void *opaque)
4876 {
4877 int r;
4878 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4879
4880 if (kvm_x86_ops) {
4881 printk(KERN_ERR "kvm: already loaded the other module\n");
4882 r = -EEXIST;
4883 goto out;
4884 }
4885
4886 if (!ops->cpu_has_kvm_support()) {
4887 printk(KERN_ERR "kvm: no hardware support\n");
4888 r = -EOPNOTSUPP;
4889 goto out;
4890 }
4891 if (ops->disabled_by_bios()) {
4892 printk(KERN_ERR "kvm: disabled by bios\n");
4893 r = -EOPNOTSUPP;
4894 goto out;
4895 }
4896
4897 r = kvm_mmu_module_init();
4898 if (r)
4899 goto out;
4900
4901 kvm_set_mmio_spte_mask();
4902 kvm_init_msr_list();
4903
4904 kvm_x86_ops = ops;
4905 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4906 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4907
4908 kvm_timer_init();
4909
4910 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4911
4912 if (cpu_has_xsave)
4913 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4914
4915 kvm_lapic_init();
4916 return 0;
4917
4918 out:
4919 return r;
4920 }
4921
4922 void kvm_arch_exit(void)
4923 {
4924 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4925
4926 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4927 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4928 CPUFREQ_TRANSITION_NOTIFIER);
4929 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4930 kvm_x86_ops = NULL;
4931 kvm_mmu_module_exit();
4932 }
4933
4934 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4935 {
4936 ++vcpu->stat.halt_exits;
4937 if (irqchip_in_kernel(vcpu->kvm)) {
4938 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4939 return 1;
4940 } else {
4941 vcpu->run->exit_reason = KVM_EXIT_HLT;
4942 return 0;
4943 }
4944 }
4945 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4946
4947 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4948 {
4949 u64 param, ingpa, outgpa, ret;
4950 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4951 bool fast, longmode;
4952 int cs_db, cs_l;
4953
4954 /*
4955 * hypercall generates UD from non zero cpl and real mode
4956 * per HYPER-V spec
4957 */
4958 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4959 kvm_queue_exception(vcpu, UD_VECTOR);
4960 return 0;
4961 }
4962
4963 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4964 longmode = is_long_mode(vcpu) && cs_l == 1;
4965
4966 if (!longmode) {
4967 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4968 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4969 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4970 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4971 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4972 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4973 }
4974 #ifdef CONFIG_X86_64
4975 else {
4976 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4977 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4978 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4979 }
4980 #endif
4981
4982 code = param & 0xffff;
4983 fast = (param >> 16) & 0x1;
4984 rep_cnt = (param >> 32) & 0xfff;
4985 rep_idx = (param >> 48) & 0xfff;
4986
4987 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4988
4989 switch (code) {
4990 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4991 kvm_vcpu_on_spin(vcpu);
4992 break;
4993 default:
4994 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4995 break;
4996 }
4997
4998 ret = res | (((u64)rep_done & 0xfff) << 32);
4999 if (longmode) {
5000 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5001 } else {
5002 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5003 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5004 }
5005
5006 return 1;
5007 }
5008
5009 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5010 {
5011 unsigned long nr, a0, a1, a2, a3, ret;
5012 int r = 1;
5013
5014 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5015 return kvm_hv_hypercall(vcpu);
5016
5017 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5018 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5019 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5020 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5021 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5022
5023 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5024
5025 if (!is_long_mode(vcpu)) {
5026 nr &= 0xFFFFFFFF;
5027 a0 &= 0xFFFFFFFF;
5028 a1 &= 0xFFFFFFFF;
5029 a2 &= 0xFFFFFFFF;
5030 a3 &= 0xFFFFFFFF;
5031 }
5032
5033 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5034 ret = -KVM_EPERM;
5035 goto out;
5036 }
5037
5038 switch (nr) {
5039 case KVM_HC_VAPIC_POLL_IRQ:
5040 ret = 0;
5041 break;
5042 default:
5043 ret = -KVM_ENOSYS;
5044 break;
5045 }
5046 out:
5047 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5048 ++vcpu->stat.hypercalls;
5049 return r;
5050 }
5051 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5052
5053 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5054 {
5055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5056 char instruction[3];
5057 unsigned long rip = kvm_rip_read(vcpu);
5058
5059 /*
5060 * Blow out the MMU to ensure that no other VCPU has an active mapping
5061 * to ensure that the updated hypercall appears atomically across all
5062 * VCPUs.
5063 */
5064 kvm_mmu_zap_all(vcpu->kvm);
5065
5066 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5067
5068 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5069 }
5070
5071 /*
5072 * Check if userspace requested an interrupt window, and that the
5073 * interrupt window is open.
5074 *
5075 * No need to exit to userspace if we already have an interrupt queued.
5076 */
5077 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5078 {
5079 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5080 vcpu->run->request_interrupt_window &&
5081 kvm_arch_interrupt_allowed(vcpu));
5082 }
5083
5084 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5085 {
5086 struct kvm_run *kvm_run = vcpu->run;
5087
5088 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5089 kvm_run->cr8 = kvm_get_cr8(vcpu);
5090 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5091 if (irqchip_in_kernel(vcpu->kvm))
5092 kvm_run->ready_for_interrupt_injection = 1;
5093 else
5094 kvm_run->ready_for_interrupt_injection =
5095 kvm_arch_interrupt_allowed(vcpu) &&
5096 !kvm_cpu_has_interrupt(vcpu) &&
5097 !kvm_event_needs_reinjection(vcpu);
5098 }
5099
5100 static void vapic_enter(struct kvm_vcpu *vcpu)
5101 {
5102 struct kvm_lapic *apic = vcpu->arch.apic;
5103 struct page *page;
5104
5105 if (!apic || !apic->vapic_addr)
5106 return;
5107
5108 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5109
5110 vcpu->arch.apic->vapic_page = page;
5111 }
5112
5113 static void vapic_exit(struct kvm_vcpu *vcpu)
5114 {
5115 struct kvm_lapic *apic = vcpu->arch.apic;
5116 int idx;
5117
5118 if (!apic || !apic->vapic_addr)
5119 return;
5120
5121 idx = srcu_read_lock(&vcpu->kvm->srcu);
5122 kvm_release_page_dirty(apic->vapic_page);
5123 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5124 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5125 }
5126
5127 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5128 {
5129 int max_irr, tpr;
5130
5131 if (!kvm_x86_ops->update_cr8_intercept)
5132 return;
5133
5134 if (!vcpu->arch.apic)
5135 return;
5136
5137 if (!vcpu->arch.apic->vapic_addr)
5138 max_irr = kvm_lapic_find_highest_irr(vcpu);
5139 else
5140 max_irr = -1;
5141
5142 if (max_irr != -1)
5143 max_irr >>= 4;
5144
5145 tpr = kvm_lapic_get_cr8(vcpu);
5146
5147 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5148 }
5149
5150 static void inject_pending_event(struct kvm_vcpu *vcpu)
5151 {
5152 /* try to reinject previous events if any */
5153 if (vcpu->arch.exception.pending) {
5154 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5155 vcpu->arch.exception.has_error_code,
5156 vcpu->arch.exception.error_code);
5157 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5158 vcpu->arch.exception.has_error_code,
5159 vcpu->arch.exception.error_code,
5160 vcpu->arch.exception.reinject);
5161 return;
5162 }
5163
5164 if (vcpu->arch.nmi_injected) {
5165 kvm_x86_ops->set_nmi(vcpu);
5166 return;
5167 }
5168
5169 if (vcpu->arch.interrupt.pending) {
5170 kvm_x86_ops->set_irq(vcpu);
5171 return;
5172 }
5173
5174 /* try to inject new event if pending */
5175 if (vcpu->arch.nmi_pending) {
5176 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5177 --vcpu->arch.nmi_pending;
5178 vcpu->arch.nmi_injected = true;
5179 kvm_x86_ops->set_nmi(vcpu);
5180 }
5181 } else if (kvm_cpu_has_interrupt(vcpu)) {
5182 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5183 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5184 false);
5185 kvm_x86_ops->set_irq(vcpu);
5186 }
5187 }
5188 }
5189
5190 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5191 {
5192 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5193 !vcpu->guest_xcr0_loaded) {
5194 /* kvm_set_xcr() also depends on this */
5195 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5196 vcpu->guest_xcr0_loaded = 1;
5197 }
5198 }
5199
5200 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5201 {
5202 if (vcpu->guest_xcr0_loaded) {
5203 if (vcpu->arch.xcr0 != host_xcr0)
5204 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5205 vcpu->guest_xcr0_loaded = 0;
5206 }
5207 }
5208
5209 static void process_nmi(struct kvm_vcpu *vcpu)
5210 {
5211 unsigned limit = 2;
5212
5213 /*
5214 * x86 is limited to one NMI running, and one NMI pending after it.
5215 * If an NMI is already in progress, limit further NMIs to just one.
5216 * Otherwise, allow two (and we'll inject the first one immediately).
5217 */
5218 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5219 limit = 1;
5220
5221 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5222 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5223 kvm_make_request(KVM_REQ_EVENT, vcpu);
5224 }
5225
5226 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5227 {
5228 int r;
5229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5230 vcpu->run->request_interrupt_window;
5231 bool req_immediate_exit = 0;
5232
5233 if (vcpu->requests) {
5234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5235 kvm_mmu_unload(vcpu);
5236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5237 __kvm_migrate_timers(vcpu);
5238 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5239 r = kvm_guest_time_update(vcpu);
5240 if (unlikely(r))
5241 goto out;
5242 }
5243 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5244 kvm_mmu_sync_roots(vcpu);
5245 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5246 kvm_x86_ops->tlb_flush(vcpu);
5247 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5248 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5249 r = 0;
5250 goto out;
5251 }
5252 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5253 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5254 r = 0;
5255 goto out;
5256 }
5257 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5258 vcpu->fpu_active = 0;
5259 kvm_x86_ops->fpu_deactivate(vcpu);
5260 }
5261 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5262 /* Page is swapped out. Do synthetic halt */
5263 vcpu->arch.apf.halted = true;
5264 r = 1;
5265 goto out;
5266 }
5267 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5268 record_steal_time(vcpu);
5269 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5270 process_nmi(vcpu);
5271 req_immediate_exit =
5272 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5273 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5274 kvm_handle_pmu_event(vcpu);
5275 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5276 kvm_deliver_pmi(vcpu);
5277 }
5278
5279 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5280 inject_pending_event(vcpu);
5281
5282 /* enable NMI/IRQ window open exits if needed */
5283 if (vcpu->arch.nmi_pending)
5284 kvm_x86_ops->enable_nmi_window(vcpu);
5285 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5286 kvm_x86_ops->enable_irq_window(vcpu);
5287
5288 if (kvm_lapic_enabled(vcpu)) {
5289 update_cr8_intercept(vcpu);
5290 kvm_lapic_sync_to_vapic(vcpu);
5291 }
5292 }
5293
5294 r = kvm_mmu_reload(vcpu);
5295 if (unlikely(r)) {
5296 goto cancel_injection;
5297 }
5298
5299 preempt_disable();
5300
5301 kvm_x86_ops->prepare_guest_switch(vcpu);
5302 if (vcpu->fpu_active)
5303 kvm_load_guest_fpu(vcpu);
5304 kvm_load_guest_xcr0(vcpu);
5305
5306 vcpu->mode = IN_GUEST_MODE;
5307
5308 /* We should set ->mode before check ->requests,
5309 * see the comment in make_all_cpus_request.
5310 */
5311 smp_mb();
5312
5313 local_irq_disable();
5314
5315 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5316 || need_resched() || signal_pending(current)) {
5317 vcpu->mode = OUTSIDE_GUEST_MODE;
5318 smp_wmb();
5319 local_irq_enable();
5320 preempt_enable();
5321 r = 1;
5322 goto cancel_injection;
5323 }
5324
5325 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5326
5327 if (req_immediate_exit)
5328 smp_send_reschedule(vcpu->cpu);
5329
5330 kvm_guest_enter();
5331
5332 if (unlikely(vcpu->arch.switch_db_regs)) {
5333 set_debugreg(0, 7);
5334 set_debugreg(vcpu->arch.eff_db[0], 0);
5335 set_debugreg(vcpu->arch.eff_db[1], 1);
5336 set_debugreg(vcpu->arch.eff_db[2], 2);
5337 set_debugreg(vcpu->arch.eff_db[3], 3);
5338 }
5339
5340 trace_kvm_entry(vcpu->vcpu_id);
5341 kvm_x86_ops->run(vcpu);
5342
5343 /*
5344 * If the guest has used debug registers, at least dr7
5345 * will be disabled while returning to the host.
5346 * If we don't have active breakpoints in the host, we don't
5347 * care about the messed up debug address registers. But if
5348 * we have some of them active, restore the old state.
5349 */
5350 if (hw_breakpoint_active())
5351 hw_breakpoint_restore();
5352
5353 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5354
5355 vcpu->mode = OUTSIDE_GUEST_MODE;
5356 smp_wmb();
5357 local_irq_enable();
5358
5359 ++vcpu->stat.exits;
5360
5361 /*
5362 * We must have an instruction between local_irq_enable() and
5363 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5364 * the interrupt shadow. The stat.exits increment will do nicely.
5365 * But we need to prevent reordering, hence this barrier():
5366 */
5367 barrier();
5368
5369 kvm_guest_exit();
5370
5371 preempt_enable();
5372
5373 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5374
5375 /*
5376 * Profile KVM exit RIPs:
5377 */
5378 if (unlikely(prof_on == KVM_PROFILING)) {
5379 unsigned long rip = kvm_rip_read(vcpu);
5380 profile_hit(KVM_PROFILING, (void *)rip);
5381 }
5382
5383 if (unlikely(vcpu->arch.tsc_always_catchup))
5384 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5385
5386 if (vcpu->arch.apic_attention)
5387 kvm_lapic_sync_from_vapic(vcpu);
5388
5389 r = kvm_x86_ops->handle_exit(vcpu);
5390 return r;
5391
5392 cancel_injection:
5393 kvm_x86_ops->cancel_injection(vcpu);
5394 if (unlikely(vcpu->arch.apic_attention))
5395 kvm_lapic_sync_from_vapic(vcpu);
5396 out:
5397 return r;
5398 }
5399
5400
5401 static int __vcpu_run(struct kvm_vcpu *vcpu)
5402 {
5403 int r;
5404 struct kvm *kvm = vcpu->kvm;
5405
5406 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5407 pr_debug("vcpu %d received sipi with vector # %x\n",
5408 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5409 kvm_lapic_reset(vcpu);
5410 r = kvm_arch_vcpu_reset(vcpu);
5411 if (r)
5412 return r;
5413 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5414 }
5415
5416 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5417 vapic_enter(vcpu);
5418
5419 r = 1;
5420 while (r > 0) {
5421 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5422 !vcpu->arch.apf.halted)
5423 r = vcpu_enter_guest(vcpu);
5424 else {
5425 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5426 kvm_vcpu_block(vcpu);
5427 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5428 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5429 {
5430 switch(vcpu->arch.mp_state) {
5431 case KVM_MP_STATE_HALTED:
5432 vcpu->arch.mp_state =
5433 KVM_MP_STATE_RUNNABLE;
5434 case KVM_MP_STATE_RUNNABLE:
5435 vcpu->arch.apf.halted = false;
5436 break;
5437 case KVM_MP_STATE_SIPI_RECEIVED:
5438 default:
5439 r = -EINTR;
5440 break;
5441 }
5442 }
5443 }
5444
5445 if (r <= 0)
5446 break;
5447
5448 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5449 if (kvm_cpu_has_pending_timer(vcpu))
5450 kvm_inject_pending_timer_irqs(vcpu);
5451
5452 if (dm_request_for_irq_injection(vcpu)) {
5453 r = -EINTR;
5454 vcpu->run->exit_reason = KVM_EXIT_INTR;
5455 ++vcpu->stat.request_irq_exits;
5456 }
5457
5458 kvm_check_async_pf_completion(vcpu);
5459
5460 if (signal_pending(current)) {
5461 r = -EINTR;
5462 vcpu->run->exit_reason = KVM_EXIT_INTR;
5463 ++vcpu->stat.signal_exits;
5464 }
5465 if (need_resched()) {
5466 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5467 kvm_resched(vcpu);
5468 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5469 }
5470 }
5471
5472 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5473
5474 vapic_exit(vcpu);
5475
5476 return r;
5477 }
5478
5479 /*
5480 * Implements the following, as a state machine:
5481 *
5482 * read:
5483 * for each fragment
5484 * write gpa, len
5485 * exit
5486 * copy data
5487 * execute insn
5488 *
5489 * write:
5490 * for each fragment
5491 * write gpa, len
5492 * copy data
5493 * exit
5494 */
5495 static int complete_mmio(struct kvm_vcpu *vcpu)
5496 {
5497 struct kvm_run *run = vcpu->run;
5498 struct kvm_mmio_fragment *frag;
5499 int r;
5500
5501 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5502 return 1;
5503
5504 if (vcpu->mmio_needed) {
5505 /* Complete previous fragment */
5506 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5507 if (!vcpu->mmio_is_write)
5508 memcpy(frag->data, run->mmio.data, frag->len);
5509 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5510 vcpu->mmio_needed = 0;
5511 if (vcpu->mmio_is_write)
5512 return 1;
5513 vcpu->mmio_read_completed = 1;
5514 goto done;
5515 }
5516 /* Initiate next fragment */
5517 ++frag;
5518 run->exit_reason = KVM_EXIT_MMIO;
5519 run->mmio.phys_addr = frag->gpa;
5520 if (vcpu->mmio_is_write)
5521 memcpy(run->mmio.data, frag->data, frag->len);
5522 run->mmio.len = frag->len;
5523 run->mmio.is_write = vcpu->mmio_is_write;
5524 return 0;
5525
5526 }
5527 done:
5528 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5529 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5530 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5531 if (r != EMULATE_DONE)
5532 return 0;
5533 return 1;
5534 }
5535
5536 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5537 {
5538 int r;
5539 sigset_t sigsaved;
5540
5541 if (!tsk_used_math(current) && init_fpu(current))
5542 return -ENOMEM;
5543
5544 if (vcpu->sigset_active)
5545 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5546
5547 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5548 kvm_vcpu_block(vcpu);
5549 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5550 r = -EAGAIN;
5551 goto out;
5552 }
5553
5554 /* re-sync apic's tpr */
5555 if (!irqchip_in_kernel(vcpu->kvm)) {
5556 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5557 r = -EINVAL;
5558 goto out;
5559 }
5560 }
5561
5562 r = complete_mmio(vcpu);
5563 if (r <= 0)
5564 goto out;
5565
5566 r = __vcpu_run(vcpu);
5567
5568 out:
5569 post_kvm_run_save(vcpu);
5570 if (vcpu->sigset_active)
5571 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5572
5573 return r;
5574 }
5575
5576 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5577 {
5578 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5579 /*
5580 * We are here if userspace calls get_regs() in the middle of
5581 * instruction emulation. Registers state needs to be copied
5582 * back from emulation context to vcpu. Userspace shouldn't do
5583 * that usually, but some bad designed PV devices (vmware
5584 * backdoor interface) need this to work
5585 */
5586 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
5587 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5588 }
5589 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5590 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5591 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5592 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5593 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5594 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5595 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5596 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5597 #ifdef CONFIG_X86_64
5598 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5599 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5600 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5601 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5602 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5603 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5604 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5605 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5606 #endif
5607
5608 regs->rip = kvm_rip_read(vcpu);
5609 regs->rflags = kvm_get_rflags(vcpu);
5610
5611 return 0;
5612 }
5613
5614 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5615 {
5616 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5617 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5618
5619 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5620 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5621 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5622 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5623 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5624 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5625 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5626 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5627 #ifdef CONFIG_X86_64
5628 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5629 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5630 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5631 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5632 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5633 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5634 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5635 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5636 #endif
5637
5638 kvm_rip_write(vcpu, regs->rip);
5639 kvm_set_rflags(vcpu, regs->rflags);
5640
5641 vcpu->arch.exception.pending = false;
5642
5643 kvm_make_request(KVM_REQ_EVENT, vcpu);
5644
5645 return 0;
5646 }
5647
5648 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5649 {
5650 struct kvm_segment cs;
5651
5652 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5653 *db = cs.db;
5654 *l = cs.l;
5655 }
5656 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5657
5658 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5659 struct kvm_sregs *sregs)
5660 {
5661 struct desc_ptr dt;
5662
5663 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5664 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5665 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5666 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5667 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5668 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5669
5670 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5671 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5672
5673 kvm_x86_ops->get_idt(vcpu, &dt);
5674 sregs->idt.limit = dt.size;
5675 sregs->idt.base = dt.address;
5676 kvm_x86_ops->get_gdt(vcpu, &dt);
5677 sregs->gdt.limit = dt.size;
5678 sregs->gdt.base = dt.address;
5679
5680 sregs->cr0 = kvm_read_cr0(vcpu);
5681 sregs->cr2 = vcpu->arch.cr2;
5682 sregs->cr3 = kvm_read_cr3(vcpu);
5683 sregs->cr4 = kvm_read_cr4(vcpu);
5684 sregs->cr8 = kvm_get_cr8(vcpu);
5685 sregs->efer = vcpu->arch.efer;
5686 sregs->apic_base = kvm_get_apic_base(vcpu);
5687
5688 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5689
5690 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5691 set_bit(vcpu->arch.interrupt.nr,
5692 (unsigned long *)sregs->interrupt_bitmap);
5693
5694 return 0;
5695 }
5696
5697 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5698 struct kvm_mp_state *mp_state)
5699 {
5700 mp_state->mp_state = vcpu->arch.mp_state;
5701 return 0;
5702 }
5703
5704 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5705 struct kvm_mp_state *mp_state)
5706 {
5707 vcpu->arch.mp_state = mp_state->mp_state;
5708 kvm_make_request(KVM_REQ_EVENT, vcpu);
5709 return 0;
5710 }
5711
5712 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5713 int reason, bool has_error_code, u32 error_code)
5714 {
5715 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5716 int ret;
5717 unsigned reg;
5718
5719 init_emulate_ctxt(vcpu);
5720
5721 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5722 has_error_code, error_code);
5723
5724 if (ret)
5725 return EMULATE_FAIL;
5726
5727 kvm_rip_write(vcpu, ctxt->eip);
5728 kvm_set_rflags(vcpu, ctxt->eflags);
5729 kvm_make_request(KVM_REQ_EVENT, vcpu);
5730 return EMULATE_DONE;
5731 }
5732 EXPORT_SYMBOL_GPL(kvm_task_switch);
5733
5734 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5735 struct kvm_sregs *sregs)
5736 {
5737 int mmu_reset_needed = 0;
5738 int pending_vec, max_bits, idx;
5739 struct desc_ptr dt;
5740
5741 dt.size = sregs->idt.limit;
5742 dt.address = sregs->idt.base;
5743 kvm_x86_ops->set_idt(vcpu, &dt);
5744 dt.size = sregs->gdt.limit;
5745 dt.address = sregs->gdt.base;
5746 kvm_x86_ops->set_gdt(vcpu, &dt);
5747
5748 vcpu->arch.cr2 = sregs->cr2;
5749 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5750 vcpu->arch.cr3 = sregs->cr3;
5751 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5752
5753 kvm_set_cr8(vcpu, sregs->cr8);
5754
5755 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5756 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5757 kvm_set_apic_base(vcpu, sregs->apic_base);
5758
5759 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5760 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5761 vcpu->arch.cr0 = sregs->cr0;
5762
5763 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5764 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5765 if (sregs->cr4 & X86_CR4_OSXSAVE)
5766 kvm_update_cpuid(vcpu);
5767
5768 idx = srcu_read_lock(&vcpu->kvm->srcu);
5769 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5770 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5771 mmu_reset_needed = 1;
5772 }
5773 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5774
5775 if (mmu_reset_needed)
5776 kvm_mmu_reset_context(vcpu);
5777
5778 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5779 pending_vec = find_first_bit(
5780 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5781 if (pending_vec < max_bits) {
5782 kvm_queue_interrupt(vcpu, pending_vec, false);
5783 pr_debug("Set back pending irq %d\n", pending_vec);
5784 }
5785
5786 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5787 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5788 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5789 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5790 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5791 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5792
5793 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5794 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5795
5796 update_cr8_intercept(vcpu);
5797
5798 /* Older userspace won't unhalt the vcpu on reset. */
5799 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5800 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5801 !is_protmode(vcpu))
5802 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5803
5804 kvm_make_request(KVM_REQ_EVENT, vcpu);
5805
5806 return 0;
5807 }
5808
5809 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5810 struct kvm_guest_debug *dbg)
5811 {
5812 unsigned long rflags;
5813 int i, r;
5814
5815 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5816 r = -EBUSY;
5817 if (vcpu->arch.exception.pending)
5818 goto out;
5819 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5820 kvm_queue_exception(vcpu, DB_VECTOR);
5821 else
5822 kvm_queue_exception(vcpu, BP_VECTOR);
5823 }
5824
5825 /*
5826 * Read rflags as long as potentially injected trace flags are still
5827 * filtered out.
5828 */
5829 rflags = kvm_get_rflags(vcpu);
5830
5831 vcpu->guest_debug = dbg->control;
5832 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5833 vcpu->guest_debug = 0;
5834
5835 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5836 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5837 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5838 vcpu->arch.switch_db_regs =
5839 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5840 } else {
5841 for (i = 0; i < KVM_NR_DB_REGS; i++)
5842 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5843 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5844 }
5845
5846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5847 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5848 get_segment_base(vcpu, VCPU_SREG_CS);
5849
5850 /*
5851 * Trigger an rflags update that will inject or remove the trace
5852 * flags.
5853 */
5854 kvm_set_rflags(vcpu, rflags);
5855
5856 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5857
5858 r = 0;
5859
5860 out:
5861
5862 return r;
5863 }
5864
5865 /*
5866 * Translate a guest virtual address to a guest physical address.
5867 */
5868 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5869 struct kvm_translation *tr)
5870 {
5871 unsigned long vaddr = tr->linear_address;
5872 gpa_t gpa;
5873 int idx;
5874
5875 idx = srcu_read_lock(&vcpu->kvm->srcu);
5876 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5877 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5878 tr->physical_address = gpa;
5879 tr->valid = gpa != UNMAPPED_GVA;
5880 tr->writeable = 1;
5881 tr->usermode = 0;
5882
5883 return 0;
5884 }
5885
5886 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5887 {
5888 struct i387_fxsave_struct *fxsave =
5889 &vcpu->arch.guest_fpu.state->fxsave;
5890
5891 memcpy(fpu->fpr, fxsave->st_space, 128);
5892 fpu->fcw = fxsave->cwd;
5893 fpu->fsw = fxsave->swd;
5894 fpu->ftwx = fxsave->twd;
5895 fpu->last_opcode = fxsave->fop;
5896 fpu->last_ip = fxsave->rip;
5897 fpu->last_dp = fxsave->rdp;
5898 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5899
5900 return 0;
5901 }
5902
5903 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5904 {
5905 struct i387_fxsave_struct *fxsave =
5906 &vcpu->arch.guest_fpu.state->fxsave;
5907
5908 memcpy(fxsave->st_space, fpu->fpr, 128);
5909 fxsave->cwd = fpu->fcw;
5910 fxsave->swd = fpu->fsw;
5911 fxsave->twd = fpu->ftwx;
5912 fxsave->fop = fpu->last_opcode;
5913 fxsave->rip = fpu->last_ip;
5914 fxsave->rdp = fpu->last_dp;
5915 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5916
5917 return 0;
5918 }
5919
5920 int fx_init(struct kvm_vcpu *vcpu)
5921 {
5922 int err;
5923
5924 err = fpu_alloc(&vcpu->arch.guest_fpu);
5925 if (err)
5926 return err;
5927
5928 fpu_finit(&vcpu->arch.guest_fpu);
5929
5930 /*
5931 * Ensure guest xcr0 is valid for loading
5932 */
5933 vcpu->arch.xcr0 = XSTATE_FP;
5934
5935 vcpu->arch.cr0 |= X86_CR0_ET;
5936
5937 return 0;
5938 }
5939 EXPORT_SYMBOL_GPL(fx_init);
5940
5941 static void fx_free(struct kvm_vcpu *vcpu)
5942 {
5943 fpu_free(&vcpu->arch.guest_fpu);
5944 }
5945
5946 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5947 {
5948 if (vcpu->guest_fpu_loaded)
5949 return;
5950
5951 /*
5952 * Restore all possible states in the guest,
5953 * and assume host would use all available bits.
5954 * Guest xcr0 would be loaded later.
5955 */
5956 kvm_put_guest_xcr0(vcpu);
5957 vcpu->guest_fpu_loaded = 1;
5958 unlazy_fpu(current);
5959 fpu_restore_checking(&vcpu->arch.guest_fpu);
5960 trace_kvm_fpu(1);
5961 }
5962
5963 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5964 {
5965 kvm_put_guest_xcr0(vcpu);
5966
5967 if (!vcpu->guest_fpu_loaded)
5968 return;
5969
5970 vcpu->guest_fpu_loaded = 0;
5971 fpu_save_init(&vcpu->arch.guest_fpu);
5972 ++vcpu->stat.fpu_reload;
5973 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5974 trace_kvm_fpu(0);
5975 }
5976
5977 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5978 {
5979 kvmclock_reset(vcpu);
5980
5981 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5982 fx_free(vcpu);
5983 kvm_x86_ops->vcpu_free(vcpu);
5984 }
5985
5986 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5987 unsigned int id)
5988 {
5989 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5990 printk_once(KERN_WARNING
5991 "kvm: SMP vm created on host with unstable TSC; "
5992 "guest TSC will not be reliable\n");
5993 return kvm_x86_ops->vcpu_create(kvm, id);
5994 }
5995
5996 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5997 {
5998 int r;
5999
6000 vcpu->arch.mtrr_state.have_fixed = 1;
6001 vcpu_load(vcpu);
6002 r = kvm_arch_vcpu_reset(vcpu);
6003 if (r == 0)
6004 r = kvm_mmu_setup(vcpu);
6005 vcpu_put(vcpu);
6006
6007 return r;
6008 }
6009
6010 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6011 {
6012 vcpu->arch.apf.msr_val = 0;
6013
6014 vcpu_load(vcpu);
6015 kvm_mmu_unload(vcpu);
6016 vcpu_put(vcpu);
6017
6018 fx_free(vcpu);
6019 kvm_x86_ops->vcpu_free(vcpu);
6020 }
6021
6022 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6023 {
6024 atomic_set(&vcpu->arch.nmi_queued, 0);
6025 vcpu->arch.nmi_pending = 0;
6026 vcpu->arch.nmi_injected = false;
6027
6028 vcpu->arch.switch_db_regs = 0;
6029 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6030 vcpu->arch.dr6 = DR6_FIXED_1;
6031 vcpu->arch.dr7 = DR7_FIXED_1;
6032
6033 kvm_make_request(KVM_REQ_EVENT, vcpu);
6034 vcpu->arch.apf.msr_val = 0;
6035 vcpu->arch.st.msr_val = 0;
6036
6037 kvmclock_reset(vcpu);
6038
6039 kvm_clear_async_pf_completion_queue(vcpu);
6040 kvm_async_pf_hash_reset(vcpu);
6041 vcpu->arch.apf.halted = false;
6042
6043 kvm_pmu_reset(vcpu);
6044
6045 return kvm_x86_ops->vcpu_reset(vcpu);
6046 }
6047
6048 int kvm_arch_hardware_enable(void *garbage)
6049 {
6050 struct kvm *kvm;
6051 struct kvm_vcpu *vcpu;
6052 int i;
6053 int ret;
6054 u64 local_tsc;
6055 u64 max_tsc = 0;
6056 bool stable, backwards_tsc = false;
6057
6058 kvm_shared_msr_cpu_online();
6059 ret = kvm_x86_ops->hardware_enable(garbage);
6060 if (ret != 0)
6061 return ret;
6062
6063 local_tsc = native_read_tsc();
6064 stable = !check_tsc_unstable();
6065 list_for_each_entry(kvm, &vm_list, vm_list) {
6066 kvm_for_each_vcpu(i, vcpu, kvm) {
6067 if (!stable && vcpu->cpu == smp_processor_id())
6068 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6069 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6070 backwards_tsc = true;
6071 if (vcpu->arch.last_host_tsc > max_tsc)
6072 max_tsc = vcpu->arch.last_host_tsc;
6073 }
6074 }
6075 }
6076
6077 /*
6078 * Sometimes, even reliable TSCs go backwards. This happens on
6079 * platforms that reset TSC during suspend or hibernate actions, but
6080 * maintain synchronization. We must compensate. Fortunately, we can
6081 * detect that condition here, which happens early in CPU bringup,
6082 * before any KVM threads can be running. Unfortunately, we can't
6083 * bring the TSCs fully up to date with real time, as we aren't yet far
6084 * enough into CPU bringup that we know how much real time has actually
6085 * elapsed; our helper function, get_kernel_ns() will be using boot
6086 * variables that haven't been updated yet.
6087 *
6088 * So we simply find the maximum observed TSC above, then record the
6089 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6090 * the adjustment will be applied. Note that we accumulate
6091 * adjustments, in case multiple suspend cycles happen before some VCPU
6092 * gets a chance to run again. In the event that no KVM threads get a
6093 * chance to run, we will miss the entire elapsed period, as we'll have
6094 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6095 * loose cycle time. This isn't too big a deal, since the loss will be
6096 * uniform across all VCPUs (not to mention the scenario is extremely
6097 * unlikely). It is possible that a second hibernate recovery happens
6098 * much faster than a first, causing the observed TSC here to be
6099 * smaller; this would require additional padding adjustment, which is
6100 * why we set last_host_tsc to the local tsc observed here.
6101 *
6102 * N.B. - this code below runs only on platforms with reliable TSC,
6103 * as that is the only way backwards_tsc is set above. Also note
6104 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6105 * have the same delta_cyc adjustment applied if backwards_tsc
6106 * is detected. Note further, this adjustment is only done once,
6107 * as we reset last_host_tsc on all VCPUs to stop this from being
6108 * called multiple times (one for each physical CPU bringup).
6109 *
6110 * Platforms with unreliable TSCs don't have to deal with this, they
6111 * will be compensated by the logic in vcpu_load, which sets the TSC to
6112 * catchup mode. This will catchup all VCPUs to real time, but cannot
6113 * guarantee that they stay in perfect synchronization.
6114 */
6115 if (backwards_tsc) {
6116 u64 delta_cyc = max_tsc - local_tsc;
6117 list_for_each_entry(kvm, &vm_list, vm_list) {
6118 kvm_for_each_vcpu(i, vcpu, kvm) {
6119 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6120 vcpu->arch.last_host_tsc = local_tsc;
6121 }
6122
6123 /*
6124 * We have to disable TSC offset matching.. if you were
6125 * booting a VM while issuing an S4 host suspend....
6126 * you may have some problem. Solving this issue is
6127 * left as an exercise to the reader.
6128 */
6129 kvm->arch.last_tsc_nsec = 0;
6130 kvm->arch.last_tsc_write = 0;
6131 }
6132
6133 }
6134 return 0;
6135 }
6136
6137 void kvm_arch_hardware_disable(void *garbage)
6138 {
6139 kvm_x86_ops->hardware_disable(garbage);
6140 drop_user_return_notifiers(garbage);
6141 }
6142
6143 int kvm_arch_hardware_setup(void)
6144 {
6145 return kvm_x86_ops->hardware_setup();
6146 }
6147
6148 void kvm_arch_hardware_unsetup(void)
6149 {
6150 kvm_x86_ops->hardware_unsetup();
6151 }
6152
6153 void kvm_arch_check_processor_compat(void *rtn)
6154 {
6155 kvm_x86_ops->check_processor_compatibility(rtn);
6156 }
6157
6158 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6159 {
6160 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6161 }
6162
6163 struct static_key kvm_no_apic_vcpu __read_mostly;
6164
6165 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6166 {
6167 struct page *page;
6168 struct kvm *kvm;
6169 int r;
6170
6171 BUG_ON(vcpu->kvm == NULL);
6172 kvm = vcpu->kvm;
6173
6174 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6175 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6176 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6177 else
6178 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6179
6180 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6181 if (!page) {
6182 r = -ENOMEM;
6183 goto fail;
6184 }
6185 vcpu->arch.pio_data = page_address(page);
6186
6187 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6188
6189 r = kvm_mmu_create(vcpu);
6190 if (r < 0)
6191 goto fail_free_pio_data;
6192
6193 if (irqchip_in_kernel(kvm)) {
6194 r = kvm_create_lapic(vcpu);
6195 if (r < 0)
6196 goto fail_mmu_destroy;
6197 } else
6198 static_key_slow_inc(&kvm_no_apic_vcpu);
6199
6200 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6201 GFP_KERNEL);
6202 if (!vcpu->arch.mce_banks) {
6203 r = -ENOMEM;
6204 goto fail_free_lapic;
6205 }
6206 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6207
6208 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6209 goto fail_free_mce_banks;
6210
6211 kvm_async_pf_hash_reset(vcpu);
6212 kvm_pmu_init(vcpu);
6213
6214 return 0;
6215 fail_free_mce_banks:
6216 kfree(vcpu->arch.mce_banks);
6217 fail_free_lapic:
6218 kvm_free_lapic(vcpu);
6219 fail_mmu_destroy:
6220 kvm_mmu_destroy(vcpu);
6221 fail_free_pio_data:
6222 free_page((unsigned long)vcpu->arch.pio_data);
6223 fail:
6224 return r;
6225 }
6226
6227 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6228 {
6229 int idx;
6230
6231 kvm_pmu_destroy(vcpu);
6232 kfree(vcpu->arch.mce_banks);
6233 kvm_free_lapic(vcpu);
6234 idx = srcu_read_lock(&vcpu->kvm->srcu);
6235 kvm_mmu_destroy(vcpu);
6236 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6237 free_page((unsigned long)vcpu->arch.pio_data);
6238 if (!irqchip_in_kernel(vcpu->kvm))
6239 static_key_slow_dec(&kvm_no_apic_vcpu);
6240 }
6241
6242 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6243 {
6244 if (type)
6245 return -EINVAL;
6246
6247 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6248 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6249
6250 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6251 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6252
6253 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6254
6255 return 0;
6256 }
6257
6258 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6259 {
6260 vcpu_load(vcpu);
6261 kvm_mmu_unload(vcpu);
6262 vcpu_put(vcpu);
6263 }
6264
6265 static void kvm_free_vcpus(struct kvm *kvm)
6266 {
6267 unsigned int i;
6268 struct kvm_vcpu *vcpu;
6269
6270 /*
6271 * Unpin any mmu pages first.
6272 */
6273 kvm_for_each_vcpu(i, vcpu, kvm) {
6274 kvm_clear_async_pf_completion_queue(vcpu);
6275 kvm_unload_vcpu_mmu(vcpu);
6276 }
6277 kvm_for_each_vcpu(i, vcpu, kvm)
6278 kvm_arch_vcpu_free(vcpu);
6279
6280 mutex_lock(&kvm->lock);
6281 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6282 kvm->vcpus[i] = NULL;
6283
6284 atomic_set(&kvm->online_vcpus, 0);
6285 mutex_unlock(&kvm->lock);
6286 }
6287
6288 void kvm_arch_sync_events(struct kvm *kvm)
6289 {
6290 kvm_free_all_assigned_devices(kvm);
6291 kvm_free_pit(kvm);
6292 }
6293
6294 void kvm_arch_destroy_vm(struct kvm *kvm)
6295 {
6296 kvm_iommu_unmap_guest(kvm);
6297 kfree(kvm->arch.vpic);
6298 kfree(kvm->arch.vioapic);
6299 kvm_free_vcpus(kvm);
6300 if (kvm->arch.apic_access_page)
6301 put_page(kvm->arch.apic_access_page);
6302 if (kvm->arch.ept_identity_pagetable)
6303 put_page(kvm->arch.ept_identity_pagetable);
6304 }
6305
6306 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6307 struct kvm_memory_slot *dont)
6308 {
6309 int i;
6310
6311 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6312 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6313 kvm_kvfree(free->arch.rmap[i]);
6314 free->arch.rmap[i] = NULL;
6315 }
6316 if (i == 0)
6317 continue;
6318
6319 if (!dont || free->arch.lpage_info[i - 1] !=
6320 dont->arch.lpage_info[i - 1]) {
6321 kvm_kvfree(free->arch.lpage_info[i - 1]);
6322 free->arch.lpage_info[i - 1] = NULL;
6323 }
6324 }
6325 }
6326
6327 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6328 {
6329 int i;
6330
6331 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6332 unsigned long ugfn;
6333 int lpages;
6334 int level = i + 1;
6335
6336 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6337 slot->base_gfn, level) + 1;
6338
6339 slot->arch.rmap[i] =
6340 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6341 if (!slot->arch.rmap[i])
6342 goto out_free;
6343 if (i == 0)
6344 continue;
6345
6346 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6347 sizeof(*slot->arch.lpage_info[i - 1]));
6348 if (!slot->arch.lpage_info[i - 1])
6349 goto out_free;
6350
6351 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6352 slot->arch.lpage_info[i - 1][0].write_count = 1;
6353 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6354 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6355 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6356 /*
6357 * If the gfn and userspace address are not aligned wrt each
6358 * other, or if explicitly asked to, disable large page
6359 * support for this slot
6360 */
6361 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6362 !kvm_largepages_enabled()) {
6363 unsigned long j;
6364
6365 for (j = 0; j < lpages; ++j)
6366 slot->arch.lpage_info[i - 1][j].write_count = 1;
6367 }
6368 }
6369
6370 return 0;
6371
6372 out_free:
6373 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6374 kvm_kvfree(slot->arch.rmap[i]);
6375 slot->arch.rmap[i] = NULL;
6376 if (i == 0)
6377 continue;
6378
6379 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6380 slot->arch.lpage_info[i - 1] = NULL;
6381 }
6382 return -ENOMEM;
6383 }
6384
6385 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6386 struct kvm_memory_slot *memslot,
6387 struct kvm_memory_slot old,
6388 struct kvm_userspace_memory_region *mem,
6389 int user_alloc)
6390 {
6391 int npages = memslot->npages;
6392 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6393
6394 /* Prevent internal slot pages from being moved by fork()/COW. */
6395 if (memslot->id >= KVM_MEMORY_SLOTS)
6396 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6397
6398 /*To keep backward compatibility with older userspace,
6399 *x86 needs to handle !user_alloc case.
6400 */
6401 if (!user_alloc) {
6402 if (npages && !old.npages) {
6403 unsigned long userspace_addr;
6404
6405 userspace_addr = vm_mmap(NULL, 0,
6406 npages * PAGE_SIZE,
6407 PROT_READ | PROT_WRITE,
6408 map_flags,
6409 0);
6410
6411 if (IS_ERR((void *)userspace_addr))
6412 return PTR_ERR((void *)userspace_addr);
6413
6414 memslot->userspace_addr = userspace_addr;
6415 }
6416 }
6417
6418
6419 return 0;
6420 }
6421
6422 void kvm_arch_commit_memory_region(struct kvm *kvm,
6423 struct kvm_userspace_memory_region *mem,
6424 struct kvm_memory_slot old,
6425 int user_alloc)
6426 {
6427
6428 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6429
6430 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
6431 int ret;
6432
6433 ret = vm_munmap(old.userspace_addr,
6434 old.npages * PAGE_SIZE);
6435 if (ret < 0)
6436 printk(KERN_WARNING
6437 "kvm_vm_ioctl_set_memory_region: "
6438 "failed to munmap memory\n");
6439 }
6440
6441 if (!kvm->arch.n_requested_mmu_pages)
6442 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6443
6444 spin_lock(&kvm->mmu_lock);
6445 if (nr_mmu_pages)
6446 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6447 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6448 spin_unlock(&kvm->mmu_lock);
6449 }
6450
6451 void kvm_arch_flush_shadow(struct kvm *kvm)
6452 {
6453 kvm_mmu_zap_all(kvm);
6454 kvm_reload_remote_mmus(kvm);
6455 }
6456
6457 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6458 {
6459 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6460 !vcpu->arch.apf.halted)
6461 || !list_empty_careful(&vcpu->async_pf.done)
6462 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6463 || atomic_read(&vcpu->arch.nmi_queued) ||
6464 (kvm_arch_interrupt_allowed(vcpu) &&
6465 kvm_cpu_has_interrupt(vcpu));
6466 }
6467
6468 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6469 {
6470 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6471 }
6472
6473 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6474 {
6475 return kvm_x86_ops->interrupt_allowed(vcpu);
6476 }
6477
6478 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6479 {
6480 unsigned long current_rip = kvm_rip_read(vcpu) +
6481 get_segment_base(vcpu, VCPU_SREG_CS);
6482
6483 return current_rip == linear_rip;
6484 }
6485 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6486
6487 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6488 {
6489 unsigned long rflags;
6490
6491 rflags = kvm_x86_ops->get_rflags(vcpu);
6492 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6493 rflags &= ~X86_EFLAGS_TF;
6494 return rflags;
6495 }
6496 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6497
6498 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6499 {
6500 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6501 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6502 rflags |= X86_EFLAGS_TF;
6503 kvm_x86_ops->set_rflags(vcpu, rflags);
6504 kvm_make_request(KVM_REQ_EVENT, vcpu);
6505 }
6506 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6507
6508 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6509 {
6510 int r;
6511
6512 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6513 is_error_page(work->page))
6514 return;
6515
6516 r = kvm_mmu_reload(vcpu);
6517 if (unlikely(r))
6518 return;
6519
6520 if (!vcpu->arch.mmu.direct_map &&
6521 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6522 return;
6523
6524 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6525 }
6526
6527 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6528 {
6529 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6530 }
6531
6532 static inline u32 kvm_async_pf_next_probe(u32 key)
6533 {
6534 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6535 }
6536
6537 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6538 {
6539 u32 key = kvm_async_pf_hash_fn(gfn);
6540
6541 while (vcpu->arch.apf.gfns[key] != ~0)
6542 key = kvm_async_pf_next_probe(key);
6543
6544 vcpu->arch.apf.gfns[key] = gfn;
6545 }
6546
6547 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6548 {
6549 int i;
6550 u32 key = kvm_async_pf_hash_fn(gfn);
6551
6552 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6553 (vcpu->arch.apf.gfns[key] != gfn &&
6554 vcpu->arch.apf.gfns[key] != ~0); i++)
6555 key = kvm_async_pf_next_probe(key);
6556
6557 return key;
6558 }
6559
6560 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6561 {
6562 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6563 }
6564
6565 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6566 {
6567 u32 i, j, k;
6568
6569 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6570 while (true) {
6571 vcpu->arch.apf.gfns[i] = ~0;
6572 do {
6573 j = kvm_async_pf_next_probe(j);
6574 if (vcpu->arch.apf.gfns[j] == ~0)
6575 return;
6576 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6577 /*
6578 * k lies cyclically in ]i,j]
6579 * | i.k.j |
6580 * |....j i.k.| or |.k..j i...|
6581 */
6582 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6583 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6584 i = j;
6585 }
6586 }
6587
6588 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6589 {
6590
6591 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6592 sizeof(val));
6593 }
6594
6595 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6596 struct kvm_async_pf *work)
6597 {
6598 struct x86_exception fault;
6599
6600 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6601 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6602
6603 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6604 (vcpu->arch.apf.send_user_only &&
6605 kvm_x86_ops->get_cpl(vcpu) == 0))
6606 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6607 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6608 fault.vector = PF_VECTOR;
6609 fault.error_code_valid = true;
6610 fault.error_code = 0;
6611 fault.nested_page_fault = false;
6612 fault.address = work->arch.token;
6613 kvm_inject_page_fault(vcpu, &fault);
6614 }
6615 }
6616
6617 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6618 struct kvm_async_pf *work)
6619 {
6620 struct x86_exception fault;
6621
6622 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6623 if (is_error_page(work->page))
6624 work->arch.token = ~0; /* broadcast wakeup */
6625 else
6626 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6627
6628 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6629 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6630 fault.vector = PF_VECTOR;
6631 fault.error_code_valid = true;
6632 fault.error_code = 0;
6633 fault.nested_page_fault = false;
6634 fault.address = work->arch.token;
6635 kvm_inject_page_fault(vcpu, &fault);
6636 }
6637 vcpu->arch.apf.halted = false;
6638 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6639 }
6640
6641 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6642 {
6643 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6644 return true;
6645 else
6646 return !kvm_event_needs_reinjection(vcpu) &&
6647 kvm_x86_ops->interrupt_allowed(vcpu);
6648 }
6649
6650 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6651 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6652 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6653 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6654 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6655 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6656 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6657 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6658 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6659 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6660 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6661 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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