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Merge tag 'kvm-3.9-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109 int nr;
110 u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
158 { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
166
167 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168 {
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172 }
173
174 static void kvm_on_user_return(struct user_return_notifier *urn)
175 {
176 unsigned slot;
177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
179 struct kvm_shared_msr_values *values;
180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190 }
191
192 static void shared_msr_update(unsigned slot, u32 msr)
193 {
194 u64 value;
195 unsigned int cpu = smp_processor_id();
196 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
197
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207 }
208
209 void kvm_define_shared_msr(unsigned slot, u32 msr)
210 {
211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
216 }
217 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219 static void kvm_shared_msr_cpu_online(void)
220 {
221 unsigned i;
222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
224 shared_msr_update(i, shared_msrs_global.msrs[i]);
225 }
226
227 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
228 {
229 unsigned int cpu = smp_processor_id();
230 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
231
232 if (((value ^ smsr->values[slot].curr) & mask) == 0)
233 return;
234 smsr->values[slot].curr = value;
235 wrmsrl(shared_msrs_global.msrs[slot], value);
236 if (!smsr->registered) {
237 smsr->urn.on_user_return = kvm_on_user_return;
238 user_return_notifier_register(&smsr->urn);
239 smsr->registered = true;
240 }
241 }
242 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
243
244 static void drop_user_return_notifiers(void *ignore)
245 {
246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
248
249 if (smsr->registered)
250 kvm_on_user_return(&smsr->urn);
251 }
252
253 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254 {
255 return vcpu->arch.apic_base;
256 }
257 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
258
259 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
260 {
261 /* TODO: reserve bits check */
262 kvm_lapic_set_base(vcpu, data);
263 }
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
268 #define EXCPT_PF 2
269
270 static int exception_class(int vector)
271 {
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285 }
286
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
290 {
291 u32 prev_nr;
292 int class1, class2;
293
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327 }
328
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
332 }
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 {
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338 }
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
342 {
343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 }
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 {
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 }
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362 else
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
364 }
365
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 {
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
370 }
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 }
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 {
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 }
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
385 /*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 {
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
395 }
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
397
398 /*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406 {
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 }
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423 {
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426 }
427
428 /*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 {
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
460 out:
461
462 return ret;
463 }
464 EXPORT_SYMBOL_GPL(load_pdptrs);
465
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 {
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469 bool changed = true;
470 int offset;
471 gfn_t gfn;
472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
485 if (r < 0)
486 goto out;
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 out:
489
490 return changed;
491 }
492
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 {
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
499 cr0 |= X86_CR0_ET;
500
501 #ifdef CONFIG_X86_64
502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
504 #endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
507
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
510
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 #ifdef CONFIG_X86_64
516 if ((vcpu->arch.efer & EFER_LME)) {
517 int cs_db, cs_l;
518
519 if (!is_pae(vcpu))
520 return 1;
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522 if (cs_l)
523 return 1;
524 } else
525 #endif
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527 kvm_read_cr3(vcpu)))
528 return 1;
529 }
530
531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
534 kvm_x86_ops->set_cr0(vcpu, cr0);
535
536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537 kvm_clear_async_pf_completion_queue(vcpu);
538 kvm_async_pf_hash_reset(vcpu);
539 }
540
541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
543 return 0;
544 }
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
546
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
548 {
549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
550 }
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
552
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554 {
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572 }
573
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575 {
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581 }
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
585 {
586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
591
592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
601 if (is_long_mode(vcpu)) {
602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
608 return 1;
609
610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
620 return 1;
621
622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624 kvm_mmu_reset_context(vcpu);
625
626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 kvm_update_cpuid(vcpu);
628
629 return 0;
630 }
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
632
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
634 {
635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636 kvm_mmu_sync_roots(vcpu);
637 kvm_mmu_flush_tlb(vcpu);
638 return 0;
639 }
640
641 if (is_long_mode(vcpu)) {
642 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
648 } else {
649 if (is_pae(vcpu)) {
650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
654 return 1;
655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
672 return 1;
673 vcpu->arch.cr3 = cr3;
674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677 }
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
679
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
681 {
682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
687 vcpu->arch.cr8 = cr8;
688 return 0;
689 }
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
691
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
693 {
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
697 return vcpu->arch.cr8;
698 }
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
700
701 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
702 {
703 unsigned long dr7;
704
705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
706 dr7 = vcpu->arch.guest_debug_dr7;
707 else
708 dr7 = vcpu->arch.dr7;
709 kvm_x86_ops->set_dr7(vcpu, dr7);
710 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
711 }
712
713 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
714 {
715 switch (dr) {
716 case 0 ... 3:
717 vcpu->arch.db[dr] = val;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
719 vcpu->arch.eff_db[dr] = val;
720 break;
721 case 4:
722 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 return 1; /* #UD */
724 /* fall through */
725 case 6:
726 if (val & 0xffffffff00000000ULL)
727 return -1; /* #GP */
728 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
729 break;
730 case 5:
731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
732 return 1; /* #UD */
733 /* fall through */
734 default: /* 7 */
735 if (val & 0xffffffff00000000ULL)
736 return -1; /* #GP */
737 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
738 kvm_update_dr7(vcpu);
739 break;
740 }
741
742 return 0;
743 }
744
745 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
746 {
747 int res;
748
749 res = __kvm_set_dr(vcpu, dr, val);
750 if (res > 0)
751 kvm_queue_exception(vcpu, UD_VECTOR);
752 else if (res < 0)
753 kvm_inject_gp(vcpu, 0);
754
755 return res;
756 }
757 EXPORT_SYMBOL_GPL(kvm_set_dr);
758
759 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
760 {
761 switch (dr) {
762 case 0 ... 3:
763 *val = vcpu->arch.db[dr];
764 break;
765 case 4:
766 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
767 return 1;
768 /* fall through */
769 case 6:
770 *val = vcpu->arch.dr6;
771 break;
772 case 5:
773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
774 return 1;
775 /* fall through */
776 default: /* 7 */
777 *val = vcpu->arch.dr7;
778 break;
779 }
780
781 return 0;
782 }
783
784 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
785 {
786 if (_kvm_get_dr(vcpu, dr, val)) {
787 kvm_queue_exception(vcpu, UD_VECTOR);
788 return 1;
789 }
790 return 0;
791 }
792 EXPORT_SYMBOL_GPL(kvm_get_dr);
793
794 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
795 {
796 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
797 u64 data;
798 int err;
799
800 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
801 if (err)
802 return err;
803 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
804 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
805 return err;
806 }
807 EXPORT_SYMBOL_GPL(kvm_rdpmc);
808
809 /*
810 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
811 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
812 *
813 * This list is modified at module load time to reflect the
814 * capabilities of the host cpu. This capabilities test skips MSRs that are
815 * kvm-specific. Those are put in the beginning of the list.
816 */
817
818 #define KVM_SAVE_MSRS_BEGIN 10
819 static u32 msrs_to_save[] = {
820 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
821 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
822 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
823 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
824 MSR_KVM_PV_EOI_EN,
825 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
826 MSR_STAR,
827 #ifdef CONFIG_X86_64
828 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
829 #endif
830 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
831 };
832
833 static unsigned num_msrs_to_save;
834
835 static const u32 emulated_msrs[] = {
836 MSR_IA32_TSC_ADJUST,
837 MSR_IA32_TSCDEADLINE,
838 MSR_IA32_MISC_ENABLE,
839 MSR_IA32_MCG_STATUS,
840 MSR_IA32_MCG_CTL,
841 };
842
843 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
844 {
845 u64 old_efer = vcpu->arch.efer;
846
847 if (efer & efer_reserved_bits)
848 return 1;
849
850 if (is_paging(vcpu)
851 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
852 return 1;
853
854 if (efer & EFER_FFXSR) {
855 struct kvm_cpuid_entry2 *feat;
856
857 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
858 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
859 return 1;
860 }
861
862 if (efer & EFER_SVME) {
863 struct kvm_cpuid_entry2 *feat;
864
865 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
866 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
867 return 1;
868 }
869
870 efer &= ~EFER_LMA;
871 efer |= vcpu->arch.efer & EFER_LMA;
872
873 kvm_x86_ops->set_efer(vcpu, efer);
874
875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
878
879 return 0;
880 }
881
882 void kvm_enable_efer_bits(u64 mask)
883 {
884 efer_reserved_bits &= ~mask;
885 }
886 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
887
888
889 /*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
894 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
895 {
896 return kvm_x86_ops->set_msr(vcpu, msr);
897 }
898
899 /*
900 * Adapt set_msr() to msr_io()'s calling convention
901 */
902 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
903 {
904 struct msr_data msr;
905
906 msr.data = *data;
907 msr.index = index;
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
910 }
911
912 #ifdef CONFIG_X86_64
913 struct pvclock_gtod_data {
914 seqcount_t seq;
915
916 struct { /* extract of a clocksource struct */
917 int vclock_mode;
918 cycle_t cycle_last;
919 cycle_t mask;
920 u32 mult;
921 u32 shift;
922 } clock;
923
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
927 };
928
929 static struct pvclock_gtod_data pvclock_gtod_data;
930
931 static void update_pvclock_gtod(struct timekeeper *tk)
932 {
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
934
935 write_seqcount_begin(&vdata->seq);
936
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
943
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
948 << tk->shift);
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
954 }
955
956 write_seqcount_end(&vdata->seq);
957 }
958 #endif
959
960
961 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
962 {
963 int version;
964 int r;
965 struct pvclock_wall_clock wc;
966 struct timespec boot;
967
968 if (!wall_clock)
969 return;
970
971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
972 if (r)
973 return;
974
975 if (version & 1)
976 ++version; /* first time write, random junk */
977
978 ++version;
979
980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
981
982 /*
983 * The guest calculates current wall clock time by adding
984 * system time (updated by kvm_guest_time_update below) to the
985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
987 */
988 getboottime(&boot);
989
990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
993 }
994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
997
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
999
1000 version++;
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1002 }
1003
1004 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1005 {
1006 uint32_t quotient, remainder;
1007
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1010 __asm__ ( "divl %4"
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1013 return quotient;
1014 }
1015
1016 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
1018 {
1019 uint64_t scaled64;
1020 int32_t shift = 0;
1021 uint64_t tps64;
1022 uint32_t tps32;
1023
1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1027 tps64 >>= 1;
1028 shift--;
1029 }
1030
1031 tps32 = (uint32_t)tps64;
1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1034 scaled64 >>= 1;
1035 else
1036 tps32 <<= 1;
1037 shift++;
1038 }
1039
1040 *pshift = shift;
1041 *pmultiplier = div_frac(scaled64, tps32);
1042
1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1045 }
1046
1047 static inline u64 get_kernel_ns(void)
1048 {
1049 struct timespec ts;
1050
1051 WARN_ON(preemptible());
1052 ktime_get_ts(&ts);
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
1055 }
1056
1057 #ifdef CONFIG_X86_64
1058 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1059 #endif
1060
1061 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1062 unsigned long max_tsc_khz;
1063
1064 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1065 {
1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
1068 }
1069
1070 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1071 {
1072 u64 v = (u64)khz * (1000000 + ppm);
1073 do_div(v, 1000000);
1074 return v;
1075 }
1076
1077 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1078 {
1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
1081
1082 /* Compute a scale to convert nanoseconds in TSC cycles */
1083 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1084 &vcpu->arch.virtual_tsc_shift,
1085 &vcpu->arch.virtual_tsc_mult);
1086 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1087
1088 /*
1089 * Compute the variation in TSC rate which is acceptable
1090 * within the range of tolerance and decide if the
1091 * rate being applied is within that bounds of the hardware
1092 * rate. If so, no scaling or compensation need be done.
1093 */
1094 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1095 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1096 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1097 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1098 use_scaling = 1;
1099 }
1100 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1101 }
1102
1103 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1104 {
1105 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1106 vcpu->arch.virtual_tsc_mult,
1107 vcpu->arch.virtual_tsc_shift);
1108 tsc += vcpu->arch.this_tsc_write;
1109 return tsc;
1110 }
1111
1112 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1113 {
1114 #ifdef CONFIG_X86_64
1115 bool vcpus_matched;
1116 bool do_request = false;
1117 struct kvm_arch *ka = &vcpu->kvm->arch;
1118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1119
1120 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1121 atomic_read(&vcpu->kvm->online_vcpus));
1122
1123 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1124 if (!ka->use_master_clock)
1125 do_request = 1;
1126
1127 if (!vcpus_matched && ka->use_master_clock)
1128 do_request = 1;
1129
1130 if (do_request)
1131 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1132
1133 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1134 atomic_read(&vcpu->kvm->online_vcpus),
1135 ka->use_master_clock, gtod->clock.vclock_mode);
1136 #endif
1137 }
1138
1139 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1140 {
1141 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1142 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1143 }
1144
1145 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1146 {
1147 struct kvm *kvm = vcpu->kvm;
1148 u64 offset, ns, elapsed;
1149 unsigned long flags;
1150 s64 usdiff;
1151 bool matched;
1152 u64 data = msr->data;
1153
1154 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1155 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1156 ns = get_kernel_ns();
1157 elapsed = ns - kvm->arch.last_tsc_nsec;
1158
1159 /* n.b - signed multiplication and division required */
1160 usdiff = data - kvm->arch.last_tsc_write;
1161 #ifdef CONFIG_X86_64
1162 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1163 #else
1164 /* do_div() only does unsigned */
1165 asm("idivl %2; xor %%edx, %%edx"
1166 : "=A"(usdiff)
1167 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1168 #endif
1169 do_div(elapsed, 1000);
1170 usdiff -= elapsed;
1171 if (usdiff < 0)
1172 usdiff = -usdiff;
1173
1174 /*
1175 * Special case: TSC write with a small delta (1 second) of virtual
1176 * cycle time against real time is interpreted as an attempt to
1177 * synchronize the CPU.
1178 *
1179 * For a reliable TSC, we can match TSC offsets, and for an unstable
1180 * TSC, we add elapsed time in this computation. We could let the
1181 * compensation code attempt to catch up if we fall behind, but
1182 * it's better to try to match offsets from the beginning.
1183 */
1184 if (usdiff < USEC_PER_SEC &&
1185 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1186 if (!check_tsc_unstable()) {
1187 offset = kvm->arch.cur_tsc_offset;
1188 pr_debug("kvm: matched tsc offset for %llu\n", data);
1189 } else {
1190 u64 delta = nsec_to_cycles(vcpu, elapsed);
1191 data += delta;
1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1193 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1194 }
1195 matched = true;
1196 } else {
1197 /*
1198 * We split periods of matched TSC writes into generations.
1199 * For each generation, we track the original measured
1200 * nanosecond time, offset, and write, so if TSCs are in
1201 * sync, we can match exact offset, and if not, we can match
1202 * exact software computation in compute_guest_tsc()
1203 *
1204 * These values are tracked in kvm->arch.cur_xxx variables.
1205 */
1206 kvm->arch.cur_tsc_generation++;
1207 kvm->arch.cur_tsc_nsec = ns;
1208 kvm->arch.cur_tsc_write = data;
1209 kvm->arch.cur_tsc_offset = offset;
1210 matched = false;
1211 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1212 kvm->arch.cur_tsc_generation, data);
1213 }
1214
1215 /*
1216 * We also track th most recent recorded KHZ, write and time to
1217 * allow the matching interval to be extended at each write.
1218 */
1219 kvm->arch.last_tsc_nsec = ns;
1220 kvm->arch.last_tsc_write = data;
1221 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1222
1223 /* Reset of TSC must disable overshoot protection below */
1224 vcpu->arch.hv_clock.tsc_timestamp = 0;
1225 vcpu->arch.last_guest_tsc = data;
1226
1227 /* Keep track of which generation this VCPU has synchronized to */
1228 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1229 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1230 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1231
1232 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1233 update_ia32_tsc_adjust_msr(vcpu, offset);
1234 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1235 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1236
1237 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1238 if (matched)
1239 kvm->arch.nr_vcpus_matched_tsc++;
1240 else
1241 kvm->arch.nr_vcpus_matched_tsc = 0;
1242
1243 kvm_track_tsc_matching(vcpu);
1244 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1245 }
1246
1247 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1248
1249 #ifdef CONFIG_X86_64
1250
1251 static cycle_t read_tsc(void)
1252 {
1253 cycle_t ret;
1254 u64 last;
1255
1256 /*
1257 * Empirically, a fence (of type that depends on the CPU)
1258 * before rdtsc is enough to ensure that rdtsc is ordered
1259 * with respect to loads. The various CPU manuals are unclear
1260 * as to whether rdtsc can be reordered with later loads,
1261 * but no one has ever seen it happen.
1262 */
1263 rdtsc_barrier();
1264 ret = (cycle_t)vget_cycles();
1265
1266 last = pvclock_gtod_data.clock.cycle_last;
1267
1268 if (likely(ret >= last))
1269 return ret;
1270
1271 /*
1272 * GCC likes to generate cmov here, but this branch is extremely
1273 * predictable (it's just a funciton of time and the likely is
1274 * very likely) and there's a data dependence, so force GCC
1275 * to generate a branch instead. I don't barrier() because
1276 * we don't actually need a barrier, and if this function
1277 * ever gets inlined it will generate worse code.
1278 */
1279 asm volatile ("");
1280 return last;
1281 }
1282
1283 static inline u64 vgettsc(cycle_t *cycle_now)
1284 {
1285 long v;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 *cycle_now = read_tsc();
1289
1290 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1291 return v * gtod->clock.mult;
1292 }
1293
1294 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1295 {
1296 unsigned long seq;
1297 u64 ns;
1298 int mode;
1299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1300
1301 ts->tv_nsec = 0;
1302 do {
1303 seq = read_seqcount_begin(&gtod->seq);
1304 mode = gtod->clock.vclock_mode;
1305 ts->tv_sec = gtod->monotonic_time_sec;
1306 ns = gtod->monotonic_time_snsec;
1307 ns += vgettsc(cycle_now);
1308 ns >>= gtod->clock.shift;
1309 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1310 timespec_add_ns(ts, ns);
1311
1312 return mode;
1313 }
1314
1315 /* returns true if host is using tsc clocksource */
1316 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1317 {
1318 struct timespec ts;
1319
1320 /* checked again under seqlock below */
1321 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1322 return false;
1323
1324 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1325 return false;
1326
1327 monotonic_to_bootbased(&ts);
1328 *kernel_ns = timespec_to_ns(&ts);
1329
1330 return true;
1331 }
1332 #endif
1333
1334 /*
1335 *
1336 * Assuming a stable TSC across physical CPUS, and a stable TSC
1337 * across virtual CPUs, the following condition is possible.
1338 * Each numbered line represents an event visible to both
1339 * CPUs at the next numbered event.
1340 *
1341 * "timespecX" represents host monotonic time. "tscX" represents
1342 * RDTSC value.
1343 *
1344 * VCPU0 on CPU0 | VCPU1 on CPU1
1345 *
1346 * 1. read timespec0,tsc0
1347 * 2. | timespec1 = timespec0 + N
1348 * | tsc1 = tsc0 + M
1349 * 3. transition to guest | transition to guest
1350 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1351 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1352 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1353 *
1354 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1355 *
1356 * - ret0 < ret1
1357 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1358 * ...
1359 * - 0 < N - M => M < N
1360 *
1361 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1362 * always the case (the difference between two distinct xtime instances
1363 * might be smaller then the difference between corresponding TSC reads,
1364 * when updating guest vcpus pvclock areas).
1365 *
1366 * To avoid that problem, do not allow visibility of distinct
1367 * system_timestamp/tsc_timestamp values simultaneously: use a master
1368 * copy of host monotonic time values. Update that master copy
1369 * in lockstep.
1370 *
1371 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1372 *
1373 */
1374
1375 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1376 {
1377 #ifdef CONFIG_X86_64
1378 struct kvm_arch *ka = &kvm->arch;
1379 int vclock_mode;
1380 bool host_tsc_clocksource, vcpus_matched;
1381
1382 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1383 atomic_read(&kvm->online_vcpus));
1384
1385 /*
1386 * If the host uses TSC clock, then passthrough TSC as stable
1387 * to the guest.
1388 */
1389 host_tsc_clocksource = kvm_get_time_and_clockread(
1390 &ka->master_kernel_ns,
1391 &ka->master_cycle_now);
1392
1393 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1394
1395 if (ka->use_master_clock)
1396 atomic_set(&kvm_guest_has_master_clock, 1);
1397
1398 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1399 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1400 vcpus_matched);
1401 #endif
1402 }
1403
1404 static int kvm_guest_time_update(struct kvm_vcpu *v)
1405 {
1406 unsigned long flags, this_tsc_khz;
1407 struct kvm_vcpu_arch *vcpu = &v->arch;
1408 struct kvm_arch *ka = &v->kvm->arch;
1409 void *shared_kaddr;
1410 s64 kernel_ns, max_kernel_ns;
1411 u64 tsc_timestamp, host_tsc;
1412 struct pvclock_vcpu_time_info *guest_hv_clock;
1413 u8 pvclock_flags;
1414 bool use_master_clock;
1415
1416 kernel_ns = 0;
1417 host_tsc = 0;
1418
1419 /* Keep irq disabled to prevent changes to the clock */
1420 local_irq_save(flags);
1421 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1422 if (unlikely(this_tsc_khz == 0)) {
1423 local_irq_restore(flags);
1424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1425 return 1;
1426 }
1427
1428 /*
1429 * If the host uses TSC clock, then passthrough TSC as stable
1430 * to the guest.
1431 */
1432 spin_lock(&ka->pvclock_gtod_sync_lock);
1433 use_master_clock = ka->use_master_clock;
1434 if (use_master_clock) {
1435 host_tsc = ka->master_cycle_now;
1436 kernel_ns = ka->master_kernel_ns;
1437 }
1438 spin_unlock(&ka->pvclock_gtod_sync_lock);
1439 if (!use_master_clock) {
1440 host_tsc = native_read_tsc();
1441 kernel_ns = get_kernel_ns();
1442 }
1443
1444 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1445
1446 /*
1447 * We may have to catch up the TSC to match elapsed wall clock
1448 * time for two reasons, even if kvmclock is used.
1449 * 1) CPU could have been running below the maximum TSC rate
1450 * 2) Broken TSC compensation resets the base at each VCPU
1451 * entry to avoid unknown leaps of TSC even when running
1452 * again on the same CPU. This may cause apparent elapsed
1453 * time to disappear, and the guest to stand still or run
1454 * very slowly.
1455 */
1456 if (vcpu->tsc_catchup) {
1457 u64 tsc = compute_guest_tsc(v, kernel_ns);
1458 if (tsc > tsc_timestamp) {
1459 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1460 tsc_timestamp = tsc;
1461 }
1462 }
1463
1464 local_irq_restore(flags);
1465
1466 if (!vcpu->time_page)
1467 return 0;
1468
1469 /*
1470 * Time as measured by the TSC may go backwards when resetting the base
1471 * tsc_timestamp. The reason for this is that the TSC resolution is
1472 * higher than the resolution of the other clock scales. Thus, many
1473 * possible measurments of the TSC correspond to one measurement of any
1474 * other clock, and so a spread of values is possible. This is not a
1475 * problem for the computation of the nanosecond clock; with TSC rates
1476 * around 1GHZ, there can only be a few cycles which correspond to one
1477 * nanosecond value, and any path through this code will inevitably
1478 * take longer than that. However, with the kernel_ns value itself,
1479 * the precision may be much lower, down to HZ granularity. If the
1480 * first sampling of TSC against kernel_ns ends in the low part of the
1481 * range, and the second in the high end of the range, we can get:
1482 *
1483 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1484 *
1485 * As the sampling errors potentially range in the thousands of cycles,
1486 * it is possible such a time value has already been observed by the
1487 * guest. To protect against this, we must compute the system time as
1488 * observed by the guest and ensure the new system time is greater.
1489 */
1490 max_kernel_ns = 0;
1491 if (vcpu->hv_clock.tsc_timestamp) {
1492 max_kernel_ns = vcpu->last_guest_tsc -
1493 vcpu->hv_clock.tsc_timestamp;
1494 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1495 vcpu->hv_clock.tsc_to_system_mul,
1496 vcpu->hv_clock.tsc_shift);
1497 max_kernel_ns += vcpu->last_kernel_ns;
1498 }
1499
1500 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1501 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1502 &vcpu->hv_clock.tsc_shift,
1503 &vcpu->hv_clock.tsc_to_system_mul);
1504 vcpu->hw_tsc_khz = this_tsc_khz;
1505 }
1506
1507 /* with a master <monotonic time, tsc value> tuple,
1508 * pvclock clock reads always increase at the (scaled) rate
1509 * of guest TSC - no need to deal with sampling errors.
1510 */
1511 if (!use_master_clock) {
1512 if (max_kernel_ns > kernel_ns)
1513 kernel_ns = max_kernel_ns;
1514 }
1515 /* With all the info we got, fill in the values */
1516 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1517 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1518 vcpu->last_kernel_ns = kernel_ns;
1519 vcpu->last_guest_tsc = tsc_timestamp;
1520
1521 /*
1522 * The interface expects us to write an even number signaling that the
1523 * update is finished. Since the guest won't see the intermediate
1524 * state, we just increase by 2 at the end.
1525 */
1526 vcpu->hv_clock.version += 2;
1527
1528 shared_kaddr = kmap_atomic(vcpu->time_page);
1529
1530 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1531
1532 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1533 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1534
1535 if (vcpu->pvclock_set_guest_stopped_request) {
1536 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1537 vcpu->pvclock_set_guest_stopped_request = false;
1538 }
1539
1540 /* If the host uses TSC clocksource, then it is stable */
1541 if (use_master_clock)
1542 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1543
1544 vcpu->hv_clock.flags = pvclock_flags;
1545
1546 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1547 sizeof(vcpu->hv_clock));
1548
1549 kunmap_atomic(shared_kaddr);
1550
1551 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1552 return 0;
1553 }
1554
1555 static bool msr_mtrr_valid(unsigned msr)
1556 {
1557 switch (msr) {
1558 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1559 case MSR_MTRRfix64K_00000:
1560 case MSR_MTRRfix16K_80000:
1561 case MSR_MTRRfix16K_A0000:
1562 case MSR_MTRRfix4K_C0000:
1563 case MSR_MTRRfix4K_C8000:
1564 case MSR_MTRRfix4K_D0000:
1565 case MSR_MTRRfix4K_D8000:
1566 case MSR_MTRRfix4K_E0000:
1567 case MSR_MTRRfix4K_E8000:
1568 case MSR_MTRRfix4K_F0000:
1569 case MSR_MTRRfix4K_F8000:
1570 case MSR_MTRRdefType:
1571 case MSR_IA32_CR_PAT:
1572 return true;
1573 case 0x2f8:
1574 return true;
1575 }
1576 return false;
1577 }
1578
1579 static bool valid_pat_type(unsigned t)
1580 {
1581 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1582 }
1583
1584 static bool valid_mtrr_type(unsigned t)
1585 {
1586 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1587 }
1588
1589 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1590 {
1591 int i;
1592
1593 if (!msr_mtrr_valid(msr))
1594 return false;
1595
1596 if (msr == MSR_IA32_CR_PAT) {
1597 for (i = 0; i < 8; i++)
1598 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1599 return false;
1600 return true;
1601 } else if (msr == MSR_MTRRdefType) {
1602 if (data & ~0xcff)
1603 return false;
1604 return valid_mtrr_type(data & 0xff);
1605 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1606 for (i = 0; i < 8 ; i++)
1607 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1608 return false;
1609 return true;
1610 }
1611
1612 /* variable MTRRs */
1613 return valid_mtrr_type(data & 0xff);
1614 }
1615
1616 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1617 {
1618 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1619
1620 if (!mtrr_valid(vcpu, msr, data))
1621 return 1;
1622
1623 if (msr == MSR_MTRRdefType) {
1624 vcpu->arch.mtrr_state.def_type = data;
1625 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1626 } else if (msr == MSR_MTRRfix64K_00000)
1627 p[0] = data;
1628 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1629 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1630 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1631 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1632 else if (msr == MSR_IA32_CR_PAT)
1633 vcpu->arch.pat = data;
1634 else { /* Variable MTRRs */
1635 int idx, is_mtrr_mask;
1636 u64 *pt;
1637
1638 idx = (msr - 0x200) / 2;
1639 is_mtrr_mask = msr - 0x200 - 2 * idx;
1640 if (!is_mtrr_mask)
1641 pt =
1642 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1643 else
1644 pt =
1645 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1646 *pt = data;
1647 }
1648
1649 kvm_mmu_reset_context(vcpu);
1650 return 0;
1651 }
1652
1653 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1654 {
1655 u64 mcg_cap = vcpu->arch.mcg_cap;
1656 unsigned bank_num = mcg_cap & 0xff;
1657
1658 switch (msr) {
1659 case MSR_IA32_MCG_STATUS:
1660 vcpu->arch.mcg_status = data;
1661 break;
1662 case MSR_IA32_MCG_CTL:
1663 if (!(mcg_cap & MCG_CTL_P))
1664 return 1;
1665 if (data != 0 && data != ~(u64)0)
1666 return -1;
1667 vcpu->arch.mcg_ctl = data;
1668 break;
1669 default:
1670 if (msr >= MSR_IA32_MC0_CTL &&
1671 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1672 u32 offset = msr - MSR_IA32_MC0_CTL;
1673 /* only 0 or all 1s can be written to IA32_MCi_CTL
1674 * some Linux kernels though clear bit 10 in bank 4 to
1675 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1676 * this to avoid an uncatched #GP in the guest
1677 */
1678 if ((offset & 0x3) == 0 &&
1679 data != 0 && (data | (1 << 10)) != ~(u64)0)
1680 return -1;
1681 vcpu->arch.mce_banks[offset] = data;
1682 break;
1683 }
1684 return 1;
1685 }
1686 return 0;
1687 }
1688
1689 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1690 {
1691 struct kvm *kvm = vcpu->kvm;
1692 int lm = is_long_mode(vcpu);
1693 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1694 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1695 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1696 : kvm->arch.xen_hvm_config.blob_size_32;
1697 u32 page_num = data & ~PAGE_MASK;
1698 u64 page_addr = data & PAGE_MASK;
1699 u8 *page;
1700 int r;
1701
1702 r = -E2BIG;
1703 if (page_num >= blob_size)
1704 goto out;
1705 r = -ENOMEM;
1706 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1707 if (IS_ERR(page)) {
1708 r = PTR_ERR(page);
1709 goto out;
1710 }
1711 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1712 goto out_free;
1713 r = 0;
1714 out_free:
1715 kfree(page);
1716 out:
1717 return r;
1718 }
1719
1720 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1721 {
1722 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1723 }
1724
1725 static bool kvm_hv_msr_partition_wide(u32 msr)
1726 {
1727 bool r = false;
1728 switch (msr) {
1729 case HV_X64_MSR_GUEST_OS_ID:
1730 case HV_X64_MSR_HYPERCALL:
1731 r = true;
1732 break;
1733 }
1734
1735 return r;
1736 }
1737
1738 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1739 {
1740 struct kvm *kvm = vcpu->kvm;
1741
1742 switch (msr) {
1743 case HV_X64_MSR_GUEST_OS_ID:
1744 kvm->arch.hv_guest_os_id = data;
1745 /* setting guest os id to zero disables hypercall page */
1746 if (!kvm->arch.hv_guest_os_id)
1747 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1748 break;
1749 case HV_X64_MSR_HYPERCALL: {
1750 u64 gfn;
1751 unsigned long addr;
1752 u8 instructions[4];
1753
1754 /* if guest os id is not set hypercall should remain disabled */
1755 if (!kvm->arch.hv_guest_os_id)
1756 break;
1757 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1758 kvm->arch.hv_hypercall = data;
1759 break;
1760 }
1761 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1762 addr = gfn_to_hva(kvm, gfn);
1763 if (kvm_is_error_hva(addr))
1764 return 1;
1765 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1766 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1767 if (__copy_to_user((void __user *)addr, instructions, 4))
1768 return 1;
1769 kvm->arch.hv_hypercall = data;
1770 break;
1771 }
1772 default:
1773 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1774 "data 0x%llx\n", msr, data);
1775 return 1;
1776 }
1777 return 0;
1778 }
1779
1780 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1781 {
1782 switch (msr) {
1783 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1784 unsigned long addr;
1785
1786 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1787 vcpu->arch.hv_vapic = data;
1788 break;
1789 }
1790 addr = gfn_to_hva(vcpu->kvm, data >>
1791 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1792 if (kvm_is_error_hva(addr))
1793 return 1;
1794 if (__clear_user((void __user *)addr, PAGE_SIZE))
1795 return 1;
1796 vcpu->arch.hv_vapic = data;
1797 break;
1798 }
1799 case HV_X64_MSR_EOI:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1801 case HV_X64_MSR_ICR:
1802 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1803 case HV_X64_MSR_TPR:
1804 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1805 default:
1806 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1807 "data 0x%llx\n", msr, data);
1808 return 1;
1809 }
1810
1811 return 0;
1812 }
1813
1814 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1815 {
1816 gpa_t gpa = data & ~0x3f;
1817
1818 /* Bits 2:5 are reserved, Should be zero */
1819 if (data & 0x3c)
1820 return 1;
1821
1822 vcpu->arch.apf.msr_val = data;
1823
1824 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1825 kvm_clear_async_pf_completion_queue(vcpu);
1826 kvm_async_pf_hash_reset(vcpu);
1827 return 0;
1828 }
1829
1830 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1831 return 1;
1832
1833 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1834 kvm_async_pf_wakeup_all(vcpu);
1835 return 0;
1836 }
1837
1838 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1839 {
1840 if (vcpu->arch.time_page) {
1841 kvm_release_page_dirty(vcpu->arch.time_page);
1842 vcpu->arch.time_page = NULL;
1843 }
1844 }
1845
1846 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1847 {
1848 u64 delta;
1849
1850 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1851 return;
1852
1853 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1854 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1855 vcpu->arch.st.accum_steal = delta;
1856 }
1857
1858 static void record_steal_time(struct kvm_vcpu *vcpu)
1859 {
1860 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1861 return;
1862
1863 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1864 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1865 return;
1866
1867 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1868 vcpu->arch.st.steal.version += 2;
1869 vcpu->arch.st.accum_steal = 0;
1870
1871 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1872 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1873 }
1874
1875 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1876 {
1877 bool pr = false;
1878 u32 msr = msr_info->index;
1879 u64 data = msr_info->data;
1880
1881 switch (msr) {
1882 case MSR_AMD64_NB_CFG:
1883 case MSR_IA32_UCODE_REV:
1884 case MSR_IA32_UCODE_WRITE:
1885 case MSR_VM_HSAVE_PA:
1886 case MSR_AMD64_PATCH_LOADER:
1887 case MSR_AMD64_BU_CFG2:
1888 break;
1889
1890 case MSR_EFER:
1891 return set_efer(vcpu, data);
1892 case MSR_K7_HWCR:
1893 data &= ~(u64)0x40; /* ignore flush filter disable */
1894 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1895 data &= ~(u64)0x8; /* ignore TLB cache disable */
1896 if (data != 0) {
1897 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1898 data);
1899 return 1;
1900 }
1901 break;
1902 case MSR_FAM10H_MMIO_CONF_BASE:
1903 if (data != 0) {
1904 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1905 "0x%llx\n", data);
1906 return 1;
1907 }
1908 break;
1909 case MSR_IA32_DEBUGCTLMSR:
1910 if (!data) {
1911 /* We support the non-activated case already */
1912 break;
1913 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1914 /* Values other than LBR and BTF are vendor-specific,
1915 thus reserved and should throw a #GP */
1916 return 1;
1917 }
1918 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1919 __func__, data);
1920 break;
1921 case 0x200 ... 0x2ff:
1922 return set_msr_mtrr(vcpu, msr, data);
1923 case MSR_IA32_APICBASE:
1924 kvm_set_apic_base(vcpu, data);
1925 break;
1926 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1927 return kvm_x2apic_msr_write(vcpu, msr, data);
1928 case MSR_IA32_TSCDEADLINE:
1929 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1930 break;
1931 case MSR_IA32_TSC_ADJUST:
1932 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1933 if (!msr_info->host_initiated) {
1934 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1935 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1936 }
1937 vcpu->arch.ia32_tsc_adjust_msr = data;
1938 }
1939 break;
1940 case MSR_IA32_MISC_ENABLE:
1941 vcpu->arch.ia32_misc_enable_msr = data;
1942 break;
1943 case MSR_KVM_WALL_CLOCK_NEW:
1944 case MSR_KVM_WALL_CLOCK:
1945 vcpu->kvm->arch.wall_clock = data;
1946 kvm_write_wall_clock(vcpu->kvm, data);
1947 break;
1948 case MSR_KVM_SYSTEM_TIME_NEW:
1949 case MSR_KVM_SYSTEM_TIME: {
1950 kvmclock_reset(vcpu);
1951
1952 vcpu->arch.time = data;
1953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1954
1955 /* we verify if the enable bit is set... */
1956 if (!(data & 1))
1957 break;
1958
1959 /* ...but clean it before doing the actual write */
1960 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1961
1962 vcpu->arch.time_page =
1963 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1964
1965 if (is_error_page(vcpu->arch.time_page))
1966 vcpu->arch.time_page = NULL;
1967
1968 break;
1969 }
1970 case MSR_KVM_ASYNC_PF_EN:
1971 if (kvm_pv_enable_async_pf(vcpu, data))
1972 return 1;
1973 break;
1974 case MSR_KVM_STEAL_TIME:
1975
1976 if (unlikely(!sched_info_on()))
1977 return 1;
1978
1979 if (data & KVM_STEAL_RESERVED_MASK)
1980 return 1;
1981
1982 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1983 data & KVM_STEAL_VALID_BITS))
1984 return 1;
1985
1986 vcpu->arch.st.msr_val = data;
1987
1988 if (!(data & KVM_MSR_ENABLED))
1989 break;
1990
1991 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1992
1993 preempt_disable();
1994 accumulate_steal_time(vcpu);
1995 preempt_enable();
1996
1997 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1998
1999 break;
2000 case MSR_KVM_PV_EOI_EN:
2001 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2002 return 1;
2003 break;
2004
2005 case MSR_IA32_MCG_CTL:
2006 case MSR_IA32_MCG_STATUS:
2007 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2008 return set_msr_mce(vcpu, msr, data);
2009
2010 /* Performance counters are not protected by a CPUID bit,
2011 * so we should check all of them in the generic path for the sake of
2012 * cross vendor migration.
2013 * Writing a zero into the event select MSRs disables them,
2014 * which we perfectly emulate ;-). Any other value should be at least
2015 * reported, some guests depend on them.
2016 */
2017 case MSR_K7_EVNTSEL0:
2018 case MSR_K7_EVNTSEL1:
2019 case MSR_K7_EVNTSEL2:
2020 case MSR_K7_EVNTSEL3:
2021 if (data != 0)
2022 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2023 "0x%x data 0x%llx\n", msr, data);
2024 break;
2025 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2026 * so we ignore writes to make it happy.
2027 */
2028 case MSR_K7_PERFCTR0:
2029 case MSR_K7_PERFCTR1:
2030 case MSR_K7_PERFCTR2:
2031 case MSR_K7_PERFCTR3:
2032 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2033 "0x%x data 0x%llx\n", msr, data);
2034 break;
2035 case MSR_P6_PERFCTR0:
2036 case MSR_P6_PERFCTR1:
2037 pr = true;
2038 case MSR_P6_EVNTSEL0:
2039 case MSR_P6_EVNTSEL1:
2040 if (kvm_pmu_msr(vcpu, msr))
2041 return kvm_pmu_set_msr(vcpu, msr, data);
2042
2043 if (pr || data != 0)
2044 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2045 "0x%x data 0x%llx\n", msr, data);
2046 break;
2047 case MSR_K7_CLK_CTL:
2048 /*
2049 * Ignore all writes to this no longer documented MSR.
2050 * Writes are only relevant for old K7 processors,
2051 * all pre-dating SVM, but a recommended workaround from
2052 * AMD for these chips. It is possible to specify the
2053 * affected processor models on the command line, hence
2054 * the need to ignore the workaround.
2055 */
2056 break;
2057 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2058 if (kvm_hv_msr_partition_wide(msr)) {
2059 int r;
2060 mutex_lock(&vcpu->kvm->lock);
2061 r = set_msr_hyperv_pw(vcpu, msr, data);
2062 mutex_unlock(&vcpu->kvm->lock);
2063 return r;
2064 } else
2065 return set_msr_hyperv(vcpu, msr, data);
2066 break;
2067 case MSR_IA32_BBL_CR_CTL3:
2068 /* Drop writes to this legacy MSR -- see rdmsr
2069 * counterpart for further detail.
2070 */
2071 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2072 break;
2073 case MSR_AMD64_OSVW_ID_LENGTH:
2074 if (!guest_cpuid_has_osvw(vcpu))
2075 return 1;
2076 vcpu->arch.osvw.length = data;
2077 break;
2078 case MSR_AMD64_OSVW_STATUS:
2079 if (!guest_cpuid_has_osvw(vcpu))
2080 return 1;
2081 vcpu->arch.osvw.status = data;
2082 break;
2083 default:
2084 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2085 return xen_hvm_config(vcpu, data);
2086 if (kvm_pmu_msr(vcpu, msr))
2087 return kvm_pmu_set_msr(vcpu, msr, data);
2088 if (!ignore_msrs) {
2089 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2090 msr, data);
2091 return 1;
2092 } else {
2093 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2094 msr, data);
2095 break;
2096 }
2097 }
2098 return 0;
2099 }
2100 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2101
2102
2103 /*
2104 * Reads an msr value (of 'msr_index') into 'pdata'.
2105 * Returns 0 on success, non-0 otherwise.
2106 * Assumes vcpu_load() was already called.
2107 */
2108 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2109 {
2110 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2111 }
2112
2113 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2114 {
2115 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2116
2117 if (!msr_mtrr_valid(msr))
2118 return 1;
2119
2120 if (msr == MSR_MTRRdefType)
2121 *pdata = vcpu->arch.mtrr_state.def_type +
2122 (vcpu->arch.mtrr_state.enabled << 10);
2123 else if (msr == MSR_MTRRfix64K_00000)
2124 *pdata = p[0];
2125 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2126 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2127 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2128 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2129 else if (msr == MSR_IA32_CR_PAT)
2130 *pdata = vcpu->arch.pat;
2131 else { /* Variable MTRRs */
2132 int idx, is_mtrr_mask;
2133 u64 *pt;
2134
2135 idx = (msr - 0x200) / 2;
2136 is_mtrr_mask = msr - 0x200 - 2 * idx;
2137 if (!is_mtrr_mask)
2138 pt =
2139 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2140 else
2141 pt =
2142 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2143 *pdata = *pt;
2144 }
2145
2146 return 0;
2147 }
2148
2149 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2150 {
2151 u64 data;
2152 u64 mcg_cap = vcpu->arch.mcg_cap;
2153 unsigned bank_num = mcg_cap & 0xff;
2154
2155 switch (msr) {
2156 case MSR_IA32_P5_MC_ADDR:
2157 case MSR_IA32_P5_MC_TYPE:
2158 data = 0;
2159 break;
2160 case MSR_IA32_MCG_CAP:
2161 data = vcpu->arch.mcg_cap;
2162 break;
2163 case MSR_IA32_MCG_CTL:
2164 if (!(mcg_cap & MCG_CTL_P))
2165 return 1;
2166 data = vcpu->arch.mcg_ctl;
2167 break;
2168 case MSR_IA32_MCG_STATUS:
2169 data = vcpu->arch.mcg_status;
2170 break;
2171 default:
2172 if (msr >= MSR_IA32_MC0_CTL &&
2173 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2174 u32 offset = msr - MSR_IA32_MC0_CTL;
2175 data = vcpu->arch.mce_banks[offset];
2176 break;
2177 }
2178 return 1;
2179 }
2180 *pdata = data;
2181 return 0;
2182 }
2183
2184 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2185 {
2186 u64 data = 0;
2187 struct kvm *kvm = vcpu->kvm;
2188
2189 switch (msr) {
2190 case HV_X64_MSR_GUEST_OS_ID:
2191 data = kvm->arch.hv_guest_os_id;
2192 break;
2193 case HV_X64_MSR_HYPERCALL:
2194 data = kvm->arch.hv_hypercall;
2195 break;
2196 default:
2197 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2198 return 1;
2199 }
2200
2201 *pdata = data;
2202 return 0;
2203 }
2204
2205 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2206 {
2207 u64 data = 0;
2208
2209 switch (msr) {
2210 case HV_X64_MSR_VP_INDEX: {
2211 int r;
2212 struct kvm_vcpu *v;
2213 kvm_for_each_vcpu(r, v, vcpu->kvm)
2214 if (v == vcpu)
2215 data = r;
2216 break;
2217 }
2218 case HV_X64_MSR_EOI:
2219 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2220 case HV_X64_MSR_ICR:
2221 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2222 case HV_X64_MSR_TPR:
2223 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2224 case HV_X64_MSR_APIC_ASSIST_PAGE:
2225 data = vcpu->arch.hv_vapic;
2226 break;
2227 default:
2228 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2229 return 1;
2230 }
2231 *pdata = data;
2232 return 0;
2233 }
2234
2235 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2236 {
2237 u64 data;
2238
2239 switch (msr) {
2240 case MSR_IA32_PLATFORM_ID:
2241 case MSR_IA32_EBL_CR_POWERON:
2242 case MSR_IA32_DEBUGCTLMSR:
2243 case MSR_IA32_LASTBRANCHFROMIP:
2244 case MSR_IA32_LASTBRANCHTOIP:
2245 case MSR_IA32_LASTINTFROMIP:
2246 case MSR_IA32_LASTINTTOIP:
2247 case MSR_K8_SYSCFG:
2248 case MSR_K7_HWCR:
2249 case MSR_VM_HSAVE_PA:
2250 case MSR_K7_EVNTSEL0:
2251 case MSR_K7_PERFCTR0:
2252 case MSR_K8_INT_PENDING_MSG:
2253 case MSR_AMD64_NB_CFG:
2254 case MSR_FAM10H_MMIO_CONF_BASE:
2255 case MSR_AMD64_BU_CFG2:
2256 data = 0;
2257 break;
2258 case MSR_P6_PERFCTR0:
2259 case MSR_P6_PERFCTR1:
2260 case MSR_P6_EVNTSEL0:
2261 case MSR_P6_EVNTSEL1:
2262 if (kvm_pmu_msr(vcpu, msr))
2263 return kvm_pmu_get_msr(vcpu, msr, pdata);
2264 data = 0;
2265 break;
2266 case MSR_IA32_UCODE_REV:
2267 data = 0x100000000ULL;
2268 break;
2269 case MSR_MTRRcap:
2270 data = 0x500 | KVM_NR_VAR_MTRR;
2271 break;
2272 case 0x200 ... 0x2ff:
2273 return get_msr_mtrr(vcpu, msr, pdata);
2274 case 0xcd: /* fsb frequency */
2275 data = 3;
2276 break;
2277 /*
2278 * MSR_EBC_FREQUENCY_ID
2279 * Conservative value valid for even the basic CPU models.
2280 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2281 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2282 * and 266MHz for model 3, or 4. Set Core Clock
2283 * Frequency to System Bus Frequency Ratio to 1 (bits
2284 * 31:24) even though these are only valid for CPU
2285 * models > 2, however guests may end up dividing or
2286 * multiplying by zero otherwise.
2287 */
2288 case MSR_EBC_FREQUENCY_ID:
2289 data = 1 << 24;
2290 break;
2291 case MSR_IA32_APICBASE:
2292 data = kvm_get_apic_base(vcpu);
2293 break;
2294 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2295 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2296 break;
2297 case MSR_IA32_TSCDEADLINE:
2298 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2299 break;
2300 case MSR_IA32_TSC_ADJUST:
2301 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2302 break;
2303 case MSR_IA32_MISC_ENABLE:
2304 data = vcpu->arch.ia32_misc_enable_msr;
2305 break;
2306 case MSR_IA32_PERF_STATUS:
2307 /* TSC increment by tick */
2308 data = 1000ULL;
2309 /* CPU multiplier */
2310 data |= (((uint64_t)4ULL) << 40);
2311 break;
2312 case MSR_EFER:
2313 data = vcpu->arch.efer;
2314 break;
2315 case MSR_KVM_WALL_CLOCK:
2316 case MSR_KVM_WALL_CLOCK_NEW:
2317 data = vcpu->kvm->arch.wall_clock;
2318 break;
2319 case MSR_KVM_SYSTEM_TIME:
2320 case MSR_KVM_SYSTEM_TIME_NEW:
2321 data = vcpu->arch.time;
2322 break;
2323 case MSR_KVM_ASYNC_PF_EN:
2324 data = vcpu->arch.apf.msr_val;
2325 break;
2326 case MSR_KVM_STEAL_TIME:
2327 data = vcpu->arch.st.msr_val;
2328 break;
2329 case MSR_KVM_PV_EOI_EN:
2330 data = vcpu->arch.pv_eoi.msr_val;
2331 break;
2332 case MSR_IA32_P5_MC_ADDR:
2333 case MSR_IA32_P5_MC_TYPE:
2334 case MSR_IA32_MCG_CAP:
2335 case MSR_IA32_MCG_CTL:
2336 case MSR_IA32_MCG_STATUS:
2337 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2338 return get_msr_mce(vcpu, msr, pdata);
2339 case MSR_K7_CLK_CTL:
2340 /*
2341 * Provide expected ramp-up count for K7. All other
2342 * are set to zero, indicating minimum divisors for
2343 * every field.
2344 *
2345 * This prevents guest kernels on AMD host with CPU
2346 * type 6, model 8 and higher from exploding due to
2347 * the rdmsr failing.
2348 */
2349 data = 0x20000000;
2350 break;
2351 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2352 if (kvm_hv_msr_partition_wide(msr)) {
2353 int r;
2354 mutex_lock(&vcpu->kvm->lock);
2355 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2356 mutex_unlock(&vcpu->kvm->lock);
2357 return r;
2358 } else
2359 return get_msr_hyperv(vcpu, msr, pdata);
2360 break;
2361 case MSR_IA32_BBL_CR_CTL3:
2362 /* This legacy MSR exists but isn't fully documented in current
2363 * silicon. It is however accessed by winxp in very narrow
2364 * scenarios where it sets bit #19, itself documented as
2365 * a "reserved" bit. Best effort attempt to source coherent
2366 * read data here should the balance of the register be
2367 * interpreted by the guest:
2368 *
2369 * L2 cache control register 3: 64GB range, 256KB size,
2370 * enabled, latency 0x1, configured
2371 */
2372 data = 0xbe702111;
2373 break;
2374 case MSR_AMD64_OSVW_ID_LENGTH:
2375 if (!guest_cpuid_has_osvw(vcpu))
2376 return 1;
2377 data = vcpu->arch.osvw.length;
2378 break;
2379 case MSR_AMD64_OSVW_STATUS:
2380 if (!guest_cpuid_has_osvw(vcpu))
2381 return 1;
2382 data = vcpu->arch.osvw.status;
2383 break;
2384 default:
2385 if (kvm_pmu_msr(vcpu, msr))
2386 return kvm_pmu_get_msr(vcpu, msr, pdata);
2387 if (!ignore_msrs) {
2388 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2389 return 1;
2390 } else {
2391 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2392 data = 0;
2393 }
2394 break;
2395 }
2396 *pdata = data;
2397 return 0;
2398 }
2399 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2400
2401 /*
2402 * Read or write a bunch of msrs. All parameters are kernel addresses.
2403 *
2404 * @return number of msrs set successfully.
2405 */
2406 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2407 struct kvm_msr_entry *entries,
2408 int (*do_msr)(struct kvm_vcpu *vcpu,
2409 unsigned index, u64 *data))
2410 {
2411 int i, idx;
2412
2413 idx = srcu_read_lock(&vcpu->kvm->srcu);
2414 for (i = 0; i < msrs->nmsrs; ++i)
2415 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2416 break;
2417 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2418
2419 return i;
2420 }
2421
2422 /*
2423 * Read or write a bunch of msrs. Parameters are user addresses.
2424 *
2425 * @return number of msrs set successfully.
2426 */
2427 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2428 int (*do_msr)(struct kvm_vcpu *vcpu,
2429 unsigned index, u64 *data),
2430 int writeback)
2431 {
2432 struct kvm_msrs msrs;
2433 struct kvm_msr_entry *entries;
2434 int r, n;
2435 unsigned size;
2436
2437 r = -EFAULT;
2438 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2439 goto out;
2440
2441 r = -E2BIG;
2442 if (msrs.nmsrs >= MAX_IO_MSRS)
2443 goto out;
2444
2445 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2446 entries = memdup_user(user_msrs->entries, size);
2447 if (IS_ERR(entries)) {
2448 r = PTR_ERR(entries);
2449 goto out;
2450 }
2451
2452 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2453 if (r < 0)
2454 goto out_free;
2455
2456 r = -EFAULT;
2457 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2458 goto out_free;
2459
2460 r = n;
2461
2462 out_free:
2463 kfree(entries);
2464 out:
2465 return r;
2466 }
2467
2468 int kvm_dev_ioctl_check_extension(long ext)
2469 {
2470 int r;
2471
2472 switch (ext) {
2473 case KVM_CAP_IRQCHIP:
2474 case KVM_CAP_HLT:
2475 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2476 case KVM_CAP_SET_TSS_ADDR:
2477 case KVM_CAP_EXT_CPUID:
2478 case KVM_CAP_CLOCKSOURCE:
2479 case KVM_CAP_PIT:
2480 case KVM_CAP_NOP_IO_DELAY:
2481 case KVM_CAP_MP_STATE:
2482 case KVM_CAP_SYNC_MMU:
2483 case KVM_CAP_USER_NMI:
2484 case KVM_CAP_REINJECT_CONTROL:
2485 case KVM_CAP_IRQ_INJECT_STATUS:
2486 case KVM_CAP_ASSIGN_DEV_IRQ:
2487 case KVM_CAP_IRQFD:
2488 case KVM_CAP_IOEVENTFD:
2489 case KVM_CAP_PIT2:
2490 case KVM_CAP_PIT_STATE2:
2491 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2492 case KVM_CAP_XEN_HVM:
2493 case KVM_CAP_ADJUST_CLOCK:
2494 case KVM_CAP_VCPU_EVENTS:
2495 case KVM_CAP_HYPERV:
2496 case KVM_CAP_HYPERV_VAPIC:
2497 case KVM_CAP_HYPERV_SPIN:
2498 case KVM_CAP_PCI_SEGMENT:
2499 case KVM_CAP_DEBUGREGS:
2500 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2501 case KVM_CAP_XSAVE:
2502 case KVM_CAP_ASYNC_PF:
2503 case KVM_CAP_GET_TSC_KHZ:
2504 case KVM_CAP_PCI_2_3:
2505 case KVM_CAP_KVMCLOCK_CTRL:
2506 case KVM_CAP_READONLY_MEM:
2507 case KVM_CAP_IRQFD_RESAMPLE:
2508 r = 1;
2509 break;
2510 case KVM_CAP_COALESCED_MMIO:
2511 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2512 break;
2513 case KVM_CAP_VAPIC:
2514 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2515 break;
2516 case KVM_CAP_NR_VCPUS:
2517 r = KVM_SOFT_MAX_VCPUS;
2518 break;
2519 case KVM_CAP_MAX_VCPUS:
2520 r = KVM_MAX_VCPUS;
2521 break;
2522 case KVM_CAP_NR_MEMSLOTS:
2523 r = KVM_USER_MEM_SLOTS;
2524 break;
2525 case KVM_CAP_PV_MMU: /* obsolete */
2526 r = 0;
2527 break;
2528 case KVM_CAP_IOMMU:
2529 r = iommu_present(&pci_bus_type);
2530 break;
2531 case KVM_CAP_MCE:
2532 r = KVM_MAX_MCE_BANKS;
2533 break;
2534 case KVM_CAP_XCRS:
2535 r = cpu_has_xsave;
2536 break;
2537 case KVM_CAP_TSC_CONTROL:
2538 r = kvm_has_tsc_control;
2539 break;
2540 case KVM_CAP_TSC_DEADLINE_TIMER:
2541 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2542 break;
2543 default:
2544 r = 0;
2545 break;
2546 }
2547 return r;
2548
2549 }
2550
2551 long kvm_arch_dev_ioctl(struct file *filp,
2552 unsigned int ioctl, unsigned long arg)
2553 {
2554 void __user *argp = (void __user *)arg;
2555 long r;
2556
2557 switch (ioctl) {
2558 case KVM_GET_MSR_INDEX_LIST: {
2559 struct kvm_msr_list __user *user_msr_list = argp;
2560 struct kvm_msr_list msr_list;
2561 unsigned n;
2562
2563 r = -EFAULT;
2564 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2565 goto out;
2566 n = msr_list.nmsrs;
2567 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2568 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2569 goto out;
2570 r = -E2BIG;
2571 if (n < msr_list.nmsrs)
2572 goto out;
2573 r = -EFAULT;
2574 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2575 num_msrs_to_save * sizeof(u32)))
2576 goto out;
2577 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2578 &emulated_msrs,
2579 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2580 goto out;
2581 r = 0;
2582 break;
2583 }
2584 case KVM_GET_SUPPORTED_CPUID: {
2585 struct kvm_cpuid2 __user *cpuid_arg = argp;
2586 struct kvm_cpuid2 cpuid;
2587
2588 r = -EFAULT;
2589 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2590 goto out;
2591 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2592 cpuid_arg->entries);
2593 if (r)
2594 goto out;
2595
2596 r = -EFAULT;
2597 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2598 goto out;
2599 r = 0;
2600 break;
2601 }
2602 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2603 u64 mce_cap;
2604
2605 mce_cap = KVM_MCE_CAP_SUPPORTED;
2606 r = -EFAULT;
2607 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2608 goto out;
2609 r = 0;
2610 break;
2611 }
2612 default:
2613 r = -EINVAL;
2614 }
2615 out:
2616 return r;
2617 }
2618
2619 static void wbinvd_ipi(void *garbage)
2620 {
2621 wbinvd();
2622 }
2623
2624 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2625 {
2626 return vcpu->kvm->arch.iommu_domain &&
2627 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2628 }
2629
2630 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2631 {
2632 /* Address WBINVD may be executed by guest */
2633 if (need_emulate_wbinvd(vcpu)) {
2634 if (kvm_x86_ops->has_wbinvd_exit())
2635 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2636 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2637 smp_call_function_single(vcpu->cpu,
2638 wbinvd_ipi, NULL, 1);
2639 }
2640
2641 kvm_x86_ops->vcpu_load(vcpu, cpu);
2642
2643 /* Apply any externally detected TSC adjustments (due to suspend) */
2644 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2645 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2646 vcpu->arch.tsc_offset_adjustment = 0;
2647 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2648 }
2649
2650 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2651 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2652 native_read_tsc() - vcpu->arch.last_host_tsc;
2653 if (tsc_delta < 0)
2654 mark_tsc_unstable("KVM discovered backwards TSC");
2655 if (check_tsc_unstable()) {
2656 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2657 vcpu->arch.last_guest_tsc);
2658 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2659 vcpu->arch.tsc_catchup = 1;
2660 }
2661 /*
2662 * On a host with synchronized TSC, there is no need to update
2663 * kvmclock on vcpu->cpu migration
2664 */
2665 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2666 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2667 if (vcpu->cpu != cpu)
2668 kvm_migrate_timers(vcpu);
2669 vcpu->cpu = cpu;
2670 }
2671
2672 accumulate_steal_time(vcpu);
2673 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2674 }
2675
2676 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2677 {
2678 kvm_x86_ops->vcpu_put(vcpu);
2679 kvm_put_guest_fpu(vcpu);
2680 vcpu->arch.last_host_tsc = native_read_tsc();
2681 }
2682
2683 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2684 struct kvm_lapic_state *s)
2685 {
2686 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2687
2688 return 0;
2689 }
2690
2691 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2692 struct kvm_lapic_state *s)
2693 {
2694 kvm_apic_post_state_restore(vcpu, s);
2695 update_cr8_intercept(vcpu);
2696
2697 return 0;
2698 }
2699
2700 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2701 struct kvm_interrupt *irq)
2702 {
2703 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
2704 return -EINVAL;
2705 if (irqchip_in_kernel(vcpu->kvm))
2706 return -ENXIO;
2707
2708 kvm_queue_interrupt(vcpu, irq->irq, false);
2709 kvm_make_request(KVM_REQ_EVENT, vcpu);
2710
2711 return 0;
2712 }
2713
2714 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2715 {
2716 kvm_inject_nmi(vcpu);
2717
2718 return 0;
2719 }
2720
2721 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2722 struct kvm_tpr_access_ctl *tac)
2723 {
2724 if (tac->flags)
2725 return -EINVAL;
2726 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2727 return 0;
2728 }
2729
2730 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2731 u64 mcg_cap)
2732 {
2733 int r;
2734 unsigned bank_num = mcg_cap & 0xff, bank;
2735
2736 r = -EINVAL;
2737 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2738 goto out;
2739 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2740 goto out;
2741 r = 0;
2742 vcpu->arch.mcg_cap = mcg_cap;
2743 /* Init IA32_MCG_CTL to all 1s */
2744 if (mcg_cap & MCG_CTL_P)
2745 vcpu->arch.mcg_ctl = ~(u64)0;
2746 /* Init IA32_MCi_CTL to all 1s */
2747 for (bank = 0; bank < bank_num; bank++)
2748 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2749 out:
2750 return r;
2751 }
2752
2753 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2754 struct kvm_x86_mce *mce)
2755 {
2756 u64 mcg_cap = vcpu->arch.mcg_cap;
2757 unsigned bank_num = mcg_cap & 0xff;
2758 u64 *banks = vcpu->arch.mce_banks;
2759
2760 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2761 return -EINVAL;
2762 /*
2763 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2764 * reporting is disabled
2765 */
2766 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2767 vcpu->arch.mcg_ctl != ~(u64)0)
2768 return 0;
2769 banks += 4 * mce->bank;
2770 /*
2771 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2772 * reporting is disabled for the bank
2773 */
2774 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2775 return 0;
2776 if (mce->status & MCI_STATUS_UC) {
2777 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2778 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2779 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2780 return 0;
2781 }
2782 if (banks[1] & MCI_STATUS_VAL)
2783 mce->status |= MCI_STATUS_OVER;
2784 banks[2] = mce->addr;
2785 banks[3] = mce->misc;
2786 vcpu->arch.mcg_status = mce->mcg_status;
2787 banks[1] = mce->status;
2788 kvm_queue_exception(vcpu, MC_VECTOR);
2789 } else if (!(banks[1] & MCI_STATUS_VAL)
2790 || !(banks[1] & MCI_STATUS_UC)) {
2791 if (banks[1] & MCI_STATUS_VAL)
2792 mce->status |= MCI_STATUS_OVER;
2793 banks[2] = mce->addr;
2794 banks[3] = mce->misc;
2795 banks[1] = mce->status;
2796 } else
2797 banks[1] |= MCI_STATUS_OVER;
2798 return 0;
2799 }
2800
2801 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2802 struct kvm_vcpu_events *events)
2803 {
2804 process_nmi(vcpu);
2805 events->exception.injected =
2806 vcpu->arch.exception.pending &&
2807 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2808 events->exception.nr = vcpu->arch.exception.nr;
2809 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2810 events->exception.pad = 0;
2811 events->exception.error_code = vcpu->arch.exception.error_code;
2812
2813 events->interrupt.injected =
2814 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2815 events->interrupt.nr = vcpu->arch.interrupt.nr;
2816 events->interrupt.soft = 0;
2817 events->interrupt.shadow =
2818 kvm_x86_ops->get_interrupt_shadow(vcpu,
2819 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2820
2821 events->nmi.injected = vcpu->arch.nmi_injected;
2822 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2823 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2824 events->nmi.pad = 0;
2825
2826 events->sipi_vector = vcpu->arch.sipi_vector;
2827
2828 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2829 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2830 | KVM_VCPUEVENT_VALID_SHADOW);
2831 memset(&events->reserved, 0, sizeof(events->reserved));
2832 }
2833
2834 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2835 struct kvm_vcpu_events *events)
2836 {
2837 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2838 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2839 | KVM_VCPUEVENT_VALID_SHADOW))
2840 return -EINVAL;
2841
2842 process_nmi(vcpu);
2843 vcpu->arch.exception.pending = events->exception.injected;
2844 vcpu->arch.exception.nr = events->exception.nr;
2845 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2846 vcpu->arch.exception.error_code = events->exception.error_code;
2847
2848 vcpu->arch.interrupt.pending = events->interrupt.injected;
2849 vcpu->arch.interrupt.nr = events->interrupt.nr;
2850 vcpu->arch.interrupt.soft = events->interrupt.soft;
2851 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2852 kvm_x86_ops->set_interrupt_shadow(vcpu,
2853 events->interrupt.shadow);
2854
2855 vcpu->arch.nmi_injected = events->nmi.injected;
2856 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2857 vcpu->arch.nmi_pending = events->nmi.pending;
2858 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2859
2860 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2861 vcpu->arch.sipi_vector = events->sipi_vector;
2862
2863 kvm_make_request(KVM_REQ_EVENT, vcpu);
2864
2865 return 0;
2866 }
2867
2868 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2869 struct kvm_debugregs *dbgregs)
2870 {
2871 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2872 dbgregs->dr6 = vcpu->arch.dr6;
2873 dbgregs->dr7 = vcpu->arch.dr7;
2874 dbgregs->flags = 0;
2875 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2876 }
2877
2878 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2879 struct kvm_debugregs *dbgregs)
2880 {
2881 if (dbgregs->flags)
2882 return -EINVAL;
2883
2884 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2885 vcpu->arch.dr6 = dbgregs->dr6;
2886 vcpu->arch.dr7 = dbgregs->dr7;
2887
2888 return 0;
2889 }
2890
2891 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2892 struct kvm_xsave *guest_xsave)
2893 {
2894 if (cpu_has_xsave)
2895 memcpy(guest_xsave->region,
2896 &vcpu->arch.guest_fpu.state->xsave,
2897 xstate_size);
2898 else {
2899 memcpy(guest_xsave->region,
2900 &vcpu->arch.guest_fpu.state->fxsave,
2901 sizeof(struct i387_fxsave_struct));
2902 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2903 XSTATE_FPSSE;
2904 }
2905 }
2906
2907 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2908 struct kvm_xsave *guest_xsave)
2909 {
2910 u64 xstate_bv =
2911 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2912
2913 if (cpu_has_xsave)
2914 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2915 guest_xsave->region, xstate_size);
2916 else {
2917 if (xstate_bv & ~XSTATE_FPSSE)
2918 return -EINVAL;
2919 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2920 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2921 }
2922 return 0;
2923 }
2924
2925 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2926 struct kvm_xcrs *guest_xcrs)
2927 {
2928 if (!cpu_has_xsave) {
2929 guest_xcrs->nr_xcrs = 0;
2930 return;
2931 }
2932
2933 guest_xcrs->nr_xcrs = 1;
2934 guest_xcrs->flags = 0;
2935 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2936 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2937 }
2938
2939 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2940 struct kvm_xcrs *guest_xcrs)
2941 {
2942 int i, r = 0;
2943
2944 if (!cpu_has_xsave)
2945 return -EINVAL;
2946
2947 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2948 return -EINVAL;
2949
2950 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2951 /* Only support XCR0 currently */
2952 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2953 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2954 guest_xcrs->xcrs[0].value);
2955 break;
2956 }
2957 if (r)
2958 r = -EINVAL;
2959 return r;
2960 }
2961
2962 /*
2963 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2964 * stopped by the hypervisor. This function will be called from the host only.
2965 * EINVAL is returned when the host attempts to set the flag for a guest that
2966 * does not support pv clocks.
2967 */
2968 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2969 {
2970 if (!vcpu->arch.time_page)
2971 return -EINVAL;
2972 vcpu->arch.pvclock_set_guest_stopped_request = true;
2973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2974 return 0;
2975 }
2976
2977 long kvm_arch_vcpu_ioctl(struct file *filp,
2978 unsigned int ioctl, unsigned long arg)
2979 {
2980 struct kvm_vcpu *vcpu = filp->private_data;
2981 void __user *argp = (void __user *)arg;
2982 int r;
2983 union {
2984 struct kvm_lapic_state *lapic;
2985 struct kvm_xsave *xsave;
2986 struct kvm_xcrs *xcrs;
2987 void *buffer;
2988 } u;
2989
2990 u.buffer = NULL;
2991 switch (ioctl) {
2992 case KVM_GET_LAPIC: {
2993 r = -EINVAL;
2994 if (!vcpu->arch.apic)
2995 goto out;
2996 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2997
2998 r = -ENOMEM;
2999 if (!u.lapic)
3000 goto out;
3001 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3002 if (r)
3003 goto out;
3004 r = -EFAULT;
3005 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3006 goto out;
3007 r = 0;
3008 break;
3009 }
3010 case KVM_SET_LAPIC: {
3011 r = -EINVAL;
3012 if (!vcpu->arch.apic)
3013 goto out;
3014 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3015 if (IS_ERR(u.lapic))
3016 return PTR_ERR(u.lapic);
3017
3018 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3019 break;
3020 }
3021 case KVM_INTERRUPT: {
3022 struct kvm_interrupt irq;
3023
3024 r = -EFAULT;
3025 if (copy_from_user(&irq, argp, sizeof irq))
3026 goto out;
3027 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3028 break;
3029 }
3030 case KVM_NMI: {
3031 r = kvm_vcpu_ioctl_nmi(vcpu);
3032 break;
3033 }
3034 case KVM_SET_CPUID: {
3035 struct kvm_cpuid __user *cpuid_arg = argp;
3036 struct kvm_cpuid cpuid;
3037
3038 r = -EFAULT;
3039 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3040 goto out;
3041 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3042 break;
3043 }
3044 case KVM_SET_CPUID2: {
3045 struct kvm_cpuid2 __user *cpuid_arg = argp;
3046 struct kvm_cpuid2 cpuid;
3047
3048 r = -EFAULT;
3049 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3050 goto out;
3051 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3052 cpuid_arg->entries);
3053 break;
3054 }
3055 case KVM_GET_CPUID2: {
3056 struct kvm_cpuid2 __user *cpuid_arg = argp;
3057 struct kvm_cpuid2 cpuid;
3058
3059 r = -EFAULT;
3060 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3061 goto out;
3062 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3063 cpuid_arg->entries);
3064 if (r)
3065 goto out;
3066 r = -EFAULT;
3067 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3068 goto out;
3069 r = 0;
3070 break;
3071 }
3072 case KVM_GET_MSRS:
3073 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3074 break;
3075 case KVM_SET_MSRS:
3076 r = msr_io(vcpu, argp, do_set_msr, 0);
3077 break;
3078 case KVM_TPR_ACCESS_REPORTING: {
3079 struct kvm_tpr_access_ctl tac;
3080
3081 r = -EFAULT;
3082 if (copy_from_user(&tac, argp, sizeof tac))
3083 goto out;
3084 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3085 if (r)
3086 goto out;
3087 r = -EFAULT;
3088 if (copy_to_user(argp, &tac, sizeof tac))
3089 goto out;
3090 r = 0;
3091 break;
3092 };
3093 case KVM_SET_VAPIC_ADDR: {
3094 struct kvm_vapic_addr va;
3095
3096 r = -EINVAL;
3097 if (!irqchip_in_kernel(vcpu->kvm))
3098 goto out;
3099 r = -EFAULT;
3100 if (copy_from_user(&va, argp, sizeof va))
3101 goto out;
3102 r = 0;
3103 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3104 break;
3105 }
3106 case KVM_X86_SETUP_MCE: {
3107 u64 mcg_cap;
3108
3109 r = -EFAULT;
3110 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3111 goto out;
3112 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3113 break;
3114 }
3115 case KVM_X86_SET_MCE: {
3116 struct kvm_x86_mce mce;
3117
3118 r = -EFAULT;
3119 if (copy_from_user(&mce, argp, sizeof mce))
3120 goto out;
3121 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3122 break;
3123 }
3124 case KVM_GET_VCPU_EVENTS: {
3125 struct kvm_vcpu_events events;
3126
3127 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3128
3129 r = -EFAULT;
3130 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3131 break;
3132 r = 0;
3133 break;
3134 }
3135 case KVM_SET_VCPU_EVENTS: {
3136 struct kvm_vcpu_events events;
3137
3138 r = -EFAULT;
3139 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3140 break;
3141
3142 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3143 break;
3144 }
3145 case KVM_GET_DEBUGREGS: {
3146 struct kvm_debugregs dbgregs;
3147
3148 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3149
3150 r = -EFAULT;
3151 if (copy_to_user(argp, &dbgregs,
3152 sizeof(struct kvm_debugregs)))
3153 break;
3154 r = 0;
3155 break;
3156 }
3157 case KVM_SET_DEBUGREGS: {
3158 struct kvm_debugregs dbgregs;
3159
3160 r = -EFAULT;
3161 if (copy_from_user(&dbgregs, argp,
3162 sizeof(struct kvm_debugregs)))
3163 break;
3164
3165 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3166 break;
3167 }
3168 case KVM_GET_XSAVE: {
3169 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3170 r = -ENOMEM;
3171 if (!u.xsave)
3172 break;
3173
3174 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3175
3176 r = -EFAULT;
3177 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3178 break;
3179 r = 0;
3180 break;
3181 }
3182 case KVM_SET_XSAVE: {
3183 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3184 if (IS_ERR(u.xsave))
3185 return PTR_ERR(u.xsave);
3186
3187 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3188 break;
3189 }
3190 case KVM_GET_XCRS: {
3191 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3192 r = -ENOMEM;
3193 if (!u.xcrs)
3194 break;
3195
3196 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3197
3198 r = -EFAULT;
3199 if (copy_to_user(argp, u.xcrs,
3200 sizeof(struct kvm_xcrs)))
3201 break;
3202 r = 0;
3203 break;
3204 }
3205 case KVM_SET_XCRS: {
3206 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3207 if (IS_ERR(u.xcrs))
3208 return PTR_ERR(u.xcrs);
3209
3210 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3211 break;
3212 }
3213 case KVM_SET_TSC_KHZ: {
3214 u32 user_tsc_khz;
3215
3216 r = -EINVAL;
3217 user_tsc_khz = (u32)arg;
3218
3219 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3220 goto out;
3221
3222 if (user_tsc_khz == 0)
3223 user_tsc_khz = tsc_khz;
3224
3225 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3226
3227 r = 0;
3228 goto out;
3229 }
3230 case KVM_GET_TSC_KHZ: {
3231 r = vcpu->arch.virtual_tsc_khz;
3232 goto out;
3233 }
3234 case KVM_KVMCLOCK_CTRL: {
3235 r = kvm_set_guest_paused(vcpu);
3236 goto out;
3237 }
3238 default:
3239 r = -EINVAL;
3240 }
3241 out:
3242 kfree(u.buffer);
3243 return r;
3244 }
3245
3246 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3247 {
3248 return VM_FAULT_SIGBUS;
3249 }
3250
3251 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3252 {
3253 int ret;
3254
3255 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3256 return -EINVAL;
3257 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3258 return ret;
3259 }
3260
3261 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3262 u64 ident_addr)
3263 {
3264 kvm->arch.ept_identity_map_addr = ident_addr;
3265 return 0;
3266 }
3267
3268 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3269 u32 kvm_nr_mmu_pages)
3270 {
3271 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3272 return -EINVAL;
3273
3274 mutex_lock(&kvm->slots_lock);
3275
3276 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3277 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3278
3279 mutex_unlock(&kvm->slots_lock);
3280 return 0;
3281 }
3282
3283 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3284 {
3285 return kvm->arch.n_max_mmu_pages;
3286 }
3287
3288 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3289 {
3290 int r;
3291
3292 r = 0;
3293 switch (chip->chip_id) {
3294 case KVM_IRQCHIP_PIC_MASTER:
3295 memcpy(&chip->chip.pic,
3296 &pic_irqchip(kvm)->pics[0],
3297 sizeof(struct kvm_pic_state));
3298 break;
3299 case KVM_IRQCHIP_PIC_SLAVE:
3300 memcpy(&chip->chip.pic,
3301 &pic_irqchip(kvm)->pics[1],
3302 sizeof(struct kvm_pic_state));
3303 break;
3304 case KVM_IRQCHIP_IOAPIC:
3305 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3306 break;
3307 default:
3308 r = -EINVAL;
3309 break;
3310 }
3311 return r;
3312 }
3313
3314 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3315 {
3316 int r;
3317
3318 r = 0;
3319 switch (chip->chip_id) {
3320 case KVM_IRQCHIP_PIC_MASTER:
3321 spin_lock(&pic_irqchip(kvm)->lock);
3322 memcpy(&pic_irqchip(kvm)->pics[0],
3323 &chip->chip.pic,
3324 sizeof(struct kvm_pic_state));
3325 spin_unlock(&pic_irqchip(kvm)->lock);
3326 break;
3327 case KVM_IRQCHIP_PIC_SLAVE:
3328 spin_lock(&pic_irqchip(kvm)->lock);
3329 memcpy(&pic_irqchip(kvm)->pics[1],
3330 &chip->chip.pic,
3331 sizeof(struct kvm_pic_state));
3332 spin_unlock(&pic_irqchip(kvm)->lock);
3333 break;
3334 case KVM_IRQCHIP_IOAPIC:
3335 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3336 break;
3337 default:
3338 r = -EINVAL;
3339 break;
3340 }
3341 kvm_pic_update_irq(pic_irqchip(kvm));
3342 return r;
3343 }
3344
3345 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3346 {
3347 int r = 0;
3348
3349 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3350 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3351 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3352 return r;
3353 }
3354
3355 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3356 {
3357 int r = 0;
3358
3359 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3360 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3361 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3362 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3363 return r;
3364 }
3365
3366 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3367 {
3368 int r = 0;
3369
3370 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3371 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3372 sizeof(ps->channels));
3373 ps->flags = kvm->arch.vpit->pit_state.flags;
3374 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3375 memset(&ps->reserved, 0, sizeof(ps->reserved));
3376 return r;
3377 }
3378
3379 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3380 {
3381 int r = 0, start = 0;
3382 u32 prev_legacy, cur_legacy;
3383 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3384 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3385 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3386 if (!prev_legacy && cur_legacy)
3387 start = 1;
3388 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3389 sizeof(kvm->arch.vpit->pit_state.channels));
3390 kvm->arch.vpit->pit_state.flags = ps->flags;
3391 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3392 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3393 return r;
3394 }
3395
3396 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3397 struct kvm_reinject_control *control)
3398 {
3399 if (!kvm->arch.vpit)
3400 return -ENXIO;
3401 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3402 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3403 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3404 return 0;
3405 }
3406
3407 /**
3408 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3409 * @kvm: kvm instance
3410 * @log: slot id and address to which we copy the log
3411 *
3412 * We need to keep it in mind that VCPU threads can write to the bitmap
3413 * concurrently. So, to avoid losing data, we keep the following order for
3414 * each bit:
3415 *
3416 * 1. Take a snapshot of the bit and clear it if needed.
3417 * 2. Write protect the corresponding page.
3418 * 3. Flush TLB's if needed.
3419 * 4. Copy the snapshot to the userspace.
3420 *
3421 * Between 2 and 3, the guest may write to the page using the remaining TLB
3422 * entry. This is not a problem because the page will be reported dirty at
3423 * step 4 using the snapshot taken before and step 3 ensures that successive
3424 * writes will be logged for the next call.
3425 */
3426 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3427 {
3428 int r;
3429 struct kvm_memory_slot *memslot;
3430 unsigned long n, i;
3431 unsigned long *dirty_bitmap;
3432 unsigned long *dirty_bitmap_buffer;
3433 bool is_dirty = false;
3434
3435 mutex_lock(&kvm->slots_lock);
3436
3437 r = -EINVAL;
3438 if (log->slot >= KVM_USER_MEM_SLOTS)
3439 goto out;
3440
3441 memslot = id_to_memslot(kvm->memslots, log->slot);
3442
3443 dirty_bitmap = memslot->dirty_bitmap;
3444 r = -ENOENT;
3445 if (!dirty_bitmap)
3446 goto out;
3447
3448 n = kvm_dirty_bitmap_bytes(memslot);
3449
3450 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3451 memset(dirty_bitmap_buffer, 0, n);
3452
3453 spin_lock(&kvm->mmu_lock);
3454
3455 for (i = 0; i < n / sizeof(long); i++) {
3456 unsigned long mask;
3457 gfn_t offset;
3458
3459 if (!dirty_bitmap[i])
3460 continue;
3461
3462 is_dirty = true;
3463
3464 mask = xchg(&dirty_bitmap[i], 0);
3465 dirty_bitmap_buffer[i] = mask;
3466
3467 offset = i * BITS_PER_LONG;
3468 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3469 }
3470 if (is_dirty)
3471 kvm_flush_remote_tlbs(kvm);
3472
3473 spin_unlock(&kvm->mmu_lock);
3474
3475 r = -EFAULT;
3476 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3477 goto out;
3478
3479 r = 0;
3480 out:
3481 mutex_unlock(&kvm->slots_lock);
3482 return r;
3483 }
3484
3485 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3486 {
3487 if (!irqchip_in_kernel(kvm))
3488 return -ENXIO;
3489
3490 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3491 irq_event->irq, irq_event->level);
3492 return 0;
3493 }
3494
3495 long kvm_arch_vm_ioctl(struct file *filp,
3496 unsigned int ioctl, unsigned long arg)
3497 {
3498 struct kvm *kvm = filp->private_data;
3499 void __user *argp = (void __user *)arg;
3500 int r = -ENOTTY;
3501 /*
3502 * This union makes it completely explicit to gcc-3.x
3503 * that these two variables' stack usage should be
3504 * combined, not added together.
3505 */
3506 union {
3507 struct kvm_pit_state ps;
3508 struct kvm_pit_state2 ps2;
3509 struct kvm_pit_config pit_config;
3510 } u;
3511
3512 switch (ioctl) {
3513 case KVM_SET_TSS_ADDR:
3514 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3515 break;
3516 case KVM_SET_IDENTITY_MAP_ADDR: {
3517 u64 ident_addr;
3518
3519 r = -EFAULT;
3520 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3521 goto out;
3522 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3523 break;
3524 }
3525 case KVM_SET_NR_MMU_PAGES:
3526 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3527 break;
3528 case KVM_GET_NR_MMU_PAGES:
3529 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3530 break;
3531 case KVM_CREATE_IRQCHIP: {
3532 struct kvm_pic *vpic;
3533
3534 mutex_lock(&kvm->lock);
3535 r = -EEXIST;
3536 if (kvm->arch.vpic)
3537 goto create_irqchip_unlock;
3538 r = -EINVAL;
3539 if (atomic_read(&kvm->online_vcpus))
3540 goto create_irqchip_unlock;
3541 r = -ENOMEM;
3542 vpic = kvm_create_pic(kvm);
3543 if (vpic) {
3544 r = kvm_ioapic_init(kvm);
3545 if (r) {
3546 mutex_lock(&kvm->slots_lock);
3547 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3548 &vpic->dev_master);
3549 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3550 &vpic->dev_slave);
3551 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3552 &vpic->dev_eclr);
3553 mutex_unlock(&kvm->slots_lock);
3554 kfree(vpic);
3555 goto create_irqchip_unlock;
3556 }
3557 } else
3558 goto create_irqchip_unlock;
3559 smp_wmb();
3560 kvm->arch.vpic = vpic;
3561 smp_wmb();
3562 r = kvm_setup_default_irq_routing(kvm);
3563 if (r) {
3564 mutex_lock(&kvm->slots_lock);
3565 mutex_lock(&kvm->irq_lock);
3566 kvm_ioapic_destroy(kvm);
3567 kvm_destroy_pic(kvm);
3568 mutex_unlock(&kvm->irq_lock);
3569 mutex_unlock(&kvm->slots_lock);
3570 }
3571 create_irqchip_unlock:
3572 mutex_unlock(&kvm->lock);
3573 break;
3574 }
3575 case KVM_CREATE_PIT:
3576 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3577 goto create_pit;
3578 case KVM_CREATE_PIT2:
3579 r = -EFAULT;
3580 if (copy_from_user(&u.pit_config, argp,
3581 sizeof(struct kvm_pit_config)))
3582 goto out;
3583 create_pit:
3584 mutex_lock(&kvm->slots_lock);
3585 r = -EEXIST;
3586 if (kvm->arch.vpit)
3587 goto create_pit_unlock;
3588 r = -ENOMEM;
3589 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3590 if (kvm->arch.vpit)
3591 r = 0;
3592 create_pit_unlock:
3593 mutex_unlock(&kvm->slots_lock);
3594 break;
3595 case KVM_GET_IRQCHIP: {
3596 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3597 struct kvm_irqchip *chip;
3598
3599 chip = memdup_user(argp, sizeof(*chip));
3600 if (IS_ERR(chip)) {
3601 r = PTR_ERR(chip);
3602 goto out;
3603 }
3604
3605 r = -ENXIO;
3606 if (!irqchip_in_kernel(kvm))
3607 goto get_irqchip_out;
3608 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3609 if (r)
3610 goto get_irqchip_out;
3611 r = -EFAULT;
3612 if (copy_to_user(argp, chip, sizeof *chip))
3613 goto get_irqchip_out;
3614 r = 0;
3615 get_irqchip_out:
3616 kfree(chip);
3617 break;
3618 }
3619 case KVM_SET_IRQCHIP: {
3620 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3621 struct kvm_irqchip *chip;
3622
3623 chip = memdup_user(argp, sizeof(*chip));
3624 if (IS_ERR(chip)) {
3625 r = PTR_ERR(chip);
3626 goto out;
3627 }
3628
3629 r = -ENXIO;
3630 if (!irqchip_in_kernel(kvm))
3631 goto set_irqchip_out;
3632 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3633 if (r)
3634 goto set_irqchip_out;
3635 r = 0;
3636 set_irqchip_out:
3637 kfree(chip);
3638 break;
3639 }
3640 case KVM_GET_PIT: {
3641 r = -EFAULT;
3642 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3643 goto out;
3644 r = -ENXIO;
3645 if (!kvm->arch.vpit)
3646 goto out;
3647 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3648 if (r)
3649 goto out;
3650 r = -EFAULT;
3651 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3652 goto out;
3653 r = 0;
3654 break;
3655 }
3656 case KVM_SET_PIT: {
3657 r = -EFAULT;
3658 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3659 goto out;
3660 r = -ENXIO;
3661 if (!kvm->arch.vpit)
3662 goto out;
3663 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3664 break;
3665 }
3666 case KVM_GET_PIT2: {
3667 r = -ENXIO;
3668 if (!kvm->arch.vpit)
3669 goto out;
3670 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3671 if (r)
3672 goto out;
3673 r = -EFAULT;
3674 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3675 goto out;
3676 r = 0;
3677 break;
3678 }
3679 case KVM_SET_PIT2: {
3680 r = -EFAULT;
3681 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3682 goto out;
3683 r = -ENXIO;
3684 if (!kvm->arch.vpit)
3685 goto out;
3686 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3687 break;
3688 }
3689 case KVM_REINJECT_CONTROL: {
3690 struct kvm_reinject_control control;
3691 r = -EFAULT;
3692 if (copy_from_user(&control, argp, sizeof(control)))
3693 goto out;
3694 r = kvm_vm_ioctl_reinject(kvm, &control);
3695 break;
3696 }
3697 case KVM_XEN_HVM_CONFIG: {
3698 r = -EFAULT;
3699 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3700 sizeof(struct kvm_xen_hvm_config)))
3701 goto out;
3702 r = -EINVAL;
3703 if (kvm->arch.xen_hvm_config.flags)
3704 goto out;
3705 r = 0;
3706 break;
3707 }
3708 case KVM_SET_CLOCK: {
3709 struct kvm_clock_data user_ns;
3710 u64 now_ns;
3711 s64 delta;
3712
3713 r = -EFAULT;
3714 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3715 goto out;
3716
3717 r = -EINVAL;
3718 if (user_ns.flags)
3719 goto out;
3720
3721 r = 0;
3722 local_irq_disable();
3723 now_ns = get_kernel_ns();
3724 delta = user_ns.clock - now_ns;
3725 local_irq_enable();
3726 kvm->arch.kvmclock_offset = delta;
3727 break;
3728 }
3729 case KVM_GET_CLOCK: {
3730 struct kvm_clock_data user_ns;
3731 u64 now_ns;
3732
3733 local_irq_disable();
3734 now_ns = get_kernel_ns();
3735 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3736 local_irq_enable();
3737 user_ns.flags = 0;
3738 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3739
3740 r = -EFAULT;
3741 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3742 goto out;
3743 r = 0;
3744 break;
3745 }
3746
3747 default:
3748 ;
3749 }
3750 out:
3751 return r;
3752 }
3753
3754 static void kvm_init_msr_list(void)
3755 {
3756 u32 dummy[2];
3757 unsigned i, j;
3758
3759 /* skip the first msrs in the list. KVM-specific */
3760 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3761 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3762 continue;
3763 if (j < i)
3764 msrs_to_save[j] = msrs_to_save[i];
3765 j++;
3766 }
3767 num_msrs_to_save = j;
3768 }
3769
3770 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3771 const void *v)
3772 {
3773 int handled = 0;
3774 int n;
3775
3776 do {
3777 n = min(len, 8);
3778 if (!(vcpu->arch.apic &&
3779 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3780 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3781 break;
3782 handled += n;
3783 addr += n;
3784 len -= n;
3785 v += n;
3786 } while (len);
3787
3788 return handled;
3789 }
3790
3791 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3792 {
3793 int handled = 0;
3794 int n;
3795
3796 do {
3797 n = min(len, 8);
3798 if (!(vcpu->arch.apic &&
3799 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3800 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3801 break;
3802 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3803 handled += n;
3804 addr += n;
3805 len -= n;
3806 v += n;
3807 } while (len);
3808
3809 return handled;
3810 }
3811
3812 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3813 struct kvm_segment *var, int seg)
3814 {
3815 kvm_x86_ops->set_segment(vcpu, var, seg);
3816 }
3817
3818 void kvm_get_segment(struct kvm_vcpu *vcpu,
3819 struct kvm_segment *var, int seg)
3820 {
3821 kvm_x86_ops->get_segment(vcpu, var, seg);
3822 }
3823
3824 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3825 {
3826 gpa_t t_gpa;
3827 struct x86_exception exception;
3828
3829 BUG_ON(!mmu_is_nested(vcpu));
3830
3831 /* NPT walks are always user-walks */
3832 access |= PFERR_USER_MASK;
3833 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3834
3835 return t_gpa;
3836 }
3837
3838 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3839 struct x86_exception *exception)
3840 {
3841 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3842 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3843 }
3844
3845 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3846 struct x86_exception *exception)
3847 {
3848 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3849 access |= PFERR_FETCH_MASK;
3850 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3851 }
3852
3853 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3854 struct x86_exception *exception)
3855 {
3856 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3857 access |= PFERR_WRITE_MASK;
3858 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3859 }
3860
3861 /* uses this to access any guest's mapped memory without checking CPL */
3862 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3863 struct x86_exception *exception)
3864 {
3865 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3866 }
3867
3868 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3869 struct kvm_vcpu *vcpu, u32 access,
3870 struct x86_exception *exception)
3871 {
3872 void *data = val;
3873 int r = X86EMUL_CONTINUE;
3874
3875 while (bytes) {
3876 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3877 exception);
3878 unsigned offset = addr & (PAGE_SIZE-1);
3879 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3880 int ret;
3881
3882 if (gpa == UNMAPPED_GVA)
3883 return X86EMUL_PROPAGATE_FAULT;
3884 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3885 if (ret < 0) {
3886 r = X86EMUL_IO_NEEDED;
3887 goto out;
3888 }
3889
3890 bytes -= toread;
3891 data += toread;
3892 addr += toread;
3893 }
3894 out:
3895 return r;
3896 }
3897
3898 /* used for instruction fetching */
3899 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3900 gva_t addr, void *val, unsigned int bytes,
3901 struct x86_exception *exception)
3902 {
3903 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3904 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3905
3906 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3907 access | PFERR_FETCH_MASK,
3908 exception);
3909 }
3910
3911 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3912 gva_t addr, void *val, unsigned int bytes,
3913 struct x86_exception *exception)
3914 {
3915 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3916 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3917
3918 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3919 exception);
3920 }
3921 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3922
3923 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3924 gva_t addr, void *val, unsigned int bytes,
3925 struct x86_exception *exception)
3926 {
3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3928 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3929 }
3930
3931 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3932 gva_t addr, void *val,
3933 unsigned int bytes,
3934 struct x86_exception *exception)
3935 {
3936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3937 void *data = val;
3938 int r = X86EMUL_CONTINUE;
3939
3940 while (bytes) {
3941 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3942 PFERR_WRITE_MASK,
3943 exception);
3944 unsigned offset = addr & (PAGE_SIZE-1);
3945 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3946 int ret;
3947
3948 if (gpa == UNMAPPED_GVA)
3949 return X86EMUL_PROPAGATE_FAULT;
3950 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3951 if (ret < 0) {
3952 r = X86EMUL_IO_NEEDED;
3953 goto out;
3954 }
3955
3956 bytes -= towrite;
3957 data += towrite;
3958 addr += towrite;
3959 }
3960 out:
3961 return r;
3962 }
3963 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3964
3965 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3966 gpa_t *gpa, struct x86_exception *exception,
3967 bool write)
3968 {
3969 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3970 | (write ? PFERR_WRITE_MASK : 0);
3971
3972 if (vcpu_match_mmio_gva(vcpu, gva)
3973 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3974 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3975 (gva & (PAGE_SIZE - 1));
3976 trace_vcpu_match_mmio(gva, *gpa, write, false);
3977 return 1;
3978 }
3979
3980 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3981
3982 if (*gpa == UNMAPPED_GVA)
3983 return -1;
3984
3985 /* For APIC access vmexit */
3986 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3987 return 1;
3988
3989 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3990 trace_vcpu_match_mmio(gva, *gpa, write, true);
3991 return 1;
3992 }
3993
3994 return 0;
3995 }
3996
3997 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3998 const void *val, int bytes)
3999 {
4000 int ret;
4001
4002 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4003 if (ret < 0)
4004 return 0;
4005 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4006 return 1;
4007 }
4008
4009 struct read_write_emulator_ops {
4010 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4011 int bytes);
4012 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4013 void *val, int bytes);
4014 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4015 int bytes, void *val);
4016 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4017 void *val, int bytes);
4018 bool write;
4019 };
4020
4021 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4022 {
4023 if (vcpu->mmio_read_completed) {
4024 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4025 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4026 vcpu->mmio_read_completed = 0;
4027 return 1;
4028 }
4029
4030 return 0;
4031 }
4032
4033 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4034 void *val, int bytes)
4035 {
4036 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4037 }
4038
4039 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4040 void *val, int bytes)
4041 {
4042 return emulator_write_phys(vcpu, gpa, val, bytes);
4043 }
4044
4045 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4046 {
4047 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4048 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4049 }
4050
4051 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4052 void *val, int bytes)
4053 {
4054 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4055 return X86EMUL_IO_NEEDED;
4056 }
4057
4058 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4059 void *val, int bytes)
4060 {
4061 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4062
4063 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4064 return X86EMUL_CONTINUE;
4065 }
4066
4067 static const struct read_write_emulator_ops read_emultor = {
4068 .read_write_prepare = read_prepare,
4069 .read_write_emulate = read_emulate,
4070 .read_write_mmio = vcpu_mmio_read,
4071 .read_write_exit_mmio = read_exit_mmio,
4072 };
4073
4074 static const struct read_write_emulator_ops write_emultor = {
4075 .read_write_emulate = write_emulate,
4076 .read_write_mmio = write_mmio,
4077 .read_write_exit_mmio = write_exit_mmio,
4078 .write = true,
4079 };
4080
4081 static int emulator_read_write_onepage(unsigned long addr, void *val,
4082 unsigned int bytes,
4083 struct x86_exception *exception,
4084 struct kvm_vcpu *vcpu,
4085 const struct read_write_emulator_ops *ops)
4086 {
4087 gpa_t gpa;
4088 int handled, ret;
4089 bool write = ops->write;
4090 struct kvm_mmio_fragment *frag;
4091
4092 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4093
4094 if (ret < 0)
4095 return X86EMUL_PROPAGATE_FAULT;
4096
4097 /* For APIC access vmexit */
4098 if (ret)
4099 goto mmio;
4100
4101 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4102 return X86EMUL_CONTINUE;
4103
4104 mmio:
4105 /*
4106 * Is this MMIO handled locally?
4107 */
4108 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4109 if (handled == bytes)
4110 return X86EMUL_CONTINUE;
4111
4112 gpa += handled;
4113 bytes -= handled;
4114 val += handled;
4115
4116 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4117 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4118 frag->gpa = gpa;
4119 frag->data = val;
4120 frag->len = bytes;
4121 return X86EMUL_CONTINUE;
4122 }
4123
4124 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4125 void *val, unsigned int bytes,
4126 struct x86_exception *exception,
4127 const struct read_write_emulator_ops *ops)
4128 {
4129 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4130 gpa_t gpa;
4131 int rc;
4132
4133 if (ops->read_write_prepare &&
4134 ops->read_write_prepare(vcpu, val, bytes))
4135 return X86EMUL_CONTINUE;
4136
4137 vcpu->mmio_nr_fragments = 0;
4138
4139 /* Crossing a page boundary? */
4140 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4141 int now;
4142
4143 now = -addr & ~PAGE_MASK;
4144 rc = emulator_read_write_onepage(addr, val, now, exception,
4145 vcpu, ops);
4146
4147 if (rc != X86EMUL_CONTINUE)
4148 return rc;
4149 addr += now;
4150 val += now;
4151 bytes -= now;
4152 }
4153
4154 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4155 vcpu, ops);
4156 if (rc != X86EMUL_CONTINUE)
4157 return rc;
4158
4159 if (!vcpu->mmio_nr_fragments)
4160 return rc;
4161
4162 gpa = vcpu->mmio_fragments[0].gpa;
4163
4164 vcpu->mmio_needed = 1;
4165 vcpu->mmio_cur_fragment = 0;
4166
4167 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4168 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4169 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4170 vcpu->run->mmio.phys_addr = gpa;
4171
4172 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4173 }
4174
4175 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4176 unsigned long addr,
4177 void *val,
4178 unsigned int bytes,
4179 struct x86_exception *exception)
4180 {
4181 return emulator_read_write(ctxt, addr, val, bytes,
4182 exception, &read_emultor);
4183 }
4184
4185 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4186 unsigned long addr,
4187 const void *val,
4188 unsigned int bytes,
4189 struct x86_exception *exception)
4190 {
4191 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4192 exception, &write_emultor);
4193 }
4194
4195 #define CMPXCHG_TYPE(t, ptr, old, new) \
4196 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4197
4198 #ifdef CONFIG_X86_64
4199 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4200 #else
4201 # define CMPXCHG64(ptr, old, new) \
4202 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4203 #endif
4204
4205 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4206 unsigned long addr,
4207 const void *old,
4208 const void *new,
4209 unsigned int bytes,
4210 struct x86_exception *exception)
4211 {
4212 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4213 gpa_t gpa;
4214 struct page *page;
4215 char *kaddr;
4216 bool exchanged;
4217
4218 /* guests cmpxchg8b have to be emulated atomically */
4219 if (bytes > 8 || (bytes & (bytes - 1)))
4220 goto emul_write;
4221
4222 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4223
4224 if (gpa == UNMAPPED_GVA ||
4225 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4226 goto emul_write;
4227
4228 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4229 goto emul_write;
4230
4231 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4232 if (is_error_page(page))
4233 goto emul_write;
4234
4235 kaddr = kmap_atomic(page);
4236 kaddr += offset_in_page(gpa);
4237 switch (bytes) {
4238 case 1:
4239 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4240 break;
4241 case 2:
4242 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4243 break;
4244 case 4:
4245 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4246 break;
4247 case 8:
4248 exchanged = CMPXCHG64(kaddr, old, new);
4249 break;
4250 default:
4251 BUG();
4252 }
4253 kunmap_atomic(kaddr);
4254 kvm_release_page_dirty(page);
4255
4256 if (!exchanged)
4257 return X86EMUL_CMPXCHG_FAILED;
4258
4259 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4260
4261 return X86EMUL_CONTINUE;
4262
4263 emul_write:
4264 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4265
4266 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4267 }
4268
4269 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4270 {
4271 /* TODO: String I/O for in kernel device */
4272 int r;
4273
4274 if (vcpu->arch.pio.in)
4275 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4276 vcpu->arch.pio.size, pd);
4277 else
4278 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4279 vcpu->arch.pio.port, vcpu->arch.pio.size,
4280 pd);
4281 return r;
4282 }
4283
4284 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4285 unsigned short port, void *val,
4286 unsigned int count, bool in)
4287 {
4288 trace_kvm_pio(!in, port, size, count);
4289
4290 vcpu->arch.pio.port = port;
4291 vcpu->arch.pio.in = in;
4292 vcpu->arch.pio.count = count;
4293 vcpu->arch.pio.size = size;
4294
4295 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4296 vcpu->arch.pio.count = 0;
4297 return 1;
4298 }
4299
4300 vcpu->run->exit_reason = KVM_EXIT_IO;
4301 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4302 vcpu->run->io.size = size;
4303 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4304 vcpu->run->io.count = count;
4305 vcpu->run->io.port = port;
4306
4307 return 0;
4308 }
4309
4310 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4311 int size, unsigned short port, void *val,
4312 unsigned int count)
4313 {
4314 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4315 int ret;
4316
4317 if (vcpu->arch.pio.count)
4318 goto data_avail;
4319
4320 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4321 if (ret) {
4322 data_avail:
4323 memcpy(val, vcpu->arch.pio_data, size * count);
4324 vcpu->arch.pio.count = 0;
4325 return 1;
4326 }
4327
4328 return 0;
4329 }
4330
4331 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4332 int size, unsigned short port,
4333 const void *val, unsigned int count)
4334 {
4335 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4336
4337 memcpy(vcpu->arch.pio_data, val, size * count);
4338 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4339 }
4340
4341 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4342 {
4343 return kvm_x86_ops->get_segment_base(vcpu, seg);
4344 }
4345
4346 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4347 {
4348 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4349 }
4350
4351 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4352 {
4353 if (!need_emulate_wbinvd(vcpu))
4354 return X86EMUL_CONTINUE;
4355
4356 if (kvm_x86_ops->has_wbinvd_exit()) {
4357 int cpu = get_cpu();
4358
4359 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4360 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4361 wbinvd_ipi, NULL, 1);
4362 put_cpu();
4363 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4364 } else
4365 wbinvd();
4366 return X86EMUL_CONTINUE;
4367 }
4368 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4369
4370 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4371 {
4372 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4373 }
4374
4375 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4376 {
4377 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4378 }
4379
4380 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4381 {
4382
4383 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4384 }
4385
4386 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4387 {
4388 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4389 }
4390
4391 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4392 {
4393 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4394 unsigned long value;
4395
4396 switch (cr) {
4397 case 0:
4398 value = kvm_read_cr0(vcpu);
4399 break;
4400 case 2:
4401 value = vcpu->arch.cr2;
4402 break;
4403 case 3:
4404 value = kvm_read_cr3(vcpu);
4405 break;
4406 case 4:
4407 value = kvm_read_cr4(vcpu);
4408 break;
4409 case 8:
4410 value = kvm_get_cr8(vcpu);
4411 break;
4412 default:
4413 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4414 return 0;
4415 }
4416
4417 return value;
4418 }
4419
4420 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4421 {
4422 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4423 int res = 0;
4424
4425 switch (cr) {
4426 case 0:
4427 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4428 break;
4429 case 2:
4430 vcpu->arch.cr2 = val;
4431 break;
4432 case 3:
4433 res = kvm_set_cr3(vcpu, val);
4434 break;
4435 case 4:
4436 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4437 break;
4438 case 8:
4439 res = kvm_set_cr8(vcpu, val);
4440 break;
4441 default:
4442 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4443 res = -1;
4444 }
4445
4446 return res;
4447 }
4448
4449 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4450 {
4451 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4452 }
4453
4454 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4455 {
4456 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4457 }
4458
4459 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4460 {
4461 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4462 }
4463
4464 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4465 {
4466 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4467 }
4468
4469 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4470 {
4471 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4472 }
4473
4474 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4475 {
4476 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4477 }
4478
4479 static unsigned long emulator_get_cached_segment_base(
4480 struct x86_emulate_ctxt *ctxt, int seg)
4481 {
4482 return get_segment_base(emul_to_vcpu(ctxt), seg);
4483 }
4484
4485 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4486 struct desc_struct *desc, u32 *base3,
4487 int seg)
4488 {
4489 struct kvm_segment var;
4490
4491 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4492 *selector = var.selector;
4493
4494 if (var.unusable) {
4495 memset(desc, 0, sizeof(*desc));
4496 return false;
4497 }
4498
4499 if (var.g)
4500 var.limit >>= 12;
4501 set_desc_limit(desc, var.limit);
4502 set_desc_base(desc, (unsigned long)var.base);
4503 #ifdef CONFIG_X86_64
4504 if (base3)
4505 *base3 = var.base >> 32;
4506 #endif
4507 desc->type = var.type;
4508 desc->s = var.s;
4509 desc->dpl = var.dpl;
4510 desc->p = var.present;
4511 desc->avl = var.avl;
4512 desc->l = var.l;
4513 desc->d = var.db;
4514 desc->g = var.g;
4515
4516 return true;
4517 }
4518
4519 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4520 struct desc_struct *desc, u32 base3,
4521 int seg)
4522 {
4523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4524 struct kvm_segment var;
4525
4526 var.selector = selector;
4527 var.base = get_desc_base(desc);
4528 #ifdef CONFIG_X86_64
4529 var.base |= ((u64)base3) << 32;
4530 #endif
4531 var.limit = get_desc_limit(desc);
4532 if (desc->g)
4533 var.limit = (var.limit << 12) | 0xfff;
4534 var.type = desc->type;
4535 var.present = desc->p;
4536 var.dpl = desc->dpl;
4537 var.db = desc->d;
4538 var.s = desc->s;
4539 var.l = desc->l;
4540 var.g = desc->g;
4541 var.avl = desc->avl;
4542 var.present = desc->p;
4543 var.unusable = !var.present;
4544 var.padding = 0;
4545
4546 kvm_set_segment(vcpu, &var, seg);
4547 return;
4548 }
4549
4550 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4551 u32 msr_index, u64 *pdata)
4552 {
4553 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4554 }
4555
4556 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4557 u32 msr_index, u64 data)
4558 {
4559 struct msr_data msr;
4560
4561 msr.data = data;
4562 msr.index = msr_index;
4563 msr.host_initiated = false;
4564 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4565 }
4566
4567 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4568 u32 pmc, u64 *pdata)
4569 {
4570 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4571 }
4572
4573 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4574 {
4575 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4576 }
4577
4578 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4579 {
4580 preempt_disable();
4581 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4582 /*
4583 * CR0.TS may reference the host fpu state, not the guest fpu state,
4584 * so it may be clear at this point.
4585 */
4586 clts();
4587 }
4588
4589 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4590 {
4591 preempt_enable();
4592 }
4593
4594 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4595 struct x86_instruction_info *info,
4596 enum x86_intercept_stage stage)
4597 {
4598 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4599 }
4600
4601 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4602 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4603 {
4604 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4605 }
4606
4607 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4608 {
4609 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4610 }
4611
4612 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4613 {
4614 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4615 }
4616
4617 static const struct x86_emulate_ops emulate_ops = {
4618 .read_gpr = emulator_read_gpr,
4619 .write_gpr = emulator_write_gpr,
4620 .read_std = kvm_read_guest_virt_system,
4621 .write_std = kvm_write_guest_virt_system,
4622 .fetch = kvm_fetch_guest_virt,
4623 .read_emulated = emulator_read_emulated,
4624 .write_emulated = emulator_write_emulated,
4625 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4626 .invlpg = emulator_invlpg,
4627 .pio_in_emulated = emulator_pio_in_emulated,
4628 .pio_out_emulated = emulator_pio_out_emulated,
4629 .get_segment = emulator_get_segment,
4630 .set_segment = emulator_set_segment,
4631 .get_cached_segment_base = emulator_get_cached_segment_base,
4632 .get_gdt = emulator_get_gdt,
4633 .get_idt = emulator_get_idt,
4634 .set_gdt = emulator_set_gdt,
4635 .set_idt = emulator_set_idt,
4636 .get_cr = emulator_get_cr,
4637 .set_cr = emulator_set_cr,
4638 .set_rflags = emulator_set_rflags,
4639 .cpl = emulator_get_cpl,
4640 .get_dr = emulator_get_dr,
4641 .set_dr = emulator_set_dr,
4642 .set_msr = emulator_set_msr,
4643 .get_msr = emulator_get_msr,
4644 .read_pmc = emulator_read_pmc,
4645 .halt = emulator_halt,
4646 .wbinvd = emulator_wbinvd,
4647 .fix_hypercall = emulator_fix_hypercall,
4648 .get_fpu = emulator_get_fpu,
4649 .put_fpu = emulator_put_fpu,
4650 .intercept = emulator_intercept,
4651 .get_cpuid = emulator_get_cpuid,
4652 };
4653
4654 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4655 {
4656 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4657 /*
4658 * an sti; sti; sequence only disable interrupts for the first
4659 * instruction. So, if the last instruction, be it emulated or
4660 * not, left the system with the INT_STI flag enabled, it
4661 * means that the last instruction is an sti. We should not
4662 * leave the flag on in this case. The same goes for mov ss
4663 */
4664 if (!(int_shadow & mask))
4665 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4666 }
4667
4668 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4669 {
4670 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4671 if (ctxt->exception.vector == PF_VECTOR)
4672 kvm_propagate_fault(vcpu, &ctxt->exception);
4673 else if (ctxt->exception.error_code_valid)
4674 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4675 ctxt->exception.error_code);
4676 else
4677 kvm_queue_exception(vcpu, ctxt->exception.vector);
4678 }
4679
4680 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4681 {
4682 memset(&ctxt->twobyte, 0,
4683 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4684
4685 ctxt->fetch.start = 0;
4686 ctxt->fetch.end = 0;
4687 ctxt->io_read.pos = 0;
4688 ctxt->io_read.end = 0;
4689 ctxt->mem_read.pos = 0;
4690 ctxt->mem_read.end = 0;
4691 }
4692
4693 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4694 {
4695 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4696 int cs_db, cs_l;
4697
4698 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4699
4700 ctxt->eflags = kvm_get_rflags(vcpu);
4701 ctxt->eip = kvm_rip_read(vcpu);
4702 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4703 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4704 cs_l ? X86EMUL_MODE_PROT64 :
4705 cs_db ? X86EMUL_MODE_PROT32 :
4706 X86EMUL_MODE_PROT16;
4707 ctxt->guest_mode = is_guest_mode(vcpu);
4708
4709 init_decode_cache(ctxt);
4710 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4711 }
4712
4713 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4714 {
4715 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4716 int ret;
4717
4718 init_emulate_ctxt(vcpu);
4719
4720 ctxt->op_bytes = 2;
4721 ctxt->ad_bytes = 2;
4722 ctxt->_eip = ctxt->eip + inc_eip;
4723 ret = emulate_int_real(ctxt, irq);
4724
4725 if (ret != X86EMUL_CONTINUE)
4726 return EMULATE_FAIL;
4727
4728 ctxt->eip = ctxt->_eip;
4729 kvm_rip_write(vcpu, ctxt->eip);
4730 kvm_set_rflags(vcpu, ctxt->eflags);
4731
4732 if (irq == NMI_VECTOR)
4733 vcpu->arch.nmi_pending = 0;
4734 else
4735 vcpu->arch.interrupt.pending = false;
4736
4737 return EMULATE_DONE;
4738 }
4739 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4740
4741 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4742 {
4743 int r = EMULATE_DONE;
4744
4745 ++vcpu->stat.insn_emulation_fail;
4746 trace_kvm_emulate_insn_failed(vcpu);
4747 if (!is_guest_mode(vcpu)) {
4748 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4749 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4750 vcpu->run->internal.ndata = 0;
4751 r = EMULATE_FAIL;
4752 }
4753 kvm_queue_exception(vcpu, UD_VECTOR);
4754
4755 return r;
4756 }
4757
4758 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4759 bool write_fault_to_shadow_pgtable)
4760 {
4761 gpa_t gpa = cr2;
4762 pfn_t pfn;
4763
4764 if (!vcpu->arch.mmu.direct_map) {
4765 /*
4766 * Write permission should be allowed since only
4767 * write access need to be emulated.
4768 */
4769 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4770
4771 /*
4772 * If the mapping is invalid in guest, let cpu retry
4773 * it to generate fault.
4774 */
4775 if (gpa == UNMAPPED_GVA)
4776 return true;
4777 }
4778
4779 /*
4780 * Do not retry the unhandleable instruction if it faults on the
4781 * readonly host memory, otherwise it will goto a infinite loop:
4782 * retry instruction -> write #PF -> emulation fail -> retry
4783 * instruction -> ...
4784 */
4785 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4786
4787 /*
4788 * If the instruction failed on the error pfn, it can not be fixed,
4789 * report the error to userspace.
4790 */
4791 if (is_error_noslot_pfn(pfn))
4792 return false;
4793
4794 kvm_release_pfn_clean(pfn);
4795
4796 /* The instructions are well-emulated on direct mmu. */
4797 if (vcpu->arch.mmu.direct_map) {
4798 unsigned int indirect_shadow_pages;
4799
4800 spin_lock(&vcpu->kvm->mmu_lock);
4801 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4802 spin_unlock(&vcpu->kvm->mmu_lock);
4803
4804 if (indirect_shadow_pages)
4805 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4806
4807 return true;
4808 }
4809
4810 /*
4811 * if emulation was due to access to shadowed page table
4812 * and it failed try to unshadow page and re-enter the
4813 * guest to let CPU execute the instruction.
4814 */
4815 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4816
4817 /*
4818 * If the access faults on its page table, it can not
4819 * be fixed by unprotecting shadow page and it should
4820 * be reported to userspace.
4821 */
4822 return !write_fault_to_shadow_pgtable;
4823 }
4824
4825 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4826 unsigned long cr2, int emulation_type)
4827 {
4828 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4829 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4830
4831 last_retry_eip = vcpu->arch.last_retry_eip;
4832 last_retry_addr = vcpu->arch.last_retry_addr;
4833
4834 /*
4835 * If the emulation is caused by #PF and it is non-page_table
4836 * writing instruction, it means the VM-EXIT is caused by shadow
4837 * page protected, we can zap the shadow page and retry this
4838 * instruction directly.
4839 *
4840 * Note: if the guest uses a non-page-table modifying instruction
4841 * on the PDE that points to the instruction, then we will unmap
4842 * the instruction and go to an infinite loop. So, we cache the
4843 * last retried eip and the last fault address, if we meet the eip
4844 * and the address again, we can break out of the potential infinite
4845 * loop.
4846 */
4847 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4848
4849 if (!(emulation_type & EMULTYPE_RETRY))
4850 return false;
4851
4852 if (x86_page_table_writing_insn(ctxt))
4853 return false;
4854
4855 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4856 return false;
4857
4858 vcpu->arch.last_retry_eip = ctxt->eip;
4859 vcpu->arch.last_retry_addr = cr2;
4860
4861 if (!vcpu->arch.mmu.direct_map)
4862 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4863
4864 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4865
4866 return true;
4867 }
4868
4869 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4870 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4871
4872 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4873 unsigned long cr2,
4874 int emulation_type,
4875 void *insn,
4876 int insn_len)
4877 {
4878 int r;
4879 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4880 bool writeback = true;
4881 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4882
4883 /*
4884 * Clear write_fault_to_shadow_pgtable here to ensure it is
4885 * never reused.
4886 */
4887 vcpu->arch.write_fault_to_shadow_pgtable = false;
4888 kvm_clear_exception_queue(vcpu);
4889
4890 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4891 init_emulate_ctxt(vcpu);
4892 ctxt->interruptibility = 0;
4893 ctxt->have_exception = false;
4894 ctxt->perm_ok = false;
4895
4896 ctxt->only_vendor_specific_insn
4897 = emulation_type & EMULTYPE_TRAP_UD;
4898
4899 r = x86_decode_insn(ctxt, insn, insn_len);
4900
4901 trace_kvm_emulate_insn_start(vcpu);
4902 ++vcpu->stat.insn_emulation;
4903 if (r != EMULATION_OK) {
4904 if (emulation_type & EMULTYPE_TRAP_UD)
4905 return EMULATE_FAIL;
4906 if (reexecute_instruction(vcpu, cr2,
4907 write_fault_to_spt))
4908 return EMULATE_DONE;
4909 if (emulation_type & EMULTYPE_SKIP)
4910 return EMULATE_FAIL;
4911 return handle_emulation_failure(vcpu);
4912 }
4913 }
4914
4915 if (emulation_type & EMULTYPE_SKIP) {
4916 kvm_rip_write(vcpu, ctxt->_eip);
4917 return EMULATE_DONE;
4918 }
4919
4920 if (retry_instruction(ctxt, cr2, emulation_type))
4921 return EMULATE_DONE;
4922
4923 /* this is needed for vmware backdoor interface to work since it
4924 changes registers values during IO operation */
4925 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4926 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4927 emulator_invalidate_register_cache(ctxt);
4928 }
4929
4930 restart:
4931 r = x86_emulate_insn(ctxt);
4932
4933 if (r == EMULATION_INTERCEPTED)
4934 return EMULATE_DONE;
4935
4936 if (r == EMULATION_FAILED) {
4937 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
4938 return EMULATE_DONE;
4939
4940 return handle_emulation_failure(vcpu);
4941 }
4942
4943 if (ctxt->have_exception) {
4944 inject_emulated_exception(vcpu);
4945 r = EMULATE_DONE;
4946 } else if (vcpu->arch.pio.count) {
4947 if (!vcpu->arch.pio.in)
4948 vcpu->arch.pio.count = 0;
4949 else {
4950 writeback = false;
4951 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4952 }
4953 r = EMULATE_DO_MMIO;
4954 } else if (vcpu->mmio_needed) {
4955 if (!vcpu->mmio_is_write)
4956 writeback = false;
4957 r = EMULATE_DO_MMIO;
4958 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4959 } else if (r == EMULATION_RESTART)
4960 goto restart;
4961 else
4962 r = EMULATE_DONE;
4963
4964 if (writeback) {
4965 toggle_interruptibility(vcpu, ctxt->interruptibility);
4966 kvm_set_rflags(vcpu, ctxt->eflags);
4967 kvm_make_request(KVM_REQ_EVENT, vcpu);
4968 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4969 kvm_rip_write(vcpu, ctxt->eip);
4970 } else
4971 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4972
4973 return r;
4974 }
4975 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4976
4977 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4978 {
4979 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4980 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4981 size, port, &val, 1);
4982 /* do not return to emulator after return from userspace */
4983 vcpu->arch.pio.count = 0;
4984 return ret;
4985 }
4986 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4987
4988 static void tsc_bad(void *info)
4989 {
4990 __this_cpu_write(cpu_tsc_khz, 0);
4991 }
4992
4993 static void tsc_khz_changed(void *data)
4994 {
4995 struct cpufreq_freqs *freq = data;
4996 unsigned long khz = 0;
4997
4998 if (data)
4999 khz = freq->new;
5000 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5001 khz = cpufreq_quick_get(raw_smp_processor_id());
5002 if (!khz)
5003 khz = tsc_khz;
5004 __this_cpu_write(cpu_tsc_khz, khz);
5005 }
5006
5007 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5008 void *data)
5009 {
5010 struct cpufreq_freqs *freq = data;
5011 struct kvm *kvm;
5012 struct kvm_vcpu *vcpu;
5013 int i, send_ipi = 0;
5014
5015 /*
5016 * We allow guests to temporarily run on slowing clocks,
5017 * provided we notify them after, or to run on accelerating
5018 * clocks, provided we notify them before. Thus time never
5019 * goes backwards.
5020 *
5021 * However, we have a problem. We can't atomically update
5022 * the frequency of a given CPU from this function; it is
5023 * merely a notifier, which can be called from any CPU.
5024 * Changing the TSC frequency at arbitrary points in time
5025 * requires a recomputation of local variables related to
5026 * the TSC for each VCPU. We must flag these local variables
5027 * to be updated and be sure the update takes place with the
5028 * new frequency before any guests proceed.
5029 *
5030 * Unfortunately, the combination of hotplug CPU and frequency
5031 * change creates an intractable locking scenario; the order
5032 * of when these callouts happen is undefined with respect to
5033 * CPU hotplug, and they can race with each other. As such,
5034 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5035 * undefined; you can actually have a CPU frequency change take
5036 * place in between the computation of X and the setting of the
5037 * variable. To protect against this problem, all updates of
5038 * the per_cpu tsc_khz variable are done in an interrupt
5039 * protected IPI, and all callers wishing to update the value
5040 * must wait for a synchronous IPI to complete (which is trivial
5041 * if the caller is on the CPU already). This establishes the
5042 * necessary total order on variable updates.
5043 *
5044 * Note that because a guest time update may take place
5045 * anytime after the setting of the VCPU's request bit, the
5046 * correct TSC value must be set before the request. However,
5047 * to ensure the update actually makes it to any guest which
5048 * starts running in hardware virtualization between the set
5049 * and the acquisition of the spinlock, we must also ping the
5050 * CPU after setting the request bit.
5051 *
5052 */
5053
5054 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5055 return 0;
5056 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5057 return 0;
5058
5059 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5060
5061 raw_spin_lock(&kvm_lock);
5062 list_for_each_entry(kvm, &vm_list, vm_list) {
5063 kvm_for_each_vcpu(i, vcpu, kvm) {
5064 if (vcpu->cpu != freq->cpu)
5065 continue;
5066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5067 if (vcpu->cpu != smp_processor_id())
5068 send_ipi = 1;
5069 }
5070 }
5071 raw_spin_unlock(&kvm_lock);
5072
5073 if (freq->old < freq->new && send_ipi) {
5074 /*
5075 * We upscale the frequency. Must make the guest
5076 * doesn't see old kvmclock values while running with
5077 * the new frequency, otherwise we risk the guest sees
5078 * time go backwards.
5079 *
5080 * In case we update the frequency for another cpu
5081 * (which might be in guest context) send an interrupt
5082 * to kick the cpu out of guest context. Next time
5083 * guest context is entered kvmclock will be updated,
5084 * so the guest will not see stale values.
5085 */
5086 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5087 }
5088 return 0;
5089 }
5090
5091 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5092 .notifier_call = kvmclock_cpufreq_notifier
5093 };
5094
5095 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5096 unsigned long action, void *hcpu)
5097 {
5098 unsigned int cpu = (unsigned long)hcpu;
5099
5100 switch (action) {
5101 case CPU_ONLINE:
5102 case CPU_DOWN_FAILED:
5103 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5104 break;
5105 case CPU_DOWN_PREPARE:
5106 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5107 break;
5108 }
5109 return NOTIFY_OK;
5110 }
5111
5112 static struct notifier_block kvmclock_cpu_notifier_block = {
5113 .notifier_call = kvmclock_cpu_notifier,
5114 .priority = -INT_MAX
5115 };
5116
5117 static void kvm_timer_init(void)
5118 {
5119 int cpu;
5120
5121 max_tsc_khz = tsc_khz;
5122 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5123 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5124 #ifdef CONFIG_CPU_FREQ
5125 struct cpufreq_policy policy;
5126 memset(&policy, 0, sizeof(policy));
5127 cpu = get_cpu();
5128 cpufreq_get_policy(&policy, cpu);
5129 if (policy.cpuinfo.max_freq)
5130 max_tsc_khz = policy.cpuinfo.max_freq;
5131 put_cpu();
5132 #endif
5133 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5134 CPUFREQ_TRANSITION_NOTIFIER);
5135 }
5136 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5137 for_each_online_cpu(cpu)
5138 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5139 }
5140
5141 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5142
5143 int kvm_is_in_guest(void)
5144 {
5145 return __this_cpu_read(current_vcpu) != NULL;
5146 }
5147
5148 static int kvm_is_user_mode(void)
5149 {
5150 int user_mode = 3;
5151
5152 if (__this_cpu_read(current_vcpu))
5153 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5154
5155 return user_mode != 0;
5156 }
5157
5158 static unsigned long kvm_get_guest_ip(void)
5159 {
5160 unsigned long ip = 0;
5161
5162 if (__this_cpu_read(current_vcpu))
5163 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5164
5165 return ip;
5166 }
5167
5168 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5169 .is_in_guest = kvm_is_in_guest,
5170 .is_user_mode = kvm_is_user_mode,
5171 .get_guest_ip = kvm_get_guest_ip,
5172 };
5173
5174 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5175 {
5176 __this_cpu_write(current_vcpu, vcpu);
5177 }
5178 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5179
5180 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5181 {
5182 __this_cpu_write(current_vcpu, NULL);
5183 }
5184 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5185
5186 static void kvm_set_mmio_spte_mask(void)
5187 {
5188 u64 mask;
5189 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5190
5191 /*
5192 * Set the reserved bits and the present bit of an paging-structure
5193 * entry to generate page fault with PFER.RSV = 1.
5194 */
5195 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5196 mask |= 1ull;
5197
5198 #ifdef CONFIG_X86_64
5199 /*
5200 * If reserved bit is not supported, clear the present bit to disable
5201 * mmio page fault.
5202 */
5203 if (maxphyaddr == 52)
5204 mask &= ~1ull;
5205 #endif
5206
5207 kvm_mmu_set_mmio_spte_mask(mask);
5208 }
5209
5210 #ifdef CONFIG_X86_64
5211 static void pvclock_gtod_update_fn(struct work_struct *work)
5212 {
5213 struct kvm *kvm;
5214
5215 struct kvm_vcpu *vcpu;
5216 int i;
5217
5218 raw_spin_lock(&kvm_lock);
5219 list_for_each_entry(kvm, &vm_list, vm_list)
5220 kvm_for_each_vcpu(i, vcpu, kvm)
5221 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5222 atomic_set(&kvm_guest_has_master_clock, 0);
5223 raw_spin_unlock(&kvm_lock);
5224 }
5225
5226 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5227
5228 /*
5229 * Notification about pvclock gtod data update.
5230 */
5231 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5232 void *priv)
5233 {
5234 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5235 struct timekeeper *tk = priv;
5236
5237 update_pvclock_gtod(tk);
5238
5239 /* disable master clock if host does not trust, or does not
5240 * use, TSC clocksource
5241 */
5242 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5243 atomic_read(&kvm_guest_has_master_clock) != 0)
5244 queue_work(system_long_wq, &pvclock_gtod_work);
5245
5246 return 0;
5247 }
5248
5249 static struct notifier_block pvclock_gtod_notifier = {
5250 .notifier_call = pvclock_gtod_notify,
5251 };
5252 #endif
5253
5254 int kvm_arch_init(void *opaque)
5255 {
5256 int r;
5257 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5258
5259 if (kvm_x86_ops) {
5260 printk(KERN_ERR "kvm: already loaded the other module\n");
5261 r = -EEXIST;
5262 goto out;
5263 }
5264
5265 if (!ops->cpu_has_kvm_support()) {
5266 printk(KERN_ERR "kvm: no hardware support\n");
5267 r = -EOPNOTSUPP;
5268 goto out;
5269 }
5270 if (ops->disabled_by_bios()) {
5271 printk(KERN_ERR "kvm: disabled by bios\n");
5272 r = -EOPNOTSUPP;
5273 goto out;
5274 }
5275
5276 r = -ENOMEM;
5277 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5278 if (!shared_msrs) {
5279 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5280 goto out;
5281 }
5282
5283 r = kvm_mmu_module_init();
5284 if (r)
5285 goto out_free_percpu;
5286
5287 kvm_set_mmio_spte_mask();
5288 kvm_init_msr_list();
5289
5290 kvm_x86_ops = ops;
5291 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5292 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5293
5294 kvm_timer_init();
5295
5296 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5297
5298 if (cpu_has_xsave)
5299 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5300
5301 kvm_lapic_init();
5302 #ifdef CONFIG_X86_64
5303 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5304 #endif
5305
5306 return 0;
5307
5308 out_free_percpu:
5309 free_percpu(shared_msrs);
5310 out:
5311 return r;
5312 }
5313
5314 void kvm_arch_exit(void)
5315 {
5316 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5317
5318 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5319 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5320 CPUFREQ_TRANSITION_NOTIFIER);
5321 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5322 #ifdef CONFIG_X86_64
5323 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5324 #endif
5325 kvm_x86_ops = NULL;
5326 kvm_mmu_module_exit();
5327 free_percpu(shared_msrs);
5328 }
5329
5330 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5331 {
5332 ++vcpu->stat.halt_exits;
5333 if (irqchip_in_kernel(vcpu->kvm)) {
5334 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5335 return 1;
5336 } else {
5337 vcpu->run->exit_reason = KVM_EXIT_HLT;
5338 return 0;
5339 }
5340 }
5341 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5342
5343 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5344 {
5345 u64 param, ingpa, outgpa, ret;
5346 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5347 bool fast, longmode;
5348 int cs_db, cs_l;
5349
5350 /*
5351 * hypercall generates UD from non zero cpl and real mode
5352 * per HYPER-V spec
5353 */
5354 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5355 kvm_queue_exception(vcpu, UD_VECTOR);
5356 return 0;
5357 }
5358
5359 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5360 longmode = is_long_mode(vcpu) && cs_l == 1;
5361
5362 if (!longmode) {
5363 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5364 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5365 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5366 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5367 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5368 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5369 }
5370 #ifdef CONFIG_X86_64
5371 else {
5372 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5373 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5374 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5375 }
5376 #endif
5377
5378 code = param & 0xffff;
5379 fast = (param >> 16) & 0x1;
5380 rep_cnt = (param >> 32) & 0xfff;
5381 rep_idx = (param >> 48) & 0xfff;
5382
5383 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5384
5385 switch (code) {
5386 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5387 kvm_vcpu_on_spin(vcpu);
5388 break;
5389 default:
5390 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5391 break;
5392 }
5393
5394 ret = res | (((u64)rep_done & 0xfff) << 32);
5395 if (longmode) {
5396 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5397 } else {
5398 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5399 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5400 }
5401
5402 return 1;
5403 }
5404
5405 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5406 {
5407 unsigned long nr, a0, a1, a2, a3, ret;
5408 int r = 1;
5409
5410 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5411 return kvm_hv_hypercall(vcpu);
5412
5413 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5414 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5415 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5416 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5417 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5418
5419 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5420
5421 if (!is_long_mode(vcpu)) {
5422 nr &= 0xFFFFFFFF;
5423 a0 &= 0xFFFFFFFF;
5424 a1 &= 0xFFFFFFFF;
5425 a2 &= 0xFFFFFFFF;
5426 a3 &= 0xFFFFFFFF;
5427 }
5428
5429 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5430 ret = -KVM_EPERM;
5431 goto out;
5432 }
5433
5434 switch (nr) {
5435 case KVM_HC_VAPIC_POLL_IRQ:
5436 ret = 0;
5437 break;
5438 default:
5439 ret = -KVM_ENOSYS;
5440 break;
5441 }
5442 out:
5443 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5444 ++vcpu->stat.hypercalls;
5445 return r;
5446 }
5447 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5448
5449 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5450 {
5451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5452 char instruction[3];
5453 unsigned long rip = kvm_rip_read(vcpu);
5454
5455 /*
5456 * Blow out the MMU to ensure that no other VCPU has an active mapping
5457 * to ensure that the updated hypercall appears atomically across all
5458 * VCPUs.
5459 */
5460 kvm_mmu_zap_all(vcpu->kvm);
5461
5462 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5463
5464 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5465 }
5466
5467 /*
5468 * Check if userspace requested an interrupt window, and that the
5469 * interrupt window is open.
5470 *
5471 * No need to exit to userspace if we already have an interrupt queued.
5472 */
5473 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5474 {
5475 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5476 vcpu->run->request_interrupt_window &&
5477 kvm_arch_interrupt_allowed(vcpu));
5478 }
5479
5480 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5481 {
5482 struct kvm_run *kvm_run = vcpu->run;
5483
5484 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5485 kvm_run->cr8 = kvm_get_cr8(vcpu);
5486 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5487 if (irqchip_in_kernel(vcpu->kvm))
5488 kvm_run->ready_for_interrupt_injection = 1;
5489 else
5490 kvm_run->ready_for_interrupt_injection =
5491 kvm_arch_interrupt_allowed(vcpu) &&
5492 !kvm_cpu_has_interrupt(vcpu) &&
5493 !kvm_event_needs_reinjection(vcpu);
5494 }
5495
5496 static int vapic_enter(struct kvm_vcpu *vcpu)
5497 {
5498 struct kvm_lapic *apic = vcpu->arch.apic;
5499 struct page *page;
5500
5501 if (!apic || !apic->vapic_addr)
5502 return 0;
5503
5504 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5505 if (is_error_page(page))
5506 return -EFAULT;
5507
5508 vcpu->arch.apic->vapic_page = page;
5509 return 0;
5510 }
5511
5512 static void vapic_exit(struct kvm_vcpu *vcpu)
5513 {
5514 struct kvm_lapic *apic = vcpu->arch.apic;
5515 int idx;
5516
5517 if (!apic || !apic->vapic_addr)
5518 return;
5519
5520 idx = srcu_read_lock(&vcpu->kvm->srcu);
5521 kvm_release_page_dirty(apic->vapic_page);
5522 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5523 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5524 }
5525
5526 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5527 {
5528 int max_irr, tpr;
5529
5530 if (!kvm_x86_ops->update_cr8_intercept)
5531 return;
5532
5533 if (!vcpu->arch.apic)
5534 return;
5535
5536 if (!vcpu->arch.apic->vapic_addr)
5537 max_irr = kvm_lapic_find_highest_irr(vcpu);
5538 else
5539 max_irr = -1;
5540
5541 if (max_irr != -1)
5542 max_irr >>= 4;
5543
5544 tpr = kvm_lapic_get_cr8(vcpu);
5545
5546 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5547 }
5548
5549 static void inject_pending_event(struct kvm_vcpu *vcpu)
5550 {
5551 /* try to reinject previous events if any */
5552 if (vcpu->arch.exception.pending) {
5553 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5554 vcpu->arch.exception.has_error_code,
5555 vcpu->arch.exception.error_code);
5556 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5557 vcpu->arch.exception.has_error_code,
5558 vcpu->arch.exception.error_code,
5559 vcpu->arch.exception.reinject);
5560 return;
5561 }
5562
5563 if (vcpu->arch.nmi_injected) {
5564 kvm_x86_ops->set_nmi(vcpu);
5565 return;
5566 }
5567
5568 if (vcpu->arch.interrupt.pending) {
5569 kvm_x86_ops->set_irq(vcpu);
5570 return;
5571 }
5572
5573 /* try to inject new event if pending */
5574 if (vcpu->arch.nmi_pending) {
5575 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5576 --vcpu->arch.nmi_pending;
5577 vcpu->arch.nmi_injected = true;
5578 kvm_x86_ops->set_nmi(vcpu);
5579 }
5580 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5581 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5582 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5583 false);
5584 kvm_x86_ops->set_irq(vcpu);
5585 }
5586 }
5587 }
5588
5589 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5590 {
5591 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5592 !vcpu->guest_xcr0_loaded) {
5593 /* kvm_set_xcr() also depends on this */
5594 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5595 vcpu->guest_xcr0_loaded = 1;
5596 }
5597 }
5598
5599 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5600 {
5601 if (vcpu->guest_xcr0_loaded) {
5602 if (vcpu->arch.xcr0 != host_xcr0)
5603 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5604 vcpu->guest_xcr0_loaded = 0;
5605 }
5606 }
5607
5608 static void process_nmi(struct kvm_vcpu *vcpu)
5609 {
5610 unsigned limit = 2;
5611
5612 /*
5613 * x86 is limited to one NMI running, and one NMI pending after it.
5614 * If an NMI is already in progress, limit further NMIs to just one.
5615 * Otherwise, allow two (and we'll inject the first one immediately).
5616 */
5617 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5618 limit = 1;
5619
5620 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5621 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5622 kvm_make_request(KVM_REQ_EVENT, vcpu);
5623 }
5624
5625 static void kvm_gen_update_masterclock(struct kvm *kvm)
5626 {
5627 #ifdef CONFIG_X86_64
5628 int i;
5629 struct kvm_vcpu *vcpu;
5630 struct kvm_arch *ka = &kvm->arch;
5631
5632 spin_lock(&ka->pvclock_gtod_sync_lock);
5633 kvm_make_mclock_inprogress_request(kvm);
5634 /* no guest entries from this point */
5635 pvclock_update_vm_gtod_copy(kvm);
5636
5637 kvm_for_each_vcpu(i, vcpu, kvm)
5638 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5639
5640 /* guest entries allowed */
5641 kvm_for_each_vcpu(i, vcpu, kvm)
5642 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5643
5644 spin_unlock(&ka->pvclock_gtod_sync_lock);
5645 #endif
5646 }
5647
5648 static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5649 {
5650 u64 eoi_exit_bitmap[4];
5651
5652 memset(eoi_exit_bitmap, 0, 32);
5653
5654 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5655 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5656 }
5657
5658 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5659 {
5660 int r;
5661 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5662 vcpu->run->request_interrupt_window;
5663 bool req_immediate_exit = 0;
5664
5665 if (vcpu->requests) {
5666 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5667 kvm_mmu_unload(vcpu);
5668 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5669 __kvm_migrate_timers(vcpu);
5670 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5671 kvm_gen_update_masterclock(vcpu->kvm);
5672 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5673 r = kvm_guest_time_update(vcpu);
5674 if (unlikely(r))
5675 goto out;
5676 }
5677 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5678 kvm_mmu_sync_roots(vcpu);
5679 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5680 kvm_x86_ops->tlb_flush(vcpu);
5681 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5682 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5683 r = 0;
5684 goto out;
5685 }
5686 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5687 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5688 r = 0;
5689 goto out;
5690 }
5691 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5692 vcpu->fpu_active = 0;
5693 kvm_x86_ops->fpu_deactivate(vcpu);
5694 }
5695 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5696 /* Page is swapped out. Do synthetic halt */
5697 vcpu->arch.apf.halted = true;
5698 r = 1;
5699 goto out;
5700 }
5701 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5702 record_steal_time(vcpu);
5703 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5704 process_nmi(vcpu);
5705 req_immediate_exit =
5706 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5707 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5708 kvm_handle_pmu_event(vcpu);
5709 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5710 kvm_deliver_pmi(vcpu);
5711 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5712 update_eoi_exitmap(vcpu);
5713 }
5714
5715 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5716 inject_pending_event(vcpu);
5717
5718 /* enable NMI/IRQ window open exits if needed */
5719 if (vcpu->arch.nmi_pending)
5720 kvm_x86_ops->enable_nmi_window(vcpu);
5721 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5722 kvm_x86_ops->enable_irq_window(vcpu);
5723
5724 if (kvm_lapic_enabled(vcpu)) {
5725 /*
5726 * Update architecture specific hints for APIC
5727 * virtual interrupt delivery.
5728 */
5729 if (kvm_x86_ops->hwapic_irr_update)
5730 kvm_x86_ops->hwapic_irr_update(vcpu,
5731 kvm_lapic_find_highest_irr(vcpu));
5732 update_cr8_intercept(vcpu);
5733 kvm_lapic_sync_to_vapic(vcpu);
5734 }
5735 }
5736
5737 r = kvm_mmu_reload(vcpu);
5738 if (unlikely(r)) {
5739 goto cancel_injection;
5740 }
5741
5742 preempt_disable();
5743
5744 kvm_x86_ops->prepare_guest_switch(vcpu);
5745 if (vcpu->fpu_active)
5746 kvm_load_guest_fpu(vcpu);
5747 kvm_load_guest_xcr0(vcpu);
5748
5749 vcpu->mode = IN_GUEST_MODE;
5750
5751 /* We should set ->mode before check ->requests,
5752 * see the comment in make_all_cpus_request.
5753 */
5754 smp_mb();
5755
5756 local_irq_disable();
5757
5758 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5759 || need_resched() || signal_pending(current)) {
5760 vcpu->mode = OUTSIDE_GUEST_MODE;
5761 smp_wmb();
5762 local_irq_enable();
5763 preempt_enable();
5764 r = 1;
5765 goto cancel_injection;
5766 }
5767
5768 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5769
5770 if (req_immediate_exit)
5771 smp_send_reschedule(vcpu->cpu);
5772
5773 kvm_guest_enter();
5774
5775 if (unlikely(vcpu->arch.switch_db_regs)) {
5776 set_debugreg(0, 7);
5777 set_debugreg(vcpu->arch.eff_db[0], 0);
5778 set_debugreg(vcpu->arch.eff_db[1], 1);
5779 set_debugreg(vcpu->arch.eff_db[2], 2);
5780 set_debugreg(vcpu->arch.eff_db[3], 3);
5781 }
5782
5783 trace_kvm_entry(vcpu->vcpu_id);
5784 kvm_x86_ops->run(vcpu);
5785
5786 /*
5787 * If the guest has used debug registers, at least dr7
5788 * will be disabled while returning to the host.
5789 * If we don't have active breakpoints in the host, we don't
5790 * care about the messed up debug address registers. But if
5791 * we have some of them active, restore the old state.
5792 */
5793 if (hw_breakpoint_active())
5794 hw_breakpoint_restore();
5795
5796 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5797 native_read_tsc());
5798
5799 vcpu->mode = OUTSIDE_GUEST_MODE;
5800 smp_wmb();
5801 local_irq_enable();
5802
5803 ++vcpu->stat.exits;
5804
5805 /*
5806 * We must have an instruction between local_irq_enable() and
5807 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5808 * the interrupt shadow. The stat.exits increment will do nicely.
5809 * But we need to prevent reordering, hence this barrier():
5810 */
5811 barrier();
5812
5813 kvm_guest_exit();
5814
5815 preempt_enable();
5816
5817 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5818
5819 /*
5820 * Profile KVM exit RIPs:
5821 */
5822 if (unlikely(prof_on == KVM_PROFILING)) {
5823 unsigned long rip = kvm_rip_read(vcpu);
5824 profile_hit(KVM_PROFILING, (void *)rip);
5825 }
5826
5827 if (unlikely(vcpu->arch.tsc_always_catchup))
5828 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5829
5830 if (vcpu->arch.apic_attention)
5831 kvm_lapic_sync_from_vapic(vcpu);
5832
5833 r = kvm_x86_ops->handle_exit(vcpu);
5834 return r;
5835
5836 cancel_injection:
5837 kvm_x86_ops->cancel_injection(vcpu);
5838 if (unlikely(vcpu->arch.apic_attention))
5839 kvm_lapic_sync_from_vapic(vcpu);
5840 out:
5841 return r;
5842 }
5843
5844
5845 static int __vcpu_run(struct kvm_vcpu *vcpu)
5846 {
5847 int r;
5848 struct kvm *kvm = vcpu->kvm;
5849
5850 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5851 pr_debug("vcpu %d received sipi with vector # %x\n",
5852 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5853 kvm_lapic_reset(vcpu);
5854 r = kvm_vcpu_reset(vcpu);
5855 if (r)
5856 return r;
5857 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5858 }
5859
5860 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5861 r = vapic_enter(vcpu);
5862 if (r) {
5863 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5864 return r;
5865 }
5866
5867 r = 1;
5868 while (r > 0) {
5869 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5870 !vcpu->arch.apf.halted)
5871 r = vcpu_enter_guest(vcpu);
5872 else {
5873 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5874 kvm_vcpu_block(vcpu);
5875 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5876 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5877 {
5878 switch(vcpu->arch.mp_state) {
5879 case KVM_MP_STATE_HALTED:
5880 vcpu->arch.mp_state =
5881 KVM_MP_STATE_RUNNABLE;
5882 case KVM_MP_STATE_RUNNABLE:
5883 vcpu->arch.apf.halted = false;
5884 break;
5885 case KVM_MP_STATE_SIPI_RECEIVED:
5886 default:
5887 r = -EINTR;
5888 break;
5889 }
5890 }
5891 }
5892
5893 if (r <= 0)
5894 break;
5895
5896 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5897 if (kvm_cpu_has_pending_timer(vcpu))
5898 kvm_inject_pending_timer_irqs(vcpu);
5899
5900 if (dm_request_for_irq_injection(vcpu)) {
5901 r = -EINTR;
5902 vcpu->run->exit_reason = KVM_EXIT_INTR;
5903 ++vcpu->stat.request_irq_exits;
5904 }
5905
5906 kvm_check_async_pf_completion(vcpu);
5907
5908 if (signal_pending(current)) {
5909 r = -EINTR;
5910 vcpu->run->exit_reason = KVM_EXIT_INTR;
5911 ++vcpu->stat.signal_exits;
5912 }
5913 if (need_resched()) {
5914 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5915 kvm_resched(vcpu);
5916 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5917 }
5918 }
5919
5920 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5921
5922 vapic_exit(vcpu);
5923
5924 return r;
5925 }
5926
5927 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5928 {
5929 int r;
5930 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5931 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5932 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5933 if (r != EMULATE_DONE)
5934 return 0;
5935 return 1;
5936 }
5937
5938 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5939 {
5940 BUG_ON(!vcpu->arch.pio.count);
5941
5942 return complete_emulated_io(vcpu);
5943 }
5944
5945 /*
5946 * Implements the following, as a state machine:
5947 *
5948 * read:
5949 * for each fragment
5950 * for each mmio piece in the fragment
5951 * write gpa, len
5952 * exit
5953 * copy data
5954 * execute insn
5955 *
5956 * write:
5957 * for each fragment
5958 * for each mmio piece in the fragment
5959 * write gpa, len
5960 * copy data
5961 * exit
5962 */
5963 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5964 {
5965 struct kvm_run *run = vcpu->run;
5966 struct kvm_mmio_fragment *frag;
5967 unsigned len;
5968
5969 BUG_ON(!vcpu->mmio_needed);
5970
5971 /* Complete previous fragment */
5972 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5973 len = min(8u, frag->len);
5974 if (!vcpu->mmio_is_write)
5975 memcpy(frag->data, run->mmio.data, len);
5976
5977 if (frag->len <= 8) {
5978 /* Switch to the next fragment. */
5979 frag++;
5980 vcpu->mmio_cur_fragment++;
5981 } else {
5982 /* Go forward to the next mmio piece. */
5983 frag->data += len;
5984 frag->gpa += len;
5985 frag->len -= len;
5986 }
5987
5988 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5989 vcpu->mmio_needed = 0;
5990 if (vcpu->mmio_is_write)
5991 return 1;
5992 vcpu->mmio_read_completed = 1;
5993 return complete_emulated_io(vcpu);
5994 }
5995
5996 run->exit_reason = KVM_EXIT_MMIO;
5997 run->mmio.phys_addr = frag->gpa;
5998 if (vcpu->mmio_is_write)
5999 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6000 run->mmio.len = min(8u, frag->len);
6001 run->mmio.is_write = vcpu->mmio_is_write;
6002 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6003 return 0;
6004 }
6005
6006
6007 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6008 {
6009 int r;
6010 sigset_t sigsaved;
6011
6012 if (!tsk_used_math(current) && init_fpu(current))
6013 return -ENOMEM;
6014
6015 if (vcpu->sigset_active)
6016 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6017
6018 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6019 kvm_vcpu_block(vcpu);
6020 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6021 r = -EAGAIN;
6022 goto out;
6023 }
6024
6025 /* re-sync apic's tpr */
6026 if (!irqchip_in_kernel(vcpu->kvm)) {
6027 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6028 r = -EINVAL;
6029 goto out;
6030 }
6031 }
6032
6033 if (unlikely(vcpu->arch.complete_userspace_io)) {
6034 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6035 vcpu->arch.complete_userspace_io = NULL;
6036 r = cui(vcpu);
6037 if (r <= 0)
6038 goto out;
6039 } else
6040 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6041
6042 r = __vcpu_run(vcpu);
6043
6044 out:
6045 post_kvm_run_save(vcpu);
6046 if (vcpu->sigset_active)
6047 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6048
6049 return r;
6050 }
6051
6052 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6053 {
6054 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6055 /*
6056 * We are here if userspace calls get_regs() in the middle of
6057 * instruction emulation. Registers state needs to be copied
6058 * back from emulation context to vcpu. Userspace shouldn't do
6059 * that usually, but some bad designed PV devices (vmware
6060 * backdoor interface) need this to work
6061 */
6062 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6063 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6064 }
6065 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6066 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6067 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6068 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6069 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6070 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6071 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6072 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6073 #ifdef CONFIG_X86_64
6074 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6075 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6076 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6077 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6078 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6079 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6080 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6081 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6082 #endif
6083
6084 regs->rip = kvm_rip_read(vcpu);
6085 regs->rflags = kvm_get_rflags(vcpu);
6086
6087 return 0;
6088 }
6089
6090 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6091 {
6092 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6093 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6094
6095 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6096 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6097 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6098 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6099 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6100 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6101 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6102 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6103 #ifdef CONFIG_X86_64
6104 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6105 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6106 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6107 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6108 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6109 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6110 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6111 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6112 #endif
6113
6114 kvm_rip_write(vcpu, regs->rip);
6115 kvm_set_rflags(vcpu, regs->rflags);
6116
6117 vcpu->arch.exception.pending = false;
6118
6119 kvm_make_request(KVM_REQ_EVENT, vcpu);
6120
6121 return 0;
6122 }
6123
6124 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6125 {
6126 struct kvm_segment cs;
6127
6128 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6129 *db = cs.db;
6130 *l = cs.l;
6131 }
6132 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6133
6134 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6135 struct kvm_sregs *sregs)
6136 {
6137 struct desc_ptr dt;
6138
6139 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6140 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6141 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6142 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6143 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6144 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6145
6146 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6147 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6148
6149 kvm_x86_ops->get_idt(vcpu, &dt);
6150 sregs->idt.limit = dt.size;
6151 sregs->idt.base = dt.address;
6152 kvm_x86_ops->get_gdt(vcpu, &dt);
6153 sregs->gdt.limit = dt.size;
6154 sregs->gdt.base = dt.address;
6155
6156 sregs->cr0 = kvm_read_cr0(vcpu);
6157 sregs->cr2 = vcpu->arch.cr2;
6158 sregs->cr3 = kvm_read_cr3(vcpu);
6159 sregs->cr4 = kvm_read_cr4(vcpu);
6160 sregs->cr8 = kvm_get_cr8(vcpu);
6161 sregs->efer = vcpu->arch.efer;
6162 sregs->apic_base = kvm_get_apic_base(vcpu);
6163
6164 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6165
6166 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6167 set_bit(vcpu->arch.interrupt.nr,
6168 (unsigned long *)sregs->interrupt_bitmap);
6169
6170 return 0;
6171 }
6172
6173 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6174 struct kvm_mp_state *mp_state)
6175 {
6176 mp_state->mp_state = vcpu->arch.mp_state;
6177 return 0;
6178 }
6179
6180 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6181 struct kvm_mp_state *mp_state)
6182 {
6183 vcpu->arch.mp_state = mp_state->mp_state;
6184 kvm_make_request(KVM_REQ_EVENT, vcpu);
6185 return 0;
6186 }
6187
6188 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6189 int reason, bool has_error_code, u32 error_code)
6190 {
6191 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6192 int ret;
6193
6194 init_emulate_ctxt(vcpu);
6195
6196 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6197 has_error_code, error_code);
6198
6199 if (ret)
6200 return EMULATE_FAIL;
6201
6202 kvm_rip_write(vcpu, ctxt->eip);
6203 kvm_set_rflags(vcpu, ctxt->eflags);
6204 kvm_make_request(KVM_REQ_EVENT, vcpu);
6205 return EMULATE_DONE;
6206 }
6207 EXPORT_SYMBOL_GPL(kvm_task_switch);
6208
6209 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6210 struct kvm_sregs *sregs)
6211 {
6212 int mmu_reset_needed = 0;
6213 int pending_vec, max_bits, idx;
6214 struct desc_ptr dt;
6215
6216 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6217 return -EINVAL;
6218
6219 dt.size = sregs->idt.limit;
6220 dt.address = sregs->idt.base;
6221 kvm_x86_ops->set_idt(vcpu, &dt);
6222 dt.size = sregs->gdt.limit;
6223 dt.address = sregs->gdt.base;
6224 kvm_x86_ops->set_gdt(vcpu, &dt);
6225
6226 vcpu->arch.cr2 = sregs->cr2;
6227 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6228 vcpu->arch.cr3 = sregs->cr3;
6229 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6230
6231 kvm_set_cr8(vcpu, sregs->cr8);
6232
6233 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6234 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6235 kvm_set_apic_base(vcpu, sregs->apic_base);
6236
6237 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6238 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6239 vcpu->arch.cr0 = sregs->cr0;
6240
6241 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6242 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6243 if (sregs->cr4 & X86_CR4_OSXSAVE)
6244 kvm_update_cpuid(vcpu);
6245
6246 idx = srcu_read_lock(&vcpu->kvm->srcu);
6247 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6248 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6249 mmu_reset_needed = 1;
6250 }
6251 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6252
6253 if (mmu_reset_needed)
6254 kvm_mmu_reset_context(vcpu);
6255
6256 max_bits = KVM_NR_INTERRUPTS;
6257 pending_vec = find_first_bit(
6258 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6259 if (pending_vec < max_bits) {
6260 kvm_queue_interrupt(vcpu, pending_vec, false);
6261 pr_debug("Set back pending irq %d\n", pending_vec);
6262 }
6263
6264 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6265 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6266 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6267 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6268 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6269 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6270
6271 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6272 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6273
6274 update_cr8_intercept(vcpu);
6275
6276 /* Older userspace won't unhalt the vcpu on reset. */
6277 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6278 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6279 !is_protmode(vcpu))
6280 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6281
6282 kvm_make_request(KVM_REQ_EVENT, vcpu);
6283
6284 return 0;
6285 }
6286
6287 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6288 struct kvm_guest_debug *dbg)
6289 {
6290 unsigned long rflags;
6291 int i, r;
6292
6293 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6294 r = -EBUSY;
6295 if (vcpu->arch.exception.pending)
6296 goto out;
6297 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6298 kvm_queue_exception(vcpu, DB_VECTOR);
6299 else
6300 kvm_queue_exception(vcpu, BP_VECTOR);
6301 }
6302
6303 /*
6304 * Read rflags as long as potentially injected trace flags are still
6305 * filtered out.
6306 */
6307 rflags = kvm_get_rflags(vcpu);
6308
6309 vcpu->guest_debug = dbg->control;
6310 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6311 vcpu->guest_debug = 0;
6312
6313 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6314 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6315 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6316 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6317 } else {
6318 for (i = 0; i < KVM_NR_DB_REGS; i++)
6319 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6320 }
6321 kvm_update_dr7(vcpu);
6322
6323 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6324 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6325 get_segment_base(vcpu, VCPU_SREG_CS);
6326
6327 /*
6328 * Trigger an rflags update that will inject or remove the trace
6329 * flags.
6330 */
6331 kvm_set_rflags(vcpu, rflags);
6332
6333 kvm_x86_ops->update_db_bp_intercept(vcpu);
6334
6335 r = 0;
6336
6337 out:
6338
6339 return r;
6340 }
6341
6342 /*
6343 * Translate a guest virtual address to a guest physical address.
6344 */
6345 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6346 struct kvm_translation *tr)
6347 {
6348 unsigned long vaddr = tr->linear_address;
6349 gpa_t gpa;
6350 int idx;
6351
6352 idx = srcu_read_lock(&vcpu->kvm->srcu);
6353 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6355 tr->physical_address = gpa;
6356 tr->valid = gpa != UNMAPPED_GVA;
6357 tr->writeable = 1;
6358 tr->usermode = 0;
6359
6360 return 0;
6361 }
6362
6363 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6364 {
6365 struct i387_fxsave_struct *fxsave =
6366 &vcpu->arch.guest_fpu.state->fxsave;
6367
6368 memcpy(fpu->fpr, fxsave->st_space, 128);
6369 fpu->fcw = fxsave->cwd;
6370 fpu->fsw = fxsave->swd;
6371 fpu->ftwx = fxsave->twd;
6372 fpu->last_opcode = fxsave->fop;
6373 fpu->last_ip = fxsave->rip;
6374 fpu->last_dp = fxsave->rdp;
6375 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6376
6377 return 0;
6378 }
6379
6380 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6381 {
6382 struct i387_fxsave_struct *fxsave =
6383 &vcpu->arch.guest_fpu.state->fxsave;
6384
6385 memcpy(fxsave->st_space, fpu->fpr, 128);
6386 fxsave->cwd = fpu->fcw;
6387 fxsave->swd = fpu->fsw;
6388 fxsave->twd = fpu->ftwx;
6389 fxsave->fop = fpu->last_opcode;
6390 fxsave->rip = fpu->last_ip;
6391 fxsave->rdp = fpu->last_dp;
6392 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6393
6394 return 0;
6395 }
6396
6397 int fx_init(struct kvm_vcpu *vcpu)
6398 {
6399 int err;
6400
6401 err = fpu_alloc(&vcpu->arch.guest_fpu);
6402 if (err)
6403 return err;
6404
6405 fpu_finit(&vcpu->arch.guest_fpu);
6406
6407 /*
6408 * Ensure guest xcr0 is valid for loading
6409 */
6410 vcpu->arch.xcr0 = XSTATE_FP;
6411
6412 vcpu->arch.cr0 |= X86_CR0_ET;
6413
6414 return 0;
6415 }
6416 EXPORT_SYMBOL_GPL(fx_init);
6417
6418 static void fx_free(struct kvm_vcpu *vcpu)
6419 {
6420 fpu_free(&vcpu->arch.guest_fpu);
6421 }
6422
6423 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6424 {
6425 if (vcpu->guest_fpu_loaded)
6426 return;
6427
6428 /*
6429 * Restore all possible states in the guest,
6430 * and assume host would use all available bits.
6431 * Guest xcr0 would be loaded later.
6432 */
6433 kvm_put_guest_xcr0(vcpu);
6434 vcpu->guest_fpu_loaded = 1;
6435 __kernel_fpu_begin();
6436 fpu_restore_checking(&vcpu->arch.guest_fpu);
6437 trace_kvm_fpu(1);
6438 }
6439
6440 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6441 {
6442 kvm_put_guest_xcr0(vcpu);
6443
6444 if (!vcpu->guest_fpu_loaded)
6445 return;
6446
6447 vcpu->guest_fpu_loaded = 0;
6448 fpu_save_init(&vcpu->arch.guest_fpu);
6449 __kernel_fpu_end();
6450 ++vcpu->stat.fpu_reload;
6451 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6452 trace_kvm_fpu(0);
6453 }
6454
6455 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6456 {
6457 kvmclock_reset(vcpu);
6458
6459 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6460 fx_free(vcpu);
6461 kvm_x86_ops->vcpu_free(vcpu);
6462 }
6463
6464 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6465 unsigned int id)
6466 {
6467 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6468 printk_once(KERN_WARNING
6469 "kvm: SMP vm created on host with unstable TSC; "
6470 "guest TSC will not be reliable\n");
6471 return kvm_x86_ops->vcpu_create(kvm, id);
6472 }
6473
6474 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6475 {
6476 int r;
6477
6478 vcpu->arch.mtrr_state.have_fixed = 1;
6479 r = vcpu_load(vcpu);
6480 if (r)
6481 return r;
6482 r = kvm_vcpu_reset(vcpu);
6483 if (r == 0)
6484 r = kvm_mmu_setup(vcpu);
6485 vcpu_put(vcpu);
6486
6487 return r;
6488 }
6489
6490 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6491 {
6492 int r;
6493 struct msr_data msr;
6494
6495 r = vcpu_load(vcpu);
6496 if (r)
6497 return r;
6498 msr.data = 0x0;
6499 msr.index = MSR_IA32_TSC;
6500 msr.host_initiated = true;
6501 kvm_write_tsc(vcpu, &msr);
6502 vcpu_put(vcpu);
6503
6504 return r;
6505 }
6506
6507 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6508 {
6509 int r;
6510 vcpu->arch.apf.msr_val = 0;
6511
6512 r = vcpu_load(vcpu);
6513 BUG_ON(r);
6514 kvm_mmu_unload(vcpu);
6515 vcpu_put(vcpu);
6516
6517 fx_free(vcpu);
6518 kvm_x86_ops->vcpu_free(vcpu);
6519 }
6520
6521 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6522 {
6523 atomic_set(&vcpu->arch.nmi_queued, 0);
6524 vcpu->arch.nmi_pending = 0;
6525 vcpu->arch.nmi_injected = false;
6526
6527 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6528 vcpu->arch.dr6 = DR6_FIXED_1;
6529 vcpu->arch.dr7 = DR7_FIXED_1;
6530 kvm_update_dr7(vcpu);
6531
6532 kvm_make_request(KVM_REQ_EVENT, vcpu);
6533 vcpu->arch.apf.msr_val = 0;
6534 vcpu->arch.st.msr_val = 0;
6535
6536 kvmclock_reset(vcpu);
6537
6538 kvm_clear_async_pf_completion_queue(vcpu);
6539 kvm_async_pf_hash_reset(vcpu);
6540 vcpu->arch.apf.halted = false;
6541
6542 kvm_pmu_reset(vcpu);
6543
6544 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6545 vcpu->arch.regs_avail = ~0;
6546 vcpu->arch.regs_dirty = ~0;
6547
6548 return kvm_x86_ops->vcpu_reset(vcpu);
6549 }
6550
6551 int kvm_arch_hardware_enable(void *garbage)
6552 {
6553 struct kvm *kvm;
6554 struct kvm_vcpu *vcpu;
6555 int i;
6556 int ret;
6557 u64 local_tsc;
6558 u64 max_tsc = 0;
6559 bool stable, backwards_tsc = false;
6560
6561 kvm_shared_msr_cpu_online();
6562 ret = kvm_x86_ops->hardware_enable(garbage);
6563 if (ret != 0)
6564 return ret;
6565
6566 local_tsc = native_read_tsc();
6567 stable = !check_tsc_unstable();
6568 list_for_each_entry(kvm, &vm_list, vm_list) {
6569 kvm_for_each_vcpu(i, vcpu, kvm) {
6570 if (!stable && vcpu->cpu == smp_processor_id())
6571 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6572 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6573 backwards_tsc = true;
6574 if (vcpu->arch.last_host_tsc > max_tsc)
6575 max_tsc = vcpu->arch.last_host_tsc;
6576 }
6577 }
6578 }
6579
6580 /*
6581 * Sometimes, even reliable TSCs go backwards. This happens on
6582 * platforms that reset TSC during suspend or hibernate actions, but
6583 * maintain synchronization. We must compensate. Fortunately, we can
6584 * detect that condition here, which happens early in CPU bringup,
6585 * before any KVM threads can be running. Unfortunately, we can't
6586 * bring the TSCs fully up to date with real time, as we aren't yet far
6587 * enough into CPU bringup that we know how much real time has actually
6588 * elapsed; our helper function, get_kernel_ns() will be using boot
6589 * variables that haven't been updated yet.
6590 *
6591 * So we simply find the maximum observed TSC above, then record the
6592 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6593 * the adjustment will be applied. Note that we accumulate
6594 * adjustments, in case multiple suspend cycles happen before some VCPU
6595 * gets a chance to run again. In the event that no KVM threads get a
6596 * chance to run, we will miss the entire elapsed period, as we'll have
6597 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6598 * loose cycle time. This isn't too big a deal, since the loss will be
6599 * uniform across all VCPUs (not to mention the scenario is extremely
6600 * unlikely). It is possible that a second hibernate recovery happens
6601 * much faster than a first, causing the observed TSC here to be
6602 * smaller; this would require additional padding adjustment, which is
6603 * why we set last_host_tsc to the local tsc observed here.
6604 *
6605 * N.B. - this code below runs only on platforms with reliable TSC,
6606 * as that is the only way backwards_tsc is set above. Also note
6607 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6608 * have the same delta_cyc adjustment applied if backwards_tsc
6609 * is detected. Note further, this adjustment is only done once,
6610 * as we reset last_host_tsc on all VCPUs to stop this from being
6611 * called multiple times (one for each physical CPU bringup).
6612 *
6613 * Platforms with unreliable TSCs don't have to deal with this, they
6614 * will be compensated by the logic in vcpu_load, which sets the TSC to
6615 * catchup mode. This will catchup all VCPUs to real time, but cannot
6616 * guarantee that they stay in perfect synchronization.
6617 */
6618 if (backwards_tsc) {
6619 u64 delta_cyc = max_tsc - local_tsc;
6620 list_for_each_entry(kvm, &vm_list, vm_list) {
6621 kvm_for_each_vcpu(i, vcpu, kvm) {
6622 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6623 vcpu->arch.last_host_tsc = local_tsc;
6624 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6625 &vcpu->requests);
6626 }
6627
6628 /*
6629 * We have to disable TSC offset matching.. if you were
6630 * booting a VM while issuing an S4 host suspend....
6631 * you may have some problem. Solving this issue is
6632 * left as an exercise to the reader.
6633 */
6634 kvm->arch.last_tsc_nsec = 0;
6635 kvm->arch.last_tsc_write = 0;
6636 }
6637
6638 }
6639 return 0;
6640 }
6641
6642 void kvm_arch_hardware_disable(void *garbage)
6643 {
6644 kvm_x86_ops->hardware_disable(garbage);
6645 drop_user_return_notifiers(garbage);
6646 }
6647
6648 int kvm_arch_hardware_setup(void)
6649 {
6650 return kvm_x86_ops->hardware_setup();
6651 }
6652
6653 void kvm_arch_hardware_unsetup(void)
6654 {
6655 kvm_x86_ops->hardware_unsetup();
6656 }
6657
6658 void kvm_arch_check_processor_compat(void *rtn)
6659 {
6660 kvm_x86_ops->check_processor_compatibility(rtn);
6661 }
6662
6663 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6664 {
6665 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6666 }
6667
6668 struct static_key kvm_no_apic_vcpu __read_mostly;
6669
6670 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6671 {
6672 struct page *page;
6673 struct kvm *kvm;
6674 int r;
6675
6676 BUG_ON(vcpu->kvm == NULL);
6677 kvm = vcpu->kvm;
6678
6679 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6680 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6681 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6682 else
6683 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6684
6685 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6686 if (!page) {
6687 r = -ENOMEM;
6688 goto fail;
6689 }
6690 vcpu->arch.pio_data = page_address(page);
6691
6692 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6693
6694 r = kvm_mmu_create(vcpu);
6695 if (r < 0)
6696 goto fail_free_pio_data;
6697
6698 if (irqchip_in_kernel(kvm)) {
6699 r = kvm_create_lapic(vcpu);
6700 if (r < 0)
6701 goto fail_mmu_destroy;
6702 } else
6703 static_key_slow_inc(&kvm_no_apic_vcpu);
6704
6705 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6706 GFP_KERNEL);
6707 if (!vcpu->arch.mce_banks) {
6708 r = -ENOMEM;
6709 goto fail_free_lapic;
6710 }
6711 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6712
6713 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6714 goto fail_free_mce_banks;
6715
6716 r = fx_init(vcpu);
6717 if (r)
6718 goto fail_free_wbinvd_dirty_mask;
6719
6720 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6721 kvm_async_pf_hash_reset(vcpu);
6722 kvm_pmu_init(vcpu);
6723
6724 return 0;
6725 fail_free_wbinvd_dirty_mask:
6726 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6727 fail_free_mce_banks:
6728 kfree(vcpu->arch.mce_banks);
6729 fail_free_lapic:
6730 kvm_free_lapic(vcpu);
6731 fail_mmu_destroy:
6732 kvm_mmu_destroy(vcpu);
6733 fail_free_pio_data:
6734 free_page((unsigned long)vcpu->arch.pio_data);
6735 fail:
6736 return r;
6737 }
6738
6739 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6740 {
6741 int idx;
6742
6743 kvm_pmu_destroy(vcpu);
6744 kfree(vcpu->arch.mce_banks);
6745 kvm_free_lapic(vcpu);
6746 idx = srcu_read_lock(&vcpu->kvm->srcu);
6747 kvm_mmu_destroy(vcpu);
6748 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6749 free_page((unsigned long)vcpu->arch.pio_data);
6750 if (!irqchip_in_kernel(vcpu->kvm))
6751 static_key_slow_dec(&kvm_no_apic_vcpu);
6752 }
6753
6754 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6755 {
6756 if (type)
6757 return -EINVAL;
6758
6759 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6760 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6761
6762 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6763 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6764 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6765 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6766 &kvm->arch.irq_sources_bitmap);
6767
6768 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6769 mutex_init(&kvm->arch.apic_map_lock);
6770 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6771
6772 pvclock_update_vm_gtod_copy(kvm);
6773
6774 return 0;
6775 }
6776
6777 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6778 {
6779 int r;
6780 r = vcpu_load(vcpu);
6781 BUG_ON(r);
6782 kvm_mmu_unload(vcpu);
6783 vcpu_put(vcpu);
6784 }
6785
6786 static void kvm_free_vcpus(struct kvm *kvm)
6787 {
6788 unsigned int i;
6789 struct kvm_vcpu *vcpu;
6790
6791 /*
6792 * Unpin any mmu pages first.
6793 */
6794 kvm_for_each_vcpu(i, vcpu, kvm) {
6795 kvm_clear_async_pf_completion_queue(vcpu);
6796 kvm_unload_vcpu_mmu(vcpu);
6797 }
6798 kvm_for_each_vcpu(i, vcpu, kvm)
6799 kvm_arch_vcpu_free(vcpu);
6800
6801 mutex_lock(&kvm->lock);
6802 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6803 kvm->vcpus[i] = NULL;
6804
6805 atomic_set(&kvm->online_vcpus, 0);
6806 mutex_unlock(&kvm->lock);
6807 }
6808
6809 void kvm_arch_sync_events(struct kvm *kvm)
6810 {
6811 kvm_free_all_assigned_devices(kvm);
6812 kvm_free_pit(kvm);
6813 }
6814
6815 void kvm_arch_destroy_vm(struct kvm *kvm)
6816 {
6817 kvm_iommu_unmap_guest(kvm);
6818 kfree(kvm->arch.vpic);
6819 kfree(kvm->arch.vioapic);
6820 kvm_free_vcpus(kvm);
6821 if (kvm->arch.apic_access_page)
6822 put_page(kvm->arch.apic_access_page);
6823 if (kvm->arch.ept_identity_pagetable)
6824 put_page(kvm->arch.ept_identity_pagetable);
6825 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6826 }
6827
6828 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6829 struct kvm_memory_slot *dont)
6830 {
6831 int i;
6832
6833 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6834 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6835 kvm_kvfree(free->arch.rmap[i]);
6836 free->arch.rmap[i] = NULL;
6837 }
6838 if (i == 0)
6839 continue;
6840
6841 if (!dont || free->arch.lpage_info[i - 1] !=
6842 dont->arch.lpage_info[i - 1]) {
6843 kvm_kvfree(free->arch.lpage_info[i - 1]);
6844 free->arch.lpage_info[i - 1] = NULL;
6845 }
6846 }
6847 }
6848
6849 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6850 {
6851 int i;
6852
6853 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6854 unsigned long ugfn;
6855 int lpages;
6856 int level = i + 1;
6857
6858 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6859 slot->base_gfn, level) + 1;
6860
6861 slot->arch.rmap[i] =
6862 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6863 if (!slot->arch.rmap[i])
6864 goto out_free;
6865 if (i == 0)
6866 continue;
6867
6868 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6869 sizeof(*slot->arch.lpage_info[i - 1]));
6870 if (!slot->arch.lpage_info[i - 1])
6871 goto out_free;
6872
6873 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6874 slot->arch.lpage_info[i - 1][0].write_count = 1;
6875 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6876 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6877 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6878 /*
6879 * If the gfn and userspace address are not aligned wrt each
6880 * other, or if explicitly asked to, disable large page
6881 * support for this slot
6882 */
6883 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6884 !kvm_largepages_enabled()) {
6885 unsigned long j;
6886
6887 for (j = 0; j < lpages; ++j)
6888 slot->arch.lpage_info[i - 1][j].write_count = 1;
6889 }
6890 }
6891
6892 return 0;
6893
6894 out_free:
6895 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6896 kvm_kvfree(slot->arch.rmap[i]);
6897 slot->arch.rmap[i] = NULL;
6898 if (i == 0)
6899 continue;
6900
6901 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6902 slot->arch.lpage_info[i - 1] = NULL;
6903 }
6904 return -ENOMEM;
6905 }
6906
6907 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6908 struct kvm_memory_slot *memslot,
6909 struct kvm_memory_slot old,
6910 struct kvm_userspace_memory_region *mem,
6911 bool user_alloc)
6912 {
6913 int npages = memslot->npages;
6914
6915 /*
6916 * Only private memory slots need to be mapped here since
6917 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
6918 */
6919 if ((memslot->id >= KVM_USER_MEM_SLOTS) && npages && !old.npages) {
6920 unsigned long userspace_addr;
6921
6922 /*
6923 * MAP_SHARED to prevent internal slot pages from being moved
6924 * by fork()/COW.
6925 */
6926 userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE,
6927 PROT_READ | PROT_WRITE,
6928 MAP_SHARED | MAP_ANONYMOUS, 0);
6929
6930 if (IS_ERR((void *)userspace_addr))
6931 return PTR_ERR((void *)userspace_addr);
6932
6933 memslot->userspace_addr = userspace_addr;
6934 }
6935
6936 return 0;
6937 }
6938
6939 void kvm_arch_commit_memory_region(struct kvm *kvm,
6940 struct kvm_userspace_memory_region *mem,
6941 struct kvm_memory_slot old,
6942 bool user_alloc)
6943 {
6944
6945 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6946
6947 if ((mem->slot >= KVM_USER_MEM_SLOTS) && old.npages && !npages) {
6948 int ret;
6949
6950 ret = vm_munmap(old.userspace_addr,
6951 old.npages * PAGE_SIZE);
6952 if (ret < 0)
6953 printk(KERN_WARNING
6954 "kvm_vm_ioctl_set_memory_region: "
6955 "failed to munmap memory\n");
6956 }
6957
6958 if (!kvm->arch.n_requested_mmu_pages)
6959 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6960
6961 if (nr_mmu_pages)
6962 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6963 /*
6964 * Write protect all pages for dirty logging.
6965 * Existing largepage mappings are destroyed here and new ones will
6966 * not be created until the end of the logging.
6967 */
6968 if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
6969 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6970 /*
6971 * If memory slot is created, or moved, we need to clear all
6972 * mmio sptes.
6973 */
6974 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6975 kvm_mmu_zap_all(kvm);
6976 kvm_reload_remote_mmus(kvm);
6977 }
6978 }
6979
6980 void kvm_arch_flush_shadow_all(struct kvm *kvm)
6981 {
6982 kvm_mmu_zap_all(kvm);
6983 kvm_reload_remote_mmus(kvm);
6984 }
6985
6986 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6987 struct kvm_memory_slot *slot)
6988 {
6989 kvm_arch_flush_shadow_all(kvm);
6990 }
6991
6992 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6993 {
6994 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6995 !vcpu->arch.apf.halted)
6996 || !list_empty_careful(&vcpu->async_pf.done)
6997 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6998 || atomic_read(&vcpu->arch.nmi_queued) ||
6999 (kvm_arch_interrupt_allowed(vcpu) &&
7000 kvm_cpu_has_interrupt(vcpu));
7001 }
7002
7003 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7004 {
7005 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7006 }
7007
7008 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7009 {
7010 return kvm_x86_ops->interrupt_allowed(vcpu);
7011 }
7012
7013 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7014 {
7015 unsigned long current_rip = kvm_rip_read(vcpu) +
7016 get_segment_base(vcpu, VCPU_SREG_CS);
7017
7018 return current_rip == linear_rip;
7019 }
7020 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7021
7022 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7023 {
7024 unsigned long rflags;
7025
7026 rflags = kvm_x86_ops->get_rflags(vcpu);
7027 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7028 rflags &= ~X86_EFLAGS_TF;
7029 return rflags;
7030 }
7031 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7032
7033 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7034 {
7035 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7036 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7037 rflags |= X86_EFLAGS_TF;
7038 kvm_x86_ops->set_rflags(vcpu, rflags);
7039 kvm_make_request(KVM_REQ_EVENT, vcpu);
7040 }
7041 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7042
7043 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7044 {
7045 int r;
7046
7047 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7048 is_error_page(work->page))
7049 return;
7050
7051 r = kvm_mmu_reload(vcpu);
7052 if (unlikely(r))
7053 return;
7054
7055 if (!vcpu->arch.mmu.direct_map &&
7056 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7057 return;
7058
7059 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7060 }
7061
7062 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7063 {
7064 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7065 }
7066
7067 static inline u32 kvm_async_pf_next_probe(u32 key)
7068 {
7069 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7070 }
7071
7072 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7073 {
7074 u32 key = kvm_async_pf_hash_fn(gfn);
7075
7076 while (vcpu->arch.apf.gfns[key] != ~0)
7077 key = kvm_async_pf_next_probe(key);
7078
7079 vcpu->arch.apf.gfns[key] = gfn;
7080 }
7081
7082 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7083 {
7084 int i;
7085 u32 key = kvm_async_pf_hash_fn(gfn);
7086
7087 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7088 (vcpu->arch.apf.gfns[key] != gfn &&
7089 vcpu->arch.apf.gfns[key] != ~0); i++)
7090 key = kvm_async_pf_next_probe(key);
7091
7092 return key;
7093 }
7094
7095 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7096 {
7097 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7098 }
7099
7100 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7101 {
7102 u32 i, j, k;
7103
7104 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7105 while (true) {
7106 vcpu->arch.apf.gfns[i] = ~0;
7107 do {
7108 j = kvm_async_pf_next_probe(j);
7109 if (vcpu->arch.apf.gfns[j] == ~0)
7110 return;
7111 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7112 /*
7113 * k lies cyclically in ]i,j]
7114 * | i.k.j |
7115 * |....j i.k.| or |.k..j i...|
7116 */
7117 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7118 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7119 i = j;
7120 }
7121 }
7122
7123 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7124 {
7125
7126 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7127 sizeof(val));
7128 }
7129
7130 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7131 struct kvm_async_pf *work)
7132 {
7133 struct x86_exception fault;
7134
7135 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7136 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7137
7138 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7139 (vcpu->arch.apf.send_user_only &&
7140 kvm_x86_ops->get_cpl(vcpu) == 0))
7141 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7142 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7143 fault.vector = PF_VECTOR;
7144 fault.error_code_valid = true;
7145 fault.error_code = 0;
7146 fault.nested_page_fault = false;
7147 fault.address = work->arch.token;
7148 kvm_inject_page_fault(vcpu, &fault);
7149 }
7150 }
7151
7152 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7153 struct kvm_async_pf *work)
7154 {
7155 struct x86_exception fault;
7156
7157 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7158 if (is_error_page(work->page))
7159 work->arch.token = ~0; /* broadcast wakeup */
7160 else
7161 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7162
7163 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7164 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7165 fault.vector = PF_VECTOR;
7166 fault.error_code_valid = true;
7167 fault.error_code = 0;
7168 fault.nested_page_fault = false;
7169 fault.address = work->arch.token;
7170 kvm_inject_page_fault(vcpu, &fault);
7171 }
7172 vcpu->arch.apf.halted = false;
7173 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7174 }
7175
7176 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7177 {
7178 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7179 return true;
7180 else
7181 return !kvm_event_needs_reinjection(vcpu) &&
7182 kvm_x86_ops->interrupt_allowed(vcpu);
7183 }
7184
7185 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7186 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7187 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7188 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7189 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7190 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7191 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7192 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7193 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7194 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7195 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7196 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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