projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <trace/events/kvm.h>
55
56 #define CREATE_TRACE_POINTS
57 #include "trace.h"
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 static bool __read_mostly kvmclock_periodic_sync = true;
103 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
105 bool kvm_has_tsc_control;
106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107 u32 kvm_max_guest_tsc_khz;
108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111 static u32 tsc_tolerance_ppm = 250;
112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
115 unsigned int lapic_timer_advance_ns = 0;
116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
118 static bool backwards_tsc_observed = false;
119
120 #define KVM_NR_SHARED_MSRS 16
121
122 struct kvm_shared_msrs_global {
123 int nr;
124 u32 msrs[KVM_NR_SHARED_MSRS];
125 };
126
127 struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
134 };
135
136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
137 static struct kvm_shared_msrs __percpu *shared_msrs;
138
139 struct kvm_stats_debugfs_item debugfs_entries[] = {
140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
150 { "halt_exits", VCPU_STAT(halt_exits) },
151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
153 { "hypercalls", VCPU_STAT(hypercalls) },
154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
161 { "irq_injections", VCPU_STAT(irq_injections) },
162 { "nmi_injections", VCPU_STAT(nmi_injections) },
163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
170 { "mmu_unsync", VM_STAT(mmu_unsync) },
171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
172 { "largepages", VM_STAT(lpages) },
173 { NULL }
174 };
175
176 u64 __read_mostly host_xcr0;
177
178 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
179
180 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181 {
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185 }
186
187 static void kvm_on_user_return(struct user_return_notifier *urn)
188 {
189 unsigned slot;
190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
192 struct kvm_shared_msr_values *values;
193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203 }
204
205 static void shared_msr_update(unsigned slot, u32 msr)
206 {
207 u64 value;
208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
210
211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220 }
221
222 void kvm_define_shared_msr(unsigned slot, u32 msr)
223 {
224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
225 shared_msrs_global.msrs[slot] = msr;
226 if (slot >= shared_msrs_global.nr)
227 shared_msrs_global.nr = slot + 1;
228 }
229 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
230
231 static void kvm_shared_msr_cpu_online(void)
232 {
233 unsigned i;
234
235 for (i = 0; i < shared_msrs_global.nr; ++i)
236 shared_msr_update(i, shared_msrs_global.msrs[i]);
237 }
238
239 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
240 {
241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
243 int err;
244
245 if (((value ^ smsr->values[slot].curr) & mask) == 0)
246 return 0;
247 smsr->values[slot].curr = value;
248 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
249 if (err)
250 return 1;
251
252 if (!smsr->registered) {
253 smsr->urn.on_user_return = kvm_on_user_return;
254 user_return_notifier_register(&smsr->urn);
255 smsr->registered = true;
256 }
257 return 0;
258 }
259 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
260
261 static void drop_user_return_notifiers(void)
262 {
263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
265
266 if (smsr->registered)
267 kvm_on_user_return(&smsr->urn);
268 }
269
270 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
271 {
272 return vcpu->arch.apic_base;
273 }
274 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
275
276 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
277 {
278 u64 old_state = vcpu->arch.apic_base &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 new_state = msr_info->data &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
283 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
284
285 if (!msr_info->host_initiated &&
286 ((msr_info->data & reserved_bits) != 0 ||
287 new_state == X2APIC_ENABLE ||
288 (new_state == MSR_IA32_APICBASE_ENABLE &&
289 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
290 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
291 old_state == 0)))
292 return 1;
293
294 kvm_lapic_set_base(vcpu, msr_info->data);
295 return 0;
296 }
297 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
298
299 asmlinkage __visible void kvm_spurious_fault(void)
300 {
301 /* Fault while not rebooting. We want the trace. */
302 BUG();
303 }
304 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
305
306 #define EXCPT_BENIGN 0
307 #define EXCPT_CONTRIBUTORY 1
308 #define EXCPT_PF 2
309
310 static int exception_class(int vector)
311 {
312 switch (vector) {
313 case PF_VECTOR:
314 return EXCPT_PF;
315 case DE_VECTOR:
316 case TS_VECTOR:
317 case NP_VECTOR:
318 case SS_VECTOR:
319 case GP_VECTOR:
320 return EXCPT_CONTRIBUTORY;
321 default:
322 break;
323 }
324 return EXCPT_BENIGN;
325 }
326
327 #define EXCPT_FAULT 0
328 #define EXCPT_TRAP 1
329 #define EXCPT_ABORT 2
330 #define EXCPT_INTERRUPT 3
331
332 static int exception_type(int vector)
333 {
334 unsigned int mask;
335
336 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
337 return EXCPT_INTERRUPT;
338
339 mask = 1 << vector;
340
341 /* #DB is trap, as instruction watchpoints are handled elsewhere */
342 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
343 return EXCPT_TRAP;
344
345 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
346 return EXCPT_ABORT;
347
348 /* Reserved exceptions will result in fault */
349 return EXCPT_FAULT;
350 }
351
352 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
353 unsigned nr, bool has_error, u32 error_code,
354 bool reinject)
355 {
356 u32 prev_nr;
357 int class1, class2;
358
359 kvm_make_request(KVM_REQ_EVENT, vcpu);
360
361 if (!vcpu->arch.exception.pending) {
362 queue:
363 if (has_error && !is_protmode(vcpu))
364 has_error = false;
365 vcpu->arch.exception.pending = true;
366 vcpu->arch.exception.has_error_code = has_error;
367 vcpu->arch.exception.nr = nr;
368 vcpu->arch.exception.error_code = error_code;
369 vcpu->arch.exception.reinject = reinject;
370 return;
371 }
372
373 /* to check exception */
374 prev_nr = vcpu->arch.exception.nr;
375 if (prev_nr == DF_VECTOR) {
376 /* triple fault -> shutdown */
377 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
378 return;
379 }
380 class1 = exception_class(prev_nr);
381 class2 = exception_class(nr);
382 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
383 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
384 /* generate double fault per SDM Table 5-5 */
385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = true;
387 vcpu->arch.exception.nr = DF_VECTOR;
388 vcpu->arch.exception.error_code = 0;
389 } else
390 /* replace previous exception with a new one in a hope
391 that instruction re-execution will regenerate lost
392 exception */
393 goto queue;
394 }
395
396 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
397 {
398 kvm_multiple_exception(vcpu, nr, false, 0, false);
399 }
400 EXPORT_SYMBOL_GPL(kvm_queue_exception);
401
402 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
403 {
404 kvm_multiple_exception(vcpu, nr, false, 0, true);
405 }
406 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
407
408 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
409 {
410 if (err)
411 kvm_inject_gp(vcpu, 0);
412 else
413 kvm_x86_ops->skip_emulated_instruction(vcpu);
414 }
415 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
416
417 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
418 {
419 ++vcpu->stat.pf_guest;
420 vcpu->arch.cr2 = fault->address;
421 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
422 }
423 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
424
425 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
426 {
427 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
428 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
429 else
430 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
431
432 return fault->nested_page_fault;
433 }
434
435 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
436 {
437 atomic_inc(&vcpu->arch.nmi_queued);
438 kvm_make_request(KVM_REQ_NMI, vcpu);
439 }
440 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
441
442 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
443 {
444 kvm_multiple_exception(vcpu, nr, true, error_code, false);
445 }
446 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
447
448 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
449 {
450 kvm_multiple_exception(vcpu, nr, true, error_code, true);
451 }
452 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
453
454 /*
455 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
456 * a #GP and return false.
457 */
458 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
459 {
460 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
461 return true;
462 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
463 return false;
464 }
465 EXPORT_SYMBOL_GPL(kvm_require_cpl);
466
467 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
468 {
469 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
470 return true;
471
472 kvm_queue_exception(vcpu, UD_VECTOR);
473 return false;
474 }
475 EXPORT_SYMBOL_GPL(kvm_require_dr);
476
477 /*
478 * This function will be used to read from the physical memory of the currently
479 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
480 * can read from guest physical or from the guest's guest physical memory.
481 */
482 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
483 gfn_t ngfn, void *data, int offset, int len,
484 u32 access)
485 {
486 struct x86_exception exception;
487 gfn_t real_gfn;
488 gpa_t ngpa;
489
490 ngpa = gfn_to_gpa(ngfn);
491 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
492 if (real_gfn == UNMAPPED_GVA)
493 return -EFAULT;
494
495 real_gfn = gpa_to_gfn(real_gfn);
496
497 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
498 }
499 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
500
501 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
502 void *data, int offset, int len, u32 access)
503 {
504 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
505 data, offset, len, access);
506 }
507
508 /*
509 * Load the pae pdptrs. Return true is they are all valid.
510 */
511 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
512 {
513 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
514 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
515 int i;
516 int ret;
517 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
518
519 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
520 offset * sizeof(u64), sizeof(pdpte),
521 PFERR_USER_MASK|PFERR_WRITE_MASK);
522 if (ret < 0) {
523 ret = 0;
524 goto out;
525 }
526 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
527 if (is_present_gpte(pdpte[i]) &&
528 (pdpte[i] &
529 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
530 ret = 0;
531 goto out;
532 }
533 }
534 ret = 1;
535
536 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_avail);
539 __set_bit(VCPU_EXREG_PDPTR,
540 (unsigned long *)&vcpu->arch.regs_dirty);
541 out:
542
543 return ret;
544 }
545 EXPORT_SYMBOL_GPL(load_pdptrs);
546
547 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
548 {
549 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
550 bool changed = true;
551 int offset;
552 gfn_t gfn;
553 int r;
554
555 if (is_long_mode(vcpu) || !is_pae(vcpu))
556 return false;
557
558 if (!test_bit(VCPU_EXREG_PDPTR,
559 (unsigned long *)&vcpu->arch.regs_avail))
560 return true;
561
562 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
563 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
564 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
565 PFERR_USER_MASK | PFERR_WRITE_MASK);
566 if (r < 0)
567 goto out;
568 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
569 out:
570
571 return changed;
572 }
573
574 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
575 {
576 unsigned long old_cr0 = kvm_read_cr0(vcpu);
577 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
578
579 cr0 |= X86_CR0_ET;
580
581 #ifdef CONFIG_X86_64
582 if (cr0 & 0xffffffff00000000UL)
583 return 1;
584 #endif
585
586 cr0 &= ~CR0_RESERVED_BITS;
587
588 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 return 1;
590
591 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 return 1;
593
594 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
595 #ifdef CONFIG_X86_64
596 if ((vcpu->arch.efer & EFER_LME)) {
597 int cs_db, cs_l;
598
599 if (!is_pae(vcpu))
600 return 1;
601 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
602 if (cs_l)
603 return 1;
604 } else
605 #endif
606 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
608 return 1;
609 }
610
611 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 return 1;
613
614 kvm_x86_ops->set_cr0(vcpu, cr0);
615
616 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
617 kvm_clear_async_pf_completion_queue(vcpu);
618 kvm_async_pf_hash_reset(vcpu);
619 }
620
621 if ((cr0 ^ old_cr0) & update_bits)
622 kvm_mmu_reset_context(vcpu);
623
624 if ((cr0 ^ old_cr0) & X86_CR0_CD)
625 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(kvm_set_cr0);
630
631 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
632 {
633 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
634 }
635 EXPORT_SYMBOL_GPL(kvm_lmsw);
636
637 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
638 {
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
640 !vcpu->guest_xcr0_loaded) {
641 /* kvm_set_xcr() also depends on this */
642 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
643 vcpu->guest_xcr0_loaded = 1;
644 }
645 }
646
647 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
648 {
649 if (vcpu->guest_xcr0_loaded) {
650 if (vcpu->arch.xcr0 != host_xcr0)
651 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
652 vcpu->guest_xcr0_loaded = 0;
653 }
654 }
655
656 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
657 {
658 u64 xcr0 = xcr;
659 u64 old_xcr0 = vcpu->arch.xcr0;
660 u64 valid_bits;
661
662 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
663 if (index != XCR_XFEATURE_ENABLED_MASK)
664 return 1;
665 if (!(xcr0 & XSTATE_FP))
666 return 1;
667 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
668 return 1;
669
670 /*
671 * Do not allow the guest to set bits that we do not support
672 * saving. However, xcr0 bit 0 is always set, even if the
673 * emulated CPU does not support XSAVE (see fx_init).
674 */
675 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
676 if (xcr0 & ~valid_bits)
677 return 1;
678
679 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
680 return 1;
681
682 if (xcr0 & XSTATE_AVX512) {
683 if (!(xcr0 & XSTATE_YMM))
684 return 1;
685 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
686 return 1;
687 }
688 kvm_put_guest_xcr0(vcpu);
689 vcpu->arch.xcr0 = xcr0;
690
691 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
692 kvm_update_cpuid(vcpu);
693 return 0;
694 }
695
696 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697 {
698 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
699 __kvm_set_xcr(vcpu, index, xcr)) {
700 kvm_inject_gp(vcpu, 0);
701 return 1;
702 }
703 return 0;
704 }
705 EXPORT_SYMBOL_GPL(kvm_set_xcr);
706
707 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
708 {
709 unsigned long old_cr4 = kvm_read_cr4(vcpu);
710 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
711 X86_CR4_SMEP | X86_CR4_SMAP;
712
713 if (cr4 & CR4_RESERVED_BITS)
714 return 1;
715
716 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
717 return 1;
718
719 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
720 return 1;
721
722 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
723 return 1;
724
725 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
726 return 1;
727
728 if (is_long_mode(vcpu)) {
729 if (!(cr4 & X86_CR4_PAE))
730 return 1;
731 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
732 && ((cr4 ^ old_cr4) & pdptr_bits)
733 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
734 kvm_read_cr3(vcpu)))
735 return 1;
736
737 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
738 if (!guest_cpuid_has_pcid(vcpu))
739 return 1;
740
741 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
742 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
743 return 1;
744 }
745
746 if (kvm_x86_ops->set_cr4(vcpu, cr4))
747 return 1;
748
749 if (((cr4 ^ old_cr4) & pdptr_bits) ||
750 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
751 kvm_mmu_reset_context(vcpu);
752
753 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
754 kvm_update_cpuid(vcpu);
755
756 return 0;
757 }
758 EXPORT_SYMBOL_GPL(kvm_set_cr4);
759
760 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
761 {
762 #ifdef CONFIG_X86_64
763 cr3 &= ~CR3_PCID_INVD;
764 #endif
765
766 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
767 kvm_mmu_sync_roots(vcpu);
768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
769 return 0;
770 }
771
772 if (is_long_mode(vcpu)) {
773 if (cr3 & CR3_L_MODE_RESERVED_BITS)
774 return 1;
775 } else if (is_pae(vcpu) && is_paging(vcpu) &&
776 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
777 return 1;
778
779 vcpu->arch.cr3 = cr3;
780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
781 kvm_mmu_new_cr3(vcpu);
782 return 0;
783 }
784 EXPORT_SYMBOL_GPL(kvm_set_cr3);
785
786 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
787 {
788 if (cr8 & CR8_RESERVED_BITS)
789 return 1;
790 if (irqchip_in_kernel(vcpu->kvm))
791 kvm_lapic_set_tpr(vcpu, cr8);
792 else
793 vcpu->arch.cr8 = cr8;
794 return 0;
795 }
796 EXPORT_SYMBOL_GPL(kvm_set_cr8);
797
798 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
799 {
800 if (irqchip_in_kernel(vcpu->kvm))
801 return kvm_lapic_get_cr8(vcpu);
802 else
803 return vcpu->arch.cr8;
804 }
805 EXPORT_SYMBOL_GPL(kvm_get_cr8);
806
807 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
808 {
809 int i;
810
811 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
812 for (i = 0; i < KVM_NR_DB_REGS; i++)
813 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
814 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
815 }
816 }
817
818 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
819 {
820 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
821 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
822 }
823
824 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
825 {
826 unsigned long dr7;
827
828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
829 dr7 = vcpu->arch.guest_debug_dr7;
830 else
831 dr7 = vcpu->arch.dr7;
832 kvm_x86_ops->set_dr7(vcpu, dr7);
833 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
834 if (dr7 & DR7_BP_EN_MASK)
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
836 }
837
838 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
839 {
840 u64 fixed = DR6_FIXED_1;
841
842 if (!guest_cpuid_has_rtm(vcpu))
843 fixed |= DR6_RTM;
844 return fixed;
845 }
846
847 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
848 {
849 switch (dr) {
850 case 0 ... 3:
851 vcpu->arch.db[dr] = val;
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
853 vcpu->arch.eff_db[dr] = val;
854 break;
855 case 4:
856 /* fall through */
857 case 6:
858 if (val & 0xffffffff00000000ULL)
859 return -1; /* #GP */
860 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
861 kvm_update_dr6(vcpu);
862 break;
863 case 5:
864 /* fall through */
865 default: /* 7 */
866 if (val & 0xffffffff00000000ULL)
867 return -1; /* #GP */
868 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
869 kvm_update_dr7(vcpu);
870 break;
871 }
872
873 return 0;
874 }
875
876 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
877 {
878 if (__kvm_set_dr(vcpu, dr, val)) {
879 kvm_inject_gp(vcpu, 0);
880 return 1;
881 }
882 return 0;
883 }
884 EXPORT_SYMBOL_GPL(kvm_set_dr);
885
886 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
887 {
888 switch (dr) {
889 case 0 ... 3:
890 *val = vcpu->arch.db[dr];
891 break;
892 case 4:
893 /* fall through */
894 case 6:
895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 *val = vcpu->arch.dr6;
897 else
898 *val = kvm_x86_ops->get_dr6(vcpu);
899 break;
900 case 5:
901 /* fall through */
902 default: /* 7 */
903 *val = vcpu->arch.dr7;
904 break;
905 }
906 return 0;
907 }
908 EXPORT_SYMBOL_GPL(kvm_get_dr);
909
910 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
911 {
912 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
913 u64 data;
914 int err;
915
916 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
917 if (err)
918 return err;
919 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
920 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
921 return err;
922 }
923 EXPORT_SYMBOL_GPL(kvm_rdpmc);
924
925 /*
926 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
927 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
928 *
929 * This list is modified at module load time to reflect the
930 * capabilities of the host cpu. This capabilities test skips MSRs that are
931 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
932 * may depend on host virtualization features rather than host cpu features.
933 */
934
935 static u32 msrs_to_save[] = {
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
937 MSR_STAR,
938 #ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940 #endif
941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
943 };
944
945 static unsigned num_msrs_to_save;
946
947 static u32 emulated_msrs[] = {
948 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
949 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
950 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
951 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
952 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
953 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
954 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
955 MSR_KVM_PV_EOI_EN,
956
957 MSR_IA32_TSC_ADJUST,
958 MSR_IA32_TSCDEADLINE,
959 MSR_IA32_MISC_ENABLE,
960 MSR_IA32_MCG_STATUS,
961 MSR_IA32_MCG_CTL,
962 MSR_IA32_SMBASE,
963 };
964
965 static unsigned num_emulated_msrs;
966
967 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
968 {
969 if (efer & efer_reserved_bits)
970 return false;
971
972 if (efer & EFER_FFXSR) {
973 struct kvm_cpuid_entry2 *feat;
974
975 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
976 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
977 return false;
978 }
979
980 if (efer & EFER_SVME) {
981 struct kvm_cpuid_entry2 *feat;
982
983 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
984 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
985 return false;
986 }
987
988 return true;
989 }
990 EXPORT_SYMBOL_GPL(kvm_valid_efer);
991
992 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
993 {
994 u64 old_efer = vcpu->arch.efer;
995
996 if (!kvm_valid_efer(vcpu, efer))
997 return 1;
998
999 if (is_paging(vcpu)
1000 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1001 return 1;
1002
1003 efer &= ~EFER_LMA;
1004 efer |= vcpu->arch.efer & EFER_LMA;
1005
1006 kvm_x86_ops->set_efer(vcpu, efer);
1007
1008 /* Update reserved bits */
1009 if ((efer ^ old_efer) & EFER_NX)
1010 kvm_mmu_reset_context(vcpu);
1011
1012 return 0;
1013 }
1014
1015 void kvm_enable_efer_bits(u64 mask)
1016 {
1017 efer_reserved_bits &= ~mask;
1018 }
1019 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1020
1021 /*
1022 * Writes msr value into into the appropriate "register".
1023 * Returns 0 on success, non-0 otherwise.
1024 * Assumes vcpu_load() was already called.
1025 */
1026 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1027 {
1028 switch (msr->index) {
1029 case MSR_FS_BASE:
1030 case MSR_GS_BASE:
1031 case MSR_KERNEL_GS_BASE:
1032 case MSR_CSTAR:
1033 case MSR_LSTAR:
1034 if (is_noncanonical_address(msr->data))
1035 return 1;
1036 break;
1037 case MSR_IA32_SYSENTER_EIP:
1038 case MSR_IA32_SYSENTER_ESP:
1039 /*
1040 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1041 * non-canonical address is written on Intel but not on
1042 * AMD (which ignores the top 32-bits, because it does
1043 * not implement 64-bit SYSENTER).
1044 *
1045 * 64-bit code should hence be able to write a non-canonical
1046 * value on AMD. Making the address canonical ensures that
1047 * vmentry does not fail on Intel after writing a non-canonical
1048 * value, and that something deterministic happens if the guest
1049 * invokes 64-bit SYSENTER.
1050 */
1051 msr->data = get_canonical(msr->data);
1052 }
1053 return kvm_x86_ops->set_msr(vcpu, msr);
1054 }
1055 EXPORT_SYMBOL_GPL(kvm_set_msr);
1056
1057 /*
1058 * Adapt set_msr() to msr_io()'s calling convention
1059 */
1060 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1061 {
1062 struct msr_data msr;
1063 int r;
1064
1065 msr.index = index;
1066 msr.host_initiated = true;
1067 r = kvm_get_msr(vcpu, &msr);
1068 if (r)
1069 return r;
1070
1071 *data = msr.data;
1072 return 0;
1073 }
1074
1075 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1076 {
1077 struct msr_data msr;
1078
1079 msr.data = *data;
1080 msr.index = index;
1081 msr.host_initiated = true;
1082 return kvm_set_msr(vcpu, &msr);
1083 }
1084
1085 #ifdef CONFIG_X86_64
1086 struct pvclock_gtod_data {
1087 seqcount_t seq;
1088
1089 struct { /* extract of a clocksource struct */
1090 int vclock_mode;
1091 cycle_t cycle_last;
1092 cycle_t mask;
1093 u32 mult;
1094 u32 shift;
1095 } clock;
1096
1097 u64 boot_ns;
1098 u64 nsec_base;
1099 };
1100
1101 static struct pvclock_gtod_data pvclock_gtod_data;
1102
1103 static void update_pvclock_gtod(struct timekeeper *tk)
1104 {
1105 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1106 u64 boot_ns;
1107
1108 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1109
1110 write_seqcount_begin(&vdata->seq);
1111
1112 /* copy pvclock gtod data */
1113 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1114 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1115 vdata->clock.mask = tk->tkr_mono.mask;
1116 vdata->clock.mult = tk->tkr_mono.mult;
1117 vdata->clock.shift = tk->tkr_mono.shift;
1118
1119 vdata->boot_ns = boot_ns;
1120 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1121
1122 write_seqcount_end(&vdata->seq);
1123 }
1124 #endif
1125
1126 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1127 {
1128 /*
1129 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1130 * vcpu_enter_guest. This function is only called from
1131 * the physical CPU that is running vcpu.
1132 */
1133 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1134 }
1135
1136 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1137 {
1138 int version;
1139 int r;
1140 struct pvclock_wall_clock wc;
1141 struct timespec boot;
1142
1143 if (!wall_clock)
1144 return;
1145
1146 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1147 if (r)
1148 return;
1149
1150 if (version & 1)
1151 ++version; /* first time write, random junk */
1152
1153 ++version;
1154
1155 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1156
1157 /*
1158 * The guest calculates current wall clock time by adding
1159 * system time (updated by kvm_guest_time_update below) to the
1160 * wall clock specified here. guest system time equals host
1161 * system time for us, thus we must fill in host boot time here.
1162 */
1163 getboottime(&boot);
1164
1165 if (kvm->arch.kvmclock_offset) {
1166 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1167 boot = timespec_sub(boot, ts);
1168 }
1169 wc.sec = boot.tv_sec;
1170 wc.nsec = boot.tv_nsec;
1171 wc.version = version;
1172
1173 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1174
1175 version++;
1176 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1177 }
1178
1179 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1180 {
1181 uint32_t quotient, remainder;
1182
1183 /* Don't try to replace with do_div(), this one calculates
1184 * "(dividend << 32) / divisor" */
1185 __asm__ ( "divl %4"
1186 : "=a" (quotient), "=d" (remainder)
1187 : "0" (0), "1" (dividend), "r" (divisor) );
1188 return quotient;
1189 }
1190
1191 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1192 s8 *pshift, u32 *pmultiplier)
1193 {
1194 uint64_t scaled64;
1195 int32_t shift = 0;
1196 uint64_t tps64;
1197 uint32_t tps32;
1198
1199 tps64 = base_khz * 1000LL;
1200 scaled64 = scaled_khz * 1000LL;
1201 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1202 tps64 >>= 1;
1203 shift--;
1204 }
1205
1206 tps32 = (uint32_t)tps64;
1207 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1208 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1209 scaled64 >>= 1;
1210 else
1211 tps32 <<= 1;
1212 shift++;
1213 }
1214
1215 *pshift = shift;
1216 *pmultiplier = div_frac(scaled64, tps32);
1217
1218 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1219 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1220 }
1221
1222 #ifdef CONFIG_X86_64
1223 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1224 #endif
1225
1226 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1227 static unsigned long max_tsc_khz;
1228
1229 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1230 {
1231 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1232 vcpu->arch.virtual_tsc_shift);
1233 }
1234
1235 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1236 {
1237 u64 v = (u64)khz * (1000000 + ppm);
1238 do_div(v, 1000000);
1239 return v;
1240 }
1241
1242 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1243 {
1244 u32 thresh_lo, thresh_hi;
1245 int use_scaling = 0;
1246
1247 /* tsc_khz can be zero if TSC calibration fails */
1248 if (this_tsc_khz == 0)
1249 return;
1250
1251 /* Compute a scale to convert nanoseconds in TSC cycles */
1252 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1253 &vcpu->arch.virtual_tsc_shift,
1254 &vcpu->arch.virtual_tsc_mult);
1255 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1256
1257 /*
1258 * Compute the variation in TSC rate which is acceptable
1259 * within the range of tolerance and decide if the
1260 * rate being applied is within that bounds of the hardware
1261 * rate. If so, no scaling or compensation need be done.
1262 */
1263 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1264 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1265 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1266 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1267 use_scaling = 1;
1268 }
1269 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1270 }
1271
1272 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1273 {
1274 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1275 vcpu->arch.virtual_tsc_mult,
1276 vcpu->arch.virtual_tsc_shift);
1277 tsc += vcpu->arch.this_tsc_write;
1278 return tsc;
1279 }
1280
1281 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1282 {
1283 #ifdef CONFIG_X86_64
1284 bool vcpus_matched;
1285 struct kvm_arch *ka = &vcpu->kvm->arch;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1289 atomic_read(&vcpu->kvm->online_vcpus));
1290
1291 /*
1292 * Once the masterclock is enabled, always perform request in
1293 * order to update it.
1294 *
1295 * In order to enable masterclock, the host clocksource must be TSC
1296 * and the vcpus need to have matched TSCs. When that happens,
1297 * perform request to enable masterclock.
1298 */
1299 if (ka->use_master_clock ||
1300 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1301 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1302
1303 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1304 atomic_read(&vcpu->kvm->online_vcpus),
1305 ka->use_master_clock, gtod->clock.vclock_mode);
1306 #endif
1307 }
1308
1309 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1310 {
1311 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1312 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1313 }
1314
1315 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1316 {
1317 struct kvm *kvm = vcpu->kvm;
1318 u64 offset, ns, elapsed;
1319 unsigned long flags;
1320 s64 usdiff;
1321 bool matched;
1322 bool already_matched;
1323 u64 data = msr->data;
1324
1325 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1326 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1327 ns = get_kernel_ns();
1328 elapsed = ns - kvm->arch.last_tsc_nsec;
1329
1330 if (vcpu->arch.virtual_tsc_khz) {
1331 int faulted = 0;
1332
1333 /* n.b - signed multiplication and division required */
1334 usdiff = data - kvm->arch.last_tsc_write;
1335 #ifdef CONFIG_X86_64
1336 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1337 #else
1338 /* do_div() only does unsigned */
1339 asm("1: idivl %[divisor]\n"
1340 "2: xor %%edx, %%edx\n"
1341 " movl $0, %[faulted]\n"
1342 "3:\n"
1343 ".section .fixup,\"ax\"\n"
1344 "4: movl $1, %[faulted]\n"
1345 " jmp 3b\n"
1346 ".previous\n"
1347
1348 _ASM_EXTABLE(1b, 4b)
1349
1350 : "=A"(usdiff), [faulted] "=r" (faulted)
1351 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1352
1353 #endif
1354 do_div(elapsed, 1000);
1355 usdiff -= elapsed;
1356 if (usdiff < 0)
1357 usdiff = -usdiff;
1358
1359 /* idivl overflow => difference is larger than USEC_PER_SEC */
1360 if (faulted)
1361 usdiff = USEC_PER_SEC;
1362 } else
1363 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1364
1365 /*
1366 * Special case: TSC write with a small delta (1 second) of virtual
1367 * cycle time against real time is interpreted as an attempt to
1368 * synchronize the CPU.
1369 *
1370 * For a reliable TSC, we can match TSC offsets, and for an unstable
1371 * TSC, we add elapsed time in this computation. We could let the
1372 * compensation code attempt to catch up if we fall behind, but
1373 * it's better to try to match offsets from the beginning.
1374 */
1375 if (usdiff < USEC_PER_SEC &&
1376 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1377 if (!check_tsc_unstable()) {
1378 offset = kvm->arch.cur_tsc_offset;
1379 pr_debug("kvm: matched tsc offset for %llu\n", data);
1380 } else {
1381 u64 delta = nsec_to_cycles(vcpu, elapsed);
1382 data += delta;
1383 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1384 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1385 }
1386 matched = true;
1387 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1388 } else {
1389 /*
1390 * We split periods of matched TSC writes into generations.
1391 * For each generation, we track the original measured
1392 * nanosecond time, offset, and write, so if TSCs are in
1393 * sync, we can match exact offset, and if not, we can match
1394 * exact software computation in compute_guest_tsc()
1395 *
1396 * These values are tracked in kvm->arch.cur_xxx variables.
1397 */
1398 kvm->arch.cur_tsc_generation++;
1399 kvm->arch.cur_tsc_nsec = ns;
1400 kvm->arch.cur_tsc_write = data;
1401 kvm->arch.cur_tsc_offset = offset;
1402 matched = false;
1403 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1404 kvm->arch.cur_tsc_generation, data);
1405 }
1406
1407 /*
1408 * We also track th most recent recorded KHZ, write and time to
1409 * allow the matching interval to be extended at each write.
1410 */
1411 kvm->arch.last_tsc_nsec = ns;
1412 kvm->arch.last_tsc_write = data;
1413 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1414
1415 vcpu->arch.last_guest_tsc = data;
1416
1417 /* Keep track of which generation this VCPU has synchronized to */
1418 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1419 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1420 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1421
1422 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1423 update_ia32_tsc_adjust_msr(vcpu, offset);
1424 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1425 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1426
1427 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1428 if (!matched) {
1429 kvm->arch.nr_vcpus_matched_tsc = 0;
1430 } else if (!already_matched) {
1431 kvm->arch.nr_vcpus_matched_tsc++;
1432 }
1433
1434 kvm_track_tsc_matching(vcpu);
1435 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1436 }
1437
1438 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1439
1440 #ifdef CONFIG_X86_64
1441
1442 static cycle_t read_tsc(void)
1443 {
1444 cycle_t ret = (cycle_t)rdtsc_ordered();
1445 u64 last = pvclock_gtod_data.clock.cycle_last;
1446
1447 if (likely(ret >= last))
1448 return ret;
1449
1450 /*
1451 * GCC likes to generate cmov here, but this branch is extremely
1452 * predictable (it's just a funciton of time and the likely is
1453 * very likely) and there's a data dependence, so force GCC
1454 * to generate a branch instead. I don't barrier() because
1455 * we don't actually need a barrier, and if this function
1456 * ever gets inlined it will generate worse code.
1457 */
1458 asm volatile ("");
1459 return last;
1460 }
1461
1462 static inline u64 vgettsc(cycle_t *cycle_now)
1463 {
1464 long v;
1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1466
1467 *cycle_now = read_tsc();
1468
1469 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1470 return v * gtod->clock.mult;
1471 }
1472
1473 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1474 {
1475 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1476 unsigned long seq;
1477 int mode;
1478 u64 ns;
1479
1480 do {
1481 seq = read_seqcount_begin(&gtod->seq);
1482 mode = gtod->clock.vclock_mode;
1483 ns = gtod->nsec_base;
1484 ns += vgettsc(cycle_now);
1485 ns >>= gtod->clock.shift;
1486 ns += gtod->boot_ns;
1487 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1488 *t = ns;
1489
1490 return mode;
1491 }
1492
1493 /* returns true if host is using tsc clocksource */
1494 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1495 {
1496 /* checked again under seqlock below */
1497 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1498 return false;
1499
1500 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1501 }
1502 #endif
1503
1504 /*
1505 *
1506 * Assuming a stable TSC across physical CPUS, and a stable TSC
1507 * across virtual CPUs, the following condition is possible.
1508 * Each numbered line represents an event visible to both
1509 * CPUs at the next numbered event.
1510 *
1511 * "timespecX" represents host monotonic time. "tscX" represents
1512 * RDTSC value.
1513 *
1514 * VCPU0 on CPU0 | VCPU1 on CPU1
1515 *
1516 * 1. read timespec0,tsc0
1517 * 2. | timespec1 = timespec0 + N
1518 * | tsc1 = tsc0 + M
1519 * 3. transition to guest | transition to guest
1520 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1521 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1522 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1523 *
1524 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1525 *
1526 * - ret0 < ret1
1527 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1528 * ...
1529 * - 0 < N - M => M < N
1530 *
1531 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1532 * always the case (the difference between two distinct xtime instances
1533 * might be smaller then the difference between corresponding TSC reads,
1534 * when updating guest vcpus pvclock areas).
1535 *
1536 * To avoid that problem, do not allow visibility of distinct
1537 * system_timestamp/tsc_timestamp values simultaneously: use a master
1538 * copy of host monotonic time values. Update that master copy
1539 * in lockstep.
1540 *
1541 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1542 *
1543 */
1544
1545 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1546 {
1547 #ifdef CONFIG_X86_64
1548 struct kvm_arch *ka = &kvm->arch;
1549 int vclock_mode;
1550 bool host_tsc_clocksource, vcpus_matched;
1551
1552 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1553 atomic_read(&kvm->online_vcpus));
1554
1555 /*
1556 * If the host uses TSC clock, then passthrough TSC as stable
1557 * to the guest.
1558 */
1559 host_tsc_clocksource = kvm_get_time_and_clockread(
1560 &ka->master_kernel_ns,
1561 &ka->master_cycle_now);
1562
1563 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1564 && !backwards_tsc_observed
1565 && !ka->boot_vcpu_runs_old_kvmclock;
1566
1567 if (ka->use_master_clock)
1568 atomic_set(&kvm_guest_has_master_clock, 1);
1569
1570 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1571 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1572 vcpus_matched);
1573 #endif
1574 }
1575
1576 static void kvm_gen_update_masterclock(struct kvm *kvm)
1577 {
1578 #ifdef CONFIG_X86_64
1579 int i;
1580 struct kvm_vcpu *vcpu;
1581 struct kvm_arch *ka = &kvm->arch;
1582
1583 spin_lock(&ka->pvclock_gtod_sync_lock);
1584 kvm_make_mclock_inprogress_request(kvm);
1585 /* no guest entries from this point */
1586 pvclock_update_vm_gtod_copy(kvm);
1587
1588 kvm_for_each_vcpu(i, vcpu, kvm)
1589 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1590
1591 /* guest entries allowed */
1592 kvm_for_each_vcpu(i, vcpu, kvm)
1593 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1594
1595 spin_unlock(&ka->pvclock_gtod_sync_lock);
1596 #endif
1597 }
1598
1599 static int kvm_guest_time_update(struct kvm_vcpu *v)
1600 {
1601 unsigned long flags, this_tsc_khz;
1602 struct kvm_vcpu_arch *vcpu = &v->arch;
1603 struct kvm_arch *ka = &v->kvm->arch;
1604 s64 kernel_ns;
1605 u64 tsc_timestamp, host_tsc;
1606 struct pvclock_vcpu_time_info guest_hv_clock;
1607 u8 pvclock_flags;
1608 bool use_master_clock;
1609
1610 kernel_ns = 0;
1611 host_tsc = 0;
1612
1613 /*
1614 * If the host uses TSC clock, then passthrough TSC as stable
1615 * to the guest.
1616 */
1617 spin_lock(&ka->pvclock_gtod_sync_lock);
1618 use_master_clock = ka->use_master_clock;
1619 if (use_master_clock) {
1620 host_tsc = ka->master_cycle_now;
1621 kernel_ns = ka->master_kernel_ns;
1622 }
1623 spin_unlock(&ka->pvclock_gtod_sync_lock);
1624
1625 /* Keep irq disabled to prevent changes to the clock */
1626 local_irq_save(flags);
1627 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1628 if (unlikely(this_tsc_khz == 0)) {
1629 local_irq_restore(flags);
1630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1631 return 1;
1632 }
1633 if (!use_master_clock) {
1634 host_tsc = rdtsc();
1635 kernel_ns = get_kernel_ns();
1636 }
1637
1638 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1639
1640 /*
1641 * We may have to catch up the TSC to match elapsed wall clock
1642 * time for two reasons, even if kvmclock is used.
1643 * 1) CPU could have been running below the maximum TSC rate
1644 * 2) Broken TSC compensation resets the base at each VCPU
1645 * entry to avoid unknown leaps of TSC even when running
1646 * again on the same CPU. This may cause apparent elapsed
1647 * time to disappear, and the guest to stand still or run
1648 * very slowly.
1649 */
1650 if (vcpu->tsc_catchup) {
1651 u64 tsc = compute_guest_tsc(v, kernel_ns);
1652 if (tsc > tsc_timestamp) {
1653 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1654 tsc_timestamp = tsc;
1655 }
1656 }
1657
1658 local_irq_restore(flags);
1659
1660 if (!vcpu->pv_time_enabled)
1661 return 0;
1662
1663 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1664 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1665 &vcpu->hv_clock.tsc_shift,
1666 &vcpu->hv_clock.tsc_to_system_mul);
1667 vcpu->hw_tsc_khz = this_tsc_khz;
1668 }
1669
1670 /* With all the info we got, fill in the values */
1671 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1672 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1673 vcpu->last_guest_tsc = tsc_timestamp;
1674
1675 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1676 &guest_hv_clock, sizeof(guest_hv_clock))))
1677 return 0;
1678
1679 /* This VCPU is paused, but it's legal for a guest to read another
1680 * VCPU's kvmclock, so we really have to follow the specification where
1681 * it says that version is odd if data is being modified, and even after
1682 * it is consistent.
1683 *
1684 * Version field updates must be kept separate. This is because
1685 * kvm_write_guest_cached might use a "rep movs" instruction, and
1686 * writes within a string instruction are weakly ordered. So there
1687 * are three writes overall.
1688 *
1689 * As a small optimization, only write the version field in the first
1690 * and third write. The vcpu->pv_time cache is still valid, because the
1691 * version field is the first in the struct.
1692 */
1693 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1694
1695 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1696 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1697 &vcpu->hv_clock,
1698 sizeof(vcpu->hv_clock.version));
1699
1700 smp_wmb();
1701
1702 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1703 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1704
1705 if (vcpu->pvclock_set_guest_stopped_request) {
1706 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1707 vcpu->pvclock_set_guest_stopped_request = false;
1708 }
1709
1710 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1711
1712 /* If the host uses TSC clocksource, then it is stable */
1713 if (use_master_clock)
1714 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1715
1716 vcpu->hv_clock.flags = pvclock_flags;
1717
1718 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1719
1720 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1721 &vcpu->hv_clock,
1722 sizeof(vcpu->hv_clock));
1723
1724 smp_wmb();
1725
1726 vcpu->hv_clock.version++;
1727 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1728 &vcpu->hv_clock,
1729 sizeof(vcpu->hv_clock.version));
1730 return 0;
1731 }
1732
1733 /*
1734 * kvmclock updates which are isolated to a given vcpu, such as
1735 * vcpu->cpu migration, should not allow system_timestamp from
1736 * the rest of the vcpus to remain static. Otherwise ntp frequency
1737 * correction applies to one vcpu's system_timestamp but not
1738 * the others.
1739 *
1740 * So in those cases, request a kvmclock update for all vcpus.
1741 * We need to rate-limit these requests though, as they can
1742 * considerably slow guests that have a large number of vcpus.
1743 * The time for a remote vcpu to update its kvmclock is bound
1744 * by the delay we use to rate-limit the updates.
1745 */
1746
1747 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1748
1749 static void kvmclock_update_fn(struct work_struct *work)
1750 {
1751 int i;
1752 struct delayed_work *dwork = to_delayed_work(work);
1753 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1754 kvmclock_update_work);
1755 struct kvm *kvm = container_of(ka, struct kvm, arch);
1756 struct kvm_vcpu *vcpu;
1757
1758 kvm_for_each_vcpu(i, vcpu, kvm) {
1759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1760 kvm_vcpu_kick(vcpu);
1761 }
1762 }
1763
1764 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1765 {
1766 struct kvm *kvm = v->kvm;
1767
1768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1769 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1770 KVMCLOCK_UPDATE_DELAY);
1771 }
1772
1773 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1774
1775 static void kvmclock_sync_fn(struct work_struct *work)
1776 {
1777 struct delayed_work *dwork = to_delayed_work(work);
1778 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1779 kvmclock_sync_work);
1780 struct kvm *kvm = container_of(ka, struct kvm, arch);
1781
1782 if (!kvmclock_periodic_sync)
1783 return;
1784
1785 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1786 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1787 KVMCLOCK_SYNC_PERIOD);
1788 }
1789
1790 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1791 {
1792 u64 mcg_cap = vcpu->arch.mcg_cap;
1793 unsigned bank_num = mcg_cap & 0xff;
1794
1795 switch (msr) {
1796 case MSR_IA32_MCG_STATUS:
1797 vcpu->arch.mcg_status = data;
1798 break;
1799 case MSR_IA32_MCG_CTL:
1800 if (!(mcg_cap & MCG_CTL_P))
1801 return 1;
1802 if (data != 0 && data != ~(u64)0)
1803 return -1;
1804 vcpu->arch.mcg_ctl = data;
1805 break;
1806 default:
1807 if (msr >= MSR_IA32_MC0_CTL &&
1808 msr < MSR_IA32_MCx_CTL(bank_num)) {
1809 u32 offset = msr - MSR_IA32_MC0_CTL;
1810 /* only 0 or all 1s can be written to IA32_MCi_CTL
1811 * some Linux kernels though clear bit 10 in bank 4 to
1812 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1813 * this to avoid an uncatched #GP in the guest
1814 */
1815 if ((offset & 0x3) == 0 &&
1816 data != 0 && (data | (1 << 10)) != ~(u64)0)
1817 return -1;
1818 vcpu->arch.mce_banks[offset] = data;
1819 break;
1820 }
1821 return 1;
1822 }
1823 return 0;
1824 }
1825
1826 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1827 {
1828 struct kvm *kvm = vcpu->kvm;
1829 int lm = is_long_mode(vcpu);
1830 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1831 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1832 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1833 : kvm->arch.xen_hvm_config.blob_size_32;
1834 u32 page_num = data & ~PAGE_MASK;
1835 u64 page_addr = data & PAGE_MASK;
1836 u8 *page;
1837 int r;
1838
1839 r = -E2BIG;
1840 if (page_num >= blob_size)
1841 goto out;
1842 r = -ENOMEM;
1843 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1844 if (IS_ERR(page)) {
1845 r = PTR_ERR(page);
1846 goto out;
1847 }
1848 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1849 goto out_free;
1850 r = 0;
1851 out_free:
1852 kfree(page);
1853 out:
1854 return r;
1855 }
1856
1857 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1858 {
1859 gpa_t gpa = data & ~0x3f;
1860
1861 /* Bits 2:5 are reserved, Should be zero */
1862 if (data & 0x3c)
1863 return 1;
1864
1865 vcpu->arch.apf.msr_val = data;
1866
1867 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1868 kvm_clear_async_pf_completion_queue(vcpu);
1869 kvm_async_pf_hash_reset(vcpu);
1870 return 0;
1871 }
1872
1873 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1874 sizeof(u32)))
1875 return 1;
1876
1877 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1878 kvm_async_pf_wakeup_all(vcpu);
1879 return 0;
1880 }
1881
1882 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1883 {
1884 vcpu->arch.pv_time_enabled = false;
1885 }
1886
1887 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1888 {
1889 u64 delta;
1890
1891 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1892 return;
1893
1894 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1895 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1896 vcpu->arch.st.accum_steal = delta;
1897 }
1898
1899 static void record_steal_time(struct kvm_vcpu *vcpu)
1900 {
1901 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1902 return;
1903
1904 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1905 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1906 return;
1907
1908 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1909 vcpu->arch.st.steal.version += 2;
1910 vcpu->arch.st.accum_steal = 0;
1911
1912 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1913 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1914 }
1915
1916 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1917 {
1918 bool pr = false;
1919 u32 msr = msr_info->index;
1920 u64 data = msr_info->data;
1921
1922 switch (msr) {
1923 case MSR_AMD64_NB_CFG:
1924 case MSR_IA32_UCODE_REV:
1925 case MSR_IA32_UCODE_WRITE:
1926 case MSR_VM_HSAVE_PA:
1927 case MSR_AMD64_PATCH_LOADER:
1928 case MSR_AMD64_BU_CFG2:
1929 break;
1930
1931 case MSR_EFER:
1932 return set_efer(vcpu, data);
1933 case MSR_K7_HWCR:
1934 data &= ~(u64)0x40; /* ignore flush filter disable */
1935 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1936 data &= ~(u64)0x8; /* ignore TLB cache disable */
1937 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1938 if (data != 0) {
1939 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1940 data);
1941 return 1;
1942 }
1943 break;
1944 case MSR_FAM10H_MMIO_CONF_BASE:
1945 if (data != 0) {
1946 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1947 "0x%llx\n", data);
1948 return 1;
1949 }
1950 break;
1951 case MSR_IA32_DEBUGCTLMSR:
1952 if (!data) {
1953 /* We support the non-activated case already */
1954 break;
1955 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1956 /* Values other than LBR and BTF are vendor-specific,
1957 thus reserved and should throw a #GP */
1958 return 1;
1959 }
1960 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1961 __func__, data);
1962 break;
1963 case 0x200 ... 0x2ff:
1964 return kvm_mtrr_set_msr(vcpu, msr, data);
1965 case MSR_IA32_APICBASE:
1966 return kvm_set_apic_base(vcpu, msr_info);
1967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1968 return kvm_x2apic_msr_write(vcpu, msr, data);
1969 case MSR_IA32_TSCDEADLINE:
1970 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1971 break;
1972 case MSR_IA32_TSC_ADJUST:
1973 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1974 if (!msr_info->host_initiated) {
1975 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1976 adjust_tsc_offset_guest(vcpu, adj);
1977 }
1978 vcpu->arch.ia32_tsc_adjust_msr = data;
1979 }
1980 break;
1981 case MSR_IA32_MISC_ENABLE:
1982 vcpu->arch.ia32_misc_enable_msr = data;
1983 break;
1984 case MSR_IA32_SMBASE:
1985 if (!msr_info->host_initiated)
1986 return 1;
1987 vcpu->arch.smbase = data;
1988 break;
1989 case MSR_KVM_WALL_CLOCK_NEW:
1990 case MSR_KVM_WALL_CLOCK:
1991 vcpu->kvm->arch.wall_clock = data;
1992 kvm_write_wall_clock(vcpu->kvm, data);
1993 break;
1994 case MSR_KVM_SYSTEM_TIME_NEW:
1995 case MSR_KVM_SYSTEM_TIME: {
1996 u64 gpa_offset;
1997 struct kvm_arch *ka = &vcpu->kvm->arch;
1998
1999 kvmclock_reset(vcpu);
2000
2001 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2002 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2003
2004 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2005 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2006 &vcpu->requests);
2007
2008 ka->boot_vcpu_runs_old_kvmclock = tmp;
2009
2010 ka->kvmclock_offset = -get_kernel_ns();
2011 }
2012
2013 vcpu->arch.time = data;
2014 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2015
2016 /* we verify if the enable bit is set... */
2017 if (!(data & 1))
2018 break;
2019
2020 gpa_offset = data & ~(PAGE_MASK | 1);
2021
2022 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2023 &vcpu->arch.pv_time, data & ~1ULL,
2024 sizeof(struct pvclock_vcpu_time_info)))
2025 vcpu->arch.pv_time_enabled = false;
2026 else
2027 vcpu->arch.pv_time_enabled = true;
2028
2029 break;
2030 }
2031 case MSR_KVM_ASYNC_PF_EN:
2032 if (kvm_pv_enable_async_pf(vcpu, data))
2033 return 1;
2034 break;
2035 case MSR_KVM_STEAL_TIME:
2036
2037 if (unlikely(!sched_info_on()))
2038 return 1;
2039
2040 if (data & KVM_STEAL_RESERVED_MASK)
2041 return 1;
2042
2043 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2044 data & KVM_STEAL_VALID_BITS,
2045 sizeof(struct kvm_steal_time)))
2046 return 1;
2047
2048 vcpu->arch.st.msr_val = data;
2049
2050 if (!(data & KVM_MSR_ENABLED))
2051 break;
2052
2053 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2054
2055 preempt_disable();
2056 accumulate_steal_time(vcpu);
2057 preempt_enable();
2058
2059 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2060
2061 break;
2062 case MSR_KVM_PV_EOI_EN:
2063 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2064 return 1;
2065 break;
2066
2067 case MSR_IA32_MCG_CTL:
2068 case MSR_IA32_MCG_STATUS:
2069 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2070 return set_msr_mce(vcpu, msr, data);
2071
2072 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2073 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2074 pr = true; /* fall through */
2075 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2076 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2077 if (kvm_pmu_is_valid_msr(vcpu, msr))
2078 return kvm_pmu_set_msr(vcpu, msr_info);
2079
2080 if (pr || data != 0)
2081 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2082 "0x%x data 0x%llx\n", msr, data);
2083 break;
2084 case MSR_K7_CLK_CTL:
2085 /*
2086 * Ignore all writes to this no longer documented MSR.
2087 * Writes are only relevant for old K7 processors,
2088 * all pre-dating SVM, but a recommended workaround from
2089 * AMD for these chips. It is possible to specify the
2090 * affected processor models on the command line, hence
2091 * the need to ignore the workaround.
2092 */
2093 break;
2094 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2095 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2096 case HV_X64_MSR_CRASH_CTL:
2097 return kvm_hv_set_msr_common(vcpu, msr, data,
2098 msr_info->host_initiated);
2099 case MSR_IA32_BBL_CR_CTL3:
2100 /* Drop writes to this legacy MSR -- see rdmsr
2101 * counterpart for further detail.
2102 */
2103 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2104 break;
2105 case MSR_AMD64_OSVW_ID_LENGTH:
2106 if (!guest_cpuid_has_osvw(vcpu))
2107 return 1;
2108 vcpu->arch.osvw.length = data;
2109 break;
2110 case MSR_AMD64_OSVW_STATUS:
2111 if (!guest_cpuid_has_osvw(vcpu))
2112 return 1;
2113 vcpu->arch.osvw.status = data;
2114 break;
2115 default:
2116 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2117 return xen_hvm_config(vcpu, data);
2118 if (kvm_pmu_is_valid_msr(vcpu, msr))
2119 return kvm_pmu_set_msr(vcpu, msr_info);
2120 if (!ignore_msrs) {
2121 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2122 msr, data);
2123 return 1;
2124 } else {
2125 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2126 msr, data);
2127 break;
2128 }
2129 }
2130 return 0;
2131 }
2132 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2133
2134
2135 /*
2136 * Reads an msr value (of 'msr_index') into 'pdata'.
2137 * Returns 0 on success, non-0 otherwise.
2138 * Assumes vcpu_load() was already called.
2139 */
2140 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2141 {
2142 return kvm_x86_ops->get_msr(vcpu, msr);
2143 }
2144 EXPORT_SYMBOL_GPL(kvm_get_msr);
2145
2146 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2147 {
2148 u64 data;
2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
2151
2152 switch (msr) {
2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
2155 data = 0;
2156 break;
2157 case MSR_IA32_MCG_CAP:
2158 data = vcpu->arch.mcg_cap;
2159 break;
2160 case MSR_IA32_MCG_CTL:
2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 data = vcpu->arch.mcg_ctl;
2164 break;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2167 break;
2168 default:
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MCx_CTL(bank_num)) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2173 break;
2174 }
2175 return 1;
2176 }
2177 *pdata = data;
2178 return 0;
2179 }
2180
2181 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2182 {
2183 switch (msr_info->index) {
2184 case MSR_IA32_PLATFORM_ID:
2185 case MSR_IA32_EBL_CR_POWERON:
2186 case MSR_IA32_DEBUGCTLMSR:
2187 case MSR_IA32_LASTBRANCHFROMIP:
2188 case MSR_IA32_LASTBRANCHTOIP:
2189 case MSR_IA32_LASTINTFROMIP:
2190 case MSR_IA32_LASTINTTOIP:
2191 case MSR_K8_SYSCFG:
2192 case MSR_K7_HWCR:
2193 case MSR_VM_HSAVE_PA:
2194 case MSR_K8_INT_PENDING_MSG:
2195 case MSR_AMD64_NB_CFG:
2196 case MSR_FAM10H_MMIO_CONF_BASE:
2197 case MSR_AMD64_BU_CFG2:
2198 msr_info->data = 0;
2199 break;
2200 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2201 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2202 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2203 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2204 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2205 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2206 msr_info->data = 0;
2207 break;
2208 case MSR_IA32_UCODE_REV:
2209 msr_info->data = 0x100000000ULL;
2210 break;
2211 case MSR_MTRRcap:
2212 case 0x200 ... 0x2ff:
2213 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2214 case 0xcd: /* fsb frequency */
2215 msr_info->data = 3;
2216 break;
2217 /*
2218 * MSR_EBC_FREQUENCY_ID
2219 * Conservative value valid for even the basic CPU models.
2220 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2221 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2222 * and 266MHz for model 3, or 4. Set Core Clock
2223 * Frequency to System Bus Frequency Ratio to 1 (bits
2224 * 31:24) even though these are only valid for CPU
2225 * models > 2, however guests may end up dividing or
2226 * multiplying by zero otherwise.
2227 */
2228 case MSR_EBC_FREQUENCY_ID:
2229 msr_info->data = 1 << 24;
2230 break;
2231 case MSR_IA32_APICBASE:
2232 msr_info->data = kvm_get_apic_base(vcpu);
2233 break;
2234 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2235 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2236 break;
2237 case MSR_IA32_TSCDEADLINE:
2238 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2239 break;
2240 case MSR_IA32_TSC_ADJUST:
2241 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2242 break;
2243 case MSR_IA32_MISC_ENABLE:
2244 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2245 break;
2246 case MSR_IA32_SMBASE:
2247 if (!msr_info->host_initiated)
2248 return 1;
2249 msr_info->data = vcpu->arch.smbase;
2250 break;
2251 case MSR_IA32_PERF_STATUS:
2252 /* TSC increment by tick */
2253 msr_info->data = 1000ULL;
2254 /* CPU multiplier */
2255 msr_info->data |= (((uint64_t)4ULL) << 40);
2256 break;
2257 case MSR_EFER:
2258 msr_info->data = vcpu->arch.efer;
2259 break;
2260 case MSR_KVM_WALL_CLOCK:
2261 case MSR_KVM_WALL_CLOCK_NEW:
2262 msr_info->data = vcpu->kvm->arch.wall_clock;
2263 break;
2264 case MSR_KVM_SYSTEM_TIME:
2265 case MSR_KVM_SYSTEM_TIME_NEW:
2266 msr_info->data = vcpu->arch.time;
2267 break;
2268 case MSR_KVM_ASYNC_PF_EN:
2269 msr_info->data = vcpu->arch.apf.msr_val;
2270 break;
2271 case MSR_KVM_STEAL_TIME:
2272 msr_info->data = vcpu->arch.st.msr_val;
2273 break;
2274 case MSR_KVM_PV_EOI_EN:
2275 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2276 break;
2277 case MSR_IA32_P5_MC_ADDR:
2278 case MSR_IA32_P5_MC_TYPE:
2279 case MSR_IA32_MCG_CAP:
2280 case MSR_IA32_MCG_CTL:
2281 case MSR_IA32_MCG_STATUS:
2282 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2283 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2284 case MSR_K7_CLK_CTL:
2285 /*
2286 * Provide expected ramp-up count for K7. All other
2287 * are set to zero, indicating minimum divisors for
2288 * every field.
2289 *
2290 * This prevents guest kernels on AMD host with CPU
2291 * type 6, model 8 and higher from exploding due to
2292 * the rdmsr failing.
2293 */
2294 msr_info->data = 0x20000000;
2295 break;
2296 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2297 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2298 case HV_X64_MSR_CRASH_CTL:
2299 return kvm_hv_get_msr_common(vcpu,
2300 msr_info->index, &msr_info->data);
2301 break;
2302 case MSR_IA32_BBL_CR_CTL3:
2303 /* This legacy MSR exists but isn't fully documented in current
2304 * silicon. It is however accessed by winxp in very narrow
2305 * scenarios where it sets bit #19, itself documented as
2306 * a "reserved" bit. Best effort attempt to source coherent
2307 * read data here should the balance of the register be
2308 * interpreted by the guest:
2309 *
2310 * L2 cache control register 3: 64GB range, 256KB size,
2311 * enabled, latency 0x1, configured
2312 */
2313 msr_info->data = 0xbe702111;
2314 break;
2315 case MSR_AMD64_OSVW_ID_LENGTH:
2316 if (!guest_cpuid_has_osvw(vcpu))
2317 return 1;
2318 msr_info->data = vcpu->arch.osvw.length;
2319 break;
2320 case MSR_AMD64_OSVW_STATUS:
2321 if (!guest_cpuid_has_osvw(vcpu))
2322 return 1;
2323 msr_info->data = vcpu->arch.osvw.status;
2324 break;
2325 default:
2326 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2327 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2328 if (!ignore_msrs) {
2329 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2330 return 1;
2331 } else {
2332 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2333 msr_info->data = 0;
2334 }
2335 break;
2336 }
2337 return 0;
2338 }
2339 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2340
2341 /*
2342 * Read or write a bunch of msrs. All parameters are kernel addresses.
2343 *
2344 * @return number of msrs set successfully.
2345 */
2346 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2347 struct kvm_msr_entry *entries,
2348 int (*do_msr)(struct kvm_vcpu *vcpu,
2349 unsigned index, u64 *data))
2350 {
2351 int i, idx;
2352
2353 idx = srcu_read_lock(&vcpu->kvm->srcu);
2354 for (i = 0; i < msrs->nmsrs; ++i)
2355 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2356 break;
2357 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2358
2359 return i;
2360 }
2361
2362 /*
2363 * Read or write a bunch of msrs. Parameters are user addresses.
2364 *
2365 * @return number of msrs set successfully.
2366 */
2367 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2368 int (*do_msr)(struct kvm_vcpu *vcpu,
2369 unsigned index, u64 *data),
2370 int writeback)
2371 {
2372 struct kvm_msrs msrs;
2373 struct kvm_msr_entry *entries;
2374 int r, n;
2375 unsigned size;
2376
2377 r = -EFAULT;
2378 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2379 goto out;
2380
2381 r = -E2BIG;
2382 if (msrs.nmsrs >= MAX_IO_MSRS)
2383 goto out;
2384
2385 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2386 entries = memdup_user(user_msrs->entries, size);
2387 if (IS_ERR(entries)) {
2388 r = PTR_ERR(entries);
2389 goto out;
2390 }
2391
2392 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2393 if (r < 0)
2394 goto out_free;
2395
2396 r = -EFAULT;
2397 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2398 goto out_free;
2399
2400 r = n;
2401
2402 out_free:
2403 kfree(entries);
2404 out:
2405 return r;
2406 }
2407
2408 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2409 {
2410 int r;
2411
2412 switch (ext) {
2413 case KVM_CAP_IRQCHIP:
2414 case KVM_CAP_HLT:
2415 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2416 case KVM_CAP_SET_TSS_ADDR:
2417 case KVM_CAP_EXT_CPUID:
2418 case KVM_CAP_EXT_EMUL_CPUID:
2419 case KVM_CAP_CLOCKSOURCE:
2420 case KVM_CAP_PIT:
2421 case KVM_CAP_NOP_IO_DELAY:
2422 case KVM_CAP_MP_STATE:
2423 case KVM_CAP_SYNC_MMU:
2424 case KVM_CAP_USER_NMI:
2425 case KVM_CAP_REINJECT_CONTROL:
2426 case KVM_CAP_IRQ_INJECT_STATUS:
2427 case KVM_CAP_IOEVENTFD:
2428 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2429 case KVM_CAP_PIT2:
2430 case KVM_CAP_PIT_STATE2:
2431 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2432 case KVM_CAP_XEN_HVM:
2433 case KVM_CAP_ADJUST_CLOCK:
2434 case KVM_CAP_VCPU_EVENTS:
2435 case KVM_CAP_HYPERV:
2436 case KVM_CAP_HYPERV_VAPIC:
2437 case KVM_CAP_HYPERV_SPIN:
2438 case KVM_CAP_PCI_SEGMENT:
2439 case KVM_CAP_DEBUGREGS:
2440 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2441 case KVM_CAP_XSAVE:
2442 case KVM_CAP_ASYNC_PF:
2443 case KVM_CAP_GET_TSC_KHZ:
2444 case KVM_CAP_KVMCLOCK_CTRL:
2445 case KVM_CAP_READONLY_MEM:
2446 case KVM_CAP_HYPERV_TIME:
2447 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2448 case KVM_CAP_TSC_DEADLINE_TIMER:
2449 case KVM_CAP_ENABLE_CAP_VM:
2450 case KVM_CAP_DISABLE_QUIRKS:
2451 case KVM_CAP_SET_BOOT_CPU_ID:
2452 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2453 case KVM_CAP_ASSIGN_DEV_IRQ:
2454 case KVM_CAP_PCI_2_3:
2455 #endif
2456 r = 1;
2457 break;
2458 case KVM_CAP_X86_SMM:
2459 /* SMBASE is usually relocated above 1M on modern chipsets,
2460 * and SMM handlers might indeed rely on 4G segment limits,
2461 * so do not report SMM to be available if real mode is
2462 * emulated via vm86 mode. Still, do not go to great lengths
2463 * to avoid userspace's usage of the feature, because it is a
2464 * fringe case that is not enabled except via specific settings
2465 * of the module parameters.
2466 */
2467 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2468 break;
2469 case KVM_CAP_COALESCED_MMIO:
2470 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2471 break;
2472 case KVM_CAP_VAPIC:
2473 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2474 break;
2475 case KVM_CAP_NR_VCPUS:
2476 r = KVM_SOFT_MAX_VCPUS;
2477 break;
2478 case KVM_CAP_MAX_VCPUS:
2479 r = KVM_MAX_VCPUS;
2480 break;
2481 case KVM_CAP_NR_MEMSLOTS:
2482 r = KVM_USER_MEM_SLOTS;
2483 break;
2484 case KVM_CAP_PV_MMU: /* obsolete */
2485 r = 0;
2486 break;
2487 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2488 case KVM_CAP_IOMMU:
2489 r = iommu_present(&pci_bus_type);
2490 break;
2491 #endif
2492 case KVM_CAP_MCE:
2493 r = KVM_MAX_MCE_BANKS;
2494 break;
2495 case KVM_CAP_XCRS:
2496 r = cpu_has_xsave;
2497 break;
2498 case KVM_CAP_TSC_CONTROL:
2499 r = kvm_has_tsc_control;
2500 break;
2501 default:
2502 r = 0;
2503 break;
2504 }
2505 return r;
2506
2507 }
2508
2509 long kvm_arch_dev_ioctl(struct file *filp,
2510 unsigned int ioctl, unsigned long arg)
2511 {
2512 void __user *argp = (void __user *)arg;
2513 long r;
2514
2515 switch (ioctl) {
2516 case KVM_GET_MSR_INDEX_LIST: {
2517 struct kvm_msr_list __user *user_msr_list = argp;
2518 struct kvm_msr_list msr_list;
2519 unsigned n;
2520
2521 r = -EFAULT;
2522 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2523 goto out;
2524 n = msr_list.nmsrs;
2525 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2526 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2527 goto out;
2528 r = -E2BIG;
2529 if (n < msr_list.nmsrs)
2530 goto out;
2531 r = -EFAULT;
2532 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2533 num_msrs_to_save * sizeof(u32)))
2534 goto out;
2535 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2536 &emulated_msrs,
2537 num_emulated_msrs * sizeof(u32)))
2538 goto out;
2539 r = 0;
2540 break;
2541 }
2542 case KVM_GET_SUPPORTED_CPUID:
2543 case KVM_GET_EMULATED_CPUID: {
2544 struct kvm_cpuid2 __user *cpuid_arg = argp;
2545 struct kvm_cpuid2 cpuid;
2546
2547 r = -EFAULT;
2548 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2549 goto out;
2550
2551 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2552 ioctl);
2553 if (r)
2554 goto out;
2555
2556 r = -EFAULT;
2557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2558 goto out;
2559 r = 0;
2560 break;
2561 }
2562 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2563 u64 mce_cap;
2564
2565 mce_cap = KVM_MCE_CAP_SUPPORTED;
2566 r = -EFAULT;
2567 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2568 goto out;
2569 r = 0;
2570 break;
2571 }
2572 default:
2573 r = -EINVAL;
2574 }
2575 out:
2576 return r;
2577 }
2578
2579 static void wbinvd_ipi(void *garbage)
2580 {
2581 wbinvd();
2582 }
2583
2584 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2585 {
2586 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2587 }
2588
2589 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2590 {
2591 /* Address WBINVD may be executed by guest */
2592 if (need_emulate_wbinvd(vcpu)) {
2593 if (kvm_x86_ops->has_wbinvd_exit())
2594 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2595 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2596 smp_call_function_single(vcpu->cpu,
2597 wbinvd_ipi, NULL, 1);
2598 }
2599
2600 kvm_x86_ops->vcpu_load(vcpu, cpu);
2601
2602 /* Apply any externally detected TSC adjustments (due to suspend) */
2603 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2604 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2605 vcpu->arch.tsc_offset_adjustment = 0;
2606 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2607 }
2608
2609 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2610 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2611 rdtsc() - vcpu->arch.last_host_tsc;
2612 if (tsc_delta < 0)
2613 mark_tsc_unstable("KVM discovered backwards TSC");
2614 if (check_tsc_unstable()) {
2615 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2616 vcpu->arch.last_guest_tsc);
2617 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2618 vcpu->arch.tsc_catchup = 1;
2619 }
2620 /*
2621 * On a host with synchronized TSC, there is no need to update
2622 * kvmclock on vcpu->cpu migration
2623 */
2624 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2625 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2626 if (vcpu->cpu != cpu)
2627 kvm_migrate_timers(vcpu);
2628 vcpu->cpu = cpu;
2629 }
2630
2631 accumulate_steal_time(vcpu);
2632 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2633 }
2634
2635 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2636 {
2637 kvm_x86_ops->vcpu_put(vcpu);
2638 kvm_put_guest_fpu(vcpu);
2639 vcpu->arch.last_host_tsc = rdtsc();
2640 }
2641
2642 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2643 struct kvm_lapic_state *s)
2644 {
2645 kvm_x86_ops->sync_pir_to_irr(vcpu);
2646 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2647
2648 return 0;
2649 }
2650
2651 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2652 struct kvm_lapic_state *s)
2653 {
2654 kvm_apic_post_state_restore(vcpu, s);
2655 update_cr8_intercept(vcpu);
2656
2657 return 0;
2658 }
2659
2660 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2661 struct kvm_interrupt *irq)
2662 {
2663 if (irq->irq >= KVM_NR_INTERRUPTS)
2664 return -EINVAL;
2665 if (irqchip_in_kernel(vcpu->kvm))
2666 return -ENXIO;
2667
2668 kvm_queue_interrupt(vcpu, irq->irq, false);
2669 kvm_make_request(KVM_REQ_EVENT, vcpu);
2670
2671 return 0;
2672 }
2673
2674 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2675 {
2676 kvm_inject_nmi(vcpu);
2677
2678 return 0;
2679 }
2680
2681 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2682 {
2683 kvm_make_request(KVM_REQ_SMI, vcpu);
2684
2685 return 0;
2686 }
2687
2688 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2689 struct kvm_tpr_access_ctl *tac)
2690 {
2691 if (tac->flags)
2692 return -EINVAL;
2693 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2694 return 0;
2695 }
2696
2697 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2698 u64 mcg_cap)
2699 {
2700 int r;
2701 unsigned bank_num = mcg_cap & 0xff, bank;
2702
2703 r = -EINVAL;
2704 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2705 goto out;
2706 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2707 goto out;
2708 r = 0;
2709 vcpu->arch.mcg_cap = mcg_cap;
2710 /* Init IA32_MCG_CTL to all 1s */
2711 if (mcg_cap & MCG_CTL_P)
2712 vcpu->arch.mcg_ctl = ~(u64)0;
2713 /* Init IA32_MCi_CTL to all 1s */
2714 for (bank = 0; bank < bank_num; bank++)
2715 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2716 out:
2717 return r;
2718 }
2719
2720 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2721 struct kvm_x86_mce *mce)
2722 {
2723 u64 mcg_cap = vcpu->arch.mcg_cap;
2724 unsigned bank_num = mcg_cap & 0xff;
2725 u64 *banks = vcpu->arch.mce_banks;
2726
2727 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2728 return -EINVAL;
2729 /*
2730 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2731 * reporting is disabled
2732 */
2733 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2734 vcpu->arch.mcg_ctl != ~(u64)0)
2735 return 0;
2736 banks += 4 * mce->bank;
2737 /*
2738 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2739 * reporting is disabled for the bank
2740 */
2741 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2742 return 0;
2743 if (mce->status & MCI_STATUS_UC) {
2744 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2745 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2746 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2747 return 0;
2748 }
2749 if (banks[1] & MCI_STATUS_VAL)
2750 mce->status |= MCI_STATUS_OVER;
2751 banks[2] = mce->addr;
2752 banks[3] = mce->misc;
2753 vcpu->arch.mcg_status = mce->mcg_status;
2754 banks[1] = mce->status;
2755 kvm_queue_exception(vcpu, MC_VECTOR);
2756 } else if (!(banks[1] & MCI_STATUS_VAL)
2757 || !(banks[1] & MCI_STATUS_UC)) {
2758 if (banks[1] & MCI_STATUS_VAL)
2759 mce->status |= MCI_STATUS_OVER;
2760 banks[2] = mce->addr;
2761 banks[3] = mce->misc;
2762 banks[1] = mce->status;
2763 } else
2764 banks[1] |= MCI_STATUS_OVER;
2765 return 0;
2766 }
2767
2768 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2769 struct kvm_vcpu_events *events)
2770 {
2771 process_nmi(vcpu);
2772 events->exception.injected =
2773 vcpu->arch.exception.pending &&
2774 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2775 events->exception.nr = vcpu->arch.exception.nr;
2776 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2777 events->exception.pad = 0;
2778 events->exception.error_code = vcpu->arch.exception.error_code;
2779
2780 events->interrupt.injected =
2781 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2782 events->interrupt.nr = vcpu->arch.interrupt.nr;
2783 events->interrupt.soft = 0;
2784 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2785
2786 events->nmi.injected = vcpu->arch.nmi_injected;
2787 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2788 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2789 events->nmi.pad = 0;
2790
2791 events->sipi_vector = 0; /* never valid when reporting to user space */
2792
2793 events->smi.smm = is_smm(vcpu);
2794 events->smi.pending = vcpu->arch.smi_pending;
2795 events->smi.smm_inside_nmi =
2796 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2797 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2798
2799 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2800 | KVM_VCPUEVENT_VALID_SHADOW
2801 | KVM_VCPUEVENT_VALID_SMM);
2802 memset(&events->reserved, 0, sizeof(events->reserved));
2803 }
2804
2805 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2806 struct kvm_vcpu_events *events)
2807 {
2808 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2809 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2810 | KVM_VCPUEVENT_VALID_SHADOW
2811 | KVM_VCPUEVENT_VALID_SMM))
2812 return -EINVAL;
2813
2814 process_nmi(vcpu);
2815 vcpu->arch.exception.pending = events->exception.injected;
2816 vcpu->arch.exception.nr = events->exception.nr;
2817 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2818 vcpu->arch.exception.error_code = events->exception.error_code;
2819
2820 vcpu->arch.interrupt.pending = events->interrupt.injected;
2821 vcpu->arch.interrupt.nr = events->interrupt.nr;
2822 vcpu->arch.interrupt.soft = events->interrupt.soft;
2823 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2824 kvm_x86_ops->set_interrupt_shadow(vcpu,
2825 events->interrupt.shadow);
2826
2827 vcpu->arch.nmi_injected = events->nmi.injected;
2828 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2829 vcpu->arch.nmi_pending = events->nmi.pending;
2830 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2831
2832 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2833 kvm_vcpu_has_lapic(vcpu))
2834 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2835
2836 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2837 if (events->smi.smm)
2838 vcpu->arch.hflags |= HF_SMM_MASK;
2839 else
2840 vcpu->arch.hflags &= ~HF_SMM_MASK;
2841 vcpu->arch.smi_pending = events->smi.pending;
2842 if (events->smi.smm_inside_nmi)
2843 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2844 else
2845 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2846 if (kvm_vcpu_has_lapic(vcpu)) {
2847 if (events->smi.latched_init)
2848 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2849 else
2850 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2851 }
2852 }
2853
2854 kvm_make_request(KVM_REQ_EVENT, vcpu);
2855
2856 return 0;
2857 }
2858
2859 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2860 struct kvm_debugregs *dbgregs)
2861 {
2862 unsigned long val;
2863
2864 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2865 kvm_get_dr(vcpu, 6, &val);
2866 dbgregs->dr6 = val;
2867 dbgregs->dr7 = vcpu->arch.dr7;
2868 dbgregs->flags = 0;
2869 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2870 }
2871
2872 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2873 struct kvm_debugregs *dbgregs)
2874 {
2875 if (dbgregs->flags)
2876 return -EINVAL;
2877
2878 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2879 kvm_update_dr0123(vcpu);
2880 vcpu->arch.dr6 = dbgregs->dr6;
2881 kvm_update_dr6(vcpu);
2882 vcpu->arch.dr7 = dbgregs->dr7;
2883 kvm_update_dr7(vcpu);
2884
2885 return 0;
2886 }
2887
2888 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2889
2890 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2891 {
2892 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2893 u64 xstate_bv = xsave->header.xfeatures;
2894 u64 valid;
2895
2896 /*
2897 * Copy legacy XSAVE area, to avoid complications with CPUID
2898 * leaves 0 and 1 in the loop below.
2899 */
2900 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2901
2902 /* Set XSTATE_BV */
2903 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2904
2905 /*
2906 * Copy each region from the possibly compacted offset to the
2907 * non-compacted offset.
2908 */
2909 valid = xstate_bv & ~XSTATE_FPSSE;
2910 while (valid) {
2911 u64 feature = valid & -valid;
2912 int index = fls64(feature) - 1;
2913 void *src = get_xsave_addr(xsave, feature);
2914
2915 if (src) {
2916 u32 size, offset, ecx, edx;
2917 cpuid_count(XSTATE_CPUID, index,
2918 &size, &offset, &ecx, &edx);
2919 memcpy(dest + offset, src, size);
2920 }
2921
2922 valid -= feature;
2923 }
2924 }
2925
2926 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2927 {
2928 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2929 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2930 u64 valid;
2931
2932 /*
2933 * Copy legacy XSAVE area, to avoid complications with CPUID
2934 * leaves 0 and 1 in the loop below.
2935 */
2936 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2937
2938 /* Set XSTATE_BV and possibly XCOMP_BV. */
2939 xsave->header.xfeatures = xstate_bv;
2940 if (cpu_has_xsaves)
2941 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2942
2943 /*
2944 * Copy each region from the non-compacted offset to the
2945 * possibly compacted offset.
2946 */
2947 valid = xstate_bv & ~XSTATE_FPSSE;
2948 while (valid) {
2949 u64 feature = valid & -valid;
2950 int index = fls64(feature) - 1;
2951 void *dest = get_xsave_addr(xsave, feature);
2952
2953 if (dest) {
2954 u32 size, offset, ecx, edx;
2955 cpuid_count(XSTATE_CPUID, index,
2956 &size, &offset, &ecx, &edx);
2957 memcpy(dest, src + offset, size);
2958 }
2959
2960 valid -= feature;
2961 }
2962 }
2963
2964 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2965 struct kvm_xsave *guest_xsave)
2966 {
2967 if (cpu_has_xsave) {
2968 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2969 fill_xsave((u8 *) guest_xsave->region, vcpu);
2970 } else {
2971 memcpy(guest_xsave->region,
2972 &vcpu->arch.guest_fpu.state.fxsave,
2973 sizeof(struct fxregs_state));
2974 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2975 XSTATE_FPSSE;
2976 }
2977 }
2978
2979 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2980 struct kvm_xsave *guest_xsave)
2981 {
2982 u64 xstate_bv =
2983 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2984
2985 if (cpu_has_xsave) {
2986 /*
2987 * Here we allow setting states that are not present in
2988 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
2989 * with old userspace.
2990 */
2991 if (xstate_bv & ~kvm_supported_xcr0())
2992 return -EINVAL;
2993 load_xsave(vcpu, (u8 *)guest_xsave->region);
2994 } else {
2995 if (xstate_bv & ~XSTATE_FPSSE)
2996 return -EINVAL;
2997 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
2998 guest_xsave->region, sizeof(struct fxregs_state));
2999 }
3000 return 0;
3001 }
3002
3003 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3004 struct kvm_xcrs *guest_xcrs)
3005 {
3006 if (!cpu_has_xsave) {
3007 guest_xcrs->nr_xcrs = 0;
3008 return;
3009 }
3010
3011 guest_xcrs->nr_xcrs = 1;
3012 guest_xcrs->flags = 0;
3013 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3014 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3015 }
3016
3017 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3018 struct kvm_xcrs *guest_xcrs)
3019 {
3020 int i, r = 0;
3021
3022 if (!cpu_has_xsave)
3023 return -EINVAL;
3024
3025 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3026 return -EINVAL;
3027
3028 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3029 /* Only support XCR0 currently */
3030 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3031 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3032 guest_xcrs->xcrs[i].value);
3033 break;
3034 }
3035 if (r)
3036 r = -EINVAL;
3037 return r;
3038 }
3039
3040 /*
3041 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3042 * stopped by the hypervisor. This function will be called from the host only.
3043 * EINVAL is returned when the host attempts to set the flag for a guest that
3044 * does not support pv clocks.
3045 */
3046 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3047 {
3048 if (!vcpu->arch.pv_time_enabled)
3049 return -EINVAL;
3050 vcpu->arch.pvclock_set_guest_stopped_request = true;
3051 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3052 return 0;
3053 }
3054
3055 long kvm_arch_vcpu_ioctl(struct file *filp,
3056 unsigned int ioctl, unsigned long arg)
3057 {
3058 struct kvm_vcpu *vcpu = filp->private_data;
3059 void __user *argp = (void __user *)arg;
3060 int r;
3061 union {
3062 struct kvm_lapic_state *lapic;
3063 struct kvm_xsave *xsave;
3064 struct kvm_xcrs *xcrs;
3065 void *buffer;
3066 } u;
3067
3068 u.buffer = NULL;
3069 switch (ioctl) {
3070 case KVM_GET_LAPIC: {
3071 r = -EINVAL;
3072 if (!vcpu->arch.apic)
3073 goto out;
3074 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3075
3076 r = -ENOMEM;
3077 if (!u.lapic)
3078 goto out;
3079 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3080 if (r)
3081 goto out;
3082 r = -EFAULT;
3083 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3084 goto out;
3085 r = 0;
3086 break;
3087 }
3088 case KVM_SET_LAPIC: {
3089 r = -EINVAL;
3090 if (!vcpu->arch.apic)
3091 goto out;
3092 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3093 if (IS_ERR(u.lapic))
3094 return PTR_ERR(u.lapic);
3095
3096 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3097 break;
3098 }
3099 case KVM_INTERRUPT: {
3100 struct kvm_interrupt irq;
3101
3102 r = -EFAULT;
3103 if (copy_from_user(&irq, argp, sizeof irq))
3104 goto out;
3105 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3106 break;
3107 }
3108 case KVM_NMI: {
3109 r = kvm_vcpu_ioctl_nmi(vcpu);
3110 break;
3111 }
3112 case KVM_SMI: {
3113 r = kvm_vcpu_ioctl_smi(vcpu);
3114 break;
3115 }
3116 case KVM_SET_CPUID: {
3117 struct kvm_cpuid __user *cpuid_arg = argp;
3118 struct kvm_cpuid cpuid;
3119
3120 r = -EFAULT;
3121 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3122 goto out;
3123 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3124 break;
3125 }
3126 case KVM_SET_CPUID2: {
3127 struct kvm_cpuid2 __user *cpuid_arg = argp;
3128 struct kvm_cpuid2 cpuid;
3129
3130 r = -EFAULT;
3131 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3132 goto out;
3133 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3134 cpuid_arg->entries);
3135 break;
3136 }
3137 case KVM_GET_CPUID2: {
3138 struct kvm_cpuid2 __user *cpuid_arg = argp;
3139 struct kvm_cpuid2 cpuid;
3140
3141 r = -EFAULT;
3142 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 goto out;
3144 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3145 cpuid_arg->entries);
3146 if (r)
3147 goto out;
3148 r = -EFAULT;
3149 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3150 goto out;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_GET_MSRS:
3155 r = msr_io(vcpu, argp, do_get_msr, 1);
3156 break;
3157 case KVM_SET_MSRS:
3158 r = msr_io(vcpu, argp, do_set_msr, 0);
3159 break;
3160 case KVM_TPR_ACCESS_REPORTING: {
3161 struct kvm_tpr_access_ctl tac;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&tac, argp, sizeof tac))
3165 goto out;
3166 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3167 if (r)
3168 goto out;
3169 r = -EFAULT;
3170 if (copy_to_user(argp, &tac, sizeof tac))
3171 goto out;
3172 r = 0;
3173 break;
3174 };
3175 case KVM_SET_VAPIC_ADDR: {
3176 struct kvm_vapic_addr va;
3177
3178 r = -EINVAL;
3179 if (!irqchip_in_kernel(vcpu->kvm))
3180 goto out;
3181 r = -EFAULT;
3182 if (copy_from_user(&va, argp, sizeof va))
3183 goto out;
3184 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3185 break;
3186 }
3187 case KVM_X86_SETUP_MCE: {
3188 u64 mcg_cap;
3189
3190 r = -EFAULT;
3191 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3192 goto out;
3193 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3194 break;
3195 }
3196 case KVM_X86_SET_MCE: {
3197 struct kvm_x86_mce mce;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&mce, argp, sizeof mce))
3201 goto out;
3202 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3203 break;
3204 }
3205 case KVM_GET_VCPU_EVENTS: {
3206 struct kvm_vcpu_events events;
3207
3208 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3209
3210 r = -EFAULT;
3211 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3212 break;
3213 r = 0;
3214 break;
3215 }
3216 case KVM_SET_VCPU_EVENTS: {
3217 struct kvm_vcpu_events events;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3221 break;
3222
3223 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3224 break;
3225 }
3226 case KVM_GET_DEBUGREGS: {
3227 struct kvm_debugregs dbgregs;
3228
3229 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3230
3231 r = -EFAULT;
3232 if (copy_to_user(argp, &dbgregs,
3233 sizeof(struct kvm_debugregs)))
3234 break;
3235 r = 0;
3236 break;
3237 }
3238 case KVM_SET_DEBUGREGS: {
3239 struct kvm_debugregs dbgregs;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&dbgregs, argp,
3243 sizeof(struct kvm_debugregs)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3247 break;
3248 }
3249 case KVM_GET_XSAVE: {
3250 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3251 r = -ENOMEM;
3252 if (!u.xsave)
3253 break;
3254
3255 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3256
3257 r = -EFAULT;
3258 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3259 break;
3260 r = 0;
3261 break;
3262 }
3263 case KVM_SET_XSAVE: {
3264 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3265 if (IS_ERR(u.xsave))
3266 return PTR_ERR(u.xsave);
3267
3268 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3269 break;
3270 }
3271 case KVM_GET_XCRS: {
3272 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3273 r = -ENOMEM;
3274 if (!u.xcrs)
3275 break;
3276
3277 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3278
3279 r = -EFAULT;
3280 if (copy_to_user(argp, u.xcrs,
3281 sizeof(struct kvm_xcrs)))
3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XCRS: {
3287 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3288 if (IS_ERR(u.xcrs))
3289 return PTR_ERR(u.xcrs);
3290
3291 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3292 break;
3293 }
3294 case KVM_SET_TSC_KHZ: {
3295 u32 user_tsc_khz;
3296
3297 r = -EINVAL;
3298 user_tsc_khz = (u32)arg;
3299
3300 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3301 goto out;
3302
3303 if (user_tsc_khz == 0)
3304 user_tsc_khz = tsc_khz;
3305
3306 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3307
3308 r = 0;
3309 goto out;
3310 }
3311 case KVM_GET_TSC_KHZ: {
3312 r = vcpu->arch.virtual_tsc_khz;
3313 goto out;
3314 }
3315 case KVM_KVMCLOCK_CTRL: {
3316 r = kvm_set_guest_paused(vcpu);
3317 goto out;
3318 }
3319 default:
3320 r = -EINVAL;
3321 }
3322 out:
3323 kfree(u.buffer);
3324 return r;
3325 }
3326
3327 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3328 {
3329 return VM_FAULT_SIGBUS;
3330 }
3331
3332 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3333 {
3334 int ret;
3335
3336 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3337 return -EINVAL;
3338 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3339 return ret;
3340 }
3341
3342 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3343 u64 ident_addr)
3344 {
3345 kvm->arch.ept_identity_map_addr = ident_addr;
3346 return 0;
3347 }
3348
3349 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3350 u32 kvm_nr_mmu_pages)
3351 {
3352 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3353 return -EINVAL;
3354
3355 mutex_lock(&kvm->slots_lock);
3356
3357 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3358 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3359
3360 mutex_unlock(&kvm->slots_lock);
3361 return 0;
3362 }
3363
3364 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3365 {
3366 return kvm->arch.n_max_mmu_pages;
3367 }
3368
3369 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3370 {
3371 int r;
3372
3373 r = 0;
3374 switch (chip->chip_id) {
3375 case KVM_IRQCHIP_PIC_MASTER:
3376 memcpy(&chip->chip.pic,
3377 &pic_irqchip(kvm)->pics[0],
3378 sizeof(struct kvm_pic_state));
3379 break;
3380 case KVM_IRQCHIP_PIC_SLAVE:
3381 memcpy(&chip->chip.pic,
3382 &pic_irqchip(kvm)->pics[1],
3383 sizeof(struct kvm_pic_state));
3384 break;
3385 case KVM_IRQCHIP_IOAPIC:
3386 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3387 break;
3388 default:
3389 r = -EINVAL;
3390 break;
3391 }
3392 return r;
3393 }
3394
3395 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3396 {
3397 int r;
3398
3399 r = 0;
3400 switch (chip->chip_id) {
3401 case KVM_IRQCHIP_PIC_MASTER:
3402 spin_lock(&pic_irqchip(kvm)->lock);
3403 memcpy(&pic_irqchip(kvm)->pics[0],
3404 &chip->chip.pic,
3405 sizeof(struct kvm_pic_state));
3406 spin_unlock(&pic_irqchip(kvm)->lock);
3407 break;
3408 case KVM_IRQCHIP_PIC_SLAVE:
3409 spin_lock(&pic_irqchip(kvm)->lock);
3410 memcpy(&pic_irqchip(kvm)->pics[1],
3411 &chip->chip.pic,
3412 sizeof(struct kvm_pic_state));
3413 spin_unlock(&pic_irqchip(kvm)->lock);
3414 break;
3415 case KVM_IRQCHIP_IOAPIC:
3416 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3417 break;
3418 default:
3419 r = -EINVAL;
3420 break;
3421 }
3422 kvm_pic_update_irq(pic_irqchip(kvm));
3423 return r;
3424 }
3425
3426 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3427 {
3428 int r = 0;
3429
3430 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3431 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3432 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3433 return r;
3434 }
3435
3436 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3437 {
3438 int r = 0;
3439
3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3441 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3442 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3444 return r;
3445 }
3446
3447 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3448 {
3449 int r = 0;
3450
3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3452 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3453 sizeof(ps->channels));
3454 ps->flags = kvm->arch.vpit->pit_state.flags;
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3456 memset(&ps->reserved, 0, sizeof(ps->reserved));
3457 return r;
3458 }
3459
3460 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461 {
3462 int r = 0, start = 0;
3463 u32 prev_legacy, cur_legacy;
3464 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3465 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3466 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3467 if (!prev_legacy && cur_legacy)
3468 start = 1;
3469 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3470 sizeof(kvm->arch.vpit->pit_state.channels));
3471 kvm->arch.vpit->pit_state.flags = ps->flags;
3472 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3473 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3474 return r;
3475 }
3476
3477 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3478 struct kvm_reinject_control *control)
3479 {
3480 if (!kvm->arch.vpit)
3481 return -ENXIO;
3482 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3483 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3484 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3485 return 0;
3486 }
3487
3488 /**
3489 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3490 * @kvm: kvm instance
3491 * @log: slot id and address to which we copy the log
3492 *
3493 * Steps 1-4 below provide general overview of dirty page logging. See
3494 * kvm_get_dirty_log_protect() function description for additional details.
3495 *
3496 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3497 * always flush the TLB (step 4) even if previous step failed and the dirty
3498 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3499 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3500 * writes will be marked dirty for next log read.
3501 *
3502 * 1. Take a snapshot of the bit and clear it if needed.
3503 * 2. Write protect the corresponding page.
3504 * 3. Copy the snapshot to the userspace.
3505 * 4. Flush TLB's if needed.
3506 */
3507 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3508 {
3509 bool is_dirty = false;
3510 int r;
3511
3512 mutex_lock(&kvm->slots_lock);
3513
3514 /*
3515 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3516 */
3517 if (kvm_x86_ops->flush_log_dirty)
3518 kvm_x86_ops->flush_log_dirty(kvm);
3519
3520 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3521
3522 /*
3523 * All the TLBs can be flushed out of mmu lock, see the comments in
3524 * kvm_mmu_slot_remove_write_access().
3525 */
3526 lockdep_assert_held(&kvm->slots_lock);
3527 if (is_dirty)
3528 kvm_flush_remote_tlbs(kvm);
3529
3530 mutex_unlock(&kvm->slots_lock);
3531 return r;
3532 }
3533
3534 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3535 bool line_status)
3536 {
3537 if (!irqchip_in_kernel(kvm))
3538 return -ENXIO;
3539
3540 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3541 irq_event->irq, irq_event->level,
3542 line_status);
3543 return 0;
3544 }
3545
3546 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3547 struct kvm_enable_cap *cap)
3548 {
3549 int r;
3550
3551 if (cap->flags)
3552 return -EINVAL;
3553
3554 switch (cap->cap) {
3555 case KVM_CAP_DISABLE_QUIRKS:
3556 kvm->arch.disabled_quirks = cap->args[0];
3557 r = 0;
3558 break;
3559 default:
3560 r = -EINVAL;
3561 break;
3562 }
3563 return r;
3564 }
3565
3566 long kvm_arch_vm_ioctl(struct file *filp,
3567 unsigned int ioctl, unsigned long arg)
3568 {
3569 struct kvm *kvm = filp->private_data;
3570 void __user *argp = (void __user *)arg;
3571 int r = -ENOTTY;
3572 /*
3573 * This union makes it completely explicit to gcc-3.x
3574 * that these two variables' stack usage should be
3575 * combined, not added together.
3576 */
3577 union {
3578 struct kvm_pit_state ps;
3579 struct kvm_pit_state2 ps2;
3580 struct kvm_pit_config pit_config;
3581 } u;
3582
3583 switch (ioctl) {
3584 case KVM_SET_TSS_ADDR:
3585 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3586 break;
3587 case KVM_SET_IDENTITY_MAP_ADDR: {
3588 u64 ident_addr;
3589
3590 r = -EFAULT;
3591 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3592 goto out;
3593 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3594 break;
3595 }
3596 case KVM_SET_NR_MMU_PAGES:
3597 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3598 break;
3599 case KVM_GET_NR_MMU_PAGES:
3600 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3601 break;
3602 case KVM_CREATE_IRQCHIP: {
3603 struct kvm_pic *vpic;
3604
3605 mutex_lock(&kvm->lock);
3606 r = -EEXIST;
3607 if (kvm->arch.vpic)
3608 goto create_irqchip_unlock;
3609 r = -EINVAL;
3610 if (atomic_read(&kvm->online_vcpus))
3611 goto create_irqchip_unlock;
3612 r = -ENOMEM;
3613 vpic = kvm_create_pic(kvm);
3614 if (vpic) {
3615 r = kvm_ioapic_init(kvm);
3616 if (r) {
3617 mutex_lock(&kvm->slots_lock);
3618 kvm_destroy_pic(vpic);
3619 mutex_unlock(&kvm->slots_lock);
3620 goto create_irqchip_unlock;
3621 }
3622 } else
3623 goto create_irqchip_unlock;
3624 r = kvm_setup_default_irq_routing(kvm);
3625 if (r) {
3626 mutex_lock(&kvm->slots_lock);
3627 mutex_lock(&kvm->irq_lock);
3628 kvm_ioapic_destroy(kvm);
3629 kvm_destroy_pic(vpic);
3630 mutex_unlock(&kvm->irq_lock);
3631 mutex_unlock(&kvm->slots_lock);
3632 goto create_irqchip_unlock;
3633 }
3634 /* Write kvm->irq_routing before kvm->arch.vpic. */
3635 smp_wmb();
3636 kvm->arch.vpic = vpic;
3637 create_irqchip_unlock:
3638 mutex_unlock(&kvm->lock);
3639 break;
3640 }
3641 case KVM_CREATE_PIT:
3642 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3643 goto create_pit;
3644 case KVM_CREATE_PIT2:
3645 r = -EFAULT;
3646 if (copy_from_user(&u.pit_config, argp,
3647 sizeof(struct kvm_pit_config)))
3648 goto out;
3649 create_pit:
3650 mutex_lock(&kvm->slots_lock);
3651 r = -EEXIST;
3652 if (kvm->arch.vpit)
3653 goto create_pit_unlock;
3654 r = -ENOMEM;
3655 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3656 if (kvm->arch.vpit)
3657 r = 0;
3658 create_pit_unlock:
3659 mutex_unlock(&kvm->slots_lock);
3660 break;
3661 case KVM_GET_IRQCHIP: {
3662 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3663 struct kvm_irqchip *chip;
3664
3665 chip = memdup_user(argp, sizeof(*chip));
3666 if (IS_ERR(chip)) {
3667 r = PTR_ERR(chip);
3668 goto out;
3669 }
3670
3671 r = -ENXIO;
3672 if (!irqchip_in_kernel(kvm))
3673 goto get_irqchip_out;
3674 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3675 if (r)
3676 goto get_irqchip_out;
3677 r = -EFAULT;
3678 if (copy_to_user(argp, chip, sizeof *chip))
3679 goto get_irqchip_out;
3680 r = 0;
3681 get_irqchip_out:
3682 kfree(chip);
3683 break;
3684 }
3685 case KVM_SET_IRQCHIP: {
3686 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3687 struct kvm_irqchip *chip;
3688
3689 chip = memdup_user(argp, sizeof(*chip));
3690 if (IS_ERR(chip)) {
3691 r = PTR_ERR(chip);
3692 goto out;
3693 }
3694
3695 r = -ENXIO;
3696 if (!irqchip_in_kernel(kvm))
3697 goto set_irqchip_out;
3698 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3699 if (r)
3700 goto set_irqchip_out;
3701 r = 0;
3702 set_irqchip_out:
3703 kfree(chip);
3704 break;
3705 }
3706 case KVM_GET_PIT: {
3707 r = -EFAULT;
3708 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3709 goto out;
3710 r = -ENXIO;
3711 if (!kvm->arch.vpit)
3712 goto out;
3713 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3714 if (r)
3715 goto out;
3716 r = -EFAULT;
3717 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3718 goto out;
3719 r = 0;
3720 break;
3721 }
3722 case KVM_SET_PIT: {
3723 r = -EFAULT;
3724 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3725 goto out;
3726 r = -ENXIO;
3727 if (!kvm->arch.vpit)
3728 goto out;
3729 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3730 break;
3731 }
3732 case KVM_GET_PIT2: {
3733 r = -ENXIO;
3734 if (!kvm->arch.vpit)
3735 goto out;
3736 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3737 if (r)
3738 goto out;
3739 r = -EFAULT;
3740 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3741 goto out;
3742 r = 0;
3743 break;
3744 }
3745 case KVM_SET_PIT2: {
3746 r = -EFAULT;
3747 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3748 goto out;
3749 r = -ENXIO;
3750 if (!kvm->arch.vpit)
3751 goto out;
3752 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3753 break;
3754 }
3755 case KVM_REINJECT_CONTROL: {
3756 struct kvm_reinject_control control;
3757 r = -EFAULT;
3758 if (copy_from_user(&control, argp, sizeof(control)))
3759 goto out;
3760 r = kvm_vm_ioctl_reinject(kvm, &control);
3761 break;
3762 }
3763 case KVM_SET_BOOT_CPU_ID:
3764 r = 0;
3765 mutex_lock(&kvm->lock);
3766 if (atomic_read(&kvm->online_vcpus) != 0)
3767 r = -EBUSY;
3768 else
3769 kvm->arch.bsp_vcpu_id = arg;
3770 mutex_unlock(&kvm->lock);
3771 break;
3772 case KVM_XEN_HVM_CONFIG: {
3773 r = -EFAULT;
3774 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3775 sizeof(struct kvm_xen_hvm_config)))
3776 goto out;
3777 r = -EINVAL;
3778 if (kvm->arch.xen_hvm_config.flags)
3779 goto out;
3780 r = 0;
3781 break;
3782 }
3783 case KVM_SET_CLOCK: {
3784 struct kvm_clock_data user_ns;
3785 u64 now_ns;
3786 s64 delta;
3787
3788 r = -EFAULT;
3789 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3790 goto out;
3791
3792 r = -EINVAL;
3793 if (user_ns.flags)
3794 goto out;
3795
3796 r = 0;
3797 local_irq_disable();
3798 now_ns = get_kernel_ns();
3799 delta = user_ns.clock - now_ns;
3800 local_irq_enable();
3801 kvm->arch.kvmclock_offset = delta;
3802 kvm_gen_update_masterclock(kvm);
3803 break;
3804 }
3805 case KVM_GET_CLOCK: {
3806 struct kvm_clock_data user_ns;
3807 u64 now_ns;
3808
3809 local_irq_disable();
3810 now_ns = get_kernel_ns();
3811 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3812 local_irq_enable();
3813 user_ns.flags = 0;
3814 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3815
3816 r = -EFAULT;
3817 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3818 goto out;
3819 r = 0;
3820 break;
3821 }
3822 case KVM_ENABLE_CAP: {
3823 struct kvm_enable_cap cap;
3824
3825 r = -EFAULT;
3826 if (copy_from_user(&cap, argp, sizeof(cap)))
3827 goto out;
3828 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3829 break;
3830 }
3831 default:
3832 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3833 }
3834 out:
3835 return r;
3836 }
3837
3838 static void kvm_init_msr_list(void)
3839 {
3840 u32 dummy[2];
3841 unsigned i, j;
3842
3843 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3844 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3845 continue;
3846
3847 /*
3848 * Even MSRs that are valid in the host may not be exposed
3849 * to the guests in some cases. We could work around this
3850 * in VMX with the generic MSR save/load machinery, but it
3851 * is not really worthwhile since it will really only
3852 * happen with nested virtualization.
3853 */
3854 switch (msrs_to_save[i]) {
3855 case MSR_IA32_BNDCFGS:
3856 if (!kvm_x86_ops->mpx_supported())
3857 continue;
3858 break;
3859 default:
3860 break;
3861 }
3862
3863 if (j < i)
3864 msrs_to_save[j] = msrs_to_save[i];
3865 j++;
3866 }
3867 num_msrs_to_save = j;
3868
3869 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3870 switch (emulated_msrs[i]) {
3871 case MSR_IA32_SMBASE:
3872 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3873 continue;
3874 break;
3875 default:
3876 break;
3877 }
3878
3879 if (j < i)
3880 emulated_msrs[j] = emulated_msrs[i];
3881 j++;
3882 }
3883 num_emulated_msrs = j;
3884 }
3885
3886 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3887 const void *v)
3888 {
3889 int handled = 0;
3890 int n;
3891
3892 do {
3893 n = min(len, 8);
3894 if (!(vcpu->arch.apic &&
3895 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3896 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3897 break;
3898 handled += n;
3899 addr += n;
3900 len -= n;
3901 v += n;
3902 } while (len);
3903
3904 return handled;
3905 }
3906
3907 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3908 {
3909 int handled = 0;
3910 int n;
3911
3912 do {
3913 n = min(len, 8);
3914 if (!(vcpu->arch.apic &&
3915 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3916 addr, n, v))
3917 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3918 break;
3919 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3920 handled += n;
3921 addr += n;
3922 len -= n;
3923 v += n;
3924 } while (len);
3925
3926 return handled;
3927 }
3928
3929 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3930 struct kvm_segment *var, int seg)
3931 {
3932 kvm_x86_ops->set_segment(vcpu, var, seg);
3933 }
3934
3935 void kvm_get_segment(struct kvm_vcpu *vcpu,
3936 struct kvm_segment *var, int seg)
3937 {
3938 kvm_x86_ops->get_segment(vcpu, var, seg);
3939 }
3940
3941 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3942 struct x86_exception *exception)
3943 {
3944 gpa_t t_gpa;
3945
3946 BUG_ON(!mmu_is_nested(vcpu));
3947
3948 /* NPT walks are always user-walks */
3949 access |= PFERR_USER_MASK;
3950 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3951
3952 return t_gpa;
3953 }
3954
3955 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3956 struct x86_exception *exception)
3957 {
3958 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3959 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3960 }
3961
3962 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3963 struct x86_exception *exception)
3964 {
3965 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3966 access |= PFERR_FETCH_MASK;
3967 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3968 }
3969
3970 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3971 struct x86_exception *exception)
3972 {
3973 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3974 access |= PFERR_WRITE_MASK;
3975 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3976 }
3977
3978 /* uses this to access any guest's mapped memory without checking CPL */
3979 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3980 struct x86_exception *exception)
3981 {
3982 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3983 }
3984
3985 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3986 struct kvm_vcpu *vcpu, u32 access,
3987 struct x86_exception *exception)
3988 {
3989 void *data = val;
3990 int r = X86EMUL_CONTINUE;
3991
3992 while (bytes) {
3993 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3994 exception);
3995 unsigned offset = addr & (PAGE_SIZE-1);
3996 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3997 int ret;
3998
3999 if (gpa == UNMAPPED_GVA)
4000 return X86EMUL_PROPAGATE_FAULT;
4001 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4002 offset, toread);
4003 if (ret < 0) {
4004 r = X86EMUL_IO_NEEDED;
4005 goto out;
4006 }
4007
4008 bytes -= toread;
4009 data += toread;
4010 addr += toread;
4011 }
4012 out:
4013 return r;
4014 }
4015
4016 /* used for instruction fetching */
4017 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4018 gva_t addr, void *val, unsigned int bytes,
4019 struct x86_exception *exception)
4020 {
4021 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4022 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4023 unsigned offset;
4024 int ret;
4025
4026 /* Inline kvm_read_guest_virt_helper for speed. */
4027 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4028 exception);
4029 if (unlikely(gpa == UNMAPPED_GVA))
4030 return X86EMUL_PROPAGATE_FAULT;
4031
4032 offset = addr & (PAGE_SIZE-1);
4033 if (WARN_ON(offset + bytes > PAGE_SIZE))
4034 bytes = (unsigned)PAGE_SIZE - offset;
4035 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4036 offset, bytes);
4037 if (unlikely(ret < 0))
4038 return X86EMUL_IO_NEEDED;
4039
4040 return X86EMUL_CONTINUE;
4041 }
4042
4043 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4044 gva_t addr, void *val, unsigned int bytes,
4045 struct x86_exception *exception)
4046 {
4047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4049
4050 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4051 exception);
4052 }
4053 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4054
4055 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4056 gva_t addr, void *val, unsigned int bytes,
4057 struct x86_exception *exception)
4058 {
4059 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4060 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4061 }
4062
4063 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4064 gva_t addr, void *val,
4065 unsigned int bytes,
4066 struct x86_exception *exception)
4067 {
4068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4069 void *data = val;
4070 int r = X86EMUL_CONTINUE;
4071
4072 while (bytes) {
4073 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4074 PFERR_WRITE_MASK,
4075 exception);
4076 unsigned offset = addr & (PAGE_SIZE-1);
4077 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4078 int ret;
4079
4080 if (gpa == UNMAPPED_GVA)
4081 return X86EMUL_PROPAGATE_FAULT;
4082 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4083 if (ret < 0) {
4084 r = X86EMUL_IO_NEEDED;
4085 goto out;
4086 }
4087
4088 bytes -= towrite;
4089 data += towrite;
4090 addr += towrite;
4091 }
4092 out:
4093 return r;
4094 }
4095 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4096
4097 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4098 gpa_t *gpa, struct x86_exception *exception,
4099 bool write)
4100 {
4101 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4102 | (write ? PFERR_WRITE_MASK : 0);
4103
4104 if (vcpu_match_mmio_gva(vcpu, gva)
4105 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4106 vcpu->arch.access, access)) {
4107 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4108 (gva & (PAGE_SIZE - 1));
4109 trace_vcpu_match_mmio(gva, *gpa, write, false);
4110 return 1;
4111 }
4112
4113 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4114
4115 if (*gpa == UNMAPPED_GVA)
4116 return -1;
4117
4118 /* For APIC access vmexit */
4119 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4120 return 1;
4121
4122 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4123 trace_vcpu_match_mmio(gva, *gpa, write, true);
4124 return 1;
4125 }
4126
4127 return 0;
4128 }
4129
4130 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4131 const void *val, int bytes)
4132 {
4133 int ret;
4134
4135 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4136 if (ret < 0)
4137 return 0;
4138 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4139 return 1;
4140 }
4141
4142 struct read_write_emulator_ops {
4143 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4144 int bytes);
4145 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4146 void *val, int bytes);
4147 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4148 int bytes, void *val);
4149 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4150 void *val, int bytes);
4151 bool write;
4152 };
4153
4154 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4155 {
4156 if (vcpu->mmio_read_completed) {
4157 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4158 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4159 vcpu->mmio_read_completed = 0;
4160 return 1;
4161 }
4162
4163 return 0;
4164 }
4165
4166 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4167 void *val, int bytes)
4168 {
4169 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4170 }
4171
4172 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4173 void *val, int bytes)
4174 {
4175 return emulator_write_phys(vcpu, gpa, val, bytes);
4176 }
4177
4178 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4179 {
4180 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4181 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4182 }
4183
4184 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4185 void *val, int bytes)
4186 {
4187 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4188 return X86EMUL_IO_NEEDED;
4189 }
4190
4191 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4192 void *val, int bytes)
4193 {
4194 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4195
4196 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4197 return X86EMUL_CONTINUE;
4198 }
4199
4200 static const struct read_write_emulator_ops read_emultor = {
4201 .read_write_prepare = read_prepare,
4202 .read_write_emulate = read_emulate,
4203 .read_write_mmio = vcpu_mmio_read,
4204 .read_write_exit_mmio = read_exit_mmio,
4205 };
4206
4207 static const struct read_write_emulator_ops write_emultor = {
4208 .read_write_emulate = write_emulate,
4209 .read_write_mmio = write_mmio,
4210 .read_write_exit_mmio = write_exit_mmio,
4211 .write = true,
4212 };
4213
4214 static int emulator_read_write_onepage(unsigned long addr, void *val,
4215 unsigned int bytes,
4216 struct x86_exception *exception,
4217 struct kvm_vcpu *vcpu,
4218 const struct read_write_emulator_ops *ops)
4219 {
4220 gpa_t gpa;
4221 int handled, ret;
4222 bool write = ops->write;
4223 struct kvm_mmio_fragment *frag;
4224
4225 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4226
4227 if (ret < 0)
4228 return X86EMUL_PROPAGATE_FAULT;
4229
4230 /* For APIC access vmexit */
4231 if (ret)
4232 goto mmio;
4233
4234 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4235 return X86EMUL_CONTINUE;
4236
4237 mmio:
4238 /*
4239 * Is this MMIO handled locally?
4240 */
4241 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4242 if (handled == bytes)
4243 return X86EMUL_CONTINUE;
4244
4245 gpa += handled;
4246 bytes -= handled;
4247 val += handled;
4248
4249 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4250 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4251 frag->gpa = gpa;
4252 frag->data = val;
4253 frag->len = bytes;
4254 return X86EMUL_CONTINUE;
4255 }
4256
4257 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4258 unsigned long addr,
4259 void *val, unsigned int bytes,
4260 struct x86_exception *exception,
4261 const struct read_write_emulator_ops *ops)
4262 {
4263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4264 gpa_t gpa;
4265 int rc;
4266
4267 if (ops->read_write_prepare &&
4268 ops->read_write_prepare(vcpu, val, bytes))
4269 return X86EMUL_CONTINUE;
4270
4271 vcpu->mmio_nr_fragments = 0;
4272
4273 /* Crossing a page boundary? */
4274 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4275 int now;
4276
4277 now = -addr & ~PAGE_MASK;
4278 rc = emulator_read_write_onepage(addr, val, now, exception,
4279 vcpu, ops);
4280
4281 if (rc != X86EMUL_CONTINUE)
4282 return rc;
4283 addr += now;
4284 if (ctxt->mode != X86EMUL_MODE_PROT64)
4285 addr = (u32)addr;
4286 val += now;
4287 bytes -= now;
4288 }
4289
4290 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4291 vcpu, ops);
4292 if (rc != X86EMUL_CONTINUE)
4293 return rc;
4294
4295 if (!vcpu->mmio_nr_fragments)
4296 return rc;
4297
4298 gpa = vcpu->mmio_fragments[0].gpa;
4299
4300 vcpu->mmio_needed = 1;
4301 vcpu->mmio_cur_fragment = 0;
4302
4303 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4304 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4305 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4306 vcpu->run->mmio.phys_addr = gpa;
4307
4308 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4309 }
4310
4311 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4312 unsigned long addr,
4313 void *val,
4314 unsigned int bytes,
4315 struct x86_exception *exception)
4316 {
4317 return emulator_read_write(ctxt, addr, val, bytes,
4318 exception, &read_emultor);
4319 }
4320
4321 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4322 unsigned long addr,
4323 const void *val,
4324 unsigned int bytes,
4325 struct x86_exception *exception)
4326 {
4327 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4328 exception, &write_emultor);
4329 }
4330
4331 #define CMPXCHG_TYPE(t, ptr, old, new) \
4332 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4333
4334 #ifdef CONFIG_X86_64
4335 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4336 #else
4337 # define CMPXCHG64(ptr, old, new) \
4338 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4339 #endif
4340
4341 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4342 unsigned long addr,
4343 const void *old,
4344 const void *new,
4345 unsigned int bytes,
4346 struct x86_exception *exception)
4347 {
4348 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4349 gpa_t gpa;
4350 struct page *page;
4351 char *kaddr;
4352 bool exchanged;
4353
4354 /* guests cmpxchg8b have to be emulated atomically */
4355 if (bytes > 8 || (bytes & (bytes - 1)))
4356 goto emul_write;
4357
4358 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4359
4360 if (gpa == UNMAPPED_GVA ||
4361 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4362 goto emul_write;
4363
4364 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4365 goto emul_write;
4366
4367 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4368 if (is_error_page(page))
4369 goto emul_write;
4370
4371 kaddr = kmap_atomic(page);
4372 kaddr += offset_in_page(gpa);
4373 switch (bytes) {
4374 case 1:
4375 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4376 break;
4377 case 2:
4378 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4379 break;
4380 case 4:
4381 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4382 break;
4383 case 8:
4384 exchanged = CMPXCHG64(kaddr, old, new);
4385 break;
4386 default:
4387 BUG();
4388 }
4389 kunmap_atomic(kaddr);
4390 kvm_release_page_dirty(page);
4391
4392 if (!exchanged)
4393 return X86EMUL_CMPXCHG_FAILED;
4394
4395 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4396 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4397
4398 return X86EMUL_CONTINUE;
4399
4400 emul_write:
4401 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4402
4403 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4404 }
4405
4406 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4407 {
4408 /* TODO: String I/O for in kernel device */
4409 int r;
4410
4411 if (vcpu->arch.pio.in)
4412 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4413 vcpu->arch.pio.size, pd);
4414 else
4415 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4416 vcpu->arch.pio.port, vcpu->arch.pio.size,
4417 pd);
4418 return r;
4419 }
4420
4421 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4422 unsigned short port, void *val,
4423 unsigned int count, bool in)
4424 {
4425 vcpu->arch.pio.port = port;
4426 vcpu->arch.pio.in = in;
4427 vcpu->arch.pio.count = count;
4428 vcpu->arch.pio.size = size;
4429
4430 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4431 vcpu->arch.pio.count = 0;
4432 return 1;
4433 }
4434
4435 vcpu->run->exit_reason = KVM_EXIT_IO;
4436 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4437 vcpu->run->io.size = size;
4438 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4439 vcpu->run->io.count = count;
4440 vcpu->run->io.port = port;
4441
4442 return 0;
4443 }
4444
4445 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4446 int size, unsigned short port, void *val,
4447 unsigned int count)
4448 {
4449 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4450 int ret;
4451
4452 if (vcpu->arch.pio.count)
4453 goto data_avail;
4454
4455 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4456 if (ret) {
4457 data_avail:
4458 memcpy(val, vcpu->arch.pio_data, size * count);
4459 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4460 vcpu->arch.pio.count = 0;
4461 return 1;
4462 }
4463
4464 return 0;
4465 }
4466
4467 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4468 int size, unsigned short port,
4469 const void *val, unsigned int count)
4470 {
4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4472
4473 memcpy(vcpu->arch.pio_data, val, size * count);
4474 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4475 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4476 }
4477
4478 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4479 {
4480 return kvm_x86_ops->get_segment_base(vcpu, seg);
4481 }
4482
4483 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4484 {
4485 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4486 }
4487
4488 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4489 {
4490 if (!need_emulate_wbinvd(vcpu))
4491 return X86EMUL_CONTINUE;
4492
4493 if (kvm_x86_ops->has_wbinvd_exit()) {
4494 int cpu = get_cpu();
4495
4496 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4497 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4498 wbinvd_ipi, NULL, 1);
4499 put_cpu();
4500 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4501 } else
4502 wbinvd();
4503 return X86EMUL_CONTINUE;
4504 }
4505
4506 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4507 {
4508 kvm_x86_ops->skip_emulated_instruction(vcpu);
4509 return kvm_emulate_wbinvd_noskip(vcpu);
4510 }
4511 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4512
4513
4514
4515 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4516 {
4517 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4518 }
4519
4520 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4521 unsigned long *dest)
4522 {
4523 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4524 }
4525
4526 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4527 unsigned long value)
4528 {
4529
4530 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4531 }
4532
4533 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4534 {
4535 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4536 }
4537
4538 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4539 {
4540 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4541 unsigned long value;
4542
4543 switch (cr) {
4544 case 0:
4545 value = kvm_read_cr0(vcpu);
4546 break;
4547 case 2:
4548 value = vcpu->arch.cr2;
4549 break;
4550 case 3:
4551 value = kvm_read_cr3(vcpu);
4552 break;
4553 case 4:
4554 value = kvm_read_cr4(vcpu);
4555 break;
4556 case 8:
4557 value = kvm_get_cr8(vcpu);
4558 break;
4559 default:
4560 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4561 return 0;
4562 }
4563
4564 return value;
4565 }
4566
4567 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4568 {
4569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4570 int res = 0;
4571
4572 switch (cr) {
4573 case 0:
4574 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4575 break;
4576 case 2:
4577 vcpu->arch.cr2 = val;
4578 break;
4579 case 3:
4580 res = kvm_set_cr3(vcpu, val);
4581 break;
4582 case 4:
4583 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4584 break;
4585 case 8:
4586 res = kvm_set_cr8(vcpu, val);
4587 break;
4588 default:
4589 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4590 res = -1;
4591 }
4592
4593 return res;
4594 }
4595
4596 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4597 {
4598 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4599 }
4600
4601 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4602 {
4603 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4604 }
4605
4606 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4607 {
4608 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4609 }
4610
4611 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4612 {
4613 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4614 }
4615
4616 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4617 {
4618 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4619 }
4620
4621 static unsigned long emulator_get_cached_segment_base(
4622 struct x86_emulate_ctxt *ctxt, int seg)
4623 {
4624 return get_segment_base(emul_to_vcpu(ctxt), seg);
4625 }
4626
4627 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4628 struct desc_struct *desc, u32 *base3,
4629 int seg)
4630 {
4631 struct kvm_segment var;
4632
4633 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4634 *selector = var.selector;
4635
4636 if (var.unusable) {
4637 memset(desc, 0, sizeof(*desc));
4638 return false;
4639 }
4640
4641 if (var.g)
4642 var.limit >>= 12;
4643 set_desc_limit(desc, var.limit);
4644 set_desc_base(desc, (unsigned long)var.base);
4645 #ifdef CONFIG_X86_64
4646 if (base3)
4647 *base3 = var.base >> 32;
4648 #endif
4649 desc->type = var.type;
4650 desc->s = var.s;
4651 desc->dpl = var.dpl;
4652 desc->p = var.present;
4653 desc->avl = var.avl;
4654 desc->l = var.l;
4655 desc->d = var.db;
4656 desc->g = var.g;
4657
4658 return true;
4659 }
4660
4661 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4662 struct desc_struct *desc, u32 base3,
4663 int seg)
4664 {
4665 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4666 struct kvm_segment var;
4667
4668 var.selector = selector;
4669 var.base = get_desc_base(desc);
4670 #ifdef CONFIG_X86_64
4671 var.base |= ((u64)base3) << 32;
4672 #endif
4673 var.limit = get_desc_limit(desc);
4674 if (desc->g)
4675 var.limit = (var.limit << 12) | 0xfff;
4676 var.type = desc->type;
4677 var.dpl = desc->dpl;
4678 var.db = desc->d;
4679 var.s = desc->s;
4680 var.l = desc->l;
4681 var.g = desc->g;
4682 var.avl = desc->avl;
4683 var.present = desc->p;
4684 var.unusable = !var.present;
4685 var.padding = 0;
4686
4687 kvm_set_segment(vcpu, &var, seg);
4688 return;
4689 }
4690
4691 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4692 u32 msr_index, u64 *pdata)
4693 {
4694 struct msr_data msr;
4695 int r;
4696
4697 msr.index = msr_index;
4698 msr.host_initiated = false;
4699 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4700 if (r)
4701 return r;
4702
4703 *pdata = msr.data;
4704 return 0;
4705 }
4706
4707 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4708 u32 msr_index, u64 data)
4709 {
4710 struct msr_data msr;
4711
4712 msr.data = data;
4713 msr.index = msr_index;
4714 msr.host_initiated = false;
4715 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4716 }
4717
4718 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4719 {
4720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4721
4722 return vcpu->arch.smbase;
4723 }
4724
4725 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4726 {
4727 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4728
4729 vcpu->arch.smbase = smbase;
4730 }
4731
4732 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4733 u32 pmc)
4734 {
4735 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4736 }
4737
4738 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4739 u32 pmc, u64 *pdata)
4740 {
4741 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4742 }
4743
4744 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4745 {
4746 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4747 }
4748
4749 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4750 {
4751 preempt_disable();
4752 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4753 /*
4754 * CR0.TS may reference the host fpu state, not the guest fpu state,
4755 * so it may be clear at this point.
4756 */
4757 clts();
4758 }
4759
4760 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4761 {
4762 preempt_enable();
4763 }
4764
4765 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4766 struct x86_instruction_info *info,
4767 enum x86_intercept_stage stage)
4768 {
4769 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4770 }
4771
4772 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4773 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4774 {
4775 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4776 }
4777
4778 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4779 {
4780 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4781 }
4782
4783 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4784 {
4785 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4786 }
4787
4788 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4789 {
4790 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4791 }
4792
4793 static const struct x86_emulate_ops emulate_ops = {
4794 .read_gpr = emulator_read_gpr,
4795 .write_gpr = emulator_write_gpr,
4796 .read_std = kvm_read_guest_virt_system,
4797 .write_std = kvm_write_guest_virt_system,
4798 .fetch = kvm_fetch_guest_virt,
4799 .read_emulated = emulator_read_emulated,
4800 .write_emulated = emulator_write_emulated,
4801 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4802 .invlpg = emulator_invlpg,
4803 .pio_in_emulated = emulator_pio_in_emulated,
4804 .pio_out_emulated = emulator_pio_out_emulated,
4805 .get_segment = emulator_get_segment,
4806 .set_segment = emulator_set_segment,
4807 .get_cached_segment_base = emulator_get_cached_segment_base,
4808 .get_gdt = emulator_get_gdt,
4809 .get_idt = emulator_get_idt,
4810 .set_gdt = emulator_set_gdt,
4811 .set_idt = emulator_set_idt,
4812 .get_cr = emulator_get_cr,
4813 .set_cr = emulator_set_cr,
4814 .cpl = emulator_get_cpl,
4815 .get_dr = emulator_get_dr,
4816 .set_dr = emulator_set_dr,
4817 .get_smbase = emulator_get_smbase,
4818 .set_smbase = emulator_set_smbase,
4819 .set_msr = emulator_set_msr,
4820 .get_msr = emulator_get_msr,
4821 .check_pmc = emulator_check_pmc,
4822 .read_pmc = emulator_read_pmc,
4823 .halt = emulator_halt,
4824 .wbinvd = emulator_wbinvd,
4825 .fix_hypercall = emulator_fix_hypercall,
4826 .get_fpu = emulator_get_fpu,
4827 .put_fpu = emulator_put_fpu,
4828 .intercept = emulator_intercept,
4829 .get_cpuid = emulator_get_cpuid,
4830 .set_nmi_mask = emulator_set_nmi_mask,
4831 };
4832
4833 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4834 {
4835 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4836 /*
4837 * an sti; sti; sequence only disable interrupts for the first
4838 * instruction. So, if the last instruction, be it emulated or
4839 * not, left the system with the INT_STI flag enabled, it
4840 * means that the last instruction is an sti. We should not
4841 * leave the flag on in this case. The same goes for mov ss
4842 */
4843 if (int_shadow & mask)
4844 mask = 0;
4845 if (unlikely(int_shadow || mask)) {
4846 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4847 if (!mask)
4848 kvm_make_request(KVM_REQ_EVENT, vcpu);
4849 }
4850 }
4851
4852 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4853 {
4854 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4855 if (ctxt->exception.vector == PF_VECTOR)
4856 return kvm_propagate_fault(vcpu, &ctxt->exception);
4857
4858 if (ctxt->exception.error_code_valid)
4859 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4860 ctxt->exception.error_code);
4861 else
4862 kvm_queue_exception(vcpu, ctxt->exception.vector);
4863 return false;
4864 }
4865
4866 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4867 {
4868 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4869 int cs_db, cs_l;
4870
4871 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4872
4873 ctxt->eflags = kvm_get_rflags(vcpu);
4874 ctxt->eip = kvm_rip_read(vcpu);
4875 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4876 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4877 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4878 cs_db ? X86EMUL_MODE_PROT32 :
4879 X86EMUL_MODE_PROT16;
4880 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4881 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4882 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4883 ctxt->emul_flags = vcpu->arch.hflags;
4884
4885 init_decode_cache(ctxt);
4886 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4887 }
4888
4889 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4890 {
4891 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4892 int ret;
4893
4894 init_emulate_ctxt(vcpu);
4895
4896 ctxt->op_bytes = 2;
4897 ctxt->ad_bytes = 2;
4898 ctxt->_eip = ctxt->eip + inc_eip;
4899 ret = emulate_int_real(ctxt, irq);
4900
4901 if (ret != X86EMUL_CONTINUE)
4902 return EMULATE_FAIL;
4903
4904 ctxt->eip = ctxt->_eip;
4905 kvm_rip_write(vcpu, ctxt->eip);
4906 kvm_set_rflags(vcpu, ctxt->eflags);
4907
4908 if (irq == NMI_VECTOR)
4909 vcpu->arch.nmi_pending = 0;
4910 else
4911 vcpu->arch.interrupt.pending = false;
4912
4913 return EMULATE_DONE;
4914 }
4915 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4916
4917 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4918 {
4919 int r = EMULATE_DONE;
4920
4921 ++vcpu->stat.insn_emulation_fail;
4922 trace_kvm_emulate_insn_failed(vcpu);
4923 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4924 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4925 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4926 vcpu->run->internal.ndata = 0;
4927 r = EMULATE_FAIL;
4928 }
4929 kvm_queue_exception(vcpu, UD_VECTOR);
4930
4931 return r;
4932 }
4933
4934 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4935 bool write_fault_to_shadow_pgtable,
4936 int emulation_type)
4937 {
4938 gpa_t gpa = cr2;
4939 pfn_t pfn;
4940
4941 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4942 return false;
4943
4944 if (!vcpu->arch.mmu.direct_map) {
4945 /*
4946 * Write permission should be allowed since only
4947 * write access need to be emulated.
4948 */
4949 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4950
4951 /*
4952 * If the mapping is invalid in guest, let cpu retry
4953 * it to generate fault.
4954 */
4955 if (gpa == UNMAPPED_GVA)
4956 return true;
4957 }
4958
4959 /*
4960 * Do not retry the unhandleable instruction if it faults on the
4961 * readonly host memory, otherwise it will goto a infinite loop:
4962 * retry instruction -> write #PF -> emulation fail -> retry
4963 * instruction -> ...
4964 */
4965 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4966
4967 /*
4968 * If the instruction failed on the error pfn, it can not be fixed,
4969 * report the error to userspace.
4970 */
4971 if (is_error_noslot_pfn(pfn))
4972 return false;
4973
4974 kvm_release_pfn_clean(pfn);
4975
4976 /* The instructions are well-emulated on direct mmu. */
4977 if (vcpu->arch.mmu.direct_map) {
4978 unsigned int indirect_shadow_pages;
4979
4980 spin_lock(&vcpu->kvm->mmu_lock);
4981 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4982 spin_unlock(&vcpu->kvm->mmu_lock);
4983
4984 if (indirect_shadow_pages)
4985 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4986
4987 return true;
4988 }
4989
4990 /*
4991 * if emulation was due to access to shadowed page table
4992 * and it failed try to unshadow page and re-enter the
4993 * guest to let CPU execute the instruction.
4994 */
4995 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4996
4997 /*
4998 * If the access faults on its page table, it can not
4999 * be fixed by unprotecting shadow page and it should
5000 * be reported to userspace.
5001 */
5002 return !write_fault_to_shadow_pgtable;
5003 }
5004
5005 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5006 unsigned long cr2, int emulation_type)
5007 {
5008 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5009 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5010
5011 last_retry_eip = vcpu->arch.last_retry_eip;
5012 last_retry_addr = vcpu->arch.last_retry_addr;
5013
5014 /*
5015 * If the emulation is caused by #PF and it is non-page_table
5016 * writing instruction, it means the VM-EXIT is caused by shadow
5017 * page protected, we can zap the shadow page and retry this
5018 * instruction directly.
5019 *
5020 * Note: if the guest uses a non-page-table modifying instruction
5021 * on the PDE that points to the instruction, then we will unmap
5022 * the instruction and go to an infinite loop. So, we cache the
5023 * last retried eip and the last fault address, if we meet the eip
5024 * and the address again, we can break out of the potential infinite
5025 * loop.
5026 */
5027 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5028
5029 if (!(emulation_type & EMULTYPE_RETRY))
5030 return false;
5031
5032 if (x86_page_table_writing_insn(ctxt))
5033 return false;
5034
5035 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5036 return false;
5037
5038 vcpu->arch.last_retry_eip = ctxt->eip;
5039 vcpu->arch.last_retry_addr = cr2;
5040
5041 if (!vcpu->arch.mmu.direct_map)
5042 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5043
5044 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5045
5046 return true;
5047 }
5048
5049 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5050 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5051
5052 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5053 {
5054 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5055 /* This is a good place to trace that we are exiting SMM. */
5056 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5057
5058 if (unlikely(vcpu->arch.smi_pending)) {
5059 kvm_make_request(KVM_REQ_SMI, vcpu);
5060 vcpu->arch.smi_pending = 0;
5061 } else {
5062 /* Process a latched INIT, if any. */
5063 kvm_make_request(KVM_REQ_EVENT, vcpu);
5064 }
5065 }
5066
5067 kvm_mmu_reset_context(vcpu);
5068 }
5069
5070 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5071 {
5072 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5073
5074 vcpu->arch.hflags = emul_flags;
5075
5076 if (changed & HF_SMM_MASK)
5077 kvm_smm_changed(vcpu);
5078 }
5079
5080 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5081 unsigned long *db)
5082 {
5083 u32 dr6 = 0;
5084 int i;
5085 u32 enable, rwlen;
5086
5087 enable = dr7;
5088 rwlen = dr7 >> 16;
5089 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5090 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5091 dr6 |= (1 << i);
5092 return dr6;
5093 }
5094
5095 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5096 {
5097 struct kvm_run *kvm_run = vcpu->run;
5098
5099 /*
5100 * rflags is the old, "raw" value of the flags. The new value has
5101 * not been saved yet.
5102 *
5103 * This is correct even for TF set by the guest, because "the
5104 * processor will not generate this exception after the instruction
5105 * that sets the TF flag".
5106 */
5107 if (unlikely(rflags & X86_EFLAGS_TF)) {
5108 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5109 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5110 DR6_RTM;
5111 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5112 kvm_run->debug.arch.exception = DB_VECTOR;
5113 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5114 *r = EMULATE_USER_EXIT;
5115 } else {
5116 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5117 /*
5118 * "Certain debug exceptions may clear bit 0-3. The
5119 * remaining contents of the DR6 register are never
5120 * cleared by the processor".
5121 */
5122 vcpu->arch.dr6 &= ~15;
5123 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5124 kvm_queue_exception(vcpu, DB_VECTOR);
5125 }
5126 }
5127 }
5128
5129 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5130 {
5131 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5132 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5133 struct kvm_run *kvm_run = vcpu->run;
5134 unsigned long eip = kvm_get_linear_rip(vcpu);
5135 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5136 vcpu->arch.guest_debug_dr7,
5137 vcpu->arch.eff_db);
5138
5139 if (dr6 != 0) {
5140 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5141 kvm_run->debug.arch.pc = eip;
5142 kvm_run->debug.arch.exception = DB_VECTOR;
5143 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5144 *r = EMULATE_USER_EXIT;
5145 return true;
5146 }
5147 }
5148
5149 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5150 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5151 unsigned long eip = kvm_get_linear_rip(vcpu);
5152 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5153 vcpu->arch.dr7,
5154 vcpu->arch.db);
5155
5156 if (dr6 != 0) {
5157 vcpu->arch.dr6 &= ~15;
5158 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5159 kvm_queue_exception(vcpu, DB_VECTOR);
5160 *r = EMULATE_DONE;
5161 return true;
5162 }
5163 }
5164
5165 return false;
5166 }
5167
5168 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5169 unsigned long cr2,
5170 int emulation_type,
5171 void *insn,
5172 int insn_len)
5173 {
5174 int r;
5175 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5176 bool writeback = true;
5177 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5178
5179 /*
5180 * Clear write_fault_to_shadow_pgtable here to ensure it is
5181 * never reused.
5182 */
5183 vcpu->arch.write_fault_to_shadow_pgtable = false;
5184 kvm_clear_exception_queue(vcpu);
5185
5186 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5187 init_emulate_ctxt(vcpu);
5188
5189 /*
5190 * We will reenter on the same instruction since
5191 * we do not set complete_userspace_io. This does not
5192 * handle watchpoints yet, those would be handled in
5193 * the emulate_ops.
5194 */
5195 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5196 return r;
5197
5198 ctxt->interruptibility = 0;
5199 ctxt->have_exception = false;
5200 ctxt->exception.vector = -1;
5201 ctxt->perm_ok = false;
5202
5203 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5204
5205 r = x86_decode_insn(ctxt, insn, insn_len);
5206
5207 trace_kvm_emulate_insn_start(vcpu);
5208 ++vcpu->stat.insn_emulation;
5209 if (r != EMULATION_OK) {
5210 if (emulation_type & EMULTYPE_TRAP_UD)
5211 return EMULATE_FAIL;
5212 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5213 emulation_type))
5214 return EMULATE_DONE;
5215 if (emulation_type & EMULTYPE_SKIP)
5216 return EMULATE_FAIL;
5217 return handle_emulation_failure(vcpu);
5218 }
5219 }
5220
5221 if (emulation_type & EMULTYPE_SKIP) {
5222 kvm_rip_write(vcpu, ctxt->_eip);
5223 if (ctxt->eflags & X86_EFLAGS_RF)
5224 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5225 return EMULATE_DONE;
5226 }
5227
5228 if (retry_instruction(ctxt, cr2, emulation_type))
5229 return EMULATE_DONE;
5230
5231 /* this is needed for vmware backdoor interface to work since it
5232 changes registers values during IO operation */
5233 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5234 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5235 emulator_invalidate_register_cache(ctxt);
5236 }
5237
5238 restart:
5239 r = x86_emulate_insn(ctxt);
5240
5241 if (r == EMULATION_INTERCEPTED)
5242 return EMULATE_DONE;
5243
5244 if (r == EMULATION_FAILED) {
5245 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5246 emulation_type))
5247 return EMULATE_DONE;
5248
5249 return handle_emulation_failure(vcpu);
5250 }
5251
5252 if (ctxt->have_exception) {
5253 r = EMULATE_DONE;
5254 if (inject_emulated_exception(vcpu))
5255 return r;
5256 } else if (vcpu->arch.pio.count) {
5257 if (!vcpu->arch.pio.in) {
5258 /* FIXME: return into emulator if single-stepping. */
5259 vcpu->arch.pio.count = 0;
5260 } else {
5261 writeback = false;
5262 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5263 }
5264 r = EMULATE_USER_EXIT;
5265 } else if (vcpu->mmio_needed) {
5266 if (!vcpu->mmio_is_write)
5267 writeback = false;
5268 r = EMULATE_USER_EXIT;
5269 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5270 } else if (r == EMULATION_RESTART)
5271 goto restart;
5272 else
5273 r = EMULATE_DONE;
5274
5275 if (writeback) {
5276 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5277 toggle_interruptibility(vcpu, ctxt->interruptibility);
5278 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5279 if (vcpu->arch.hflags != ctxt->emul_flags)
5280 kvm_set_hflags(vcpu, ctxt->emul_flags);
5281 kvm_rip_write(vcpu, ctxt->eip);
5282 if (r == EMULATE_DONE)
5283 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5284 if (!ctxt->have_exception ||
5285 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5286 __kvm_set_rflags(vcpu, ctxt->eflags);
5287
5288 /*
5289 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5290 * do nothing, and it will be requested again as soon as
5291 * the shadow expires. But we still need to check here,
5292 * because POPF has no interrupt shadow.
5293 */
5294 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5295 kvm_make_request(KVM_REQ_EVENT, vcpu);
5296 } else
5297 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5298
5299 return r;
5300 }
5301 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5302
5303 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5304 {
5305 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5306 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5307 size, port, &val, 1);
5308 /* do not return to emulator after return from userspace */
5309 vcpu->arch.pio.count = 0;
5310 return ret;
5311 }
5312 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5313
5314 static void tsc_bad(void *info)
5315 {
5316 __this_cpu_write(cpu_tsc_khz, 0);
5317 }
5318
5319 static void tsc_khz_changed(void *data)
5320 {
5321 struct cpufreq_freqs *freq = data;
5322 unsigned long khz = 0;
5323
5324 if (data)
5325 khz = freq->new;
5326 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5327 khz = cpufreq_quick_get(raw_smp_processor_id());
5328 if (!khz)
5329 khz = tsc_khz;
5330 __this_cpu_write(cpu_tsc_khz, khz);
5331 }
5332
5333 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5334 void *data)
5335 {
5336 struct cpufreq_freqs *freq = data;
5337 struct kvm *kvm;
5338 struct kvm_vcpu *vcpu;
5339 int i, send_ipi = 0;
5340
5341 /*
5342 * We allow guests to temporarily run on slowing clocks,
5343 * provided we notify them after, or to run on accelerating
5344 * clocks, provided we notify them before. Thus time never
5345 * goes backwards.
5346 *
5347 * However, we have a problem. We can't atomically update
5348 * the frequency of a given CPU from this function; it is
5349 * merely a notifier, which can be called from any CPU.
5350 * Changing the TSC frequency at arbitrary points in time
5351 * requires a recomputation of local variables related to
5352 * the TSC for each VCPU. We must flag these local variables
5353 * to be updated and be sure the update takes place with the
5354 * new frequency before any guests proceed.
5355 *
5356 * Unfortunately, the combination of hotplug CPU and frequency
5357 * change creates an intractable locking scenario; the order
5358 * of when these callouts happen is undefined with respect to
5359 * CPU hotplug, and they can race with each other. As such,
5360 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5361 * undefined; you can actually have a CPU frequency change take
5362 * place in between the computation of X and the setting of the
5363 * variable. To protect against this problem, all updates of
5364 * the per_cpu tsc_khz variable are done in an interrupt
5365 * protected IPI, and all callers wishing to update the value
5366 * must wait for a synchronous IPI to complete (which is trivial
5367 * if the caller is on the CPU already). This establishes the
5368 * necessary total order on variable updates.
5369 *
5370 * Note that because a guest time update may take place
5371 * anytime after the setting of the VCPU's request bit, the
5372 * correct TSC value must be set before the request. However,
5373 * to ensure the update actually makes it to any guest which
5374 * starts running in hardware virtualization between the set
5375 * and the acquisition of the spinlock, we must also ping the
5376 * CPU after setting the request bit.
5377 *
5378 */
5379
5380 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5381 return 0;
5382 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5383 return 0;
5384
5385 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5386
5387 spin_lock(&kvm_lock);
5388 list_for_each_entry(kvm, &vm_list, vm_list) {
5389 kvm_for_each_vcpu(i, vcpu, kvm) {
5390 if (vcpu->cpu != freq->cpu)
5391 continue;
5392 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5393 if (vcpu->cpu != smp_processor_id())
5394 send_ipi = 1;
5395 }
5396 }
5397 spin_unlock(&kvm_lock);
5398
5399 if (freq->old < freq->new && send_ipi) {
5400 /*
5401 * We upscale the frequency. Must make the guest
5402 * doesn't see old kvmclock values while running with
5403 * the new frequency, otherwise we risk the guest sees
5404 * time go backwards.
5405 *
5406 * In case we update the frequency for another cpu
5407 * (which might be in guest context) send an interrupt
5408 * to kick the cpu out of guest context. Next time
5409 * guest context is entered kvmclock will be updated,
5410 * so the guest will not see stale values.
5411 */
5412 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5413 }
5414 return 0;
5415 }
5416
5417 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5418 .notifier_call = kvmclock_cpufreq_notifier
5419 };
5420
5421 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5422 unsigned long action, void *hcpu)
5423 {
5424 unsigned int cpu = (unsigned long)hcpu;
5425
5426 switch (action) {
5427 case CPU_ONLINE:
5428 case CPU_DOWN_FAILED:
5429 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5430 break;
5431 case CPU_DOWN_PREPARE:
5432 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5433 break;
5434 }
5435 return NOTIFY_OK;
5436 }
5437
5438 static struct notifier_block kvmclock_cpu_notifier_block = {
5439 .notifier_call = kvmclock_cpu_notifier,
5440 .priority = -INT_MAX
5441 };
5442
5443 static void kvm_timer_init(void)
5444 {
5445 int cpu;
5446
5447 max_tsc_khz = tsc_khz;
5448
5449 cpu_notifier_register_begin();
5450 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5451 #ifdef CONFIG_CPU_FREQ
5452 struct cpufreq_policy policy;
5453 memset(&policy, 0, sizeof(policy));
5454 cpu = get_cpu();
5455 cpufreq_get_policy(&policy, cpu);
5456 if (policy.cpuinfo.max_freq)
5457 max_tsc_khz = policy.cpuinfo.max_freq;
5458 put_cpu();
5459 #endif
5460 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5461 CPUFREQ_TRANSITION_NOTIFIER);
5462 }
5463 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5464 for_each_online_cpu(cpu)
5465 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5466
5467 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5468 cpu_notifier_register_done();
5469
5470 }
5471
5472 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5473
5474 int kvm_is_in_guest(void)
5475 {
5476 return __this_cpu_read(current_vcpu) != NULL;
5477 }
5478
5479 static int kvm_is_user_mode(void)
5480 {
5481 int user_mode = 3;
5482
5483 if (__this_cpu_read(current_vcpu))
5484 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5485
5486 return user_mode != 0;
5487 }
5488
5489 static unsigned long kvm_get_guest_ip(void)
5490 {
5491 unsigned long ip = 0;
5492
5493 if (__this_cpu_read(current_vcpu))
5494 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5495
5496 return ip;
5497 }
5498
5499 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5500 .is_in_guest = kvm_is_in_guest,
5501 .is_user_mode = kvm_is_user_mode,
5502 .get_guest_ip = kvm_get_guest_ip,
5503 };
5504
5505 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5506 {
5507 __this_cpu_write(current_vcpu, vcpu);
5508 }
5509 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5510
5511 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5512 {
5513 __this_cpu_write(current_vcpu, NULL);
5514 }
5515 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5516
5517 static void kvm_set_mmio_spte_mask(void)
5518 {
5519 u64 mask;
5520 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5521
5522 /*
5523 * Set the reserved bits and the present bit of an paging-structure
5524 * entry to generate page fault with PFER.RSV = 1.
5525 */
5526 /* Mask the reserved physical address bits. */
5527 mask = rsvd_bits(maxphyaddr, 51);
5528
5529 /* Bit 62 is always reserved for 32bit host. */
5530 mask |= 0x3ull << 62;
5531
5532 /* Set the present bit. */
5533 mask |= 1ull;
5534
5535 #ifdef CONFIG_X86_64
5536 /*
5537 * If reserved bit is not supported, clear the present bit to disable
5538 * mmio page fault.
5539 */
5540 if (maxphyaddr == 52)
5541 mask &= ~1ull;
5542 #endif
5543
5544 kvm_mmu_set_mmio_spte_mask(mask);
5545 }
5546
5547 #ifdef CONFIG_X86_64
5548 static void pvclock_gtod_update_fn(struct work_struct *work)
5549 {
5550 struct kvm *kvm;
5551
5552 struct kvm_vcpu *vcpu;
5553 int i;
5554
5555 spin_lock(&kvm_lock);
5556 list_for_each_entry(kvm, &vm_list, vm_list)
5557 kvm_for_each_vcpu(i, vcpu, kvm)
5558 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5559 atomic_set(&kvm_guest_has_master_clock, 0);
5560 spin_unlock(&kvm_lock);
5561 }
5562
5563 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5564
5565 /*
5566 * Notification about pvclock gtod data update.
5567 */
5568 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5569 void *priv)
5570 {
5571 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5572 struct timekeeper *tk = priv;
5573
5574 update_pvclock_gtod(tk);
5575
5576 /* disable master clock if host does not trust, or does not
5577 * use, TSC clocksource
5578 */
5579 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5580 atomic_read(&kvm_guest_has_master_clock) != 0)
5581 queue_work(system_long_wq, &pvclock_gtod_work);
5582
5583 return 0;
5584 }
5585
5586 static struct notifier_block pvclock_gtod_notifier = {
5587 .notifier_call = pvclock_gtod_notify,
5588 };
5589 #endif
5590
5591 int kvm_arch_init(void *opaque)
5592 {
5593 int r;
5594 struct kvm_x86_ops *ops = opaque;
5595
5596 if (kvm_x86_ops) {
5597 printk(KERN_ERR "kvm: already loaded the other module\n");
5598 r = -EEXIST;
5599 goto out;
5600 }
5601
5602 if (!ops->cpu_has_kvm_support()) {
5603 printk(KERN_ERR "kvm: no hardware support\n");
5604 r = -EOPNOTSUPP;
5605 goto out;
5606 }
5607 if (ops->disabled_by_bios()) {
5608 printk(KERN_ERR "kvm: disabled by bios\n");
5609 r = -EOPNOTSUPP;
5610 goto out;
5611 }
5612
5613 r = -ENOMEM;
5614 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5615 if (!shared_msrs) {
5616 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5617 goto out;
5618 }
5619
5620 r = kvm_mmu_module_init();
5621 if (r)
5622 goto out_free_percpu;
5623
5624 kvm_set_mmio_spte_mask();
5625
5626 kvm_x86_ops = ops;
5627
5628 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5629 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5630
5631 kvm_timer_init();
5632
5633 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5634
5635 if (cpu_has_xsave)
5636 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5637
5638 kvm_lapic_init();
5639 #ifdef CONFIG_X86_64
5640 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5641 #endif
5642
5643 return 0;
5644
5645 out_free_percpu:
5646 free_percpu(shared_msrs);
5647 out:
5648 return r;
5649 }
5650
5651 void kvm_arch_exit(void)
5652 {
5653 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5654
5655 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5656 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5657 CPUFREQ_TRANSITION_NOTIFIER);
5658 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5659 #ifdef CONFIG_X86_64
5660 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5661 #endif
5662 kvm_x86_ops = NULL;
5663 kvm_mmu_module_exit();
5664 free_percpu(shared_msrs);
5665 }
5666
5667 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5668 {
5669 ++vcpu->stat.halt_exits;
5670 if (irqchip_in_kernel(vcpu->kvm)) {
5671 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5672 return 1;
5673 } else {
5674 vcpu->run->exit_reason = KVM_EXIT_HLT;
5675 return 0;
5676 }
5677 }
5678 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5679
5680 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5681 {
5682 kvm_x86_ops->skip_emulated_instruction(vcpu);
5683 return kvm_vcpu_halt(vcpu);
5684 }
5685 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5686
5687 /*
5688 * kvm_pv_kick_cpu_op: Kick a vcpu.
5689 *
5690 * @apicid - apicid of vcpu to be kicked.
5691 */
5692 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5693 {
5694 struct kvm_lapic_irq lapic_irq;
5695
5696 lapic_irq.shorthand = 0;
5697 lapic_irq.dest_mode = 0;
5698 lapic_irq.dest_id = apicid;
5699 lapic_irq.msi_redir_hint = false;
5700
5701 lapic_irq.delivery_mode = APIC_DM_REMRD;
5702 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5703 }
5704
5705 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5706 {
5707 unsigned long nr, a0, a1, a2, a3, ret;
5708 int op_64_bit, r = 1;
5709
5710 kvm_x86_ops->skip_emulated_instruction(vcpu);
5711
5712 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5713 return kvm_hv_hypercall(vcpu);
5714
5715 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5716 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5717 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5718 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5719 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5720
5721 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5722
5723 op_64_bit = is_64_bit_mode(vcpu);
5724 if (!op_64_bit) {
5725 nr &= 0xFFFFFFFF;
5726 a0 &= 0xFFFFFFFF;
5727 a1 &= 0xFFFFFFFF;
5728 a2 &= 0xFFFFFFFF;
5729 a3 &= 0xFFFFFFFF;
5730 }
5731
5732 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5733 ret = -KVM_EPERM;
5734 goto out;
5735 }
5736
5737 switch (nr) {
5738 case KVM_HC_VAPIC_POLL_IRQ:
5739 ret = 0;
5740 break;
5741 case KVM_HC_KICK_CPU:
5742 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5743 ret = 0;
5744 break;
5745 default:
5746 ret = -KVM_ENOSYS;
5747 break;
5748 }
5749 out:
5750 if (!op_64_bit)
5751 ret = (u32)ret;
5752 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5753 ++vcpu->stat.hypercalls;
5754 return r;
5755 }
5756 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5757
5758 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5759 {
5760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5761 char instruction[3];
5762 unsigned long rip = kvm_rip_read(vcpu);
5763
5764 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5765
5766 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5767 }
5768
5769 /*
5770 * Check if userspace requested an interrupt window, and that the
5771 * interrupt window is open.
5772 *
5773 * No need to exit to userspace if we already have an interrupt queued.
5774 */
5775 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5776 {
5777 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5778 vcpu->run->request_interrupt_window &&
5779 kvm_arch_interrupt_allowed(vcpu));
5780 }
5781
5782 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5783 {
5784 struct kvm_run *kvm_run = vcpu->run;
5785
5786 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5787 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5788 kvm_run->cr8 = kvm_get_cr8(vcpu);
5789 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5790 if (irqchip_in_kernel(vcpu->kvm))
5791 kvm_run->ready_for_interrupt_injection = 1;
5792 else
5793 kvm_run->ready_for_interrupt_injection =
5794 kvm_arch_interrupt_allowed(vcpu) &&
5795 !kvm_cpu_has_interrupt(vcpu) &&
5796 !kvm_event_needs_reinjection(vcpu);
5797 }
5798
5799 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5800 {
5801 int max_irr, tpr;
5802
5803 if (!kvm_x86_ops->update_cr8_intercept)
5804 return;
5805
5806 if (!vcpu->arch.apic)
5807 return;
5808
5809 if (!vcpu->arch.apic->vapic_addr)
5810 max_irr = kvm_lapic_find_highest_irr(vcpu);
5811 else
5812 max_irr = -1;
5813
5814 if (max_irr != -1)
5815 max_irr >>= 4;
5816
5817 tpr = kvm_lapic_get_cr8(vcpu);
5818
5819 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5820 }
5821
5822 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5823 {
5824 int r;
5825
5826 /* try to reinject previous events if any */
5827 if (vcpu->arch.exception.pending) {
5828 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5829 vcpu->arch.exception.has_error_code,
5830 vcpu->arch.exception.error_code);
5831
5832 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5833 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5834 X86_EFLAGS_RF);
5835
5836 if (vcpu->arch.exception.nr == DB_VECTOR &&
5837 (vcpu->arch.dr7 & DR7_GD)) {
5838 vcpu->arch.dr7 &= ~DR7_GD;
5839 kvm_update_dr7(vcpu);
5840 }
5841
5842 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5843 vcpu->arch.exception.has_error_code,
5844 vcpu->arch.exception.error_code,
5845 vcpu->arch.exception.reinject);
5846 return 0;
5847 }
5848
5849 if (vcpu->arch.nmi_injected) {
5850 kvm_x86_ops->set_nmi(vcpu);
5851 return 0;
5852 }
5853
5854 if (vcpu->arch.interrupt.pending) {
5855 kvm_x86_ops->set_irq(vcpu);
5856 return 0;
5857 }
5858
5859 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5860 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5861 if (r != 0)
5862 return r;
5863 }
5864
5865 /* try to inject new event if pending */
5866 if (vcpu->arch.nmi_pending) {
5867 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5868 --vcpu->arch.nmi_pending;
5869 vcpu->arch.nmi_injected = true;
5870 kvm_x86_ops->set_nmi(vcpu);
5871 }
5872 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5873 /*
5874 * Because interrupts can be injected asynchronously, we are
5875 * calling check_nested_events again here to avoid a race condition.
5876 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5877 * proposal and current concerns. Perhaps we should be setting
5878 * KVM_REQ_EVENT only on certain events and not unconditionally?
5879 */
5880 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5881 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5882 if (r != 0)
5883 return r;
5884 }
5885 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5886 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5887 false);
5888 kvm_x86_ops->set_irq(vcpu);
5889 }
5890 }
5891 return 0;
5892 }
5893
5894 static void process_nmi(struct kvm_vcpu *vcpu)
5895 {
5896 unsigned limit = 2;
5897
5898 /*
5899 * x86 is limited to one NMI running, and one NMI pending after it.
5900 * If an NMI is already in progress, limit further NMIs to just one.
5901 * Otherwise, allow two (and we'll inject the first one immediately).
5902 */
5903 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5904 limit = 1;
5905
5906 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5907 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5908 kvm_make_request(KVM_REQ_EVENT, vcpu);
5909 }
5910
5911 #define put_smstate(type, buf, offset, val) \
5912 *(type *)((buf) + (offset) - 0x7e00) = val
5913
5914 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5915 {
5916 u32 flags = 0;
5917 flags |= seg->g << 23;
5918 flags |= seg->db << 22;
5919 flags |= seg->l << 21;
5920 flags |= seg->avl << 20;
5921 flags |= seg->present << 15;
5922 flags |= seg->dpl << 13;
5923 flags |= seg->s << 12;
5924 flags |= seg->type << 8;
5925 return flags;
5926 }
5927
5928 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5929 {
5930 struct kvm_segment seg;
5931 int offset;
5932
5933 kvm_get_segment(vcpu, &seg, n);
5934 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5935
5936 if (n < 3)
5937 offset = 0x7f84 + n * 12;
5938 else
5939 offset = 0x7f2c + (n - 3) * 12;
5940
5941 put_smstate(u32, buf, offset + 8, seg.base);
5942 put_smstate(u32, buf, offset + 4, seg.limit);
5943 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5944 }
5945
5946 #ifdef CONFIG_X86_64
5947 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5948 {
5949 struct kvm_segment seg;
5950 int offset;
5951 u16 flags;
5952
5953 kvm_get_segment(vcpu, &seg, n);
5954 offset = 0x7e00 + n * 16;
5955
5956 flags = process_smi_get_segment_flags(&seg) >> 8;
5957 put_smstate(u16, buf, offset, seg.selector);
5958 put_smstate(u16, buf, offset + 2, flags);
5959 put_smstate(u32, buf, offset + 4, seg.limit);
5960 put_smstate(u64, buf, offset + 8, seg.base);
5961 }
5962 #endif
5963
5964 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5965 {
5966 struct desc_ptr dt;
5967 struct kvm_segment seg;
5968 unsigned long val;
5969 int i;
5970
5971 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5972 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5973 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5974 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5975
5976 for (i = 0; i < 8; i++)
5977 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
5978
5979 kvm_get_dr(vcpu, 6, &val);
5980 put_smstate(u32, buf, 0x7fcc, (u32)val);
5981 kvm_get_dr(vcpu, 7, &val);
5982 put_smstate(u32, buf, 0x7fc8, (u32)val);
5983
5984 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
5985 put_smstate(u32, buf, 0x7fc4, seg.selector);
5986 put_smstate(u32, buf, 0x7f64, seg.base);
5987 put_smstate(u32, buf, 0x7f60, seg.limit);
5988 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
5989
5990 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
5991 put_smstate(u32, buf, 0x7fc0, seg.selector);
5992 put_smstate(u32, buf, 0x7f80, seg.base);
5993 put_smstate(u32, buf, 0x7f7c, seg.limit);
5994 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
5995
5996 kvm_x86_ops->get_gdt(vcpu, &dt);
5997 put_smstate(u32, buf, 0x7f74, dt.address);
5998 put_smstate(u32, buf, 0x7f70, dt.size);
5999
6000 kvm_x86_ops->get_idt(vcpu, &dt);
6001 put_smstate(u32, buf, 0x7f58, dt.address);
6002 put_smstate(u32, buf, 0x7f54, dt.size);
6003
6004 for (i = 0; i < 6; i++)
6005 process_smi_save_seg_32(vcpu, buf, i);
6006
6007 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6008
6009 /* revision id */
6010 put_smstate(u32, buf, 0x7efc, 0x00020000);
6011 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6012 }
6013
6014 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6015 {
6016 #ifdef CONFIG_X86_64
6017 struct desc_ptr dt;
6018 struct kvm_segment seg;
6019 unsigned long val;
6020 int i;
6021
6022 for (i = 0; i < 16; i++)
6023 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6024
6025 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6026 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6027
6028 kvm_get_dr(vcpu, 6, &val);
6029 put_smstate(u64, buf, 0x7f68, val);
6030 kvm_get_dr(vcpu, 7, &val);
6031 put_smstate(u64, buf, 0x7f60, val);
6032
6033 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6034 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6035 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6036
6037 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6038
6039 /* revision id */
6040 put_smstate(u32, buf, 0x7efc, 0x00020064);
6041
6042 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6043
6044 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6045 put_smstate(u16, buf, 0x7e90, seg.selector);
6046 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6047 put_smstate(u32, buf, 0x7e94, seg.limit);
6048 put_smstate(u64, buf, 0x7e98, seg.base);
6049
6050 kvm_x86_ops->get_idt(vcpu, &dt);
6051 put_smstate(u32, buf, 0x7e84, dt.size);
6052 put_smstate(u64, buf, 0x7e88, dt.address);
6053
6054 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6055 put_smstate(u16, buf, 0x7e70, seg.selector);
6056 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6057 put_smstate(u32, buf, 0x7e74, seg.limit);
6058 put_smstate(u64, buf, 0x7e78, seg.base);
6059
6060 kvm_x86_ops->get_gdt(vcpu, &dt);
6061 put_smstate(u32, buf, 0x7e64, dt.size);
6062 put_smstate(u64, buf, 0x7e68, dt.address);
6063
6064 for (i = 0; i < 6; i++)
6065 process_smi_save_seg_64(vcpu, buf, i);
6066 #else
6067 WARN_ON_ONCE(1);
6068 #endif
6069 }
6070
6071 static void process_smi(struct kvm_vcpu *vcpu)
6072 {
6073 struct kvm_segment cs, ds;
6074 struct desc_ptr dt;
6075 char buf[512];
6076 u32 cr0;
6077
6078 if (is_smm(vcpu)) {
6079 vcpu->arch.smi_pending = true;
6080 return;
6081 }
6082
6083 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6084 vcpu->arch.hflags |= HF_SMM_MASK;
6085 memset(buf, 0, 512);
6086 if (guest_cpuid_has_longmode(vcpu))
6087 process_smi_save_state_64(vcpu, buf);
6088 else
6089 process_smi_save_state_32(vcpu, buf);
6090
6091 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6092
6093 if (kvm_x86_ops->get_nmi_mask(vcpu))
6094 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6095 else
6096 kvm_x86_ops->set_nmi_mask(vcpu, true);
6097
6098 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6099 kvm_rip_write(vcpu, 0x8000);
6100
6101 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6102 kvm_x86_ops->set_cr0(vcpu, cr0);
6103 vcpu->arch.cr0 = cr0;
6104
6105 kvm_x86_ops->set_cr4(vcpu, 0);
6106
6107 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6108 dt.address = dt.size = 0;
6109 kvm_x86_ops->set_idt(vcpu, &dt);
6110
6111 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6112
6113 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6114 cs.base = vcpu->arch.smbase;
6115
6116 ds.selector = 0;
6117 ds.base = 0;
6118
6119 cs.limit = ds.limit = 0xffffffff;
6120 cs.type = ds.type = 0x3;
6121 cs.dpl = ds.dpl = 0;
6122 cs.db = ds.db = 0;
6123 cs.s = ds.s = 1;
6124 cs.l = ds.l = 0;
6125 cs.g = ds.g = 1;
6126 cs.avl = ds.avl = 0;
6127 cs.present = ds.present = 1;
6128 cs.unusable = ds.unusable = 0;
6129 cs.padding = ds.padding = 0;
6130
6131 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6132 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6133 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6134 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6135 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6136 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6137
6138 if (guest_cpuid_has_longmode(vcpu))
6139 kvm_x86_ops->set_efer(vcpu, 0);
6140
6141 kvm_update_cpuid(vcpu);
6142 kvm_mmu_reset_context(vcpu);
6143 }
6144
6145 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6146 {
6147 u64 eoi_exit_bitmap[4];
6148 u32 tmr[8];
6149
6150 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6151 return;
6152
6153 memset(eoi_exit_bitmap, 0, 32);
6154 memset(tmr, 0, 32);
6155
6156 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6157 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6158 kvm_apic_update_tmr(vcpu, tmr);
6159 }
6160
6161 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6162 {
6163 ++vcpu->stat.tlb_flush;
6164 kvm_x86_ops->tlb_flush(vcpu);
6165 }
6166
6167 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6168 {
6169 struct page *page = NULL;
6170
6171 if (!irqchip_in_kernel(vcpu->kvm))
6172 return;
6173
6174 if (!kvm_x86_ops->set_apic_access_page_addr)
6175 return;
6176
6177 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6178 if (is_error_page(page))
6179 return;
6180 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6181
6182 /*
6183 * Do not pin apic access page in memory, the MMU notifier
6184 * will call us again if it is migrated or swapped out.
6185 */
6186 put_page(page);
6187 }
6188 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6189
6190 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6191 unsigned long address)
6192 {
6193 /*
6194 * The physical address of apic access page is stored in the VMCS.
6195 * Update it when it becomes invalid.
6196 */
6197 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6198 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6199 }
6200
6201 /*
6202 * Returns 1 to let vcpu_run() continue the guest execution loop without
6203 * exiting to the userspace. Otherwise, the value will be returned to the
6204 * userspace.
6205 */
6206 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6207 {
6208 int r;
6209 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6210 vcpu->run->request_interrupt_window;
6211 bool req_immediate_exit = false;
6212
6213 if (vcpu->requests) {
6214 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6215 kvm_mmu_unload(vcpu);
6216 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6217 __kvm_migrate_timers(vcpu);
6218 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6219 kvm_gen_update_masterclock(vcpu->kvm);
6220 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6221 kvm_gen_kvmclock_update(vcpu);
6222 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6223 r = kvm_guest_time_update(vcpu);
6224 if (unlikely(r))
6225 goto out;
6226 }
6227 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6228 kvm_mmu_sync_roots(vcpu);
6229 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6230 kvm_vcpu_flush_tlb(vcpu);
6231 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6232 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6233 r = 0;
6234 goto out;
6235 }
6236 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6237 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6238 r = 0;
6239 goto out;
6240 }
6241 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6242 vcpu->fpu_active = 0;
6243 kvm_x86_ops->fpu_deactivate(vcpu);
6244 }
6245 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6246 /* Page is swapped out. Do synthetic halt */
6247 vcpu->arch.apf.halted = true;
6248 r = 1;
6249 goto out;
6250 }
6251 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6252 record_steal_time(vcpu);
6253 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6254 process_smi(vcpu);
6255 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6256 process_nmi(vcpu);
6257 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6258 kvm_pmu_handle_event(vcpu);
6259 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6260 kvm_pmu_deliver_pmi(vcpu);
6261 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6262 vcpu_scan_ioapic(vcpu);
6263 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6264 kvm_vcpu_reload_apic_access_page(vcpu);
6265 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6266 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6267 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6268 r = 0;
6269 goto out;
6270 }
6271 }
6272
6273 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6274 kvm_apic_accept_events(vcpu);
6275 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6276 r = 1;
6277 goto out;
6278 }
6279
6280 if (inject_pending_event(vcpu, req_int_win) != 0)
6281 req_immediate_exit = true;
6282 /* enable NMI/IRQ window open exits if needed */
6283 else if (vcpu->arch.nmi_pending)
6284 kvm_x86_ops->enable_nmi_window(vcpu);
6285 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6286 kvm_x86_ops->enable_irq_window(vcpu);
6287
6288 if (kvm_lapic_enabled(vcpu)) {
6289 /*
6290 * Update architecture specific hints for APIC
6291 * virtual interrupt delivery.
6292 */
6293 if (kvm_x86_ops->hwapic_irr_update)
6294 kvm_x86_ops->hwapic_irr_update(vcpu,
6295 kvm_lapic_find_highest_irr(vcpu));
6296 update_cr8_intercept(vcpu);
6297 kvm_lapic_sync_to_vapic(vcpu);
6298 }
6299 }
6300
6301 r = kvm_mmu_reload(vcpu);
6302 if (unlikely(r)) {
6303 goto cancel_injection;
6304 }
6305
6306 preempt_disable();
6307
6308 kvm_x86_ops->prepare_guest_switch(vcpu);
6309 if (vcpu->fpu_active)
6310 kvm_load_guest_fpu(vcpu);
6311 kvm_load_guest_xcr0(vcpu);
6312
6313 vcpu->mode = IN_GUEST_MODE;
6314
6315 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6316
6317 /* We should set ->mode before check ->requests,
6318 * see the comment in make_all_cpus_request.
6319 */
6320 smp_mb__after_srcu_read_unlock();
6321
6322 local_irq_disable();
6323
6324 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6325 || need_resched() || signal_pending(current)) {
6326 vcpu->mode = OUTSIDE_GUEST_MODE;
6327 smp_wmb();
6328 local_irq_enable();
6329 preempt_enable();
6330 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6331 r = 1;
6332 goto cancel_injection;
6333 }
6334
6335 if (req_immediate_exit)
6336 smp_send_reschedule(vcpu->cpu);
6337
6338 __kvm_guest_enter();
6339
6340 if (unlikely(vcpu->arch.switch_db_regs)) {
6341 set_debugreg(0, 7);
6342 set_debugreg(vcpu->arch.eff_db[0], 0);
6343 set_debugreg(vcpu->arch.eff_db[1], 1);
6344 set_debugreg(vcpu->arch.eff_db[2], 2);
6345 set_debugreg(vcpu->arch.eff_db[3], 3);
6346 set_debugreg(vcpu->arch.dr6, 6);
6347 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6348 }
6349
6350 trace_kvm_entry(vcpu->vcpu_id);
6351 wait_lapic_expire(vcpu);
6352 kvm_x86_ops->run(vcpu);
6353
6354 /*
6355 * Do this here before restoring debug registers on the host. And
6356 * since we do this before handling the vmexit, a DR access vmexit
6357 * can (a) read the correct value of the debug registers, (b) set
6358 * KVM_DEBUGREG_WONT_EXIT again.
6359 */
6360 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6361 int i;
6362
6363 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6364 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6365 for (i = 0; i < KVM_NR_DB_REGS; i++)
6366 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6367 }
6368
6369 /*
6370 * If the guest has used debug registers, at least dr7
6371 * will be disabled while returning to the host.
6372 * If we don't have active breakpoints in the host, we don't
6373 * care about the messed up debug address registers. But if
6374 * we have some of them active, restore the old state.
6375 */
6376 if (hw_breakpoint_active())
6377 hw_breakpoint_restore();
6378
6379 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6380 rdtsc());
6381
6382 vcpu->mode = OUTSIDE_GUEST_MODE;
6383 smp_wmb();
6384
6385 /* Interrupt is enabled by handle_external_intr() */
6386 kvm_x86_ops->handle_external_intr(vcpu);
6387
6388 ++vcpu->stat.exits;
6389
6390 /*
6391 * We must have an instruction between local_irq_enable() and
6392 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6393 * the interrupt shadow. The stat.exits increment will do nicely.
6394 * But we need to prevent reordering, hence this barrier():
6395 */
6396 barrier();
6397
6398 kvm_guest_exit();
6399
6400 preempt_enable();
6401
6402 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6403
6404 /*
6405 * Profile KVM exit RIPs:
6406 */
6407 if (unlikely(prof_on == KVM_PROFILING)) {
6408 unsigned long rip = kvm_rip_read(vcpu);
6409 profile_hit(KVM_PROFILING, (void *)rip);
6410 }
6411
6412 if (unlikely(vcpu->arch.tsc_always_catchup))
6413 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6414
6415 if (vcpu->arch.apic_attention)
6416 kvm_lapic_sync_from_vapic(vcpu);
6417
6418 r = kvm_x86_ops->handle_exit(vcpu);
6419 return r;
6420
6421 cancel_injection:
6422 kvm_x86_ops->cancel_injection(vcpu);
6423 if (unlikely(vcpu->arch.apic_attention))
6424 kvm_lapic_sync_from_vapic(vcpu);
6425 out:
6426 return r;
6427 }
6428
6429 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6430 {
6431 if (!kvm_arch_vcpu_runnable(vcpu)) {
6432 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6433 kvm_vcpu_block(vcpu);
6434 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6435 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6436 return 1;
6437 }
6438
6439 kvm_apic_accept_events(vcpu);
6440 switch(vcpu->arch.mp_state) {
6441 case KVM_MP_STATE_HALTED:
6442 vcpu->arch.pv.pv_unhalted = false;
6443 vcpu->arch.mp_state =
6444 KVM_MP_STATE_RUNNABLE;
6445 case KVM_MP_STATE_RUNNABLE:
6446 vcpu->arch.apf.halted = false;
6447 break;
6448 case KVM_MP_STATE_INIT_RECEIVED:
6449 break;
6450 default:
6451 return -EINTR;
6452 break;
6453 }
6454 return 1;
6455 }
6456
6457 static int vcpu_run(struct kvm_vcpu *vcpu)
6458 {
6459 int r;
6460 struct kvm *kvm = vcpu->kvm;
6461
6462 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6463
6464 for (;;) {
6465 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6466 !vcpu->arch.apf.halted)
6467 r = vcpu_enter_guest(vcpu);
6468 else
6469 r = vcpu_block(kvm, vcpu);
6470 if (r <= 0)
6471 break;
6472
6473 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6474 if (kvm_cpu_has_pending_timer(vcpu))
6475 kvm_inject_pending_timer_irqs(vcpu);
6476
6477 if (dm_request_for_irq_injection(vcpu)) {
6478 r = -EINTR;
6479 vcpu->run->exit_reason = KVM_EXIT_INTR;
6480 ++vcpu->stat.request_irq_exits;
6481 break;
6482 }
6483
6484 kvm_check_async_pf_completion(vcpu);
6485
6486 if (signal_pending(current)) {
6487 r = -EINTR;
6488 vcpu->run->exit_reason = KVM_EXIT_INTR;
6489 ++vcpu->stat.signal_exits;
6490 break;
6491 }
6492 if (need_resched()) {
6493 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6494 cond_resched();
6495 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6496 }
6497 }
6498
6499 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6500
6501 return r;
6502 }
6503
6504 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6505 {
6506 int r;
6507 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6508 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6509 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6510 if (r != EMULATE_DONE)
6511 return 0;
6512 return 1;
6513 }
6514
6515 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6516 {
6517 BUG_ON(!vcpu->arch.pio.count);
6518
6519 return complete_emulated_io(vcpu);
6520 }
6521
6522 /*
6523 * Implements the following, as a state machine:
6524 *
6525 * read:
6526 * for each fragment
6527 * for each mmio piece in the fragment
6528 * write gpa, len
6529 * exit
6530 * copy data
6531 * execute insn
6532 *
6533 * write:
6534 * for each fragment
6535 * for each mmio piece in the fragment
6536 * write gpa, len
6537 * copy data
6538 * exit
6539 */
6540 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6541 {
6542 struct kvm_run *run = vcpu->run;
6543 struct kvm_mmio_fragment *frag;
6544 unsigned len;
6545
6546 BUG_ON(!vcpu->mmio_needed);
6547
6548 /* Complete previous fragment */
6549 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6550 len = min(8u, frag->len);
6551 if (!vcpu->mmio_is_write)
6552 memcpy(frag->data, run->mmio.data, len);
6553
6554 if (frag->len <= 8) {
6555 /* Switch to the next fragment. */
6556 frag++;
6557 vcpu->mmio_cur_fragment++;
6558 } else {
6559 /* Go forward to the next mmio piece. */
6560 frag->data += len;
6561 frag->gpa += len;
6562 frag->len -= len;
6563 }
6564
6565 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6566 vcpu->mmio_needed = 0;
6567
6568 /* FIXME: return into emulator if single-stepping. */
6569 if (vcpu->mmio_is_write)
6570 return 1;
6571 vcpu->mmio_read_completed = 1;
6572 return complete_emulated_io(vcpu);
6573 }
6574
6575 run->exit_reason = KVM_EXIT_MMIO;
6576 run->mmio.phys_addr = frag->gpa;
6577 if (vcpu->mmio_is_write)
6578 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6579 run->mmio.len = min(8u, frag->len);
6580 run->mmio.is_write = vcpu->mmio_is_write;
6581 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6582 return 0;
6583 }
6584
6585
6586 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6587 {
6588 struct fpu *fpu = &current->thread.fpu;
6589 int r;
6590 sigset_t sigsaved;
6591
6592 fpu__activate_curr(fpu);
6593
6594 if (vcpu->sigset_active)
6595 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6596
6597 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6598 kvm_vcpu_block(vcpu);
6599 kvm_apic_accept_events(vcpu);
6600 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6601 r = -EAGAIN;
6602 goto out;
6603 }
6604
6605 /* re-sync apic's tpr */
6606 if (!irqchip_in_kernel(vcpu->kvm)) {
6607 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6608 r = -EINVAL;
6609 goto out;
6610 }
6611 }
6612
6613 if (unlikely(vcpu->arch.complete_userspace_io)) {
6614 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6615 vcpu->arch.complete_userspace_io = NULL;
6616 r = cui(vcpu);
6617 if (r <= 0)
6618 goto out;
6619 } else
6620 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6621
6622 r = vcpu_run(vcpu);
6623
6624 out:
6625 post_kvm_run_save(vcpu);
6626 if (vcpu->sigset_active)
6627 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6628
6629 return r;
6630 }
6631
6632 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6633 {
6634 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6635 /*
6636 * We are here if userspace calls get_regs() in the middle of
6637 * instruction emulation. Registers state needs to be copied
6638 * back from emulation context to vcpu. Userspace shouldn't do
6639 * that usually, but some bad designed PV devices (vmware
6640 * backdoor interface) need this to work
6641 */
6642 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6643 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6644 }
6645 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6646 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6647 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6648 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6649 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6650 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6651 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6652 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6653 #ifdef CONFIG_X86_64
6654 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6655 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6656 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6657 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6658 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6659 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6660 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6661 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6662 #endif
6663
6664 regs->rip = kvm_rip_read(vcpu);
6665 regs->rflags = kvm_get_rflags(vcpu);
6666
6667 return 0;
6668 }
6669
6670 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6671 {
6672 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6673 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6674
6675 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6676 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6677 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6678 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6679 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6680 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6681 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6682 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6683 #ifdef CONFIG_X86_64
6684 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6685 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6686 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6687 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6688 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6689 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6690 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6691 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6692 #endif
6693
6694 kvm_rip_write(vcpu, regs->rip);
6695 kvm_set_rflags(vcpu, regs->rflags);
6696
6697 vcpu->arch.exception.pending = false;
6698
6699 kvm_make_request(KVM_REQ_EVENT, vcpu);
6700
6701 return 0;
6702 }
6703
6704 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6705 {
6706 struct kvm_segment cs;
6707
6708 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6709 *db = cs.db;
6710 *l = cs.l;
6711 }
6712 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6713
6714 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6715 struct kvm_sregs *sregs)
6716 {
6717 struct desc_ptr dt;
6718
6719 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6720 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6721 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6722 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6723 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6724 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6725
6726 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6727 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6728
6729 kvm_x86_ops->get_idt(vcpu, &dt);
6730 sregs->idt.limit = dt.size;
6731 sregs->idt.base = dt.address;
6732 kvm_x86_ops->get_gdt(vcpu, &dt);
6733 sregs->gdt.limit = dt.size;
6734 sregs->gdt.base = dt.address;
6735
6736 sregs->cr0 = kvm_read_cr0(vcpu);
6737 sregs->cr2 = vcpu->arch.cr2;
6738 sregs->cr3 = kvm_read_cr3(vcpu);
6739 sregs->cr4 = kvm_read_cr4(vcpu);
6740 sregs->cr8 = kvm_get_cr8(vcpu);
6741 sregs->efer = vcpu->arch.efer;
6742 sregs->apic_base = kvm_get_apic_base(vcpu);
6743
6744 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6745
6746 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6747 set_bit(vcpu->arch.interrupt.nr,
6748 (unsigned long *)sregs->interrupt_bitmap);
6749
6750 return 0;
6751 }
6752
6753 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6754 struct kvm_mp_state *mp_state)
6755 {
6756 kvm_apic_accept_events(vcpu);
6757 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6758 vcpu->arch.pv.pv_unhalted)
6759 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6760 else
6761 mp_state->mp_state = vcpu->arch.mp_state;
6762
6763 return 0;
6764 }
6765
6766 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6767 struct kvm_mp_state *mp_state)
6768 {
6769 if (!kvm_vcpu_has_lapic(vcpu) &&
6770 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6771 return -EINVAL;
6772
6773 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6774 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6775 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6776 } else
6777 vcpu->arch.mp_state = mp_state->mp_state;
6778 kvm_make_request(KVM_REQ_EVENT, vcpu);
6779 return 0;
6780 }
6781
6782 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6783 int reason, bool has_error_code, u32 error_code)
6784 {
6785 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6786 int ret;
6787
6788 init_emulate_ctxt(vcpu);
6789
6790 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6791 has_error_code, error_code);
6792
6793 if (ret)
6794 return EMULATE_FAIL;
6795
6796 kvm_rip_write(vcpu, ctxt->eip);
6797 kvm_set_rflags(vcpu, ctxt->eflags);
6798 kvm_make_request(KVM_REQ_EVENT, vcpu);
6799 return EMULATE_DONE;
6800 }
6801 EXPORT_SYMBOL_GPL(kvm_task_switch);
6802
6803 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6804 struct kvm_sregs *sregs)
6805 {
6806 struct msr_data apic_base_msr;
6807 int mmu_reset_needed = 0;
6808 int pending_vec, max_bits, idx;
6809 struct desc_ptr dt;
6810
6811 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6812 return -EINVAL;
6813
6814 dt.size = sregs->idt.limit;
6815 dt.address = sregs->idt.base;
6816 kvm_x86_ops->set_idt(vcpu, &dt);
6817 dt.size = sregs->gdt.limit;
6818 dt.address = sregs->gdt.base;
6819 kvm_x86_ops->set_gdt(vcpu, &dt);
6820
6821 vcpu->arch.cr2 = sregs->cr2;
6822 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6823 vcpu->arch.cr3 = sregs->cr3;
6824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6825
6826 kvm_set_cr8(vcpu, sregs->cr8);
6827
6828 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6829 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6830 apic_base_msr.data = sregs->apic_base;
6831 apic_base_msr.host_initiated = true;
6832 kvm_set_apic_base(vcpu, &apic_base_msr);
6833
6834 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6835 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6836 vcpu->arch.cr0 = sregs->cr0;
6837
6838 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6839 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6840 if (sregs->cr4 & X86_CR4_OSXSAVE)
6841 kvm_update_cpuid(vcpu);
6842
6843 idx = srcu_read_lock(&vcpu->kvm->srcu);
6844 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6845 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6846 mmu_reset_needed = 1;
6847 }
6848 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6849
6850 if (mmu_reset_needed)
6851 kvm_mmu_reset_context(vcpu);
6852
6853 max_bits = KVM_NR_INTERRUPTS;
6854 pending_vec = find_first_bit(
6855 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6856 if (pending_vec < max_bits) {
6857 kvm_queue_interrupt(vcpu, pending_vec, false);
6858 pr_debug("Set back pending irq %d\n", pending_vec);
6859 }
6860
6861 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6862 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6863 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6864 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6865 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6866 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6867
6868 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6869 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6870
6871 update_cr8_intercept(vcpu);
6872
6873 /* Older userspace won't unhalt the vcpu on reset. */
6874 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6875 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6876 !is_protmode(vcpu))
6877 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6878
6879 kvm_make_request(KVM_REQ_EVENT, vcpu);
6880
6881 return 0;
6882 }
6883
6884 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6885 struct kvm_guest_debug *dbg)
6886 {
6887 unsigned long rflags;
6888 int i, r;
6889
6890 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6891 r = -EBUSY;
6892 if (vcpu->arch.exception.pending)
6893 goto out;
6894 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6895 kvm_queue_exception(vcpu, DB_VECTOR);
6896 else
6897 kvm_queue_exception(vcpu, BP_VECTOR);
6898 }
6899
6900 /*
6901 * Read rflags as long as potentially injected trace flags are still
6902 * filtered out.
6903 */
6904 rflags = kvm_get_rflags(vcpu);
6905
6906 vcpu->guest_debug = dbg->control;
6907 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6908 vcpu->guest_debug = 0;
6909
6910 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6911 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6912 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6913 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6914 } else {
6915 for (i = 0; i < KVM_NR_DB_REGS; i++)
6916 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6917 }
6918 kvm_update_dr7(vcpu);
6919
6920 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6921 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6922 get_segment_base(vcpu, VCPU_SREG_CS);
6923
6924 /*
6925 * Trigger an rflags update that will inject or remove the trace
6926 * flags.
6927 */
6928 kvm_set_rflags(vcpu, rflags);
6929
6930 kvm_x86_ops->update_db_bp_intercept(vcpu);
6931
6932 r = 0;
6933
6934 out:
6935
6936 return r;
6937 }
6938
6939 /*
6940 * Translate a guest virtual address to a guest physical address.
6941 */
6942 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6943 struct kvm_translation *tr)
6944 {
6945 unsigned long vaddr = tr->linear_address;
6946 gpa_t gpa;
6947 int idx;
6948
6949 idx = srcu_read_lock(&vcpu->kvm->srcu);
6950 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6951 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6952 tr->physical_address = gpa;
6953 tr->valid = gpa != UNMAPPED_GVA;
6954 tr->writeable = 1;
6955 tr->usermode = 0;
6956
6957 return 0;
6958 }
6959
6960 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6961 {
6962 struct fxregs_state *fxsave =
6963 &vcpu->arch.guest_fpu.state.fxsave;
6964
6965 memcpy(fpu->fpr, fxsave->st_space, 128);
6966 fpu->fcw = fxsave->cwd;
6967 fpu->fsw = fxsave->swd;
6968 fpu->ftwx = fxsave->twd;
6969 fpu->last_opcode = fxsave->fop;
6970 fpu->last_ip = fxsave->rip;
6971 fpu->last_dp = fxsave->rdp;
6972 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6973
6974 return 0;
6975 }
6976
6977 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6978 {
6979 struct fxregs_state *fxsave =
6980 &vcpu->arch.guest_fpu.state.fxsave;
6981
6982 memcpy(fxsave->st_space, fpu->fpr, 128);
6983 fxsave->cwd = fpu->fcw;
6984 fxsave->swd = fpu->fsw;
6985 fxsave->twd = fpu->ftwx;
6986 fxsave->fop = fpu->last_opcode;
6987 fxsave->rip = fpu->last_ip;
6988 fxsave->rdp = fpu->last_dp;
6989 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6990
6991 return 0;
6992 }
6993
6994 static void fx_init(struct kvm_vcpu *vcpu)
6995 {
6996 fpstate_init(&vcpu->arch.guest_fpu.state);
6997 if (cpu_has_xsaves)
6998 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
6999 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7000
7001 /*
7002 * Ensure guest xcr0 is valid for loading
7003 */
7004 vcpu->arch.xcr0 = XSTATE_FP;
7005
7006 vcpu->arch.cr0 |= X86_CR0_ET;
7007 }
7008
7009 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7010 {
7011 if (vcpu->guest_fpu_loaded)
7012 return;
7013
7014 /*
7015 * Restore all possible states in the guest,
7016 * and assume host would use all available bits.
7017 * Guest xcr0 would be loaded later.
7018 */
7019 kvm_put_guest_xcr0(vcpu);
7020 vcpu->guest_fpu_loaded = 1;
7021 __kernel_fpu_begin();
7022 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7023 trace_kvm_fpu(1);
7024 }
7025
7026 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7027 {
7028 kvm_put_guest_xcr0(vcpu);
7029
7030 if (!vcpu->guest_fpu_loaded) {
7031 vcpu->fpu_counter = 0;
7032 return;
7033 }
7034
7035 vcpu->guest_fpu_loaded = 0;
7036 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7037 __kernel_fpu_end();
7038 ++vcpu->stat.fpu_reload;
7039 /*
7040 * If using eager FPU mode, or if the guest is a frequent user
7041 * of the FPU, just leave the FPU active for next time.
7042 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7043 * the FPU in bursts will revert to loading it on demand.
7044 */
7045 if (!vcpu->arch.eager_fpu) {
7046 if (++vcpu->fpu_counter < 5)
7047 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7048 }
7049 trace_kvm_fpu(0);
7050 }
7051
7052 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7053 {
7054 kvmclock_reset(vcpu);
7055
7056 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7057 kvm_x86_ops->vcpu_free(vcpu);
7058 }
7059
7060 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7061 unsigned int id)
7062 {
7063 struct kvm_vcpu *vcpu;
7064
7065 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7066 printk_once(KERN_WARNING
7067 "kvm: SMP vm created on host with unstable TSC; "
7068 "guest TSC will not be reliable\n");
7069
7070 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7071
7072 return vcpu;
7073 }
7074
7075 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7076 {
7077 int r;
7078
7079 kvm_vcpu_mtrr_init(vcpu);
7080 r = vcpu_load(vcpu);
7081 if (r)
7082 return r;
7083 kvm_vcpu_reset(vcpu, false);
7084 kvm_mmu_setup(vcpu);
7085 vcpu_put(vcpu);
7086 return r;
7087 }
7088
7089 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7090 {
7091 struct msr_data msr;
7092 struct kvm *kvm = vcpu->kvm;
7093
7094 if (vcpu_load(vcpu))
7095 return;
7096 msr.data = 0x0;
7097 msr.index = MSR_IA32_TSC;
7098 msr.host_initiated = true;
7099 kvm_write_tsc(vcpu, &msr);
7100 vcpu_put(vcpu);
7101
7102 if (!kvmclock_periodic_sync)
7103 return;
7104
7105 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7106 KVMCLOCK_SYNC_PERIOD);
7107 }
7108
7109 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7110 {
7111 int r;
7112 vcpu->arch.apf.msr_val = 0;
7113
7114 r = vcpu_load(vcpu);
7115 BUG_ON(r);
7116 kvm_mmu_unload(vcpu);
7117 vcpu_put(vcpu);
7118
7119 kvm_x86_ops->vcpu_free(vcpu);
7120 }
7121
7122 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7123 {
7124 vcpu->arch.hflags = 0;
7125
7126 atomic_set(&vcpu->arch.nmi_queued, 0);
7127 vcpu->arch.nmi_pending = 0;
7128 vcpu->arch.nmi_injected = false;
7129 kvm_clear_interrupt_queue(vcpu);
7130 kvm_clear_exception_queue(vcpu);
7131
7132 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7133 kvm_update_dr0123(vcpu);
7134 vcpu->arch.dr6 = DR6_INIT;
7135 kvm_update_dr6(vcpu);
7136 vcpu->arch.dr7 = DR7_FIXED_1;
7137 kvm_update_dr7(vcpu);
7138
7139 vcpu->arch.cr2 = 0;
7140
7141 kvm_make_request(KVM_REQ_EVENT, vcpu);
7142 vcpu->arch.apf.msr_val = 0;
7143 vcpu->arch.st.msr_val = 0;
7144
7145 kvmclock_reset(vcpu);
7146
7147 kvm_clear_async_pf_completion_queue(vcpu);
7148 kvm_async_pf_hash_reset(vcpu);
7149 vcpu->arch.apf.halted = false;
7150
7151 if (!init_event) {
7152 kvm_pmu_reset(vcpu);
7153 vcpu->arch.smbase = 0x30000;
7154 }
7155
7156 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7157 vcpu->arch.regs_avail = ~0;
7158 vcpu->arch.regs_dirty = ~0;
7159
7160 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7161 }
7162
7163 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7164 {
7165 struct kvm_segment cs;
7166
7167 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7168 cs.selector = vector << 8;
7169 cs.base = vector << 12;
7170 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7171 kvm_rip_write(vcpu, 0);
7172 }
7173
7174 int kvm_arch_hardware_enable(void)
7175 {
7176 struct kvm *kvm;
7177 struct kvm_vcpu *vcpu;
7178 int i;
7179 int ret;
7180 u64 local_tsc;
7181 u64 max_tsc = 0;
7182 bool stable, backwards_tsc = false;
7183
7184 kvm_shared_msr_cpu_online();
7185 ret = kvm_x86_ops->hardware_enable();
7186 if (ret != 0)
7187 return ret;
7188
7189 local_tsc = rdtsc();
7190 stable = !check_tsc_unstable();
7191 list_for_each_entry(kvm, &vm_list, vm_list) {
7192 kvm_for_each_vcpu(i, vcpu, kvm) {
7193 if (!stable && vcpu->cpu == smp_processor_id())
7194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7195 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7196 backwards_tsc = true;
7197 if (vcpu->arch.last_host_tsc > max_tsc)
7198 max_tsc = vcpu->arch.last_host_tsc;
7199 }
7200 }
7201 }
7202
7203 /*
7204 * Sometimes, even reliable TSCs go backwards. This happens on
7205 * platforms that reset TSC during suspend or hibernate actions, but
7206 * maintain synchronization. We must compensate. Fortunately, we can
7207 * detect that condition here, which happens early in CPU bringup,
7208 * before any KVM threads can be running. Unfortunately, we can't
7209 * bring the TSCs fully up to date with real time, as we aren't yet far
7210 * enough into CPU bringup that we know how much real time has actually
7211 * elapsed; our helper function, get_kernel_ns() will be using boot
7212 * variables that haven't been updated yet.
7213 *
7214 * So we simply find the maximum observed TSC above, then record the
7215 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7216 * the adjustment will be applied. Note that we accumulate
7217 * adjustments, in case multiple suspend cycles happen before some VCPU
7218 * gets a chance to run again. In the event that no KVM threads get a
7219 * chance to run, we will miss the entire elapsed period, as we'll have
7220 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7221 * loose cycle time. This isn't too big a deal, since the loss will be
7222 * uniform across all VCPUs (not to mention the scenario is extremely
7223 * unlikely). It is possible that a second hibernate recovery happens
7224 * much faster than a first, causing the observed TSC here to be
7225 * smaller; this would require additional padding adjustment, which is
7226 * why we set last_host_tsc to the local tsc observed here.
7227 *
7228 * N.B. - this code below runs only on platforms with reliable TSC,
7229 * as that is the only way backwards_tsc is set above. Also note
7230 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7231 * have the same delta_cyc adjustment applied if backwards_tsc
7232 * is detected. Note further, this adjustment is only done once,
7233 * as we reset last_host_tsc on all VCPUs to stop this from being
7234 * called multiple times (one for each physical CPU bringup).
7235 *
7236 * Platforms with unreliable TSCs don't have to deal with this, they
7237 * will be compensated by the logic in vcpu_load, which sets the TSC to
7238 * catchup mode. This will catchup all VCPUs to real time, but cannot
7239 * guarantee that they stay in perfect synchronization.
7240 */
7241 if (backwards_tsc) {
7242 u64 delta_cyc = max_tsc - local_tsc;
7243 backwards_tsc_observed = true;
7244 list_for_each_entry(kvm, &vm_list, vm_list) {
7245 kvm_for_each_vcpu(i, vcpu, kvm) {
7246 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7247 vcpu->arch.last_host_tsc = local_tsc;
7248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7249 }
7250
7251 /*
7252 * We have to disable TSC offset matching.. if you were
7253 * booting a VM while issuing an S4 host suspend....
7254 * you may have some problem. Solving this issue is
7255 * left as an exercise to the reader.
7256 */
7257 kvm->arch.last_tsc_nsec = 0;
7258 kvm->arch.last_tsc_write = 0;
7259 }
7260
7261 }
7262 return 0;
7263 }
7264
7265 void kvm_arch_hardware_disable(void)
7266 {
7267 kvm_x86_ops->hardware_disable();
7268 drop_user_return_notifiers();
7269 }
7270
7271 int kvm_arch_hardware_setup(void)
7272 {
7273 int r;
7274
7275 r = kvm_x86_ops->hardware_setup();
7276 if (r != 0)
7277 return r;
7278
7279 kvm_init_msr_list();
7280 return 0;
7281 }
7282
7283 void kvm_arch_hardware_unsetup(void)
7284 {
7285 kvm_x86_ops->hardware_unsetup();
7286 }
7287
7288 void kvm_arch_check_processor_compat(void *rtn)
7289 {
7290 kvm_x86_ops->check_processor_compatibility(rtn);
7291 }
7292
7293 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7294 {
7295 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7296 }
7297 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7298
7299 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7300 {
7301 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7302 }
7303
7304 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7305 {
7306 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7307 }
7308
7309 struct static_key kvm_no_apic_vcpu __read_mostly;
7310
7311 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7312 {
7313 struct page *page;
7314 struct kvm *kvm;
7315 int r;
7316
7317 BUG_ON(vcpu->kvm == NULL);
7318 kvm = vcpu->kvm;
7319
7320 vcpu->arch.pv.pv_unhalted = false;
7321 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7322 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7323 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7324 else
7325 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7326
7327 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7328 if (!page) {
7329 r = -ENOMEM;
7330 goto fail;
7331 }
7332 vcpu->arch.pio_data = page_address(page);
7333
7334 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7335
7336 r = kvm_mmu_create(vcpu);
7337 if (r < 0)
7338 goto fail_free_pio_data;
7339
7340 if (irqchip_in_kernel(kvm)) {
7341 r = kvm_create_lapic(vcpu);
7342 if (r < 0)
7343 goto fail_mmu_destroy;
7344 } else
7345 static_key_slow_inc(&kvm_no_apic_vcpu);
7346
7347 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7348 GFP_KERNEL);
7349 if (!vcpu->arch.mce_banks) {
7350 r = -ENOMEM;
7351 goto fail_free_lapic;
7352 }
7353 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7354
7355 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7356 r = -ENOMEM;
7357 goto fail_free_mce_banks;
7358 }
7359
7360 fx_init(vcpu);
7361
7362 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7363 vcpu->arch.pv_time_enabled = false;
7364
7365 vcpu->arch.guest_supported_xcr0 = 0;
7366 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7367
7368 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7369
7370 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7371
7372 kvm_async_pf_hash_reset(vcpu);
7373 kvm_pmu_init(vcpu);
7374
7375 return 0;
7376
7377 fail_free_mce_banks:
7378 kfree(vcpu->arch.mce_banks);
7379 fail_free_lapic:
7380 kvm_free_lapic(vcpu);
7381 fail_mmu_destroy:
7382 kvm_mmu_destroy(vcpu);
7383 fail_free_pio_data:
7384 free_page((unsigned long)vcpu->arch.pio_data);
7385 fail:
7386 return r;
7387 }
7388
7389 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7390 {
7391 int idx;
7392
7393 kvm_pmu_destroy(vcpu);
7394 kfree(vcpu->arch.mce_banks);
7395 kvm_free_lapic(vcpu);
7396 idx = srcu_read_lock(&vcpu->kvm->srcu);
7397 kvm_mmu_destroy(vcpu);
7398 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7399 free_page((unsigned long)vcpu->arch.pio_data);
7400 if (!irqchip_in_kernel(vcpu->kvm))
7401 static_key_slow_dec(&kvm_no_apic_vcpu);
7402 }
7403
7404 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7405 {
7406 kvm_x86_ops->sched_in(vcpu, cpu);
7407 }
7408
7409 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7410 {
7411 if (type)
7412 return -EINVAL;
7413
7414 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7415 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7416 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7417 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7418 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7419
7420 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7421 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7422 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7423 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7424 &kvm->arch.irq_sources_bitmap);
7425
7426 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7427 mutex_init(&kvm->arch.apic_map_lock);
7428 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7429
7430 pvclock_update_vm_gtod_copy(kvm);
7431
7432 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7433 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7434
7435 return 0;
7436 }
7437
7438 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7439 {
7440 int r;
7441 r = vcpu_load(vcpu);
7442 BUG_ON(r);
7443 kvm_mmu_unload(vcpu);
7444 vcpu_put(vcpu);
7445 }
7446
7447 static void kvm_free_vcpus(struct kvm *kvm)
7448 {
7449 unsigned int i;
7450 struct kvm_vcpu *vcpu;
7451
7452 /*
7453 * Unpin any mmu pages first.
7454 */
7455 kvm_for_each_vcpu(i, vcpu, kvm) {
7456 kvm_clear_async_pf_completion_queue(vcpu);
7457 kvm_unload_vcpu_mmu(vcpu);
7458 }
7459 kvm_for_each_vcpu(i, vcpu, kvm)
7460 kvm_arch_vcpu_free(vcpu);
7461
7462 mutex_lock(&kvm->lock);
7463 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7464 kvm->vcpus[i] = NULL;
7465
7466 atomic_set(&kvm->online_vcpus, 0);
7467 mutex_unlock(&kvm->lock);
7468 }
7469
7470 void kvm_arch_sync_events(struct kvm *kvm)
7471 {
7472 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7473 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7474 kvm_free_all_assigned_devices(kvm);
7475 kvm_free_pit(kvm);
7476 }
7477
7478 int __x86_set_memory_region(struct kvm *kvm,
7479 const struct kvm_userspace_memory_region *mem)
7480 {
7481 int i, r;
7482
7483 /* Called with kvm->slots_lock held. */
7484 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7485
7486 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7487 struct kvm_userspace_memory_region m = *mem;
7488
7489 m.slot |= i << 16;
7490 r = __kvm_set_memory_region(kvm, &m);
7491 if (r < 0)
7492 return r;
7493 }
7494
7495 return 0;
7496 }
7497 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7498
7499 int x86_set_memory_region(struct kvm *kvm,
7500 const struct kvm_userspace_memory_region *mem)
7501 {
7502 int r;
7503
7504 mutex_lock(&kvm->slots_lock);
7505 r = __x86_set_memory_region(kvm, mem);
7506 mutex_unlock(&kvm->slots_lock);
7507
7508 return r;
7509 }
7510 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7511
7512 void kvm_arch_destroy_vm(struct kvm *kvm)
7513 {
7514 if (current->mm == kvm->mm) {
7515 /*
7516 * Free memory regions allocated on behalf of userspace,
7517 * unless the the memory map has changed due to process exit
7518 * or fd copying.
7519 */
7520 struct kvm_userspace_memory_region mem;
7521 memset(&mem, 0, sizeof(mem));
7522 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7523 x86_set_memory_region(kvm, &mem);
7524
7525 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7526 x86_set_memory_region(kvm, &mem);
7527
7528 mem.slot = TSS_PRIVATE_MEMSLOT;
7529 x86_set_memory_region(kvm, &mem);
7530 }
7531 kvm_iommu_unmap_guest(kvm);
7532 kfree(kvm->arch.vpic);
7533 kfree(kvm->arch.vioapic);
7534 kvm_free_vcpus(kvm);
7535 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7536 }
7537
7538 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7539 struct kvm_memory_slot *dont)
7540 {
7541 int i;
7542
7543 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7544 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7545 kvfree(free->arch.rmap[i]);
7546 free->arch.rmap[i] = NULL;
7547 }
7548 if (i == 0)
7549 continue;
7550
7551 if (!dont || free->arch.lpage_info[i - 1] !=
7552 dont->arch.lpage_info[i - 1]) {
7553 kvfree(free->arch.lpage_info[i - 1]);
7554 free->arch.lpage_info[i - 1] = NULL;
7555 }
7556 }
7557 }
7558
7559 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7560 unsigned long npages)
7561 {
7562 int i;
7563
7564 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7565 unsigned long ugfn;
7566 int lpages;
7567 int level = i + 1;
7568
7569 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7570 slot->base_gfn, level) + 1;
7571
7572 slot->arch.rmap[i] =
7573 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7574 if (!slot->arch.rmap[i])
7575 goto out_free;
7576 if (i == 0)
7577 continue;
7578
7579 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7580 sizeof(*slot->arch.lpage_info[i - 1]));
7581 if (!slot->arch.lpage_info[i - 1])
7582 goto out_free;
7583
7584 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7585 slot->arch.lpage_info[i - 1][0].write_count = 1;
7586 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7587 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7588 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7589 /*
7590 * If the gfn and userspace address are not aligned wrt each
7591 * other, or if explicitly asked to, disable large page
7592 * support for this slot
7593 */
7594 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7595 !kvm_largepages_enabled()) {
7596 unsigned long j;
7597
7598 for (j = 0; j < lpages; ++j)
7599 slot->arch.lpage_info[i - 1][j].write_count = 1;
7600 }
7601 }
7602
7603 return 0;
7604
7605 out_free:
7606 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7607 kvfree(slot->arch.rmap[i]);
7608 slot->arch.rmap[i] = NULL;
7609 if (i == 0)
7610 continue;
7611
7612 kvfree(slot->arch.lpage_info[i - 1]);
7613 slot->arch.lpage_info[i - 1] = NULL;
7614 }
7615 return -ENOMEM;
7616 }
7617
7618 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7619 {
7620 /*
7621 * memslots->generation has been incremented.
7622 * mmio generation may have reached its maximum value.
7623 */
7624 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7625 }
7626
7627 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7628 struct kvm_memory_slot *memslot,
7629 const struct kvm_userspace_memory_region *mem,
7630 enum kvm_mr_change change)
7631 {
7632 /*
7633 * Only private memory slots need to be mapped here since
7634 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7635 */
7636 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7637 unsigned long userspace_addr;
7638
7639 /*
7640 * MAP_SHARED to prevent internal slot pages from being moved
7641 * by fork()/COW.
7642 */
7643 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7644 PROT_READ | PROT_WRITE,
7645 MAP_SHARED | MAP_ANONYMOUS, 0);
7646
7647 if (IS_ERR((void *)userspace_addr))
7648 return PTR_ERR((void *)userspace_addr);
7649
7650 memslot->userspace_addr = userspace_addr;
7651 }
7652
7653 return 0;
7654 }
7655
7656 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7657 struct kvm_memory_slot *new)
7658 {
7659 /* Still write protect RO slot */
7660 if (new->flags & KVM_MEM_READONLY) {
7661 kvm_mmu_slot_remove_write_access(kvm, new);
7662 return;
7663 }
7664
7665 /*
7666 * Call kvm_x86_ops dirty logging hooks when they are valid.
7667 *
7668 * kvm_x86_ops->slot_disable_log_dirty is called when:
7669 *
7670 * - KVM_MR_CREATE with dirty logging is disabled
7671 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7672 *
7673 * The reason is, in case of PML, we need to set D-bit for any slots
7674 * with dirty logging disabled in order to eliminate unnecessary GPA
7675 * logging in PML buffer (and potential PML buffer full VMEXT). This
7676 * guarantees leaving PML enabled during guest's lifetime won't have
7677 * any additonal overhead from PML when guest is running with dirty
7678 * logging disabled for memory slots.
7679 *
7680 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7681 * to dirty logging mode.
7682 *
7683 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7684 *
7685 * In case of write protect:
7686 *
7687 * Write protect all pages for dirty logging.
7688 *
7689 * All the sptes including the large sptes which point to this
7690 * slot are set to readonly. We can not create any new large
7691 * spte on this slot until the end of the logging.
7692 *
7693 * See the comments in fast_page_fault().
7694 */
7695 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7696 if (kvm_x86_ops->slot_enable_log_dirty)
7697 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7698 else
7699 kvm_mmu_slot_remove_write_access(kvm, new);
7700 } else {
7701 if (kvm_x86_ops->slot_disable_log_dirty)
7702 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7703 }
7704 }
7705
7706 void kvm_arch_commit_memory_region(struct kvm *kvm,
7707 const struct kvm_userspace_memory_region *mem,
7708 const struct kvm_memory_slot *old,
7709 const struct kvm_memory_slot *new,
7710 enum kvm_mr_change change)
7711 {
7712 int nr_mmu_pages = 0;
7713
7714 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7715 int ret;
7716
7717 ret = vm_munmap(old->userspace_addr,
7718 old->npages * PAGE_SIZE);
7719 if (ret < 0)
7720 printk(KERN_WARNING
7721 "kvm_vm_ioctl_set_memory_region: "
7722 "failed to munmap memory\n");
7723 }
7724
7725 if (!kvm->arch.n_requested_mmu_pages)
7726 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7727
7728 if (nr_mmu_pages)
7729 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7730
7731 /*
7732 * Dirty logging tracks sptes in 4k granularity, meaning that large
7733 * sptes have to be split. If live migration is successful, the guest
7734 * in the source machine will be destroyed and large sptes will be
7735 * created in the destination. However, if the guest continues to run
7736 * in the source machine (for example if live migration fails), small
7737 * sptes will remain around and cause bad performance.
7738 *
7739 * Scan sptes if dirty logging has been stopped, dropping those
7740 * which can be collapsed into a single large-page spte. Later
7741 * page faults will create the large-page sptes.
7742 */
7743 if ((change != KVM_MR_DELETE) &&
7744 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7745 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7746 kvm_mmu_zap_collapsible_sptes(kvm, new);
7747
7748 /*
7749 * Set up write protection and/or dirty logging for the new slot.
7750 *
7751 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7752 * been zapped so no dirty logging staff is needed for old slot. For
7753 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7754 * new and it's also covered when dealing with the new slot.
7755 *
7756 * FIXME: const-ify all uses of struct kvm_memory_slot.
7757 */
7758 if (change != KVM_MR_DELETE)
7759 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7760 }
7761
7762 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7763 {
7764 kvm_mmu_invalidate_zap_all_pages(kvm);
7765 }
7766
7767 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7768 struct kvm_memory_slot *slot)
7769 {
7770 kvm_mmu_invalidate_zap_all_pages(kvm);
7771 }
7772
7773 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7774 {
7775 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7776 kvm_x86_ops->check_nested_events(vcpu, false);
7777
7778 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7779 !vcpu->arch.apf.halted)
7780 || !list_empty_careful(&vcpu->async_pf.done)
7781 || kvm_apic_has_events(vcpu)
7782 || vcpu->arch.pv.pv_unhalted
7783 || atomic_read(&vcpu->arch.nmi_queued) ||
7784 (kvm_arch_interrupt_allowed(vcpu) &&
7785 kvm_cpu_has_interrupt(vcpu));
7786 }
7787
7788 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7789 {
7790 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7791 }
7792
7793 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7794 {
7795 return kvm_x86_ops->interrupt_allowed(vcpu);
7796 }
7797
7798 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7799 {
7800 if (is_64_bit_mode(vcpu))
7801 return kvm_rip_read(vcpu);
7802 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7803 kvm_rip_read(vcpu));
7804 }
7805 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7806
7807 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7808 {
7809 return kvm_get_linear_rip(vcpu) == linear_rip;
7810 }
7811 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7812
7813 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7814 {
7815 unsigned long rflags;
7816
7817 rflags = kvm_x86_ops->get_rflags(vcpu);
7818 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7819 rflags &= ~X86_EFLAGS_TF;
7820 return rflags;
7821 }
7822 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7823
7824 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7825 {
7826 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7827 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7828 rflags |= X86_EFLAGS_TF;
7829 kvm_x86_ops->set_rflags(vcpu, rflags);
7830 }
7831
7832 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7833 {
7834 __kvm_set_rflags(vcpu, rflags);
7835 kvm_make_request(KVM_REQ_EVENT, vcpu);
7836 }
7837 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7838
7839 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7840 {
7841 int r;
7842
7843 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7844 work->wakeup_all)
7845 return;
7846
7847 r = kvm_mmu_reload(vcpu);
7848 if (unlikely(r))
7849 return;
7850
7851 if (!vcpu->arch.mmu.direct_map &&
7852 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7853 return;
7854
7855 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7856 }
7857
7858 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7859 {
7860 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7861 }
7862
7863 static inline u32 kvm_async_pf_next_probe(u32 key)
7864 {
7865 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7866 }
7867
7868 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7869 {
7870 u32 key = kvm_async_pf_hash_fn(gfn);
7871
7872 while (vcpu->arch.apf.gfns[key] != ~0)
7873 key = kvm_async_pf_next_probe(key);
7874
7875 vcpu->arch.apf.gfns[key] = gfn;
7876 }
7877
7878 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7879 {
7880 int i;
7881 u32 key = kvm_async_pf_hash_fn(gfn);
7882
7883 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7884 (vcpu->arch.apf.gfns[key] != gfn &&
7885 vcpu->arch.apf.gfns[key] != ~0); i++)
7886 key = kvm_async_pf_next_probe(key);
7887
7888 return key;
7889 }
7890
7891 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7892 {
7893 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7894 }
7895
7896 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7897 {
7898 u32 i, j, k;
7899
7900 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7901 while (true) {
7902 vcpu->arch.apf.gfns[i] = ~0;
7903 do {
7904 j = kvm_async_pf_next_probe(j);
7905 if (vcpu->arch.apf.gfns[j] == ~0)
7906 return;
7907 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7908 /*
7909 * k lies cyclically in ]i,j]
7910 * | i.k.j |
7911 * |....j i.k.| or |.k..j i...|
7912 */
7913 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7914 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7915 i = j;
7916 }
7917 }
7918
7919 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7920 {
7921
7922 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7923 sizeof(val));
7924 }
7925
7926 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7927 struct kvm_async_pf *work)
7928 {
7929 struct x86_exception fault;
7930
7931 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7932 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7933
7934 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7935 (vcpu->arch.apf.send_user_only &&
7936 kvm_x86_ops->get_cpl(vcpu) == 0))
7937 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7938 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7939 fault.vector = PF_VECTOR;
7940 fault.error_code_valid = true;
7941 fault.error_code = 0;
7942 fault.nested_page_fault = false;
7943 fault.address = work->arch.token;
7944 kvm_inject_page_fault(vcpu, &fault);
7945 }
7946 }
7947
7948 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7949 struct kvm_async_pf *work)
7950 {
7951 struct x86_exception fault;
7952
7953 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7954 if (work->wakeup_all)
7955 work->arch.token = ~0; /* broadcast wakeup */
7956 else
7957 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7958
7959 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7960 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7961 fault.vector = PF_VECTOR;
7962 fault.error_code_valid = true;
7963 fault.error_code = 0;
7964 fault.nested_page_fault = false;
7965 fault.address = work->arch.token;
7966 kvm_inject_page_fault(vcpu, &fault);
7967 }
7968 vcpu->arch.apf.halted = false;
7969 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7970 }
7971
7972 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7973 {
7974 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7975 return true;
7976 else
7977 return !kvm_event_needs_reinjection(vcpu) &&
7978 kvm_x86_ops->interrupt_allowed(vcpu);
7979 }
7980
7981 void kvm_arch_start_assignment(struct kvm *kvm)
7982 {
7983 atomic_inc(&kvm->arch.assigned_device_count);
7984 }
7985 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
7986
7987 void kvm_arch_end_assignment(struct kvm *kvm)
7988 {
7989 atomic_dec(&kvm->arch.assigned_device_count);
7990 }
7991 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
7992
7993 bool kvm_arch_has_assigned_device(struct kvm *kvm)
7994 {
7995 return atomic_read(&kvm->arch.assigned_device_count);
7996 }
7997 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
7998
7999 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8000 {
8001 atomic_inc(&kvm->arch.noncoherent_dma_count);
8002 }
8003 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8004
8005 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8006 {
8007 atomic_dec(&kvm->arch.noncoherent_dma_count);
8008 }
8009 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8010
8011 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8012 {
8013 return atomic_read(&kvm->arch.noncoherent_dma_count);
8014 }
8015 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8016
8017 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8019 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8020 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8027 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8028 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8029 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8030 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
This page took 0.199233 seconds and 6 git commands to generate.