projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: x86: remove unused last_kernel_ns variable
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 return;
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256 return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261 {
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
280 }
281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
283 asmlinkage void kvm_spurious_fault(void)
284 {
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287 }
288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
290 #define EXCPT_BENIGN 0
291 #define EXCPT_CONTRIBUTORY 1
292 #define EXCPT_PF 2
293
294 static int exception_class(int vector)
295 {
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309 }
310
311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
314 {
315 u32 prev_nr;
316 int class1, class2;
317
318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
326 vcpu->arch.exception.reinject = reinject;
327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351 }
352
353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354 {
355 kvm_multiple_exception(vcpu, nr, false, 0, false);
356 }
357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360 {
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362 }
363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
366 {
367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371 }
372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
373
374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
375 {
376 ++vcpu->stat.pf_guest;
377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
379 }
380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
381
382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
383 {
384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
386 else
387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
388 }
389
390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391 {
392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
394 }
395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398 {
399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404 {
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
409 /*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
414 {
415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
419 }
420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
421
422 /*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430 {
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442 }
443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447 {
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450 }
451
452 /*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
456 {
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
462
463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
471 if (is_present_gpte(pdpte[i]) &&
472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
484 out:
485
486 return ret;
487 }
488 EXPORT_SYMBOL_GPL(load_pdptrs);
489
490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491 {
492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
493 bool changed = true;
494 int offset;
495 gfn_t gfn;
496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
509 if (r < 0)
510 goto out;
511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
512 out:
513
514 return changed;
515 }
516
517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
518 {
519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
523 cr0 |= X86_CR0_ET;
524
525 #ifdef CONFIG_X86_64
526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
528 #endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
531
532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
534
535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539 #ifdef CONFIG_X86_64
540 if ((vcpu->arch.efer & EFER_LME)) {
541 int cs_db, cs_l;
542
543 if (!is_pae(vcpu))
544 return 1;
545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
546 if (cs_l)
547 return 1;
548 } else
549 #endif
550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
551 kvm_read_cr3(vcpu)))
552 return 1;
553 }
554
555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
558 kvm_x86_ops->set_cr0(vcpu, cr0);
559
560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
561 kvm_clear_async_pf_completion_queue(vcpu);
562 kvm_async_pf_hash_reset(vcpu);
563 }
564
565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
567 return 0;
568 }
569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
570
571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
572 {
573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
574 }
575 EXPORT_SYMBOL_GPL(kvm_lmsw);
576
577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578 {
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585 }
586
587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588 {
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594 }
595
596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597 {
598 u64 xcr0;
599 u64 valid_bits;
600
601 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
602 if (index != XCR_XFEATURE_ENABLED_MASK)
603 return 1;
604 xcr0 = xcr;
605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
617 return 1;
618
619 kvm_put_guest_xcr0(vcpu);
620 vcpu->arch.xcr0 = xcr0;
621 return 0;
622 }
623
624 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
625 {
626 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
627 __kvm_set_xcr(vcpu, index, xcr)) {
628 kvm_inject_gp(vcpu, 0);
629 return 1;
630 }
631 return 0;
632 }
633 EXPORT_SYMBOL_GPL(kvm_set_xcr);
634
635 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
636 {
637 unsigned long old_cr4 = kvm_read_cr4(vcpu);
638 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
639 X86_CR4_PAE | X86_CR4_SMEP;
640 if (cr4 & CR4_RESERVED_BITS)
641 return 1;
642
643 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
644 return 1;
645
646 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
647 return 1;
648
649 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
650 return 1;
651
652 if (is_long_mode(vcpu)) {
653 if (!(cr4 & X86_CR4_PAE))
654 return 1;
655 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
656 && ((cr4 ^ old_cr4) & pdptr_bits)
657 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
658 kvm_read_cr3(vcpu)))
659 return 1;
660
661 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
662 if (!guest_cpuid_has_pcid(vcpu))
663 return 1;
664
665 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
666 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
667 return 1;
668 }
669
670 if (kvm_x86_ops->set_cr4(vcpu, cr4))
671 return 1;
672
673 if (((cr4 ^ old_cr4) & pdptr_bits) ||
674 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
675 kvm_mmu_reset_context(vcpu);
676
677 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
678 kvm_update_cpuid(vcpu);
679
680 return 0;
681 }
682 EXPORT_SYMBOL_GPL(kvm_set_cr4);
683
684 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
685 {
686 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
687 kvm_mmu_sync_roots(vcpu);
688 kvm_mmu_flush_tlb(vcpu);
689 return 0;
690 }
691
692 if (is_long_mode(vcpu)) {
693 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
694 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
695 return 1;
696 } else
697 if (cr3 & CR3_L_MODE_RESERVED_BITS)
698 return 1;
699 } else {
700 if (is_pae(vcpu)) {
701 if (cr3 & CR3_PAE_RESERVED_BITS)
702 return 1;
703 if (is_paging(vcpu) &&
704 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
705 return 1;
706 }
707 /*
708 * We don't check reserved bits in nonpae mode, because
709 * this isn't enforced, and VMware depends on this.
710 */
711 }
712
713 vcpu->arch.cr3 = cr3;
714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
715 kvm_mmu_new_cr3(vcpu);
716 return 0;
717 }
718 EXPORT_SYMBOL_GPL(kvm_set_cr3);
719
720 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
721 {
722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
727 vcpu->arch.cr8 = cr8;
728 return 0;
729 }
730 EXPORT_SYMBOL_GPL(kvm_set_cr8);
731
732 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
733 {
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
737 return vcpu->arch.cr8;
738 }
739 EXPORT_SYMBOL_GPL(kvm_get_cr8);
740
741 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742 {
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745 }
746
747 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748 {
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
756 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
757 }
758
759 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
760 {
761 switch (dr) {
762 case 0 ... 3:
763 vcpu->arch.db[dr] = val;
764 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
765 vcpu->arch.eff_db[dr] = val;
766 break;
767 case 4:
768 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
769 return 1; /* #UD */
770 /* fall through */
771 case 6:
772 if (val & 0xffffffff00000000ULL)
773 return -1; /* #GP */
774 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
775 kvm_update_dr6(vcpu);
776 break;
777 case 5:
778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
779 return 1; /* #UD */
780 /* fall through */
781 default: /* 7 */
782 if (val & 0xffffffff00000000ULL)
783 return -1; /* #GP */
784 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
785 kvm_update_dr7(vcpu);
786 break;
787 }
788
789 return 0;
790 }
791
792 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
793 {
794 int res;
795
796 res = __kvm_set_dr(vcpu, dr, val);
797 if (res > 0)
798 kvm_queue_exception(vcpu, UD_VECTOR);
799 else if (res < 0)
800 kvm_inject_gp(vcpu, 0);
801
802 return res;
803 }
804 EXPORT_SYMBOL_GPL(kvm_set_dr);
805
806 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
807 {
808 switch (dr) {
809 case 0 ... 3:
810 *val = vcpu->arch.db[dr];
811 break;
812 case 4:
813 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
814 return 1;
815 /* fall through */
816 case 6:
817 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
818 *val = vcpu->arch.dr6;
819 else
820 *val = kvm_x86_ops->get_dr6(vcpu);
821 break;
822 case 5:
823 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
824 return 1;
825 /* fall through */
826 default: /* 7 */
827 *val = vcpu->arch.dr7;
828 break;
829 }
830
831 return 0;
832 }
833
834 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
835 {
836 if (_kvm_get_dr(vcpu, dr, val)) {
837 kvm_queue_exception(vcpu, UD_VECTOR);
838 return 1;
839 }
840 return 0;
841 }
842 EXPORT_SYMBOL_GPL(kvm_get_dr);
843
844 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
845 {
846 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
847 u64 data;
848 int err;
849
850 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
851 if (err)
852 return err;
853 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
854 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
855 return err;
856 }
857 EXPORT_SYMBOL_GPL(kvm_rdpmc);
858
859 /*
860 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
861 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
862 *
863 * This list is modified at module load time to reflect the
864 * capabilities of the host cpu. This capabilities test skips MSRs that are
865 * kvm-specific. Those are put in the beginning of the list.
866 */
867
868 #define KVM_SAVE_MSRS_BEGIN 12
869 static u32 msrs_to_save[] = {
870 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
871 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
872 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
873 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
874 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
875 MSR_KVM_PV_EOI_EN,
876 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
877 MSR_STAR,
878 #ifdef CONFIG_X86_64
879 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
880 #endif
881 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
882 MSR_IA32_FEATURE_CONTROL
883 };
884
885 static unsigned num_msrs_to_save;
886
887 static const u32 emulated_msrs[] = {
888 MSR_IA32_TSC_ADJUST,
889 MSR_IA32_TSCDEADLINE,
890 MSR_IA32_MISC_ENABLE,
891 MSR_IA32_MCG_STATUS,
892 MSR_IA32_MCG_CTL,
893 };
894
895 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
896 {
897 if (efer & efer_reserved_bits)
898 return false;
899
900 if (efer & EFER_FFXSR) {
901 struct kvm_cpuid_entry2 *feat;
902
903 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
904 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
905 return false;
906 }
907
908 if (efer & EFER_SVME) {
909 struct kvm_cpuid_entry2 *feat;
910
911 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
912 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
913 return false;
914 }
915
916 return true;
917 }
918 EXPORT_SYMBOL_GPL(kvm_valid_efer);
919
920 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
921 {
922 u64 old_efer = vcpu->arch.efer;
923
924 if (!kvm_valid_efer(vcpu, efer))
925 return 1;
926
927 if (is_paging(vcpu)
928 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
929 return 1;
930
931 efer &= ~EFER_LMA;
932 efer |= vcpu->arch.efer & EFER_LMA;
933
934 kvm_x86_ops->set_efer(vcpu, efer);
935
936 /* Update reserved bits */
937 if ((efer ^ old_efer) & EFER_NX)
938 kvm_mmu_reset_context(vcpu);
939
940 return 0;
941 }
942
943 void kvm_enable_efer_bits(u64 mask)
944 {
945 efer_reserved_bits &= ~mask;
946 }
947 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
948
949
950 /*
951 * Writes msr value into into the appropriate "register".
952 * Returns 0 on success, non-0 otherwise.
953 * Assumes vcpu_load() was already called.
954 */
955 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
956 {
957 return kvm_x86_ops->set_msr(vcpu, msr);
958 }
959
960 /*
961 * Adapt set_msr() to msr_io()'s calling convention
962 */
963 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
964 {
965 struct msr_data msr;
966
967 msr.data = *data;
968 msr.index = index;
969 msr.host_initiated = true;
970 return kvm_set_msr(vcpu, &msr);
971 }
972
973 #ifdef CONFIG_X86_64
974 struct pvclock_gtod_data {
975 seqcount_t seq;
976
977 struct { /* extract of a clocksource struct */
978 int vclock_mode;
979 cycle_t cycle_last;
980 cycle_t mask;
981 u32 mult;
982 u32 shift;
983 } clock;
984
985 /* open coded 'struct timespec' */
986 u64 monotonic_time_snsec;
987 time_t monotonic_time_sec;
988 };
989
990 static struct pvclock_gtod_data pvclock_gtod_data;
991
992 static void update_pvclock_gtod(struct timekeeper *tk)
993 {
994 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
995
996 write_seqcount_begin(&vdata->seq);
997
998 /* copy pvclock gtod data */
999 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1000 vdata->clock.cycle_last = tk->clock->cycle_last;
1001 vdata->clock.mask = tk->clock->mask;
1002 vdata->clock.mult = tk->mult;
1003 vdata->clock.shift = tk->shift;
1004
1005 vdata->monotonic_time_sec = tk->xtime_sec
1006 + tk->wall_to_monotonic.tv_sec;
1007 vdata->monotonic_time_snsec = tk->xtime_nsec
1008 + (tk->wall_to_monotonic.tv_nsec
1009 << tk->shift);
1010 while (vdata->monotonic_time_snsec >=
1011 (((u64)NSEC_PER_SEC) << tk->shift)) {
1012 vdata->monotonic_time_snsec -=
1013 ((u64)NSEC_PER_SEC) << tk->shift;
1014 vdata->monotonic_time_sec++;
1015 }
1016
1017 write_seqcount_end(&vdata->seq);
1018 }
1019 #endif
1020
1021
1022 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1023 {
1024 int version;
1025 int r;
1026 struct pvclock_wall_clock wc;
1027 struct timespec boot;
1028
1029 if (!wall_clock)
1030 return;
1031
1032 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1033 if (r)
1034 return;
1035
1036 if (version & 1)
1037 ++version; /* first time write, random junk */
1038
1039 ++version;
1040
1041 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1042
1043 /*
1044 * The guest calculates current wall clock time by adding
1045 * system time (updated by kvm_guest_time_update below) to the
1046 * wall clock specified here. guest system time equals host
1047 * system time for us, thus we must fill in host boot time here.
1048 */
1049 getboottime(&boot);
1050
1051 if (kvm->arch.kvmclock_offset) {
1052 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1053 boot = timespec_sub(boot, ts);
1054 }
1055 wc.sec = boot.tv_sec;
1056 wc.nsec = boot.tv_nsec;
1057 wc.version = version;
1058
1059 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1060
1061 version++;
1062 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1063 }
1064
1065 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1066 {
1067 uint32_t quotient, remainder;
1068
1069 /* Don't try to replace with do_div(), this one calculates
1070 * "(dividend << 32) / divisor" */
1071 __asm__ ( "divl %4"
1072 : "=a" (quotient), "=d" (remainder)
1073 : "0" (0), "1" (dividend), "r" (divisor) );
1074 return quotient;
1075 }
1076
1077 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1078 s8 *pshift, u32 *pmultiplier)
1079 {
1080 uint64_t scaled64;
1081 int32_t shift = 0;
1082 uint64_t tps64;
1083 uint32_t tps32;
1084
1085 tps64 = base_khz * 1000LL;
1086 scaled64 = scaled_khz * 1000LL;
1087 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1088 tps64 >>= 1;
1089 shift--;
1090 }
1091
1092 tps32 = (uint32_t)tps64;
1093 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1094 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1095 scaled64 >>= 1;
1096 else
1097 tps32 <<= 1;
1098 shift++;
1099 }
1100
1101 *pshift = shift;
1102 *pmultiplier = div_frac(scaled64, tps32);
1103
1104 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1105 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1106 }
1107
1108 static inline u64 get_kernel_ns(void)
1109 {
1110 struct timespec ts;
1111
1112 WARN_ON(preemptible());
1113 ktime_get_ts(&ts);
1114 monotonic_to_bootbased(&ts);
1115 return timespec_to_ns(&ts);
1116 }
1117
1118 #ifdef CONFIG_X86_64
1119 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1120 #endif
1121
1122 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1123 unsigned long max_tsc_khz;
1124
1125 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1126 {
1127 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1128 vcpu->arch.virtual_tsc_shift);
1129 }
1130
1131 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1132 {
1133 u64 v = (u64)khz * (1000000 + ppm);
1134 do_div(v, 1000000);
1135 return v;
1136 }
1137
1138 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1139 {
1140 u32 thresh_lo, thresh_hi;
1141 int use_scaling = 0;
1142
1143 /* tsc_khz can be zero if TSC calibration fails */
1144 if (this_tsc_khz == 0)
1145 return;
1146
1147 /* Compute a scale to convert nanoseconds in TSC cycles */
1148 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1149 &vcpu->arch.virtual_tsc_shift,
1150 &vcpu->arch.virtual_tsc_mult);
1151 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1152
1153 /*
1154 * Compute the variation in TSC rate which is acceptable
1155 * within the range of tolerance and decide if the
1156 * rate being applied is within that bounds of the hardware
1157 * rate. If so, no scaling or compensation need be done.
1158 */
1159 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1160 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1161 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1162 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1163 use_scaling = 1;
1164 }
1165 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1166 }
1167
1168 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1169 {
1170 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1171 vcpu->arch.virtual_tsc_mult,
1172 vcpu->arch.virtual_tsc_shift);
1173 tsc += vcpu->arch.this_tsc_write;
1174 return tsc;
1175 }
1176
1177 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1178 {
1179 #ifdef CONFIG_X86_64
1180 bool vcpus_matched;
1181 bool do_request = false;
1182 struct kvm_arch *ka = &vcpu->kvm->arch;
1183 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1184
1185 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1186 atomic_read(&vcpu->kvm->online_vcpus));
1187
1188 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1189 if (!ka->use_master_clock)
1190 do_request = 1;
1191
1192 if (!vcpus_matched && ka->use_master_clock)
1193 do_request = 1;
1194
1195 if (do_request)
1196 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1197
1198 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1199 atomic_read(&vcpu->kvm->online_vcpus),
1200 ka->use_master_clock, gtod->clock.vclock_mode);
1201 #endif
1202 }
1203
1204 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1205 {
1206 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1207 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1208 }
1209
1210 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1211 {
1212 struct kvm *kvm = vcpu->kvm;
1213 u64 offset, ns, elapsed;
1214 unsigned long flags;
1215 s64 usdiff;
1216 bool matched;
1217 u64 data = msr->data;
1218
1219 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1220 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1221 ns = get_kernel_ns();
1222 elapsed = ns - kvm->arch.last_tsc_nsec;
1223
1224 if (vcpu->arch.virtual_tsc_khz) {
1225 int faulted = 0;
1226
1227 /* n.b - signed multiplication and division required */
1228 usdiff = data - kvm->arch.last_tsc_write;
1229 #ifdef CONFIG_X86_64
1230 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1231 #else
1232 /* do_div() only does unsigned */
1233 asm("1: idivl %[divisor]\n"
1234 "2: xor %%edx, %%edx\n"
1235 " movl $0, %[faulted]\n"
1236 "3:\n"
1237 ".section .fixup,\"ax\"\n"
1238 "4: movl $1, %[faulted]\n"
1239 " jmp 3b\n"
1240 ".previous\n"
1241
1242 _ASM_EXTABLE(1b, 4b)
1243
1244 : "=A"(usdiff), [faulted] "=r" (faulted)
1245 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1246
1247 #endif
1248 do_div(elapsed, 1000);
1249 usdiff -= elapsed;
1250 if (usdiff < 0)
1251 usdiff = -usdiff;
1252
1253 /* idivl overflow => difference is larger than USEC_PER_SEC */
1254 if (faulted)
1255 usdiff = USEC_PER_SEC;
1256 } else
1257 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1258
1259 /*
1260 * Special case: TSC write with a small delta (1 second) of virtual
1261 * cycle time against real time is interpreted as an attempt to
1262 * synchronize the CPU.
1263 *
1264 * For a reliable TSC, we can match TSC offsets, and for an unstable
1265 * TSC, we add elapsed time in this computation. We could let the
1266 * compensation code attempt to catch up if we fall behind, but
1267 * it's better to try to match offsets from the beginning.
1268 */
1269 if (usdiff < USEC_PER_SEC &&
1270 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1271 if (!check_tsc_unstable()) {
1272 offset = kvm->arch.cur_tsc_offset;
1273 pr_debug("kvm: matched tsc offset for %llu\n", data);
1274 } else {
1275 u64 delta = nsec_to_cycles(vcpu, elapsed);
1276 data += delta;
1277 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1278 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1279 }
1280 matched = true;
1281 } else {
1282 /*
1283 * We split periods of matched TSC writes into generations.
1284 * For each generation, we track the original measured
1285 * nanosecond time, offset, and write, so if TSCs are in
1286 * sync, we can match exact offset, and if not, we can match
1287 * exact software computation in compute_guest_tsc()
1288 *
1289 * These values are tracked in kvm->arch.cur_xxx variables.
1290 */
1291 kvm->arch.cur_tsc_generation++;
1292 kvm->arch.cur_tsc_nsec = ns;
1293 kvm->arch.cur_tsc_write = data;
1294 kvm->arch.cur_tsc_offset = offset;
1295 matched = false;
1296 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1297 kvm->arch.cur_tsc_generation, data);
1298 }
1299
1300 /*
1301 * We also track th most recent recorded KHZ, write and time to
1302 * allow the matching interval to be extended at each write.
1303 */
1304 kvm->arch.last_tsc_nsec = ns;
1305 kvm->arch.last_tsc_write = data;
1306 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1307
1308 vcpu->arch.last_guest_tsc = data;
1309
1310 /* Keep track of which generation this VCPU has synchronized to */
1311 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1312 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1313 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1314
1315 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1316 update_ia32_tsc_adjust_msr(vcpu, offset);
1317 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1318 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1319
1320 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1321 if (matched)
1322 kvm->arch.nr_vcpus_matched_tsc++;
1323 else
1324 kvm->arch.nr_vcpus_matched_tsc = 0;
1325
1326 kvm_track_tsc_matching(vcpu);
1327 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1328 }
1329
1330 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1331
1332 #ifdef CONFIG_X86_64
1333
1334 static cycle_t read_tsc(void)
1335 {
1336 cycle_t ret;
1337 u64 last;
1338
1339 /*
1340 * Empirically, a fence (of type that depends on the CPU)
1341 * before rdtsc is enough to ensure that rdtsc is ordered
1342 * with respect to loads. The various CPU manuals are unclear
1343 * as to whether rdtsc can be reordered with later loads,
1344 * but no one has ever seen it happen.
1345 */
1346 rdtsc_barrier();
1347 ret = (cycle_t)vget_cycles();
1348
1349 last = pvclock_gtod_data.clock.cycle_last;
1350
1351 if (likely(ret >= last))
1352 return ret;
1353
1354 /*
1355 * GCC likes to generate cmov here, but this branch is extremely
1356 * predictable (it's just a funciton of time and the likely is
1357 * very likely) and there's a data dependence, so force GCC
1358 * to generate a branch instead. I don't barrier() because
1359 * we don't actually need a barrier, and if this function
1360 * ever gets inlined it will generate worse code.
1361 */
1362 asm volatile ("");
1363 return last;
1364 }
1365
1366 static inline u64 vgettsc(cycle_t *cycle_now)
1367 {
1368 long v;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1370
1371 *cycle_now = read_tsc();
1372
1373 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1374 return v * gtod->clock.mult;
1375 }
1376
1377 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1378 {
1379 unsigned long seq;
1380 u64 ns;
1381 int mode;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 ts->tv_nsec = 0;
1385 do {
1386 seq = read_seqcount_begin(&gtod->seq);
1387 mode = gtod->clock.vclock_mode;
1388 ts->tv_sec = gtod->monotonic_time_sec;
1389 ns = gtod->monotonic_time_snsec;
1390 ns += vgettsc(cycle_now);
1391 ns >>= gtod->clock.shift;
1392 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1393 timespec_add_ns(ts, ns);
1394
1395 return mode;
1396 }
1397
1398 /* returns true if host is using tsc clocksource */
1399 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1400 {
1401 struct timespec ts;
1402
1403 /* checked again under seqlock below */
1404 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1405 return false;
1406
1407 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1408 return false;
1409
1410 monotonic_to_bootbased(&ts);
1411 *kernel_ns = timespec_to_ns(&ts);
1412
1413 return true;
1414 }
1415 #endif
1416
1417 /*
1418 *
1419 * Assuming a stable TSC across physical CPUS, and a stable TSC
1420 * across virtual CPUs, the following condition is possible.
1421 * Each numbered line represents an event visible to both
1422 * CPUs at the next numbered event.
1423 *
1424 * "timespecX" represents host monotonic time. "tscX" represents
1425 * RDTSC value.
1426 *
1427 * VCPU0 on CPU0 | VCPU1 on CPU1
1428 *
1429 * 1. read timespec0,tsc0
1430 * 2. | timespec1 = timespec0 + N
1431 * | tsc1 = tsc0 + M
1432 * 3. transition to guest | transition to guest
1433 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1434 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1435 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1436 *
1437 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1438 *
1439 * - ret0 < ret1
1440 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1441 * ...
1442 * - 0 < N - M => M < N
1443 *
1444 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1445 * always the case (the difference between two distinct xtime instances
1446 * might be smaller then the difference between corresponding TSC reads,
1447 * when updating guest vcpus pvclock areas).
1448 *
1449 * To avoid that problem, do not allow visibility of distinct
1450 * system_timestamp/tsc_timestamp values simultaneously: use a master
1451 * copy of host monotonic time values. Update that master copy
1452 * in lockstep.
1453 *
1454 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1455 *
1456 */
1457
1458 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1459 {
1460 #ifdef CONFIG_X86_64
1461 struct kvm_arch *ka = &kvm->arch;
1462 int vclock_mode;
1463 bool host_tsc_clocksource, vcpus_matched;
1464
1465 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1466 atomic_read(&kvm->online_vcpus));
1467
1468 /*
1469 * If the host uses TSC clock, then passthrough TSC as stable
1470 * to the guest.
1471 */
1472 host_tsc_clocksource = kvm_get_time_and_clockread(
1473 &ka->master_kernel_ns,
1474 &ka->master_cycle_now);
1475
1476 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1477
1478 if (ka->use_master_clock)
1479 atomic_set(&kvm_guest_has_master_clock, 1);
1480
1481 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1482 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1483 vcpus_matched);
1484 #endif
1485 }
1486
1487 static void kvm_gen_update_masterclock(struct kvm *kvm)
1488 {
1489 #ifdef CONFIG_X86_64
1490 int i;
1491 struct kvm_vcpu *vcpu;
1492 struct kvm_arch *ka = &kvm->arch;
1493
1494 spin_lock(&ka->pvclock_gtod_sync_lock);
1495 kvm_make_mclock_inprogress_request(kvm);
1496 /* no guest entries from this point */
1497 pvclock_update_vm_gtod_copy(kvm);
1498
1499 kvm_for_each_vcpu(i, vcpu, kvm)
1500 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1501
1502 /* guest entries allowed */
1503 kvm_for_each_vcpu(i, vcpu, kvm)
1504 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1505
1506 spin_unlock(&ka->pvclock_gtod_sync_lock);
1507 #endif
1508 }
1509
1510 static int kvm_guest_time_update(struct kvm_vcpu *v)
1511 {
1512 unsigned long flags, this_tsc_khz;
1513 struct kvm_vcpu_arch *vcpu = &v->arch;
1514 struct kvm_arch *ka = &v->kvm->arch;
1515 s64 kernel_ns;
1516 u64 tsc_timestamp, host_tsc;
1517 struct pvclock_vcpu_time_info guest_hv_clock;
1518 u8 pvclock_flags;
1519 bool use_master_clock;
1520
1521 kernel_ns = 0;
1522 host_tsc = 0;
1523
1524 /*
1525 * If the host uses TSC clock, then passthrough TSC as stable
1526 * to the guest.
1527 */
1528 spin_lock(&ka->pvclock_gtod_sync_lock);
1529 use_master_clock = ka->use_master_clock;
1530 if (use_master_clock) {
1531 host_tsc = ka->master_cycle_now;
1532 kernel_ns = ka->master_kernel_ns;
1533 }
1534 spin_unlock(&ka->pvclock_gtod_sync_lock);
1535
1536 /* Keep irq disabled to prevent changes to the clock */
1537 local_irq_save(flags);
1538 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1539 if (unlikely(this_tsc_khz == 0)) {
1540 local_irq_restore(flags);
1541 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1542 return 1;
1543 }
1544 if (!use_master_clock) {
1545 host_tsc = native_read_tsc();
1546 kernel_ns = get_kernel_ns();
1547 }
1548
1549 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1550
1551 /*
1552 * We may have to catch up the TSC to match elapsed wall clock
1553 * time for two reasons, even if kvmclock is used.
1554 * 1) CPU could have been running below the maximum TSC rate
1555 * 2) Broken TSC compensation resets the base at each VCPU
1556 * entry to avoid unknown leaps of TSC even when running
1557 * again on the same CPU. This may cause apparent elapsed
1558 * time to disappear, and the guest to stand still or run
1559 * very slowly.
1560 */
1561 if (vcpu->tsc_catchup) {
1562 u64 tsc = compute_guest_tsc(v, kernel_ns);
1563 if (tsc > tsc_timestamp) {
1564 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1565 tsc_timestamp = tsc;
1566 }
1567 }
1568
1569 local_irq_restore(flags);
1570
1571 if (!vcpu->pv_time_enabled)
1572 return 0;
1573
1574 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1575 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1576 &vcpu->hv_clock.tsc_shift,
1577 &vcpu->hv_clock.tsc_to_system_mul);
1578 vcpu->hw_tsc_khz = this_tsc_khz;
1579 }
1580
1581 /* With all the info we got, fill in the values */
1582 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1583 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1584 vcpu->last_guest_tsc = tsc_timestamp;
1585
1586 /*
1587 * The interface expects us to write an even number signaling that the
1588 * update is finished. Since the guest won't see the intermediate
1589 * state, we just increase by 2 at the end.
1590 */
1591 vcpu->hv_clock.version += 2;
1592
1593 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1594 &guest_hv_clock, sizeof(guest_hv_clock))))
1595 return 0;
1596
1597 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1598 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1599
1600 if (vcpu->pvclock_set_guest_stopped_request) {
1601 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1602 vcpu->pvclock_set_guest_stopped_request = false;
1603 }
1604
1605 /* If the host uses TSC clocksource, then it is stable */
1606 if (use_master_clock)
1607 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1608
1609 vcpu->hv_clock.flags = pvclock_flags;
1610
1611 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1612 &vcpu->hv_clock,
1613 sizeof(vcpu->hv_clock));
1614 return 0;
1615 }
1616
1617 /*
1618 * kvmclock updates which are isolated to a given vcpu, such as
1619 * vcpu->cpu migration, should not allow system_timestamp from
1620 * the rest of the vcpus to remain static. Otherwise ntp frequency
1621 * correction applies to one vcpu's system_timestamp but not
1622 * the others.
1623 *
1624 * So in those cases, request a kvmclock update for all vcpus.
1625 * The worst case for a remote vcpu to update its kvmclock
1626 * is then bounded by maximum nohz sleep latency.
1627 */
1628
1629 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1630 {
1631 int i;
1632 struct kvm *kvm = v->kvm;
1633 struct kvm_vcpu *vcpu;
1634
1635 kvm_for_each_vcpu(i, vcpu, kvm) {
1636 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1637 kvm_vcpu_kick(vcpu);
1638 }
1639 }
1640
1641 static bool msr_mtrr_valid(unsigned msr)
1642 {
1643 switch (msr) {
1644 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1645 case MSR_MTRRfix64K_00000:
1646 case MSR_MTRRfix16K_80000:
1647 case MSR_MTRRfix16K_A0000:
1648 case MSR_MTRRfix4K_C0000:
1649 case MSR_MTRRfix4K_C8000:
1650 case MSR_MTRRfix4K_D0000:
1651 case MSR_MTRRfix4K_D8000:
1652 case MSR_MTRRfix4K_E0000:
1653 case MSR_MTRRfix4K_E8000:
1654 case MSR_MTRRfix4K_F0000:
1655 case MSR_MTRRfix4K_F8000:
1656 case MSR_MTRRdefType:
1657 case MSR_IA32_CR_PAT:
1658 return true;
1659 case 0x2f8:
1660 return true;
1661 }
1662 return false;
1663 }
1664
1665 static bool valid_pat_type(unsigned t)
1666 {
1667 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1668 }
1669
1670 static bool valid_mtrr_type(unsigned t)
1671 {
1672 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1673 }
1674
1675 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1676 {
1677 int i;
1678
1679 if (!msr_mtrr_valid(msr))
1680 return false;
1681
1682 if (msr == MSR_IA32_CR_PAT) {
1683 for (i = 0; i < 8; i++)
1684 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1685 return false;
1686 return true;
1687 } else if (msr == MSR_MTRRdefType) {
1688 if (data & ~0xcff)
1689 return false;
1690 return valid_mtrr_type(data & 0xff);
1691 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1692 for (i = 0; i < 8 ; i++)
1693 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1694 return false;
1695 return true;
1696 }
1697
1698 /* variable MTRRs */
1699 return valid_mtrr_type(data & 0xff);
1700 }
1701
1702 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1703 {
1704 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1705
1706 if (!mtrr_valid(vcpu, msr, data))
1707 return 1;
1708
1709 if (msr == MSR_MTRRdefType) {
1710 vcpu->arch.mtrr_state.def_type = data;
1711 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1712 } else if (msr == MSR_MTRRfix64K_00000)
1713 p[0] = data;
1714 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1715 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1716 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1717 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1718 else if (msr == MSR_IA32_CR_PAT)
1719 vcpu->arch.pat = data;
1720 else { /* Variable MTRRs */
1721 int idx, is_mtrr_mask;
1722 u64 *pt;
1723
1724 idx = (msr - 0x200) / 2;
1725 is_mtrr_mask = msr - 0x200 - 2 * idx;
1726 if (!is_mtrr_mask)
1727 pt =
1728 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1729 else
1730 pt =
1731 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1732 *pt = data;
1733 }
1734
1735 kvm_mmu_reset_context(vcpu);
1736 return 0;
1737 }
1738
1739 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1740 {
1741 u64 mcg_cap = vcpu->arch.mcg_cap;
1742 unsigned bank_num = mcg_cap & 0xff;
1743
1744 switch (msr) {
1745 case MSR_IA32_MCG_STATUS:
1746 vcpu->arch.mcg_status = data;
1747 break;
1748 case MSR_IA32_MCG_CTL:
1749 if (!(mcg_cap & MCG_CTL_P))
1750 return 1;
1751 if (data != 0 && data != ~(u64)0)
1752 return -1;
1753 vcpu->arch.mcg_ctl = data;
1754 break;
1755 default:
1756 if (msr >= MSR_IA32_MC0_CTL &&
1757 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1758 u32 offset = msr - MSR_IA32_MC0_CTL;
1759 /* only 0 or all 1s can be written to IA32_MCi_CTL
1760 * some Linux kernels though clear bit 10 in bank 4 to
1761 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1762 * this to avoid an uncatched #GP in the guest
1763 */
1764 if ((offset & 0x3) == 0 &&
1765 data != 0 && (data | (1 << 10)) != ~(u64)0)
1766 return -1;
1767 vcpu->arch.mce_banks[offset] = data;
1768 break;
1769 }
1770 return 1;
1771 }
1772 return 0;
1773 }
1774
1775 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1776 {
1777 struct kvm *kvm = vcpu->kvm;
1778 int lm = is_long_mode(vcpu);
1779 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1780 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1781 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1782 : kvm->arch.xen_hvm_config.blob_size_32;
1783 u32 page_num = data & ~PAGE_MASK;
1784 u64 page_addr = data & PAGE_MASK;
1785 u8 *page;
1786 int r;
1787
1788 r = -E2BIG;
1789 if (page_num >= blob_size)
1790 goto out;
1791 r = -ENOMEM;
1792 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1793 if (IS_ERR(page)) {
1794 r = PTR_ERR(page);
1795 goto out;
1796 }
1797 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1798 goto out_free;
1799 r = 0;
1800 out_free:
1801 kfree(page);
1802 out:
1803 return r;
1804 }
1805
1806 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1807 {
1808 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1809 }
1810
1811 static bool kvm_hv_msr_partition_wide(u32 msr)
1812 {
1813 bool r = false;
1814 switch (msr) {
1815 case HV_X64_MSR_GUEST_OS_ID:
1816 case HV_X64_MSR_HYPERCALL:
1817 case HV_X64_MSR_REFERENCE_TSC:
1818 case HV_X64_MSR_TIME_REF_COUNT:
1819 r = true;
1820 break;
1821 }
1822
1823 return r;
1824 }
1825
1826 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1827 {
1828 struct kvm *kvm = vcpu->kvm;
1829
1830 switch (msr) {
1831 case HV_X64_MSR_GUEST_OS_ID:
1832 kvm->arch.hv_guest_os_id = data;
1833 /* setting guest os id to zero disables hypercall page */
1834 if (!kvm->arch.hv_guest_os_id)
1835 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1836 break;
1837 case HV_X64_MSR_HYPERCALL: {
1838 u64 gfn;
1839 unsigned long addr;
1840 u8 instructions[4];
1841
1842 /* if guest os id is not set hypercall should remain disabled */
1843 if (!kvm->arch.hv_guest_os_id)
1844 break;
1845 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1846 kvm->arch.hv_hypercall = data;
1847 break;
1848 }
1849 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1850 addr = gfn_to_hva(kvm, gfn);
1851 if (kvm_is_error_hva(addr))
1852 return 1;
1853 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1854 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1855 if (__copy_to_user((void __user *)addr, instructions, 4))
1856 return 1;
1857 kvm->arch.hv_hypercall = data;
1858 mark_page_dirty(kvm, gfn);
1859 break;
1860 }
1861 case HV_X64_MSR_REFERENCE_TSC: {
1862 u64 gfn;
1863 HV_REFERENCE_TSC_PAGE tsc_ref;
1864 memset(&tsc_ref, 0, sizeof(tsc_ref));
1865 kvm->arch.hv_tsc_page = data;
1866 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1867 break;
1868 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1869 if (kvm_write_guest(kvm, data,
1870 &tsc_ref, sizeof(tsc_ref)))
1871 return 1;
1872 mark_page_dirty(kvm, gfn);
1873 break;
1874 }
1875 default:
1876 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1877 "data 0x%llx\n", msr, data);
1878 return 1;
1879 }
1880 return 0;
1881 }
1882
1883 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1884 {
1885 switch (msr) {
1886 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1887 u64 gfn;
1888 unsigned long addr;
1889
1890 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1891 vcpu->arch.hv_vapic = data;
1892 break;
1893 }
1894 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1895 addr = gfn_to_hva(vcpu->kvm, gfn);
1896 if (kvm_is_error_hva(addr))
1897 return 1;
1898 if (__clear_user((void __user *)addr, PAGE_SIZE))
1899 return 1;
1900 vcpu->arch.hv_vapic = data;
1901 mark_page_dirty(vcpu->kvm, gfn);
1902 break;
1903 }
1904 case HV_X64_MSR_EOI:
1905 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1906 case HV_X64_MSR_ICR:
1907 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1908 case HV_X64_MSR_TPR:
1909 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1910 default:
1911 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1912 "data 0x%llx\n", msr, data);
1913 return 1;
1914 }
1915
1916 return 0;
1917 }
1918
1919 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1920 {
1921 gpa_t gpa = data & ~0x3f;
1922
1923 /* Bits 2:5 are reserved, Should be zero */
1924 if (data & 0x3c)
1925 return 1;
1926
1927 vcpu->arch.apf.msr_val = data;
1928
1929 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1930 kvm_clear_async_pf_completion_queue(vcpu);
1931 kvm_async_pf_hash_reset(vcpu);
1932 return 0;
1933 }
1934
1935 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1936 sizeof(u32)))
1937 return 1;
1938
1939 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1940 kvm_async_pf_wakeup_all(vcpu);
1941 return 0;
1942 }
1943
1944 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1945 {
1946 vcpu->arch.pv_time_enabled = false;
1947 }
1948
1949 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1950 {
1951 u64 delta;
1952
1953 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1954 return;
1955
1956 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1957 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1958 vcpu->arch.st.accum_steal = delta;
1959 }
1960
1961 static void record_steal_time(struct kvm_vcpu *vcpu)
1962 {
1963 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1964 return;
1965
1966 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1967 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1968 return;
1969
1970 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1971 vcpu->arch.st.steal.version += 2;
1972 vcpu->arch.st.accum_steal = 0;
1973
1974 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1975 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1976 }
1977
1978 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1979 {
1980 bool pr = false;
1981 u32 msr = msr_info->index;
1982 u64 data = msr_info->data;
1983
1984 switch (msr) {
1985 case MSR_AMD64_NB_CFG:
1986 case MSR_IA32_UCODE_REV:
1987 case MSR_IA32_UCODE_WRITE:
1988 case MSR_VM_HSAVE_PA:
1989 case MSR_AMD64_PATCH_LOADER:
1990 case MSR_AMD64_BU_CFG2:
1991 break;
1992
1993 case MSR_EFER:
1994 return set_efer(vcpu, data);
1995 case MSR_K7_HWCR:
1996 data &= ~(u64)0x40; /* ignore flush filter disable */
1997 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1998 data &= ~(u64)0x8; /* ignore TLB cache disable */
1999 if (data != 0) {
2000 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2001 data);
2002 return 1;
2003 }
2004 break;
2005 case MSR_FAM10H_MMIO_CONF_BASE:
2006 if (data != 0) {
2007 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2008 "0x%llx\n", data);
2009 return 1;
2010 }
2011 break;
2012 case MSR_IA32_DEBUGCTLMSR:
2013 if (!data) {
2014 /* We support the non-activated case already */
2015 break;
2016 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2017 /* Values other than LBR and BTF are vendor-specific,
2018 thus reserved and should throw a #GP */
2019 return 1;
2020 }
2021 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2022 __func__, data);
2023 break;
2024 case 0x200 ... 0x2ff:
2025 return set_msr_mtrr(vcpu, msr, data);
2026 case MSR_IA32_APICBASE:
2027 return kvm_set_apic_base(vcpu, msr_info);
2028 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2029 return kvm_x2apic_msr_write(vcpu, msr, data);
2030 case MSR_IA32_TSCDEADLINE:
2031 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2032 break;
2033 case MSR_IA32_TSC_ADJUST:
2034 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2035 if (!msr_info->host_initiated) {
2036 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2037 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2038 }
2039 vcpu->arch.ia32_tsc_adjust_msr = data;
2040 }
2041 break;
2042 case MSR_IA32_MISC_ENABLE:
2043 vcpu->arch.ia32_misc_enable_msr = data;
2044 break;
2045 case MSR_KVM_WALL_CLOCK_NEW:
2046 case MSR_KVM_WALL_CLOCK:
2047 vcpu->kvm->arch.wall_clock = data;
2048 kvm_write_wall_clock(vcpu->kvm, data);
2049 break;
2050 case MSR_KVM_SYSTEM_TIME_NEW:
2051 case MSR_KVM_SYSTEM_TIME: {
2052 u64 gpa_offset;
2053 kvmclock_reset(vcpu);
2054
2055 vcpu->arch.time = data;
2056 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2057
2058 /* we verify if the enable bit is set... */
2059 if (!(data & 1))
2060 break;
2061
2062 gpa_offset = data & ~(PAGE_MASK | 1);
2063
2064 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2065 &vcpu->arch.pv_time, data & ~1ULL,
2066 sizeof(struct pvclock_vcpu_time_info)))
2067 vcpu->arch.pv_time_enabled = false;
2068 else
2069 vcpu->arch.pv_time_enabled = true;
2070
2071 break;
2072 }
2073 case MSR_KVM_ASYNC_PF_EN:
2074 if (kvm_pv_enable_async_pf(vcpu, data))
2075 return 1;
2076 break;
2077 case MSR_KVM_STEAL_TIME:
2078
2079 if (unlikely(!sched_info_on()))
2080 return 1;
2081
2082 if (data & KVM_STEAL_RESERVED_MASK)
2083 return 1;
2084
2085 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2086 data & KVM_STEAL_VALID_BITS,
2087 sizeof(struct kvm_steal_time)))
2088 return 1;
2089
2090 vcpu->arch.st.msr_val = data;
2091
2092 if (!(data & KVM_MSR_ENABLED))
2093 break;
2094
2095 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2096
2097 preempt_disable();
2098 accumulate_steal_time(vcpu);
2099 preempt_enable();
2100
2101 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2102
2103 break;
2104 case MSR_KVM_PV_EOI_EN:
2105 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2106 return 1;
2107 break;
2108
2109 case MSR_IA32_MCG_CTL:
2110 case MSR_IA32_MCG_STATUS:
2111 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2112 return set_msr_mce(vcpu, msr, data);
2113
2114 /* Performance counters are not protected by a CPUID bit,
2115 * so we should check all of them in the generic path for the sake of
2116 * cross vendor migration.
2117 * Writing a zero into the event select MSRs disables them,
2118 * which we perfectly emulate ;-). Any other value should be at least
2119 * reported, some guests depend on them.
2120 */
2121 case MSR_K7_EVNTSEL0:
2122 case MSR_K7_EVNTSEL1:
2123 case MSR_K7_EVNTSEL2:
2124 case MSR_K7_EVNTSEL3:
2125 if (data != 0)
2126 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2127 "0x%x data 0x%llx\n", msr, data);
2128 break;
2129 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2130 * so we ignore writes to make it happy.
2131 */
2132 case MSR_K7_PERFCTR0:
2133 case MSR_K7_PERFCTR1:
2134 case MSR_K7_PERFCTR2:
2135 case MSR_K7_PERFCTR3:
2136 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2137 "0x%x data 0x%llx\n", msr, data);
2138 break;
2139 case MSR_P6_PERFCTR0:
2140 case MSR_P6_PERFCTR1:
2141 pr = true;
2142 case MSR_P6_EVNTSEL0:
2143 case MSR_P6_EVNTSEL1:
2144 if (kvm_pmu_msr(vcpu, msr))
2145 return kvm_pmu_set_msr(vcpu, msr_info);
2146
2147 if (pr || data != 0)
2148 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2149 "0x%x data 0x%llx\n", msr, data);
2150 break;
2151 case MSR_K7_CLK_CTL:
2152 /*
2153 * Ignore all writes to this no longer documented MSR.
2154 * Writes are only relevant for old K7 processors,
2155 * all pre-dating SVM, but a recommended workaround from
2156 * AMD for these chips. It is possible to specify the
2157 * affected processor models on the command line, hence
2158 * the need to ignore the workaround.
2159 */
2160 break;
2161 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2162 if (kvm_hv_msr_partition_wide(msr)) {
2163 int r;
2164 mutex_lock(&vcpu->kvm->lock);
2165 r = set_msr_hyperv_pw(vcpu, msr, data);
2166 mutex_unlock(&vcpu->kvm->lock);
2167 return r;
2168 } else
2169 return set_msr_hyperv(vcpu, msr, data);
2170 break;
2171 case MSR_IA32_BBL_CR_CTL3:
2172 /* Drop writes to this legacy MSR -- see rdmsr
2173 * counterpart for further detail.
2174 */
2175 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2176 break;
2177 case MSR_AMD64_OSVW_ID_LENGTH:
2178 if (!guest_cpuid_has_osvw(vcpu))
2179 return 1;
2180 vcpu->arch.osvw.length = data;
2181 break;
2182 case MSR_AMD64_OSVW_STATUS:
2183 if (!guest_cpuid_has_osvw(vcpu))
2184 return 1;
2185 vcpu->arch.osvw.status = data;
2186 break;
2187 default:
2188 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2189 return xen_hvm_config(vcpu, data);
2190 if (kvm_pmu_msr(vcpu, msr))
2191 return kvm_pmu_set_msr(vcpu, msr_info);
2192 if (!ignore_msrs) {
2193 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2194 msr, data);
2195 return 1;
2196 } else {
2197 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2198 msr, data);
2199 break;
2200 }
2201 }
2202 return 0;
2203 }
2204 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2205
2206
2207 /*
2208 * Reads an msr value (of 'msr_index') into 'pdata'.
2209 * Returns 0 on success, non-0 otherwise.
2210 * Assumes vcpu_load() was already called.
2211 */
2212 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2213 {
2214 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2215 }
2216
2217 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2218 {
2219 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2220
2221 if (!msr_mtrr_valid(msr))
2222 return 1;
2223
2224 if (msr == MSR_MTRRdefType)
2225 *pdata = vcpu->arch.mtrr_state.def_type +
2226 (vcpu->arch.mtrr_state.enabled << 10);
2227 else if (msr == MSR_MTRRfix64K_00000)
2228 *pdata = p[0];
2229 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2230 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2231 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2232 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2233 else if (msr == MSR_IA32_CR_PAT)
2234 *pdata = vcpu->arch.pat;
2235 else { /* Variable MTRRs */
2236 int idx, is_mtrr_mask;
2237 u64 *pt;
2238
2239 idx = (msr - 0x200) / 2;
2240 is_mtrr_mask = msr - 0x200 - 2 * idx;
2241 if (!is_mtrr_mask)
2242 pt =
2243 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2244 else
2245 pt =
2246 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2247 *pdata = *pt;
2248 }
2249
2250 return 0;
2251 }
2252
2253 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254 {
2255 u64 data;
2256 u64 mcg_cap = vcpu->arch.mcg_cap;
2257 unsigned bank_num = mcg_cap & 0xff;
2258
2259 switch (msr) {
2260 case MSR_IA32_P5_MC_ADDR:
2261 case MSR_IA32_P5_MC_TYPE:
2262 data = 0;
2263 break;
2264 case MSR_IA32_MCG_CAP:
2265 data = vcpu->arch.mcg_cap;
2266 break;
2267 case MSR_IA32_MCG_CTL:
2268 if (!(mcg_cap & MCG_CTL_P))
2269 return 1;
2270 data = vcpu->arch.mcg_ctl;
2271 break;
2272 case MSR_IA32_MCG_STATUS:
2273 data = vcpu->arch.mcg_status;
2274 break;
2275 default:
2276 if (msr >= MSR_IA32_MC0_CTL &&
2277 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2278 u32 offset = msr - MSR_IA32_MC0_CTL;
2279 data = vcpu->arch.mce_banks[offset];
2280 break;
2281 }
2282 return 1;
2283 }
2284 *pdata = data;
2285 return 0;
2286 }
2287
2288 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2289 {
2290 u64 data = 0;
2291 struct kvm *kvm = vcpu->kvm;
2292
2293 switch (msr) {
2294 case HV_X64_MSR_GUEST_OS_ID:
2295 data = kvm->arch.hv_guest_os_id;
2296 break;
2297 case HV_X64_MSR_HYPERCALL:
2298 data = kvm->arch.hv_hypercall;
2299 break;
2300 case HV_X64_MSR_TIME_REF_COUNT: {
2301 data =
2302 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2303 break;
2304 }
2305 case HV_X64_MSR_REFERENCE_TSC:
2306 data = kvm->arch.hv_tsc_page;
2307 break;
2308 default:
2309 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2310 return 1;
2311 }
2312
2313 *pdata = data;
2314 return 0;
2315 }
2316
2317 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2318 {
2319 u64 data = 0;
2320
2321 switch (msr) {
2322 case HV_X64_MSR_VP_INDEX: {
2323 int r;
2324 struct kvm_vcpu *v;
2325 kvm_for_each_vcpu(r, v, vcpu->kvm)
2326 if (v == vcpu)
2327 data = r;
2328 break;
2329 }
2330 case HV_X64_MSR_EOI:
2331 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2332 case HV_X64_MSR_ICR:
2333 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2334 case HV_X64_MSR_TPR:
2335 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2336 case HV_X64_MSR_APIC_ASSIST_PAGE:
2337 data = vcpu->arch.hv_vapic;
2338 break;
2339 default:
2340 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2341 return 1;
2342 }
2343 *pdata = data;
2344 return 0;
2345 }
2346
2347 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2348 {
2349 u64 data;
2350
2351 switch (msr) {
2352 case MSR_IA32_PLATFORM_ID:
2353 case MSR_IA32_EBL_CR_POWERON:
2354 case MSR_IA32_DEBUGCTLMSR:
2355 case MSR_IA32_LASTBRANCHFROMIP:
2356 case MSR_IA32_LASTBRANCHTOIP:
2357 case MSR_IA32_LASTINTFROMIP:
2358 case MSR_IA32_LASTINTTOIP:
2359 case MSR_K8_SYSCFG:
2360 case MSR_K7_HWCR:
2361 case MSR_VM_HSAVE_PA:
2362 case MSR_K7_EVNTSEL0:
2363 case MSR_K7_PERFCTR0:
2364 case MSR_K8_INT_PENDING_MSG:
2365 case MSR_AMD64_NB_CFG:
2366 case MSR_FAM10H_MMIO_CONF_BASE:
2367 case MSR_AMD64_BU_CFG2:
2368 data = 0;
2369 break;
2370 case MSR_P6_PERFCTR0:
2371 case MSR_P6_PERFCTR1:
2372 case MSR_P6_EVNTSEL0:
2373 case MSR_P6_EVNTSEL1:
2374 if (kvm_pmu_msr(vcpu, msr))
2375 return kvm_pmu_get_msr(vcpu, msr, pdata);
2376 data = 0;
2377 break;
2378 case MSR_IA32_UCODE_REV:
2379 data = 0x100000000ULL;
2380 break;
2381 case MSR_MTRRcap:
2382 data = 0x500 | KVM_NR_VAR_MTRR;
2383 break;
2384 case 0x200 ... 0x2ff:
2385 return get_msr_mtrr(vcpu, msr, pdata);
2386 case 0xcd: /* fsb frequency */
2387 data = 3;
2388 break;
2389 /*
2390 * MSR_EBC_FREQUENCY_ID
2391 * Conservative value valid for even the basic CPU models.
2392 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2393 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2394 * and 266MHz for model 3, or 4. Set Core Clock
2395 * Frequency to System Bus Frequency Ratio to 1 (bits
2396 * 31:24) even though these are only valid for CPU
2397 * models > 2, however guests may end up dividing or
2398 * multiplying by zero otherwise.
2399 */
2400 case MSR_EBC_FREQUENCY_ID:
2401 data = 1 << 24;
2402 break;
2403 case MSR_IA32_APICBASE:
2404 data = kvm_get_apic_base(vcpu);
2405 break;
2406 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2407 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2408 break;
2409 case MSR_IA32_TSCDEADLINE:
2410 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2411 break;
2412 case MSR_IA32_TSC_ADJUST:
2413 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2414 break;
2415 case MSR_IA32_MISC_ENABLE:
2416 data = vcpu->arch.ia32_misc_enable_msr;
2417 break;
2418 case MSR_IA32_PERF_STATUS:
2419 /* TSC increment by tick */
2420 data = 1000ULL;
2421 /* CPU multiplier */
2422 data |= (((uint64_t)4ULL) << 40);
2423 break;
2424 case MSR_EFER:
2425 data = vcpu->arch.efer;
2426 break;
2427 case MSR_KVM_WALL_CLOCK:
2428 case MSR_KVM_WALL_CLOCK_NEW:
2429 data = vcpu->kvm->arch.wall_clock;
2430 break;
2431 case MSR_KVM_SYSTEM_TIME:
2432 case MSR_KVM_SYSTEM_TIME_NEW:
2433 data = vcpu->arch.time;
2434 break;
2435 case MSR_KVM_ASYNC_PF_EN:
2436 data = vcpu->arch.apf.msr_val;
2437 break;
2438 case MSR_KVM_STEAL_TIME:
2439 data = vcpu->arch.st.msr_val;
2440 break;
2441 case MSR_KVM_PV_EOI_EN:
2442 data = vcpu->arch.pv_eoi.msr_val;
2443 break;
2444 case MSR_IA32_P5_MC_ADDR:
2445 case MSR_IA32_P5_MC_TYPE:
2446 case MSR_IA32_MCG_CAP:
2447 case MSR_IA32_MCG_CTL:
2448 case MSR_IA32_MCG_STATUS:
2449 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2450 return get_msr_mce(vcpu, msr, pdata);
2451 case MSR_K7_CLK_CTL:
2452 /*
2453 * Provide expected ramp-up count for K7. All other
2454 * are set to zero, indicating minimum divisors for
2455 * every field.
2456 *
2457 * This prevents guest kernels on AMD host with CPU
2458 * type 6, model 8 and higher from exploding due to
2459 * the rdmsr failing.
2460 */
2461 data = 0x20000000;
2462 break;
2463 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2464 if (kvm_hv_msr_partition_wide(msr)) {
2465 int r;
2466 mutex_lock(&vcpu->kvm->lock);
2467 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2468 mutex_unlock(&vcpu->kvm->lock);
2469 return r;
2470 } else
2471 return get_msr_hyperv(vcpu, msr, pdata);
2472 break;
2473 case MSR_IA32_BBL_CR_CTL3:
2474 /* This legacy MSR exists but isn't fully documented in current
2475 * silicon. It is however accessed by winxp in very narrow
2476 * scenarios where it sets bit #19, itself documented as
2477 * a "reserved" bit. Best effort attempt to source coherent
2478 * read data here should the balance of the register be
2479 * interpreted by the guest:
2480 *
2481 * L2 cache control register 3: 64GB range, 256KB size,
2482 * enabled, latency 0x1, configured
2483 */
2484 data = 0xbe702111;
2485 break;
2486 case MSR_AMD64_OSVW_ID_LENGTH:
2487 if (!guest_cpuid_has_osvw(vcpu))
2488 return 1;
2489 data = vcpu->arch.osvw.length;
2490 break;
2491 case MSR_AMD64_OSVW_STATUS:
2492 if (!guest_cpuid_has_osvw(vcpu))
2493 return 1;
2494 data = vcpu->arch.osvw.status;
2495 break;
2496 default:
2497 if (kvm_pmu_msr(vcpu, msr))
2498 return kvm_pmu_get_msr(vcpu, msr, pdata);
2499 if (!ignore_msrs) {
2500 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2501 return 1;
2502 } else {
2503 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2504 data = 0;
2505 }
2506 break;
2507 }
2508 *pdata = data;
2509 return 0;
2510 }
2511 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2512
2513 /*
2514 * Read or write a bunch of msrs. All parameters are kernel addresses.
2515 *
2516 * @return number of msrs set successfully.
2517 */
2518 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2519 struct kvm_msr_entry *entries,
2520 int (*do_msr)(struct kvm_vcpu *vcpu,
2521 unsigned index, u64 *data))
2522 {
2523 int i, idx;
2524
2525 idx = srcu_read_lock(&vcpu->kvm->srcu);
2526 for (i = 0; i < msrs->nmsrs; ++i)
2527 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2528 break;
2529 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2530
2531 return i;
2532 }
2533
2534 /*
2535 * Read or write a bunch of msrs. Parameters are user addresses.
2536 *
2537 * @return number of msrs set successfully.
2538 */
2539 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2540 int (*do_msr)(struct kvm_vcpu *vcpu,
2541 unsigned index, u64 *data),
2542 int writeback)
2543 {
2544 struct kvm_msrs msrs;
2545 struct kvm_msr_entry *entries;
2546 int r, n;
2547 unsigned size;
2548
2549 r = -EFAULT;
2550 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2551 goto out;
2552
2553 r = -E2BIG;
2554 if (msrs.nmsrs >= MAX_IO_MSRS)
2555 goto out;
2556
2557 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2558 entries = memdup_user(user_msrs->entries, size);
2559 if (IS_ERR(entries)) {
2560 r = PTR_ERR(entries);
2561 goto out;
2562 }
2563
2564 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2565 if (r < 0)
2566 goto out_free;
2567
2568 r = -EFAULT;
2569 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2570 goto out_free;
2571
2572 r = n;
2573
2574 out_free:
2575 kfree(entries);
2576 out:
2577 return r;
2578 }
2579
2580 int kvm_dev_ioctl_check_extension(long ext)
2581 {
2582 int r;
2583
2584 switch (ext) {
2585 case KVM_CAP_IRQCHIP:
2586 case KVM_CAP_HLT:
2587 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2588 case KVM_CAP_SET_TSS_ADDR:
2589 case KVM_CAP_EXT_CPUID:
2590 case KVM_CAP_EXT_EMUL_CPUID:
2591 case KVM_CAP_CLOCKSOURCE:
2592 case KVM_CAP_PIT:
2593 case KVM_CAP_NOP_IO_DELAY:
2594 case KVM_CAP_MP_STATE:
2595 case KVM_CAP_SYNC_MMU:
2596 case KVM_CAP_USER_NMI:
2597 case KVM_CAP_REINJECT_CONTROL:
2598 case KVM_CAP_IRQ_INJECT_STATUS:
2599 case KVM_CAP_IRQFD:
2600 case KVM_CAP_IOEVENTFD:
2601 case KVM_CAP_PIT2:
2602 case KVM_CAP_PIT_STATE2:
2603 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2604 case KVM_CAP_XEN_HVM:
2605 case KVM_CAP_ADJUST_CLOCK:
2606 case KVM_CAP_VCPU_EVENTS:
2607 case KVM_CAP_HYPERV:
2608 case KVM_CAP_HYPERV_VAPIC:
2609 case KVM_CAP_HYPERV_SPIN:
2610 case KVM_CAP_PCI_SEGMENT:
2611 case KVM_CAP_DEBUGREGS:
2612 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2613 case KVM_CAP_XSAVE:
2614 case KVM_CAP_ASYNC_PF:
2615 case KVM_CAP_GET_TSC_KHZ:
2616 case KVM_CAP_KVMCLOCK_CTRL:
2617 case KVM_CAP_READONLY_MEM:
2618 case KVM_CAP_HYPERV_TIME:
2619 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2620 case KVM_CAP_ASSIGN_DEV_IRQ:
2621 case KVM_CAP_PCI_2_3:
2622 #endif
2623 r = 1;
2624 break;
2625 case KVM_CAP_COALESCED_MMIO:
2626 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2627 break;
2628 case KVM_CAP_VAPIC:
2629 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2630 break;
2631 case KVM_CAP_NR_VCPUS:
2632 r = KVM_SOFT_MAX_VCPUS;
2633 break;
2634 case KVM_CAP_MAX_VCPUS:
2635 r = KVM_MAX_VCPUS;
2636 break;
2637 case KVM_CAP_NR_MEMSLOTS:
2638 r = KVM_USER_MEM_SLOTS;
2639 break;
2640 case KVM_CAP_PV_MMU: /* obsolete */
2641 r = 0;
2642 break;
2643 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2644 case KVM_CAP_IOMMU:
2645 r = iommu_present(&pci_bus_type);
2646 break;
2647 #endif
2648 case KVM_CAP_MCE:
2649 r = KVM_MAX_MCE_BANKS;
2650 break;
2651 case KVM_CAP_XCRS:
2652 r = cpu_has_xsave;
2653 break;
2654 case KVM_CAP_TSC_CONTROL:
2655 r = kvm_has_tsc_control;
2656 break;
2657 case KVM_CAP_TSC_DEADLINE_TIMER:
2658 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2659 break;
2660 default:
2661 r = 0;
2662 break;
2663 }
2664 return r;
2665
2666 }
2667
2668 long kvm_arch_dev_ioctl(struct file *filp,
2669 unsigned int ioctl, unsigned long arg)
2670 {
2671 void __user *argp = (void __user *)arg;
2672 long r;
2673
2674 switch (ioctl) {
2675 case KVM_GET_MSR_INDEX_LIST: {
2676 struct kvm_msr_list __user *user_msr_list = argp;
2677 struct kvm_msr_list msr_list;
2678 unsigned n;
2679
2680 r = -EFAULT;
2681 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2682 goto out;
2683 n = msr_list.nmsrs;
2684 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2685 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2686 goto out;
2687 r = -E2BIG;
2688 if (n < msr_list.nmsrs)
2689 goto out;
2690 r = -EFAULT;
2691 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2692 num_msrs_to_save * sizeof(u32)))
2693 goto out;
2694 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2695 &emulated_msrs,
2696 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2697 goto out;
2698 r = 0;
2699 break;
2700 }
2701 case KVM_GET_SUPPORTED_CPUID:
2702 case KVM_GET_EMULATED_CPUID: {
2703 struct kvm_cpuid2 __user *cpuid_arg = argp;
2704 struct kvm_cpuid2 cpuid;
2705
2706 r = -EFAULT;
2707 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2708 goto out;
2709
2710 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2711 ioctl);
2712 if (r)
2713 goto out;
2714
2715 r = -EFAULT;
2716 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2717 goto out;
2718 r = 0;
2719 break;
2720 }
2721 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2722 u64 mce_cap;
2723
2724 mce_cap = KVM_MCE_CAP_SUPPORTED;
2725 r = -EFAULT;
2726 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2727 goto out;
2728 r = 0;
2729 break;
2730 }
2731 default:
2732 r = -EINVAL;
2733 }
2734 out:
2735 return r;
2736 }
2737
2738 static void wbinvd_ipi(void *garbage)
2739 {
2740 wbinvd();
2741 }
2742
2743 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2744 {
2745 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2746 }
2747
2748 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2749 {
2750 /* Address WBINVD may be executed by guest */
2751 if (need_emulate_wbinvd(vcpu)) {
2752 if (kvm_x86_ops->has_wbinvd_exit())
2753 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2754 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2755 smp_call_function_single(vcpu->cpu,
2756 wbinvd_ipi, NULL, 1);
2757 }
2758
2759 kvm_x86_ops->vcpu_load(vcpu, cpu);
2760
2761 /* Apply any externally detected TSC adjustments (due to suspend) */
2762 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2763 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2764 vcpu->arch.tsc_offset_adjustment = 0;
2765 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2766 }
2767
2768 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2769 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2770 native_read_tsc() - vcpu->arch.last_host_tsc;
2771 if (tsc_delta < 0)
2772 mark_tsc_unstable("KVM discovered backwards TSC");
2773 if (check_tsc_unstable()) {
2774 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2775 vcpu->arch.last_guest_tsc);
2776 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2777 vcpu->arch.tsc_catchup = 1;
2778 }
2779 /*
2780 * On a host with synchronized TSC, there is no need to update
2781 * kvmclock on vcpu->cpu migration
2782 */
2783 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2784 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2785 if (vcpu->cpu != cpu)
2786 kvm_migrate_timers(vcpu);
2787 vcpu->cpu = cpu;
2788 }
2789
2790 accumulate_steal_time(vcpu);
2791 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2792 }
2793
2794 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2795 {
2796 kvm_x86_ops->vcpu_put(vcpu);
2797 kvm_put_guest_fpu(vcpu);
2798 vcpu->arch.last_host_tsc = native_read_tsc();
2799 }
2800
2801 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2802 struct kvm_lapic_state *s)
2803 {
2804 kvm_x86_ops->sync_pir_to_irr(vcpu);
2805 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2806
2807 return 0;
2808 }
2809
2810 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2811 struct kvm_lapic_state *s)
2812 {
2813 kvm_apic_post_state_restore(vcpu, s);
2814 update_cr8_intercept(vcpu);
2815
2816 return 0;
2817 }
2818
2819 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2820 struct kvm_interrupt *irq)
2821 {
2822 if (irq->irq >= KVM_NR_INTERRUPTS)
2823 return -EINVAL;
2824 if (irqchip_in_kernel(vcpu->kvm))
2825 return -ENXIO;
2826
2827 kvm_queue_interrupt(vcpu, irq->irq, false);
2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
2829
2830 return 0;
2831 }
2832
2833 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2834 {
2835 kvm_inject_nmi(vcpu);
2836
2837 return 0;
2838 }
2839
2840 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2841 struct kvm_tpr_access_ctl *tac)
2842 {
2843 if (tac->flags)
2844 return -EINVAL;
2845 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2846 return 0;
2847 }
2848
2849 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2850 u64 mcg_cap)
2851 {
2852 int r;
2853 unsigned bank_num = mcg_cap & 0xff, bank;
2854
2855 r = -EINVAL;
2856 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2857 goto out;
2858 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2859 goto out;
2860 r = 0;
2861 vcpu->arch.mcg_cap = mcg_cap;
2862 /* Init IA32_MCG_CTL to all 1s */
2863 if (mcg_cap & MCG_CTL_P)
2864 vcpu->arch.mcg_ctl = ~(u64)0;
2865 /* Init IA32_MCi_CTL to all 1s */
2866 for (bank = 0; bank < bank_num; bank++)
2867 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2868 out:
2869 return r;
2870 }
2871
2872 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2873 struct kvm_x86_mce *mce)
2874 {
2875 u64 mcg_cap = vcpu->arch.mcg_cap;
2876 unsigned bank_num = mcg_cap & 0xff;
2877 u64 *banks = vcpu->arch.mce_banks;
2878
2879 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2880 return -EINVAL;
2881 /*
2882 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2883 * reporting is disabled
2884 */
2885 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2886 vcpu->arch.mcg_ctl != ~(u64)0)
2887 return 0;
2888 banks += 4 * mce->bank;
2889 /*
2890 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2891 * reporting is disabled for the bank
2892 */
2893 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2894 return 0;
2895 if (mce->status & MCI_STATUS_UC) {
2896 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2897 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2898 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2899 return 0;
2900 }
2901 if (banks[1] & MCI_STATUS_VAL)
2902 mce->status |= MCI_STATUS_OVER;
2903 banks[2] = mce->addr;
2904 banks[3] = mce->misc;
2905 vcpu->arch.mcg_status = mce->mcg_status;
2906 banks[1] = mce->status;
2907 kvm_queue_exception(vcpu, MC_VECTOR);
2908 } else if (!(banks[1] & MCI_STATUS_VAL)
2909 || !(banks[1] & MCI_STATUS_UC)) {
2910 if (banks[1] & MCI_STATUS_VAL)
2911 mce->status |= MCI_STATUS_OVER;
2912 banks[2] = mce->addr;
2913 banks[3] = mce->misc;
2914 banks[1] = mce->status;
2915 } else
2916 banks[1] |= MCI_STATUS_OVER;
2917 return 0;
2918 }
2919
2920 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2921 struct kvm_vcpu_events *events)
2922 {
2923 process_nmi(vcpu);
2924 events->exception.injected =
2925 vcpu->arch.exception.pending &&
2926 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2927 events->exception.nr = vcpu->arch.exception.nr;
2928 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2929 events->exception.pad = 0;
2930 events->exception.error_code = vcpu->arch.exception.error_code;
2931
2932 events->interrupt.injected =
2933 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2934 events->interrupt.nr = vcpu->arch.interrupt.nr;
2935 events->interrupt.soft = 0;
2936 events->interrupt.shadow =
2937 kvm_x86_ops->get_interrupt_shadow(vcpu,
2938 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2939
2940 events->nmi.injected = vcpu->arch.nmi_injected;
2941 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2942 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2943 events->nmi.pad = 0;
2944
2945 events->sipi_vector = 0; /* never valid when reporting to user space */
2946
2947 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2948 | KVM_VCPUEVENT_VALID_SHADOW);
2949 memset(&events->reserved, 0, sizeof(events->reserved));
2950 }
2951
2952 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2953 struct kvm_vcpu_events *events)
2954 {
2955 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2956 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2957 | KVM_VCPUEVENT_VALID_SHADOW))
2958 return -EINVAL;
2959
2960 process_nmi(vcpu);
2961 vcpu->arch.exception.pending = events->exception.injected;
2962 vcpu->arch.exception.nr = events->exception.nr;
2963 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2964 vcpu->arch.exception.error_code = events->exception.error_code;
2965
2966 vcpu->arch.interrupt.pending = events->interrupt.injected;
2967 vcpu->arch.interrupt.nr = events->interrupt.nr;
2968 vcpu->arch.interrupt.soft = events->interrupt.soft;
2969 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2970 kvm_x86_ops->set_interrupt_shadow(vcpu,
2971 events->interrupt.shadow);
2972
2973 vcpu->arch.nmi_injected = events->nmi.injected;
2974 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2975 vcpu->arch.nmi_pending = events->nmi.pending;
2976 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2977
2978 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2979 kvm_vcpu_has_lapic(vcpu))
2980 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2981
2982 kvm_make_request(KVM_REQ_EVENT, vcpu);
2983
2984 return 0;
2985 }
2986
2987 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2988 struct kvm_debugregs *dbgregs)
2989 {
2990 unsigned long val;
2991
2992 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2993 _kvm_get_dr(vcpu, 6, &val);
2994 dbgregs->dr6 = val;
2995 dbgregs->dr7 = vcpu->arch.dr7;
2996 dbgregs->flags = 0;
2997 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2998 }
2999
3000 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3001 struct kvm_debugregs *dbgregs)
3002 {
3003 if (dbgregs->flags)
3004 return -EINVAL;
3005
3006 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3007 vcpu->arch.dr6 = dbgregs->dr6;
3008 kvm_update_dr6(vcpu);
3009 vcpu->arch.dr7 = dbgregs->dr7;
3010 kvm_update_dr7(vcpu);
3011
3012 return 0;
3013 }
3014
3015 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3016 struct kvm_xsave *guest_xsave)
3017 {
3018 if (cpu_has_xsave) {
3019 memcpy(guest_xsave->region,
3020 &vcpu->arch.guest_fpu.state->xsave,
3021 vcpu->arch.guest_xstate_size);
3022 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3023 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3024 } else {
3025 memcpy(guest_xsave->region,
3026 &vcpu->arch.guest_fpu.state->fxsave,
3027 sizeof(struct i387_fxsave_struct));
3028 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3029 XSTATE_FPSSE;
3030 }
3031 }
3032
3033 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3034 struct kvm_xsave *guest_xsave)
3035 {
3036 u64 xstate_bv =
3037 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3038
3039 if (cpu_has_xsave) {
3040 /*
3041 * Here we allow setting states that are not present in
3042 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3043 * with old userspace.
3044 */
3045 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3046 return -EINVAL;
3047 if (xstate_bv & ~host_xcr0)
3048 return -EINVAL;
3049 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3050 guest_xsave->region, vcpu->arch.guest_xstate_size);
3051 } else {
3052 if (xstate_bv & ~XSTATE_FPSSE)
3053 return -EINVAL;
3054 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3055 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3056 }
3057 return 0;
3058 }
3059
3060 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3061 struct kvm_xcrs *guest_xcrs)
3062 {
3063 if (!cpu_has_xsave) {
3064 guest_xcrs->nr_xcrs = 0;
3065 return;
3066 }
3067
3068 guest_xcrs->nr_xcrs = 1;
3069 guest_xcrs->flags = 0;
3070 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3071 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3072 }
3073
3074 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3075 struct kvm_xcrs *guest_xcrs)
3076 {
3077 int i, r = 0;
3078
3079 if (!cpu_has_xsave)
3080 return -EINVAL;
3081
3082 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3083 return -EINVAL;
3084
3085 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3086 /* Only support XCR0 currently */
3087 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3088 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3089 guest_xcrs->xcrs[i].value);
3090 break;
3091 }
3092 if (r)
3093 r = -EINVAL;
3094 return r;
3095 }
3096
3097 /*
3098 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3099 * stopped by the hypervisor. This function will be called from the host only.
3100 * EINVAL is returned when the host attempts to set the flag for a guest that
3101 * does not support pv clocks.
3102 */
3103 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3104 {
3105 if (!vcpu->arch.pv_time_enabled)
3106 return -EINVAL;
3107 vcpu->arch.pvclock_set_guest_stopped_request = true;
3108 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3109 return 0;
3110 }
3111
3112 long kvm_arch_vcpu_ioctl(struct file *filp,
3113 unsigned int ioctl, unsigned long arg)
3114 {
3115 struct kvm_vcpu *vcpu = filp->private_data;
3116 void __user *argp = (void __user *)arg;
3117 int r;
3118 union {
3119 struct kvm_lapic_state *lapic;
3120 struct kvm_xsave *xsave;
3121 struct kvm_xcrs *xcrs;
3122 void *buffer;
3123 } u;
3124
3125 u.buffer = NULL;
3126 switch (ioctl) {
3127 case KVM_GET_LAPIC: {
3128 r = -EINVAL;
3129 if (!vcpu->arch.apic)
3130 goto out;
3131 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3132
3133 r = -ENOMEM;
3134 if (!u.lapic)
3135 goto out;
3136 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3137 if (r)
3138 goto out;
3139 r = -EFAULT;
3140 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3141 goto out;
3142 r = 0;
3143 break;
3144 }
3145 case KVM_SET_LAPIC: {
3146 r = -EINVAL;
3147 if (!vcpu->arch.apic)
3148 goto out;
3149 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3150 if (IS_ERR(u.lapic))
3151 return PTR_ERR(u.lapic);
3152
3153 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3154 break;
3155 }
3156 case KVM_INTERRUPT: {
3157 struct kvm_interrupt irq;
3158
3159 r = -EFAULT;
3160 if (copy_from_user(&irq, argp, sizeof irq))
3161 goto out;
3162 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3163 break;
3164 }
3165 case KVM_NMI: {
3166 r = kvm_vcpu_ioctl_nmi(vcpu);
3167 break;
3168 }
3169 case KVM_SET_CPUID: {
3170 struct kvm_cpuid __user *cpuid_arg = argp;
3171 struct kvm_cpuid cpuid;
3172
3173 r = -EFAULT;
3174 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3175 goto out;
3176 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3177 break;
3178 }
3179 case KVM_SET_CPUID2: {
3180 struct kvm_cpuid2 __user *cpuid_arg = argp;
3181 struct kvm_cpuid2 cpuid;
3182
3183 r = -EFAULT;
3184 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3185 goto out;
3186 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3187 cpuid_arg->entries);
3188 break;
3189 }
3190 case KVM_GET_CPUID2: {
3191 struct kvm_cpuid2 __user *cpuid_arg = argp;
3192 struct kvm_cpuid2 cpuid;
3193
3194 r = -EFAULT;
3195 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3196 goto out;
3197 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3198 cpuid_arg->entries);
3199 if (r)
3200 goto out;
3201 r = -EFAULT;
3202 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3203 goto out;
3204 r = 0;
3205 break;
3206 }
3207 case KVM_GET_MSRS:
3208 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3209 break;
3210 case KVM_SET_MSRS:
3211 r = msr_io(vcpu, argp, do_set_msr, 0);
3212 break;
3213 case KVM_TPR_ACCESS_REPORTING: {
3214 struct kvm_tpr_access_ctl tac;
3215
3216 r = -EFAULT;
3217 if (copy_from_user(&tac, argp, sizeof tac))
3218 goto out;
3219 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3220 if (r)
3221 goto out;
3222 r = -EFAULT;
3223 if (copy_to_user(argp, &tac, sizeof tac))
3224 goto out;
3225 r = 0;
3226 break;
3227 };
3228 case KVM_SET_VAPIC_ADDR: {
3229 struct kvm_vapic_addr va;
3230
3231 r = -EINVAL;
3232 if (!irqchip_in_kernel(vcpu->kvm))
3233 goto out;
3234 r = -EFAULT;
3235 if (copy_from_user(&va, argp, sizeof va))
3236 goto out;
3237 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3238 break;
3239 }
3240 case KVM_X86_SETUP_MCE: {
3241 u64 mcg_cap;
3242
3243 r = -EFAULT;
3244 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3245 goto out;
3246 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3247 break;
3248 }
3249 case KVM_X86_SET_MCE: {
3250 struct kvm_x86_mce mce;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&mce, argp, sizeof mce))
3254 goto out;
3255 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3256 break;
3257 }
3258 case KVM_GET_VCPU_EVENTS: {
3259 struct kvm_vcpu_events events;
3260
3261 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3262
3263 r = -EFAULT;
3264 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3265 break;
3266 r = 0;
3267 break;
3268 }
3269 case KVM_SET_VCPU_EVENTS: {
3270 struct kvm_vcpu_events events;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3274 break;
3275
3276 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3277 break;
3278 }
3279 case KVM_GET_DEBUGREGS: {
3280 struct kvm_debugregs dbgregs;
3281
3282 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3283
3284 r = -EFAULT;
3285 if (copy_to_user(argp, &dbgregs,
3286 sizeof(struct kvm_debugregs)))
3287 break;
3288 r = 0;
3289 break;
3290 }
3291 case KVM_SET_DEBUGREGS: {
3292 struct kvm_debugregs dbgregs;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&dbgregs, argp,
3296 sizeof(struct kvm_debugregs)))
3297 break;
3298
3299 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3300 break;
3301 }
3302 case KVM_GET_XSAVE: {
3303 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3304 r = -ENOMEM;
3305 if (!u.xsave)
3306 break;
3307
3308 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3309
3310 r = -EFAULT;
3311 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3312 break;
3313 r = 0;
3314 break;
3315 }
3316 case KVM_SET_XSAVE: {
3317 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3318 if (IS_ERR(u.xsave))
3319 return PTR_ERR(u.xsave);
3320
3321 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3322 break;
3323 }
3324 case KVM_GET_XCRS: {
3325 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3326 r = -ENOMEM;
3327 if (!u.xcrs)
3328 break;
3329
3330 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3331
3332 r = -EFAULT;
3333 if (copy_to_user(argp, u.xcrs,
3334 sizeof(struct kvm_xcrs)))
3335 break;
3336 r = 0;
3337 break;
3338 }
3339 case KVM_SET_XCRS: {
3340 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3341 if (IS_ERR(u.xcrs))
3342 return PTR_ERR(u.xcrs);
3343
3344 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3345 break;
3346 }
3347 case KVM_SET_TSC_KHZ: {
3348 u32 user_tsc_khz;
3349
3350 r = -EINVAL;
3351 user_tsc_khz = (u32)arg;
3352
3353 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3354 goto out;
3355
3356 if (user_tsc_khz == 0)
3357 user_tsc_khz = tsc_khz;
3358
3359 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3360
3361 r = 0;
3362 goto out;
3363 }
3364 case KVM_GET_TSC_KHZ: {
3365 r = vcpu->arch.virtual_tsc_khz;
3366 goto out;
3367 }
3368 case KVM_KVMCLOCK_CTRL: {
3369 r = kvm_set_guest_paused(vcpu);
3370 goto out;
3371 }
3372 default:
3373 r = -EINVAL;
3374 }
3375 out:
3376 kfree(u.buffer);
3377 return r;
3378 }
3379
3380 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3381 {
3382 return VM_FAULT_SIGBUS;
3383 }
3384
3385 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3386 {
3387 int ret;
3388
3389 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3390 return -EINVAL;
3391 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3392 return ret;
3393 }
3394
3395 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3396 u64 ident_addr)
3397 {
3398 kvm->arch.ept_identity_map_addr = ident_addr;
3399 return 0;
3400 }
3401
3402 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3403 u32 kvm_nr_mmu_pages)
3404 {
3405 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3406 return -EINVAL;
3407
3408 mutex_lock(&kvm->slots_lock);
3409
3410 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3411 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3412
3413 mutex_unlock(&kvm->slots_lock);
3414 return 0;
3415 }
3416
3417 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3418 {
3419 return kvm->arch.n_max_mmu_pages;
3420 }
3421
3422 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3423 {
3424 int r;
3425
3426 r = 0;
3427 switch (chip->chip_id) {
3428 case KVM_IRQCHIP_PIC_MASTER:
3429 memcpy(&chip->chip.pic,
3430 &pic_irqchip(kvm)->pics[0],
3431 sizeof(struct kvm_pic_state));
3432 break;
3433 case KVM_IRQCHIP_PIC_SLAVE:
3434 memcpy(&chip->chip.pic,
3435 &pic_irqchip(kvm)->pics[1],
3436 sizeof(struct kvm_pic_state));
3437 break;
3438 case KVM_IRQCHIP_IOAPIC:
3439 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3440 break;
3441 default:
3442 r = -EINVAL;
3443 break;
3444 }
3445 return r;
3446 }
3447
3448 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3449 {
3450 int r;
3451
3452 r = 0;
3453 switch (chip->chip_id) {
3454 case KVM_IRQCHIP_PIC_MASTER:
3455 spin_lock(&pic_irqchip(kvm)->lock);
3456 memcpy(&pic_irqchip(kvm)->pics[0],
3457 &chip->chip.pic,
3458 sizeof(struct kvm_pic_state));
3459 spin_unlock(&pic_irqchip(kvm)->lock);
3460 break;
3461 case KVM_IRQCHIP_PIC_SLAVE:
3462 spin_lock(&pic_irqchip(kvm)->lock);
3463 memcpy(&pic_irqchip(kvm)->pics[1],
3464 &chip->chip.pic,
3465 sizeof(struct kvm_pic_state));
3466 spin_unlock(&pic_irqchip(kvm)->lock);
3467 break;
3468 case KVM_IRQCHIP_IOAPIC:
3469 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3470 break;
3471 default:
3472 r = -EINVAL;
3473 break;
3474 }
3475 kvm_pic_update_irq(pic_irqchip(kvm));
3476 return r;
3477 }
3478
3479 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3480 {
3481 int r = 0;
3482
3483 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3484 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3485 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3486 return r;
3487 }
3488
3489 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3490 {
3491 int r = 0;
3492
3493 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3494 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3495 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3497 return r;
3498 }
3499
3500 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3501 {
3502 int r = 0;
3503
3504 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3505 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3506 sizeof(ps->channels));
3507 ps->flags = kvm->arch.vpit->pit_state.flags;
3508 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3509 memset(&ps->reserved, 0, sizeof(ps->reserved));
3510 return r;
3511 }
3512
3513 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3514 {
3515 int r = 0, start = 0;
3516 u32 prev_legacy, cur_legacy;
3517 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3518 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3519 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3520 if (!prev_legacy && cur_legacy)
3521 start = 1;
3522 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3523 sizeof(kvm->arch.vpit->pit_state.channels));
3524 kvm->arch.vpit->pit_state.flags = ps->flags;
3525 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3526 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3527 return r;
3528 }
3529
3530 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3531 struct kvm_reinject_control *control)
3532 {
3533 if (!kvm->arch.vpit)
3534 return -ENXIO;
3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3536 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3537 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3538 return 0;
3539 }
3540
3541 /**
3542 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3543 * @kvm: kvm instance
3544 * @log: slot id and address to which we copy the log
3545 *
3546 * We need to keep it in mind that VCPU threads can write to the bitmap
3547 * concurrently. So, to avoid losing data, we keep the following order for
3548 * each bit:
3549 *
3550 * 1. Take a snapshot of the bit and clear it if needed.
3551 * 2. Write protect the corresponding page.
3552 * 3. Flush TLB's if needed.
3553 * 4. Copy the snapshot to the userspace.
3554 *
3555 * Between 2 and 3, the guest may write to the page using the remaining TLB
3556 * entry. This is not a problem because the page will be reported dirty at
3557 * step 4 using the snapshot taken before and step 3 ensures that successive
3558 * writes will be logged for the next call.
3559 */
3560 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3561 {
3562 int r;
3563 struct kvm_memory_slot *memslot;
3564 unsigned long n, i;
3565 unsigned long *dirty_bitmap;
3566 unsigned long *dirty_bitmap_buffer;
3567 bool is_dirty = false;
3568
3569 mutex_lock(&kvm->slots_lock);
3570
3571 r = -EINVAL;
3572 if (log->slot >= KVM_USER_MEM_SLOTS)
3573 goto out;
3574
3575 memslot = id_to_memslot(kvm->memslots, log->slot);
3576
3577 dirty_bitmap = memslot->dirty_bitmap;
3578 r = -ENOENT;
3579 if (!dirty_bitmap)
3580 goto out;
3581
3582 n = kvm_dirty_bitmap_bytes(memslot);
3583
3584 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3585 memset(dirty_bitmap_buffer, 0, n);
3586
3587 spin_lock(&kvm->mmu_lock);
3588
3589 for (i = 0; i < n / sizeof(long); i++) {
3590 unsigned long mask;
3591 gfn_t offset;
3592
3593 if (!dirty_bitmap[i])
3594 continue;
3595
3596 is_dirty = true;
3597
3598 mask = xchg(&dirty_bitmap[i], 0);
3599 dirty_bitmap_buffer[i] = mask;
3600
3601 offset = i * BITS_PER_LONG;
3602 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3603 }
3604 if (is_dirty)
3605 kvm_flush_remote_tlbs(kvm);
3606
3607 spin_unlock(&kvm->mmu_lock);
3608
3609 r = -EFAULT;
3610 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3611 goto out;
3612
3613 r = 0;
3614 out:
3615 mutex_unlock(&kvm->slots_lock);
3616 return r;
3617 }
3618
3619 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3620 bool line_status)
3621 {
3622 if (!irqchip_in_kernel(kvm))
3623 return -ENXIO;
3624
3625 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3626 irq_event->irq, irq_event->level,
3627 line_status);
3628 return 0;
3629 }
3630
3631 long kvm_arch_vm_ioctl(struct file *filp,
3632 unsigned int ioctl, unsigned long arg)
3633 {
3634 struct kvm *kvm = filp->private_data;
3635 void __user *argp = (void __user *)arg;
3636 int r = -ENOTTY;
3637 /*
3638 * This union makes it completely explicit to gcc-3.x
3639 * that these two variables' stack usage should be
3640 * combined, not added together.
3641 */
3642 union {
3643 struct kvm_pit_state ps;
3644 struct kvm_pit_state2 ps2;
3645 struct kvm_pit_config pit_config;
3646 } u;
3647
3648 switch (ioctl) {
3649 case KVM_SET_TSS_ADDR:
3650 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3651 break;
3652 case KVM_SET_IDENTITY_MAP_ADDR: {
3653 u64 ident_addr;
3654
3655 r = -EFAULT;
3656 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3657 goto out;
3658 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3659 break;
3660 }
3661 case KVM_SET_NR_MMU_PAGES:
3662 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3663 break;
3664 case KVM_GET_NR_MMU_PAGES:
3665 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3666 break;
3667 case KVM_CREATE_IRQCHIP: {
3668 struct kvm_pic *vpic;
3669
3670 mutex_lock(&kvm->lock);
3671 r = -EEXIST;
3672 if (kvm->arch.vpic)
3673 goto create_irqchip_unlock;
3674 r = -EINVAL;
3675 if (atomic_read(&kvm->online_vcpus))
3676 goto create_irqchip_unlock;
3677 r = -ENOMEM;
3678 vpic = kvm_create_pic(kvm);
3679 if (vpic) {
3680 r = kvm_ioapic_init(kvm);
3681 if (r) {
3682 mutex_lock(&kvm->slots_lock);
3683 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3684 &vpic->dev_master);
3685 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3686 &vpic->dev_slave);
3687 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3688 &vpic->dev_eclr);
3689 mutex_unlock(&kvm->slots_lock);
3690 kfree(vpic);
3691 goto create_irqchip_unlock;
3692 }
3693 } else
3694 goto create_irqchip_unlock;
3695 smp_wmb();
3696 kvm->arch.vpic = vpic;
3697 smp_wmb();
3698 r = kvm_setup_default_irq_routing(kvm);
3699 if (r) {
3700 mutex_lock(&kvm->slots_lock);
3701 mutex_lock(&kvm->irq_lock);
3702 kvm_ioapic_destroy(kvm);
3703 kvm_destroy_pic(kvm);
3704 mutex_unlock(&kvm->irq_lock);
3705 mutex_unlock(&kvm->slots_lock);
3706 }
3707 create_irqchip_unlock:
3708 mutex_unlock(&kvm->lock);
3709 break;
3710 }
3711 case KVM_CREATE_PIT:
3712 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3713 goto create_pit;
3714 case KVM_CREATE_PIT2:
3715 r = -EFAULT;
3716 if (copy_from_user(&u.pit_config, argp,
3717 sizeof(struct kvm_pit_config)))
3718 goto out;
3719 create_pit:
3720 mutex_lock(&kvm->slots_lock);
3721 r = -EEXIST;
3722 if (kvm->arch.vpit)
3723 goto create_pit_unlock;
3724 r = -ENOMEM;
3725 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3726 if (kvm->arch.vpit)
3727 r = 0;
3728 create_pit_unlock:
3729 mutex_unlock(&kvm->slots_lock);
3730 break;
3731 case KVM_GET_IRQCHIP: {
3732 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3733 struct kvm_irqchip *chip;
3734
3735 chip = memdup_user(argp, sizeof(*chip));
3736 if (IS_ERR(chip)) {
3737 r = PTR_ERR(chip);
3738 goto out;
3739 }
3740
3741 r = -ENXIO;
3742 if (!irqchip_in_kernel(kvm))
3743 goto get_irqchip_out;
3744 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3745 if (r)
3746 goto get_irqchip_out;
3747 r = -EFAULT;
3748 if (copy_to_user(argp, chip, sizeof *chip))
3749 goto get_irqchip_out;
3750 r = 0;
3751 get_irqchip_out:
3752 kfree(chip);
3753 break;
3754 }
3755 case KVM_SET_IRQCHIP: {
3756 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3757 struct kvm_irqchip *chip;
3758
3759 chip = memdup_user(argp, sizeof(*chip));
3760 if (IS_ERR(chip)) {
3761 r = PTR_ERR(chip);
3762 goto out;
3763 }
3764
3765 r = -ENXIO;
3766 if (!irqchip_in_kernel(kvm))
3767 goto set_irqchip_out;
3768 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3769 if (r)
3770 goto set_irqchip_out;
3771 r = 0;
3772 set_irqchip_out:
3773 kfree(chip);
3774 break;
3775 }
3776 case KVM_GET_PIT: {
3777 r = -EFAULT;
3778 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3779 goto out;
3780 r = -ENXIO;
3781 if (!kvm->arch.vpit)
3782 goto out;
3783 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3784 if (r)
3785 goto out;
3786 r = -EFAULT;
3787 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3788 goto out;
3789 r = 0;
3790 break;
3791 }
3792 case KVM_SET_PIT: {
3793 r = -EFAULT;
3794 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3795 goto out;
3796 r = -ENXIO;
3797 if (!kvm->arch.vpit)
3798 goto out;
3799 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3800 break;
3801 }
3802 case KVM_GET_PIT2: {
3803 r = -ENXIO;
3804 if (!kvm->arch.vpit)
3805 goto out;
3806 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3807 if (r)
3808 goto out;
3809 r = -EFAULT;
3810 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3811 goto out;
3812 r = 0;
3813 break;
3814 }
3815 case KVM_SET_PIT2: {
3816 r = -EFAULT;
3817 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3818 goto out;
3819 r = -ENXIO;
3820 if (!kvm->arch.vpit)
3821 goto out;
3822 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3823 break;
3824 }
3825 case KVM_REINJECT_CONTROL: {
3826 struct kvm_reinject_control control;
3827 r = -EFAULT;
3828 if (copy_from_user(&control, argp, sizeof(control)))
3829 goto out;
3830 r = kvm_vm_ioctl_reinject(kvm, &control);
3831 break;
3832 }
3833 case KVM_XEN_HVM_CONFIG: {
3834 r = -EFAULT;
3835 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3836 sizeof(struct kvm_xen_hvm_config)))
3837 goto out;
3838 r = -EINVAL;
3839 if (kvm->arch.xen_hvm_config.flags)
3840 goto out;
3841 r = 0;
3842 break;
3843 }
3844 case KVM_SET_CLOCK: {
3845 struct kvm_clock_data user_ns;
3846 u64 now_ns;
3847 s64 delta;
3848
3849 r = -EFAULT;
3850 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3851 goto out;
3852
3853 r = -EINVAL;
3854 if (user_ns.flags)
3855 goto out;
3856
3857 r = 0;
3858 local_irq_disable();
3859 now_ns = get_kernel_ns();
3860 delta = user_ns.clock - now_ns;
3861 local_irq_enable();
3862 kvm->arch.kvmclock_offset = delta;
3863 kvm_gen_update_masterclock(kvm);
3864 break;
3865 }
3866 case KVM_GET_CLOCK: {
3867 struct kvm_clock_data user_ns;
3868 u64 now_ns;
3869
3870 local_irq_disable();
3871 now_ns = get_kernel_ns();
3872 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3873 local_irq_enable();
3874 user_ns.flags = 0;
3875 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3876
3877 r = -EFAULT;
3878 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3879 goto out;
3880 r = 0;
3881 break;
3882 }
3883
3884 default:
3885 ;
3886 }
3887 out:
3888 return r;
3889 }
3890
3891 static void kvm_init_msr_list(void)
3892 {
3893 u32 dummy[2];
3894 unsigned i, j;
3895
3896 /* skip the first msrs in the list. KVM-specific */
3897 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3898 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3899 continue;
3900 if (j < i)
3901 msrs_to_save[j] = msrs_to_save[i];
3902 j++;
3903 }
3904 num_msrs_to_save = j;
3905 }
3906
3907 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3908 const void *v)
3909 {
3910 int handled = 0;
3911 int n;
3912
3913 do {
3914 n = min(len, 8);
3915 if (!(vcpu->arch.apic &&
3916 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3917 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3918 break;
3919 handled += n;
3920 addr += n;
3921 len -= n;
3922 v += n;
3923 } while (len);
3924
3925 return handled;
3926 }
3927
3928 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3929 {
3930 int handled = 0;
3931 int n;
3932
3933 do {
3934 n = min(len, 8);
3935 if (!(vcpu->arch.apic &&
3936 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3937 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3938 break;
3939 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3940 handled += n;
3941 addr += n;
3942 len -= n;
3943 v += n;
3944 } while (len);
3945
3946 return handled;
3947 }
3948
3949 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3950 struct kvm_segment *var, int seg)
3951 {
3952 kvm_x86_ops->set_segment(vcpu, var, seg);
3953 }
3954
3955 void kvm_get_segment(struct kvm_vcpu *vcpu,
3956 struct kvm_segment *var, int seg)
3957 {
3958 kvm_x86_ops->get_segment(vcpu, var, seg);
3959 }
3960
3961 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3962 {
3963 gpa_t t_gpa;
3964 struct x86_exception exception;
3965
3966 BUG_ON(!mmu_is_nested(vcpu));
3967
3968 /* NPT walks are always user-walks */
3969 access |= PFERR_USER_MASK;
3970 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3971
3972 return t_gpa;
3973 }
3974
3975 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3976 struct x86_exception *exception)
3977 {
3978 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3979 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3980 }
3981
3982 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3983 struct x86_exception *exception)
3984 {
3985 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3986 access |= PFERR_FETCH_MASK;
3987 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3988 }
3989
3990 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3991 struct x86_exception *exception)
3992 {
3993 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3994 access |= PFERR_WRITE_MASK;
3995 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3996 }
3997
3998 /* uses this to access any guest's mapped memory without checking CPL */
3999 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
4001 {
4002 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4003 }
4004
4005 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4006 struct kvm_vcpu *vcpu, u32 access,
4007 struct x86_exception *exception)
4008 {
4009 void *data = val;
4010 int r = X86EMUL_CONTINUE;
4011
4012 while (bytes) {
4013 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4014 exception);
4015 unsigned offset = addr & (PAGE_SIZE-1);
4016 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4017 int ret;
4018
4019 if (gpa == UNMAPPED_GVA)
4020 return X86EMUL_PROPAGATE_FAULT;
4021 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4022 if (ret < 0) {
4023 r = X86EMUL_IO_NEEDED;
4024 goto out;
4025 }
4026
4027 bytes -= toread;
4028 data += toread;
4029 addr += toread;
4030 }
4031 out:
4032 return r;
4033 }
4034
4035 /* used for instruction fetching */
4036 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4037 gva_t addr, void *val, unsigned int bytes,
4038 struct x86_exception *exception)
4039 {
4040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4042
4043 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4044 access | PFERR_FETCH_MASK,
4045 exception);
4046 }
4047
4048 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4049 gva_t addr, void *val, unsigned int bytes,
4050 struct x86_exception *exception)
4051 {
4052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4053 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4054
4055 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4056 exception);
4057 }
4058 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4059
4060 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4061 gva_t addr, void *val, unsigned int bytes,
4062 struct x86_exception *exception)
4063 {
4064 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4065 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4066 }
4067
4068 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4069 gva_t addr, void *val,
4070 unsigned int bytes,
4071 struct x86_exception *exception)
4072 {
4073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4074 void *data = val;
4075 int r = X86EMUL_CONTINUE;
4076
4077 while (bytes) {
4078 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4079 PFERR_WRITE_MASK,
4080 exception);
4081 unsigned offset = addr & (PAGE_SIZE-1);
4082 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4083 int ret;
4084
4085 if (gpa == UNMAPPED_GVA)
4086 return X86EMUL_PROPAGATE_FAULT;
4087 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4088 if (ret < 0) {
4089 r = X86EMUL_IO_NEEDED;
4090 goto out;
4091 }
4092
4093 bytes -= towrite;
4094 data += towrite;
4095 addr += towrite;
4096 }
4097 out:
4098 return r;
4099 }
4100 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4101
4102 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4103 gpa_t *gpa, struct x86_exception *exception,
4104 bool write)
4105 {
4106 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4107 | (write ? PFERR_WRITE_MASK : 0);
4108
4109 if (vcpu_match_mmio_gva(vcpu, gva)
4110 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4111 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4112 (gva & (PAGE_SIZE - 1));
4113 trace_vcpu_match_mmio(gva, *gpa, write, false);
4114 return 1;
4115 }
4116
4117 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4118
4119 if (*gpa == UNMAPPED_GVA)
4120 return -1;
4121
4122 /* For APIC access vmexit */
4123 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4124 return 1;
4125
4126 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4127 trace_vcpu_match_mmio(gva, *gpa, write, true);
4128 return 1;
4129 }
4130
4131 return 0;
4132 }
4133
4134 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4135 const void *val, int bytes)
4136 {
4137 int ret;
4138
4139 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4140 if (ret < 0)
4141 return 0;
4142 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4143 return 1;
4144 }
4145
4146 struct read_write_emulator_ops {
4147 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4148 int bytes);
4149 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4150 void *val, int bytes);
4151 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4152 int bytes, void *val);
4153 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4154 void *val, int bytes);
4155 bool write;
4156 };
4157
4158 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4159 {
4160 if (vcpu->mmio_read_completed) {
4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4162 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4163 vcpu->mmio_read_completed = 0;
4164 return 1;
4165 }
4166
4167 return 0;
4168 }
4169
4170 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4171 void *val, int bytes)
4172 {
4173 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4174 }
4175
4176 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4177 void *val, int bytes)
4178 {
4179 return emulator_write_phys(vcpu, gpa, val, bytes);
4180 }
4181
4182 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4183 {
4184 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4185 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4186 }
4187
4188 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4189 void *val, int bytes)
4190 {
4191 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4192 return X86EMUL_IO_NEEDED;
4193 }
4194
4195 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4196 void *val, int bytes)
4197 {
4198 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4199
4200 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4201 return X86EMUL_CONTINUE;
4202 }
4203
4204 static const struct read_write_emulator_ops read_emultor = {
4205 .read_write_prepare = read_prepare,
4206 .read_write_emulate = read_emulate,
4207 .read_write_mmio = vcpu_mmio_read,
4208 .read_write_exit_mmio = read_exit_mmio,
4209 };
4210
4211 static const struct read_write_emulator_ops write_emultor = {
4212 .read_write_emulate = write_emulate,
4213 .read_write_mmio = write_mmio,
4214 .read_write_exit_mmio = write_exit_mmio,
4215 .write = true,
4216 };
4217
4218 static int emulator_read_write_onepage(unsigned long addr, void *val,
4219 unsigned int bytes,
4220 struct x86_exception *exception,
4221 struct kvm_vcpu *vcpu,
4222 const struct read_write_emulator_ops *ops)
4223 {
4224 gpa_t gpa;
4225 int handled, ret;
4226 bool write = ops->write;
4227 struct kvm_mmio_fragment *frag;
4228
4229 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4230
4231 if (ret < 0)
4232 return X86EMUL_PROPAGATE_FAULT;
4233
4234 /* For APIC access vmexit */
4235 if (ret)
4236 goto mmio;
4237
4238 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4239 return X86EMUL_CONTINUE;
4240
4241 mmio:
4242 /*
4243 * Is this MMIO handled locally?
4244 */
4245 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4246 if (handled == bytes)
4247 return X86EMUL_CONTINUE;
4248
4249 gpa += handled;
4250 bytes -= handled;
4251 val += handled;
4252
4253 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4254 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4255 frag->gpa = gpa;
4256 frag->data = val;
4257 frag->len = bytes;
4258 return X86EMUL_CONTINUE;
4259 }
4260
4261 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4262 void *val, unsigned int bytes,
4263 struct x86_exception *exception,
4264 const struct read_write_emulator_ops *ops)
4265 {
4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4267 gpa_t gpa;
4268 int rc;
4269
4270 if (ops->read_write_prepare &&
4271 ops->read_write_prepare(vcpu, val, bytes))
4272 return X86EMUL_CONTINUE;
4273
4274 vcpu->mmio_nr_fragments = 0;
4275
4276 /* Crossing a page boundary? */
4277 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4278 int now;
4279
4280 now = -addr & ~PAGE_MASK;
4281 rc = emulator_read_write_onepage(addr, val, now, exception,
4282 vcpu, ops);
4283
4284 if (rc != X86EMUL_CONTINUE)
4285 return rc;
4286 addr += now;
4287 val += now;
4288 bytes -= now;
4289 }
4290
4291 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4292 vcpu, ops);
4293 if (rc != X86EMUL_CONTINUE)
4294 return rc;
4295
4296 if (!vcpu->mmio_nr_fragments)
4297 return rc;
4298
4299 gpa = vcpu->mmio_fragments[0].gpa;
4300
4301 vcpu->mmio_needed = 1;
4302 vcpu->mmio_cur_fragment = 0;
4303
4304 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4305 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4306 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4307 vcpu->run->mmio.phys_addr = gpa;
4308
4309 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4310 }
4311
4312 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
4314 void *val,
4315 unsigned int bytes,
4316 struct x86_exception *exception)
4317 {
4318 return emulator_read_write(ctxt, addr, val, bytes,
4319 exception, &read_emultor);
4320 }
4321
4322 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4323 unsigned long addr,
4324 const void *val,
4325 unsigned int bytes,
4326 struct x86_exception *exception)
4327 {
4328 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4329 exception, &write_emultor);
4330 }
4331
4332 #define CMPXCHG_TYPE(t, ptr, old, new) \
4333 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4334
4335 #ifdef CONFIG_X86_64
4336 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4337 #else
4338 # define CMPXCHG64(ptr, old, new) \
4339 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4340 #endif
4341
4342 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4343 unsigned long addr,
4344 const void *old,
4345 const void *new,
4346 unsigned int bytes,
4347 struct x86_exception *exception)
4348 {
4349 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4350 gpa_t gpa;
4351 struct page *page;
4352 char *kaddr;
4353 bool exchanged;
4354
4355 /* guests cmpxchg8b have to be emulated atomically */
4356 if (bytes > 8 || (bytes & (bytes - 1)))
4357 goto emul_write;
4358
4359 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4360
4361 if (gpa == UNMAPPED_GVA ||
4362 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4363 goto emul_write;
4364
4365 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4366 goto emul_write;
4367
4368 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4369 if (is_error_page(page))
4370 goto emul_write;
4371
4372 kaddr = kmap_atomic(page);
4373 kaddr += offset_in_page(gpa);
4374 switch (bytes) {
4375 case 1:
4376 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4377 break;
4378 case 2:
4379 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4380 break;
4381 case 4:
4382 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4383 break;
4384 case 8:
4385 exchanged = CMPXCHG64(kaddr, old, new);
4386 break;
4387 default:
4388 BUG();
4389 }
4390 kunmap_atomic(kaddr);
4391 kvm_release_page_dirty(page);
4392
4393 if (!exchanged)
4394 return X86EMUL_CMPXCHG_FAILED;
4395
4396 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4397
4398 return X86EMUL_CONTINUE;
4399
4400 emul_write:
4401 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4402
4403 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4404 }
4405
4406 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4407 {
4408 /* TODO: String I/O for in kernel device */
4409 int r;
4410
4411 if (vcpu->arch.pio.in)
4412 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4413 vcpu->arch.pio.size, pd);
4414 else
4415 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4416 vcpu->arch.pio.port, vcpu->arch.pio.size,
4417 pd);
4418 return r;
4419 }
4420
4421 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4422 unsigned short port, void *val,
4423 unsigned int count, bool in)
4424 {
4425 trace_kvm_pio(!in, port, size, count);
4426
4427 vcpu->arch.pio.port = port;
4428 vcpu->arch.pio.in = in;
4429 vcpu->arch.pio.count = count;
4430 vcpu->arch.pio.size = size;
4431
4432 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4433 vcpu->arch.pio.count = 0;
4434 return 1;
4435 }
4436
4437 vcpu->run->exit_reason = KVM_EXIT_IO;
4438 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4439 vcpu->run->io.size = size;
4440 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4441 vcpu->run->io.count = count;
4442 vcpu->run->io.port = port;
4443
4444 return 0;
4445 }
4446
4447 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4448 int size, unsigned short port, void *val,
4449 unsigned int count)
4450 {
4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4452 int ret;
4453
4454 if (vcpu->arch.pio.count)
4455 goto data_avail;
4456
4457 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4458 if (ret) {
4459 data_avail:
4460 memcpy(val, vcpu->arch.pio_data, size * count);
4461 vcpu->arch.pio.count = 0;
4462 return 1;
4463 }
4464
4465 return 0;
4466 }
4467
4468 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4469 int size, unsigned short port,
4470 const void *val, unsigned int count)
4471 {
4472 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4473
4474 memcpy(vcpu->arch.pio_data, val, size * count);
4475 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4476 }
4477
4478 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4479 {
4480 return kvm_x86_ops->get_segment_base(vcpu, seg);
4481 }
4482
4483 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4484 {
4485 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4486 }
4487
4488 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4489 {
4490 if (!need_emulate_wbinvd(vcpu))
4491 return X86EMUL_CONTINUE;
4492
4493 if (kvm_x86_ops->has_wbinvd_exit()) {
4494 int cpu = get_cpu();
4495
4496 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4497 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4498 wbinvd_ipi, NULL, 1);
4499 put_cpu();
4500 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4501 } else
4502 wbinvd();
4503 return X86EMUL_CONTINUE;
4504 }
4505 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4506
4507 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4508 {
4509 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4510 }
4511
4512 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4513 {
4514 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4515 }
4516
4517 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4518 {
4519
4520 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4521 }
4522
4523 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4524 {
4525 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4526 }
4527
4528 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4529 {
4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4531 unsigned long value;
4532
4533 switch (cr) {
4534 case 0:
4535 value = kvm_read_cr0(vcpu);
4536 break;
4537 case 2:
4538 value = vcpu->arch.cr2;
4539 break;
4540 case 3:
4541 value = kvm_read_cr3(vcpu);
4542 break;
4543 case 4:
4544 value = kvm_read_cr4(vcpu);
4545 break;
4546 case 8:
4547 value = kvm_get_cr8(vcpu);
4548 break;
4549 default:
4550 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4551 return 0;
4552 }
4553
4554 return value;
4555 }
4556
4557 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4558 {
4559 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4560 int res = 0;
4561
4562 switch (cr) {
4563 case 0:
4564 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4565 break;
4566 case 2:
4567 vcpu->arch.cr2 = val;
4568 break;
4569 case 3:
4570 res = kvm_set_cr3(vcpu, val);
4571 break;
4572 case 4:
4573 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4574 break;
4575 case 8:
4576 res = kvm_set_cr8(vcpu, val);
4577 break;
4578 default:
4579 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4580 res = -1;
4581 }
4582
4583 return res;
4584 }
4585
4586 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4587 {
4588 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4589 }
4590
4591 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4592 {
4593 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4594 }
4595
4596 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4597 {
4598 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4599 }
4600
4601 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4602 {
4603 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4604 }
4605
4606 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4607 {
4608 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4609 }
4610
4611 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4612 {
4613 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4614 }
4615
4616 static unsigned long emulator_get_cached_segment_base(
4617 struct x86_emulate_ctxt *ctxt, int seg)
4618 {
4619 return get_segment_base(emul_to_vcpu(ctxt), seg);
4620 }
4621
4622 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4623 struct desc_struct *desc, u32 *base3,
4624 int seg)
4625 {
4626 struct kvm_segment var;
4627
4628 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4629 *selector = var.selector;
4630
4631 if (var.unusable) {
4632 memset(desc, 0, sizeof(*desc));
4633 return false;
4634 }
4635
4636 if (var.g)
4637 var.limit >>= 12;
4638 set_desc_limit(desc, var.limit);
4639 set_desc_base(desc, (unsigned long)var.base);
4640 #ifdef CONFIG_X86_64
4641 if (base3)
4642 *base3 = var.base >> 32;
4643 #endif
4644 desc->type = var.type;
4645 desc->s = var.s;
4646 desc->dpl = var.dpl;
4647 desc->p = var.present;
4648 desc->avl = var.avl;
4649 desc->l = var.l;
4650 desc->d = var.db;
4651 desc->g = var.g;
4652
4653 return true;
4654 }
4655
4656 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4657 struct desc_struct *desc, u32 base3,
4658 int seg)
4659 {
4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4661 struct kvm_segment var;
4662
4663 var.selector = selector;
4664 var.base = get_desc_base(desc);
4665 #ifdef CONFIG_X86_64
4666 var.base |= ((u64)base3) << 32;
4667 #endif
4668 var.limit = get_desc_limit(desc);
4669 if (desc->g)
4670 var.limit = (var.limit << 12) | 0xfff;
4671 var.type = desc->type;
4672 var.present = desc->p;
4673 var.dpl = desc->dpl;
4674 var.db = desc->d;
4675 var.s = desc->s;
4676 var.l = desc->l;
4677 var.g = desc->g;
4678 var.avl = desc->avl;
4679 var.present = desc->p;
4680 var.unusable = !var.present;
4681 var.padding = 0;
4682
4683 kvm_set_segment(vcpu, &var, seg);
4684 return;
4685 }
4686
4687 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4688 u32 msr_index, u64 *pdata)
4689 {
4690 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4691 }
4692
4693 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4694 u32 msr_index, u64 data)
4695 {
4696 struct msr_data msr;
4697
4698 msr.data = data;
4699 msr.index = msr_index;
4700 msr.host_initiated = false;
4701 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4702 }
4703
4704 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4705 u32 pmc, u64 *pdata)
4706 {
4707 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4708 }
4709
4710 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4711 {
4712 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4713 }
4714
4715 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4716 {
4717 preempt_disable();
4718 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4719 /*
4720 * CR0.TS may reference the host fpu state, not the guest fpu state,
4721 * so it may be clear at this point.
4722 */
4723 clts();
4724 }
4725
4726 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4727 {
4728 preempt_enable();
4729 }
4730
4731 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4732 struct x86_instruction_info *info,
4733 enum x86_intercept_stage stage)
4734 {
4735 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4736 }
4737
4738 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4739 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4740 {
4741 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4742 }
4743
4744 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4745 {
4746 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4747 }
4748
4749 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4750 {
4751 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4752 }
4753
4754 static const struct x86_emulate_ops emulate_ops = {
4755 .read_gpr = emulator_read_gpr,
4756 .write_gpr = emulator_write_gpr,
4757 .read_std = kvm_read_guest_virt_system,
4758 .write_std = kvm_write_guest_virt_system,
4759 .fetch = kvm_fetch_guest_virt,
4760 .read_emulated = emulator_read_emulated,
4761 .write_emulated = emulator_write_emulated,
4762 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4763 .invlpg = emulator_invlpg,
4764 .pio_in_emulated = emulator_pio_in_emulated,
4765 .pio_out_emulated = emulator_pio_out_emulated,
4766 .get_segment = emulator_get_segment,
4767 .set_segment = emulator_set_segment,
4768 .get_cached_segment_base = emulator_get_cached_segment_base,
4769 .get_gdt = emulator_get_gdt,
4770 .get_idt = emulator_get_idt,
4771 .set_gdt = emulator_set_gdt,
4772 .set_idt = emulator_set_idt,
4773 .get_cr = emulator_get_cr,
4774 .set_cr = emulator_set_cr,
4775 .set_rflags = emulator_set_rflags,
4776 .cpl = emulator_get_cpl,
4777 .get_dr = emulator_get_dr,
4778 .set_dr = emulator_set_dr,
4779 .set_msr = emulator_set_msr,
4780 .get_msr = emulator_get_msr,
4781 .read_pmc = emulator_read_pmc,
4782 .halt = emulator_halt,
4783 .wbinvd = emulator_wbinvd,
4784 .fix_hypercall = emulator_fix_hypercall,
4785 .get_fpu = emulator_get_fpu,
4786 .put_fpu = emulator_put_fpu,
4787 .intercept = emulator_intercept,
4788 .get_cpuid = emulator_get_cpuid,
4789 };
4790
4791 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4792 {
4793 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4794 /*
4795 * an sti; sti; sequence only disable interrupts for the first
4796 * instruction. So, if the last instruction, be it emulated or
4797 * not, left the system with the INT_STI flag enabled, it
4798 * means that the last instruction is an sti. We should not
4799 * leave the flag on in this case. The same goes for mov ss
4800 */
4801 if (!(int_shadow & mask))
4802 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4803 }
4804
4805 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4806 {
4807 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4808 if (ctxt->exception.vector == PF_VECTOR)
4809 kvm_propagate_fault(vcpu, &ctxt->exception);
4810 else if (ctxt->exception.error_code_valid)
4811 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4812 ctxt->exception.error_code);
4813 else
4814 kvm_queue_exception(vcpu, ctxt->exception.vector);
4815 }
4816
4817 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4818 {
4819 memset(&ctxt->opcode_len, 0,
4820 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4821
4822 ctxt->fetch.start = 0;
4823 ctxt->fetch.end = 0;
4824 ctxt->io_read.pos = 0;
4825 ctxt->io_read.end = 0;
4826 ctxt->mem_read.pos = 0;
4827 ctxt->mem_read.end = 0;
4828 }
4829
4830 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4831 {
4832 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4833 int cs_db, cs_l;
4834
4835 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4836
4837 ctxt->eflags = kvm_get_rflags(vcpu);
4838 ctxt->eip = kvm_rip_read(vcpu);
4839 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4840 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4841 cs_l ? X86EMUL_MODE_PROT64 :
4842 cs_db ? X86EMUL_MODE_PROT32 :
4843 X86EMUL_MODE_PROT16;
4844 ctxt->guest_mode = is_guest_mode(vcpu);
4845
4846 init_decode_cache(ctxt);
4847 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4848 }
4849
4850 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4851 {
4852 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4853 int ret;
4854
4855 init_emulate_ctxt(vcpu);
4856
4857 ctxt->op_bytes = 2;
4858 ctxt->ad_bytes = 2;
4859 ctxt->_eip = ctxt->eip + inc_eip;
4860 ret = emulate_int_real(ctxt, irq);
4861
4862 if (ret != X86EMUL_CONTINUE)
4863 return EMULATE_FAIL;
4864
4865 ctxt->eip = ctxt->_eip;
4866 kvm_rip_write(vcpu, ctxt->eip);
4867 kvm_set_rflags(vcpu, ctxt->eflags);
4868
4869 if (irq == NMI_VECTOR)
4870 vcpu->arch.nmi_pending = 0;
4871 else
4872 vcpu->arch.interrupt.pending = false;
4873
4874 return EMULATE_DONE;
4875 }
4876 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4877
4878 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4879 {
4880 int r = EMULATE_DONE;
4881
4882 ++vcpu->stat.insn_emulation_fail;
4883 trace_kvm_emulate_insn_failed(vcpu);
4884 if (!is_guest_mode(vcpu)) {
4885 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4886 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4887 vcpu->run->internal.ndata = 0;
4888 r = EMULATE_FAIL;
4889 }
4890 kvm_queue_exception(vcpu, UD_VECTOR);
4891
4892 return r;
4893 }
4894
4895 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4896 bool write_fault_to_shadow_pgtable,
4897 int emulation_type)
4898 {
4899 gpa_t gpa = cr2;
4900 pfn_t pfn;
4901
4902 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4903 return false;
4904
4905 if (!vcpu->arch.mmu.direct_map) {
4906 /*
4907 * Write permission should be allowed since only
4908 * write access need to be emulated.
4909 */
4910 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4911
4912 /*
4913 * If the mapping is invalid in guest, let cpu retry
4914 * it to generate fault.
4915 */
4916 if (gpa == UNMAPPED_GVA)
4917 return true;
4918 }
4919
4920 /*
4921 * Do not retry the unhandleable instruction if it faults on the
4922 * readonly host memory, otherwise it will goto a infinite loop:
4923 * retry instruction -> write #PF -> emulation fail -> retry
4924 * instruction -> ...
4925 */
4926 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4927
4928 /*
4929 * If the instruction failed on the error pfn, it can not be fixed,
4930 * report the error to userspace.
4931 */
4932 if (is_error_noslot_pfn(pfn))
4933 return false;
4934
4935 kvm_release_pfn_clean(pfn);
4936
4937 /* The instructions are well-emulated on direct mmu. */
4938 if (vcpu->arch.mmu.direct_map) {
4939 unsigned int indirect_shadow_pages;
4940
4941 spin_lock(&vcpu->kvm->mmu_lock);
4942 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4943 spin_unlock(&vcpu->kvm->mmu_lock);
4944
4945 if (indirect_shadow_pages)
4946 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4947
4948 return true;
4949 }
4950
4951 /*
4952 * if emulation was due to access to shadowed page table
4953 * and it failed try to unshadow page and re-enter the
4954 * guest to let CPU execute the instruction.
4955 */
4956 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4957
4958 /*
4959 * If the access faults on its page table, it can not
4960 * be fixed by unprotecting shadow page and it should
4961 * be reported to userspace.
4962 */
4963 return !write_fault_to_shadow_pgtable;
4964 }
4965
4966 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4967 unsigned long cr2, int emulation_type)
4968 {
4969 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4970 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4971
4972 last_retry_eip = vcpu->arch.last_retry_eip;
4973 last_retry_addr = vcpu->arch.last_retry_addr;
4974
4975 /*
4976 * If the emulation is caused by #PF and it is non-page_table
4977 * writing instruction, it means the VM-EXIT is caused by shadow
4978 * page protected, we can zap the shadow page and retry this
4979 * instruction directly.
4980 *
4981 * Note: if the guest uses a non-page-table modifying instruction
4982 * on the PDE that points to the instruction, then we will unmap
4983 * the instruction and go to an infinite loop. So, we cache the
4984 * last retried eip and the last fault address, if we meet the eip
4985 * and the address again, we can break out of the potential infinite
4986 * loop.
4987 */
4988 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4989
4990 if (!(emulation_type & EMULTYPE_RETRY))
4991 return false;
4992
4993 if (x86_page_table_writing_insn(ctxt))
4994 return false;
4995
4996 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4997 return false;
4998
4999 vcpu->arch.last_retry_eip = ctxt->eip;
5000 vcpu->arch.last_retry_addr = cr2;
5001
5002 if (!vcpu->arch.mmu.direct_map)
5003 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5004
5005 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5006
5007 return true;
5008 }
5009
5010 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5011 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5012
5013 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5014 unsigned long *db)
5015 {
5016 u32 dr6 = 0;
5017 int i;
5018 u32 enable, rwlen;
5019
5020 enable = dr7;
5021 rwlen = dr7 >> 16;
5022 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5023 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5024 dr6 |= (1 << i);
5025 return dr6;
5026 }
5027
5028 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5029 {
5030 struct kvm_run *kvm_run = vcpu->run;
5031
5032 /*
5033 * Use the "raw" value to see if TF was passed to the processor.
5034 * Note that the new value of the flags has not been saved yet.
5035 *
5036 * This is correct even for TF set by the guest, because "the
5037 * processor will not generate this exception after the instruction
5038 * that sets the TF flag".
5039 */
5040 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5041
5042 if (unlikely(rflags & X86_EFLAGS_TF)) {
5043 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5044 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5045 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5046 kvm_run->debug.arch.exception = DB_VECTOR;
5047 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5048 *r = EMULATE_USER_EXIT;
5049 } else {
5050 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5051 /*
5052 * "Certain debug exceptions may clear bit 0-3. The
5053 * remaining contents of the DR6 register are never
5054 * cleared by the processor".
5055 */
5056 vcpu->arch.dr6 &= ~15;
5057 vcpu->arch.dr6 |= DR6_BS;
5058 kvm_queue_exception(vcpu, DB_VECTOR);
5059 }
5060 }
5061 }
5062
5063 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5064 {
5065 struct kvm_run *kvm_run = vcpu->run;
5066 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5067 u32 dr6 = 0;
5068
5069 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5070 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5071 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5072 vcpu->arch.guest_debug_dr7,
5073 vcpu->arch.eff_db);
5074
5075 if (dr6 != 0) {
5076 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5077 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5078 get_segment_base(vcpu, VCPU_SREG_CS);
5079
5080 kvm_run->debug.arch.exception = DB_VECTOR;
5081 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5082 *r = EMULATE_USER_EXIT;
5083 return true;
5084 }
5085 }
5086
5087 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5088 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5089 vcpu->arch.dr7,
5090 vcpu->arch.db);
5091
5092 if (dr6 != 0) {
5093 vcpu->arch.dr6 &= ~15;
5094 vcpu->arch.dr6 |= dr6;
5095 kvm_queue_exception(vcpu, DB_VECTOR);
5096 *r = EMULATE_DONE;
5097 return true;
5098 }
5099 }
5100
5101 return false;
5102 }
5103
5104 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5105 unsigned long cr2,
5106 int emulation_type,
5107 void *insn,
5108 int insn_len)
5109 {
5110 int r;
5111 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5112 bool writeback = true;
5113 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5114
5115 /*
5116 * Clear write_fault_to_shadow_pgtable here to ensure it is
5117 * never reused.
5118 */
5119 vcpu->arch.write_fault_to_shadow_pgtable = false;
5120 kvm_clear_exception_queue(vcpu);
5121
5122 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5123 init_emulate_ctxt(vcpu);
5124
5125 /*
5126 * We will reenter on the same instruction since
5127 * we do not set complete_userspace_io. This does not
5128 * handle watchpoints yet, those would be handled in
5129 * the emulate_ops.
5130 */
5131 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5132 return r;
5133
5134 ctxt->interruptibility = 0;
5135 ctxt->have_exception = false;
5136 ctxt->perm_ok = false;
5137
5138 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5139
5140 r = x86_decode_insn(ctxt, insn, insn_len);
5141
5142 trace_kvm_emulate_insn_start(vcpu);
5143 ++vcpu->stat.insn_emulation;
5144 if (r != EMULATION_OK) {
5145 if (emulation_type & EMULTYPE_TRAP_UD)
5146 return EMULATE_FAIL;
5147 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5148 emulation_type))
5149 return EMULATE_DONE;
5150 if (emulation_type & EMULTYPE_SKIP)
5151 return EMULATE_FAIL;
5152 return handle_emulation_failure(vcpu);
5153 }
5154 }
5155
5156 if (emulation_type & EMULTYPE_SKIP) {
5157 kvm_rip_write(vcpu, ctxt->_eip);
5158 return EMULATE_DONE;
5159 }
5160
5161 if (retry_instruction(ctxt, cr2, emulation_type))
5162 return EMULATE_DONE;
5163
5164 /* this is needed for vmware backdoor interface to work since it
5165 changes registers values during IO operation */
5166 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5167 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5168 emulator_invalidate_register_cache(ctxt);
5169 }
5170
5171 restart:
5172 r = x86_emulate_insn(ctxt);
5173
5174 if (r == EMULATION_INTERCEPTED)
5175 return EMULATE_DONE;
5176
5177 if (r == EMULATION_FAILED) {
5178 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5179 emulation_type))
5180 return EMULATE_DONE;
5181
5182 return handle_emulation_failure(vcpu);
5183 }
5184
5185 if (ctxt->have_exception) {
5186 inject_emulated_exception(vcpu);
5187 r = EMULATE_DONE;
5188 } else if (vcpu->arch.pio.count) {
5189 if (!vcpu->arch.pio.in) {
5190 /* FIXME: return into emulator if single-stepping. */
5191 vcpu->arch.pio.count = 0;
5192 } else {
5193 writeback = false;
5194 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5195 }
5196 r = EMULATE_USER_EXIT;
5197 } else if (vcpu->mmio_needed) {
5198 if (!vcpu->mmio_is_write)
5199 writeback = false;
5200 r = EMULATE_USER_EXIT;
5201 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5202 } else if (r == EMULATION_RESTART)
5203 goto restart;
5204 else
5205 r = EMULATE_DONE;
5206
5207 if (writeback) {
5208 toggle_interruptibility(vcpu, ctxt->interruptibility);
5209 kvm_make_request(KVM_REQ_EVENT, vcpu);
5210 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5211 kvm_rip_write(vcpu, ctxt->eip);
5212 if (r == EMULATE_DONE)
5213 kvm_vcpu_check_singlestep(vcpu, &r);
5214 kvm_set_rflags(vcpu, ctxt->eflags);
5215 } else
5216 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5217
5218 return r;
5219 }
5220 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5221
5222 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5223 {
5224 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5225 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5226 size, port, &val, 1);
5227 /* do not return to emulator after return from userspace */
5228 vcpu->arch.pio.count = 0;
5229 return ret;
5230 }
5231 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5232
5233 static void tsc_bad(void *info)
5234 {
5235 __this_cpu_write(cpu_tsc_khz, 0);
5236 }
5237
5238 static void tsc_khz_changed(void *data)
5239 {
5240 struct cpufreq_freqs *freq = data;
5241 unsigned long khz = 0;
5242
5243 if (data)
5244 khz = freq->new;
5245 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5246 khz = cpufreq_quick_get(raw_smp_processor_id());
5247 if (!khz)
5248 khz = tsc_khz;
5249 __this_cpu_write(cpu_tsc_khz, khz);
5250 }
5251
5252 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5253 void *data)
5254 {
5255 struct cpufreq_freqs *freq = data;
5256 struct kvm *kvm;
5257 struct kvm_vcpu *vcpu;
5258 int i, send_ipi = 0;
5259
5260 /*
5261 * We allow guests to temporarily run on slowing clocks,
5262 * provided we notify them after, or to run on accelerating
5263 * clocks, provided we notify them before. Thus time never
5264 * goes backwards.
5265 *
5266 * However, we have a problem. We can't atomically update
5267 * the frequency of a given CPU from this function; it is
5268 * merely a notifier, which can be called from any CPU.
5269 * Changing the TSC frequency at arbitrary points in time
5270 * requires a recomputation of local variables related to
5271 * the TSC for each VCPU. We must flag these local variables
5272 * to be updated and be sure the update takes place with the
5273 * new frequency before any guests proceed.
5274 *
5275 * Unfortunately, the combination of hotplug CPU and frequency
5276 * change creates an intractable locking scenario; the order
5277 * of when these callouts happen is undefined with respect to
5278 * CPU hotplug, and they can race with each other. As such,
5279 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5280 * undefined; you can actually have a CPU frequency change take
5281 * place in between the computation of X and the setting of the
5282 * variable. To protect against this problem, all updates of
5283 * the per_cpu tsc_khz variable are done in an interrupt
5284 * protected IPI, and all callers wishing to update the value
5285 * must wait for a synchronous IPI to complete (which is trivial
5286 * if the caller is on the CPU already). This establishes the
5287 * necessary total order on variable updates.
5288 *
5289 * Note that because a guest time update may take place
5290 * anytime after the setting of the VCPU's request bit, the
5291 * correct TSC value must be set before the request. However,
5292 * to ensure the update actually makes it to any guest which
5293 * starts running in hardware virtualization between the set
5294 * and the acquisition of the spinlock, we must also ping the
5295 * CPU after setting the request bit.
5296 *
5297 */
5298
5299 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5300 return 0;
5301 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5302 return 0;
5303
5304 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5305
5306 spin_lock(&kvm_lock);
5307 list_for_each_entry(kvm, &vm_list, vm_list) {
5308 kvm_for_each_vcpu(i, vcpu, kvm) {
5309 if (vcpu->cpu != freq->cpu)
5310 continue;
5311 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5312 if (vcpu->cpu != smp_processor_id())
5313 send_ipi = 1;
5314 }
5315 }
5316 spin_unlock(&kvm_lock);
5317
5318 if (freq->old < freq->new && send_ipi) {
5319 /*
5320 * We upscale the frequency. Must make the guest
5321 * doesn't see old kvmclock values while running with
5322 * the new frequency, otherwise we risk the guest sees
5323 * time go backwards.
5324 *
5325 * In case we update the frequency for another cpu
5326 * (which might be in guest context) send an interrupt
5327 * to kick the cpu out of guest context. Next time
5328 * guest context is entered kvmclock will be updated,
5329 * so the guest will not see stale values.
5330 */
5331 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5332 }
5333 return 0;
5334 }
5335
5336 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5337 .notifier_call = kvmclock_cpufreq_notifier
5338 };
5339
5340 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5341 unsigned long action, void *hcpu)
5342 {
5343 unsigned int cpu = (unsigned long)hcpu;
5344
5345 switch (action) {
5346 case CPU_ONLINE:
5347 case CPU_DOWN_FAILED:
5348 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5349 break;
5350 case CPU_DOWN_PREPARE:
5351 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5352 break;
5353 }
5354 return NOTIFY_OK;
5355 }
5356
5357 static struct notifier_block kvmclock_cpu_notifier_block = {
5358 .notifier_call = kvmclock_cpu_notifier,
5359 .priority = -INT_MAX
5360 };
5361
5362 static void kvm_timer_init(void)
5363 {
5364 int cpu;
5365
5366 max_tsc_khz = tsc_khz;
5367 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5368 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5369 #ifdef CONFIG_CPU_FREQ
5370 struct cpufreq_policy policy;
5371 memset(&policy, 0, sizeof(policy));
5372 cpu = get_cpu();
5373 cpufreq_get_policy(&policy, cpu);
5374 if (policy.cpuinfo.max_freq)
5375 max_tsc_khz = policy.cpuinfo.max_freq;
5376 put_cpu();
5377 #endif
5378 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5379 CPUFREQ_TRANSITION_NOTIFIER);
5380 }
5381 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5382 for_each_online_cpu(cpu)
5383 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5384 }
5385
5386 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5387
5388 int kvm_is_in_guest(void)
5389 {
5390 return __this_cpu_read(current_vcpu) != NULL;
5391 }
5392
5393 static int kvm_is_user_mode(void)
5394 {
5395 int user_mode = 3;
5396
5397 if (__this_cpu_read(current_vcpu))
5398 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5399
5400 return user_mode != 0;
5401 }
5402
5403 static unsigned long kvm_get_guest_ip(void)
5404 {
5405 unsigned long ip = 0;
5406
5407 if (__this_cpu_read(current_vcpu))
5408 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5409
5410 return ip;
5411 }
5412
5413 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5414 .is_in_guest = kvm_is_in_guest,
5415 .is_user_mode = kvm_is_user_mode,
5416 .get_guest_ip = kvm_get_guest_ip,
5417 };
5418
5419 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5420 {
5421 __this_cpu_write(current_vcpu, vcpu);
5422 }
5423 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5424
5425 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5426 {
5427 __this_cpu_write(current_vcpu, NULL);
5428 }
5429 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5430
5431 static void kvm_set_mmio_spte_mask(void)
5432 {
5433 u64 mask;
5434 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5435
5436 /*
5437 * Set the reserved bits and the present bit of an paging-structure
5438 * entry to generate page fault with PFER.RSV = 1.
5439 */
5440 /* Mask the reserved physical address bits. */
5441 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5442
5443 /* Bit 62 is always reserved for 32bit host. */
5444 mask |= 0x3ull << 62;
5445
5446 /* Set the present bit. */
5447 mask |= 1ull;
5448
5449 #ifdef CONFIG_X86_64
5450 /*
5451 * If reserved bit is not supported, clear the present bit to disable
5452 * mmio page fault.
5453 */
5454 if (maxphyaddr == 52)
5455 mask &= ~1ull;
5456 #endif
5457
5458 kvm_mmu_set_mmio_spte_mask(mask);
5459 }
5460
5461 #ifdef CONFIG_X86_64
5462 static void pvclock_gtod_update_fn(struct work_struct *work)
5463 {
5464 struct kvm *kvm;
5465
5466 struct kvm_vcpu *vcpu;
5467 int i;
5468
5469 spin_lock(&kvm_lock);
5470 list_for_each_entry(kvm, &vm_list, vm_list)
5471 kvm_for_each_vcpu(i, vcpu, kvm)
5472 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5473 atomic_set(&kvm_guest_has_master_clock, 0);
5474 spin_unlock(&kvm_lock);
5475 }
5476
5477 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5478
5479 /*
5480 * Notification about pvclock gtod data update.
5481 */
5482 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5483 void *priv)
5484 {
5485 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5486 struct timekeeper *tk = priv;
5487
5488 update_pvclock_gtod(tk);
5489
5490 /* disable master clock if host does not trust, or does not
5491 * use, TSC clocksource
5492 */
5493 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5494 atomic_read(&kvm_guest_has_master_clock) != 0)
5495 queue_work(system_long_wq, &pvclock_gtod_work);
5496
5497 return 0;
5498 }
5499
5500 static struct notifier_block pvclock_gtod_notifier = {
5501 .notifier_call = pvclock_gtod_notify,
5502 };
5503 #endif
5504
5505 int kvm_arch_init(void *opaque)
5506 {
5507 int r;
5508 struct kvm_x86_ops *ops = opaque;
5509
5510 if (kvm_x86_ops) {
5511 printk(KERN_ERR "kvm: already loaded the other module\n");
5512 r = -EEXIST;
5513 goto out;
5514 }
5515
5516 if (!ops->cpu_has_kvm_support()) {
5517 printk(KERN_ERR "kvm: no hardware support\n");
5518 r = -EOPNOTSUPP;
5519 goto out;
5520 }
5521 if (ops->disabled_by_bios()) {
5522 printk(KERN_ERR "kvm: disabled by bios\n");
5523 r = -EOPNOTSUPP;
5524 goto out;
5525 }
5526
5527 r = -ENOMEM;
5528 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5529 if (!shared_msrs) {
5530 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5531 goto out;
5532 }
5533
5534 r = kvm_mmu_module_init();
5535 if (r)
5536 goto out_free_percpu;
5537
5538 kvm_set_mmio_spte_mask();
5539 kvm_init_msr_list();
5540
5541 kvm_x86_ops = ops;
5542 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5543 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5544
5545 kvm_timer_init();
5546
5547 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5548
5549 if (cpu_has_xsave)
5550 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5551
5552 kvm_lapic_init();
5553 #ifdef CONFIG_X86_64
5554 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5555 #endif
5556
5557 return 0;
5558
5559 out_free_percpu:
5560 free_percpu(shared_msrs);
5561 out:
5562 return r;
5563 }
5564
5565 void kvm_arch_exit(void)
5566 {
5567 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5568
5569 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5570 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5571 CPUFREQ_TRANSITION_NOTIFIER);
5572 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5573 #ifdef CONFIG_X86_64
5574 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5575 #endif
5576 kvm_x86_ops = NULL;
5577 kvm_mmu_module_exit();
5578 free_percpu(shared_msrs);
5579 }
5580
5581 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5582 {
5583 ++vcpu->stat.halt_exits;
5584 if (irqchip_in_kernel(vcpu->kvm)) {
5585 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5586 return 1;
5587 } else {
5588 vcpu->run->exit_reason = KVM_EXIT_HLT;
5589 return 0;
5590 }
5591 }
5592 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5593
5594 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5595 {
5596 u64 param, ingpa, outgpa, ret;
5597 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5598 bool fast, longmode;
5599 int cs_db, cs_l;
5600
5601 /*
5602 * hypercall generates UD from non zero cpl and real mode
5603 * per HYPER-V spec
5604 */
5605 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5606 kvm_queue_exception(vcpu, UD_VECTOR);
5607 return 0;
5608 }
5609
5610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5611 longmode = is_long_mode(vcpu) && cs_l == 1;
5612
5613 if (!longmode) {
5614 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5615 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5616 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5617 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5618 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5619 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5620 }
5621 #ifdef CONFIG_X86_64
5622 else {
5623 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5624 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5625 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5626 }
5627 #endif
5628
5629 code = param & 0xffff;
5630 fast = (param >> 16) & 0x1;
5631 rep_cnt = (param >> 32) & 0xfff;
5632 rep_idx = (param >> 48) & 0xfff;
5633
5634 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5635
5636 switch (code) {
5637 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5638 kvm_vcpu_on_spin(vcpu);
5639 break;
5640 default:
5641 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5642 break;
5643 }
5644
5645 ret = res | (((u64)rep_done & 0xfff) << 32);
5646 if (longmode) {
5647 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5648 } else {
5649 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5650 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5651 }
5652
5653 return 1;
5654 }
5655
5656 /*
5657 * kvm_pv_kick_cpu_op: Kick a vcpu.
5658 *
5659 * @apicid - apicid of vcpu to be kicked.
5660 */
5661 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5662 {
5663 struct kvm_lapic_irq lapic_irq;
5664
5665 lapic_irq.shorthand = 0;
5666 lapic_irq.dest_mode = 0;
5667 lapic_irq.dest_id = apicid;
5668
5669 lapic_irq.delivery_mode = APIC_DM_REMRD;
5670 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5671 }
5672
5673 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5674 {
5675 unsigned long nr, a0, a1, a2, a3, ret;
5676 int r = 1;
5677
5678 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5679 return kvm_hv_hypercall(vcpu);
5680
5681 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5682 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5683 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5684 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5685 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5686
5687 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5688
5689 if (!is_long_mode(vcpu)) {
5690 nr &= 0xFFFFFFFF;
5691 a0 &= 0xFFFFFFFF;
5692 a1 &= 0xFFFFFFFF;
5693 a2 &= 0xFFFFFFFF;
5694 a3 &= 0xFFFFFFFF;
5695 }
5696
5697 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5698 ret = -KVM_EPERM;
5699 goto out;
5700 }
5701
5702 switch (nr) {
5703 case KVM_HC_VAPIC_POLL_IRQ:
5704 ret = 0;
5705 break;
5706 case KVM_HC_KICK_CPU:
5707 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5708 ret = 0;
5709 break;
5710 default:
5711 ret = -KVM_ENOSYS;
5712 break;
5713 }
5714 out:
5715 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5716 ++vcpu->stat.hypercalls;
5717 return r;
5718 }
5719 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5720
5721 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5722 {
5723 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5724 char instruction[3];
5725 unsigned long rip = kvm_rip_read(vcpu);
5726
5727 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5728
5729 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5730 }
5731
5732 /*
5733 * Check if userspace requested an interrupt window, and that the
5734 * interrupt window is open.
5735 *
5736 * No need to exit to userspace if we already have an interrupt queued.
5737 */
5738 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5739 {
5740 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5741 vcpu->run->request_interrupt_window &&
5742 kvm_arch_interrupt_allowed(vcpu));
5743 }
5744
5745 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5746 {
5747 struct kvm_run *kvm_run = vcpu->run;
5748
5749 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5750 kvm_run->cr8 = kvm_get_cr8(vcpu);
5751 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5752 if (irqchip_in_kernel(vcpu->kvm))
5753 kvm_run->ready_for_interrupt_injection = 1;
5754 else
5755 kvm_run->ready_for_interrupt_injection =
5756 kvm_arch_interrupt_allowed(vcpu) &&
5757 !kvm_cpu_has_interrupt(vcpu) &&
5758 !kvm_event_needs_reinjection(vcpu);
5759 }
5760
5761 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5762 {
5763 int max_irr, tpr;
5764
5765 if (!kvm_x86_ops->update_cr8_intercept)
5766 return;
5767
5768 if (!vcpu->arch.apic)
5769 return;
5770
5771 if (!vcpu->arch.apic->vapic_addr)
5772 max_irr = kvm_lapic_find_highest_irr(vcpu);
5773 else
5774 max_irr = -1;
5775
5776 if (max_irr != -1)
5777 max_irr >>= 4;
5778
5779 tpr = kvm_lapic_get_cr8(vcpu);
5780
5781 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5782 }
5783
5784 static void inject_pending_event(struct kvm_vcpu *vcpu)
5785 {
5786 /* try to reinject previous events if any */
5787 if (vcpu->arch.exception.pending) {
5788 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5789 vcpu->arch.exception.has_error_code,
5790 vcpu->arch.exception.error_code);
5791 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5792 vcpu->arch.exception.has_error_code,
5793 vcpu->arch.exception.error_code,
5794 vcpu->arch.exception.reinject);
5795 return;
5796 }
5797
5798 if (vcpu->arch.nmi_injected) {
5799 kvm_x86_ops->set_nmi(vcpu);
5800 return;
5801 }
5802
5803 if (vcpu->arch.interrupt.pending) {
5804 kvm_x86_ops->set_irq(vcpu);
5805 return;
5806 }
5807
5808 /* try to inject new event if pending */
5809 if (vcpu->arch.nmi_pending) {
5810 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5811 --vcpu->arch.nmi_pending;
5812 vcpu->arch.nmi_injected = true;
5813 kvm_x86_ops->set_nmi(vcpu);
5814 }
5815 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5816 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5817 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5818 false);
5819 kvm_x86_ops->set_irq(vcpu);
5820 }
5821 }
5822 }
5823
5824 static void process_nmi(struct kvm_vcpu *vcpu)
5825 {
5826 unsigned limit = 2;
5827
5828 /*
5829 * x86 is limited to one NMI running, and one NMI pending after it.
5830 * If an NMI is already in progress, limit further NMIs to just one.
5831 * Otherwise, allow two (and we'll inject the first one immediately).
5832 */
5833 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5834 limit = 1;
5835
5836 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5837 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5838 kvm_make_request(KVM_REQ_EVENT, vcpu);
5839 }
5840
5841 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5842 {
5843 u64 eoi_exit_bitmap[4];
5844 u32 tmr[8];
5845
5846 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5847 return;
5848
5849 memset(eoi_exit_bitmap, 0, 32);
5850 memset(tmr, 0, 32);
5851
5852 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5853 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5854 kvm_apic_update_tmr(vcpu, tmr);
5855 }
5856
5857 /*
5858 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5859 * exiting to the userspace. Otherwise, the value will be returned to the
5860 * userspace.
5861 */
5862 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5863 {
5864 int r;
5865 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5866 vcpu->run->request_interrupt_window;
5867 bool req_immediate_exit = false;
5868
5869 if (vcpu->requests) {
5870 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5871 kvm_mmu_unload(vcpu);
5872 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5873 __kvm_migrate_timers(vcpu);
5874 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5875 kvm_gen_update_masterclock(vcpu->kvm);
5876 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5877 kvm_gen_kvmclock_update(vcpu);
5878 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5879 r = kvm_guest_time_update(vcpu);
5880 if (unlikely(r))
5881 goto out;
5882 }
5883 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5884 kvm_mmu_sync_roots(vcpu);
5885 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5886 kvm_x86_ops->tlb_flush(vcpu);
5887 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5888 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5889 r = 0;
5890 goto out;
5891 }
5892 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5893 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5894 r = 0;
5895 goto out;
5896 }
5897 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5898 vcpu->fpu_active = 0;
5899 kvm_x86_ops->fpu_deactivate(vcpu);
5900 }
5901 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5902 /* Page is swapped out. Do synthetic halt */
5903 vcpu->arch.apf.halted = true;
5904 r = 1;
5905 goto out;
5906 }
5907 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5908 record_steal_time(vcpu);
5909 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5910 process_nmi(vcpu);
5911 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5912 kvm_handle_pmu_event(vcpu);
5913 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5914 kvm_deliver_pmi(vcpu);
5915 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5916 vcpu_scan_ioapic(vcpu);
5917 }
5918
5919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5920 kvm_apic_accept_events(vcpu);
5921 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5922 r = 1;
5923 goto out;
5924 }
5925
5926 inject_pending_event(vcpu);
5927
5928 /* enable NMI/IRQ window open exits if needed */
5929 if (vcpu->arch.nmi_pending)
5930 req_immediate_exit =
5931 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5932 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5933 req_immediate_exit =
5934 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5935
5936 if (kvm_lapic_enabled(vcpu)) {
5937 /*
5938 * Update architecture specific hints for APIC
5939 * virtual interrupt delivery.
5940 */
5941 if (kvm_x86_ops->hwapic_irr_update)
5942 kvm_x86_ops->hwapic_irr_update(vcpu,
5943 kvm_lapic_find_highest_irr(vcpu));
5944 update_cr8_intercept(vcpu);
5945 kvm_lapic_sync_to_vapic(vcpu);
5946 }
5947 }
5948
5949 r = kvm_mmu_reload(vcpu);
5950 if (unlikely(r)) {
5951 goto cancel_injection;
5952 }
5953
5954 preempt_disable();
5955
5956 kvm_x86_ops->prepare_guest_switch(vcpu);
5957 if (vcpu->fpu_active)
5958 kvm_load_guest_fpu(vcpu);
5959 kvm_load_guest_xcr0(vcpu);
5960
5961 vcpu->mode = IN_GUEST_MODE;
5962
5963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5964
5965 /* We should set ->mode before check ->requests,
5966 * see the comment in make_all_cpus_request.
5967 */
5968 smp_mb__after_srcu_read_unlock();
5969
5970 local_irq_disable();
5971
5972 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5973 || need_resched() || signal_pending(current)) {
5974 vcpu->mode = OUTSIDE_GUEST_MODE;
5975 smp_wmb();
5976 local_irq_enable();
5977 preempt_enable();
5978 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5979 r = 1;
5980 goto cancel_injection;
5981 }
5982
5983 if (req_immediate_exit)
5984 smp_send_reschedule(vcpu->cpu);
5985
5986 kvm_guest_enter();
5987
5988 if (unlikely(vcpu->arch.switch_db_regs)) {
5989 set_debugreg(0, 7);
5990 set_debugreg(vcpu->arch.eff_db[0], 0);
5991 set_debugreg(vcpu->arch.eff_db[1], 1);
5992 set_debugreg(vcpu->arch.eff_db[2], 2);
5993 set_debugreg(vcpu->arch.eff_db[3], 3);
5994 }
5995
5996 trace_kvm_entry(vcpu->vcpu_id);
5997 kvm_x86_ops->run(vcpu);
5998
5999 /*
6000 * If the guest has used debug registers, at least dr7
6001 * will be disabled while returning to the host.
6002 * If we don't have active breakpoints in the host, we don't
6003 * care about the messed up debug address registers. But if
6004 * we have some of them active, restore the old state.
6005 */
6006 if (hw_breakpoint_active())
6007 hw_breakpoint_restore();
6008
6009 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6010 native_read_tsc());
6011
6012 vcpu->mode = OUTSIDE_GUEST_MODE;
6013 smp_wmb();
6014
6015 /* Interrupt is enabled by handle_external_intr() */
6016 kvm_x86_ops->handle_external_intr(vcpu);
6017
6018 ++vcpu->stat.exits;
6019
6020 /*
6021 * We must have an instruction between local_irq_enable() and
6022 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6023 * the interrupt shadow. The stat.exits increment will do nicely.
6024 * But we need to prevent reordering, hence this barrier():
6025 */
6026 barrier();
6027
6028 kvm_guest_exit();
6029
6030 preempt_enable();
6031
6032 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6033
6034 /*
6035 * Profile KVM exit RIPs:
6036 */
6037 if (unlikely(prof_on == KVM_PROFILING)) {
6038 unsigned long rip = kvm_rip_read(vcpu);
6039 profile_hit(KVM_PROFILING, (void *)rip);
6040 }
6041
6042 if (unlikely(vcpu->arch.tsc_always_catchup))
6043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6044
6045 if (vcpu->arch.apic_attention)
6046 kvm_lapic_sync_from_vapic(vcpu);
6047
6048 r = kvm_x86_ops->handle_exit(vcpu);
6049 return r;
6050
6051 cancel_injection:
6052 kvm_x86_ops->cancel_injection(vcpu);
6053 if (unlikely(vcpu->arch.apic_attention))
6054 kvm_lapic_sync_from_vapic(vcpu);
6055 out:
6056 return r;
6057 }
6058
6059
6060 static int __vcpu_run(struct kvm_vcpu *vcpu)
6061 {
6062 int r;
6063 struct kvm *kvm = vcpu->kvm;
6064
6065 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6066
6067 r = 1;
6068 while (r > 0) {
6069 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6070 !vcpu->arch.apf.halted)
6071 r = vcpu_enter_guest(vcpu);
6072 else {
6073 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6074 kvm_vcpu_block(vcpu);
6075 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6076 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6077 kvm_apic_accept_events(vcpu);
6078 switch(vcpu->arch.mp_state) {
6079 case KVM_MP_STATE_HALTED:
6080 vcpu->arch.pv.pv_unhalted = false;
6081 vcpu->arch.mp_state =
6082 KVM_MP_STATE_RUNNABLE;
6083 case KVM_MP_STATE_RUNNABLE:
6084 vcpu->arch.apf.halted = false;
6085 break;
6086 case KVM_MP_STATE_INIT_RECEIVED:
6087 break;
6088 default:
6089 r = -EINTR;
6090 break;
6091 }
6092 }
6093 }
6094
6095 if (r <= 0)
6096 break;
6097
6098 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6099 if (kvm_cpu_has_pending_timer(vcpu))
6100 kvm_inject_pending_timer_irqs(vcpu);
6101
6102 if (dm_request_for_irq_injection(vcpu)) {
6103 r = -EINTR;
6104 vcpu->run->exit_reason = KVM_EXIT_INTR;
6105 ++vcpu->stat.request_irq_exits;
6106 }
6107
6108 kvm_check_async_pf_completion(vcpu);
6109
6110 if (signal_pending(current)) {
6111 r = -EINTR;
6112 vcpu->run->exit_reason = KVM_EXIT_INTR;
6113 ++vcpu->stat.signal_exits;
6114 }
6115 if (need_resched()) {
6116 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6117 cond_resched();
6118 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6119 }
6120 }
6121
6122 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6123
6124 return r;
6125 }
6126
6127 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6128 {
6129 int r;
6130 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6131 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6132 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6133 if (r != EMULATE_DONE)
6134 return 0;
6135 return 1;
6136 }
6137
6138 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6139 {
6140 BUG_ON(!vcpu->arch.pio.count);
6141
6142 return complete_emulated_io(vcpu);
6143 }
6144
6145 /*
6146 * Implements the following, as a state machine:
6147 *
6148 * read:
6149 * for each fragment
6150 * for each mmio piece in the fragment
6151 * write gpa, len
6152 * exit
6153 * copy data
6154 * execute insn
6155 *
6156 * write:
6157 * for each fragment
6158 * for each mmio piece in the fragment
6159 * write gpa, len
6160 * copy data
6161 * exit
6162 */
6163 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6164 {
6165 struct kvm_run *run = vcpu->run;
6166 struct kvm_mmio_fragment *frag;
6167 unsigned len;
6168
6169 BUG_ON(!vcpu->mmio_needed);
6170
6171 /* Complete previous fragment */
6172 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6173 len = min(8u, frag->len);
6174 if (!vcpu->mmio_is_write)
6175 memcpy(frag->data, run->mmio.data, len);
6176
6177 if (frag->len <= 8) {
6178 /* Switch to the next fragment. */
6179 frag++;
6180 vcpu->mmio_cur_fragment++;
6181 } else {
6182 /* Go forward to the next mmio piece. */
6183 frag->data += len;
6184 frag->gpa += len;
6185 frag->len -= len;
6186 }
6187
6188 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6189 vcpu->mmio_needed = 0;
6190
6191 /* FIXME: return into emulator if single-stepping. */
6192 if (vcpu->mmio_is_write)
6193 return 1;
6194 vcpu->mmio_read_completed = 1;
6195 return complete_emulated_io(vcpu);
6196 }
6197
6198 run->exit_reason = KVM_EXIT_MMIO;
6199 run->mmio.phys_addr = frag->gpa;
6200 if (vcpu->mmio_is_write)
6201 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6202 run->mmio.len = min(8u, frag->len);
6203 run->mmio.is_write = vcpu->mmio_is_write;
6204 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6205 return 0;
6206 }
6207
6208
6209 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6210 {
6211 int r;
6212 sigset_t sigsaved;
6213
6214 if (!tsk_used_math(current) && init_fpu(current))
6215 return -ENOMEM;
6216
6217 if (vcpu->sigset_active)
6218 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6219
6220 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6221 kvm_vcpu_block(vcpu);
6222 kvm_apic_accept_events(vcpu);
6223 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6224 r = -EAGAIN;
6225 goto out;
6226 }
6227
6228 /* re-sync apic's tpr */
6229 if (!irqchip_in_kernel(vcpu->kvm)) {
6230 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6231 r = -EINVAL;
6232 goto out;
6233 }
6234 }
6235
6236 if (unlikely(vcpu->arch.complete_userspace_io)) {
6237 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6238 vcpu->arch.complete_userspace_io = NULL;
6239 r = cui(vcpu);
6240 if (r <= 0)
6241 goto out;
6242 } else
6243 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6244
6245 r = __vcpu_run(vcpu);
6246
6247 out:
6248 post_kvm_run_save(vcpu);
6249 if (vcpu->sigset_active)
6250 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6251
6252 return r;
6253 }
6254
6255 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6256 {
6257 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6258 /*
6259 * We are here if userspace calls get_regs() in the middle of
6260 * instruction emulation. Registers state needs to be copied
6261 * back from emulation context to vcpu. Userspace shouldn't do
6262 * that usually, but some bad designed PV devices (vmware
6263 * backdoor interface) need this to work
6264 */
6265 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6266 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6267 }
6268 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6269 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6270 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6271 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6272 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6273 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6274 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6275 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6276 #ifdef CONFIG_X86_64
6277 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6278 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6279 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6280 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6281 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6282 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6283 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6284 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6285 #endif
6286
6287 regs->rip = kvm_rip_read(vcpu);
6288 regs->rflags = kvm_get_rflags(vcpu);
6289
6290 return 0;
6291 }
6292
6293 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6294 {
6295 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6296 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6297
6298 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6299 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6300 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6301 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6302 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6303 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6304 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6305 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6306 #ifdef CONFIG_X86_64
6307 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6308 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6309 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6310 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6311 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6312 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6313 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6314 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6315 #endif
6316
6317 kvm_rip_write(vcpu, regs->rip);
6318 kvm_set_rflags(vcpu, regs->rflags);
6319
6320 vcpu->arch.exception.pending = false;
6321
6322 kvm_make_request(KVM_REQ_EVENT, vcpu);
6323
6324 return 0;
6325 }
6326
6327 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6328 {
6329 struct kvm_segment cs;
6330
6331 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6332 *db = cs.db;
6333 *l = cs.l;
6334 }
6335 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6336
6337 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6338 struct kvm_sregs *sregs)
6339 {
6340 struct desc_ptr dt;
6341
6342 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6343 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6344 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6345 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6346 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6347 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6348
6349 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6350 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6351
6352 kvm_x86_ops->get_idt(vcpu, &dt);
6353 sregs->idt.limit = dt.size;
6354 sregs->idt.base = dt.address;
6355 kvm_x86_ops->get_gdt(vcpu, &dt);
6356 sregs->gdt.limit = dt.size;
6357 sregs->gdt.base = dt.address;
6358
6359 sregs->cr0 = kvm_read_cr0(vcpu);
6360 sregs->cr2 = vcpu->arch.cr2;
6361 sregs->cr3 = kvm_read_cr3(vcpu);
6362 sregs->cr4 = kvm_read_cr4(vcpu);
6363 sregs->cr8 = kvm_get_cr8(vcpu);
6364 sregs->efer = vcpu->arch.efer;
6365 sregs->apic_base = kvm_get_apic_base(vcpu);
6366
6367 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6368
6369 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6370 set_bit(vcpu->arch.interrupt.nr,
6371 (unsigned long *)sregs->interrupt_bitmap);
6372
6373 return 0;
6374 }
6375
6376 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6377 struct kvm_mp_state *mp_state)
6378 {
6379 kvm_apic_accept_events(vcpu);
6380 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6381 vcpu->arch.pv.pv_unhalted)
6382 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6383 else
6384 mp_state->mp_state = vcpu->arch.mp_state;
6385
6386 return 0;
6387 }
6388
6389 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6390 struct kvm_mp_state *mp_state)
6391 {
6392 if (!kvm_vcpu_has_lapic(vcpu) &&
6393 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6394 return -EINVAL;
6395
6396 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6397 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6398 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6399 } else
6400 vcpu->arch.mp_state = mp_state->mp_state;
6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
6402 return 0;
6403 }
6404
6405 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6406 int reason, bool has_error_code, u32 error_code)
6407 {
6408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6409 int ret;
6410
6411 init_emulate_ctxt(vcpu);
6412
6413 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6414 has_error_code, error_code);
6415
6416 if (ret)
6417 return EMULATE_FAIL;
6418
6419 kvm_rip_write(vcpu, ctxt->eip);
6420 kvm_set_rflags(vcpu, ctxt->eflags);
6421 kvm_make_request(KVM_REQ_EVENT, vcpu);
6422 return EMULATE_DONE;
6423 }
6424 EXPORT_SYMBOL_GPL(kvm_task_switch);
6425
6426 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6427 struct kvm_sregs *sregs)
6428 {
6429 struct msr_data apic_base_msr;
6430 int mmu_reset_needed = 0;
6431 int pending_vec, max_bits, idx;
6432 struct desc_ptr dt;
6433
6434 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6435 return -EINVAL;
6436
6437 dt.size = sregs->idt.limit;
6438 dt.address = sregs->idt.base;
6439 kvm_x86_ops->set_idt(vcpu, &dt);
6440 dt.size = sregs->gdt.limit;
6441 dt.address = sregs->gdt.base;
6442 kvm_x86_ops->set_gdt(vcpu, &dt);
6443
6444 vcpu->arch.cr2 = sregs->cr2;
6445 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6446 vcpu->arch.cr3 = sregs->cr3;
6447 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6448
6449 kvm_set_cr8(vcpu, sregs->cr8);
6450
6451 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6452 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6453 apic_base_msr.data = sregs->apic_base;
6454 apic_base_msr.host_initiated = true;
6455 kvm_set_apic_base(vcpu, &apic_base_msr);
6456
6457 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6458 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6459 vcpu->arch.cr0 = sregs->cr0;
6460
6461 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6462 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6463 if (sregs->cr4 & X86_CR4_OSXSAVE)
6464 kvm_update_cpuid(vcpu);
6465
6466 idx = srcu_read_lock(&vcpu->kvm->srcu);
6467 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6468 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6469 mmu_reset_needed = 1;
6470 }
6471 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6472
6473 if (mmu_reset_needed)
6474 kvm_mmu_reset_context(vcpu);
6475
6476 max_bits = KVM_NR_INTERRUPTS;
6477 pending_vec = find_first_bit(
6478 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6479 if (pending_vec < max_bits) {
6480 kvm_queue_interrupt(vcpu, pending_vec, false);
6481 pr_debug("Set back pending irq %d\n", pending_vec);
6482 }
6483
6484 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6485 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6486 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6487 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6488 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6489 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6490
6491 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6492 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6493
6494 update_cr8_intercept(vcpu);
6495
6496 /* Older userspace won't unhalt the vcpu on reset. */
6497 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6498 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6499 !is_protmode(vcpu))
6500 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6501
6502 kvm_make_request(KVM_REQ_EVENT, vcpu);
6503
6504 return 0;
6505 }
6506
6507 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6508 struct kvm_guest_debug *dbg)
6509 {
6510 unsigned long rflags;
6511 int i, r;
6512
6513 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6514 r = -EBUSY;
6515 if (vcpu->arch.exception.pending)
6516 goto out;
6517 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6518 kvm_queue_exception(vcpu, DB_VECTOR);
6519 else
6520 kvm_queue_exception(vcpu, BP_VECTOR);
6521 }
6522
6523 /*
6524 * Read rflags as long as potentially injected trace flags are still
6525 * filtered out.
6526 */
6527 rflags = kvm_get_rflags(vcpu);
6528
6529 vcpu->guest_debug = dbg->control;
6530 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6531 vcpu->guest_debug = 0;
6532
6533 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6534 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6535 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6536 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6537 } else {
6538 for (i = 0; i < KVM_NR_DB_REGS; i++)
6539 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6540 }
6541 kvm_update_dr7(vcpu);
6542
6543 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6544 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6545 get_segment_base(vcpu, VCPU_SREG_CS);
6546
6547 /*
6548 * Trigger an rflags update that will inject or remove the trace
6549 * flags.
6550 */
6551 kvm_set_rflags(vcpu, rflags);
6552
6553 kvm_x86_ops->update_db_bp_intercept(vcpu);
6554
6555 r = 0;
6556
6557 out:
6558
6559 return r;
6560 }
6561
6562 /*
6563 * Translate a guest virtual address to a guest physical address.
6564 */
6565 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6566 struct kvm_translation *tr)
6567 {
6568 unsigned long vaddr = tr->linear_address;
6569 gpa_t gpa;
6570 int idx;
6571
6572 idx = srcu_read_lock(&vcpu->kvm->srcu);
6573 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6574 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6575 tr->physical_address = gpa;
6576 tr->valid = gpa != UNMAPPED_GVA;
6577 tr->writeable = 1;
6578 tr->usermode = 0;
6579
6580 return 0;
6581 }
6582
6583 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6584 {
6585 struct i387_fxsave_struct *fxsave =
6586 &vcpu->arch.guest_fpu.state->fxsave;
6587
6588 memcpy(fpu->fpr, fxsave->st_space, 128);
6589 fpu->fcw = fxsave->cwd;
6590 fpu->fsw = fxsave->swd;
6591 fpu->ftwx = fxsave->twd;
6592 fpu->last_opcode = fxsave->fop;
6593 fpu->last_ip = fxsave->rip;
6594 fpu->last_dp = fxsave->rdp;
6595 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6596
6597 return 0;
6598 }
6599
6600 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6601 {
6602 struct i387_fxsave_struct *fxsave =
6603 &vcpu->arch.guest_fpu.state->fxsave;
6604
6605 memcpy(fxsave->st_space, fpu->fpr, 128);
6606 fxsave->cwd = fpu->fcw;
6607 fxsave->swd = fpu->fsw;
6608 fxsave->twd = fpu->ftwx;
6609 fxsave->fop = fpu->last_opcode;
6610 fxsave->rip = fpu->last_ip;
6611 fxsave->rdp = fpu->last_dp;
6612 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6613
6614 return 0;
6615 }
6616
6617 int fx_init(struct kvm_vcpu *vcpu)
6618 {
6619 int err;
6620
6621 err = fpu_alloc(&vcpu->arch.guest_fpu);
6622 if (err)
6623 return err;
6624
6625 fpu_finit(&vcpu->arch.guest_fpu);
6626
6627 /*
6628 * Ensure guest xcr0 is valid for loading
6629 */
6630 vcpu->arch.xcr0 = XSTATE_FP;
6631
6632 vcpu->arch.cr0 |= X86_CR0_ET;
6633
6634 return 0;
6635 }
6636 EXPORT_SYMBOL_GPL(fx_init);
6637
6638 static void fx_free(struct kvm_vcpu *vcpu)
6639 {
6640 fpu_free(&vcpu->arch.guest_fpu);
6641 }
6642
6643 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6644 {
6645 if (vcpu->guest_fpu_loaded)
6646 return;
6647
6648 /*
6649 * Restore all possible states in the guest,
6650 * and assume host would use all available bits.
6651 * Guest xcr0 would be loaded later.
6652 */
6653 kvm_put_guest_xcr0(vcpu);
6654 vcpu->guest_fpu_loaded = 1;
6655 __kernel_fpu_begin();
6656 fpu_restore_checking(&vcpu->arch.guest_fpu);
6657 trace_kvm_fpu(1);
6658 }
6659
6660 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6661 {
6662 kvm_put_guest_xcr0(vcpu);
6663
6664 if (!vcpu->guest_fpu_loaded)
6665 return;
6666
6667 vcpu->guest_fpu_loaded = 0;
6668 fpu_save_init(&vcpu->arch.guest_fpu);
6669 __kernel_fpu_end();
6670 ++vcpu->stat.fpu_reload;
6671 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6672 trace_kvm_fpu(0);
6673 }
6674
6675 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6676 {
6677 kvmclock_reset(vcpu);
6678
6679 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6680 fx_free(vcpu);
6681 kvm_x86_ops->vcpu_free(vcpu);
6682 }
6683
6684 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6685 unsigned int id)
6686 {
6687 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6688 printk_once(KERN_WARNING
6689 "kvm: SMP vm created on host with unstable TSC; "
6690 "guest TSC will not be reliable\n");
6691 return kvm_x86_ops->vcpu_create(kvm, id);
6692 }
6693
6694 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6695 {
6696 int r;
6697
6698 vcpu->arch.mtrr_state.have_fixed = 1;
6699 r = vcpu_load(vcpu);
6700 if (r)
6701 return r;
6702 kvm_vcpu_reset(vcpu);
6703 kvm_mmu_setup(vcpu);
6704 vcpu_put(vcpu);
6705
6706 return r;
6707 }
6708
6709 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6710 {
6711 int r;
6712 struct msr_data msr;
6713
6714 r = vcpu_load(vcpu);
6715 if (r)
6716 return r;
6717 msr.data = 0x0;
6718 msr.index = MSR_IA32_TSC;
6719 msr.host_initiated = true;
6720 kvm_write_tsc(vcpu, &msr);
6721 vcpu_put(vcpu);
6722
6723 return r;
6724 }
6725
6726 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6727 {
6728 int r;
6729 vcpu->arch.apf.msr_val = 0;
6730
6731 r = vcpu_load(vcpu);
6732 BUG_ON(r);
6733 kvm_mmu_unload(vcpu);
6734 vcpu_put(vcpu);
6735
6736 fx_free(vcpu);
6737 kvm_x86_ops->vcpu_free(vcpu);
6738 }
6739
6740 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6741 {
6742 atomic_set(&vcpu->arch.nmi_queued, 0);
6743 vcpu->arch.nmi_pending = 0;
6744 vcpu->arch.nmi_injected = false;
6745
6746 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6747 vcpu->arch.dr6 = DR6_FIXED_1;
6748 kvm_update_dr6(vcpu);
6749 vcpu->arch.dr7 = DR7_FIXED_1;
6750 kvm_update_dr7(vcpu);
6751
6752 kvm_make_request(KVM_REQ_EVENT, vcpu);
6753 vcpu->arch.apf.msr_val = 0;
6754 vcpu->arch.st.msr_val = 0;
6755
6756 kvmclock_reset(vcpu);
6757
6758 kvm_clear_async_pf_completion_queue(vcpu);
6759 kvm_async_pf_hash_reset(vcpu);
6760 vcpu->arch.apf.halted = false;
6761
6762 kvm_pmu_reset(vcpu);
6763
6764 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6765 vcpu->arch.regs_avail = ~0;
6766 vcpu->arch.regs_dirty = ~0;
6767
6768 kvm_x86_ops->vcpu_reset(vcpu);
6769 }
6770
6771 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6772 {
6773 struct kvm_segment cs;
6774
6775 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6776 cs.selector = vector << 8;
6777 cs.base = vector << 12;
6778 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6779 kvm_rip_write(vcpu, 0);
6780 }
6781
6782 int kvm_arch_hardware_enable(void *garbage)
6783 {
6784 struct kvm *kvm;
6785 struct kvm_vcpu *vcpu;
6786 int i;
6787 int ret;
6788 u64 local_tsc;
6789 u64 max_tsc = 0;
6790 bool stable, backwards_tsc = false;
6791
6792 kvm_shared_msr_cpu_online();
6793 ret = kvm_x86_ops->hardware_enable(garbage);
6794 if (ret != 0)
6795 return ret;
6796
6797 local_tsc = native_read_tsc();
6798 stable = !check_tsc_unstable();
6799 list_for_each_entry(kvm, &vm_list, vm_list) {
6800 kvm_for_each_vcpu(i, vcpu, kvm) {
6801 if (!stable && vcpu->cpu == smp_processor_id())
6802 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6803 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6804 backwards_tsc = true;
6805 if (vcpu->arch.last_host_tsc > max_tsc)
6806 max_tsc = vcpu->arch.last_host_tsc;
6807 }
6808 }
6809 }
6810
6811 /*
6812 * Sometimes, even reliable TSCs go backwards. This happens on
6813 * platforms that reset TSC during suspend or hibernate actions, but
6814 * maintain synchronization. We must compensate. Fortunately, we can
6815 * detect that condition here, which happens early in CPU bringup,
6816 * before any KVM threads can be running. Unfortunately, we can't
6817 * bring the TSCs fully up to date with real time, as we aren't yet far
6818 * enough into CPU bringup that we know how much real time has actually
6819 * elapsed; our helper function, get_kernel_ns() will be using boot
6820 * variables that haven't been updated yet.
6821 *
6822 * So we simply find the maximum observed TSC above, then record the
6823 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6824 * the adjustment will be applied. Note that we accumulate
6825 * adjustments, in case multiple suspend cycles happen before some VCPU
6826 * gets a chance to run again. In the event that no KVM threads get a
6827 * chance to run, we will miss the entire elapsed period, as we'll have
6828 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6829 * loose cycle time. This isn't too big a deal, since the loss will be
6830 * uniform across all VCPUs (not to mention the scenario is extremely
6831 * unlikely). It is possible that a second hibernate recovery happens
6832 * much faster than a first, causing the observed TSC here to be
6833 * smaller; this would require additional padding adjustment, which is
6834 * why we set last_host_tsc to the local tsc observed here.
6835 *
6836 * N.B. - this code below runs only on platforms with reliable TSC,
6837 * as that is the only way backwards_tsc is set above. Also note
6838 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6839 * have the same delta_cyc adjustment applied if backwards_tsc
6840 * is detected. Note further, this adjustment is only done once,
6841 * as we reset last_host_tsc on all VCPUs to stop this from being
6842 * called multiple times (one for each physical CPU bringup).
6843 *
6844 * Platforms with unreliable TSCs don't have to deal with this, they
6845 * will be compensated by the logic in vcpu_load, which sets the TSC to
6846 * catchup mode. This will catchup all VCPUs to real time, but cannot
6847 * guarantee that they stay in perfect synchronization.
6848 */
6849 if (backwards_tsc) {
6850 u64 delta_cyc = max_tsc - local_tsc;
6851 list_for_each_entry(kvm, &vm_list, vm_list) {
6852 kvm_for_each_vcpu(i, vcpu, kvm) {
6853 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6854 vcpu->arch.last_host_tsc = local_tsc;
6855 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6856 &vcpu->requests);
6857 }
6858
6859 /*
6860 * We have to disable TSC offset matching.. if you were
6861 * booting a VM while issuing an S4 host suspend....
6862 * you may have some problem. Solving this issue is
6863 * left as an exercise to the reader.
6864 */
6865 kvm->arch.last_tsc_nsec = 0;
6866 kvm->arch.last_tsc_write = 0;
6867 }
6868
6869 }
6870 return 0;
6871 }
6872
6873 void kvm_arch_hardware_disable(void *garbage)
6874 {
6875 kvm_x86_ops->hardware_disable(garbage);
6876 drop_user_return_notifiers(garbage);
6877 }
6878
6879 int kvm_arch_hardware_setup(void)
6880 {
6881 return kvm_x86_ops->hardware_setup();
6882 }
6883
6884 void kvm_arch_hardware_unsetup(void)
6885 {
6886 kvm_x86_ops->hardware_unsetup();
6887 }
6888
6889 void kvm_arch_check_processor_compat(void *rtn)
6890 {
6891 kvm_x86_ops->check_processor_compatibility(rtn);
6892 }
6893
6894 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6895 {
6896 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6897 }
6898
6899 struct static_key kvm_no_apic_vcpu __read_mostly;
6900
6901 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6902 {
6903 struct page *page;
6904 struct kvm *kvm;
6905 int r;
6906
6907 BUG_ON(vcpu->kvm == NULL);
6908 kvm = vcpu->kvm;
6909
6910 vcpu->arch.pv.pv_unhalted = false;
6911 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6912 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6913 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6914 else
6915 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6916
6917 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6918 if (!page) {
6919 r = -ENOMEM;
6920 goto fail;
6921 }
6922 vcpu->arch.pio_data = page_address(page);
6923
6924 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6925
6926 r = kvm_mmu_create(vcpu);
6927 if (r < 0)
6928 goto fail_free_pio_data;
6929
6930 if (irqchip_in_kernel(kvm)) {
6931 r = kvm_create_lapic(vcpu);
6932 if (r < 0)
6933 goto fail_mmu_destroy;
6934 } else
6935 static_key_slow_inc(&kvm_no_apic_vcpu);
6936
6937 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6938 GFP_KERNEL);
6939 if (!vcpu->arch.mce_banks) {
6940 r = -ENOMEM;
6941 goto fail_free_lapic;
6942 }
6943 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6944
6945 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6946 r = -ENOMEM;
6947 goto fail_free_mce_banks;
6948 }
6949
6950 r = fx_init(vcpu);
6951 if (r)
6952 goto fail_free_wbinvd_dirty_mask;
6953
6954 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6955 vcpu->arch.pv_time_enabled = false;
6956
6957 vcpu->arch.guest_supported_xcr0 = 0;
6958 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
6959
6960 kvm_async_pf_hash_reset(vcpu);
6961 kvm_pmu_init(vcpu);
6962
6963 return 0;
6964 fail_free_wbinvd_dirty_mask:
6965 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6966 fail_free_mce_banks:
6967 kfree(vcpu->arch.mce_banks);
6968 fail_free_lapic:
6969 kvm_free_lapic(vcpu);
6970 fail_mmu_destroy:
6971 kvm_mmu_destroy(vcpu);
6972 fail_free_pio_data:
6973 free_page((unsigned long)vcpu->arch.pio_data);
6974 fail:
6975 return r;
6976 }
6977
6978 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6979 {
6980 int idx;
6981
6982 kvm_pmu_destroy(vcpu);
6983 kfree(vcpu->arch.mce_banks);
6984 kvm_free_lapic(vcpu);
6985 idx = srcu_read_lock(&vcpu->kvm->srcu);
6986 kvm_mmu_destroy(vcpu);
6987 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6988 free_page((unsigned long)vcpu->arch.pio_data);
6989 if (!irqchip_in_kernel(vcpu->kvm))
6990 static_key_slow_dec(&kvm_no_apic_vcpu);
6991 }
6992
6993 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6994 {
6995 if (type)
6996 return -EINVAL;
6997
6998 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6999 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7000 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7001 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7002
7003 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7004 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7005 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7006 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7007 &kvm->arch.irq_sources_bitmap);
7008
7009 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7010 mutex_init(&kvm->arch.apic_map_lock);
7011 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7012
7013 pvclock_update_vm_gtod_copy(kvm);
7014
7015 return 0;
7016 }
7017
7018 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7019 {
7020 int r;
7021 r = vcpu_load(vcpu);
7022 BUG_ON(r);
7023 kvm_mmu_unload(vcpu);
7024 vcpu_put(vcpu);
7025 }
7026
7027 static void kvm_free_vcpus(struct kvm *kvm)
7028 {
7029 unsigned int i;
7030 struct kvm_vcpu *vcpu;
7031
7032 /*
7033 * Unpin any mmu pages first.
7034 */
7035 kvm_for_each_vcpu(i, vcpu, kvm) {
7036 kvm_clear_async_pf_completion_queue(vcpu);
7037 kvm_unload_vcpu_mmu(vcpu);
7038 }
7039 kvm_for_each_vcpu(i, vcpu, kvm)
7040 kvm_arch_vcpu_free(vcpu);
7041
7042 mutex_lock(&kvm->lock);
7043 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7044 kvm->vcpus[i] = NULL;
7045
7046 atomic_set(&kvm->online_vcpus, 0);
7047 mutex_unlock(&kvm->lock);
7048 }
7049
7050 void kvm_arch_sync_events(struct kvm *kvm)
7051 {
7052 kvm_free_all_assigned_devices(kvm);
7053 kvm_free_pit(kvm);
7054 }
7055
7056 void kvm_arch_destroy_vm(struct kvm *kvm)
7057 {
7058 if (current->mm == kvm->mm) {
7059 /*
7060 * Free memory regions allocated on behalf of userspace,
7061 * unless the the memory map has changed due to process exit
7062 * or fd copying.
7063 */
7064 struct kvm_userspace_memory_region mem;
7065 memset(&mem, 0, sizeof(mem));
7066 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7067 kvm_set_memory_region(kvm, &mem);
7068
7069 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071
7072 mem.slot = TSS_PRIVATE_MEMSLOT;
7073 kvm_set_memory_region(kvm, &mem);
7074 }
7075 kvm_iommu_unmap_guest(kvm);
7076 kfree(kvm->arch.vpic);
7077 kfree(kvm->arch.vioapic);
7078 kvm_free_vcpus(kvm);
7079 if (kvm->arch.apic_access_page)
7080 put_page(kvm->arch.apic_access_page);
7081 if (kvm->arch.ept_identity_pagetable)
7082 put_page(kvm->arch.ept_identity_pagetable);
7083 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7084 }
7085
7086 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7087 struct kvm_memory_slot *dont)
7088 {
7089 int i;
7090
7091 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7092 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7093 kvm_kvfree(free->arch.rmap[i]);
7094 free->arch.rmap[i] = NULL;
7095 }
7096 if (i == 0)
7097 continue;
7098
7099 if (!dont || free->arch.lpage_info[i - 1] !=
7100 dont->arch.lpage_info[i - 1]) {
7101 kvm_kvfree(free->arch.lpage_info[i - 1]);
7102 free->arch.lpage_info[i - 1] = NULL;
7103 }
7104 }
7105 }
7106
7107 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7108 unsigned long npages)
7109 {
7110 int i;
7111
7112 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7113 unsigned long ugfn;
7114 int lpages;
7115 int level = i + 1;
7116
7117 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7118 slot->base_gfn, level) + 1;
7119
7120 slot->arch.rmap[i] =
7121 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7122 if (!slot->arch.rmap[i])
7123 goto out_free;
7124 if (i == 0)
7125 continue;
7126
7127 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7128 sizeof(*slot->arch.lpage_info[i - 1]));
7129 if (!slot->arch.lpage_info[i - 1])
7130 goto out_free;
7131
7132 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7133 slot->arch.lpage_info[i - 1][0].write_count = 1;
7134 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7135 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7136 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7137 /*
7138 * If the gfn and userspace address are not aligned wrt each
7139 * other, or if explicitly asked to, disable large page
7140 * support for this slot
7141 */
7142 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7143 !kvm_largepages_enabled()) {
7144 unsigned long j;
7145
7146 for (j = 0; j < lpages; ++j)
7147 slot->arch.lpage_info[i - 1][j].write_count = 1;
7148 }
7149 }
7150
7151 return 0;
7152
7153 out_free:
7154 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7155 kvm_kvfree(slot->arch.rmap[i]);
7156 slot->arch.rmap[i] = NULL;
7157 if (i == 0)
7158 continue;
7159
7160 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7161 slot->arch.lpage_info[i - 1] = NULL;
7162 }
7163 return -ENOMEM;
7164 }
7165
7166 void kvm_arch_memslots_updated(struct kvm *kvm)
7167 {
7168 /*
7169 * memslots->generation has been incremented.
7170 * mmio generation may have reached its maximum value.
7171 */
7172 kvm_mmu_invalidate_mmio_sptes(kvm);
7173 }
7174
7175 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7176 struct kvm_memory_slot *memslot,
7177 struct kvm_userspace_memory_region *mem,
7178 enum kvm_mr_change change)
7179 {
7180 /*
7181 * Only private memory slots need to be mapped here since
7182 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7183 */
7184 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7185 unsigned long userspace_addr;
7186
7187 /*
7188 * MAP_SHARED to prevent internal slot pages from being moved
7189 * by fork()/COW.
7190 */
7191 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7192 PROT_READ | PROT_WRITE,
7193 MAP_SHARED | MAP_ANONYMOUS, 0);
7194
7195 if (IS_ERR((void *)userspace_addr))
7196 return PTR_ERR((void *)userspace_addr);
7197
7198 memslot->userspace_addr = userspace_addr;
7199 }
7200
7201 return 0;
7202 }
7203
7204 void kvm_arch_commit_memory_region(struct kvm *kvm,
7205 struct kvm_userspace_memory_region *mem,
7206 const struct kvm_memory_slot *old,
7207 enum kvm_mr_change change)
7208 {
7209
7210 int nr_mmu_pages = 0;
7211
7212 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7213 int ret;
7214
7215 ret = vm_munmap(old->userspace_addr,
7216 old->npages * PAGE_SIZE);
7217 if (ret < 0)
7218 printk(KERN_WARNING
7219 "kvm_vm_ioctl_set_memory_region: "
7220 "failed to munmap memory\n");
7221 }
7222
7223 if (!kvm->arch.n_requested_mmu_pages)
7224 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7225
7226 if (nr_mmu_pages)
7227 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7228 /*
7229 * Write protect all pages for dirty logging.
7230 * Existing largepage mappings are destroyed here and new ones will
7231 * not be created until the end of the logging.
7232 */
7233 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7234 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7235 }
7236
7237 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7238 {
7239 kvm_mmu_invalidate_zap_all_pages(kvm);
7240 }
7241
7242 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7243 struct kvm_memory_slot *slot)
7244 {
7245 kvm_mmu_invalidate_zap_all_pages(kvm);
7246 }
7247
7248 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7249 {
7250 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7251 !vcpu->arch.apf.halted)
7252 || !list_empty_careful(&vcpu->async_pf.done)
7253 || kvm_apic_has_events(vcpu)
7254 || vcpu->arch.pv.pv_unhalted
7255 || atomic_read(&vcpu->arch.nmi_queued) ||
7256 (kvm_arch_interrupt_allowed(vcpu) &&
7257 kvm_cpu_has_interrupt(vcpu));
7258 }
7259
7260 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7261 {
7262 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7263 }
7264
7265 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7266 {
7267 return kvm_x86_ops->interrupt_allowed(vcpu);
7268 }
7269
7270 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7271 {
7272 unsigned long current_rip = kvm_rip_read(vcpu) +
7273 get_segment_base(vcpu, VCPU_SREG_CS);
7274
7275 return current_rip == linear_rip;
7276 }
7277 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7278
7279 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7280 {
7281 unsigned long rflags;
7282
7283 rflags = kvm_x86_ops->get_rflags(vcpu);
7284 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7285 rflags &= ~X86_EFLAGS_TF;
7286 return rflags;
7287 }
7288 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7289
7290 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7291 {
7292 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7293 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7294 rflags |= X86_EFLAGS_TF;
7295 kvm_x86_ops->set_rflags(vcpu, rflags);
7296 kvm_make_request(KVM_REQ_EVENT, vcpu);
7297 }
7298 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7299
7300 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7301 {
7302 int r;
7303
7304 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7305 work->wakeup_all)
7306 return;
7307
7308 r = kvm_mmu_reload(vcpu);
7309 if (unlikely(r))
7310 return;
7311
7312 if (!vcpu->arch.mmu.direct_map &&
7313 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7314 return;
7315
7316 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7317 }
7318
7319 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7320 {
7321 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7322 }
7323
7324 static inline u32 kvm_async_pf_next_probe(u32 key)
7325 {
7326 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7327 }
7328
7329 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7330 {
7331 u32 key = kvm_async_pf_hash_fn(gfn);
7332
7333 while (vcpu->arch.apf.gfns[key] != ~0)
7334 key = kvm_async_pf_next_probe(key);
7335
7336 vcpu->arch.apf.gfns[key] = gfn;
7337 }
7338
7339 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7340 {
7341 int i;
7342 u32 key = kvm_async_pf_hash_fn(gfn);
7343
7344 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7345 (vcpu->arch.apf.gfns[key] != gfn &&
7346 vcpu->arch.apf.gfns[key] != ~0); i++)
7347 key = kvm_async_pf_next_probe(key);
7348
7349 return key;
7350 }
7351
7352 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7353 {
7354 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7355 }
7356
7357 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7358 {
7359 u32 i, j, k;
7360
7361 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7362 while (true) {
7363 vcpu->arch.apf.gfns[i] = ~0;
7364 do {
7365 j = kvm_async_pf_next_probe(j);
7366 if (vcpu->arch.apf.gfns[j] == ~0)
7367 return;
7368 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7369 /*
7370 * k lies cyclically in ]i,j]
7371 * | i.k.j |
7372 * |....j i.k.| or |.k..j i...|
7373 */
7374 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7375 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7376 i = j;
7377 }
7378 }
7379
7380 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7381 {
7382
7383 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7384 sizeof(val));
7385 }
7386
7387 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7388 struct kvm_async_pf *work)
7389 {
7390 struct x86_exception fault;
7391
7392 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7393 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7394
7395 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7396 (vcpu->arch.apf.send_user_only &&
7397 kvm_x86_ops->get_cpl(vcpu) == 0))
7398 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7399 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7400 fault.vector = PF_VECTOR;
7401 fault.error_code_valid = true;
7402 fault.error_code = 0;
7403 fault.nested_page_fault = false;
7404 fault.address = work->arch.token;
7405 kvm_inject_page_fault(vcpu, &fault);
7406 }
7407 }
7408
7409 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7410 struct kvm_async_pf *work)
7411 {
7412 struct x86_exception fault;
7413
7414 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7415 if (work->wakeup_all)
7416 work->arch.token = ~0; /* broadcast wakeup */
7417 else
7418 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7419
7420 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7421 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7422 fault.vector = PF_VECTOR;
7423 fault.error_code_valid = true;
7424 fault.error_code = 0;
7425 fault.nested_page_fault = false;
7426 fault.address = work->arch.token;
7427 kvm_inject_page_fault(vcpu, &fault);
7428 }
7429 vcpu->arch.apf.halted = false;
7430 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7431 }
7432
7433 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7434 {
7435 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7436 return true;
7437 else
7438 return !kvm_event_needs_reinjection(vcpu) &&
7439 kvm_x86_ops->interrupt_allowed(vcpu);
7440 }
7441
7442 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7443 {
7444 atomic_inc(&kvm->arch.noncoherent_dma_count);
7445 }
7446 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7447
7448 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7449 {
7450 atomic_dec(&kvm->arch.noncoherent_dma_count);
7451 }
7452 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7453
7454 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7455 {
7456 return atomic_read(&kvm->arch.noncoherent_dma_count);
7457 }
7458 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7459
7460 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7461 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7462 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7463 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7464 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7465 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7466 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7467 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7468 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7469 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7470 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7471 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7472 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
This page took 0.263578 seconds and 6 git commands to generate.