projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: Add SMAP support when setting CR4
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 return;
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256 return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261 {
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
280 }
281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
283 asmlinkage void kvm_spurious_fault(void)
284 {
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287 }
288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
290 #define EXCPT_BENIGN 0
291 #define EXCPT_CONTRIBUTORY 1
292 #define EXCPT_PF 2
293
294 static int exception_class(int vector)
295 {
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309 }
310
311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
314 {
315 u32 prev_nr;
316 int class1, class2;
317
318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
326 vcpu->arch.exception.reinject = reinject;
327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351 }
352
353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354 {
355 kvm_multiple_exception(vcpu, nr, false, 0, false);
356 }
357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360 {
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362 }
363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
366 {
367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371 }
372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
373
374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
375 {
376 ++vcpu->stat.pf_guest;
377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
379 }
380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
381
382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
383 {
384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
386 else
387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
388 }
389
390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391 {
392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
394 }
395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398 {
399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404 {
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
409 /*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
414 {
415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
419 }
420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
421
422 /*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430 {
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442 }
443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447 {
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450 }
451
452 /*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
456 {
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
462
463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
471 if (is_present_gpte(pdpte[i]) &&
472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
484 out:
485
486 return ret;
487 }
488 EXPORT_SYMBOL_GPL(load_pdptrs);
489
490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491 {
492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
493 bool changed = true;
494 int offset;
495 gfn_t gfn;
496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
509 if (r < 0)
510 goto out;
511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
512 out:
513
514 return changed;
515 }
516
517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
518 {
519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
523 cr0 |= X86_CR0_ET;
524
525 #ifdef CONFIG_X86_64
526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
528 #endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
531
532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
534
535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539 #ifdef CONFIG_X86_64
540 if ((vcpu->arch.efer & EFER_LME)) {
541 int cs_db, cs_l;
542
543 if (!is_pae(vcpu))
544 return 1;
545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
546 if (cs_l)
547 return 1;
548 } else
549 #endif
550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
551 kvm_read_cr3(vcpu)))
552 return 1;
553 }
554
555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
558 kvm_x86_ops->set_cr0(vcpu, cr0);
559
560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
561 kvm_clear_async_pf_completion_queue(vcpu);
562 kvm_async_pf_hash_reset(vcpu);
563 }
564
565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
567 return 0;
568 }
569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
570
571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
572 {
573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
574 }
575 EXPORT_SYMBOL_GPL(kvm_lmsw);
576
577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578 {
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585 }
586
587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588 {
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594 }
595
596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597 {
598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
600 u64 valid_bits;
601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
617 return 1;
618
619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
622 kvm_put_guest_xcr0(vcpu);
623 vcpu->arch.xcr0 = xcr0;
624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
627 return 0;
628 }
629
630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631 {
632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638 }
639 EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
642 {
643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
648
649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
656 return 1;
657
658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
659 return 1;
660
661 if (is_long_mode(vcpu)) {
662 if (!(cr4 & X86_CR4_PAE))
663 return 1;
664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665 && ((cr4 ^ old_cr4) & pdptr_bits)
666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
667 kvm_read_cr3(vcpu)))
668 return 1;
669
670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671 if (!guest_cpuid_has_pcid(vcpu))
672 return 1;
673
674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
676 return 1;
677 }
678
679 if (kvm_x86_ops->set_cr4(vcpu, cr4))
680 return 1;
681
682 if (((cr4 ^ old_cr4) & pdptr_bits) ||
683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
684 kvm_mmu_reset_context(vcpu);
685
686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
688
689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
690 kvm_update_cpuid(vcpu);
691
692 return 0;
693 }
694 EXPORT_SYMBOL_GPL(kvm_set_cr4);
695
696 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
697 {
698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
699 kvm_mmu_sync_roots(vcpu);
700 kvm_mmu_flush_tlb(vcpu);
701 return 0;
702 }
703
704 if (is_long_mode(vcpu)) {
705 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
706 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
707 return 1;
708 } else
709 if (cr3 & CR3_L_MODE_RESERVED_BITS)
710 return 1;
711 } else {
712 if (is_pae(vcpu)) {
713 if (cr3 & CR3_PAE_RESERVED_BITS)
714 return 1;
715 if (is_paging(vcpu) &&
716 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
717 return 1;
718 }
719 /*
720 * We don't check reserved bits in nonpae mode, because
721 * this isn't enforced, and VMware depends on this.
722 */
723 }
724
725 vcpu->arch.cr3 = cr3;
726 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
727 kvm_mmu_new_cr3(vcpu);
728 return 0;
729 }
730 EXPORT_SYMBOL_GPL(kvm_set_cr3);
731
732 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
733 {
734 if (cr8 & CR8_RESERVED_BITS)
735 return 1;
736 if (irqchip_in_kernel(vcpu->kvm))
737 kvm_lapic_set_tpr(vcpu, cr8);
738 else
739 vcpu->arch.cr8 = cr8;
740 return 0;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_cr8);
743
744 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
745 {
746 if (irqchip_in_kernel(vcpu->kvm))
747 return kvm_lapic_get_cr8(vcpu);
748 else
749 return vcpu->arch.cr8;
750 }
751 EXPORT_SYMBOL_GPL(kvm_get_cr8);
752
753 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
754 {
755 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
756 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
757 }
758
759 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
760 {
761 unsigned long dr7;
762
763 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
764 dr7 = vcpu->arch.guest_debug_dr7;
765 else
766 dr7 = vcpu->arch.dr7;
767 kvm_x86_ops->set_dr7(vcpu, dr7);
768 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
769 if (dr7 & DR7_BP_EN_MASK)
770 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
771 }
772
773 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
774 {
775 switch (dr) {
776 case 0 ... 3:
777 vcpu->arch.db[dr] = val;
778 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
779 vcpu->arch.eff_db[dr] = val;
780 break;
781 case 4:
782 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
783 return 1; /* #UD */
784 /* fall through */
785 case 6:
786 if (val & 0xffffffff00000000ULL)
787 return -1; /* #GP */
788 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
789 kvm_update_dr6(vcpu);
790 break;
791 case 5:
792 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
793 return 1; /* #UD */
794 /* fall through */
795 default: /* 7 */
796 if (val & 0xffffffff00000000ULL)
797 return -1; /* #GP */
798 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
799 kvm_update_dr7(vcpu);
800 break;
801 }
802
803 return 0;
804 }
805
806 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
807 {
808 int res;
809
810 res = __kvm_set_dr(vcpu, dr, val);
811 if (res > 0)
812 kvm_queue_exception(vcpu, UD_VECTOR);
813 else if (res < 0)
814 kvm_inject_gp(vcpu, 0);
815
816 return res;
817 }
818 EXPORT_SYMBOL_GPL(kvm_set_dr);
819
820 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
821 {
822 switch (dr) {
823 case 0 ... 3:
824 *val = vcpu->arch.db[dr];
825 break;
826 case 4:
827 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
828 return 1;
829 /* fall through */
830 case 6:
831 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
832 *val = vcpu->arch.dr6;
833 else
834 *val = kvm_x86_ops->get_dr6(vcpu);
835 break;
836 case 5:
837 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
838 return 1;
839 /* fall through */
840 default: /* 7 */
841 *val = vcpu->arch.dr7;
842 break;
843 }
844
845 return 0;
846 }
847
848 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
849 {
850 if (_kvm_get_dr(vcpu, dr, val)) {
851 kvm_queue_exception(vcpu, UD_VECTOR);
852 return 1;
853 }
854 return 0;
855 }
856 EXPORT_SYMBOL_GPL(kvm_get_dr);
857
858 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
859 {
860 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
861 u64 data;
862 int err;
863
864 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
865 if (err)
866 return err;
867 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
868 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
869 return err;
870 }
871 EXPORT_SYMBOL_GPL(kvm_rdpmc);
872
873 /*
874 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
875 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
876 *
877 * This list is modified at module load time to reflect the
878 * capabilities of the host cpu. This capabilities test skips MSRs that are
879 * kvm-specific. Those are put in the beginning of the list.
880 */
881
882 #define KVM_SAVE_MSRS_BEGIN 12
883 static u32 msrs_to_save[] = {
884 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
885 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
886 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
887 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
888 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
889 MSR_KVM_PV_EOI_EN,
890 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
891 MSR_STAR,
892 #ifdef CONFIG_X86_64
893 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
894 #endif
895 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
896 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
897 };
898
899 static unsigned num_msrs_to_save;
900
901 static const u32 emulated_msrs[] = {
902 MSR_IA32_TSC_ADJUST,
903 MSR_IA32_TSCDEADLINE,
904 MSR_IA32_MISC_ENABLE,
905 MSR_IA32_MCG_STATUS,
906 MSR_IA32_MCG_CTL,
907 };
908
909 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
910 {
911 if (efer & efer_reserved_bits)
912 return false;
913
914 if (efer & EFER_FFXSR) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
918 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
919 return false;
920 }
921
922 if (efer & EFER_SVME) {
923 struct kvm_cpuid_entry2 *feat;
924
925 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
926 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
927 return false;
928 }
929
930 return true;
931 }
932 EXPORT_SYMBOL_GPL(kvm_valid_efer);
933
934 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
935 {
936 u64 old_efer = vcpu->arch.efer;
937
938 if (!kvm_valid_efer(vcpu, efer))
939 return 1;
940
941 if (is_paging(vcpu)
942 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
943 return 1;
944
945 efer &= ~EFER_LMA;
946 efer |= vcpu->arch.efer & EFER_LMA;
947
948 kvm_x86_ops->set_efer(vcpu, efer);
949
950 /* Update reserved bits */
951 if ((efer ^ old_efer) & EFER_NX)
952 kvm_mmu_reset_context(vcpu);
953
954 return 0;
955 }
956
957 void kvm_enable_efer_bits(u64 mask)
958 {
959 efer_reserved_bits &= ~mask;
960 }
961 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
962
963
964 /*
965 * Writes msr value into into the appropriate "register".
966 * Returns 0 on success, non-0 otherwise.
967 * Assumes vcpu_load() was already called.
968 */
969 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
970 {
971 return kvm_x86_ops->set_msr(vcpu, msr);
972 }
973
974 /*
975 * Adapt set_msr() to msr_io()'s calling convention
976 */
977 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
978 {
979 struct msr_data msr;
980
981 msr.data = *data;
982 msr.index = index;
983 msr.host_initiated = true;
984 return kvm_set_msr(vcpu, &msr);
985 }
986
987 #ifdef CONFIG_X86_64
988 struct pvclock_gtod_data {
989 seqcount_t seq;
990
991 struct { /* extract of a clocksource struct */
992 int vclock_mode;
993 cycle_t cycle_last;
994 cycle_t mask;
995 u32 mult;
996 u32 shift;
997 } clock;
998
999 /* open coded 'struct timespec' */
1000 u64 monotonic_time_snsec;
1001 time_t monotonic_time_sec;
1002 };
1003
1004 static struct pvclock_gtod_data pvclock_gtod_data;
1005
1006 static void update_pvclock_gtod(struct timekeeper *tk)
1007 {
1008 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1009
1010 write_seqcount_begin(&vdata->seq);
1011
1012 /* copy pvclock gtod data */
1013 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1014 vdata->clock.cycle_last = tk->clock->cycle_last;
1015 vdata->clock.mask = tk->clock->mask;
1016 vdata->clock.mult = tk->mult;
1017 vdata->clock.shift = tk->shift;
1018
1019 vdata->monotonic_time_sec = tk->xtime_sec
1020 + tk->wall_to_monotonic.tv_sec;
1021 vdata->monotonic_time_snsec = tk->xtime_nsec
1022 + (tk->wall_to_monotonic.tv_nsec
1023 << tk->shift);
1024 while (vdata->monotonic_time_snsec >=
1025 (((u64)NSEC_PER_SEC) << tk->shift)) {
1026 vdata->monotonic_time_snsec -=
1027 ((u64)NSEC_PER_SEC) << tk->shift;
1028 vdata->monotonic_time_sec++;
1029 }
1030
1031 write_seqcount_end(&vdata->seq);
1032 }
1033 #endif
1034
1035
1036 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1037 {
1038 int version;
1039 int r;
1040 struct pvclock_wall_clock wc;
1041 struct timespec boot;
1042
1043 if (!wall_clock)
1044 return;
1045
1046 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1047 if (r)
1048 return;
1049
1050 if (version & 1)
1051 ++version; /* first time write, random junk */
1052
1053 ++version;
1054
1055 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1056
1057 /*
1058 * The guest calculates current wall clock time by adding
1059 * system time (updated by kvm_guest_time_update below) to the
1060 * wall clock specified here. guest system time equals host
1061 * system time for us, thus we must fill in host boot time here.
1062 */
1063 getboottime(&boot);
1064
1065 if (kvm->arch.kvmclock_offset) {
1066 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1067 boot = timespec_sub(boot, ts);
1068 }
1069 wc.sec = boot.tv_sec;
1070 wc.nsec = boot.tv_nsec;
1071 wc.version = version;
1072
1073 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1074
1075 version++;
1076 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1077 }
1078
1079 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1080 {
1081 uint32_t quotient, remainder;
1082
1083 /* Don't try to replace with do_div(), this one calculates
1084 * "(dividend << 32) / divisor" */
1085 __asm__ ( "divl %4"
1086 : "=a" (quotient), "=d" (remainder)
1087 : "0" (0), "1" (dividend), "r" (divisor) );
1088 return quotient;
1089 }
1090
1091 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1092 s8 *pshift, u32 *pmultiplier)
1093 {
1094 uint64_t scaled64;
1095 int32_t shift = 0;
1096 uint64_t tps64;
1097 uint32_t tps32;
1098
1099 tps64 = base_khz * 1000LL;
1100 scaled64 = scaled_khz * 1000LL;
1101 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1102 tps64 >>= 1;
1103 shift--;
1104 }
1105
1106 tps32 = (uint32_t)tps64;
1107 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1108 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1109 scaled64 >>= 1;
1110 else
1111 tps32 <<= 1;
1112 shift++;
1113 }
1114
1115 *pshift = shift;
1116 *pmultiplier = div_frac(scaled64, tps32);
1117
1118 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1119 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1120 }
1121
1122 static inline u64 get_kernel_ns(void)
1123 {
1124 struct timespec ts;
1125
1126 WARN_ON(preemptible());
1127 ktime_get_ts(&ts);
1128 monotonic_to_bootbased(&ts);
1129 return timespec_to_ns(&ts);
1130 }
1131
1132 #ifdef CONFIG_X86_64
1133 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1134 #endif
1135
1136 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1137 unsigned long max_tsc_khz;
1138
1139 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1140 {
1141 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1142 vcpu->arch.virtual_tsc_shift);
1143 }
1144
1145 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1146 {
1147 u64 v = (u64)khz * (1000000 + ppm);
1148 do_div(v, 1000000);
1149 return v;
1150 }
1151
1152 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1153 {
1154 u32 thresh_lo, thresh_hi;
1155 int use_scaling = 0;
1156
1157 /* tsc_khz can be zero if TSC calibration fails */
1158 if (this_tsc_khz == 0)
1159 return;
1160
1161 /* Compute a scale to convert nanoseconds in TSC cycles */
1162 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1163 &vcpu->arch.virtual_tsc_shift,
1164 &vcpu->arch.virtual_tsc_mult);
1165 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1166
1167 /*
1168 * Compute the variation in TSC rate which is acceptable
1169 * within the range of tolerance and decide if the
1170 * rate being applied is within that bounds of the hardware
1171 * rate. If so, no scaling or compensation need be done.
1172 */
1173 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1174 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1175 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1176 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1177 use_scaling = 1;
1178 }
1179 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1180 }
1181
1182 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1183 {
1184 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1185 vcpu->arch.virtual_tsc_mult,
1186 vcpu->arch.virtual_tsc_shift);
1187 tsc += vcpu->arch.this_tsc_write;
1188 return tsc;
1189 }
1190
1191 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1192 {
1193 #ifdef CONFIG_X86_64
1194 bool vcpus_matched;
1195 bool do_request = false;
1196 struct kvm_arch *ka = &vcpu->kvm->arch;
1197 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1198
1199 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1200 atomic_read(&vcpu->kvm->online_vcpus));
1201
1202 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1203 if (!ka->use_master_clock)
1204 do_request = 1;
1205
1206 if (!vcpus_matched && ka->use_master_clock)
1207 do_request = 1;
1208
1209 if (do_request)
1210 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1211
1212 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1213 atomic_read(&vcpu->kvm->online_vcpus),
1214 ka->use_master_clock, gtod->clock.vclock_mode);
1215 #endif
1216 }
1217
1218 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1219 {
1220 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1221 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1222 }
1223
1224 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1225 {
1226 struct kvm *kvm = vcpu->kvm;
1227 u64 offset, ns, elapsed;
1228 unsigned long flags;
1229 s64 usdiff;
1230 bool matched;
1231 u64 data = msr->data;
1232
1233 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1234 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1235 ns = get_kernel_ns();
1236 elapsed = ns - kvm->arch.last_tsc_nsec;
1237
1238 if (vcpu->arch.virtual_tsc_khz) {
1239 int faulted = 0;
1240
1241 /* n.b - signed multiplication and division required */
1242 usdiff = data - kvm->arch.last_tsc_write;
1243 #ifdef CONFIG_X86_64
1244 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1245 #else
1246 /* do_div() only does unsigned */
1247 asm("1: idivl %[divisor]\n"
1248 "2: xor %%edx, %%edx\n"
1249 " movl $0, %[faulted]\n"
1250 "3:\n"
1251 ".section .fixup,\"ax\"\n"
1252 "4: movl $1, %[faulted]\n"
1253 " jmp 3b\n"
1254 ".previous\n"
1255
1256 _ASM_EXTABLE(1b, 4b)
1257
1258 : "=A"(usdiff), [faulted] "=r" (faulted)
1259 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1260
1261 #endif
1262 do_div(elapsed, 1000);
1263 usdiff -= elapsed;
1264 if (usdiff < 0)
1265 usdiff = -usdiff;
1266
1267 /* idivl overflow => difference is larger than USEC_PER_SEC */
1268 if (faulted)
1269 usdiff = USEC_PER_SEC;
1270 } else
1271 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1272
1273 /*
1274 * Special case: TSC write with a small delta (1 second) of virtual
1275 * cycle time against real time is interpreted as an attempt to
1276 * synchronize the CPU.
1277 *
1278 * For a reliable TSC, we can match TSC offsets, and for an unstable
1279 * TSC, we add elapsed time in this computation. We could let the
1280 * compensation code attempt to catch up if we fall behind, but
1281 * it's better to try to match offsets from the beginning.
1282 */
1283 if (usdiff < USEC_PER_SEC &&
1284 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1285 if (!check_tsc_unstable()) {
1286 offset = kvm->arch.cur_tsc_offset;
1287 pr_debug("kvm: matched tsc offset for %llu\n", data);
1288 } else {
1289 u64 delta = nsec_to_cycles(vcpu, elapsed);
1290 data += delta;
1291 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1292 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1293 }
1294 matched = true;
1295 } else {
1296 /*
1297 * We split periods of matched TSC writes into generations.
1298 * For each generation, we track the original measured
1299 * nanosecond time, offset, and write, so if TSCs are in
1300 * sync, we can match exact offset, and if not, we can match
1301 * exact software computation in compute_guest_tsc()
1302 *
1303 * These values are tracked in kvm->arch.cur_xxx variables.
1304 */
1305 kvm->arch.cur_tsc_generation++;
1306 kvm->arch.cur_tsc_nsec = ns;
1307 kvm->arch.cur_tsc_write = data;
1308 kvm->arch.cur_tsc_offset = offset;
1309 matched = false;
1310 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1311 kvm->arch.cur_tsc_generation, data);
1312 }
1313
1314 /*
1315 * We also track th most recent recorded KHZ, write and time to
1316 * allow the matching interval to be extended at each write.
1317 */
1318 kvm->arch.last_tsc_nsec = ns;
1319 kvm->arch.last_tsc_write = data;
1320 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1321
1322 vcpu->arch.last_guest_tsc = data;
1323
1324 /* Keep track of which generation this VCPU has synchronized to */
1325 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1326 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1327 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1328
1329 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1330 update_ia32_tsc_adjust_msr(vcpu, offset);
1331 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1332 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1333
1334 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1335 if (matched)
1336 kvm->arch.nr_vcpus_matched_tsc++;
1337 else
1338 kvm->arch.nr_vcpus_matched_tsc = 0;
1339
1340 kvm_track_tsc_matching(vcpu);
1341 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1342 }
1343
1344 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1345
1346 #ifdef CONFIG_X86_64
1347
1348 static cycle_t read_tsc(void)
1349 {
1350 cycle_t ret;
1351 u64 last;
1352
1353 /*
1354 * Empirically, a fence (of type that depends on the CPU)
1355 * before rdtsc is enough to ensure that rdtsc is ordered
1356 * with respect to loads. The various CPU manuals are unclear
1357 * as to whether rdtsc can be reordered with later loads,
1358 * but no one has ever seen it happen.
1359 */
1360 rdtsc_barrier();
1361 ret = (cycle_t)vget_cycles();
1362
1363 last = pvclock_gtod_data.clock.cycle_last;
1364
1365 if (likely(ret >= last))
1366 return ret;
1367
1368 /*
1369 * GCC likes to generate cmov here, but this branch is extremely
1370 * predictable (it's just a funciton of time and the likely is
1371 * very likely) and there's a data dependence, so force GCC
1372 * to generate a branch instead. I don't barrier() because
1373 * we don't actually need a barrier, and if this function
1374 * ever gets inlined it will generate worse code.
1375 */
1376 asm volatile ("");
1377 return last;
1378 }
1379
1380 static inline u64 vgettsc(cycle_t *cycle_now)
1381 {
1382 long v;
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384
1385 *cycle_now = read_tsc();
1386
1387 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1388 return v * gtod->clock.mult;
1389 }
1390
1391 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1392 {
1393 unsigned long seq;
1394 u64 ns;
1395 int mode;
1396 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1397
1398 ts->tv_nsec = 0;
1399 do {
1400 seq = read_seqcount_begin(&gtod->seq);
1401 mode = gtod->clock.vclock_mode;
1402 ts->tv_sec = gtod->monotonic_time_sec;
1403 ns = gtod->monotonic_time_snsec;
1404 ns += vgettsc(cycle_now);
1405 ns >>= gtod->clock.shift;
1406 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1407 timespec_add_ns(ts, ns);
1408
1409 return mode;
1410 }
1411
1412 /* returns true if host is using tsc clocksource */
1413 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1414 {
1415 struct timespec ts;
1416
1417 /* checked again under seqlock below */
1418 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1419 return false;
1420
1421 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1422 return false;
1423
1424 monotonic_to_bootbased(&ts);
1425 *kernel_ns = timespec_to_ns(&ts);
1426
1427 return true;
1428 }
1429 #endif
1430
1431 /*
1432 *
1433 * Assuming a stable TSC across physical CPUS, and a stable TSC
1434 * across virtual CPUs, the following condition is possible.
1435 * Each numbered line represents an event visible to both
1436 * CPUs at the next numbered event.
1437 *
1438 * "timespecX" represents host monotonic time. "tscX" represents
1439 * RDTSC value.
1440 *
1441 * VCPU0 on CPU0 | VCPU1 on CPU1
1442 *
1443 * 1. read timespec0,tsc0
1444 * 2. | timespec1 = timespec0 + N
1445 * | tsc1 = tsc0 + M
1446 * 3. transition to guest | transition to guest
1447 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1448 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1449 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1450 *
1451 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1452 *
1453 * - ret0 < ret1
1454 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1455 * ...
1456 * - 0 < N - M => M < N
1457 *
1458 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1459 * always the case (the difference between two distinct xtime instances
1460 * might be smaller then the difference between corresponding TSC reads,
1461 * when updating guest vcpus pvclock areas).
1462 *
1463 * To avoid that problem, do not allow visibility of distinct
1464 * system_timestamp/tsc_timestamp values simultaneously: use a master
1465 * copy of host monotonic time values. Update that master copy
1466 * in lockstep.
1467 *
1468 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1469 *
1470 */
1471
1472 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1473 {
1474 #ifdef CONFIG_X86_64
1475 struct kvm_arch *ka = &kvm->arch;
1476 int vclock_mode;
1477 bool host_tsc_clocksource, vcpus_matched;
1478
1479 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1480 atomic_read(&kvm->online_vcpus));
1481
1482 /*
1483 * If the host uses TSC clock, then passthrough TSC as stable
1484 * to the guest.
1485 */
1486 host_tsc_clocksource = kvm_get_time_and_clockread(
1487 &ka->master_kernel_ns,
1488 &ka->master_cycle_now);
1489
1490 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1491
1492 if (ka->use_master_clock)
1493 atomic_set(&kvm_guest_has_master_clock, 1);
1494
1495 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1496 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1497 vcpus_matched);
1498 #endif
1499 }
1500
1501 static void kvm_gen_update_masterclock(struct kvm *kvm)
1502 {
1503 #ifdef CONFIG_X86_64
1504 int i;
1505 struct kvm_vcpu *vcpu;
1506 struct kvm_arch *ka = &kvm->arch;
1507
1508 spin_lock(&ka->pvclock_gtod_sync_lock);
1509 kvm_make_mclock_inprogress_request(kvm);
1510 /* no guest entries from this point */
1511 pvclock_update_vm_gtod_copy(kvm);
1512
1513 kvm_for_each_vcpu(i, vcpu, kvm)
1514 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1515
1516 /* guest entries allowed */
1517 kvm_for_each_vcpu(i, vcpu, kvm)
1518 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1519
1520 spin_unlock(&ka->pvclock_gtod_sync_lock);
1521 #endif
1522 }
1523
1524 static int kvm_guest_time_update(struct kvm_vcpu *v)
1525 {
1526 unsigned long flags, this_tsc_khz;
1527 struct kvm_vcpu_arch *vcpu = &v->arch;
1528 struct kvm_arch *ka = &v->kvm->arch;
1529 s64 kernel_ns;
1530 u64 tsc_timestamp, host_tsc;
1531 struct pvclock_vcpu_time_info guest_hv_clock;
1532 u8 pvclock_flags;
1533 bool use_master_clock;
1534
1535 kernel_ns = 0;
1536 host_tsc = 0;
1537
1538 /*
1539 * If the host uses TSC clock, then passthrough TSC as stable
1540 * to the guest.
1541 */
1542 spin_lock(&ka->pvclock_gtod_sync_lock);
1543 use_master_clock = ka->use_master_clock;
1544 if (use_master_clock) {
1545 host_tsc = ka->master_cycle_now;
1546 kernel_ns = ka->master_kernel_ns;
1547 }
1548 spin_unlock(&ka->pvclock_gtod_sync_lock);
1549
1550 /* Keep irq disabled to prevent changes to the clock */
1551 local_irq_save(flags);
1552 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1553 if (unlikely(this_tsc_khz == 0)) {
1554 local_irq_restore(flags);
1555 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1556 return 1;
1557 }
1558 if (!use_master_clock) {
1559 host_tsc = native_read_tsc();
1560 kernel_ns = get_kernel_ns();
1561 }
1562
1563 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1564
1565 /*
1566 * We may have to catch up the TSC to match elapsed wall clock
1567 * time for two reasons, even if kvmclock is used.
1568 * 1) CPU could have been running below the maximum TSC rate
1569 * 2) Broken TSC compensation resets the base at each VCPU
1570 * entry to avoid unknown leaps of TSC even when running
1571 * again on the same CPU. This may cause apparent elapsed
1572 * time to disappear, and the guest to stand still or run
1573 * very slowly.
1574 */
1575 if (vcpu->tsc_catchup) {
1576 u64 tsc = compute_guest_tsc(v, kernel_ns);
1577 if (tsc > tsc_timestamp) {
1578 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1579 tsc_timestamp = tsc;
1580 }
1581 }
1582
1583 local_irq_restore(flags);
1584
1585 if (!vcpu->pv_time_enabled)
1586 return 0;
1587
1588 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1589 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1590 &vcpu->hv_clock.tsc_shift,
1591 &vcpu->hv_clock.tsc_to_system_mul);
1592 vcpu->hw_tsc_khz = this_tsc_khz;
1593 }
1594
1595 /* With all the info we got, fill in the values */
1596 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1597 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1598 vcpu->last_guest_tsc = tsc_timestamp;
1599
1600 /*
1601 * The interface expects us to write an even number signaling that the
1602 * update is finished. Since the guest won't see the intermediate
1603 * state, we just increase by 2 at the end.
1604 */
1605 vcpu->hv_clock.version += 2;
1606
1607 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1608 &guest_hv_clock, sizeof(guest_hv_clock))))
1609 return 0;
1610
1611 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1612 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1613
1614 if (vcpu->pvclock_set_guest_stopped_request) {
1615 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1616 vcpu->pvclock_set_guest_stopped_request = false;
1617 }
1618
1619 /* If the host uses TSC clocksource, then it is stable */
1620 if (use_master_clock)
1621 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1622
1623 vcpu->hv_clock.flags = pvclock_flags;
1624
1625 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1626 &vcpu->hv_clock,
1627 sizeof(vcpu->hv_clock));
1628 return 0;
1629 }
1630
1631 /*
1632 * kvmclock updates which are isolated to a given vcpu, such as
1633 * vcpu->cpu migration, should not allow system_timestamp from
1634 * the rest of the vcpus to remain static. Otherwise ntp frequency
1635 * correction applies to one vcpu's system_timestamp but not
1636 * the others.
1637 *
1638 * So in those cases, request a kvmclock update for all vcpus.
1639 * We need to rate-limit these requests though, as they can
1640 * considerably slow guests that have a large number of vcpus.
1641 * The time for a remote vcpu to update its kvmclock is bound
1642 * by the delay we use to rate-limit the updates.
1643 */
1644
1645 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1646
1647 static void kvmclock_update_fn(struct work_struct *work)
1648 {
1649 int i;
1650 struct delayed_work *dwork = to_delayed_work(work);
1651 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1652 kvmclock_update_work);
1653 struct kvm *kvm = container_of(ka, struct kvm, arch);
1654 struct kvm_vcpu *vcpu;
1655
1656 kvm_for_each_vcpu(i, vcpu, kvm) {
1657 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1658 kvm_vcpu_kick(vcpu);
1659 }
1660 }
1661
1662 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1663 {
1664 struct kvm *kvm = v->kvm;
1665
1666 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1667 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1668 KVMCLOCK_UPDATE_DELAY);
1669 }
1670
1671 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1672
1673 static void kvmclock_sync_fn(struct work_struct *work)
1674 {
1675 struct delayed_work *dwork = to_delayed_work(work);
1676 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1677 kvmclock_sync_work);
1678 struct kvm *kvm = container_of(ka, struct kvm, arch);
1679
1680 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1681 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1682 KVMCLOCK_SYNC_PERIOD);
1683 }
1684
1685 static bool msr_mtrr_valid(unsigned msr)
1686 {
1687 switch (msr) {
1688 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1689 case MSR_MTRRfix64K_00000:
1690 case MSR_MTRRfix16K_80000:
1691 case MSR_MTRRfix16K_A0000:
1692 case MSR_MTRRfix4K_C0000:
1693 case MSR_MTRRfix4K_C8000:
1694 case MSR_MTRRfix4K_D0000:
1695 case MSR_MTRRfix4K_D8000:
1696 case MSR_MTRRfix4K_E0000:
1697 case MSR_MTRRfix4K_E8000:
1698 case MSR_MTRRfix4K_F0000:
1699 case MSR_MTRRfix4K_F8000:
1700 case MSR_MTRRdefType:
1701 case MSR_IA32_CR_PAT:
1702 return true;
1703 case 0x2f8:
1704 return true;
1705 }
1706 return false;
1707 }
1708
1709 static bool valid_pat_type(unsigned t)
1710 {
1711 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1712 }
1713
1714 static bool valid_mtrr_type(unsigned t)
1715 {
1716 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1717 }
1718
1719 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1720 {
1721 int i;
1722
1723 if (!msr_mtrr_valid(msr))
1724 return false;
1725
1726 if (msr == MSR_IA32_CR_PAT) {
1727 for (i = 0; i < 8; i++)
1728 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1729 return false;
1730 return true;
1731 } else if (msr == MSR_MTRRdefType) {
1732 if (data & ~0xcff)
1733 return false;
1734 return valid_mtrr_type(data & 0xff);
1735 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1736 for (i = 0; i < 8 ; i++)
1737 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1738 return false;
1739 return true;
1740 }
1741
1742 /* variable MTRRs */
1743 return valid_mtrr_type(data & 0xff);
1744 }
1745
1746 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1747 {
1748 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1749
1750 if (!mtrr_valid(vcpu, msr, data))
1751 return 1;
1752
1753 if (msr == MSR_MTRRdefType) {
1754 vcpu->arch.mtrr_state.def_type = data;
1755 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1756 } else if (msr == MSR_MTRRfix64K_00000)
1757 p[0] = data;
1758 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1759 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1760 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1761 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1762 else if (msr == MSR_IA32_CR_PAT)
1763 vcpu->arch.pat = data;
1764 else { /* Variable MTRRs */
1765 int idx, is_mtrr_mask;
1766 u64 *pt;
1767
1768 idx = (msr - 0x200) / 2;
1769 is_mtrr_mask = msr - 0x200 - 2 * idx;
1770 if (!is_mtrr_mask)
1771 pt =
1772 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1773 else
1774 pt =
1775 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1776 *pt = data;
1777 }
1778
1779 kvm_mmu_reset_context(vcpu);
1780 return 0;
1781 }
1782
1783 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1784 {
1785 u64 mcg_cap = vcpu->arch.mcg_cap;
1786 unsigned bank_num = mcg_cap & 0xff;
1787
1788 switch (msr) {
1789 case MSR_IA32_MCG_STATUS:
1790 vcpu->arch.mcg_status = data;
1791 break;
1792 case MSR_IA32_MCG_CTL:
1793 if (!(mcg_cap & MCG_CTL_P))
1794 return 1;
1795 if (data != 0 && data != ~(u64)0)
1796 return -1;
1797 vcpu->arch.mcg_ctl = data;
1798 break;
1799 default:
1800 if (msr >= MSR_IA32_MC0_CTL &&
1801 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1802 u32 offset = msr - MSR_IA32_MC0_CTL;
1803 /* only 0 or all 1s can be written to IA32_MCi_CTL
1804 * some Linux kernels though clear bit 10 in bank 4 to
1805 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1806 * this to avoid an uncatched #GP in the guest
1807 */
1808 if ((offset & 0x3) == 0 &&
1809 data != 0 && (data | (1 << 10)) != ~(u64)0)
1810 return -1;
1811 vcpu->arch.mce_banks[offset] = data;
1812 break;
1813 }
1814 return 1;
1815 }
1816 return 0;
1817 }
1818
1819 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1820 {
1821 struct kvm *kvm = vcpu->kvm;
1822 int lm = is_long_mode(vcpu);
1823 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1824 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1825 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1826 : kvm->arch.xen_hvm_config.blob_size_32;
1827 u32 page_num = data & ~PAGE_MASK;
1828 u64 page_addr = data & PAGE_MASK;
1829 u8 *page;
1830 int r;
1831
1832 r = -E2BIG;
1833 if (page_num >= blob_size)
1834 goto out;
1835 r = -ENOMEM;
1836 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1837 if (IS_ERR(page)) {
1838 r = PTR_ERR(page);
1839 goto out;
1840 }
1841 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1842 goto out_free;
1843 r = 0;
1844 out_free:
1845 kfree(page);
1846 out:
1847 return r;
1848 }
1849
1850 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1851 {
1852 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1853 }
1854
1855 static bool kvm_hv_msr_partition_wide(u32 msr)
1856 {
1857 bool r = false;
1858 switch (msr) {
1859 case HV_X64_MSR_GUEST_OS_ID:
1860 case HV_X64_MSR_HYPERCALL:
1861 case HV_X64_MSR_REFERENCE_TSC:
1862 case HV_X64_MSR_TIME_REF_COUNT:
1863 r = true;
1864 break;
1865 }
1866
1867 return r;
1868 }
1869
1870 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1871 {
1872 struct kvm *kvm = vcpu->kvm;
1873
1874 switch (msr) {
1875 case HV_X64_MSR_GUEST_OS_ID:
1876 kvm->arch.hv_guest_os_id = data;
1877 /* setting guest os id to zero disables hypercall page */
1878 if (!kvm->arch.hv_guest_os_id)
1879 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1880 break;
1881 case HV_X64_MSR_HYPERCALL: {
1882 u64 gfn;
1883 unsigned long addr;
1884 u8 instructions[4];
1885
1886 /* if guest os id is not set hypercall should remain disabled */
1887 if (!kvm->arch.hv_guest_os_id)
1888 break;
1889 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1890 kvm->arch.hv_hypercall = data;
1891 break;
1892 }
1893 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1894 addr = gfn_to_hva(kvm, gfn);
1895 if (kvm_is_error_hva(addr))
1896 return 1;
1897 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1898 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1899 if (__copy_to_user((void __user *)addr, instructions, 4))
1900 return 1;
1901 kvm->arch.hv_hypercall = data;
1902 mark_page_dirty(kvm, gfn);
1903 break;
1904 }
1905 case HV_X64_MSR_REFERENCE_TSC: {
1906 u64 gfn;
1907 HV_REFERENCE_TSC_PAGE tsc_ref;
1908 memset(&tsc_ref, 0, sizeof(tsc_ref));
1909 kvm->arch.hv_tsc_page = data;
1910 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1911 break;
1912 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1913 if (kvm_write_guest(kvm, data,
1914 &tsc_ref, sizeof(tsc_ref)))
1915 return 1;
1916 mark_page_dirty(kvm, gfn);
1917 break;
1918 }
1919 default:
1920 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1921 "data 0x%llx\n", msr, data);
1922 return 1;
1923 }
1924 return 0;
1925 }
1926
1927 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1928 {
1929 switch (msr) {
1930 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1931 u64 gfn;
1932 unsigned long addr;
1933
1934 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1935 vcpu->arch.hv_vapic = data;
1936 break;
1937 }
1938 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1939 addr = gfn_to_hva(vcpu->kvm, gfn);
1940 if (kvm_is_error_hva(addr))
1941 return 1;
1942 if (__clear_user((void __user *)addr, PAGE_SIZE))
1943 return 1;
1944 vcpu->arch.hv_vapic = data;
1945 mark_page_dirty(vcpu->kvm, gfn);
1946 break;
1947 }
1948 case HV_X64_MSR_EOI:
1949 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1950 case HV_X64_MSR_ICR:
1951 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1952 case HV_X64_MSR_TPR:
1953 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1954 default:
1955 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1956 "data 0x%llx\n", msr, data);
1957 return 1;
1958 }
1959
1960 return 0;
1961 }
1962
1963 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1964 {
1965 gpa_t gpa = data & ~0x3f;
1966
1967 /* Bits 2:5 are reserved, Should be zero */
1968 if (data & 0x3c)
1969 return 1;
1970
1971 vcpu->arch.apf.msr_val = data;
1972
1973 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1974 kvm_clear_async_pf_completion_queue(vcpu);
1975 kvm_async_pf_hash_reset(vcpu);
1976 return 0;
1977 }
1978
1979 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1980 sizeof(u32)))
1981 return 1;
1982
1983 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1984 kvm_async_pf_wakeup_all(vcpu);
1985 return 0;
1986 }
1987
1988 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1989 {
1990 vcpu->arch.pv_time_enabled = false;
1991 }
1992
1993 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1994 {
1995 u64 delta;
1996
1997 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1998 return;
1999
2000 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2001 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2002 vcpu->arch.st.accum_steal = delta;
2003 }
2004
2005 static void record_steal_time(struct kvm_vcpu *vcpu)
2006 {
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2008 return;
2009
2010 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2012 return;
2013
2014 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2015 vcpu->arch.st.steal.version += 2;
2016 vcpu->arch.st.accum_steal = 0;
2017
2018 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2019 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2020 }
2021
2022 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2023 {
2024 bool pr = false;
2025 u32 msr = msr_info->index;
2026 u64 data = msr_info->data;
2027
2028 switch (msr) {
2029 case MSR_AMD64_NB_CFG:
2030 case MSR_IA32_UCODE_REV:
2031 case MSR_IA32_UCODE_WRITE:
2032 case MSR_VM_HSAVE_PA:
2033 case MSR_AMD64_PATCH_LOADER:
2034 case MSR_AMD64_BU_CFG2:
2035 break;
2036
2037 case MSR_EFER:
2038 return set_efer(vcpu, data);
2039 case MSR_K7_HWCR:
2040 data &= ~(u64)0x40; /* ignore flush filter disable */
2041 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2042 data &= ~(u64)0x8; /* ignore TLB cache disable */
2043 if (data != 0) {
2044 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2045 data);
2046 return 1;
2047 }
2048 break;
2049 case MSR_FAM10H_MMIO_CONF_BASE:
2050 if (data != 0) {
2051 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2052 "0x%llx\n", data);
2053 return 1;
2054 }
2055 break;
2056 case MSR_IA32_DEBUGCTLMSR:
2057 if (!data) {
2058 /* We support the non-activated case already */
2059 break;
2060 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2061 /* Values other than LBR and BTF are vendor-specific,
2062 thus reserved and should throw a #GP */
2063 return 1;
2064 }
2065 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2066 __func__, data);
2067 break;
2068 case 0x200 ... 0x2ff:
2069 return set_msr_mtrr(vcpu, msr, data);
2070 case MSR_IA32_APICBASE:
2071 return kvm_set_apic_base(vcpu, msr_info);
2072 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2073 return kvm_x2apic_msr_write(vcpu, msr, data);
2074 case MSR_IA32_TSCDEADLINE:
2075 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2076 break;
2077 case MSR_IA32_TSC_ADJUST:
2078 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2079 if (!msr_info->host_initiated) {
2080 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2081 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2082 }
2083 vcpu->arch.ia32_tsc_adjust_msr = data;
2084 }
2085 break;
2086 case MSR_IA32_MISC_ENABLE:
2087 vcpu->arch.ia32_misc_enable_msr = data;
2088 break;
2089 case MSR_KVM_WALL_CLOCK_NEW:
2090 case MSR_KVM_WALL_CLOCK:
2091 vcpu->kvm->arch.wall_clock = data;
2092 kvm_write_wall_clock(vcpu->kvm, data);
2093 break;
2094 case MSR_KVM_SYSTEM_TIME_NEW:
2095 case MSR_KVM_SYSTEM_TIME: {
2096 u64 gpa_offset;
2097 kvmclock_reset(vcpu);
2098
2099 vcpu->arch.time = data;
2100 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2101
2102 /* we verify if the enable bit is set... */
2103 if (!(data & 1))
2104 break;
2105
2106 gpa_offset = data & ~(PAGE_MASK | 1);
2107
2108 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2109 &vcpu->arch.pv_time, data & ~1ULL,
2110 sizeof(struct pvclock_vcpu_time_info)))
2111 vcpu->arch.pv_time_enabled = false;
2112 else
2113 vcpu->arch.pv_time_enabled = true;
2114
2115 break;
2116 }
2117 case MSR_KVM_ASYNC_PF_EN:
2118 if (kvm_pv_enable_async_pf(vcpu, data))
2119 return 1;
2120 break;
2121 case MSR_KVM_STEAL_TIME:
2122
2123 if (unlikely(!sched_info_on()))
2124 return 1;
2125
2126 if (data & KVM_STEAL_RESERVED_MASK)
2127 return 1;
2128
2129 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2130 data & KVM_STEAL_VALID_BITS,
2131 sizeof(struct kvm_steal_time)))
2132 return 1;
2133
2134 vcpu->arch.st.msr_val = data;
2135
2136 if (!(data & KVM_MSR_ENABLED))
2137 break;
2138
2139 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2140
2141 preempt_disable();
2142 accumulate_steal_time(vcpu);
2143 preempt_enable();
2144
2145 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2146
2147 break;
2148 case MSR_KVM_PV_EOI_EN:
2149 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2150 return 1;
2151 break;
2152
2153 case MSR_IA32_MCG_CTL:
2154 case MSR_IA32_MCG_STATUS:
2155 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2156 return set_msr_mce(vcpu, msr, data);
2157
2158 /* Performance counters are not protected by a CPUID bit,
2159 * so we should check all of them in the generic path for the sake of
2160 * cross vendor migration.
2161 * Writing a zero into the event select MSRs disables them,
2162 * which we perfectly emulate ;-). Any other value should be at least
2163 * reported, some guests depend on them.
2164 */
2165 case MSR_K7_EVNTSEL0:
2166 case MSR_K7_EVNTSEL1:
2167 case MSR_K7_EVNTSEL2:
2168 case MSR_K7_EVNTSEL3:
2169 if (data != 0)
2170 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2171 "0x%x data 0x%llx\n", msr, data);
2172 break;
2173 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2174 * so we ignore writes to make it happy.
2175 */
2176 case MSR_K7_PERFCTR0:
2177 case MSR_K7_PERFCTR1:
2178 case MSR_K7_PERFCTR2:
2179 case MSR_K7_PERFCTR3:
2180 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2181 "0x%x data 0x%llx\n", msr, data);
2182 break;
2183 case MSR_P6_PERFCTR0:
2184 case MSR_P6_PERFCTR1:
2185 pr = true;
2186 case MSR_P6_EVNTSEL0:
2187 case MSR_P6_EVNTSEL1:
2188 if (kvm_pmu_msr(vcpu, msr))
2189 return kvm_pmu_set_msr(vcpu, msr_info);
2190
2191 if (pr || data != 0)
2192 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2193 "0x%x data 0x%llx\n", msr, data);
2194 break;
2195 case MSR_K7_CLK_CTL:
2196 /*
2197 * Ignore all writes to this no longer documented MSR.
2198 * Writes are only relevant for old K7 processors,
2199 * all pre-dating SVM, but a recommended workaround from
2200 * AMD for these chips. It is possible to specify the
2201 * affected processor models on the command line, hence
2202 * the need to ignore the workaround.
2203 */
2204 break;
2205 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2206 if (kvm_hv_msr_partition_wide(msr)) {
2207 int r;
2208 mutex_lock(&vcpu->kvm->lock);
2209 r = set_msr_hyperv_pw(vcpu, msr, data);
2210 mutex_unlock(&vcpu->kvm->lock);
2211 return r;
2212 } else
2213 return set_msr_hyperv(vcpu, msr, data);
2214 break;
2215 case MSR_IA32_BBL_CR_CTL3:
2216 /* Drop writes to this legacy MSR -- see rdmsr
2217 * counterpart for further detail.
2218 */
2219 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2220 break;
2221 case MSR_AMD64_OSVW_ID_LENGTH:
2222 if (!guest_cpuid_has_osvw(vcpu))
2223 return 1;
2224 vcpu->arch.osvw.length = data;
2225 break;
2226 case MSR_AMD64_OSVW_STATUS:
2227 if (!guest_cpuid_has_osvw(vcpu))
2228 return 1;
2229 vcpu->arch.osvw.status = data;
2230 break;
2231 default:
2232 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2233 return xen_hvm_config(vcpu, data);
2234 if (kvm_pmu_msr(vcpu, msr))
2235 return kvm_pmu_set_msr(vcpu, msr_info);
2236 if (!ignore_msrs) {
2237 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2238 msr, data);
2239 return 1;
2240 } else {
2241 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2242 msr, data);
2243 break;
2244 }
2245 }
2246 return 0;
2247 }
2248 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2249
2250
2251 /*
2252 * Reads an msr value (of 'msr_index') into 'pdata'.
2253 * Returns 0 on success, non-0 otherwise.
2254 * Assumes vcpu_load() was already called.
2255 */
2256 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2257 {
2258 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2259 }
2260
2261 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2262 {
2263 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2264
2265 if (!msr_mtrr_valid(msr))
2266 return 1;
2267
2268 if (msr == MSR_MTRRdefType)
2269 *pdata = vcpu->arch.mtrr_state.def_type +
2270 (vcpu->arch.mtrr_state.enabled << 10);
2271 else if (msr == MSR_MTRRfix64K_00000)
2272 *pdata = p[0];
2273 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2274 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2275 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2276 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2277 else if (msr == MSR_IA32_CR_PAT)
2278 *pdata = vcpu->arch.pat;
2279 else { /* Variable MTRRs */
2280 int idx, is_mtrr_mask;
2281 u64 *pt;
2282
2283 idx = (msr - 0x200) / 2;
2284 is_mtrr_mask = msr - 0x200 - 2 * idx;
2285 if (!is_mtrr_mask)
2286 pt =
2287 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2288 else
2289 pt =
2290 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2291 *pdata = *pt;
2292 }
2293
2294 return 0;
2295 }
2296
2297 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2298 {
2299 u64 data;
2300 u64 mcg_cap = vcpu->arch.mcg_cap;
2301 unsigned bank_num = mcg_cap & 0xff;
2302
2303 switch (msr) {
2304 case MSR_IA32_P5_MC_ADDR:
2305 case MSR_IA32_P5_MC_TYPE:
2306 data = 0;
2307 break;
2308 case MSR_IA32_MCG_CAP:
2309 data = vcpu->arch.mcg_cap;
2310 break;
2311 case MSR_IA32_MCG_CTL:
2312 if (!(mcg_cap & MCG_CTL_P))
2313 return 1;
2314 data = vcpu->arch.mcg_ctl;
2315 break;
2316 case MSR_IA32_MCG_STATUS:
2317 data = vcpu->arch.mcg_status;
2318 break;
2319 default:
2320 if (msr >= MSR_IA32_MC0_CTL &&
2321 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2322 u32 offset = msr - MSR_IA32_MC0_CTL;
2323 data = vcpu->arch.mce_banks[offset];
2324 break;
2325 }
2326 return 1;
2327 }
2328 *pdata = data;
2329 return 0;
2330 }
2331
2332 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2333 {
2334 u64 data = 0;
2335 struct kvm *kvm = vcpu->kvm;
2336
2337 switch (msr) {
2338 case HV_X64_MSR_GUEST_OS_ID:
2339 data = kvm->arch.hv_guest_os_id;
2340 break;
2341 case HV_X64_MSR_HYPERCALL:
2342 data = kvm->arch.hv_hypercall;
2343 break;
2344 case HV_X64_MSR_TIME_REF_COUNT: {
2345 data =
2346 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2347 break;
2348 }
2349 case HV_X64_MSR_REFERENCE_TSC:
2350 data = kvm->arch.hv_tsc_page;
2351 break;
2352 default:
2353 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2354 return 1;
2355 }
2356
2357 *pdata = data;
2358 return 0;
2359 }
2360
2361 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2362 {
2363 u64 data = 0;
2364
2365 switch (msr) {
2366 case HV_X64_MSR_VP_INDEX: {
2367 int r;
2368 struct kvm_vcpu *v;
2369 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2370 if (v == vcpu) {
2371 data = r;
2372 break;
2373 }
2374 }
2375 break;
2376 }
2377 case HV_X64_MSR_EOI:
2378 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2379 case HV_X64_MSR_ICR:
2380 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2381 case HV_X64_MSR_TPR:
2382 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2383 case HV_X64_MSR_APIC_ASSIST_PAGE:
2384 data = vcpu->arch.hv_vapic;
2385 break;
2386 default:
2387 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2388 return 1;
2389 }
2390 *pdata = data;
2391 return 0;
2392 }
2393
2394 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2395 {
2396 u64 data;
2397
2398 switch (msr) {
2399 case MSR_IA32_PLATFORM_ID:
2400 case MSR_IA32_EBL_CR_POWERON:
2401 case MSR_IA32_DEBUGCTLMSR:
2402 case MSR_IA32_LASTBRANCHFROMIP:
2403 case MSR_IA32_LASTBRANCHTOIP:
2404 case MSR_IA32_LASTINTFROMIP:
2405 case MSR_IA32_LASTINTTOIP:
2406 case MSR_K8_SYSCFG:
2407 case MSR_K7_HWCR:
2408 case MSR_VM_HSAVE_PA:
2409 case MSR_K7_EVNTSEL0:
2410 case MSR_K7_PERFCTR0:
2411 case MSR_K8_INT_PENDING_MSG:
2412 case MSR_AMD64_NB_CFG:
2413 case MSR_FAM10H_MMIO_CONF_BASE:
2414 case MSR_AMD64_BU_CFG2:
2415 data = 0;
2416 break;
2417 case MSR_P6_PERFCTR0:
2418 case MSR_P6_PERFCTR1:
2419 case MSR_P6_EVNTSEL0:
2420 case MSR_P6_EVNTSEL1:
2421 if (kvm_pmu_msr(vcpu, msr))
2422 return kvm_pmu_get_msr(vcpu, msr, pdata);
2423 data = 0;
2424 break;
2425 case MSR_IA32_UCODE_REV:
2426 data = 0x100000000ULL;
2427 break;
2428 case MSR_MTRRcap:
2429 data = 0x500 | KVM_NR_VAR_MTRR;
2430 break;
2431 case 0x200 ... 0x2ff:
2432 return get_msr_mtrr(vcpu, msr, pdata);
2433 case 0xcd: /* fsb frequency */
2434 data = 3;
2435 break;
2436 /*
2437 * MSR_EBC_FREQUENCY_ID
2438 * Conservative value valid for even the basic CPU models.
2439 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2440 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2441 * and 266MHz for model 3, or 4. Set Core Clock
2442 * Frequency to System Bus Frequency Ratio to 1 (bits
2443 * 31:24) even though these are only valid for CPU
2444 * models > 2, however guests may end up dividing or
2445 * multiplying by zero otherwise.
2446 */
2447 case MSR_EBC_FREQUENCY_ID:
2448 data = 1 << 24;
2449 break;
2450 case MSR_IA32_APICBASE:
2451 data = kvm_get_apic_base(vcpu);
2452 break;
2453 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2454 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2455 break;
2456 case MSR_IA32_TSCDEADLINE:
2457 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2458 break;
2459 case MSR_IA32_TSC_ADJUST:
2460 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2461 break;
2462 case MSR_IA32_MISC_ENABLE:
2463 data = vcpu->arch.ia32_misc_enable_msr;
2464 break;
2465 case MSR_IA32_PERF_STATUS:
2466 /* TSC increment by tick */
2467 data = 1000ULL;
2468 /* CPU multiplier */
2469 data |= (((uint64_t)4ULL) << 40);
2470 break;
2471 case MSR_EFER:
2472 data = vcpu->arch.efer;
2473 break;
2474 case MSR_KVM_WALL_CLOCK:
2475 case MSR_KVM_WALL_CLOCK_NEW:
2476 data = vcpu->kvm->arch.wall_clock;
2477 break;
2478 case MSR_KVM_SYSTEM_TIME:
2479 case MSR_KVM_SYSTEM_TIME_NEW:
2480 data = vcpu->arch.time;
2481 break;
2482 case MSR_KVM_ASYNC_PF_EN:
2483 data = vcpu->arch.apf.msr_val;
2484 break;
2485 case MSR_KVM_STEAL_TIME:
2486 data = vcpu->arch.st.msr_val;
2487 break;
2488 case MSR_KVM_PV_EOI_EN:
2489 data = vcpu->arch.pv_eoi.msr_val;
2490 break;
2491 case MSR_IA32_P5_MC_ADDR:
2492 case MSR_IA32_P5_MC_TYPE:
2493 case MSR_IA32_MCG_CAP:
2494 case MSR_IA32_MCG_CTL:
2495 case MSR_IA32_MCG_STATUS:
2496 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2497 return get_msr_mce(vcpu, msr, pdata);
2498 case MSR_K7_CLK_CTL:
2499 /*
2500 * Provide expected ramp-up count for K7. All other
2501 * are set to zero, indicating minimum divisors for
2502 * every field.
2503 *
2504 * This prevents guest kernels on AMD host with CPU
2505 * type 6, model 8 and higher from exploding due to
2506 * the rdmsr failing.
2507 */
2508 data = 0x20000000;
2509 break;
2510 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2511 if (kvm_hv_msr_partition_wide(msr)) {
2512 int r;
2513 mutex_lock(&vcpu->kvm->lock);
2514 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2515 mutex_unlock(&vcpu->kvm->lock);
2516 return r;
2517 } else
2518 return get_msr_hyperv(vcpu, msr, pdata);
2519 break;
2520 case MSR_IA32_BBL_CR_CTL3:
2521 /* This legacy MSR exists but isn't fully documented in current
2522 * silicon. It is however accessed by winxp in very narrow
2523 * scenarios where it sets bit #19, itself documented as
2524 * a "reserved" bit. Best effort attempt to source coherent
2525 * read data here should the balance of the register be
2526 * interpreted by the guest:
2527 *
2528 * L2 cache control register 3: 64GB range, 256KB size,
2529 * enabled, latency 0x1, configured
2530 */
2531 data = 0xbe702111;
2532 break;
2533 case MSR_AMD64_OSVW_ID_LENGTH:
2534 if (!guest_cpuid_has_osvw(vcpu))
2535 return 1;
2536 data = vcpu->arch.osvw.length;
2537 break;
2538 case MSR_AMD64_OSVW_STATUS:
2539 if (!guest_cpuid_has_osvw(vcpu))
2540 return 1;
2541 data = vcpu->arch.osvw.status;
2542 break;
2543 default:
2544 if (kvm_pmu_msr(vcpu, msr))
2545 return kvm_pmu_get_msr(vcpu, msr, pdata);
2546 if (!ignore_msrs) {
2547 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2548 return 1;
2549 } else {
2550 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2551 data = 0;
2552 }
2553 break;
2554 }
2555 *pdata = data;
2556 return 0;
2557 }
2558 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2559
2560 /*
2561 * Read or write a bunch of msrs. All parameters are kernel addresses.
2562 *
2563 * @return number of msrs set successfully.
2564 */
2565 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2566 struct kvm_msr_entry *entries,
2567 int (*do_msr)(struct kvm_vcpu *vcpu,
2568 unsigned index, u64 *data))
2569 {
2570 int i, idx;
2571
2572 idx = srcu_read_lock(&vcpu->kvm->srcu);
2573 for (i = 0; i < msrs->nmsrs; ++i)
2574 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2575 break;
2576 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2577
2578 return i;
2579 }
2580
2581 /*
2582 * Read or write a bunch of msrs. Parameters are user addresses.
2583 *
2584 * @return number of msrs set successfully.
2585 */
2586 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2587 int (*do_msr)(struct kvm_vcpu *vcpu,
2588 unsigned index, u64 *data),
2589 int writeback)
2590 {
2591 struct kvm_msrs msrs;
2592 struct kvm_msr_entry *entries;
2593 int r, n;
2594 unsigned size;
2595
2596 r = -EFAULT;
2597 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2598 goto out;
2599
2600 r = -E2BIG;
2601 if (msrs.nmsrs >= MAX_IO_MSRS)
2602 goto out;
2603
2604 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2605 entries = memdup_user(user_msrs->entries, size);
2606 if (IS_ERR(entries)) {
2607 r = PTR_ERR(entries);
2608 goto out;
2609 }
2610
2611 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2612 if (r < 0)
2613 goto out_free;
2614
2615 r = -EFAULT;
2616 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2617 goto out_free;
2618
2619 r = n;
2620
2621 out_free:
2622 kfree(entries);
2623 out:
2624 return r;
2625 }
2626
2627 int kvm_dev_ioctl_check_extension(long ext)
2628 {
2629 int r;
2630
2631 switch (ext) {
2632 case KVM_CAP_IRQCHIP:
2633 case KVM_CAP_HLT:
2634 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2635 case KVM_CAP_SET_TSS_ADDR:
2636 case KVM_CAP_EXT_CPUID:
2637 case KVM_CAP_EXT_EMUL_CPUID:
2638 case KVM_CAP_CLOCKSOURCE:
2639 case KVM_CAP_PIT:
2640 case KVM_CAP_NOP_IO_DELAY:
2641 case KVM_CAP_MP_STATE:
2642 case KVM_CAP_SYNC_MMU:
2643 case KVM_CAP_USER_NMI:
2644 case KVM_CAP_REINJECT_CONTROL:
2645 case KVM_CAP_IRQ_INJECT_STATUS:
2646 case KVM_CAP_IRQFD:
2647 case KVM_CAP_IOEVENTFD:
2648 case KVM_CAP_PIT2:
2649 case KVM_CAP_PIT_STATE2:
2650 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2651 case KVM_CAP_XEN_HVM:
2652 case KVM_CAP_ADJUST_CLOCK:
2653 case KVM_CAP_VCPU_EVENTS:
2654 case KVM_CAP_HYPERV:
2655 case KVM_CAP_HYPERV_VAPIC:
2656 case KVM_CAP_HYPERV_SPIN:
2657 case KVM_CAP_PCI_SEGMENT:
2658 case KVM_CAP_DEBUGREGS:
2659 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2660 case KVM_CAP_XSAVE:
2661 case KVM_CAP_ASYNC_PF:
2662 case KVM_CAP_GET_TSC_KHZ:
2663 case KVM_CAP_KVMCLOCK_CTRL:
2664 case KVM_CAP_READONLY_MEM:
2665 case KVM_CAP_HYPERV_TIME:
2666 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2667 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2668 case KVM_CAP_ASSIGN_DEV_IRQ:
2669 case KVM_CAP_PCI_2_3:
2670 #endif
2671 r = 1;
2672 break;
2673 case KVM_CAP_COALESCED_MMIO:
2674 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2675 break;
2676 case KVM_CAP_VAPIC:
2677 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2678 break;
2679 case KVM_CAP_NR_VCPUS:
2680 r = KVM_SOFT_MAX_VCPUS;
2681 break;
2682 case KVM_CAP_MAX_VCPUS:
2683 r = KVM_MAX_VCPUS;
2684 break;
2685 case KVM_CAP_NR_MEMSLOTS:
2686 r = KVM_USER_MEM_SLOTS;
2687 break;
2688 case KVM_CAP_PV_MMU: /* obsolete */
2689 r = 0;
2690 break;
2691 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2692 case KVM_CAP_IOMMU:
2693 r = iommu_present(&pci_bus_type);
2694 break;
2695 #endif
2696 case KVM_CAP_MCE:
2697 r = KVM_MAX_MCE_BANKS;
2698 break;
2699 case KVM_CAP_XCRS:
2700 r = cpu_has_xsave;
2701 break;
2702 case KVM_CAP_TSC_CONTROL:
2703 r = kvm_has_tsc_control;
2704 break;
2705 case KVM_CAP_TSC_DEADLINE_TIMER:
2706 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2707 break;
2708 default:
2709 r = 0;
2710 break;
2711 }
2712 return r;
2713
2714 }
2715
2716 long kvm_arch_dev_ioctl(struct file *filp,
2717 unsigned int ioctl, unsigned long arg)
2718 {
2719 void __user *argp = (void __user *)arg;
2720 long r;
2721
2722 switch (ioctl) {
2723 case KVM_GET_MSR_INDEX_LIST: {
2724 struct kvm_msr_list __user *user_msr_list = argp;
2725 struct kvm_msr_list msr_list;
2726 unsigned n;
2727
2728 r = -EFAULT;
2729 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2730 goto out;
2731 n = msr_list.nmsrs;
2732 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2733 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2734 goto out;
2735 r = -E2BIG;
2736 if (n < msr_list.nmsrs)
2737 goto out;
2738 r = -EFAULT;
2739 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2740 num_msrs_to_save * sizeof(u32)))
2741 goto out;
2742 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2743 &emulated_msrs,
2744 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2745 goto out;
2746 r = 0;
2747 break;
2748 }
2749 case KVM_GET_SUPPORTED_CPUID:
2750 case KVM_GET_EMULATED_CPUID: {
2751 struct kvm_cpuid2 __user *cpuid_arg = argp;
2752 struct kvm_cpuid2 cpuid;
2753
2754 r = -EFAULT;
2755 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2756 goto out;
2757
2758 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2759 ioctl);
2760 if (r)
2761 goto out;
2762
2763 r = -EFAULT;
2764 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2765 goto out;
2766 r = 0;
2767 break;
2768 }
2769 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2770 u64 mce_cap;
2771
2772 mce_cap = KVM_MCE_CAP_SUPPORTED;
2773 r = -EFAULT;
2774 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2775 goto out;
2776 r = 0;
2777 break;
2778 }
2779 default:
2780 r = -EINVAL;
2781 }
2782 out:
2783 return r;
2784 }
2785
2786 static void wbinvd_ipi(void *garbage)
2787 {
2788 wbinvd();
2789 }
2790
2791 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2792 {
2793 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2794 }
2795
2796 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2797 {
2798 /* Address WBINVD may be executed by guest */
2799 if (need_emulate_wbinvd(vcpu)) {
2800 if (kvm_x86_ops->has_wbinvd_exit())
2801 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2802 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2803 smp_call_function_single(vcpu->cpu,
2804 wbinvd_ipi, NULL, 1);
2805 }
2806
2807 kvm_x86_ops->vcpu_load(vcpu, cpu);
2808
2809 /* Apply any externally detected TSC adjustments (due to suspend) */
2810 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2811 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2812 vcpu->arch.tsc_offset_adjustment = 0;
2813 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2814 }
2815
2816 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2817 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2818 native_read_tsc() - vcpu->arch.last_host_tsc;
2819 if (tsc_delta < 0)
2820 mark_tsc_unstable("KVM discovered backwards TSC");
2821 if (check_tsc_unstable()) {
2822 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2823 vcpu->arch.last_guest_tsc);
2824 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2825 vcpu->arch.tsc_catchup = 1;
2826 }
2827 /*
2828 * On a host with synchronized TSC, there is no need to update
2829 * kvmclock on vcpu->cpu migration
2830 */
2831 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2832 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2833 if (vcpu->cpu != cpu)
2834 kvm_migrate_timers(vcpu);
2835 vcpu->cpu = cpu;
2836 }
2837
2838 accumulate_steal_time(vcpu);
2839 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2840 }
2841
2842 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2843 {
2844 kvm_x86_ops->vcpu_put(vcpu);
2845 kvm_put_guest_fpu(vcpu);
2846 vcpu->arch.last_host_tsc = native_read_tsc();
2847 }
2848
2849 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2850 struct kvm_lapic_state *s)
2851 {
2852 kvm_x86_ops->sync_pir_to_irr(vcpu);
2853 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2854
2855 return 0;
2856 }
2857
2858 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2859 struct kvm_lapic_state *s)
2860 {
2861 kvm_apic_post_state_restore(vcpu, s);
2862 update_cr8_intercept(vcpu);
2863
2864 return 0;
2865 }
2866
2867 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2868 struct kvm_interrupt *irq)
2869 {
2870 if (irq->irq >= KVM_NR_INTERRUPTS)
2871 return -EINVAL;
2872 if (irqchip_in_kernel(vcpu->kvm))
2873 return -ENXIO;
2874
2875 kvm_queue_interrupt(vcpu, irq->irq, false);
2876 kvm_make_request(KVM_REQ_EVENT, vcpu);
2877
2878 return 0;
2879 }
2880
2881 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2882 {
2883 kvm_inject_nmi(vcpu);
2884
2885 return 0;
2886 }
2887
2888 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2889 struct kvm_tpr_access_ctl *tac)
2890 {
2891 if (tac->flags)
2892 return -EINVAL;
2893 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2894 return 0;
2895 }
2896
2897 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2898 u64 mcg_cap)
2899 {
2900 int r;
2901 unsigned bank_num = mcg_cap & 0xff, bank;
2902
2903 r = -EINVAL;
2904 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2905 goto out;
2906 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2907 goto out;
2908 r = 0;
2909 vcpu->arch.mcg_cap = mcg_cap;
2910 /* Init IA32_MCG_CTL to all 1s */
2911 if (mcg_cap & MCG_CTL_P)
2912 vcpu->arch.mcg_ctl = ~(u64)0;
2913 /* Init IA32_MCi_CTL to all 1s */
2914 for (bank = 0; bank < bank_num; bank++)
2915 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2916 out:
2917 return r;
2918 }
2919
2920 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2921 struct kvm_x86_mce *mce)
2922 {
2923 u64 mcg_cap = vcpu->arch.mcg_cap;
2924 unsigned bank_num = mcg_cap & 0xff;
2925 u64 *banks = vcpu->arch.mce_banks;
2926
2927 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2928 return -EINVAL;
2929 /*
2930 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2931 * reporting is disabled
2932 */
2933 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2934 vcpu->arch.mcg_ctl != ~(u64)0)
2935 return 0;
2936 banks += 4 * mce->bank;
2937 /*
2938 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2939 * reporting is disabled for the bank
2940 */
2941 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2942 return 0;
2943 if (mce->status & MCI_STATUS_UC) {
2944 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2945 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2946 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2947 return 0;
2948 }
2949 if (banks[1] & MCI_STATUS_VAL)
2950 mce->status |= MCI_STATUS_OVER;
2951 banks[2] = mce->addr;
2952 banks[3] = mce->misc;
2953 vcpu->arch.mcg_status = mce->mcg_status;
2954 banks[1] = mce->status;
2955 kvm_queue_exception(vcpu, MC_VECTOR);
2956 } else if (!(banks[1] & MCI_STATUS_VAL)
2957 || !(banks[1] & MCI_STATUS_UC)) {
2958 if (banks[1] & MCI_STATUS_VAL)
2959 mce->status |= MCI_STATUS_OVER;
2960 banks[2] = mce->addr;
2961 banks[3] = mce->misc;
2962 banks[1] = mce->status;
2963 } else
2964 banks[1] |= MCI_STATUS_OVER;
2965 return 0;
2966 }
2967
2968 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2969 struct kvm_vcpu_events *events)
2970 {
2971 process_nmi(vcpu);
2972 events->exception.injected =
2973 vcpu->arch.exception.pending &&
2974 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2975 events->exception.nr = vcpu->arch.exception.nr;
2976 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2977 events->exception.pad = 0;
2978 events->exception.error_code = vcpu->arch.exception.error_code;
2979
2980 events->interrupt.injected =
2981 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2982 events->interrupt.nr = vcpu->arch.interrupt.nr;
2983 events->interrupt.soft = 0;
2984 events->interrupt.shadow =
2985 kvm_x86_ops->get_interrupt_shadow(vcpu,
2986 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2987
2988 events->nmi.injected = vcpu->arch.nmi_injected;
2989 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2990 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2991 events->nmi.pad = 0;
2992
2993 events->sipi_vector = 0; /* never valid when reporting to user space */
2994
2995 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2996 | KVM_VCPUEVENT_VALID_SHADOW);
2997 memset(&events->reserved, 0, sizeof(events->reserved));
2998 }
2999
3000 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3001 struct kvm_vcpu_events *events)
3002 {
3003 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3004 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3005 | KVM_VCPUEVENT_VALID_SHADOW))
3006 return -EINVAL;
3007
3008 process_nmi(vcpu);
3009 vcpu->arch.exception.pending = events->exception.injected;
3010 vcpu->arch.exception.nr = events->exception.nr;
3011 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3012 vcpu->arch.exception.error_code = events->exception.error_code;
3013
3014 vcpu->arch.interrupt.pending = events->interrupt.injected;
3015 vcpu->arch.interrupt.nr = events->interrupt.nr;
3016 vcpu->arch.interrupt.soft = events->interrupt.soft;
3017 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3018 kvm_x86_ops->set_interrupt_shadow(vcpu,
3019 events->interrupt.shadow);
3020
3021 vcpu->arch.nmi_injected = events->nmi.injected;
3022 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3023 vcpu->arch.nmi_pending = events->nmi.pending;
3024 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3025
3026 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3027 kvm_vcpu_has_lapic(vcpu))
3028 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3029
3030 kvm_make_request(KVM_REQ_EVENT, vcpu);
3031
3032 return 0;
3033 }
3034
3035 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3036 struct kvm_debugregs *dbgregs)
3037 {
3038 unsigned long val;
3039
3040 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3041 _kvm_get_dr(vcpu, 6, &val);
3042 dbgregs->dr6 = val;
3043 dbgregs->dr7 = vcpu->arch.dr7;
3044 dbgregs->flags = 0;
3045 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3046 }
3047
3048 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3049 struct kvm_debugregs *dbgregs)
3050 {
3051 if (dbgregs->flags)
3052 return -EINVAL;
3053
3054 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3055 vcpu->arch.dr6 = dbgregs->dr6;
3056 kvm_update_dr6(vcpu);
3057 vcpu->arch.dr7 = dbgregs->dr7;
3058 kvm_update_dr7(vcpu);
3059
3060 return 0;
3061 }
3062
3063 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3064 struct kvm_xsave *guest_xsave)
3065 {
3066 if (cpu_has_xsave) {
3067 memcpy(guest_xsave->region,
3068 &vcpu->arch.guest_fpu.state->xsave,
3069 vcpu->arch.guest_xstate_size);
3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3071 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3072 } else {
3073 memcpy(guest_xsave->region,
3074 &vcpu->arch.guest_fpu.state->fxsave,
3075 sizeof(struct i387_fxsave_struct));
3076 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3077 XSTATE_FPSSE;
3078 }
3079 }
3080
3081 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3082 struct kvm_xsave *guest_xsave)
3083 {
3084 u64 xstate_bv =
3085 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3086
3087 if (cpu_has_xsave) {
3088 /*
3089 * Here we allow setting states that are not present in
3090 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3091 * with old userspace.
3092 */
3093 if (xstate_bv & ~kvm_supported_xcr0())
3094 return -EINVAL;
3095 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3096 guest_xsave->region, vcpu->arch.guest_xstate_size);
3097 } else {
3098 if (xstate_bv & ~XSTATE_FPSSE)
3099 return -EINVAL;
3100 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3101 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3102 }
3103 return 0;
3104 }
3105
3106 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3107 struct kvm_xcrs *guest_xcrs)
3108 {
3109 if (!cpu_has_xsave) {
3110 guest_xcrs->nr_xcrs = 0;
3111 return;
3112 }
3113
3114 guest_xcrs->nr_xcrs = 1;
3115 guest_xcrs->flags = 0;
3116 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3117 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3118 }
3119
3120 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3121 struct kvm_xcrs *guest_xcrs)
3122 {
3123 int i, r = 0;
3124
3125 if (!cpu_has_xsave)
3126 return -EINVAL;
3127
3128 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3129 return -EINVAL;
3130
3131 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3132 /* Only support XCR0 currently */
3133 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3134 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3135 guest_xcrs->xcrs[i].value);
3136 break;
3137 }
3138 if (r)
3139 r = -EINVAL;
3140 return r;
3141 }
3142
3143 /*
3144 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3145 * stopped by the hypervisor. This function will be called from the host only.
3146 * EINVAL is returned when the host attempts to set the flag for a guest that
3147 * does not support pv clocks.
3148 */
3149 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3150 {
3151 if (!vcpu->arch.pv_time_enabled)
3152 return -EINVAL;
3153 vcpu->arch.pvclock_set_guest_stopped_request = true;
3154 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3155 return 0;
3156 }
3157
3158 long kvm_arch_vcpu_ioctl(struct file *filp,
3159 unsigned int ioctl, unsigned long arg)
3160 {
3161 struct kvm_vcpu *vcpu = filp->private_data;
3162 void __user *argp = (void __user *)arg;
3163 int r;
3164 union {
3165 struct kvm_lapic_state *lapic;
3166 struct kvm_xsave *xsave;
3167 struct kvm_xcrs *xcrs;
3168 void *buffer;
3169 } u;
3170
3171 u.buffer = NULL;
3172 switch (ioctl) {
3173 case KVM_GET_LAPIC: {
3174 r = -EINVAL;
3175 if (!vcpu->arch.apic)
3176 goto out;
3177 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3178
3179 r = -ENOMEM;
3180 if (!u.lapic)
3181 goto out;
3182 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3183 if (r)
3184 goto out;
3185 r = -EFAULT;
3186 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3187 goto out;
3188 r = 0;
3189 break;
3190 }
3191 case KVM_SET_LAPIC: {
3192 r = -EINVAL;
3193 if (!vcpu->arch.apic)
3194 goto out;
3195 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3196 if (IS_ERR(u.lapic))
3197 return PTR_ERR(u.lapic);
3198
3199 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3200 break;
3201 }
3202 case KVM_INTERRUPT: {
3203 struct kvm_interrupt irq;
3204
3205 r = -EFAULT;
3206 if (copy_from_user(&irq, argp, sizeof irq))
3207 goto out;
3208 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3209 break;
3210 }
3211 case KVM_NMI: {
3212 r = kvm_vcpu_ioctl_nmi(vcpu);
3213 break;
3214 }
3215 case KVM_SET_CPUID: {
3216 struct kvm_cpuid __user *cpuid_arg = argp;
3217 struct kvm_cpuid cpuid;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3221 goto out;
3222 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3223 break;
3224 }
3225 case KVM_SET_CPUID2: {
3226 struct kvm_cpuid2 __user *cpuid_arg = argp;
3227 struct kvm_cpuid2 cpuid;
3228
3229 r = -EFAULT;
3230 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3231 goto out;
3232 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3233 cpuid_arg->entries);
3234 break;
3235 }
3236 case KVM_GET_CPUID2: {
3237 struct kvm_cpuid2 __user *cpuid_arg = argp;
3238 struct kvm_cpuid2 cpuid;
3239
3240 r = -EFAULT;
3241 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3242 goto out;
3243 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3244 cpuid_arg->entries);
3245 if (r)
3246 goto out;
3247 r = -EFAULT;
3248 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3249 goto out;
3250 r = 0;
3251 break;
3252 }
3253 case KVM_GET_MSRS:
3254 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3255 break;
3256 case KVM_SET_MSRS:
3257 r = msr_io(vcpu, argp, do_set_msr, 0);
3258 break;
3259 case KVM_TPR_ACCESS_REPORTING: {
3260 struct kvm_tpr_access_ctl tac;
3261
3262 r = -EFAULT;
3263 if (copy_from_user(&tac, argp, sizeof tac))
3264 goto out;
3265 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3266 if (r)
3267 goto out;
3268 r = -EFAULT;
3269 if (copy_to_user(argp, &tac, sizeof tac))
3270 goto out;
3271 r = 0;
3272 break;
3273 };
3274 case KVM_SET_VAPIC_ADDR: {
3275 struct kvm_vapic_addr va;
3276
3277 r = -EINVAL;
3278 if (!irqchip_in_kernel(vcpu->kvm))
3279 goto out;
3280 r = -EFAULT;
3281 if (copy_from_user(&va, argp, sizeof va))
3282 goto out;
3283 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3284 break;
3285 }
3286 case KVM_X86_SETUP_MCE: {
3287 u64 mcg_cap;
3288
3289 r = -EFAULT;
3290 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3291 goto out;
3292 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3293 break;
3294 }
3295 case KVM_X86_SET_MCE: {
3296 struct kvm_x86_mce mce;
3297
3298 r = -EFAULT;
3299 if (copy_from_user(&mce, argp, sizeof mce))
3300 goto out;
3301 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3302 break;
3303 }
3304 case KVM_GET_VCPU_EVENTS: {
3305 struct kvm_vcpu_events events;
3306
3307 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3308
3309 r = -EFAULT;
3310 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3311 break;
3312 r = 0;
3313 break;
3314 }
3315 case KVM_SET_VCPU_EVENTS: {
3316 struct kvm_vcpu_events events;
3317
3318 r = -EFAULT;
3319 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3320 break;
3321
3322 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3323 break;
3324 }
3325 case KVM_GET_DEBUGREGS: {
3326 struct kvm_debugregs dbgregs;
3327
3328 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3329
3330 r = -EFAULT;
3331 if (copy_to_user(argp, &dbgregs,
3332 sizeof(struct kvm_debugregs)))
3333 break;
3334 r = 0;
3335 break;
3336 }
3337 case KVM_SET_DEBUGREGS: {
3338 struct kvm_debugregs dbgregs;
3339
3340 r = -EFAULT;
3341 if (copy_from_user(&dbgregs, argp,
3342 sizeof(struct kvm_debugregs)))
3343 break;
3344
3345 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3346 break;
3347 }
3348 case KVM_GET_XSAVE: {
3349 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3350 r = -ENOMEM;
3351 if (!u.xsave)
3352 break;
3353
3354 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3355
3356 r = -EFAULT;
3357 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3358 break;
3359 r = 0;
3360 break;
3361 }
3362 case KVM_SET_XSAVE: {
3363 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3364 if (IS_ERR(u.xsave))
3365 return PTR_ERR(u.xsave);
3366
3367 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3368 break;
3369 }
3370 case KVM_GET_XCRS: {
3371 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3372 r = -ENOMEM;
3373 if (!u.xcrs)
3374 break;
3375
3376 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3377
3378 r = -EFAULT;
3379 if (copy_to_user(argp, u.xcrs,
3380 sizeof(struct kvm_xcrs)))
3381 break;
3382 r = 0;
3383 break;
3384 }
3385 case KVM_SET_XCRS: {
3386 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3387 if (IS_ERR(u.xcrs))
3388 return PTR_ERR(u.xcrs);
3389
3390 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3391 break;
3392 }
3393 case KVM_SET_TSC_KHZ: {
3394 u32 user_tsc_khz;
3395
3396 r = -EINVAL;
3397 user_tsc_khz = (u32)arg;
3398
3399 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3400 goto out;
3401
3402 if (user_tsc_khz == 0)
3403 user_tsc_khz = tsc_khz;
3404
3405 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3406
3407 r = 0;
3408 goto out;
3409 }
3410 case KVM_GET_TSC_KHZ: {
3411 r = vcpu->arch.virtual_tsc_khz;
3412 goto out;
3413 }
3414 case KVM_KVMCLOCK_CTRL: {
3415 r = kvm_set_guest_paused(vcpu);
3416 goto out;
3417 }
3418 default:
3419 r = -EINVAL;
3420 }
3421 out:
3422 kfree(u.buffer);
3423 return r;
3424 }
3425
3426 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3427 {
3428 return VM_FAULT_SIGBUS;
3429 }
3430
3431 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3432 {
3433 int ret;
3434
3435 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3436 return -EINVAL;
3437 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3438 return ret;
3439 }
3440
3441 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3442 u64 ident_addr)
3443 {
3444 kvm->arch.ept_identity_map_addr = ident_addr;
3445 return 0;
3446 }
3447
3448 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3449 u32 kvm_nr_mmu_pages)
3450 {
3451 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3452 return -EINVAL;
3453
3454 mutex_lock(&kvm->slots_lock);
3455
3456 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3457 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3458
3459 mutex_unlock(&kvm->slots_lock);
3460 return 0;
3461 }
3462
3463 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3464 {
3465 return kvm->arch.n_max_mmu_pages;
3466 }
3467
3468 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3469 {
3470 int r;
3471
3472 r = 0;
3473 switch (chip->chip_id) {
3474 case KVM_IRQCHIP_PIC_MASTER:
3475 memcpy(&chip->chip.pic,
3476 &pic_irqchip(kvm)->pics[0],
3477 sizeof(struct kvm_pic_state));
3478 break;
3479 case KVM_IRQCHIP_PIC_SLAVE:
3480 memcpy(&chip->chip.pic,
3481 &pic_irqchip(kvm)->pics[1],
3482 sizeof(struct kvm_pic_state));
3483 break;
3484 case KVM_IRQCHIP_IOAPIC:
3485 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3486 break;
3487 default:
3488 r = -EINVAL;
3489 break;
3490 }
3491 return r;
3492 }
3493
3494 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3495 {
3496 int r;
3497
3498 r = 0;
3499 switch (chip->chip_id) {
3500 case KVM_IRQCHIP_PIC_MASTER:
3501 spin_lock(&pic_irqchip(kvm)->lock);
3502 memcpy(&pic_irqchip(kvm)->pics[0],
3503 &chip->chip.pic,
3504 sizeof(struct kvm_pic_state));
3505 spin_unlock(&pic_irqchip(kvm)->lock);
3506 break;
3507 case KVM_IRQCHIP_PIC_SLAVE:
3508 spin_lock(&pic_irqchip(kvm)->lock);
3509 memcpy(&pic_irqchip(kvm)->pics[1],
3510 &chip->chip.pic,
3511 sizeof(struct kvm_pic_state));
3512 spin_unlock(&pic_irqchip(kvm)->lock);
3513 break;
3514 case KVM_IRQCHIP_IOAPIC:
3515 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3516 break;
3517 default:
3518 r = -EINVAL;
3519 break;
3520 }
3521 kvm_pic_update_irq(pic_irqchip(kvm));
3522 return r;
3523 }
3524
3525 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3526 {
3527 int r = 0;
3528
3529 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3530 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3531 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3532 return r;
3533 }
3534
3535 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3536 {
3537 int r = 0;
3538
3539 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3540 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3541 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3542 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3543 return r;
3544 }
3545
3546 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3547 {
3548 int r = 0;
3549
3550 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3551 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3552 sizeof(ps->channels));
3553 ps->flags = kvm->arch.vpit->pit_state.flags;
3554 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3555 memset(&ps->reserved, 0, sizeof(ps->reserved));
3556 return r;
3557 }
3558
3559 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3560 {
3561 int r = 0, start = 0;
3562 u32 prev_legacy, cur_legacy;
3563 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3564 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3565 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3566 if (!prev_legacy && cur_legacy)
3567 start = 1;
3568 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3569 sizeof(kvm->arch.vpit->pit_state.channels));
3570 kvm->arch.vpit->pit_state.flags = ps->flags;
3571 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3572 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3573 return r;
3574 }
3575
3576 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3577 struct kvm_reinject_control *control)
3578 {
3579 if (!kvm->arch.vpit)
3580 return -ENXIO;
3581 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3582 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3583 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3584 return 0;
3585 }
3586
3587 /**
3588 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3589 * @kvm: kvm instance
3590 * @log: slot id and address to which we copy the log
3591 *
3592 * We need to keep it in mind that VCPU threads can write to the bitmap
3593 * concurrently. So, to avoid losing data, we keep the following order for
3594 * each bit:
3595 *
3596 * 1. Take a snapshot of the bit and clear it if needed.
3597 * 2. Write protect the corresponding page.
3598 * 3. Flush TLB's if needed.
3599 * 4. Copy the snapshot to the userspace.
3600 *
3601 * Between 2 and 3, the guest may write to the page using the remaining TLB
3602 * entry. This is not a problem because the page will be reported dirty at
3603 * step 4 using the snapshot taken before and step 3 ensures that successive
3604 * writes will be logged for the next call.
3605 */
3606 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3607 {
3608 int r;
3609 struct kvm_memory_slot *memslot;
3610 unsigned long n, i;
3611 unsigned long *dirty_bitmap;
3612 unsigned long *dirty_bitmap_buffer;
3613 bool is_dirty = false;
3614
3615 mutex_lock(&kvm->slots_lock);
3616
3617 r = -EINVAL;
3618 if (log->slot >= KVM_USER_MEM_SLOTS)
3619 goto out;
3620
3621 memslot = id_to_memslot(kvm->memslots, log->slot);
3622
3623 dirty_bitmap = memslot->dirty_bitmap;
3624 r = -ENOENT;
3625 if (!dirty_bitmap)
3626 goto out;
3627
3628 n = kvm_dirty_bitmap_bytes(memslot);
3629
3630 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3631 memset(dirty_bitmap_buffer, 0, n);
3632
3633 spin_lock(&kvm->mmu_lock);
3634
3635 for (i = 0; i < n / sizeof(long); i++) {
3636 unsigned long mask;
3637 gfn_t offset;
3638
3639 if (!dirty_bitmap[i])
3640 continue;
3641
3642 is_dirty = true;
3643
3644 mask = xchg(&dirty_bitmap[i], 0);
3645 dirty_bitmap_buffer[i] = mask;
3646
3647 offset = i * BITS_PER_LONG;
3648 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3649 }
3650 if (is_dirty)
3651 kvm_flush_remote_tlbs(kvm);
3652
3653 spin_unlock(&kvm->mmu_lock);
3654
3655 r = -EFAULT;
3656 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3657 goto out;
3658
3659 r = 0;
3660 out:
3661 mutex_unlock(&kvm->slots_lock);
3662 return r;
3663 }
3664
3665 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3666 bool line_status)
3667 {
3668 if (!irqchip_in_kernel(kvm))
3669 return -ENXIO;
3670
3671 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3672 irq_event->irq, irq_event->level,
3673 line_status);
3674 return 0;
3675 }
3676
3677 long kvm_arch_vm_ioctl(struct file *filp,
3678 unsigned int ioctl, unsigned long arg)
3679 {
3680 struct kvm *kvm = filp->private_data;
3681 void __user *argp = (void __user *)arg;
3682 int r = -ENOTTY;
3683 /*
3684 * This union makes it completely explicit to gcc-3.x
3685 * that these two variables' stack usage should be
3686 * combined, not added together.
3687 */
3688 union {
3689 struct kvm_pit_state ps;
3690 struct kvm_pit_state2 ps2;
3691 struct kvm_pit_config pit_config;
3692 } u;
3693
3694 switch (ioctl) {
3695 case KVM_SET_TSS_ADDR:
3696 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3697 break;
3698 case KVM_SET_IDENTITY_MAP_ADDR: {
3699 u64 ident_addr;
3700
3701 r = -EFAULT;
3702 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3703 goto out;
3704 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3705 break;
3706 }
3707 case KVM_SET_NR_MMU_PAGES:
3708 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3709 break;
3710 case KVM_GET_NR_MMU_PAGES:
3711 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3712 break;
3713 case KVM_CREATE_IRQCHIP: {
3714 struct kvm_pic *vpic;
3715
3716 mutex_lock(&kvm->lock);
3717 r = -EEXIST;
3718 if (kvm->arch.vpic)
3719 goto create_irqchip_unlock;
3720 r = -EINVAL;
3721 if (atomic_read(&kvm->online_vcpus))
3722 goto create_irqchip_unlock;
3723 r = -ENOMEM;
3724 vpic = kvm_create_pic(kvm);
3725 if (vpic) {
3726 r = kvm_ioapic_init(kvm);
3727 if (r) {
3728 mutex_lock(&kvm->slots_lock);
3729 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3730 &vpic->dev_master);
3731 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3732 &vpic->dev_slave);
3733 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3734 &vpic->dev_eclr);
3735 mutex_unlock(&kvm->slots_lock);
3736 kfree(vpic);
3737 goto create_irqchip_unlock;
3738 }
3739 } else
3740 goto create_irqchip_unlock;
3741 smp_wmb();
3742 kvm->arch.vpic = vpic;
3743 smp_wmb();
3744 r = kvm_setup_default_irq_routing(kvm);
3745 if (r) {
3746 mutex_lock(&kvm->slots_lock);
3747 mutex_lock(&kvm->irq_lock);
3748 kvm_ioapic_destroy(kvm);
3749 kvm_destroy_pic(kvm);
3750 mutex_unlock(&kvm->irq_lock);
3751 mutex_unlock(&kvm->slots_lock);
3752 }
3753 create_irqchip_unlock:
3754 mutex_unlock(&kvm->lock);
3755 break;
3756 }
3757 case KVM_CREATE_PIT:
3758 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3759 goto create_pit;
3760 case KVM_CREATE_PIT2:
3761 r = -EFAULT;
3762 if (copy_from_user(&u.pit_config, argp,
3763 sizeof(struct kvm_pit_config)))
3764 goto out;
3765 create_pit:
3766 mutex_lock(&kvm->slots_lock);
3767 r = -EEXIST;
3768 if (kvm->arch.vpit)
3769 goto create_pit_unlock;
3770 r = -ENOMEM;
3771 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3772 if (kvm->arch.vpit)
3773 r = 0;
3774 create_pit_unlock:
3775 mutex_unlock(&kvm->slots_lock);
3776 break;
3777 case KVM_GET_IRQCHIP: {
3778 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3779 struct kvm_irqchip *chip;
3780
3781 chip = memdup_user(argp, sizeof(*chip));
3782 if (IS_ERR(chip)) {
3783 r = PTR_ERR(chip);
3784 goto out;
3785 }
3786
3787 r = -ENXIO;
3788 if (!irqchip_in_kernel(kvm))
3789 goto get_irqchip_out;
3790 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3791 if (r)
3792 goto get_irqchip_out;
3793 r = -EFAULT;
3794 if (copy_to_user(argp, chip, sizeof *chip))
3795 goto get_irqchip_out;
3796 r = 0;
3797 get_irqchip_out:
3798 kfree(chip);
3799 break;
3800 }
3801 case KVM_SET_IRQCHIP: {
3802 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3803 struct kvm_irqchip *chip;
3804
3805 chip = memdup_user(argp, sizeof(*chip));
3806 if (IS_ERR(chip)) {
3807 r = PTR_ERR(chip);
3808 goto out;
3809 }
3810
3811 r = -ENXIO;
3812 if (!irqchip_in_kernel(kvm))
3813 goto set_irqchip_out;
3814 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3815 if (r)
3816 goto set_irqchip_out;
3817 r = 0;
3818 set_irqchip_out:
3819 kfree(chip);
3820 break;
3821 }
3822 case KVM_GET_PIT: {
3823 r = -EFAULT;
3824 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3825 goto out;
3826 r = -ENXIO;
3827 if (!kvm->arch.vpit)
3828 goto out;
3829 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3830 if (r)
3831 goto out;
3832 r = -EFAULT;
3833 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3834 goto out;
3835 r = 0;
3836 break;
3837 }
3838 case KVM_SET_PIT: {
3839 r = -EFAULT;
3840 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3841 goto out;
3842 r = -ENXIO;
3843 if (!kvm->arch.vpit)
3844 goto out;
3845 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3846 break;
3847 }
3848 case KVM_GET_PIT2: {
3849 r = -ENXIO;
3850 if (!kvm->arch.vpit)
3851 goto out;
3852 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3853 if (r)
3854 goto out;
3855 r = -EFAULT;
3856 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3857 goto out;
3858 r = 0;
3859 break;
3860 }
3861 case KVM_SET_PIT2: {
3862 r = -EFAULT;
3863 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3864 goto out;
3865 r = -ENXIO;
3866 if (!kvm->arch.vpit)
3867 goto out;
3868 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3869 break;
3870 }
3871 case KVM_REINJECT_CONTROL: {
3872 struct kvm_reinject_control control;
3873 r = -EFAULT;
3874 if (copy_from_user(&control, argp, sizeof(control)))
3875 goto out;
3876 r = kvm_vm_ioctl_reinject(kvm, &control);
3877 break;
3878 }
3879 case KVM_XEN_HVM_CONFIG: {
3880 r = -EFAULT;
3881 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3882 sizeof(struct kvm_xen_hvm_config)))
3883 goto out;
3884 r = -EINVAL;
3885 if (kvm->arch.xen_hvm_config.flags)
3886 goto out;
3887 r = 0;
3888 break;
3889 }
3890 case KVM_SET_CLOCK: {
3891 struct kvm_clock_data user_ns;
3892 u64 now_ns;
3893 s64 delta;
3894
3895 r = -EFAULT;
3896 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3897 goto out;
3898
3899 r = -EINVAL;
3900 if (user_ns.flags)
3901 goto out;
3902
3903 r = 0;
3904 local_irq_disable();
3905 now_ns = get_kernel_ns();
3906 delta = user_ns.clock - now_ns;
3907 local_irq_enable();
3908 kvm->arch.kvmclock_offset = delta;
3909 kvm_gen_update_masterclock(kvm);
3910 break;
3911 }
3912 case KVM_GET_CLOCK: {
3913 struct kvm_clock_data user_ns;
3914 u64 now_ns;
3915
3916 local_irq_disable();
3917 now_ns = get_kernel_ns();
3918 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3919 local_irq_enable();
3920 user_ns.flags = 0;
3921 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3922
3923 r = -EFAULT;
3924 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3925 goto out;
3926 r = 0;
3927 break;
3928 }
3929
3930 default:
3931 ;
3932 }
3933 out:
3934 return r;
3935 }
3936
3937 static void kvm_init_msr_list(void)
3938 {
3939 u32 dummy[2];
3940 unsigned i, j;
3941
3942 /* skip the first msrs in the list. KVM-specific */
3943 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3944 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3945 continue;
3946
3947 /*
3948 * Even MSRs that are valid in the host may not be exposed
3949 * to the guests in some cases. We could work around this
3950 * in VMX with the generic MSR save/load machinery, but it
3951 * is not really worthwhile since it will really only
3952 * happen with nested virtualization.
3953 */
3954 switch (msrs_to_save[i]) {
3955 case MSR_IA32_BNDCFGS:
3956 if (!kvm_x86_ops->mpx_supported())
3957 continue;
3958 break;
3959 default:
3960 break;
3961 }
3962
3963 if (j < i)
3964 msrs_to_save[j] = msrs_to_save[i];
3965 j++;
3966 }
3967 num_msrs_to_save = j;
3968 }
3969
3970 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3971 const void *v)
3972 {
3973 int handled = 0;
3974 int n;
3975
3976 do {
3977 n = min(len, 8);
3978 if (!(vcpu->arch.apic &&
3979 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3980 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3981 break;
3982 handled += n;
3983 addr += n;
3984 len -= n;
3985 v += n;
3986 } while (len);
3987
3988 return handled;
3989 }
3990
3991 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3992 {
3993 int handled = 0;
3994 int n;
3995
3996 do {
3997 n = min(len, 8);
3998 if (!(vcpu->arch.apic &&
3999 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4000 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4001 break;
4002 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4003 handled += n;
4004 addr += n;
4005 len -= n;
4006 v += n;
4007 } while (len);
4008
4009 return handled;
4010 }
4011
4012 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4013 struct kvm_segment *var, int seg)
4014 {
4015 kvm_x86_ops->set_segment(vcpu, var, seg);
4016 }
4017
4018 void kvm_get_segment(struct kvm_vcpu *vcpu,
4019 struct kvm_segment *var, int seg)
4020 {
4021 kvm_x86_ops->get_segment(vcpu, var, seg);
4022 }
4023
4024 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4025 {
4026 gpa_t t_gpa;
4027 struct x86_exception exception;
4028
4029 BUG_ON(!mmu_is_nested(vcpu));
4030
4031 /* NPT walks are always user-walks */
4032 access |= PFERR_USER_MASK;
4033 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4034
4035 return t_gpa;
4036 }
4037
4038 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4039 struct x86_exception *exception)
4040 {
4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4042 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4043 }
4044
4045 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4046 struct x86_exception *exception)
4047 {
4048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4049 access |= PFERR_FETCH_MASK;
4050 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4051 }
4052
4053 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4054 struct x86_exception *exception)
4055 {
4056 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4057 access |= PFERR_WRITE_MASK;
4058 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4059 }
4060
4061 /* uses this to access any guest's mapped memory without checking CPL */
4062 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4063 struct x86_exception *exception)
4064 {
4065 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4066 }
4067
4068 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4069 struct kvm_vcpu *vcpu, u32 access,
4070 struct x86_exception *exception)
4071 {
4072 void *data = val;
4073 int r = X86EMUL_CONTINUE;
4074
4075 while (bytes) {
4076 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4077 exception);
4078 unsigned offset = addr & (PAGE_SIZE-1);
4079 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4080 int ret;
4081
4082 if (gpa == UNMAPPED_GVA)
4083 return X86EMUL_PROPAGATE_FAULT;
4084 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4085 if (ret < 0) {
4086 r = X86EMUL_IO_NEEDED;
4087 goto out;
4088 }
4089
4090 bytes -= toread;
4091 data += toread;
4092 addr += toread;
4093 }
4094 out:
4095 return r;
4096 }
4097
4098 /* used for instruction fetching */
4099 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4100 gva_t addr, void *val, unsigned int bytes,
4101 struct x86_exception *exception)
4102 {
4103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4104 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4105
4106 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4107 access | PFERR_FETCH_MASK,
4108 exception);
4109 }
4110
4111 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4112 gva_t addr, void *val, unsigned int bytes,
4113 struct x86_exception *exception)
4114 {
4115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4116 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4117
4118 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4119 exception);
4120 }
4121 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4122
4123 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4124 gva_t addr, void *val, unsigned int bytes,
4125 struct x86_exception *exception)
4126 {
4127 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4128 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4129 }
4130
4131 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4132 gva_t addr, void *val,
4133 unsigned int bytes,
4134 struct x86_exception *exception)
4135 {
4136 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4137 void *data = val;
4138 int r = X86EMUL_CONTINUE;
4139
4140 while (bytes) {
4141 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4142 PFERR_WRITE_MASK,
4143 exception);
4144 unsigned offset = addr & (PAGE_SIZE-1);
4145 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4146 int ret;
4147
4148 if (gpa == UNMAPPED_GVA)
4149 return X86EMUL_PROPAGATE_FAULT;
4150 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4151 if (ret < 0) {
4152 r = X86EMUL_IO_NEEDED;
4153 goto out;
4154 }
4155
4156 bytes -= towrite;
4157 data += towrite;
4158 addr += towrite;
4159 }
4160 out:
4161 return r;
4162 }
4163 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4164
4165 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4166 gpa_t *gpa, struct x86_exception *exception,
4167 bool write)
4168 {
4169 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4170 | (write ? PFERR_WRITE_MASK : 0);
4171
4172 if (vcpu_match_mmio_gva(vcpu, gva)
4173 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4174 vcpu->arch.access, access)) {
4175 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4176 (gva & (PAGE_SIZE - 1));
4177 trace_vcpu_match_mmio(gva, *gpa, write, false);
4178 return 1;
4179 }
4180
4181 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4182
4183 if (*gpa == UNMAPPED_GVA)
4184 return -1;
4185
4186 /* For APIC access vmexit */
4187 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4188 return 1;
4189
4190 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4191 trace_vcpu_match_mmio(gva, *gpa, write, true);
4192 return 1;
4193 }
4194
4195 return 0;
4196 }
4197
4198 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4199 const void *val, int bytes)
4200 {
4201 int ret;
4202
4203 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4204 if (ret < 0)
4205 return 0;
4206 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4207 return 1;
4208 }
4209
4210 struct read_write_emulator_ops {
4211 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4212 int bytes);
4213 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4214 void *val, int bytes);
4215 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4216 int bytes, void *val);
4217 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4218 void *val, int bytes);
4219 bool write;
4220 };
4221
4222 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4223 {
4224 if (vcpu->mmio_read_completed) {
4225 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4226 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4227 vcpu->mmio_read_completed = 0;
4228 return 1;
4229 }
4230
4231 return 0;
4232 }
4233
4234 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4235 void *val, int bytes)
4236 {
4237 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4238 }
4239
4240 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4241 void *val, int bytes)
4242 {
4243 return emulator_write_phys(vcpu, gpa, val, bytes);
4244 }
4245
4246 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4247 {
4248 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4249 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4250 }
4251
4252 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4253 void *val, int bytes)
4254 {
4255 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4256 return X86EMUL_IO_NEEDED;
4257 }
4258
4259 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4260 void *val, int bytes)
4261 {
4262 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4263
4264 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4265 return X86EMUL_CONTINUE;
4266 }
4267
4268 static const struct read_write_emulator_ops read_emultor = {
4269 .read_write_prepare = read_prepare,
4270 .read_write_emulate = read_emulate,
4271 .read_write_mmio = vcpu_mmio_read,
4272 .read_write_exit_mmio = read_exit_mmio,
4273 };
4274
4275 static const struct read_write_emulator_ops write_emultor = {
4276 .read_write_emulate = write_emulate,
4277 .read_write_mmio = write_mmio,
4278 .read_write_exit_mmio = write_exit_mmio,
4279 .write = true,
4280 };
4281
4282 static int emulator_read_write_onepage(unsigned long addr, void *val,
4283 unsigned int bytes,
4284 struct x86_exception *exception,
4285 struct kvm_vcpu *vcpu,
4286 const struct read_write_emulator_ops *ops)
4287 {
4288 gpa_t gpa;
4289 int handled, ret;
4290 bool write = ops->write;
4291 struct kvm_mmio_fragment *frag;
4292
4293 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4294
4295 if (ret < 0)
4296 return X86EMUL_PROPAGATE_FAULT;
4297
4298 /* For APIC access vmexit */
4299 if (ret)
4300 goto mmio;
4301
4302 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4303 return X86EMUL_CONTINUE;
4304
4305 mmio:
4306 /*
4307 * Is this MMIO handled locally?
4308 */
4309 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4310 if (handled == bytes)
4311 return X86EMUL_CONTINUE;
4312
4313 gpa += handled;
4314 bytes -= handled;
4315 val += handled;
4316
4317 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4318 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4319 frag->gpa = gpa;
4320 frag->data = val;
4321 frag->len = bytes;
4322 return X86EMUL_CONTINUE;
4323 }
4324
4325 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4326 void *val, unsigned int bytes,
4327 struct x86_exception *exception,
4328 const struct read_write_emulator_ops *ops)
4329 {
4330 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4331 gpa_t gpa;
4332 int rc;
4333
4334 if (ops->read_write_prepare &&
4335 ops->read_write_prepare(vcpu, val, bytes))
4336 return X86EMUL_CONTINUE;
4337
4338 vcpu->mmio_nr_fragments = 0;
4339
4340 /* Crossing a page boundary? */
4341 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4342 int now;
4343
4344 now = -addr & ~PAGE_MASK;
4345 rc = emulator_read_write_onepage(addr, val, now, exception,
4346 vcpu, ops);
4347
4348 if (rc != X86EMUL_CONTINUE)
4349 return rc;
4350 addr += now;
4351 val += now;
4352 bytes -= now;
4353 }
4354
4355 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4356 vcpu, ops);
4357 if (rc != X86EMUL_CONTINUE)
4358 return rc;
4359
4360 if (!vcpu->mmio_nr_fragments)
4361 return rc;
4362
4363 gpa = vcpu->mmio_fragments[0].gpa;
4364
4365 vcpu->mmio_needed = 1;
4366 vcpu->mmio_cur_fragment = 0;
4367
4368 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4369 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4370 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4371 vcpu->run->mmio.phys_addr = gpa;
4372
4373 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4374 }
4375
4376 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4377 unsigned long addr,
4378 void *val,
4379 unsigned int bytes,
4380 struct x86_exception *exception)
4381 {
4382 return emulator_read_write(ctxt, addr, val, bytes,
4383 exception, &read_emultor);
4384 }
4385
4386 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4387 unsigned long addr,
4388 const void *val,
4389 unsigned int bytes,
4390 struct x86_exception *exception)
4391 {
4392 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4393 exception, &write_emultor);
4394 }
4395
4396 #define CMPXCHG_TYPE(t, ptr, old, new) \
4397 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4398
4399 #ifdef CONFIG_X86_64
4400 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4401 #else
4402 # define CMPXCHG64(ptr, old, new) \
4403 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4404 #endif
4405
4406 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4407 unsigned long addr,
4408 const void *old,
4409 const void *new,
4410 unsigned int bytes,
4411 struct x86_exception *exception)
4412 {
4413 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4414 gpa_t gpa;
4415 struct page *page;
4416 char *kaddr;
4417 bool exchanged;
4418
4419 /* guests cmpxchg8b have to be emulated atomically */
4420 if (bytes > 8 || (bytes & (bytes - 1)))
4421 goto emul_write;
4422
4423 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4424
4425 if (gpa == UNMAPPED_GVA ||
4426 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4427 goto emul_write;
4428
4429 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4430 goto emul_write;
4431
4432 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4433 if (is_error_page(page))
4434 goto emul_write;
4435
4436 kaddr = kmap_atomic(page);
4437 kaddr += offset_in_page(gpa);
4438 switch (bytes) {
4439 case 1:
4440 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4441 break;
4442 case 2:
4443 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4444 break;
4445 case 4:
4446 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4447 break;
4448 case 8:
4449 exchanged = CMPXCHG64(kaddr, old, new);
4450 break;
4451 default:
4452 BUG();
4453 }
4454 kunmap_atomic(kaddr);
4455 kvm_release_page_dirty(page);
4456
4457 if (!exchanged)
4458 return X86EMUL_CMPXCHG_FAILED;
4459
4460 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4461 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4462
4463 return X86EMUL_CONTINUE;
4464
4465 emul_write:
4466 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4467
4468 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4469 }
4470
4471 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4472 {
4473 /* TODO: String I/O for in kernel device */
4474 int r;
4475
4476 if (vcpu->arch.pio.in)
4477 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4478 vcpu->arch.pio.size, pd);
4479 else
4480 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4481 vcpu->arch.pio.port, vcpu->arch.pio.size,
4482 pd);
4483 return r;
4484 }
4485
4486 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4487 unsigned short port, void *val,
4488 unsigned int count, bool in)
4489 {
4490 trace_kvm_pio(!in, port, size, count);
4491
4492 vcpu->arch.pio.port = port;
4493 vcpu->arch.pio.in = in;
4494 vcpu->arch.pio.count = count;
4495 vcpu->arch.pio.size = size;
4496
4497 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4498 vcpu->arch.pio.count = 0;
4499 return 1;
4500 }
4501
4502 vcpu->run->exit_reason = KVM_EXIT_IO;
4503 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4504 vcpu->run->io.size = size;
4505 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4506 vcpu->run->io.count = count;
4507 vcpu->run->io.port = port;
4508
4509 return 0;
4510 }
4511
4512 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4513 int size, unsigned short port, void *val,
4514 unsigned int count)
4515 {
4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4517 int ret;
4518
4519 if (vcpu->arch.pio.count)
4520 goto data_avail;
4521
4522 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4523 if (ret) {
4524 data_avail:
4525 memcpy(val, vcpu->arch.pio_data, size * count);
4526 vcpu->arch.pio.count = 0;
4527 return 1;
4528 }
4529
4530 return 0;
4531 }
4532
4533 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4534 int size, unsigned short port,
4535 const void *val, unsigned int count)
4536 {
4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4538
4539 memcpy(vcpu->arch.pio_data, val, size * count);
4540 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4541 }
4542
4543 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4544 {
4545 return kvm_x86_ops->get_segment_base(vcpu, seg);
4546 }
4547
4548 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4549 {
4550 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4551 }
4552
4553 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4554 {
4555 if (!need_emulate_wbinvd(vcpu))
4556 return X86EMUL_CONTINUE;
4557
4558 if (kvm_x86_ops->has_wbinvd_exit()) {
4559 int cpu = get_cpu();
4560
4561 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4562 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4563 wbinvd_ipi, NULL, 1);
4564 put_cpu();
4565 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4566 } else
4567 wbinvd();
4568 return X86EMUL_CONTINUE;
4569 }
4570 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4571
4572 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4573 {
4574 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4575 }
4576
4577 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4578 {
4579 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4580 }
4581
4582 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4583 {
4584
4585 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4586 }
4587
4588 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4589 {
4590 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4591 }
4592
4593 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4594 {
4595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4596 unsigned long value;
4597
4598 switch (cr) {
4599 case 0:
4600 value = kvm_read_cr0(vcpu);
4601 break;
4602 case 2:
4603 value = vcpu->arch.cr2;
4604 break;
4605 case 3:
4606 value = kvm_read_cr3(vcpu);
4607 break;
4608 case 4:
4609 value = kvm_read_cr4(vcpu);
4610 break;
4611 case 8:
4612 value = kvm_get_cr8(vcpu);
4613 break;
4614 default:
4615 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4616 return 0;
4617 }
4618
4619 return value;
4620 }
4621
4622 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4623 {
4624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4625 int res = 0;
4626
4627 switch (cr) {
4628 case 0:
4629 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4630 break;
4631 case 2:
4632 vcpu->arch.cr2 = val;
4633 break;
4634 case 3:
4635 res = kvm_set_cr3(vcpu, val);
4636 break;
4637 case 4:
4638 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4639 break;
4640 case 8:
4641 res = kvm_set_cr8(vcpu, val);
4642 break;
4643 default:
4644 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4645 res = -1;
4646 }
4647
4648 return res;
4649 }
4650
4651 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4652 {
4653 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4654 }
4655
4656 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4657 {
4658 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4659 }
4660
4661 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4662 {
4663 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4664 }
4665
4666 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4667 {
4668 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4669 }
4670
4671 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4672 {
4673 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4674 }
4675
4676 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4677 {
4678 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4679 }
4680
4681 static unsigned long emulator_get_cached_segment_base(
4682 struct x86_emulate_ctxt *ctxt, int seg)
4683 {
4684 return get_segment_base(emul_to_vcpu(ctxt), seg);
4685 }
4686
4687 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4688 struct desc_struct *desc, u32 *base3,
4689 int seg)
4690 {
4691 struct kvm_segment var;
4692
4693 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4694 *selector = var.selector;
4695
4696 if (var.unusable) {
4697 memset(desc, 0, sizeof(*desc));
4698 return false;
4699 }
4700
4701 if (var.g)
4702 var.limit >>= 12;
4703 set_desc_limit(desc, var.limit);
4704 set_desc_base(desc, (unsigned long)var.base);
4705 #ifdef CONFIG_X86_64
4706 if (base3)
4707 *base3 = var.base >> 32;
4708 #endif
4709 desc->type = var.type;
4710 desc->s = var.s;
4711 desc->dpl = var.dpl;
4712 desc->p = var.present;
4713 desc->avl = var.avl;
4714 desc->l = var.l;
4715 desc->d = var.db;
4716 desc->g = var.g;
4717
4718 return true;
4719 }
4720
4721 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4722 struct desc_struct *desc, u32 base3,
4723 int seg)
4724 {
4725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4726 struct kvm_segment var;
4727
4728 var.selector = selector;
4729 var.base = get_desc_base(desc);
4730 #ifdef CONFIG_X86_64
4731 var.base |= ((u64)base3) << 32;
4732 #endif
4733 var.limit = get_desc_limit(desc);
4734 if (desc->g)
4735 var.limit = (var.limit << 12) | 0xfff;
4736 var.type = desc->type;
4737 var.present = desc->p;
4738 var.dpl = desc->dpl;
4739 var.db = desc->d;
4740 var.s = desc->s;
4741 var.l = desc->l;
4742 var.g = desc->g;
4743 var.avl = desc->avl;
4744 var.present = desc->p;
4745 var.unusable = !var.present;
4746 var.padding = 0;
4747
4748 kvm_set_segment(vcpu, &var, seg);
4749 return;
4750 }
4751
4752 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4753 u32 msr_index, u64 *pdata)
4754 {
4755 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4756 }
4757
4758 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4759 u32 msr_index, u64 data)
4760 {
4761 struct msr_data msr;
4762
4763 msr.data = data;
4764 msr.index = msr_index;
4765 msr.host_initiated = false;
4766 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4767 }
4768
4769 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4770 u32 pmc, u64 *pdata)
4771 {
4772 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4773 }
4774
4775 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4776 {
4777 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4778 }
4779
4780 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4781 {
4782 preempt_disable();
4783 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4784 /*
4785 * CR0.TS may reference the host fpu state, not the guest fpu state,
4786 * so it may be clear at this point.
4787 */
4788 clts();
4789 }
4790
4791 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4792 {
4793 preempt_enable();
4794 }
4795
4796 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4797 struct x86_instruction_info *info,
4798 enum x86_intercept_stage stage)
4799 {
4800 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4801 }
4802
4803 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4804 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4805 {
4806 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4807 }
4808
4809 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4810 {
4811 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4812 }
4813
4814 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4815 {
4816 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4817 }
4818
4819 static const struct x86_emulate_ops emulate_ops = {
4820 .read_gpr = emulator_read_gpr,
4821 .write_gpr = emulator_write_gpr,
4822 .read_std = kvm_read_guest_virt_system,
4823 .write_std = kvm_write_guest_virt_system,
4824 .fetch = kvm_fetch_guest_virt,
4825 .read_emulated = emulator_read_emulated,
4826 .write_emulated = emulator_write_emulated,
4827 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4828 .invlpg = emulator_invlpg,
4829 .pio_in_emulated = emulator_pio_in_emulated,
4830 .pio_out_emulated = emulator_pio_out_emulated,
4831 .get_segment = emulator_get_segment,
4832 .set_segment = emulator_set_segment,
4833 .get_cached_segment_base = emulator_get_cached_segment_base,
4834 .get_gdt = emulator_get_gdt,
4835 .get_idt = emulator_get_idt,
4836 .set_gdt = emulator_set_gdt,
4837 .set_idt = emulator_set_idt,
4838 .get_cr = emulator_get_cr,
4839 .set_cr = emulator_set_cr,
4840 .set_rflags = emulator_set_rflags,
4841 .cpl = emulator_get_cpl,
4842 .get_dr = emulator_get_dr,
4843 .set_dr = emulator_set_dr,
4844 .set_msr = emulator_set_msr,
4845 .get_msr = emulator_get_msr,
4846 .read_pmc = emulator_read_pmc,
4847 .halt = emulator_halt,
4848 .wbinvd = emulator_wbinvd,
4849 .fix_hypercall = emulator_fix_hypercall,
4850 .get_fpu = emulator_get_fpu,
4851 .put_fpu = emulator_put_fpu,
4852 .intercept = emulator_intercept,
4853 .get_cpuid = emulator_get_cpuid,
4854 };
4855
4856 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4857 {
4858 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4859 /*
4860 * an sti; sti; sequence only disable interrupts for the first
4861 * instruction. So, if the last instruction, be it emulated or
4862 * not, left the system with the INT_STI flag enabled, it
4863 * means that the last instruction is an sti. We should not
4864 * leave the flag on in this case. The same goes for mov ss
4865 */
4866 if (!(int_shadow & mask))
4867 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4868 }
4869
4870 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4871 {
4872 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4873 if (ctxt->exception.vector == PF_VECTOR)
4874 kvm_propagate_fault(vcpu, &ctxt->exception);
4875 else if (ctxt->exception.error_code_valid)
4876 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4877 ctxt->exception.error_code);
4878 else
4879 kvm_queue_exception(vcpu, ctxt->exception.vector);
4880 }
4881
4882 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4883 {
4884 memset(&ctxt->opcode_len, 0,
4885 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4886
4887 ctxt->fetch.start = 0;
4888 ctxt->fetch.end = 0;
4889 ctxt->io_read.pos = 0;
4890 ctxt->io_read.end = 0;
4891 ctxt->mem_read.pos = 0;
4892 ctxt->mem_read.end = 0;
4893 }
4894
4895 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4896 {
4897 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4898 int cs_db, cs_l;
4899
4900 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4901
4902 ctxt->eflags = kvm_get_rflags(vcpu);
4903 ctxt->eip = kvm_rip_read(vcpu);
4904 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4905 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4906 cs_l ? X86EMUL_MODE_PROT64 :
4907 cs_db ? X86EMUL_MODE_PROT32 :
4908 X86EMUL_MODE_PROT16;
4909 ctxt->guest_mode = is_guest_mode(vcpu);
4910
4911 init_decode_cache(ctxt);
4912 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4913 }
4914
4915 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4916 {
4917 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4918 int ret;
4919
4920 init_emulate_ctxt(vcpu);
4921
4922 ctxt->op_bytes = 2;
4923 ctxt->ad_bytes = 2;
4924 ctxt->_eip = ctxt->eip + inc_eip;
4925 ret = emulate_int_real(ctxt, irq);
4926
4927 if (ret != X86EMUL_CONTINUE)
4928 return EMULATE_FAIL;
4929
4930 ctxt->eip = ctxt->_eip;
4931 kvm_rip_write(vcpu, ctxt->eip);
4932 kvm_set_rflags(vcpu, ctxt->eflags);
4933
4934 if (irq == NMI_VECTOR)
4935 vcpu->arch.nmi_pending = 0;
4936 else
4937 vcpu->arch.interrupt.pending = false;
4938
4939 return EMULATE_DONE;
4940 }
4941 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4942
4943 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4944 {
4945 int r = EMULATE_DONE;
4946
4947 ++vcpu->stat.insn_emulation_fail;
4948 trace_kvm_emulate_insn_failed(vcpu);
4949 if (!is_guest_mode(vcpu)) {
4950 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4951 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4952 vcpu->run->internal.ndata = 0;
4953 r = EMULATE_FAIL;
4954 }
4955 kvm_queue_exception(vcpu, UD_VECTOR);
4956
4957 return r;
4958 }
4959
4960 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4961 bool write_fault_to_shadow_pgtable,
4962 int emulation_type)
4963 {
4964 gpa_t gpa = cr2;
4965 pfn_t pfn;
4966
4967 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4968 return false;
4969
4970 if (!vcpu->arch.mmu.direct_map) {
4971 /*
4972 * Write permission should be allowed since only
4973 * write access need to be emulated.
4974 */
4975 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4976
4977 /*
4978 * If the mapping is invalid in guest, let cpu retry
4979 * it to generate fault.
4980 */
4981 if (gpa == UNMAPPED_GVA)
4982 return true;
4983 }
4984
4985 /*
4986 * Do not retry the unhandleable instruction if it faults on the
4987 * readonly host memory, otherwise it will goto a infinite loop:
4988 * retry instruction -> write #PF -> emulation fail -> retry
4989 * instruction -> ...
4990 */
4991 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4992
4993 /*
4994 * If the instruction failed on the error pfn, it can not be fixed,
4995 * report the error to userspace.
4996 */
4997 if (is_error_noslot_pfn(pfn))
4998 return false;
4999
5000 kvm_release_pfn_clean(pfn);
5001
5002 /* The instructions are well-emulated on direct mmu. */
5003 if (vcpu->arch.mmu.direct_map) {
5004 unsigned int indirect_shadow_pages;
5005
5006 spin_lock(&vcpu->kvm->mmu_lock);
5007 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5008 spin_unlock(&vcpu->kvm->mmu_lock);
5009
5010 if (indirect_shadow_pages)
5011 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5012
5013 return true;
5014 }
5015
5016 /*
5017 * if emulation was due to access to shadowed page table
5018 * and it failed try to unshadow page and re-enter the
5019 * guest to let CPU execute the instruction.
5020 */
5021 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5022
5023 /*
5024 * If the access faults on its page table, it can not
5025 * be fixed by unprotecting shadow page and it should
5026 * be reported to userspace.
5027 */
5028 return !write_fault_to_shadow_pgtable;
5029 }
5030
5031 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5032 unsigned long cr2, int emulation_type)
5033 {
5034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5035 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5036
5037 last_retry_eip = vcpu->arch.last_retry_eip;
5038 last_retry_addr = vcpu->arch.last_retry_addr;
5039
5040 /*
5041 * If the emulation is caused by #PF and it is non-page_table
5042 * writing instruction, it means the VM-EXIT is caused by shadow
5043 * page protected, we can zap the shadow page and retry this
5044 * instruction directly.
5045 *
5046 * Note: if the guest uses a non-page-table modifying instruction
5047 * on the PDE that points to the instruction, then we will unmap
5048 * the instruction and go to an infinite loop. So, we cache the
5049 * last retried eip and the last fault address, if we meet the eip
5050 * and the address again, we can break out of the potential infinite
5051 * loop.
5052 */
5053 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5054
5055 if (!(emulation_type & EMULTYPE_RETRY))
5056 return false;
5057
5058 if (x86_page_table_writing_insn(ctxt))
5059 return false;
5060
5061 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5062 return false;
5063
5064 vcpu->arch.last_retry_eip = ctxt->eip;
5065 vcpu->arch.last_retry_addr = cr2;
5066
5067 if (!vcpu->arch.mmu.direct_map)
5068 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5069
5070 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5071
5072 return true;
5073 }
5074
5075 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5076 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5077
5078 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5079 unsigned long *db)
5080 {
5081 u32 dr6 = 0;
5082 int i;
5083 u32 enable, rwlen;
5084
5085 enable = dr7;
5086 rwlen = dr7 >> 16;
5087 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5088 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5089 dr6 |= (1 << i);
5090 return dr6;
5091 }
5092
5093 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5094 {
5095 struct kvm_run *kvm_run = vcpu->run;
5096
5097 /*
5098 * Use the "raw" value to see if TF was passed to the processor.
5099 * Note that the new value of the flags has not been saved yet.
5100 *
5101 * This is correct even for TF set by the guest, because "the
5102 * processor will not generate this exception after the instruction
5103 * that sets the TF flag".
5104 */
5105 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5106
5107 if (unlikely(rflags & X86_EFLAGS_TF)) {
5108 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5109 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5110 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5111 kvm_run->debug.arch.exception = DB_VECTOR;
5112 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5113 *r = EMULATE_USER_EXIT;
5114 } else {
5115 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5116 /*
5117 * "Certain debug exceptions may clear bit 0-3. The
5118 * remaining contents of the DR6 register are never
5119 * cleared by the processor".
5120 */
5121 vcpu->arch.dr6 &= ~15;
5122 vcpu->arch.dr6 |= DR6_BS;
5123 kvm_queue_exception(vcpu, DB_VECTOR);
5124 }
5125 }
5126 }
5127
5128 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5129 {
5130 struct kvm_run *kvm_run = vcpu->run;
5131 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5132 u32 dr6 = 0;
5133
5134 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5135 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5136 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5137 vcpu->arch.guest_debug_dr7,
5138 vcpu->arch.eff_db);
5139
5140 if (dr6 != 0) {
5141 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5142 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5143 get_segment_base(vcpu, VCPU_SREG_CS);
5144
5145 kvm_run->debug.arch.exception = DB_VECTOR;
5146 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5147 *r = EMULATE_USER_EXIT;
5148 return true;
5149 }
5150 }
5151
5152 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5153 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5154 vcpu->arch.dr7,
5155 vcpu->arch.db);
5156
5157 if (dr6 != 0) {
5158 vcpu->arch.dr6 &= ~15;
5159 vcpu->arch.dr6 |= dr6;
5160 kvm_queue_exception(vcpu, DB_VECTOR);
5161 *r = EMULATE_DONE;
5162 return true;
5163 }
5164 }
5165
5166 return false;
5167 }
5168
5169 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5170 unsigned long cr2,
5171 int emulation_type,
5172 void *insn,
5173 int insn_len)
5174 {
5175 int r;
5176 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5177 bool writeback = true;
5178 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5179
5180 /*
5181 * Clear write_fault_to_shadow_pgtable here to ensure it is
5182 * never reused.
5183 */
5184 vcpu->arch.write_fault_to_shadow_pgtable = false;
5185 kvm_clear_exception_queue(vcpu);
5186
5187 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5188 init_emulate_ctxt(vcpu);
5189
5190 /*
5191 * We will reenter on the same instruction since
5192 * we do not set complete_userspace_io. This does not
5193 * handle watchpoints yet, those would be handled in
5194 * the emulate_ops.
5195 */
5196 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5197 return r;
5198
5199 ctxt->interruptibility = 0;
5200 ctxt->have_exception = false;
5201 ctxt->perm_ok = false;
5202
5203 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5204
5205 r = x86_decode_insn(ctxt, insn, insn_len);
5206
5207 trace_kvm_emulate_insn_start(vcpu);
5208 ++vcpu->stat.insn_emulation;
5209 if (r != EMULATION_OK) {
5210 if (emulation_type & EMULTYPE_TRAP_UD)
5211 return EMULATE_FAIL;
5212 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5213 emulation_type))
5214 return EMULATE_DONE;
5215 if (emulation_type & EMULTYPE_SKIP)
5216 return EMULATE_FAIL;
5217 return handle_emulation_failure(vcpu);
5218 }
5219 }
5220
5221 if (emulation_type & EMULTYPE_SKIP) {
5222 kvm_rip_write(vcpu, ctxt->_eip);
5223 return EMULATE_DONE;
5224 }
5225
5226 if (retry_instruction(ctxt, cr2, emulation_type))
5227 return EMULATE_DONE;
5228
5229 /* this is needed for vmware backdoor interface to work since it
5230 changes registers values during IO operation */
5231 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5232 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5233 emulator_invalidate_register_cache(ctxt);
5234 }
5235
5236 restart:
5237 r = x86_emulate_insn(ctxt);
5238
5239 if (r == EMULATION_INTERCEPTED)
5240 return EMULATE_DONE;
5241
5242 if (r == EMULATION_FAILED) {
5243 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5244 emulation_type))
5245 return EMULATE_DONE;
5246
5247 return handle_emulation_failure(vcpu);
5248 }
5249
5250 if (ctxt->have_exception) {
5251 inject_emulated_exception(vcpu);
5252 r = EMULATE_DONE;
5253 } else if (vcpu->arch.pio.count) {
5254 if (!vcpu->arch.pio.in) {
5255 /* FIXME: return into emulator if single-stepping. */
5256 vcpu->arch.pio.count = 0;
5257 } else {
5258 writeback = false;
5259 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5260 }
5261 r = EMULATE_USER_EXIT;
5262 } else if (vcpu->mmio_needed) {
5263 if (!vcpu->mmio_is_write)
5264 writeback = false;
5265 r = EMULATE_USER_EXIT;
5266 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5267 } else if (r == EMULATION_RESTART)
5268 goto restart;
5269 else
5270 r = EMULATE_DONE;
5271
5272 if (writeback) {
5273 toggle_interruptibility(vcpu, ctxt->interruptibility);
5274 kvm_make_request(KVM_REQ_EVENT, vcpu);
5275 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5276 kvm_rip_write(vcpu, ctxt->eip);
5277 if (r == EMULATE_DONE)
5278 kvm_vcpu_check_singlestep(vcpu, &r);
5279 kvm_set_rflags(vcpu, ctxt->eflags);
5280 } else
5281 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5282
5283 return r;
5284 }
5285 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5286
5287 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5288 {
5289 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5290 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5291 size, port, &val, 1);
5292 /* do not return to emulator after return from userspace */
5293 vcpu->arch.pio.count = 0;
5294 return ret;
5295 }
5296 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5297
5298 static void tsc_bad(void *info)
5299 {
5300 __this_cpu_write(cpu_tsc_khz, 0);
5301 }
5302
5303 static void tsc_khz_changed(void *data)
5304 {
5305 struct cpufreq_freqs *freq = data;
5306 unsigned long khz = 0;
5307
5308 if (data)
5309 khz = freq->new;
5310 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5311 khz = cpufreq_quick_get(raw_smp_processor_id());
5312 if (!khz)
5313 khz = tsc_khz;
5314 __this_cpu_write(cpu_tsc_khz, khz);
5315 }
5316
5317 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5318 void *data)
5319 {
5320 struct cpufreq_freqs *freq = data;
5321 struct kvm *kvm;
5322 struct kvm_vcpu *vcpu;
5323 int i, send_ipi = 0;
5324
5325 /*
5326 * We allow guests to temporarily run on slowing clocks,
5327 * provided we notify them after, or to run on accelerating
5328 * clocks, provided we notify them before. Thus time never
5329 * goes backwards.
5330 *
5331 * However, we have a problem. We can't atomically update
5332 * the frequency of a given CPU from this function; it is
5333 * merely a notifier, which can be called from any CPU.
5334 * Changing the TSC frequency at arbitrary points in time
5335 * requires a recomputation of local variables related to
5336 * the TSC for each VCPU. We must flag these local variables
5337 * to be updated and be sure the update takes place with the
5338 * new frequency before any guests proceed.
5339 *
5340 * Unfortunately, the combination of hotplug CPU and frequency
5341 * change creates an intractable locking scenario; the order
5342 * of when these callouts happen is undefined with respect to
5343 * CPU hotplug, and they can race with each other. As such,
5344 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5345 * undefined; you can actually have a CPU frequency change take
5346 * place in between the computation of X and the setting of the
5347 * variable. To protect against this problem, all updates of
5348 * the per_cpu tsc_khz variable are done in an interrupt
5349 * protected IPI, and all callers wishing to update the value
5350 * must wait for a synchronous IPI to complete (which is trivial
5351 * if the caller is on the CPU already). This establishes the
5352 * necessary total order on variable updates.
5353 *
5354 * Note that because a guest time update may take place
5355 * anytime after the setting of the VCPU's request bit, the
5356 * correct TSC value must be set before the request. However,
5357 * to ensure the update actually makes it to any guest which
5358 * starts running in hardware virtualization between the set
5359 * and the acquisition of the spinlock, we must also ping the
5360 * CPU after setting the request bit.
5361 *
5362 */
5363
5364 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5365 return 0;
5366 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5367 return 0;
5368
5369 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5370
5371 spin_lock(&kvm_lock);
5372 list_for_each_entry(kvm, &vm_list, vm_list) {
5373 kvm_for_each_vcpu(i, vcpu, kvm) {
5374 if (vcpu->cpu != freq->cpu)
5375 continue;
5376 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5377 if (vcpu->cpu != smp_processor_id())
5378 send_ipi = 1;
5379 }
5380 }
5381 spin_unlock(&kvm_lock);
5382
5383 if (freq->old < freq->new && send_ipi) {
5384 /*
5385 * We upscale the frequency. Must make the guest
5386 * doesn't see old kvmclock values while running with
5387 * the new frequency, otherwise we risk the guest sees
5388 * time go backwards.
5389 *
5390 * In case we update the frequency for another cpu
5391 * (which might be in guest context) send an interrupt
5392 * to kick the cpu out of guest context. Next time
5393 * guest context is entered kvmclock will be updated,
5394 * so the guest will not see stale values.
5395 */
5396 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5397 }
5398 return 0;
5399 }
5400
5401 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5402 .notifier_call = kvmclock_cpufreq_notifier
5403 };
5404
5405 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5406 unsigned long action, void *hcpu)
5407 {
5408 unsigned int cpu = (unsigned long)hcpu;
5409
5410 switch (action) {
5411 case CPU_ONLINE:
5412 case CPU_DOWN_FAILED:
5413 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5414 break;
5415 case CPU_DOWN_PREPARE:
5416 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5417 break;
5418 }
5419 return NOTIFY_OK;
5420 }
5421
5422 static struct notifier_block kvmclock_cpu_notifier_block = {
5423 .notifier_call = kvmclock_cpu_notifier,
5424 .priority = -INT_MAX
5425 };
5426
5427 static void kvm_timer_init(void)
5428 {
5429 int cpu;
5430
5431 max_tsc_khz = tsc_khz;
5432 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5433 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5434 #ifdef CONFIG_CPU_FREQ
5435 struct cpufreq_policy policy;
5436 memset(&policy, 0, sizeof(policy));
5437 cpu = get_cpu();
5438 cpufreq_get_policy(&policy, cpu);
5439 if (policy.cpuinfo.max_freq)
5440 max_tsc_khz = policy.cpuinfo.max_freq;
5441 put_cpu();
5442 #endif
5443 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5444 CPUFREQ_TRANSITION_NOTIFIER);
5445 }
5446 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5447 for_each_online_cpu(cpu)
5448 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5449 }
5450
5451 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5452
5453 int kvm_is_in_guest(void)
5454 {
5455 return __this_cpu_read(current_vcpu) != NULL;
5456 }
5457
5458 static int kvm_is_user_mode(void)
5459 {
5460 int user_mode = 3;
5461
5462 if (__this_cpu_read(current_vcpu))
5463 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5464
5465 return user_mode != 0;
5466 }
5467
5468 static unsigned long kvm_get_guest_ip(void)
5469 {
5470 unsigned long ip = 0;
5471
5472 if (__this_cpu_read(current_vcpu))
5473 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5474
5475 return ip;
5476 }
5477
5478 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5479 .is_in_guest = kvm_is_in_guest,
5480 .is_user_mode = kvm_is_user_mode,
5481 .get_guest_ip = kvm_get_guest_ip,
5482 };
5483
5484 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5485 {
5486 __this_cpu_write(current_vcpu, vcpu);
5487 }
5488 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5489
5490 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5491 {
5492 __this_cpu_write(current_vcpu, NULL);
5493 }
5494 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5495
5496 static void kvm_set_mmio_spte_mask(void)
5497 {
5498 u64 mask;
5499 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5500
5501 /*
5502 * Set the reserved bits and the present bit of an paging-structure
5503 * entry to generate page fault with PFER.RSV = 1.
5504 */
5505 /* Mask the reserved physical address bits. */
5506 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5507
5508 /* Bit 62 is always reserved for 32bit host. */
5509 mask |= 0x3ull << 62;
5510
5511 /* Set the present bit. */
5512 mask |= 1ull;
5513
5514 #ifdef CONFIG_X86_64
5515 /*
5516 * If reserved bit is not supported, clear the present bit to disable
5517 * mmio page fault.
5518 */
5519 if (maxphyaddr == 52)
5520 mask &= ~1ull;
5521 #endif
5522
5523 kvm_mmu_set_mmio_spte_mask(mask);
5524 }
5525
5526 #ifdef CONFIG_X86_64
5527 static void pvclock_gtod_update_fn(struct work_struct *work)
5528 {
5529 struct kvm *kvm;
5530
5531 struct kvm_vcpu *vcpu;
5532 int i;
5533
5534 spin_lock(&kvm_lock);
5535 list_for_each_entry(kvm, &vm_list, vm_list)
5536 kvm_for_each_vcpu(i, vcpu, kvm)
5537 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5538 atomic_set(&kvm_guest_has_master_clock, 0);
5539 spin_unlock(&kvm_lock);
5540 }
5541
5542 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5543
5544 /*
5545 * Notification about pvclock gtod data update.
5546 */
5547 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5548 void *priv)
5549 {
5550 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5551 struct timekeeper *tk = priv;
5552
5553 update_pvclock_gtod(tk);
5554
5555 /* disable master clock if host does not trust, or does not
5556 * use, TSC clocksource
5557 */
5558 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5559 atomic_read(&kvm_guest_has_master_clock) != 0)
5560 queue_work(system_long_wq, &pvclock_gtod_work);
5561
5562 return 0;
5563 }
5564
5565 static struct notifier_block pvclock_gtod_notifier = {
5566 .notifier_call = pvclock_gtod_notify,
5567 };
5568 #endif
5569
5570 int kvm_arch_init(void *opaque)
5571 {
5572 int r;
5573 struct kvm_x86_ops *ops = opaque;
5574
5575 if (kvm_x86_ops) {
5576 printk(KERN_ERR "kvm: already loaded the other module\n");
5577 r = -EEXIST;
5578 goto out;
5579 }
5580
5581 if (!ops->cpu_has_kvm_support()) {
5582 printk(KERN_ERR "kvm: no hardware support\n");
5583 r = -EOPNOTSUPP;
5584 goto out;
5585 }
5586 if (ops->disabled_by_bios()) {
5587 printk(KERN_ERR "kvm: disabled by bios\n");
5588 r = -EOPNOTSUPP;
5589 goto out;
5590 }
5591
5592 r = -ENOMEM;
5593 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5594 if (!shared_msrs) {
5595 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5596 goto out;
5597 }
5598
5599 r = kvm_mmu_module_init();
5600 if (r)
5601 goto out_free_percpu;
5602
5603 kvm_set_mmio_spte_mask();
5604
5605 kvm_x86_ops = ops;
5606 kvm_init_msr_list();
5607
5608 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5609 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5610
5611 kvm_timer_init();
5612
5613 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5614
5615 if (cpu_has_xsave)
5616 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5617
5618 kvm_lapic_init();
5619 #ifdef CONFIG_X86_64
5620 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5621 #endif
5622
5623 return 0;
5624
5625 out_free_percpu:
5626 free_percpu(shared_msrs);
5627 out:
5628 return r;
5629 }
5630
5631 void kvm_arch_exit(void)
5632 {
5633 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5634
5635 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5636 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5637 CPUFREQ_TRANSITION_NOTIFIER);
5638 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5639 #ifdef CONFIG_X86_64
5640 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5641 #endif
5642 kvm_x86_ops = NULL;
5643 kvm_mmu_module_exit();
5644 free_percpu(shared_msrs);
5645 }
5646
5647 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5648 {
5649 ++vcpu->stat.halt_exits;
5650 if (irqchip_in_kernel(vcpu->kvm)) {
5651 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5652 return 1;
5653 } else {
5654 vcpu->run->exit_reason = KVM_EXIT_HLT;
5655 return 0;
5656 }
5657 }
5658 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5659
5660 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5661 {
5662 u64 param, ingpa, outgpa, ret;
5663 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5664 bool fast, longmode;
5665 int cs_db, cs_l;
5666
5667 /*
5668 * hypercall generates UD from non zero cpl and real mode
5669 * per HYPER-V spec
5670 */
5671 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5672 kvm_queue_exception(vcpu, UD_VECTOR);
5673 return 0;
5674 }
5675
5676 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5677 longmode = is_long_mode(vcpu) && cs_l == 1;
5678
5679 if (!longmode) {
5680 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5681 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5682 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5683 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5684 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5685 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5686 }
5687 #ifdef CONFIG_X86_64
5688 else {
5689 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5690 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5691 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5692 }
5693 #endif
5694
5695 code = param & 0xffff;
5696 fast = (param >> 16) & 0x1;
5697 rep_cnt = (param >> 32) & 0xfff;
5698 rep_idx = (param >> 48) & 0xfff;
5699
5700 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5701
5702 switch (code) {
5703 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5704 kvm_vcpu_on_spin(vcpu);
5705 break;
5706 default:
5707 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5708 break;
5709 }
5710
5711 ret = res | (((u64)rep_done & 0xfff) << 32);
5712 if (longmode) {
5713 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5714 } else {
5715 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5716 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5717 }
5718
5719 return 1;
5720 }
5721
5722 /*
5723 * kvm_pv_kick_cpu_op: Kick a vcpu.
5724 *
5725 * @apicid - apicid of vcpu to be kicked.
5726 */
5727 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5728 {
5729 struct kvm_lapic_irq lapic_irq;
5730
5731 lapic_irq.shorthand = 0;
5732 lapic_irq.dest_mode = 0;
5733 lapic_irq.dest_id = apicid;
5734
5735 lapic_irq.delivery_mode = APIC_DM_REMRD;
5736 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5737 }
5738
5739 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5740 {
5741 unsigned long nr, a0, a1, a2, a3, ret;
5742 int r = 1;
5743
5744 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5745 return kvm_hv_hypercall(vcpu);
5746
5747 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5748 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5749 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5750 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5751 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5752
5753 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5754
5755 if (!is_long_mode(vcpu)) {
5756 nr &= 0xFFFFFFFF;
5757 a0 &= 0xFFFFFFFF;
5758 a1 &= 0xFFFFFFFF;
5759 a2 &= 0xFFFFFFFF;
5760 a3 &= 0xFFFFFFFF;
5761 }
5762
5763 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5764 ret = -KVM_EPERM;
5765 goto out;
5766 }
5767
5768 switch (nr) {
5769 case KVM_HC_VAPIC_POLL_IRQ:
5770 ret = 0;
5771 break;
5772 case KVM_HC_KICK_CPU:
5773 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5774 ret = 0;
5775 break;
5776 default:
5777 ret = -KVM_ENOSYS;
5778 break;
5779 }
5780 out:
5781 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5782 ++vcpu->stat.hypercalls;
5783 return r;
5784 }
5785 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5786
5787 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5788 {
5789 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5790 char instruction[3];
5791 unsigned long rip = kvm_rip_read(vcpu);
5792
5793 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5794
5795 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5796 }
5797
5798 /*
5799 * Check if userspace requested an interrupt window, and that the
5800 * interrupt window is open.
5801 *
5802 * No need to exit to userspace if we already have an interrupt queued.
5803 */
5804 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5805 {
5806 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5807 vcpu->run->request_interrupt_window &&
5808 kvm_arch_interrupt_allowed(vcpu));
5809 }
5810
5811 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5812 {
5813 struct kvm_run *kvm_run = vcpu->run;
5814
5815 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5816 kvm_run->cr8 = kvm_get_cr8(vcpu);
5817 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5818 if (irqchip_in_kernel(vcpu->kvm))
5819 kvm_run->ready_for_interrupt_injection = 1;
5820 else
5821 kvm_run->ready_for_interrupt_injection =
5822 kvm_arch_interrupt_allowed(vcpu) &&
5823 !kvm_cpu_has_interrupt(vcpu) &&
5824 !kvm_event_needs_reinjection(vcpu);
5825 }
5826
5827 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5828 {
5829 int max_irr, tpr;
5830
5831 if (!kvm_x86_ops->update_cr8_intercept)
5832 return;
5833
5834 if (!vcpu->arch.apic)
5835 return;
5836
5837 if (!vcpu->arch.apic->vapic_addr)
5838 max_irr = kvm_lapic_find_highest_irr(vcpu);
5839 else
5840 max_irr = -1;
5841
5842 if (max_irr != -1)
5843 max_irr >>= 4;
5844
5845 tpr = kvm_lapic_get_cr8(vcpu);
5846
5847 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5848 }
5849
5850 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5851 {
5852 int r;
5853
5854 /* try to reinject previous events if any */
5855 if (vcpu->arch.exception.pending) {
5856 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5857 vcpu->arch.exception.has_error_code,
5858 vcpu->arch.exception.error_code);
5859 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5860 vcpu->arch.exception.has_error_code,
5861 vcpu->arch.exception.error_code,
5862 vcpu->arch.exception.reinject);
5863 return 0;
5864 }
5865
5866 if (vcpu->arch.nmi_injected) {
5867 kvm_x86_ops->set_nmi(vcpu);
5868 return 0;
5869 }
5870
5871 if (vcpu->arch.interrupt.pending) {
5872 kvm_x86_ops->set_irq(vcpu);
5873 return 0;
5874 }
5875
5876 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5877 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5878 if (r != 0)
5879 return r;
5880 }
5881
5882 /* try to inject new event if pending */
5883 if (vcpu->arch.nmi_pending) {
5884 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5885 --vcpu->arch.nmi_pending;
5886 vcpu->arch.nmi_injected = true;
5887 kvm_x86_ops->set_nmi(vcpu);
5888 }
5889 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5890 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5891 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5892 false);
5893 kvm_x86_ops->set_irq(vcpu);
5894 }
5895 }
5896 return 0;
5897 }
5898
5899 static void process_nmi(struct kvm_vcpu *vcpu)
5900 {
5901 unsigned limit = 2;
5902
5903 /*
5904 * x86 is limited to one NMI running, and one NMI pending after it.
5905 * If an NMI is already in progress, limit further NMIs to just one.
5906 * Otherwise, allow two (and we'll inject the first one immediately).
5907 */
5908 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5909 limit = 1;
5910
5911 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5912 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5913 kvm_make_request(KVM_REQ_EVENT, vcpu);
5914 }
5915
5916 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5917 {
5918 u64 eoi_exit_bitmap[4];
5919 u32 tmr[8];
5920
5921 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5922 return;
5923
5924 memset(eoi_exit_bitmap, 0, 32);
5925 memset(tmr, 0, 32);
5926
5927 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5928 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5929 kvm_apic_update_tmr(vcpu, tmr);
5930 }
5931
5932 /*
5933 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5934 * exiting to the userspace. Otherwise, the value will be returned to the
5935 * userspace.
5936 */
5937 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5938 {
5939 int r;
5940 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5941 vcpu->run->request_interrupt_window;
5942 bool req_immediate_exit = false;
5943
5944 if (vcpu->requests) {
5945 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5946 kvm_mmu_unload(vcpu);
5947 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5948 __kvm_migrate_timers(vcpu);
5949 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5950 kvm_gen_update_masterclock(vcpu->kvm);
5951 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5952 kvm_gen_kvmclock_update(vcpu);
5953 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5954 r = kvm_guest_time_update(vcpu);
5955 if (unlikely(r))
5956 goto out;
5957 }
5958 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5959 kvm_mmu_sync_roots(vcpu);
5960 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5961 kvm_x86_ops->tlb_flush(vcpu);
5962 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5963 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5964 r = 0;
5965 goto out;
5966 }
5967 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5968 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5969 r = 0;
5970 goto out;
5971 }
5972 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5973 vcpu->fpu_active = 0;
5974 kvm_x86_ops->fpu_deactivate(vcpu);
5975 }
5976 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5977 /* Page is swapped out. Do synthetic halt */
5978 vcpu->arch.apf.halted = true;
5979 r = 1;
5980 goto out;
5981 }
5982 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5983 record_steal_time(vcpu);
5984 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5985 process_nmi(vcpu);
5986 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5987 kvm_handle_pmu_event(vcpu);
5988 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5989 kvm_deliver_pmi(vcpu);
5990 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5991 vcpu_scan_ioapic(vcpu);
5992 }
5993
5994 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5995 kvm_apic_accept_events(vcpu);
5996 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5997 r = 1;
5998 goto out;
5999 }
6000
6001 if (inject_pending_event(vcpu, req_int_win) != 0)
6002 req_immediate_exit = true;
6003 /* enable NMI/IRQ window open exits if needed */
6004 else if (vcpu->arch.nmi_pending)
6005 kvm_x86_ops->enable_nmi_window(vcpu);
6006 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6007 kvm_x86_ops->enable_irq_window(vcpu);
6008
6009 if (kvm_lapic_enabled(vcpu)) {
6010 /*
6011 * Update architecture specific hints for APIC
6012 * virtual interrupt delivery.
6013 */
6014 if (kvm_x86_ops->hwapic_irr_update)
6015 kvm_x86_ops->hwapic_irr_update(vcpu,
6016 kvm_lapic_find_highest_irr(vcpu));
6017 update_cr8_intercept(vcpu);
6018 kvm_lapic_sync_to_vapic(vcpu);
6019 }
6020 }
6021
6022 r = kvm_mmu_reload(vcpu);
6023 if (unlikely(r)) {
6024 goto cancel_injection;
6025 }
6026
6027 preempt_disable();
6028
6029 kvm_x86_ops->prepare_guest_switch(vcpu);
6030 if (vcpu->fpu_active)
6031 kvm_load_guest_fpu(vcpu);
6032 kvm_load_guest_xcr0(vcpu);
6033
6034 vcpu->mode = IN_GUEST_MODE;
6035
6036 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6037
6038 /* We should set ->mode before check ->requests,
6039 * see the comment in make_all_cpus_request.
6040 */
6041 smp_mb__after_srcu_read_unlock();
6042
6043 local_irq_disable();
6044
6045 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6046 || need_resched() || signal_pending(current)) {
6047 vcpu->mode = OUTSIDE_GUEST_MODE;
6048 smp_wmb();
6049 local_irq_enable();
6050 preempt_enable();
6051 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6052 r = 1;
6053 goto cancel_injection;
6054 }
6055
6056 if (req_immediate_exit)
6057 smp_send_reschedule(vcpu->cpu);
6058
6059 kvm_guest_enter();
6060
6061 if (unlikely(vcpu->arch.switch_db_regs)) {
6062 set_debugreg(0, 7);
6063 set_debugreg(vcpu->arch.eff_db[0], 0);
6064 set_debugreg(vcpu->arch.eff_db[1], 1);
6065 set_debugreg(vcpu->arch.eff_db[2], 2);
6066 set_debugreg(vcpu->arch.eff_db[3], 3);
6067 set_debugreg(vcpu->arch.dr6, 6);
6068 }
6069
6070 trace_kvm_entry(vcpu->vcpu_id);
6071 kvm_x86_ops->run(vcpu);
6072
6073 /*
6074 * Do this here before restoring debug registers on the host. And
6075 * since we do this before handling the vmexit, a DR access vmexit
6076 * can (a) read the correct value of the debug registers, (b) set
6077 * KVM_DEBUGREG_WONT_EXIT again.
6078 */
6079 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6080 int i;
6081
6082 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6083 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6084 for (i = 0; i < KVM_NR_DB_REGS; i++)
6085 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6086 }
6087
6088 /*
6089 * If the guest has used debug registers, at least dr7
6090 * will be disabled while returning to the host.
6091 * If we don't have active breakpoints in the host, we don't
6092 * care about the messed up debug address registers. But if
6093 * we have some of them active, restore the old state.
6094 */
6095 if (hw_breakpoint_active())
6096 hw_breakpoint_restore();
6097
6098 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6099 native_read_tsc());
6100
6101 vcpu->mode = OUTSIDE_GUEST_MODE;
6102 smp_wmb();
6103
6104 /* Interrupt is enabled by handle_external_intr() */
6105 kvm_x86_ops->handle_external_intr(vcpu);
6106
6107 ++vcpu->stat.exits;
6108
6109 /*
6110 * We must have an instruction between local_irq_enable() and
6111 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6112 * the interrupt shadow. The stat.exits increment will do nicely.
6113 * But we need to prevent reordering, hence this barrier():
6114 */
6115 barrier();
6116
6117 kvm_guest_exit();
6118
6119 preempt_enable();
6120
6121 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6122
6123 /*
6124 * Profile KVM exit RIPs:
6125 */
6126 if (unlikely(prof_on == KVM_PROFILING)) {
6127 unsigned long rip = kvm_rip_read(vcpu);
6128 profile_hit(KVM_PROFILING, (void *)rip);
6129 }
6130
6131 if (unlikely(vcpu->arch.tsc_always_catchup))
6132 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6133
6134 if (vcpu->arch.apic_attention)
6135 kvm_lapic_sync_from_vapic(vcpu);
6136
6137 r = kvm_x86_ops->handle_exit(vcpu);
6138 return r;
6139
6140 cancel_injection:
6141 kvm_x86_ops->cancel_injection(vcpu);
6142 if (unlikely(vcpu->arch.apic_attention))
6143 kvm_lapic_sync_from_vapic(vcpu);
6144 out:
6145 return r;
6146 }
6147
6148
6149 static int __vcpu_run(struct kvm_vcpu *vcpu)
6150 {
6151 int r;
6152 struct kvm *kvm = vcpu->kvm;
6153
6154 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6155
6156 r = 1;
6157 while (r > 0) {
6158 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6159 !vcpu->arch.apf.halted)
6160 r = vcpu_enter_guest(vcpu);
6161 else {
6162 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6163 kvm_vcpu_block(vcpu);
6164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6165 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6166 kvm_apic_accept_events(vcpu);
6167 switch(vcpu->arch.mp_state) {
6168 case KVM_MP_STATE_HALTED:
6169 vcpu->arch.pv.pv_unhalted = false;
6170 vcpu->arch.mp_state =
6171 KVM_MP_STATE_RUNNABLE;
6172 case KVM_MP_STATE_RUNNABLE:
6173 vcpu->arch.apf.halted = false;
6174 break;
6175 case KVM_MP_STATE_INIT_RECEIVED:
6176 break;
6177 default:
6178 r = -EINTR;
6179 break;
6180 }
6181 }
6182 }
6183
6184 if (r <= 0)
6185 break;
6186
6187 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6188 if (kvm_cpu_has_pending_timer(vcpu))
6189 kvm_inject_pending_timer_irqs(vcpu);
6190
6191 if (dm_request_for_irq_injection(vcpu)) {
6192 r = -EINTR;
6193 vcpu->run->exit_reason = KVM_EXIT_INTR;
6194 ++vcpu->stat.request_irq_exits;
6195 }
6196
6197 kvm_check_async_pf_completion(vcpu);
6198
6199 if (signal_pending(current)) {
6200 r = -EINTR;
6201 vcpu->run->exit_reason = KVM_EXIT_INTR;
6202 ++vcpu->stat.signal_exits;
6203 }
6204 if (need_resched()) {
6205 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6206 cond_resched();
6207 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6208 }
6209 }
6210
6211 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6212
6213 return r;
6214 }
6215
6216 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6217 {
6218 int r;
6219 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6220 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6221 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6222 if (r != EMULATE_DONE)
6223 return 0;
6224 return 1;
6225 }
6226
6227 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6228 {
6229 BUG_ON(!vcpu->arch.pio.count);
6230
6231 return complete_emulated_io(vcpu);
6232 }
6233
6234 /*
6235 * Implements the following, as a state machine:
6236 *
6237 * read:
6238 * for each fragment
6239 * for each mmio piece in the fragment
6240 * write gpa, len
6241 * exit
6242 * copy data
6243 * execute insn
6244 *
6245 * write:
6246 * for each fragment
6247 * for each mmio piece in the fragment
6248 * write gpa, len
6249 * copy data
6250 * exit
6251 */
6252 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6253 {
6254 struct kvm_run *run = vcpu->run;
6255 struct kvm_mmio_fragment *frag;
6256 unsigned len;
6257
6258 BUG_ON(!vcpu->mmio_needed);
6259
6260 /* Complete previous fragment */
6261 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6262 len = min(8u, frag->len);
6263 if (!vcpu->mmio_is_write)
6264 memcpy(frag->data, run->mmio.data, len);
6265
6266 if (frag->len <= 8) {
6267 /* Switch to the next fragment. */
6268 frag++;
6269 vcpu->mmio_cur_fragment++;
6270 } else {
6271 /* Go forward to the next mmio piece. */
6272 frag->data += len;
6273 frag->gpa += len;
6274 frag->len -= len;
6275 }
6276
6277 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6278 vcpu->mmio_needed = 0;
6279
6280 /* FIXME: return into emulator if single-stepping. */
6281 if (vcpu->mmio_is_write)
6282 return 1;
6283 vcpu->mmio_read_completed = 1;
6284 return complete_emulated_io(vcpu);
6285 }
6286
6287 run->exit_reason = KVM_EXIT_MMIO;
6288 run->mmio.phys_addr = frag->gpa;
6289 if (vcpu->mmio_is_write)
6290 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6291 run->mmio.len = min(8u, frag->len);
6292 run->mmio.is_write = vcpu->mmio_is_write;
6293 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6294 return 0;
6295 }
6296
6297
6298 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6299 {
6300 int r;
6301 sigset_t sigsaved;
6302
6303 if (!tsk_used_math(current) && init_fpu(current))
6304 return -ENOMEM;
6305
6306 if (vcpu->sigset_active)
6307 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6308
6309 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6310 kvm_vcpu_block(vcpu);
6311 kvm_apic_accept_events(vcpu);
6312 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6313 r = -EAGAIN;
6314 goto out;
6315 }
6316
6317 /* re-sync apic's tpr */
6318 if (!irqchip_in_kernel(vcpu->kvm)) {
6319 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6320 r = -EINVAL;
6321 goto out;
6322 }
6323 }
6324
6325 if (unlikely(vcpu->arch.complete_userspace_io)) {
6326 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6327 vcpu->arch.complete_userspace_io = NULL;
6328 r = cui(vcpu);
6329 if (r <= 0)
6330 goto out;
6331 } else
6332 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6333
6334 r = __vcpu_run(vcpu);
6335
6336 out:
6337 post_kvm_run_save(vcpu);
6338 if (vcpu->sigset_active)
6339 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6340
6341 return r;
6342 }
6343
6344 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6345 {
6346 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6347 /*
6348 * We are here if userspace calls get_regs() in the middle of
6349 * instruction emulation. Registers state needs to be copied
6350 * back from emulation context to vcpu. Userspace shouldn't do
6351 * that usually, but some bad designed PV devices (vmware
6352 * backdoor interface) need this to work
6353 */
6354 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6355 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6356 }
6357 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6358 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6359 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6360 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6361 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6362 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6363 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6364 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6365 #ifdef CONFIG_X86_64
6366 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6367 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6368 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6369 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6370 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6371 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6372 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6373 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6374 #endif
6375
6376 regs->rip = kvm_rip_read(vcpu);
6377 regs->rflags = kvm_get_rflags(vcpu);
6378
6379 return 0;
6380 }
6381
6382 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6383 {
6384 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6385 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6386
6387 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6388 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6389 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6390 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6391 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6392 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6393 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6394 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6395 #ifdef CONFIG_X86_64
6396 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6397 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6398 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6399 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6400 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6401 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6402 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6403 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6404 #endif
6405
6406 kvm_rip_write(vcpu, regs->rip);
6407 kvm_set_rflags(vcpu, regs->rflags);
6408
6409 vcpu->arch.exception.pending = false;
6410
6411 kvm_make_request(KVM_REQ_EVENT, vcpu);
6412
6413 return 0;
6414 }
6415
6416 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6417 {
6418 struct kvm_segment cs;
6419
6420 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6421 *db = cs.db;
6422 *l = cs.l;
6423 }
6424 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6425
6426 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6427 struct kvm_sregs *sregs)
6428 {
6429 struct desc_ptr dt;
6430
6431 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6432 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6433 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6434 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6435 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6436 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6437
6438 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6439 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6440
6441 kvm_x86_ops->get_idt(vcpu, &dt);
6442 sregs->idt.limit = dt.size;
6443 sregs->idt.base = dt.address;
6444 kvm_x86_ops->get_gdt(vcpu, &dt);
6445 sregs->gdt.limit = dt.size;
6446 sregs->gdt.base = dt.address;
6447
6448 sregs->cr0 = kvm_read_cr0(vcpu);
6449 sregs->cr2 = vcpu->arch.cr2;
6450 sregs->cr3 = kvm_read_cr3(vcpu);
6451 sregs->cr4 = kvm_read_cr4(vcpu);
6452 sregs->cr8 = kvm_get_cr8(vcpu);
6453 sregs->efer = vcpu->arch.efer;
6454 sregs->apic_base = kvm_get_apic_base(vcpu);
6455
6456 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6457
6458 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6459 set_bit(vcpu->arch.interrupt.nr,
6460 (unsigned long *)sregs->interrupt_bitmap);
6461
6462 return 0;
6463 }
6464
6465 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6466 struct kvm_mp_state *mp_state)
6467 {
6468 kvm_apic_accept_events(vcpu);
6469 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6470 vcpu->arch.pv.pv_unhalted)
6471 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6472 else
6473 mp_state->mp_state = vcpu->arch.mp_state;
6474
6475 return 0;
6476 }
6477
6478 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6479 struct kvm_mp_state *mp_state)
6480 {
6481 if (!kvm_vcpu_has_lapic(vcpu) &&
6482 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6483 return -EINVAL;
6484
6485 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6486 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6487 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6488 } else
6489 vcpu->arch.mp_state = mp_state->mp_state;
6490 kvm_make_request(KVM_REQ_EVENT, vcpu);
6491 return 0;
6492 }
6493
6494 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6495 int reason, bool has_error_code, u32 error_code)
6496 {
6497 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6498 int ret;
6499
6500 init_emulate_ctxt(vcpu);
6501
6502 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6503 has_error_code, error_code);
6504
6505 if (ret)
6506 return EMULATE_FAIL;
6507
6508 kvm_rip_write(vcpu, ctxt->eip);
6509 kvm_set_rflags(vcpu, ctxt->eflags);
6510 kvm_make_request(KVM_REQ_EVENT, vcpu);
6511 return EMULATE_DONE;
6512 }
6513 EXPORT_SYMBOL_GPL(kvm_task_switch);
6514
6515 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6516 struct kvm_sregs *sregs)
6517 {
6518 struct msr_data apic_base_msr;
6519 int mmu_reset_needed = 0;
6520 int pending_vec, max_bits, idx;
6521 struct desc_ptr dt;
6522
6523 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6524 return -EINVAL;
6525
6526 dt.size = sregs->idt.limit;
6527 dt.address = sregs->idt.base;
6528 kvm_x86_ops->set_idt(vcpu, &dt);
6529 dt.size = sregs->gdt.limit;
6530 dt.address = sregs->gdt.base;
6531 kvm_x86_ops->set_gdt(vcpu, &dt);
6532
6533 vcpu->arch.cr2 = sregs->cr2;
6534 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6535 vcpu->arch.cr3 = sregs->cr3;
6536 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6537
6538 kvm_set_cr8(vcpu, sregs->cr8);
6539
6540 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6541 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6542 apic_base_msr.data = sregs->apic_base;
6543 apic_base_msr.host_initiated = true;
6544 kvm_set_apic_base(vcpu, &apic_base_msr);
6545
6546 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6547 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6548 vcpu->arch.cr0 = sregs->cr0;
6549
6550 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6551 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6552 if (sregs->cr4 & X86_CR4_OSXSAVE)
6553 kvm_update_cpuid(vcpu);
6554
6555 idx = srcu_read_lock(&vcpu->kvm->srcu);
6556 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6557 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6558 mmu_reset_needed = 1;
6559 }
6560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6561
6562 if (mmu_reset_needed)
6563 kvm_mmu_reset_context(vcpu);
6564
6565 max_bits = KVM_NR_INTERRUPTS;
6566 pending_vec = find_first_bit(
6567 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6568 if (pending_vec < max_bits) {
6569 kvm_queue_interrupt(vcpu, pending_vec, false);
6570 pr_debug("Set back pending irq %d\n", pending_vec);
6571 }
6572
6573 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6574 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6575 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6576 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6577 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6578 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6579
6580 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6581 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6582
6583 update_cr8_intercept(vcpu);
6584
6585 /* Older userspace won't unhalt the vcpu on reset. */
6586 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6587 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6588 !is_protmode(vcpu))
6589 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6590
6591 kvm_make_request(KVM_REQ_EVENT, vcpu);
6592
6593 return 0;
6594 }
6595
6596 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6597 struct kvm_guest_debug *dbg)
6598 {
6599 unsigned long rflags;
6600 int i, r;
6601
6602 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6603 r = -EBUSY;
6604 if (vcpu->arch.exception.pending)
6605 goto out;
6606 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6607 kvm_queue_exception(vcpu, DB_VECTOR);
6608 else
6609 kvm_queue_exception(vcpu, BP_VECTOR);
6610 }
6611
6612 /*
6613 * Read rflags as long as potentially injected trace flags are still
6614 * filtered out.
6615 */
6616 rflags = kvm_get_rflags(vcpu);
6617
6618 vcpu->guest_debug = dbg->control;
6619 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6620 vcpu->guest_debug = 0;
6621
6622 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6623 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6624 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6625 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6626 } else {
6627 for (i = 0; i < KVM_NR_DB_REGS; i++)
6628 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6629 }
6630 kvm_update_dr7(vcpu);
6631
6632 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6633 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6634 get_segment_base(vcpu, VCPU_SREG_CS);
6635
6636 /*
6637 * Trigger an rflags update that will inject or remove the trace
6638 * flags.
6639 */
6640 kvm_set_rflags(vcpu, rflags);
6641
6642 kvm_x86_ops->update_db_bp_intercept(vcpu);
6643
6644 r = 0;
6645
6646 out:
6647
6648 return r;
6649 }
6650
6651 /*
6652 * Translate a guest virtual address to a guest physical address.
6653 */
6654 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6655 struct kvm_translation *tr)
6656 {
6657 unsigned long vaddr = tr->linear_address;
6658 gpa_t gpa;
6659 int idx;
6660
6661 idx = srcu_read_lock(&vcpu->kvm->srcu);
6662 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6663 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6664 tr->physical_address = gpa;
6665 tr->valid = gpa != UNMAPPED_GVA;
6666 tr->writeable = 1;
6667 tr->usermode = 0;
6668
6669 return 0;
6670 }
6671
6672 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6673 {
6674 struct i387_fxsave_struct *fxsave =
6675 &vcpu->arch.guest_fpu.state->fxsave;
6676
6677 memcpy(fpu->fpr, fxsave->st_space, 128);
6678 fpu->fcw = fxsave->cwd;
6679 fpu->fsw = fxsave->swd;
6680 fpu->ftwx = fxsave->twd;
6681 fpu->last_opcode = fxsave->fop;
6682 fpu->last_ip = fxsave->rip;
6683 fpu->last_dp = fxsave->rdp;
6684 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6685
6686 return 0;
6687 }
6688
6689 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6690 {
6691 struct i387_fxsave_struct *fxsave =
6692 &vcpu->arch.guest_fpu.state->fxsave;
6693
6694 memcpy(fxsave->st_space, fpu->fpr, 128);
6695 fxsave->cwd = fpu->fcw;
6696 fxsave->swd = fpu->fsw;
6697 fxsave->twd = fpu->ftwx;
6698 fxsave->fop = fpu->last_opcode;
6699 fxsave->rip = fpu->last_ip;
6700 fxsave->rdp = fpu->last_dp;
6701 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6702
6703 return 0;
6704 }
6705
6706 int fx_init(struct kvm_vcpu *vcpu)
6707 {
6708 int err;
6709
6710 err = fpu_alloc(&vcpu->arch.guest_fpu);
6711 if (err)
6712 return err;
6713
6714 fpu_finit(&vcpu->arch.guest_fpu);
6715
6716 /*
6717 * Ensure guest xcr0 is valid for loading
6718 */
6719 vcpu->arch.xcr0 = XSTATE_FP;
6720
6721 vcpu->arch.cr0 |= X86_CR0_ET;
6722
6723 return 0;
6724 }
6725 EXPORT_SYMBOL_GPL(fx_init);
6726
6727 static void fx_free(struct kvm_vcpu *vcpu)
6728 {
6729 fpu_free(&vcpu->arch.guest_fpu);
6730 }
6731
6732 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6733 {
6734 if (vcpu->guest_fpu_loaded)
6735 return;
6736
6737 /*
6738 * Restore all possible states in the guest,
6739 * and assume host would use all available bits.
6740 * Guest xcr0 would be loaded later.
6741 */
6742 kvm_put_guest_xcr0(vcpu);
6743 vcpu->guest_fpu_loaded = 1;
6744 __kernel_fpu_begin();
6745 fpu_restore_checking(&vcpu->arch.guest_fpu);
6746 trace_kvm_fpu(1);
6747 }
6748
6749 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6750 {
6751 kvm_put_guest_xcr0(vcpu);
6752
6753 if (!vcpu->guest_fpu_loaded)
6754 return;
6755
6756 vcpu->guest_fpu_loaded = 0;
6757 fpu_save_init(&vcpu->arch.guest_fpu);
6758 __kernel_fpu_end();
6759 ++vcpu->stat.fpu_reload;
6760 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6761 trace_kvm_fpu(0);
6762 }
6763
6764 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6765 {
6766 kvmclock_reset(vcpu);
6767
6768 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6769 fx_free(vcpu);
6770 kvm_x86_ops->vcpu_free(vcpu);
6771 }
6772
6773 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6774 unsigned int id)
6775 {
6776 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6777 printk_once(KERN_WARNING
6778 "kvm: SMP vm created on host with unstable TSC; "
6779 "guest TSC will not be reliable\n");
6780 return kvm_x86_ops->vcpu_create(kvm, id);
6781 }
6782
6783 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6784 {
6785 int r;
6786
6787 vcpu->arch.mtrr_state.have_fixed = 1;
6788 r = vcpu_load(vcpu);
6789 if (r)
6790 return r;
6791 kvm_vcpu_reset(vcpu);
6792 kvm_mmu_setup(vcpu);
6793 vcpu_put(vcpu);
6794
6795 return r;
6796 }
6797
6798 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6799 {
6800 int r;
6801 struct msr_data msr;
6802 struct kvm *kvm = vcpu->kvm;
6803
6804 r = vcpu_load(vcpu);
6805 if (r)
6806 return r;
6807 msr.data = 0x0;
6808 msr.index = MSR_IA32_TSC;
6809 msr.host_initiated = true;
6810 kvm_write_tsc(vcpu, &msr);
6811 vcpu_put(vcpu);
6812
6813 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6814 KVMCLOCK_SYNC_PERIOD);
6815
6816 return r;
6817 }
6818
6819 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6820 {
6821 int r;
6822 vcpu->arch.apf.msr_val = 0;
6823
6824 r = vcpu_load(vcpu);
6825 BUG_ON(r);
6826 kvm_mmu_unload(vcpu);
6827 vcpu_put(vcpu);
6828
6829 fx_free(vcpu);
6830 kvm_x86_ops->vcpu_free(vcpu);
6831 }
6832
6833 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6834 {
6835 atomic_set(&vcpu->arch.nmi_queued, 0);
6836 vcpu->arch.nmi_pending = 0;
6837 vcpu->arch.nmi_injected = false;
6838
6839 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6840 vcpu->arch.dr6 = DR6_FIXED_1;
6841 kvm_update_dr6(vcpu);
6842 vcpu->arch.dr7 = DR7_FIXED_1;
6843 kvm_update_dr7(vcpu);
6844
6845 kvm_make_request(KVM_REQ_EVENT, vcpu);
6846 vcpu->arch.apf.msr_val = 0;
6847 vcpu->arch.st.msr_val = 0;
6848
6849 kvmclock_reset(vcpu);
6850
6851 kvm_clear_async_pf_completion_queue(vcpu);
6852 kvm_async_pf_hash_reset(vcpu);
6853 vcpu->arch.apf.halted = false;
6854
6855 kvm_pmu_reset(vcpu);
6856
6857 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6858 vcpu->arch.regs_avail = ~0;
6859 vcpu->arch.regs_dirty = ~0;
6860
6861 kvm_x86_ops->vcpu_reset(vcpu);
6862 }
6863
6864 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6865 {
6866 struct kvm_segment cs;
6867
6868 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6869 cs.selector = vector << 8;
6870 cs.base = vector << 12;
6871 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6872 kvm_rip_write(vcpu, 0);
6873 }
6874
6875 int kvm_arch_hardware_enable(void *garbage)
6876 {
6877 struct kvm *kvm;
6878 struct kvm_vcpu *vcpu;
6879 int i;
6880 int ret;
6881 u64 local_tsc;
6882 u64 max_tsc = 0;
6883 bool stable, backwards_tsc = false;
6884
6885 kvm_shared_msr_cpu_online();
6886 ret = kvm_x86_ops->hardware_enable(garbage);
6887 if (ret != 0)
6888 return ret;
6889
6890 local_tsc = native_read_tsc();
6891 stable = !check_tsc_unstable();
6892 list_for_each_entry(kvm, &vm_list, vm_list) {
6893 kvm_for_each_vcpu(i, vcpu, kvm) {
6894 if (!stable && vcpu->cpu == smp_processor_id())
6895 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6896 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6897 backwards_tsc = true;
6898 if (vcpu->arch.last_host_tsc > max_tsc)
6899 max_tsc = vcpu->arch.last_host_tsc;
6900 }
6901 }
6902 }
6903
6904 /*
6905 * Sometimes, even reliable TSCs go backwards. This happens on
6906 * platforms that reset TSC during suspend or hibernate actions, but
6907 * maintain synchronization. We must compensate. Fortunately, we can
6908 * detect that condition here, which happens early in CPU bringup,
6909 * before any KVM threads can be running. Unfortunately, we can't
6910 * bring the TSCs fully up to date with real time, as we aren't yet far
6911 * enough into CPU bringup that we know how much real time has actually
6912 * elapsed; our helper function, get_kernel_ns() will be using boot
6913 * variables that haven't been updated yet.
6914 *
6915 * So we simply find the maximum observed TSC above, then record the
6916 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6917 * the adjustment will be applied. Note that we accumulate
6918 * adjustments, in case multiple suspend cycles happen before some VCPU
6919 * gets a chance to run again. In the event that no KVM threads get a
6920 * chance to run, we will miss the entire elapsed period, as we'll have
6921 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6922 * loose cycle time. This isn't too big a deal, since the loss will be
6923 * uniform across all VCPUs (not to mention the scenario is extremely
6924 * unlikely). It is possible that a second hibernate recovery happens
6925 * much faster than a first, causing the observed TSC here to be
6926 * smaller; this would require additional padding adjustment, which is
6927 * why we set last_host_tsc to the local tsc observed here.
6928 *
6929 * N.B. - this code below runs only on platforms with reliable TSC,
6930 * as that is the only way backwards_tsc is set above. Also note
6931 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6932 * have the same delta_cyc adjustment applied if backwards_tsc
6933 * is detected. Note further, this adjustment is only done once,
6934 * as we reset last_host_tsc on all VCPUs to stop this from being
6935 * called multiple times (one for each physical CPU bringup).
6936 *
6937 * Platforms with unreliable TSCs don't have to deal with this, they
6938 * will be compensated by the logic in vcpu_load, which sets the TSC to
6939 * catchup mode. This will catchup all VCPUs to real time, but cannot
6940 * guarantee that they stay in perfect synchronization.
6941 */
6942 if (backwards_tsc) {
6943 u64 delta_cyc = max_tsc - local_tsc;
6944 list_for_each_entry(kvm, &vm_list, vm_list) {
6945 kvm_for_each_vcpu(i, vcpu, kvm) {
6946 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6947 vcpu->arch.last_host_tsc = local_tsc;
6948 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6949 &vcpu->requests);
6950 }
6951
6952 /*
6953 * We have to disable TSC offset matching.. if you were
6954 * booting a VM while issuing an S4 host suspend....
6955 * you may have some problem. Solving this issue is
6956 * left as an exercise to the reader.
6957 */
6958 kvm->arch.last_tsc_nsec = 0;
6959 kvm->arch.last_tsc_write = 0;
6960 }
6961
6962 }
6963 return 0;
6964 }
6965
6966 void kvm_arch_hardware_disable(void *garbage)
6967 {
6968 kvm_x86_ops->hardware_disable(garbage);
6969 drop_user_return_notifiers(garbage);
6970 }
6971
6972 int kvm_arch_hardware_setup(void)
6973 {
6974 return kvm_x86_ops->hardware_setup();
6975 }
6976
6977 void kvm_arch_hardware_unsetup(void)
6978 {
6979 kvm_x86_ops->hardware_unsetup();
6980 }
6981
6982 void kvm_arch_check_processor_compat(void *rtn)
6983 {
6984 kvm_x86_ops->check_processor_compatibility(rtn);
6985 }
6986
6987 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6988 {
6989 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6990 }
6991
6992 struct static_key kvm_no_apic_vcpu __read_mostly;
6993
6994 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6995 {
6996 struct page *page;
6997 struct kvm *kvm;
6998 int r;
6999
7000 BUG_ON(vcpu->kvm == NULL);
7001 kvm = vcpu->kvm;
7002
7003 vcpu->arch.pv.pv_unhalted = false;
7004 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7005 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7006 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7007 else
7008 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7009
7010 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7011 if (!page) {
7012 r = -ENOMEM;
7013 goto fail;
7014 }
7015 vcpu->arch.pio_data = page_address(page);
7016
7017 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7018
7019 r = kvm_mmu_create(vcpu);
7020 if (r < 0)
7021 goto fail_free_pio_data;
7022
7023 if (irqchip_in_kernel(kvm)) {
7024 r = kvm_create_lapic(vcpu);
7025 if (r < 0)
7026 goto fail_mmu_destroy;
7027 } else
7028 static_key_slow_inc(&kvm_no_apic_vcpu);
7029
7030 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7031 GFP_KERNEL);
7032 if (!vcpu->arch.mce_banks) {
7033 r = -ENOMEM;
7034 goto fail_free_lapic;
7035 }
7036 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7037
7038 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7039 r = -ENOMEM;
7040 goto fail_free_mce_banks;
7041 }
7042
7043 r = fx_init(vcpu);
7044 if (r)
7045 goto fail_free_wbinvd_dirty_mask;
7046
7047 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7048 vcpu->arch.pv_time_enabled = false;
7049
7050 vcpu->arch.guest_supported_xcr0 = 0;
7051 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7052
7053 kvm_async_pf_hash_reset(vcpu);
7054 kvm_pmu_init(vcpu);
7055
7056 return 0;
7057 fail_free_wbinvd_dirty_mask:
7058 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7059 fail_free_mce_banks:
7060 kfree(vcpu->arch.mce_banks);
7061 fail_free_lapic:
7062 kvm_free_lapic(vcpu);
7063 fail_mmu_destroy:
7064 kvm_mmu_destroy(vcpu);
7065 fail_free_pio_data:
7066 free_page((unsigned long)vcpu->arch.pio_data);
7067 fail:
7068 return r;
7069 }
7070
7071 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7072 {
7073 int idx;
7074
7075 kvm_pmu_destroy(vcpu);
7076 kfree(vcpu->arch.mce_banks);
7077 kvm_free_lapic(vcpu);
7078 idx = srcu_read_lock(&vcpu->kvm->srcu);
7079 kvm_mmu_destroy(vcpu);
7080 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7081 free_page((unsigned long)vcpu->arch.pio_data);
7082 if (!irqchip_in_kernel(vcpu->kvm))
7083 static_key_slow_dec(&kvm_no_apic_vcpu);
7084 }
7085
7086 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7087 {
7088 if (type)
7089 return -EINVAL;
7090
7091 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7092 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7093 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7094 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7095
7096 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7097 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7098 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7099 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7100 &kvm->arch.irq_sources_bitmap);
7101
7102 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7103 mutex_init(&kvm->arch.apic_map_lock);
7104 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7105
7106 pvclock_update_vm_gtod_copy(kvm);
7107
7108 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7109 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7110
7111 return 0;
7112 }
7113
7114 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7115 {
7116 int r;
7117 r = vcpu_load(vcpu);
7118 BUG_ON(r);
7119 kvm_mmu_unload(vcpu);
7120 vcpu_put(vcpu);
7121 }
7122
7123 static void kvm_free_vcpus(struct kvm *kvm)
7124 {
7125 unsigned int i;
7126 struct kvm_vcpu *vcpu;
7127
7128 /*
7129 * Unpin any mmu pages first.
7130 */
7131 kvm_for_each_vcpu(i, vcpu, kvm) {
7132 kvm_clear_async_pf_completion_queue(vcpu);
7133 kvm_unload_vcpu_mmu(vcpu);
7134 }
7135 kvm_for_each_vcpu(i, vcpu, kvm)
7136 kvm_arch_vcpu_free(vcpu);
7137
7138 mutex_lock(&kvm->lock);
7139 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7140 kvm->vcpus[i] = NULL;
7141
7142 atomic_set(&kvm->online_vcpus, 0);
7143 mutex_unlock(&kvm->lock);
7144 }
7145
7146 void kvm_arch_sync_events(struct kvm *kvm)
7147 {
7148 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7149 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7150 kvm_free_all_assigned_devices(kvm);
7151 kvm_free_pit(kvm);
7152 }
7153
7154 void kvm_arch_destroy_vm(struct kvm *kvm)
7155 {
7156 if (current->mm == kvm->mm) {
7157 /*
7158 * Free memory regions allocated on behalf of userspace,
7159 * unless the the memory map has changed due to process exit
7160 * or fd copying.
7161 */
7162 struct kvm_userspace_memory_region mem;
7163 memset(&mem, 0, sizeof(mem));
7164 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7165 kvm_set_memory_region(kvm, &mem);
7166
7167 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7168 kvm_set_memory_region(kvm, &mem);
7169
7170 mem.slot = TSS_PRIVATE_MEMSLOT;
7171 kvm_set_memory_region(kvm, &mem);
7172 }
7173 kvm_iommu_unmap_guest(kvm);
7174 kfree(kvm->arch.vpic);
7175 kfree(kvm->arch.vioapic);
7176 kvm_free_vcpus(kvm);
7177 if (kvm->arch.apic_access_page)
7178 put_page(kvm->arch.apic_access_page);
7179 if (kvm->arch.ept_identity_pagetable)
7180 put_page(kvm->arch.ept_identity_pagetable);
7181 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7182 }
7183
7184 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7185 struct kvm_memory_slot *dont)
7186 {
7187 int i;
7188
7189 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7190 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7191 kvm_kvfree(free->arch.rmap[i]);
7192 free->arch.rmap[i] = NULL;
7193 }
7194 if (i == 0)
7195 continue;
7196
7197 if (!dont || free->arch.lpage_info[i - 1] !=
7198 dont->arch.lpage_info[i - 1]) {
7199 kvm_kvfree(free->arch.lpage_info[i - 1]);
7200 free->arch.lpage_info[i - 1] = NULL;
7201 }
7202 }
7203 }
7204
7205 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7206 unsigned long npages)
7207 {
7208 int i;
7209
7210 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7211 unsigned long ugfn;
7212 int lpages;
7213 int level = i + 1;
7214
7215 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7216 slot->base_gfn, level) + 1;
7217
7218 slot->arch.rmap[i] =
7219 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7220 if (!slot->arch.rmap[i])
7221 goto out_free;
7222 if (i == 0)
7223 continue;
7224
7225 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7226 sizeof(*slot->arch.lpage_info[i - 1]));
7227 if (!slot->arch.lpage_info[i - 1])
7228 goto out_free;
7229
7230 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7231 slot->arch.lpage_info[i - 1][0].write_count = 1;
7232 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7233 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7234 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7235 /*
7236 * If the gfn and userspace address are not aligned wrt each
7237 * other, or if explicitly asked to, disable large page
7238 * support for this slot
7239 */
7240 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7241 !kvm_largepages_enabled()) {
7242 unsigned long j;
7243
7244 for (j = 0; j < lpages; ++j)
7245 slot->arch.lpage_info[i - 1][j].write_count = 1;
7246 }
7247 }
7248
7249 return 0;
7250
7251 out_free:
7252 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7253 kvm_kvfree(slot->arch.rmap[i]);
7254 slot->arch.rmap[i] = NULL;
7255 if (i == 0)
7256 continue;
7257
7258 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7259 slot->arch.lpage_info[i - 1] = NULL;
7260 }
7261 return -ENOMEM;
7262 }
7263
7264 void kvm_arch_memslots_updated(struct kvm *kvm)
7265 {
7266 /*
7267 * memslots->generation has been incremented.
7268 * mmio generation may have reached its maximum value.
7269 */
7270 kvm_mmu_invalidate_mmio_sptes(kvm);
7271 }
7272
7273 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7274 struct kvm_memory_slot *memslot,
7275 struct kvm_userspace_memory_region *mem,
7276 enum kvm_mr_change change)
7277 {
7278 /*
7279 * Only private memory slots need to be mapped here since
7280 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7281 */
7282 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7283 unsigned long userspace_addr;
7284
7285 /*
7286 * MAP_SHARED to prevent internal slot pages from being moved
7287 * by fork()/COW.
7288 */
7289 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7290 PROT_READ | PROT_WRITE,
7291 MAP_SHARED | MAP_ANONYMOUS, 0);
7292
7293 if (IS_ERR((void *)userspace_addr))
7294 return PTR_ERR((void *)userspace_addr);
7295
7296 memslot->userspace_addr = userspace_addr;
7297 }
7298
7299 return 0;
7300 }
7301
7302 void kvm_arch_commit_memory_region(struct kvm *kvm,
7303 struct kvm_userspace_memory_region *mem,
7304 const struct kvm_memory_slot *old,
7305 enum kvm_mr_change change)
7306 {
7307
7308 int nr_mmu_pages = 0;
7309
7310 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7311 int ret;
7312
7313 ret = vm_munmap(old->userspace_addr,
7314 old->npages * PAGE_SIZE);
7315 if (ret < 0)
7316 printk(KERN_WARNING
7317 "kvm_vm_ioctl_set_memory_region: "
7318 "failed to munmap memory\n");
7319 }
7320
7321 if (!kvm->arch.n_requested_mmu_pages)
7322 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7323
7324 if (nr_mmu_pages)
7325 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7326 /*
7327 * Write protect all pages for dirty logging.
7328 * Existing largepage mappings are destroyed here and new ones will
7329 * not be created until the end of the logging.
7330 */
7331 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7332 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7333 }
7334
7335 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7336 {
7337 kvm_mmu_invalidate_zap_all_pages(kvm);
7338 }
7339
7340 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7341 struct kvm_memory_slot *slot)
7342 {
7343 kvm_mmu_invalidate_zap_all_pages(kvm);
7344 }
7345
7346 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7347 {
7348 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7349 kvm_x86_ops->check_nested_events(vcpu, false);
7350
7351 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7352 !vcpu->arch.apf.halted)
7353 || !list_empty_careful(&vcpu->async_pf.done)
7354 || kvm_apic_has_events(vcpu)
7355 || vcpu->arch.pv.pv_unhalted
7356 || atomic_read(&vcpu->arch.nmi_queued) ||
7357 (kvm_arch_interrupt_allowed(vcpu) &&
7358 kvm_cpu_has_interrupt(vcpu));
7359 }
7360
7361 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7362 {
7363 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7364 }
7365
7366 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7367 {
7368 return kvm_x86_ops->interrupt_allowed(vcpu);
7369 }
7370
7371 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7372 {
7373 unsigned long current_rip = kvm_rip_read(vcpu) +
7374 get_segment_base(vcpu, VCPU_SREG_CS);
7375
7376 return current_rip == linear_rip;
7377 }
7378 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7379
7380 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7381 {
7382 unsigned long rflags;
7383
7384 rflags = kvm_x86_ops->get_rflags(vcpu);
7385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7386 rflags &= ~X86_EFLAGS_TF;
7387 return rflags;
7388 }
7389 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7390
7391 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7392 {
7393 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7394 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7395 rflags |= X86_EFLAGS_TF;
7396 kvm_x86_ops->set_rflags(vcpu, rflags);
7397 kvm_make_request(KVM_REQ_EVENT, vcpu);
7398 }
7399 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7400
7401 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7402 {
7403 int r;
7404
7405 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7406 work->wakeup_all)
7407 return;
7408
7409 r = kvm_mmu_reload(vcpu);
7410 if (unlikely(r))
7411 return;
7412
7413 if (!vcpu->arch.mmu.direct_map &&
7414 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7415 return;
7416
7417 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7418 }
7419
7420 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7421 {
7422 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7423 }
7424
7425 static inline u32 kvm_async_pf_next_probe(u32 key)
7426 {
7427 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7428 }
7429
7430 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7431 {
7432 u32 key = kvm_async_pf_hash_fn(gfn);
7433
7434 while (vcpu->arch.apf.gfns[key] != ~0)
7435 key = kvm_async_pf_next_probe(key);
7436
7437 vcpu->arch.apf.gfns[key] = gfn;
7438 }
7439
7440 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7441 {
7442 int i;
7443 u32 key = kvm_async_pf_hash_fn(gfn);
7444
7445 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7446 (vcpu->arch.apf.gfns[key] != gfn &&
7447 vcpu->arch.apf.gfns[key] != ~0); i++)
7448 key = kvm_async_pf_next_probe(key);
7449
7450 return key;
7451 }
7452
7453 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7454 {
7455 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7456 }
7457
7458 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7459 {
7460 u32 i, j, k;
7461
7462 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7463 while (true) {
7464 vcpu->arch.apf.gfns[i] = ~0;
7465 do {
7466 j = kvm_async_pf_next_probe(j);
7467 if (vcpu->arch.apf.gfns[j] == ~0)
7468 return;
7469 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7470 /*
7471 * k lies cyclically in ]i,j]
7472 * | i.k.j |
7473 * |....j i.k.| or |.k..j i...|
7474 */
7475 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7476 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7477 i = j;
7478 }
7479 }
7480
7481 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7482 {
7483
7484 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7485 sizeof(val));
7486 }
7487
7488 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7489 struct kvm_async_pf *work)
7490 {
7491 struct x86_exception fault;
7492
7493 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7494 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7495
7496 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7497 (vcpu->arch.apf.send_user_only &&
7498 kvm_x86_ops->get_cpl(vcpu) == 0))
7499 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7500 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7501 fault.vector = PF_VECTOR;
7502 fault.error_code_valid = true;
7503 fault.error_code = 0;
7504 fault.nested_page_fault = false;
7505 fault.address = work->arch.token;
7506 kvm_inject_page_fault(vcpu, &fault);
7507 }
7508 }
7509
7510 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7511 struct kvm_async_pf *work)
7512 {
7513 struct x86_exception fault;
7514
7515 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7516 if (work->wakeup_all)
7517 work->arch.token = ~0; /* broadcast wakeup */
7518 else
7519 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7520
7521 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7522 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7523 fault.vector = PF_VECTOR;
7524 fault.error_code_valid = true;
7525 fault.error_code = 0;
7526 fault.nested_page_fault = false;
7527 fault.address = work->arch.token;
7528 kvm_inject_page_fault(vcpu, &fault);
7529 }
7530 vcpu->arch.apf.halted = false;
7531 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7532 }
7533
7534 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7535 {
7536 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7537 return true;
7538 else
7539 return !kvm_event_needs_reinjection(vcpu) &&
7540 kvm_x86_ops->interrupt_allowed(vcpu);
7541 }
7542
7543 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7544 {
7545 atomic_inc(&kvm->arch.noncoherent_dma_count);
7546 }
7547 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7548
7549 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7550 {
7551 atomic_dec(&kvm->arch.noncoherent_dma_count);
7552 }
7553 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7554
7555 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7556 {
7557 return atomic_read(&kvm->arch.noncoherent_dma_count);
7558 }
7559 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7560
7561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
This page took 0.189689 seconds and 6 git commands to generate.