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Merge branch 'for-4.0' of git://linux-nfs.org/~bfields/linux
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
53
54 #define CREATE_TRACE_POINTS
55 #include "trace.h"
56
57 #include <asm/debugreg.h>
58 #include <asm/msr.h>
59 #include <asm/desc.h>
60 #include <asm/mtrr.h>
61 #include <asm/mce.h>
62 #include <asm/i387.h>
63 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/xcr.h>
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 bool kvm_has_tsc_control;
103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104 u32 kvm_max_guest_tsc_khz;
105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108 static u32 tsc_tolerance_ppm = 250;
109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
112 unsigned int lapic_timer_advance_ns = 0;
113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
115 static bool backwards_tsc_observed = false;
116
117 #define KVM_NR_SHARED_MSRS 16
118
119 struct kvm_shared_msrs_global {
120 int nr;
121 u32 msrs[KVM_NR_SHARED_MSRS];
122 };
123
124 struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
131 };
132
133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
134 static struct kvm_shared_msrs __percpu *shared_msrs;
135
136 struct kvm_stats_debugfs_item debugfs_entries[] = {
137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
147 { "halt_exits", VCPU_STAT(halt_exits) },
148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
149 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
150 { "hypercalls", VCPU_STAT(hypercalls) },
151 { "request_irq", VCPU_STAT(request_irq_exits) },
152 { "irq_exits", VCPU_STAT(irq_exits) },
153 { "host_state_reload", VCPU_STAT(host_state_reload) },
154 { "efer_reload", VCPU_STAT(efer_reload) },
155 { "fpu_reload", VCPU_STAT(fpu_reload) },
156 { "insn_emulation", VCPU_STAT(insn_emulation) },
157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
158 { "irq_injections", VCPU_STAT(irq_injections) },
159 { "nmi_injections", VCPU_STAT(nmi_injections) },
160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164 { "mmu_flooded", VM_STAT(mmu_flooded) },
165 { "mmu_recycled", VM_STAT(mmu_recycled) },
166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
167 { "mmu_unsync", VM_STAT(mmu_unsync) },
168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
169 { "largepages", VM_STAT(lpages) },
170 { NULL }
171 };
172
173 u64 __read_mostly host_xcr0;
174
175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176
177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178 {
179 int i;
180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181 vcpu->arch.apf.gfns[i] = ~0;
182 }
183
184 static void kvm_on_user_return(struct user_return_notifier *urn)
185 {
186 unsigned slot;
187 struct kvm_shared_msrs *locals
188 = container_of(urn, struct kvm_shared_msrs, urn);
189 struct kvm_shared_msr_values *values;
190
191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
192 values = &locals->values[slot];
193 if (values->host != values->curr) {
194 wrmsrl(shared_msrs_global.msrs[slot], values->host);
195 values->curr = values->host;
196 }
197 }
198 locals->registered = false;
199 user_return_notifier_unregister(urn);
200 }
201
202 static void shared_msr_update(unsigned slot, u32 msr)
203 {
204 u64 value;
205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207
208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217 }
218
219 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 {
221 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
222 if (slot >= shared_msrs_global.nr)
223 shared_msrs_global.nr = slot + 1;
224 shared_msrs_global.msrs[slot] = msr;
225 /* we need ensured the shared_msr_global have been updated */
226 smp_wmb();
227 }
228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230 static void kvm_shared_msr_cpu_online(void)
231 {
232 unsigned i;
233
234 for (i = 0; i < shared_msrs_global.nr; ++i)
235 shared_msr_update(i, shared_msrs_global.msrs[i]);
236 }
237
238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 {
240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242 int err;
243
244 if (((value ^ smsr->values[slot].curr) & mask) == 0)
245 return 0;
246 smsr->values[slot].curr = value;
247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248 if (err)
249 return 1;
250
251 if (!smsr->registered) {
252 smsr->urn.on_user_return = kvm_on_user_return;
253 user_return_notifier_register(&smsr->urn);
254 smsr->registered = true;
255 }
256 return 0;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
260 static void drop_user_return_notifiers(void)
261 {
262 unsigned int cpu = smp_processor_id();
263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264
265 if (smsr->registered)
266 kvm_on_user_return(&smsr->urn);
267 }
268
269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 {
271 return vcpu->arch.apic_base;
272 }
273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 {
277 u64 old_state = vcpu->arch.apic_base &
278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279 u64 new_state = msr_info->data &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284 if (!msr_info->host_initiated &&
285 ((msr_info->data & reserved_bits) != 0 ||
286 new_state == X2APIC_ENABLE ||
287 (new_state == MSR_IA32_APICBASE_ENABLE &&
288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290 old_state == 0)))
291 return 1;
292
293 kvm_lapic_set_base(vcpu, msr_info->data);
294 return 0;
295 }
296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
298 asmlinkage __visible void kvm_spurious_fault(void)
299 {
300 /* Fault while not rebooting. We want the trace. */
301 BUG();
302 }
303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
305 #define EXCPT_BENIGN 0
306 #define EXCPT_CONTRIBUTORY 1
307 #define EXCPT_PF 2
308
309 static int exception_class(int vector)
310 {
311 switch (vector) {
312 case PF_VECTOR:
313 return EXCPT_PF;
314 case DE_VECTOR:
315 case TS_VECTOR:
316 case NP_VECTOR:
317 case SS_VECTOR:
318 case GP_VECTOR:
319 return EXCPT_CONTRIBUTORY;
320 default:
321 break;
322 }
323 return EXCPT_BENIGN;
324 }
325
326 #define EXCPT_FAULT 0
327 #define EXCPT_TRAP 1
328 #define EXCPT_ABORT 2
329 #define EXCPT_INTERRUPT 3
330
331 static int exception_type(int vector)
332 {
333 unsigned int mask;
334
335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336 return EXCPT_INTERRUPT;
337
338 mask = 1 << vector;
339
340 /* #DB is trap, as instruction watchpoints are handled elsewhere */
341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342 return EXCPT_TRAP;
343
344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345 return EXCPT_ABORT;
346
347 /* Reserved exceptions will result in fault */
348 return EXCPT_FAULT;
349 }
350
351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
352 unsigned nr, bool has_error, u32 error_code,
353 bool reinject)
354 {
355 u32 prev_nr;
356 int class1, class2;
357
358 kvm_make_request(KVM_REQ_EVENT, vcpu);
359
360 if (!vcpu->arch.exception.pending) {
361 queue:
362 if (has_error && !is_protmode(vcpu))
363 has_error = false;
364 vcpu->arch.exception.pending = true;
365 vcpu->arch.exception.has_error_code = has_error;
366 vcpu->arch.exception.nr = nr;
367 vcpu->arch.exception.error_code = error_code;
368 vcpu->arch.exception.reinject = reinject;
369 return;
370 }
371
372 /* to check exception */
373 prev_nr = vcpu->arch.exception.nr;
374 if (prev_nr == DF_VECTOR) {
375 /* triple fault -> shutdown */
376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
377 return;
378 }
379 class1 = exception_class(prev_nr);
380 class2 = exception_class(nr);
381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383 /* generate double fault per SDM Table 5-5 */
384 vcpu->arch.exception.pending = true;
385 vcpu->arch.exception.has_error_code = true;
386 vcpu->arch.exception.nr = DF_VECTOR;
387 vcpu->arch.exception.error_code = 0;
388 } else
389 /* replace previous exception with a new one in a hope
390 that instruction re-execution will regenerate lost
391 exception */
392 goto queue;
393 }
394
395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 {
397 kvm_multiple_exception(vcpu, nr, false, 0, false);
398 }
399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 {
403 kvm_multiple_exception(vcpu, nr, false, 0, true);
404 }
405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
408 {
409 if (err)
410 kvm_inject_gp(vcpu, 0);
411 else
412 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 }
414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415
416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 {
418 ++vcpu->stat.pf_guest;
419 vcpu->arch.cr2 = fault->address;
420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 }
422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423
424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 {
426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428 else
429 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430
431 return fault->nested_page_fault;
432 }
433
434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 {
436 atomic_inc(&vcpu->arch.nmi_queued);
437 kvm_make_request(KVM_REQ_NMI, vcpu);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 {
443 kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 }
445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 {
449 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 }
451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
453 /*
454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
455 * a #GP and return false.
456 */
457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 {
459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 return true;
461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462 return false;
463 }
464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465
466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 {
468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469 return true;
470
471 kvm_queue_exception(vcpu, UD_VECTOR);
472 return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_dr);
475
476 /*
477 * This function will be used to read from the physical memory of the currently
478 * running guest. The difference to kvm_read_guest_page is that this function
479 * can read from guest physical or from the guest's guest physical memory.
480 */
481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482 gfn_t ngfn, void *data, int offset, int len,
483 u32 access)
484 {
485 struct x86_exception exception;
486 gfn_t real_gfn;
487 gpa_t ngpa;
488
489 ngpa = gfn_to_gpa(ngfn);
490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
491 if (real_gfn == UNMAPPED_GVA)
492 return -EFAULT;
493
494 real_gfn = gpa_to_gfn(real_gfn);
495
496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 }
498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
501 void *data, int offset, int len, u32 access)
502 {
503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504 data, offset, len, access);
505 }
506
507 /*
508 * Load the pae pdptrs. Return true is they are all valid.
509 */
510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 {
512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514 int i;
515 int ret;
516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517
518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519 offset * sizeof(u64), sizeof(pdpte),
520 PFERR_USER_MASK|PFERR_WRITE_MASK);
521 if (ret < 0) {
522 ret = 0;
523 goto out;
524 }
525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
526 if (is_present_gpte(pdpte[i]) &&
527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
528 ret = 0;
529 goto out;
530 }
531 }
532 ret = 1;
533
534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
535 __set_bit(VCPU_EXREG_PDPTR,
536 (unsigned long *)&vcpu->arch.regs_avail);
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_dirty);
539 out:
540
541 return ret;
542 }
543 EXPORT_SYMBOL_GPL(load_pdptrs);
544
545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 {
547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
548 bool changed = true;
549 int offset;
550 gfn_t gfn;
551 int r;
552
553 if (is_long_mode(vcpu) || !is_pae(vcpu))
554 return false;
555
556 if (!test_bit(VCPU_EXREG_PDPTR,
557 (unsigned long *)&vcpu->arch.regs_avail))
558 return true;
559
560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563 PFERR_USER_MASK | PFERR_WRITE_MASK);
564 if (r < 0)
565 goto out;
566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
567 out:
568
569 return changed;
570 }
571
572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 {
574 unsigned long old_cr0 = kvm_read_cr0(vcpu);
575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576 X86_CR0_CD | X86_CR0_NW;
577
578 cr0 |= X86_CR0_ET;
579
580 #ifdef CONFIG_X86_64
581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
583 #endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
586
587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
589
590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 #ifdef CONFIG_X86_64
595 if ((vcpu->arch.efer & EFER_LME)) {
596 int cs_db, cs_l;
597
598 if (!is_pae(vcpu))
599 return 1;
600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
601 if (cs_l)
602 return 1;
603 } else
604 #endif
605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606 kvm_read_cr3(vcpu)))
607 return 1;
608 }
609
610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
613 kvm_x86_ops->set_cr0(vcpu, cr0);
614
615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
616 kvm_clear_async_pf_completion_queue(vcpu);
617 kvm_async_pf_hash_reset(vcpu);
618 }
619
620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
622 return 0;
623 }
624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625
626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 {
628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 }
630 EXPORT_SYMBOL_GPL(kvm_lmsw);
631
632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 {
634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635 !vcpu->guest_xcr0_loaded) {
636 /* kvm_set_xcr() also depends on this */
637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638 vcpu->guest_xcr0_loaded = 1;
639 }
640 }
641
642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 {
644 if (vcpu->guest_xcr0_loaded) {
645 if (vcpu->arch.xcr0 != host_xcr0)
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647 vcpu->guest_xcr0_loaded = 0;
648 }
649 }
650
651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
652 {
653 u64 xcr0 = xcr;
654 u64 old_xcr0 = vcpu->arch.xcr0;
655 u64 valid_bits;
656
657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
658 if (index != XCR_XFEATURE_ENABLED_MASK)
659 return 1;
660 if (!(xcr0 & XSTATE_FP))
661 return 1;
662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663 return 1;
664
665 /*
666 * Do not allow the guest to set bits that we do not support
667 * saving. However, xcr0 bit 0 is always set, even if the
668 * emulated CPU does not support XSAVE (see fx_init).
669 */
670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671 if (xcr0 & ~valid_bits)
672 return 1;
673
674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675 return 1;
676
677 if (xcr0 & XSTATE_AVX512) {
678 if (!(xcr0 & XSTATE_YMM))
679 return 1;
680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681 return 1;
682 }
683 kvm_put_guest_xcr0(vcpu);
684 vcpu->arch.xcr0 = xcr0;
685
686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687 kvm_update_cpuid(vcpu);
688 return 0;
689 }
690
691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692 {
693 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694 __kvm_set_xcr(vcpu, index, xcr)) {
695 kvm_inject_gp(vcpu, 0);
696 return 1;
697 }
698 return 0;
699 }
700 EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
703 {
704 unsigned long old_cr4 = kvm_read_cr4(vcpu);
705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
706 X86_CR4_PAE | X86_CR4_SMEP;
707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
709
710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
720 return 1;
721
722 if (is_long_mode(vcpu)) {
723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
729 return 1;
730
731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
741 return 1;
742
743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
745 kvm_mmu_reset_context(vcpu);
746
747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
749
750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
751 kvm_update_cpuid(vcpu);
752
753 return 0;
754 }
755 EXPORT_SYMBOL_GPL(kvm_set_cr4);
756
757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
758 {
759 #ifdef CONFIG_X86_64
760 cr3 &= ~CR3_PCID_INVD;
761 #endif
762
763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
764 kvm_mmu_sync_roots(vcpu);
765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
766 return 0;
767 }
768
769 if (is_long_mode(vcpu)) {
770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
774 return 1;
775
776 vcpu->arch.cr3 = cr3;
777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
778 kvm_mmu_new_cr3(vcpu);
779 return 0;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_cr3);
782
783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
784 {
785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
790 vcpu->arch.cr8 = cr8;
791 return 0;
792 }
793 EXPORT_SYMBOL_GPL(kvm_set_cr8);
794
795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
796 {
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
800 return vcpu->arch.cr8;
801 }
802 EXPORT_SYMBOL_GPL(kvm_get_cr8);
803
804 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
805 {
806 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
807 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
808 }
809
810 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
811 {
812 unsigned long dr7;
813
814 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
815 dr7 = vcpu->arch.guest_debug_dr7;
816 else
817 dr7 = vcpu->arch.dr7;
818 kvm_x86_ops->set_dr7(vcpu, dr7);
819 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
820 if (dr7 & DR7_BP_EN_MASK)
821 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
822 }
823
824 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
825 {
826 u64 fixed = DR6_FIXED_1;
827
828 if (!guest_cpuid_has_rtm(vcpu))
829 fixed |= DR6_RTM;
830 return fixed;
831 }
832
833 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
834 {
835 switch (dr) {
836 case 0 ... 3:
837 vcpu->arch.db[dr] = val;
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 vcpu->arch.eff_db[dr] = val;
840 break;
841 case 4:
842 /* fall through */
843 case 6:
844 if (val & 0xffffffff00000000ULL)
845 return -1; /* #GP */
846 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
847 kvm_update_dr6(vcpu);
848 break;
849 case 5:
850 /* fall through */
851 default: /* 7 */
852 if (val & 0xffffffff00000000ULL)
853 return -1; /* #GP */
854 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
855 kvm_update_dr7(vcpu);
856 break;
857 }
858
859 return 0;
860 }
861
862 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
863 {
864 if (__kvm_set_dr(vcpu, dr, val)) {
865 kvm_inject_gp(vcpu, 0);
866 return 1;
867 }
868 return 0;
869 }
870 EXPORT_SYMBOL_GPL(kvm_set_dr);
871
872 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
873 {
874 switch (dr) {
875 case 0 ... 3:
876 *val = vcpu->arch.db[dr];
877 break;
878 case 4:
879 /* fall through */
880 case 6:
881 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
882 *val = vcpu->arch.dr6;
883 else
884 *val = kvm_x86_ops->get_dr6(vcpu);
885 break;
886 case 5:
887 /* fall through */
888 default: /* 7 */
889 *val = vcpu->arch.dr7;
890 break;
891 }
892 return 0;
893 }
894 EXPORT_SYMBOL_GPL(kvm_get_dr);
895
896 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
897 {
898 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
899 u64 data;
900 int err;
901
902 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
903 if (err)
904 return err;
905 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
906 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
907 return err;
908 }
909 EXPORT_SYMBOL_GPL(kvm_rdpmc);
910
911 /*
912 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
913 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
914 *
915 * This list is modified at module load time to reflect the
916 * capabilities of the host cpu. This capabilities test skips MSRs that are
917 * kvm-specific. Those are put in the beginning of the list.
918 */
919
920 #define KVM_SAVE_MSRS_BEGIN 12
921 static u32 msrs_to_save[] = {
922 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
923 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
924 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
925 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
926 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
927 MSR_KVM_PV_EOI_EN,
928 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
929 MSR_STAR,
930 #ifdef CONFIG_X86_64
931 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
932 #endif
933 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
934 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
935 };
936
937 static unsigned num_msrs_to_save;
938
939 static const u32 emulated_msrs[] = {
940 MSR_IA32_TSC_ADJUST,
941 MSR_IA32_TSCDEADLINE,
942 MSR_IA32_MISC_ENABLE,
943 MSR_IA32_MCG_STATUS,
944 MSR_IA32_MCG_CTL,
945 };
946
947 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
948 {
949 if (efer & efer_reserved_bits)
950 return false;
951
952 if (efer & EFER_FFXSR) {
953 struct kvm_cpuid_entry2 *feat;
954
955 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
956 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
957 return false;
958 }
959
960 if (efer & EFER_SVME) {
961 struct kvm_cpuid_entry2 *feat;
962
963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
964 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
965 return false;
966 }
967
968 return true;
969 }
970 EXPORT_SYMBOL_GPL(kvm_valid_efer);
971
972 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
973 {
974 u64 old_efer = vcpu->arch.efer;
975
976 if (!kvm_valid_efer(vcpu, efer))
977 return 1;
978
979 if (is_paging(vcpu)
980 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
981 return 1;
982
983 efer &= ~EFER_LMA;
984 efer |= vcpu->arch.efer & EFER_LMA;
985
986 kvm_x86_ops->set_efer(vcpu, efer);
987
988 /* Update reserved bits */
989 if ((efer ^ old_efer) & EFER_NX)
990 kvm_mmu_reset_context(vcpu);
991
992 return 0;
993 }
994
995 void kvm_enable_efer_bits(u64 mask)
996 {
997 efer_reserved_bits &= ~mask;
998 }
999 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1000
1001 /*
1002 * Writes msr value into into the appropriate "register".
1003 * Returns 0 on success, non-0 otherwise.
1004 * Assumes vcpu_load() was already called.
1005 */
1006 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1007 {
1008 switch (msr->index) {
1009 case MSR_FS_BASE:
1010 case MSR_GS_BASE:
1011 case MSR_KERNEL_GS_BASE:
1012 case MSR_CSTAR:
1013 case MSR_LSTAR:
1014 if (is_noncanonical_address(msr->data))
1015 return 1;
1016 break;
1017 case MSR_IA32_SYSENTER_EIP:
1018 case MSR_IA32_SYSENTER_ESP:
1019 /*
1020 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1021 * non-canonical address is written on Intel but not on
1022 * AMD (which ignores the top 32-bits, because it does
1023 * not implement 64-bit SYSENTER).
1024 *
1025 * 64-bit code should hence be able to write a non-canonical
1026 * value on AMD. Making the address canonical ensures that
1027 * vmentry does not fail on Intel after writing a non-canonical
1028 * value, and that something deterministic happens if the guest
1029 * invokes 64-bit SYSENTER.
1030 */
1031 msr->data = get_canonical(msr->data);
1032 }
1033 return kvm_x86_ops->set_msr(vcpu, msr);
1034 }
1035 EXPORT_SYMBOL_GPL(kvm_set_msr);
1036
1037 /*
1038 * Adapt set_msr() to msr_io()'s calling convention
1039 */
1040 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1041 {
1042 struct msr_data msr;
1043
1044 msr.data = *data;
1045 msr.index = index;
1046 msr.host_initiated = true;
1047 return kvm_set_msr(vcpu, &msr);
1048 }
1049
1050 #ifdef CONFIG_X86_64
1051 struct pvclock_gtod_data {
1052 seqcount_t seq;
1053
1054 struct { /* extract of a clocksource struct */
1055 int vclock_mode;
1056 cycle_t cycle_last;
1057 cycle_t mask;
1058 u32 mult;
1059 u32 shift;
1060 } clock;
1061
1062 u64 boot_ns;
1063 u64 nsec_base;
1064 };
1065
1066 static struct pvclock_gtod_data pvclock_gtod_data;
1067
1068 static void update_pvclock_gtod(struct timekeeper *tk)
1069 {
1070 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1071 u64 boot_ns;
1072
1073 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
1074
1075 write_seqcount_begin(&vdata->seq);
1076
1077 /* copy pvclock gtod data */
1078 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1079 vdata->clock.cycle_last = tk->tkr.cycle_last;
1080 vdata->clock.mask = tk->tkr.mask;
1081 vdata->clock.mult = tk->tkr.mult;
1082 vdata->clock.shift = tk->tkr.shift;
1083
1084 vdata->boot_ns = boot_ns;
1085 vdata->nsec_base = tk->tkr.xtime_nsec;
1086
1087 write_seqcount_end(&vdata->seq);
1088 }
1089 #endif
1090
1091 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1092 {
1093 /*
1094 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1095 * vcpu_enter_guest. This function is only called from
1096 * the physical CPU that is running vcpu.
1097 */
1098 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1099 }
1100
1101 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1102 {
1103 int version;
1104 int r;
1105 struct pvclock_wall_clock wc;
1106 struct timespec boot;
1107
1108 if (!wall_clock)
1109 return;
1110
1111 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1112 if (r)
1113 return;
1114
1115 if (version & 1)
1116 ++version; /* first time write, random junk */
1117
1118 ++version;
1119
1120 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1121
1122 /*
1123 * The guest calculates current wall clock time by adding
1124 * system time (updated by kvm_guest_time_update below) to the
1125 * wall clock specified here. guest system time equals host
1126 * system time for us, thus we must fill in host boot time here.
1127 */
1128 getboottime(&boot);
1129
1130 if (kvm->arch.kvmclock_offset) {
1131 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1132 boot = timespec_sub(boot, ts);
1133 }
1134 wc.sec = boot.tv_sec;
1135 wc.nsec = boot.tv_nsec;
1136 wc.version = version;
1137
1138 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1139
1140 version++;
1141 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1142 }
1143
1144 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1145 {
1146 uint32_t quotient, remainder;
1147
1148 /* Don't try to replace with do_div(), this one calculates
1149 * "(dividend << 32) / divisor" */
1150 __asm__ ( "divl %4"
1151 : "=a" (quotient), "=d" (remainder)
1152 : "0" (0), "1" (dividend), "r" (divisor) );
1153 return quotient;
1154 }
1155
1156 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1157 s8 *pshift, u32 *pmultiplier)
1158 {
1159 uint64_t scaled64;
1160 int32_t shift = 0;
1161 uint64_t tps64;
1162 uint32_t tps32;
1163
1164 tps64 = base_khz * 1000LL;
1165 scaled64 = scaled_khz * 1000LL;
1166 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1167 tps64 >>= 1;
1168 shift--;
1169 }
1170
1171 tps32 = (uint32_t)tps64;
1172 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1173 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1174 scaled64 >>= 1;
1175 else
1176 tps32 <<= 1;
1177 shift++;
1178 }
1179
1180 *pshift = shift;
1181 *pmultiplier = div_frac(scaled64, tps32);
1182
1183 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1184 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1185 }
1186
1187 static inline u64 get_kernel_ns(void)
1188 {
1189 return ktime_get_boot_ns();
1190 }
1191
1192 #ifdef CONFIG_X86_64
1193 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1194 #endif
1195
1196 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1197 static unsigned long max_tsc_khz;
1198
1199 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1200 {
1201 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1202 vcpu->arch.virtual_tsc_shift);
1203 }
1204
1205 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1206 {
1207 u64 v = (u64)khz * (1000000 + ppm);
1208 do_div(v, 1000000);
1209 return v;
1210 }
1211
1212 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1213 {
1214 u32 thresh_lo, thresh_hi;
1215 int use_scaling = 0;
1216
1217 /* tsc_khz can be zero if TSC calibration fails */
1218 if (this_tsc_khz == 0)
1219 return;
1220
1221 /* Compute a scale to convert nanoseconds in TSC cycles */
1222 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1223 &vcpu->arch.virtual_tsc_shift,
1224 &vcpu->arch.virtual_tsc_mult);
1225 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1226
1227 /*
1228 * Compute the variation in TSC rate which is acceptable
1229 * within the range of tolerance and decide if the
1230 * rate being applied is within that bounds of the hardware
1231 * rate. If so, no scaling or compensation need be done.
1232 */
1233 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1234 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1235 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1236 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1237 use_scaling = 1;
1238 }
1239 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1240 }
1241
1242 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1243 {
1244 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1245 vcpu->arch.virtual_tsc_mult,
1246 vcpu->arch.virtual_tsc_shift);
1247 tsc += vcpu->arch.this_tsc_write;
1248 return tsc;
1249 }
1250
1251 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1252 {
1253 #ifdef CONFIG_X86_64
1254 bool vcpus_matched;
1255 struct kvm_arch *ka = &vcpu->kvm->arch;
1256 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1257
1258 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1259 atomic_read(&vcpu->kvm->online_vcpus));
1260
1261 /*
1262 * Once the masterclock is enabled, always perform request in
1263 * order to update it.
1264 *
1265 * In order to enable masterclock, the host clocksource must be TSC
1266 * and the vcpus need to have matched TSCs. When that happens,
1267 * perform request to enable masterclock.
1268 */
1269 if (ka->use_master_clock ||
1270 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1271 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1272
1273 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1274 atomic_read(&vcpu->kvm->online_vcpus),
1275 ka->use_master_clock, gtod->clock.vclock_mode);
1276 #endif
1277 }
1278
1279 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1280 {
1281 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1282 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1283 }
1284
1285 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1286 {
1287 struct kvm *kvm = vcpu->kvm;
1288 u64 offset, ns, elapsed;
1289 unsigned long flags;
1290 s64 usdiff;
1291 bool matched;
1292 bool already_matched;
1293 u64 data = msr->data;
1294
1295 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1296 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1297 ns = get_kernel_ns();
1298 elapsed = ns - kvm->arch.last_tsc_nsec;
1299
1300 if (vcpu->arch.virtual_tsc_khz) {
1301 int faulted = 0;
1302
1303 /* n.b - signed multiplication and division required */
1304 usdiff = data - kvm->arch.last_tsc_write;
1305 #ifdef CONFIG_X86_64
1306 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1307 #else
1308 /* do_div() only does unsigned */
1309 asm("1: idivl %[divisor]\n"
1310 "2: xor %%edx, %%edx\n"
1311 " movl $0, %[faulted]\n"
1312 "3:\n"
1313 ".section .fixup,\"ax\"\n"
1314 "4: movl $1, %[faulted]\n"
1315 " jmp 3b\n"
1316 ".previous\n"
1317
1318 _ASM_EXTABLE(1b, 4b)
1319
1320 : "=A"(usdiff), [faulted] "=r" (faulted)
1321 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1322
1323 #endif
1324 do_div(elapsed, 1000);
1325 usdiff -= elapsed;
1326 if (usdiff < 0)
1327 usdiff = -usdiff;
1328
1329 /* idivl overflow => difference is larger than USEC_PER_SEC */
1330 if (faulted)
1331 usdiff = USEC_PER_SEC;
1332 } else
1333 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1334
1335 /*
1336 * Special case: TSC write with a small delta (1 second) of virtual
1337 * cycle time against real time is interpreted as an attempt to
1338 * synchronize the CPU.
1339 *
1340 * For a reliable TSC, we can match TSC offsets, and for an unstable
1341 * TSC, we add elapsed time in this computation. We could let the
1342 * compensation code attempt to catch up if we fall behind, but
1343 * it's better to try to match offsets from the beginning.
1344 */
1345 if (usdiff < USEC_PER_SEC &&
1346 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1347 if (!check_tsc_unstable()) {
1348 offset = kvm->arch.cur_tsc_offset;
1349 pr_debug("kvm: matched tsc offset for %llu\n", data);
1350 } else {
1351 u64 delta = nsec_to_cycles(vcpu, elapsed);
1352 data += delta;
1353 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1354 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1355 }
1356 matched = true;
1357 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1358 } else {
1359 /*
1360 * We split periods of matched TSC writes into generations.
1361 * For each generation, we track the original measured
1362 * nanosecond time, offset, and write, so if TSCs are in
1363 * sync, we can match exact offset, and if not, we can match
1364 * exact software computation in compute_guest_tsc()
1365 *
1366 * These values are tracked in kvm->arch.cur_xxx variables.
1367 */
1368 kvm->arch.cur_tsc_generation++;
1369 kvm->arch.cur_tsc_nsec = ns;
1370 kvm->arch.cur_tsc_write = data;
1371 kvm->arch.cur_tsc_offset = offset;
1372 matched = false;
1373 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1374 kvm->arch.cur_tsc_generation, data);
1375 }
1376
1377 /*
1378 * We also track th most recent recorded KHZ, write and time to
1379 * allow the matching interval to be extended at each write.
1380 */
1381 kvm->arch.last_tsc_nsec = ns;
1382 kvm->arch.last_tsc_write = data;
1383 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1384
1385 vcpu->arch.last_guest_tsc = data;
1386
1387 /* Keep track of which generation this VCPU has synchronized to */
1388 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1389 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1390 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1391
1392 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1393 update_ia32_tsc_adjust_msr(vcpu, offset);
1394 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1395 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1396
1397 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1398 if (!matched) {
1399 kvm->arch.nr_vcpus_matched_tsc = 0;
1400 } else if (!already_matched) {
1401 kvm->arch.nr_vcpus_matched_tsc++;
1402 }
1403
1404 kvm_track_tsc_matching(vcpu);
1405 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1406 }
1407
1408 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1409
1410 #ifdef CONFIG_X86_64
1411
1412 static cycle_t read_tsc(void)
1413 {
1414 cycle_t ret;
1415 u64 last;
1416
1417 /*
1418 * Empirically, a fence (of type that depends on the CPU)
1419 * before rdtsc is enough to ensure that rdtsc is ordered
1420 * with respect to loads. The various CPU manuals are unclear
1421 * as to whether rdtsc can be reordered with later loads,
1422 * but no one has ever seen it happen.
1423 */
1424 rdtsc_barrier();
1425 ret = (cycle_t)vget_cycles();
1426
1427 last = pvclock_gtod_data.clock.cycle_last;
1428
1429 if (likely(ret >= last))
1430 return ret;
1431
1432 /*
1433 * GCC likes to generate cmov here, but this branch is extremely
1434 * predictable (it's just a funciton of time and the likely is
1435 * very likely) and there's a data dependence, so force GCC
1436 * to generate a branch instead. I don't barrier() because
1437 * we don't actually need a barrier, and if this function
1438 * ever gets inlined it will generate worse code.
1439 */
1440 asm volatile ("");
1441 return last;
1442 }
1443
1444 static inline u64 vgettsc(cycle_t *cycle_now)
1445 {
1446 long v;
1447 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1448
1449 *cycle_now = read_tsc();
1450
1451 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1452 return v * gtod->clock.mult;
1453 }
1454
1455 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1456 {
1457 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1458 unsigned long seq;
1459 int mode;
1460 u64 ns;
1461
1462 do {
1463 seq = read_seqcount_begin(&gtod->seq);
1464 mode = gtod->clock.vclock_mode;
1465 ns = gtod->nsec_base;
1466 ns += vgettsc(cycle_now);
1467 ns >>= gtod->clock.shift;
1468 ns += gtod->boot_ns;
1469 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1470 *t = ns;
1471
1472 return mode;
1473 }
1474
1475 /* returns true if host is using tsc clocksource */
1476 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1477 {
1478 /* checked again under seqlock below */
1479 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1480 return false;
1481
1482 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1483 }
1484 #endif
1485
1486 /*
1487 *
1488 * Assuming a stable TSC across physical CPUS, and a stable TSC
1489 * across virtual CPUs, the following condition is possible.
1490 * Each numbered line represents an event visible to both
1491 * CPUs at the next numbered event.
1492 *
1493 * "timespecX" represents host monotonic time. "tscX" represents
1494 * RDTSC value.
1495 *
1496 * VCPU0 on CPU0 | VCPU1 on CPU1
1497 *
1498 * 1. read timespec0,tsc0
1499 * 2. | timespec1 = timespec0 + N
1500 * | tsc1 = tsc0 + M
1501 * 3. transition to guest | transition to guest
1502 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1503 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1504 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1505 *
1506 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1507 *
1508 * - ret0 < ret1
1509 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1510 * ...
1511 * - 0 < N - M => M < N
1512 *
1513 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1514 * always the case (the difference between two distinct xtime instances
1515 * might be smaller then the difference between corresponding TSC reads,
1516 * when updating guest vcpus pvclock areas).
1517 *
1518 * To avoid that problem, do not allow visibility of distinct
1519 * system_timestamp/tsc_timestamp values simultaneously: use a master
1520 * copy of host monotonic time values. Update that master copy
1521 * in lockstep.
1522 *
1523 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1524 *
1525 */
1526
1527 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1528 {
1529 #ifdef CONFIG_X86_64
1530 struct kvm_arch *ka = &kvm->arch;
1531 int vclock_mode;
1532 bool host_tsc_clocksource, vcpus_matched;
1533
1534 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1535 atomic_read(&kvm->online_vcpus));
1536
1537 /*
1538 * If the host uses TSC clock, then passthrough TSC as stable
1539 * to the guest.
1540 */
1541 host_tsc_clocksource = kvm_get_time_and_clockread(
1542 &ka->master_kernel_ns,
1543 &ka->master_cycle_now);
1544
1545 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1546 && !backwards_tsc_observed
1547 && !ka->boot_vcpu_runs_old_kvmclock;
1548
1549 if (ka->use_master_clock)
1550 atomic_set(&kvm_guest_has_master_clock, 1);
1551
1552 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1553 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1554 vcpus_matched);
1555 #endif
1556 }
1557
1558 static void kvm_gen_update_masterclock(struct kvm *kvm)
1559 {
1560 #ifdef CONFIG_X86_64
1561 int i;
1562 struct kvm_vcpu *vcpu;
1563 struct kvm_arch *ka = &kvm->arch;
1564
1565 spin_lock(&ka->pvclock_gtod_sync_lock);
1566 kvm_make_mclock_inprogress_request(kvm);
1567 /* no guest entries from this point */
1568 pvclock_update_vm_gtod_copy(kvm);
1569
1570 kvm_for_each_vcpu(i, vcpu, kvm)
1571 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1572
1573 /* guest entries allowed */
1574 kvm_for_each_vcpu(i, vcpu, kvm)
1575 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1576
1577 spin_unlock(&ka->pvclock_gtod_sync_lock);
1578 #endif
1579 }
1580
1581 static int kvm_guest_time_update(struct kvm_vcpu *v)
1582 {
1583 unsigned long flags, this_tsc_khz;
1584 struct kvm_vcpu_arch *vcpu = &v->arch;
1585 struct kvm_arch *ka = &v->kvm->arch;
1586 s64 kernel_ns;
1587 u64 tsc_timestamp, host_tsc;
1588 struct pvclock_vcpu_time_info guest_hv_clock;
1589 u8 pvclock_flags;
1590 bool use_master_clock;
1591
1592 kernel_ns = 0;
1593 host_tsc = 0;
1594
1595 /*
1596 * If the host uses TSC clock, then passthrough TSC as stable
1597 * to the guest.
1598 */
1599 spin_lock(&ka->pvclock_gtod_sync_lock);
1600 use_master_clock = ka->use_master_clock;
1601 if (use_master_clock) {
1602 host_tsc = ka->master_cycle_now;
1603 kernel_ns = ka->master_kernel_ns;
1604 }
1605 spin_unlock(&ka->pvclock_gtod_sync_lock);
1606
1607 /* Keep irq disabled to prevent changes to the clock */
1608 local_irq_save(flags);
1609 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1610 if (unlikely(this_tsc_khz == 0)) {
1611 local_irq_restore(flags);
1612 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1613 return 1;
1614 }
1615 if (!use_master_clock) {
1616 host_tsc = native_read_tsc();
1617 kernel_ns = get_kernel_ns();
1618 }
1619
1620 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1621
1622 /*
1623 * We may have to catch up the TSC to match elapsed wall clock
1624 * time for two reasons, even if kvmclock is used.
1625 * 1) CPU could have been running below the maximum TSC rate
1626 * 2) Broken TSC compensation resets the base at each VCPU
1627 * entry to avoid unknown leaps of TSC even when running
1628 * again on the same CPU. This may cause apparent elapsed
1629 * time to disappear, and the guest to stand still or run
1630 * very slowly.
1631 */
1632 if (vcpu->tsc_catchup) {
1633 u64 tsc = compute_guest_tsc(v, kernel_ns);
1634 if (tsc > tsc_timestamp) {
1635 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1636 tsc_timestamp = tsc;
1637 }
1638 }
1639
1640 local_irq_restore(flags);
1641
1642 if (!vcpu->pv_time_enabled)
1643 return 0;
1644
1645 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1646 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1647 &vcpu->hv_clock.tsc_shift,
1648 &vcpu->hv_clock.tsc_to_system_mul);
1649 vcpu->hw_tsc_khz = this_tsc_khz;
1650 }
1651
1652 /* With all the info we got, fill in the values */
1653 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1654 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1655 vcpu->last_guest_tsc = tsc_timestamp;
1656
1657 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1658 &guest_hv_clock, sizeof(guest_hv_clock))))
1659 return 0;
1660
1661 /*
1662 * The interface expects us to write an even number signaling that the
1663 * update is finished. Since the guest won't see the intermediate
1664 * state, we just increase by 2 at the end.
1665 */
1666 vcpu->hv_clock.version = guest_hv_clock.version + 2;
1667
1668 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1669 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1670
1671 if (vcpu->pvclock_set_guest_stopped_request) {
1672 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1673 vcpu->pvclock_set_guest_stopped_request = false;
1674 }
1675
1676 /* If the host uses TSC clocksource, then it is stable */
1677 if (use_master_clock)
1678 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1679
1680 vcpu->hv_clock.flags = pvclock_flags;
1681
1682 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1683
1684 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1685 &vcpu->hv_clock,
1686 sizeof(vcpu->hv_clock));
1687 return 0;
1688 }
1689
1690 /*
1691 * kvmclock updates which are isolated to a given vcpu, such as
1692 * vcpu->cpu migration, should not allow system_timestamp from
1693 * the rest of the vcpus to remain static. Otherwise ntp frequency
1694 * correction applies to one vcpu's system_timestamp but not
1695 * the others.
1696 *
1697 * So in those cases, request a kvmclock update for all vcpus.
1698 * We need to rate-limit these requests though, as they can
1699 * considerably slow guests that have a large number of vcpus.
1700 * The time for a remote vcpu to update its kvmclock is bound
1701 * by the delay we use to rate-limit the updates.
1702 */
1703
1704 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1705
1706 static void kvmclock_update_fn(struct work_struct *work)
1707 {
1708 int i;
1709 struct delayed_work *dwork = to_delayed_work(work);
1710 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1711 kvmclock_update_work);
1712 struct kvm *kvm = container_of(ka, struct kvm, arch);
1713 struct kvm_vcpu *vcpu;
1714
1715 kvm_for_each_vcpu(i, vcpu, kvm) {
1716 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1717 kvm_vcpu_kick(vcpu);
1718 }
1719 }
1720
1721 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1722 {
1723 struct kvm *kvm = v->kvm;
1724
1725 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1726 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1727 KVMCLOCK_UPDATE_DELAY);
1728 }
1729
1730 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1731
1732 static void kvmclock_sync_fn(struct work_struct *work)
1733 {
1734 struct delayed_work *dwork = to_delayed_work(work);
1735 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1736 kvmclock_sync_work);
1737 struct kvm *kvm = container_of(ka, struct kvm, arch);
1738
1739 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1740 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1741 KVMCLOCK_SYNC_PERIOD);
1742 }
1743
1744 static bool msr_mtrr_valid(unsigned msr)
1745 {
1746 switch (msr) {
1747 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1748 case MSR_MTRRfix64K_00000:
1749 case MSR_MTRRfix16K_80000:
1750 case MSR_MTRRfix16K_A0000:
1751 case MSR_MTRRfix4K_C0000:
1752 case MSR_MTRRfix4K_C8000:
1753 case MSR_MTRRfix4K_D0000:
1754 case MSR_MTRRfix4K_D8000:
1755 case MSR_MTRRfix4K_E0000:
1756 case MSR_MTRRfix4K_E8000:
1757 case MSR_MTRRfix4K_F0000:
1758 case MSR_MTRRfix4K_F8000:
1759 case MSR_MTRRdefType:
1760 case MSR_IA32_CR_PAT:
1761 return true;
1762 case 0x2f8:
1763 return true;
1764 }
1765 return false;
1766 }
1767
1768 static bool valid_pat_type(unsigned t)
1769 {
1770 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1771 }
1772
1773 static bool valid_mtrr_type(unsigned t)
1774 {
1775 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1776 }
1777
1778 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1779 {
1780 int i;
1781 u64 mask;
1782
1783 if (!msr_mtrr_valid(msr))
1784 return false;
1785
1786 if (msr == MSR_IA32_CR_PAT) {
1787 for (i = 0; i < 8; i++)
1788 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1789 return false;
1790 return true;
1791 } else if (msr == MSR_MTRRdefType) {
1792 if (data & ~0xcff)
1793 return false;
1794 return valid_mtrr_type(data & 0xff);
1795 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1796 for (i = 0; i < 8 ; i++)
1797 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1798 return false;
1799 return true;
1800 }
1801
1802 /* variable MTRRs */
1803 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1804
1805 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1806 if ((msr & 1) == 0) {
1807 /* MTRR base */
1808 if (!valid_mtrr_type(data & 0xff))
1809 return false;
1810 mask |= 0xf00;
1811 } else
1812 /* MTRR mask */
1813 mask |= 0x7ff;
1814 if (data & mask) {
1815 kvm_inject_gp(vcpu, 0);
1816 return false;
1817 }
1818
1819 return true;
1820 }
1821 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1822
1823 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1824 {
1825 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1826
1827 if (!kvm_mtrr_valid(vcpu, msr, data))
1828 return 1;
1829
1830 if (msr == MSR_MTRRdefType) {
1831 vcpu->arch.mtrr_state.def_type = data;
1832 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1833 } else if (msr == MSR_MTRRfix64K_00000)
1834 p[0] = data;
1835 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1836 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1837 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1838 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1839 else if (msr == MSR_IA32_CR_PAT)
1840 vcpu->arch.pat = data;
1841 else { /* Variable MTRRs */
1842 int idx, is_mtrr_mask;
1843 u64 *pt;
1844
1845 idx = (msr - 0x200) / 2;
1846 is_mtrr_mask = msr - 0x200 - 2 * idx;
1847 if (!is_mtrr_mask)
1848 pt =
1849 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1850 else
1851 pt =
1852 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1853 *pt = data;
1854 }
1855
1856 kvm_mmu_reset_context(vcpu);
1857 return 0;
1858 }
1859
1860 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1861 {
1862 u64 mcg_cap = vcpu->arch.mcg_cap;
1863 unsigned bank_num = mcg_cap & 0xff;
1864
1865 switch (msr) {
1866 case MSR_IA32_MCG_STATUS:
1867 vcpu->arch.mcg_status = data;
1868 break;
1869 case MSR_IA32_MCG_CTL:
1870 if (!(mcg_cap & MCG_CTL_P))
1871 return 1;
1872 if (data != 0 && data != ~(u64)0)
1873 return -1;
1874 vcpu->arch.mcg_ctl = data;
1875 break;
1876 default:
1877 if (msr >= MSR_IA32_MC0_CTL &&
1878 msr < MSR_IA32_MCx_CTL(bank_num)) {
1879 u32 offset = msr - MSR_IA32_MC0_CTL;
1880 /* only 0 or all 1s can be written to IA32_MCi_CTL
1881 * some Linux kernels though clear bit 10 in bank 4 to
1882 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1883 * this to avoid an uncatched #GP in the guest
1884 */
1885 if ((offset & 0x3) == 0 &&
1886 data != 0 && (data | (1 << 10)) != ~(u64)0)
1887 return -1;
1888 vcpu->arch.mce_banks[offset] = data;
1889 break;
1890 }
1891 return 1;
1892 }
1893 return 0;
1894 }
1895
1896 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1897 {
1898 struct kvm *kvm = vcpu->kvm;
1899 int lm = is_long_mode(vcpu);
1900 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1901 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1902 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1903 : kvm->arch.xen_hvm_config.blob_size_32;
1904 u32 page_num = data & ~PAGE_MASK;
1905 u64 page_addr = data & PAGE_MASK;
1906 u8 *page;
1907 int r;
1908
1909 r = -E2BIG;
1910 if (page_num >= blob_size)
1911 goto out;
1912 r = -ENOMEM;
1913 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1914 if (IS_ERR(page)) {
1915 r = PTR_ERR(page);
1916 goto out;
1917 }
1918 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1919 goto out_free;
1920 r = 0;
1921 out_free:
1922 kfree(page);
1923 out:
1924 return r;
1925 }
1926
1927 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1928 {
1929 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1930 }
1931
1932 static bool kvm_hv_msr_partition_wide(u32 msr)
1933 {
1934 bool r = false;
1935 switch (msr) {
1936 case HV_X64_MSR_GUEST_OS_ID:
1937 case HV_X64_MSR_HYPERCALL:
1938 case HV_X64_MSR_REFERENCE_TSC:
1939 case HV_X64_MSR_TIME_REF_COUNT:
1940 r = true;
1941 break;
1942 }
1943
1944 return r;
1945 }
1946
1947 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1948 {
1949 struct kvm *kvm = vcpu->kvm;
1950
1951 switch (msr) {
1952 case HV_X64_MSR_GUEST_OS_ID:
1953 kvm->arch.hv_guest_os_id = data;
1954 /* setting guest os id to zero disables hypercall page */
1955 if (!kvm->arch.hv_guest_os_id)
1956 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1957 break;
1958 case HV_X64_MSR_HYPERCALL: {
1959 u64 gfn;
1960 unsigned long addr;
1961 u8 instructions[4];
1962
1963 /* if guest os id is not set hypercall should remain disabled */
1964 if (!kvm->arch.hv_guest_os_id)
1965 break;
1966 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1967 kvm->arch.hv_hypercall = data;
1968 break;
1969 }
1970 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1971 addr = gfn_to_hva(kvm, gfn);
1972 if (kvm_is_error_hva(addr))
1973 return 1;
1974 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1975 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1976 if (__copy_to_user((void __user *)addr, instructions, 4))
1977 return 1;
1978 kvm->arch.hv_hypercall = data;
1979 mark_page_dirty(kvm, gfn);
1980 break;
1981 }
1982 case HV_X64_MSR_REFERENCE_TSC: {
1983 u64 gfn;
1984 HV_REFERENCE_TSC_PAGE tsc_ref;
1985 memset(&tsc_ref, 0, sizeof(tsc_ref));
1986 kvm->arch.hv_tsc_page = data;
1987 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1988 break;
1989 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1990 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1991 &tsc_ref, sizeof(tsc_ref)))
1992 return 1;
1993 mark_page_dirty(kvm, gfn);
1994 break;
1995 }
1996 default:
1997 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1998 "data 0x%llx\n", msr, data);
1999 return 1;
2000 }
2001 return 0;
2002 }
2003
2004 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2005 {
2006 switch (msr) {
2007 case HV_X64_MSR_APIC_ASSIST_PAGE: {
2008 u64 gfn;
2009 unsigned long addr;
2010
2011 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2012 vcpu->arch.hv_vapic = data;
2013 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2014 return 1;
2015 break;
2016 }
2017 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2018 addr = gfn_to_hva(vcpu->kvm, gfn);
2019 if (kvm_is_error_hva(addr))
2020 return 1;
2021 if (__clear_user((void __user *)addr, PAGE_SIZE))
2022 return 1;
2023 vcpu->arch.hv_vapic = data;
2024 mark_page_dirty(vcpu->kvm, gfn);
2025 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2026 return 1;
2027 break;
2028 }
2029 case HV_X64_MSR_EOI:
2030 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2031 case HV_X64_MSR_ICR:
2032 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2033 case HV_X64_MSR_TPR:
2034 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2035 default:
2036 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2037 "data 0x%llx\n", msr, data);
2038 return 1;
2039 }
2040
2041 return 0;
2042 }
2043
2044 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2045 {
2046 gpa_t gpa = data & ~0x3f;
2047
2048 /* Bits 2:5 are reserved, Should be zero */
2049 if (data & 0x3c)
2050 return 1;
2051
2052 vcpu->arch.apf.msr_val = data;
2053
2054 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2055 kvm_clear_async_pf_completion_queue(vcpu);
2056 kvm_async_pf_hash_reset(vcpu);
2057 return 0;
2058 }
2059
2060 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2061 sizeof(u32)))
2062 return 1;
2063
2064 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2065 kvm_async_pf_wakeup_all(vcpu);
2066 return 0;
2067 }
2068
2069 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2070 {
2071 vcpu->arch.pv_time_enabled = false;
2072 }
2073
2074 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2075 {
2076 u64 delta;
2077
2078 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2079 return;
2080
2081 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2082 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2083 vcpu->arch.st.accum_steal = delta;
2084 }
2085
2086 static void record_steal_time(struct kvm_vcpu *vcpu)
2087 {
2088 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2089 return;
2090
2091 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2092 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2093 return;
2094
2095 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2096 vcpu->arch.st.steal.version += 2;
2097 vcpu->arch.st.accum_steal = 0;
2098
2099 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2100 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2101 }
2102
2103 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2104 {
2105 bool pr = false;
2106 u32 msr = msr_info->index;
2107 u64 data = msr_info->data;
2108
2109 switch (msr) {
2110 case MSR_AMD64_NB_CFG:
2111 case MSR_IA32_UCODE_REV:
2112 case MSR_IA32_UCODE_WRITE:
2113 case MSR_VM_HSAVE_PA:
2114 case MSR_AMD64_PATCH_LOADER:
2115 case MSR_AMD64_BU_CFG2:
2116 break;
2117
2118 case MSR_EFER:
2119 return set_efer(vcpu, data);
2120 case MSR_K7_HWCR:
2121 data &= ~(u64)0x40; /* ignore flush filter disable */
2122 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2123 data &= ~(u64)0x8; /* ignore TLB cache disable */
2124 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2125 if (data != 0) {
2126 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2127 data);
2128 return 1;
2129 }
2130 break;
2131 case MSR_FAM10H_MMIO_CONF_BASE:
2132 if (data != 0) {
2133 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2134 "0x%llx\n", data);
2135 return 1;
2136 }
2137 break;
2138 case MSR_IA32_DEBUGCTLMSR:
2139 if (!data) {
2140 /* We support the non-activated case already */
2141 break;
2142 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2143 /* Values other than LBR and BTF are vendor-specific,
2144 thus reserved and should throw a #GP */
2145 return 1;
2146 }
2147 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2148 __func__, data);
2149 break;
2150 case 0x200 ... 0x2ff:
2151 return set_msr_mtrr(vcpu, msr, data);
2152 case MSR_IA32_APICBASE:
2153 return kvm_set_apic_base(vcpu, msr_info);
2154 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2155 return kvm_x2apic_msr_write(vcpu, msr, data);
2156 case MSR_IA32_TSCDEADLINE:
2157 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2158 break;
2159 case MSR_IA32_TSC_ADJUST:
2160 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2161 if (!msr_info->host_initiated) {
2162 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2163 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2164 }
2165 vcpu->arch.ia32_tsc_adjust_msr = data;
2166 }
2167 break;
2168 case MSR_IA32_MISC_ENABLE:
2169 vcpu->arch.ia32_misc_enable_msr = data;
2170 break;
2171 case MSR_KVM_WALL_CLOCK_NEW:
2172 case MSR_KVM_WALL_CLOCK:
2173 vcpu->kvm->arch.wall_clock = data;
2174 kvm_write_wall_clock(vcpu->kvm, data);
2175 break;
2176 case MSR_KVM_SYSTEM_TIME_NEW:
2177 case MSR_KVM_SYSTEM_TIME: {
2178 u64 gpa_offset;
2179 struct kvm_arch *ka = &vcpu->kvm->arch;
2180
2181 kvmclock_reset(vcpu);
2182
2183 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2184 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2185
2186 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2187 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2188 &vcpu->requests);
2189
2190 ka->boot_vcpu_runs_old_kvmclock = tmp;
2191 }
2192
2193 vcpu->arch.time = data;
2194 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2195
2196 /* we verify if the enable bit is set... */
2197 if (!(data & 1))
2198 break;
2199
2200 gpa_offset = data & ~(PAGE_MASK | 1);
2201
2202 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2203 &vcpu->arch.pv_time, data & ~1ULL,
2204 sizeof(struct pvclock_vcpu_time_info)))
2205 vcpu->arch.pv_time_enabled = false;
2206 else
2207 vcpu->arch.pv_time_enabled = true;
2208
2209 break;
2210 }
2211 case MSR_KVM_ASYNC_PF_EN:
2212 if (kvm_pv_enable_async_pf(vcpu, data))
2213 return 1;
2214 break;
2215 case MSR_KVM_STEAL_TIME:
2216
2217 if (unlikely(!sched_info_on()))
2218 return 1;
2219
2220 if (data & KVM_STEAL_RESERVED_MASK)
2221 return 1;
2222
2223 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2224 data & KVM_STEAL_VALID_BITS,
2225 sizeof(struct kvm_steal_time)))
2226 return 1;
2227
2228 vcpu->arch.st.msr_val = data;
2229
2230 if (!(data & KVM_MSR_ENABLED))
2231 break;
2232
2233 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2234
2235 preempt_disable();
2236 accumulate_steal_time(vcpu);
2237 preempt_enable();
2238
2239 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2240
2241 break;
2242 case MSR_KVM_PV_EOI_EN:
2243 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2244 return 1;
2245 break;
2246
2247 case MSR_IA32_MCG_CTL:
2248 case MSR_IA32_MCG_STATUS:
2249 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2250 return set_msr_mce(vcpu, msr, data);
2251
2252 /* Performance counters are not protected by a CPUID bit,
2253 * so we should check all of them in the generic path for the sake of
2254 * cross vendor migration.
2255 * Writing a zero into the event select MSRs disables them,
2256 * which we perfectly emulate ;-). Any other value should be at least
2257 * reported, some guests depend on them.
2258 */
2259 case MSR_K7_EVNTSEL0:
2260 case MSR_K7_EVNTSEL1:
2261 case MSR_K7_EVNTSEL2:
2262 case MSR_K7_EVNTSEL3:
2263 if (data != 0)
2264 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2265 "0x%x data 0x%llx\n", msr, data);
2266 break;
2267 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2268 * so we ignore writes to make it happy.
2269 */
2270 case MSR_K7_PERFCTR0:
2271 case MSR_K7_PERFCTR1:
2272 case MSR_K7_PERFCTR2:
2273 case MSR_K7_PERFCTR3:
2274 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2275 "0x%x data 0x%llx\n", msr, data);
2276 break;
2277 case MSR_P6_PERFCTR0:
2278 case MSR_P6_PERFCTR1:
2279 pr = true;
2280 case MSR_P6_EVNTSEL0:
2281 case MSR_P6_EVNTSEL1:
2282 if (kvm_pmu_msr(vcpu, msr))
2283 return kvm_pmu_set_msr(vcpu, msr_info);
2284
2285 if (pr || data != 0)
2286 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2287 "0x%x data 0x%llx\n", msr, data);
2288 break;
2289 case MSR_K7_CLK_CTL:
2290 /*
2291 * Ignore all writes to this no longer documented MSR.
2292 * Writes are only relevant for old K7 processors,
2293 * all pre-dating SVM, but a recommended workaround from
2294 * AMD for these chips. It is possible to specify the
2295 * affected processor models on the command line, hence
2296 * the need to ignore the workaround.
2297 */
2298 break;
2299 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2300 if (kvm_hv_msr_partition_wide(msr)) {
2301 int r;
2302 mutex_lock(&vcpu->kvm->lock);
2303 r = set_msr_hyperv_pw(vcpu, msr, data);
2304 mutex_unlock(&vcpu->kvm->lock);
2305 return r;
2306 } else
2307 return set_msr_hyperv(vcpu, msr, data);
2308 break;
2309 case MSR_IA32_BBL_CR_CTL3:
2310 /* Drop writes to this legacy MSR -- see rdmsr
2311 * counterpart for further detail.
2312 */
2313 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2314 break;
2315 case MSR_AMD64_OSVW_ID_LENGTH:
2316 if (!guest_cpuid_has_osvw(vcpu))
2317 return 1;
2318 vcpu->arch.osvw.length = data;
2319 break;
2320 case MSR_AMD64_OSVW_STATUS:
2321 if (!guest_cpuid_has_osvw(vcpu))
2322 return 1;
2323 vcpu->arch.osvw.status = data;
2324 break;
2325 default:
2326 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2327 return xen_hvm_config(vcpu, data);
2328 if (kvm_pmu_msr(vcpu, msr))
2329 return kvm_pmu_set_msr(vcpu, msr_info);
2330 if (!ignore_msrs) {
2331 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2332 msr, data);
2333 return 1;
2334 } else {
2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2336 msr, data);
2337 break;
2338 }
2339 }
2340 return 0;
2341 }
2342 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2343
2344
2345 /*
2346 * Reads an msr value (of 'msr_index') into 'pdata'.
2347 * Returns 0 on success, non-0 otherwise.
2348 * Assumes vcpu_load() was already called.
2349 */
2350 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2351 {
2352 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2353 }
2354 EXPORT_SYMBOL_GPL(kvm_get_msr);
2355
2356 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2357 {
2358 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2359
2360 if (!msr_mtrr_valid(msr))
2361 return 1;
2362
2363 if (msr == MSR_MTRRdefType)
2364 *pdata = vcpu->arch.mtrr_state.def_type +
2365 (vcpu->arch.mtrr_state.enabled << 10);
2366 else if (msr == MSR_MTRRfix64K_00000)
2367 *pdata = p[0];
2368 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2369 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2370 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2371 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2372 else if (msr == MSR_IA32_CR_PAT)
2373 *pdata = vcpu->arch.pat;
2374 else { /* Variable MTRRs */
2375 int idx, is_mtrr_mask;
2376 u64 *pt;
2377
2378 idx = (msr - 0x200) / 2;
2379 is_mtrr_mask = msr - 0x200 - 2 * idx;
2380 if (!is_mtrr_mask)
2381 pt =
2382 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2383 else
2384 pt =
2385 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2386 *pdata = *pt;
2387 }
2388
2389 return 0;
2390 }
2391
2392 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2393 {
2394 u64 data;
2395 u64 mcg_cap = vcpu->arch.mcg_cap;
2396 unsigned bank_num = mcg_cap & 0xff;
2397
2398 switch (msr) {
2399 case MSR_IA32_P5_MC_ADDR:
2400 case MSR_IA32_P5_MC_TYPE:
2401 data = 0;
2402 break;
2403 case MSR_IA32_MCG_CAP:
2404 data = vcpu->arch.mcg_cap;
2405 break;
2406 case MSR_IA32_MCG_CTL:
2407 if (!(mcg_cap & MCG_CTL_P))
2408 return 1;
2409 data = vcpu->arch.mcg_ctl;
2410 break;
2411 case MSR_IA32_MCG_STATUS:
2412 data = vcpu->arch.mcg_status;
2413 break;
2414 default:
2415 if (msr >= MSR_IA32_MC0_CTL &&
2416 msr < MSR_IA32_MCx_CTL(bank_num)) {
2417 u32 offset = msr - MSR_IA32_MC0_CTL;
2418 data = vcpu->arch.mce_banks[offset];
2419 break;
2420 }
2421 return 1;
2422 }
2423 *pdata = data;
2424 return 0;
2425 }
2426
2427 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2428 {
2429 u64 data = 0;
2430 struct kvm *kvm = vcpu->kvm;
2431
2432 switch (msr) {
2433 case HV_X64_MSR_GUEST_OS_ID:
2434 data = kvm->arch.hv_guest_os_id;
2435 break;
2436 case HV_X64_MSR_HYPERCALL:
2437 data = kvm->arch.hv_hypercall;
2438 break;
2439 case HV_X64_MSR_TIME_REF_COUNT: {
2440 data =
2441 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2442 break;
2443 }
2444 case HV_X64_MSR_REFERENCE_TSC:
2445 data = kvm->arch.hv_tsc_page;
2446 break;
2447 default:
2448 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2449 return 1;
2450 }
2451
2452 *pdata = data;
2453 return 0;
2454 }
2455
2456 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2457 {
2458 u64 data = 0;
2459
2460 switch (msr) {
2461 case HV_X64_MSR_VP_INDEX: {
2462 int r;
2463 struct kvm_vcpu *v;
2464 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2465 if (v == vcpu) {
2466 data = r;
2467 break;
2468 }
2469 }
2470 break;
2471 }
2472 case HV_X64_MSR_EOI:
2473 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2474 case HV_X64_MSR_ICR:
2475 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2476 case HV_X64_MSR_TPR:
2477 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2478 case HV_X64_MSR_APIC_ASSIST_PAGE:
2479 data = vcpu->arch.hv_vapic;
2480 break;
2481 default:
2482 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2483 return 1;
2484 }
2485 *pdata = data;
2486 return 0;
2487 }
2488
2489 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2490 {
2491 u64 data;
2492
2493 switch (msr) {
2494 case MSR_IA32_PLATFORM_ID:
2495 case MSR_IA32_EBL_CR_POWERON:
2496 case MSR_IA32_DEBUGCTLMSR:
2497 case MSR_IA32_LASTBRANCHFROMIP:
2498 case MSR_IA32_LASTBRANCHTOIP:
2499 case MSR_IA32_LASTINTFROMIP:
2500 case MSR_IA32_LASTINTTOIP:
2501 case MSR_K8_SYSCFG:
2502 case MSR_K7_HWCR:
2503 case MSR_VM_HSAVE_PA:
2504 case MSR_K7_EVNTSEL0:
2505 case MSR_K7_EVNTSEL1:
2506 case MSR_K7_EVNTSEL2:
2507 case MSR_K7_EVNTSEL3:
2508 case MSR_K7_PERFCTR0:
2509 case MSR_K7_PERFCTR1:
2510 case MSR_K7_PERFCTR2:
2511 case MSR_K7_PERFCTR3:
2512 case MSR_K8_INT_PENDING_MSG:
2513 case MSR_AMD64_NB_CFG:
2514 case MSR_FAM10H_MMIO_CONF_BASE:
2515 case MSR_AMD64_BU_CFG2:
2516 data = 0;
2517 break;
2518 case MSR_P6_PERFCTR0:
2519 case MSR_P6_PERFCTR1:
2520 case MSR_P6_EVNTSEL0:
2521 case MSR_P6_EVNTSEL1:
2522 if (kvm_pmu_msr(vcpu, msr))
2523 return kvm_pmu_get_msr(vcpu, msr, pdata);
2524 data = 0;
2525 break;
2526 case MSR_IA32_UCODE_REV:
2527 data = 0x100000000ULL;
2528 break;
2529 case MSR_MTRRcap:
2530 data = 0x500 | KVM_NR_VAR_MTRR;
2531 break;
2532 case 0x200 ... 0x2ff:
2533 return get_msr_mtrr(vcpu, msr, pdata);
2534 case 0xcd: /* fsb frequency */
2535 data = 3;
2536 break;
2537 /*
2538 * MSR_EBC_FREQUENCY_ID
2539 * Conservative value valid for even the basic CPU models.
2540 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2541 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2542 * and 266MHz for model 3, or 4. Set Core Clock
2543 * Frequency to System Bus Frequency Ratio to 1 (bits
2544 * 31:24) even though these are only valid for CPU
2545 * models > 2, however guests may end up dividing or
2546 * multiplying by zero otherwise.
2547 */
2548 case MSR_EBC_FREQUENCY_ID:
2549 data = 1 << 24;
2550 break;
2551 case MSR_IA32_APICBASE:
2552 data = kvm_get_apic_base(vcpu);
2553 break;
2554 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2555 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2556 break;
2557 case MSR_IA32_TSCDEADLINE:
2558 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2559 break;
2560 case MSR_IA32_TSC_ADJUST:
2561 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2562 break;
2563 case MSR_IA32_MISC_ENABLE:
2564 data = vcpu->arch.ia32_misc_enable_msr;
2565 break;
2566 case MSR_IA32_PERF_STATUS:
2567 /* TSC increment by tick */
2568 data = 1000ULL;
2569 /* CPU multiplier */
2570 data |= (((uint64_t)4ULL) << 40);
2571 break;
2572 case MSR_EFER:
2573 data = vcpu->arch.efer;
2574 break;
2575 case MSR_KVM_WALL_CLOCK:
2576 case MSR_KVM_WALL_CLOCK_NEW:
2577 data = vcpu->kvm->arch.wall_clock;
2578 break;
2579 case MSR_KVM_SYSTEM_TIME:
2580 case MSR_KVM_SYSTEM_TIME_NEW:
2581 data = vcpu->arch.time;
2582 break;
2583 case MSR_KVM_ASYNC_PF_EN:
2584 data = vcpu->arch.apf.msr_val;
2585 break;
2586 case MSR_KVM_STEAL_TIME:
2587 data = vcpu->arch.st.msr_val;
2588 break;
2589 case MSR_KVM_PV_EOI_EN:
2590 data = vcpu->arch.pv_eoi.msr_val;
2591 break;
2592 case MSR_IA32_P5_MC_ADDR:
2593 case MSR_IA32_P5_MC_TYPE:
2594 case MSR_IA32_MCG_CAP:
2595 case MSR_IA32_MCG_CTL:
2596 case MSR_IA32_MCG_STATUS:
2597 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2598 return get_msr_mce(vcpu, msr, pdata);
2599 case MSR_K7_CLK_CTL:
2600 /*
2601 * Provide expected ramp-up count for K7. All other
2602 * are set to zero, indicating minimum divisors for
2603 * every field.
2604 *
2605 * This prevents guest kernels on AMD host with CPU
2606 * type 6, model 8 and higher from exploding due to
2607 * the rdmsr failing.
2608 */
2609 data = 0x20000000;
2610 break;
2611 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2612 if (kvm_hv_msr_partition_wide(msr)) {
2613 int r;
2614 mutex_lock(&vcpu->kvm->lock);
2615 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2616 mutex_unlock(&vcpu->kvm->lock);
2617 return r;
2618 } else
2619 return get_msr_hyperv(vcpu, msr, pdata);
2620 break;
2621 case MSR_IA32_BBL_CR_CTL3:
2622 /* This legacy MSR exists but isn't fully documented in current
2623 * silicon. It is however accessed by winxp in very narrow
2624 * scenarios where it sets bit #19, itself documented as
2625 * a "reserved" bit. Best effort attempt to source coherent
2626 * read data here should the balance of the register be
2627 * interpreted by the guest:
2628 *
2629 * L2 cache control register 3: 64GB range, 256KB size,
2630 * enabled, latency 0x1, configured
2631 */
2632 data = 0xbe702111;
2633 break;
2634 case MSR_AMD64_OSVW_ID_LENGTH:
2635 if (!guest_cpuid_has_osvw(vcpu))
2636 return 1;
2637 data = vcpu->arch.osvw.length;
2638 break;
2639 case MSR_AMD64_OSVW_STATUS:
2640 if (!guest_cpuid_has_osvw(vcpu))
2641 return 1;
2642 data = vcpu->arch.osvw.status;
2643 break;
2644 default:
2645 if (kvm_pmu_msr(vcpu, msr))
2646 return kvm_pmu_get_msr(vcpu, msr, pdata);
2647 if (!ignore_msrs) {
2648 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2649 return 1;
2650 } else {
2651 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2652 data = 0;
2653 }
2654 break;
2655 }
2656 *pdata = data;
2657 return 0;
2658 }
2659 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2660
2661 /*
2662 * Read or write a bunch of msrs. All parameters are kernel addresses.
2663 *
2664 * @return number of msrs set successfully.
2665 */
2666 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2667 struct kvm_msr_entry *entries,
2668 int (*do_msr)(struct kvm_vcpu *vcpu,
2669 unsigned index, u64 *data))
2670 {
2671 int i, idx;
2672
2673 idx = srcu_read_lock(&vcpu->kvm->srcu);
2674 for (i = 0; i < msrs->nmsrs; ++i)
2675 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2676 break;
2677 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2678
2679 return i;
2680 }
2681
2682 /*
2683 * Read or write a bunch of msrs. Parameters are user addresses.
2684 *
2685 * @return number of msrs set successfully.
2686 */
2687 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2688 int (*do_msr)(struct kvm_vcpu *vcpu,
2689 unsigned index, u64 *data),
2690 int writeback)
2691 {
2692 struct kvm_msrs msrs;
2693 struct kvm_msr_entry *entries;
2694 int r, n;
2695 unsigned size;
2696
2697 r = -EFAULT;
2698 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2699 goto out;
2700
2701 r = -E2BIG;
2702 if (msrs.nmsrs >= MAX_IO_MSRS)
2703 goto out;
2704
2705 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2706 entries = memdup_user(user_msrs->entries, size);
2707 if (IS_ERR(entries)) {
2708 r = PTR_ERR(entries);
2709 goto out;
2710 }
2711
2712 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2713 if (r < 0)
2714 goto out_free;
2715
2716 r = -EFAULT;
2717 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2718 goto out_free;
2719
2720 r = n;
2721
2722 out_free:
2723 kfree(entries);
2724 out:
2725 return r;
2726 }
2727
2728 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2729 {
2730 int r;
2731
2732 switch (ext) {
2733 case KVM_CAP_IRQCHIP:
2734 case KVM_CAP_HLT:
2735 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2736 case KVM_CAP_SET_TSS_ADDR:
2737 case KVM_CAP_EXT_CPUID:
2738 case KVM_CAP_EXT_EMUL_CPUID:
2739 case KVM_CAP_CLOCKSOURCE:
2740 case KVM_CAP_PIT:
2741 case KVM_CAP_NOP_IO_DELAY:
2742 case KVM_CAP_MP_STATE:
2743 case KVM_CAP_SYNC_MMU:
2744 case KVM_CAP_USER_NMI:
2745 case KVM_CAP_REINJECT_CONTROL:
2746 case KVM_CAP_IRQ_INJECT_STATUS:
2747 case KVM_CAP_IRQFD:
2748 case KVM_CAP_IOEVENTFD:
2749 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2750 case KVM_CAP_PIT2:
2751 case KVM_CAP_PIT_STATE2:
2752 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2753 case KVM_CAP_XEN_HVM:
2754 case KVM_CAP_ADJUST_CLOCK:
2755 case KVM_CAP_VCPU_EVENTS:
2756 case KVM_CAP_HYPERV:
2757 case KVM_CAP_HYPERV_VAPIC:
2758 case KVM_CAP_HYPERV_SPIN:
2759 case KVM_CAP_PCI_SEGMENT:
2760 case KVM_CAP_DEBUGREGS:
2761 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2762 case KVM_CAP_XSAVE:
2763 case KVM_CAP_ASYNC_PF:
2764 case KVM_CAP_GET_TSC_KHZ:
2765 case KVM_CAP_KVMCLOCK_CTRL:
2766 case KVM_CAP_READONLY_MEM:
2767 case KVM_CAP_HYPERV_TIME:
2768 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2769 case KVM_CAP_TSC_DEADLINE_TIMER:
2770 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2771 case KVM_CAP_ASSIGN_DEV_IRQ:
2772 case KVM_CAP_PCI_2_3:
2773 #endif
2774 r = 1;
2775 break;
2776 case KVM_CAP_COALESCED_MMIO:
2777 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2778 break;
2779 case KVM_CAP_VAPIC:
2780 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2781 break;
2782 case KVM_CAP_NR_VCPUS:
2783 r = KVM_SOFT_MAX_VCPUS;
2784 break;
2785 case KVM_CAP_MAX_VCPUS:
2786 r = KVM_MAX_VCPUS;
2787 break;
2788 case KVM_CAP_NR_MEMSLOTS:
2789 r = KVM_USER_MEM_SLOTS;
2790 break;
2791 case KVM_CAP_PV_MMU: /* obsolete */
2792 r = 0;
2793 break;
2794 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2795 case KVM_CAP_IOMMU:
2796 r = iommu_present(&pci_bus_type);
2797 break;
2798 #endif
2799 case KVM_CAP_MCE:
2800 r = KVM_MAX_MCE_BANKS;
2801 break;
2802 case KVM_CAP_XCRS:
2803 r = cpu_has_xsave;
2804 break;
2805 case KVM_CAP_TSC_CONTROL:
2806 r = kvm_has_tsc_control;
2807 break;
2808 default:
2809 r = 0;
2810 break;
2811 }
2812 return r;
2813
2814 }
2815
2816 long kvm_arch_dev_ioctl(struct file *filp,
2817 unsigned int ioctl, unsigned long arg)
2818 {
2819 void __user *argp = (void __user *)arg;
2820 long r;
2821
2822 switch (ioctl) {
2823 case KVM_GET_MSR_INDEX_LIST: {
2824 struct kvm_msr_list __user *user_msr_list = argp;
2825 struct kvm_msr_list msr_list;
2826 unsigned n;
2827
2828 r = -EFAULT;
2829 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2830 goto out;
2831 n = msr_list.nmsrs;
2832 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2833 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2834 goto out;
2835 r = -E2BIG;
2836 if (n < msr_list.nmsrs)
2837 goto out;
2838 r = -EFAULT;
2839 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2840 num_msrs_to_save * sizeof(u32)))
2841 goto out;
2842 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2843 &emulated_msrs,
2844 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2845 goto out;
2846 r = 0;
2847 break;
2848 }
2849 case KVM_GET_SUPPORTED_CPUID:
2850 case KVM_GET_EMULATED_CPUID: {
2851 struct kvm_cpuid2 __user *cpuid_arg = argp;
2852 struct kvm_cpuid2 cpuid;
2853
2854 r = -EFAULT;
2855 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2856 goto out;
2857
2858 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2859 ioctl);
2860 if (r)
2861 goto out;
2862
2863 r = -EFAULT;
2864 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2865 goto out;
2866 r = 0;
2867 break;
2868 }
2869 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2870 u64 mce_cap;
2871
2872 mce_cap = KVM_MCE_CAP_SUPPORTED;
2873 r = -EFAULT;
2874 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2875 goto out;
2876 r = 0;
2877 break;
2878 }
2879 default:
2880 r = -EINVAL;
2881 }
2882 out:
2883 return r;
2884 }
2885
2886 static void wbinvd_ipi(void *garbage)
2887 {
2888 wbinvd();
2889 }
2890
2891 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2892 {
2893 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2894 }
2895
2896 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2897 {
2898 /* Address WBINVD may be executed by guest */
2899 if (need_emulate_wbinvd(vcpu)) {
2900 if (kvm_x86_ops->has_wbinvd_exit())
2901 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2902 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2903 smp_call_function_single(vcpu->cpu,
2904 wbinvd_ipi, NULL, 1);
2905 }
2906
2907 kvm_x86_ops->vcpu_load(vcpu, cpu);
2908
2909 /* Apply any externally detected TSC adjustments (due to suspend) */
2910 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2911 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2912 vcpu->arch.tsc_offset_adjustment = 0;
2913 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2914 }
2915
2916 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2917 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2918 native_read_tsc() - vcpu->arch.last_host_tsc;
2919 if (tsc_delta < 0)
2920 mark_tsc_unstable("KVM discovered backwards TSC");
2921 if (check_tsc_unstable()) {
2922 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2923 vcpu->arch.last_guest_tsc);
2924 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2925 vcpu->arch.tsc_catchup = 1;
2926 }
2927 /*
2928 * On a host with synchronized TSC, there is no need to update
2929 * kvmclock on vcpu->cpu migration
2930 */
2931 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2932 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2933 if (vcpu->cpu != cpu)
2934 kvm_migrate_timers(vcpu);
2935 vcpu->cpu = cpu;
2936 }
2937
2938 accumulate_steal_time(vcpu);
2939 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2940 }
2941
2942 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2943 {
2944 kvm_x86_ops->vcpu_put(vcpu);
2945 kvm_put_guest_fpu(vcpu);
2946 vcpu->arch.last_host_tsc = native_read_tsc();
2947 }
2948
2949 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2950 struct kvm_lapic_state *s)
2951 {
2952 kvm_x86_ops->sync_pir_to_irr(vcpu);
2953 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2954
2955 return 0;
2956 }
2957
2958 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2959 struct kvm_lapic_state *s)
2960 {
2961 kvm_apic_post_state_restore(vcpu, s);
2962 update_cr8_intercept(vcpu);
2963
2964 return 0;
2965 }
2966
2967 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2968 struct kvm_interrupt *irq)
2969 {
2970 if (irq->irq >= KVM_NR_INTERRUPTS)
2971 return -EINVAL;
2972 if (irqchip_in_kernel(vcpu->kvm))
2973 return -ENXIO;
2974
2975 kvm_queue_interrupt(vcpu, irq->irq, false);
2976 kvm_make_request(KVM_REQ_EVENT, vcpu);
2977
2978 return 0;
2979 }
2980
2981 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2982 {
2983 kvm_inject_nmi(vcpu);
2984
2985 return 0;
2986 }
2987
2988 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2989 struct kvm_tpr_access_ctl *tac)
2990 {
2991 if (tac->flags)
2992 return -EINVAL;
2993 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2994 return 0;
2995 }
2996
2997 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2998 u64 mcg_cap)
2999 {
3000 int r;
3001 unsigned bank_num = mcg_cap & 0xff, bank;
3002
3003 r = -EINVAL;
3004 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3005 goto out;
3006 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3007 goto out;
3008 r = 0;
3009 vcpu->arch.mcg_cap = mcg_cap;
3010 /* Init IA32_MCG_CTL to all 1s */
3011 if (mcg_cap & MCG_CTL_P)
3012 vcpu->arch.mcg_ctl = ~(u64)0;
3013 /* Init IA32_MCi_CTL to all 1s */
3014 for (bank = 0; bank < bank_num; bank++)
3015 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3016 out:
3017 return r;
3018 }
3019
3020 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3021 struct kvm_x86_mce *mce)
3022 {
3023 u64 mcg_cap = vcpu->arch.mcg_cap;
3024 unsigned bank_num = mcg_cap & 0xff;
3025 u64 *banks = vcpu->arch.mce_banks;
3026
3027 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3028 return -EINVAL;
3029 /*
3030 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3031 * reporting is disabled
3032 */
3033 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3034 vcpu->arch.mcg_ctl != ~(u64)0)
3035 return 0;
3036 banks += 4 * mce->bank;
3037 /*
3038 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3039 * reporting is disabled for the bank
3040 */
3041 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3042 return 0;
3043 if (mce->status & MCI_STATUS_UC) {
3044 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3045 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3046 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3047 return 0;
3048 }
3049 if (banks[1] & MCI_STATUS_VAL)
3050 mce->status |= MCI_STATUS_OVER;
3051 banks[2] = mce->addr;
3052 banks[3] = mce->misc;
3053 vcpu->arch.mcg_status = mce->mcg_status;
3054 banks[1] = mce->status;
3055 kvm_queue_exception(vcpu, MC_VECTOR);
3056 } else if (!(banks[1] & MCI_STATUS_VAL)
3057 || !(banks[1] & MCI_STATUS_UC)) {
3058 if (banks[1] & MCI_STATUS_VAL)
3059 mce->status |= MCI_STATUS_OVER;
3060 banks[2] = mce->addr;
3061 banks[3] = mce->misc;
3062 banks[1] = mce->status;
3063 } else
3064 banks[1] |= MCI_STATUS_OVER;
3065 return 0;
3066 }
3067
3068 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3069 struct kvm_vcpu_events *events)
3070 {
3071 process_nmi(vcpu);
3072 events->exception.injected =
3073 vcpu->arch.exception.pending &&
3074 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3075 events->exception.nr = vcpu->arch.exception.nr;
3076 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3077 events->exception.pad = 0;
3078 events->exception.error_code = vcpu->arch.exception.error_code;
3079
3080 events->interrupt.injected =
3081 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3082 events->interrupt.nr = vcpu->arch.interrupt.nr;
3083 events->interrupt.soft = 0;
3084 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3085
3086 events->nmi.injected = vcpu->arch.nmi_injected;
3087 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3088 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3089 events->nmi.pad = 0;
3090
3091 events->sipi_vector = 0; /* never valid when reporting to user space */
3092
3093 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3094 | KVM_VCPUEVENT_VALID_SHADOW);
3095 memset(&events->reserved, 0, sizeof(events->reserved));
3096 }
3097
3098 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3099 struct kvm_vcpu_events *events)
3100 {
3101 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3102 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3103 | KVM_VCPUEVENT_VALID_SHADOW))
3104 return -EINVAL;
3105
3106 process_nmi(vcpu);
3107 vcpu->arch.exception.pending = events->exception.injected;
3108 vcpu->arch.exception.nr = events->exception.nr;
3109 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3110 vcpu->arch.exception.error_code = events->exception.error_code;
3111
3112 vcpu->arch.interrupt.pending = events->interrupt.injected;
3113 vcpu->arch.interrupt.nr = events->interrupt.nr;
3114 vcpu->arch.interrupt.soft = events->interrupt.soft;
3115 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3116 kvm_x86_ops->set_interrupt_shadow(vcpu,
3117 events->interrupt.shadow);
3118
3119 vcpu->arch.nmi_injected = events->nmi.injected;
3120 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3121 vcpu->arch.nmi_pending = events->nmi.pending;
3122 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3123
3124 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3125 kvm_vcpu_has_lapic(vcpu))
3126 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3127
3128 kvm_make_request(KVM_REQ_EVENT, vcpu);
3129
3130 return 0;
3131 }
3132
3133 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3134 struct kvm_debugregs *dbgregs)
3135 {
3136 unsigned long val;
3137
3138 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3139 kvm_get_dr(vcpu, 6, &val);
3140 dbgregs->dr6 = val;
3141 dbgregs->dr7 = vcpu->arch.dr7;
3142 dbgregs->flags = 0;
3143 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3144 }
3145
3146 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3147 struct kvm_debugregs *dbgregs)
3148 {
3149 if (dbgregs->flags)
3150 return -EINVAL;
3151
3152 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3153 vcpu->arch.dr6 = dbgregs->dr6;
3154 kvm_update_dr6(vcpu);
3155 vcpu->arch.dr7 = dbgregs->dr7;
3156 kvm_update_dr7(vcpu);
3157
3158 return 0;
3159 }
3160
3161 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3162
3163 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3164 {
3165 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3166 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3167 u64 valid;
3168
3169 /*
3170 * Copy legacy XSAVE area, to avoid complications with CPUID
3171 * leaves 0 and 1 in the loop below.
3172 */
3173 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3174
3175 /* Set XSTATE_BV */
3176 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3177
3178 /*
3179 * Copy each region from the possibly compacted offset to the
3180 * non-compacted offset.
3181 */
3182 valid = xstate_bv & ~XSTATE_FPSSE;
3183 while (valid) {
3184 u64 feature = valid & -valid;
3185 int index = fls64(feature) - 1;
3186 void *src = get_xsave_addr(xsave, feature);
3187
3188 if (src) {
3189 u32 size, offset, ecx, edx;
3190 cpuid_count(XSTATE_CPUID, index,
3191 &size, &offset, &ecx, &edx);
3192 memcpy(dest + offset, src, size);
3193 }
3194
3195 valid -= feature;
3196 }
3197 }
3198
3199 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3200 {
3201 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3202 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3203 u64 valid;
3204
3205 /*
3206 * Copy legacy XSAVE area, to avoid complications with CPUID
3207 * leaves 0 and 1 in the loop below.
3208 */
3209 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3210
3211 /* Set XSTATE_BV and possibly XCOMP_BV. */
3212 xsave->xsave_hdr.xstate_bv = xstate_bv;
3213 if (cpu_has_xsaves)
3214 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3215
3216 /*
3217 * Copy each region from the non-compacted offset to the
3218 * possibly compacted offset.
3219 */
3220 valid = xstate_bv & ~XSTATE_FPSSE;
3221 while (valid) {
3222 u64 feature = valid & -valid;
3223 int index = fls64(feature) - 1;
3224 void *dest = get_xsave_addr(xsave, feature);
3225
3226 if (dest) {
3227 u32 size, offset, ecx, edx;
3228 cpuid_count(XSTATE_CPUID, index,
3229 &size, &offset, &ecx, &edx);
3230 memcpy(dest, src + offset, size);
3231 } else
3232 WARN_ON_ONCE(1);
3233
3234 valid -= feature;
3235 }
3236 }
3237
3238 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3239 struct kvm_xsave *guest_xsave)
3240 {
3241 if (cpu_has_xsave) {
3242 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3243 fill_xsave((u8 *) guest_xsave->region, vcpu);
3244 } else {
3245 memcpy(guest_xsave->region,
3246 &vcpu->arch.guest_fpu.state->fxsave,
3247 sizeof(struct i387_fxsave_struct));
3248 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3249 XSTATE_FPSSE;
3250 }
3251 }
3252
3253 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3254 struct kvm_xsave *guest_xsave)
3255 {
3256 u64 xstate_bv =
3257 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3258
3259 if (cpu_has_xsave) {
3260 /*
3261 * Here we allow setting states that are not present in
3262 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3263 * with old userspace.
3264 */
3265 if (xstate_bv & ~kvm_supported_xcr0())
3266 return -EINVAL;
3267 load_xsave(vcpu, (u8 *)guest_xsave->region);
3268 } else {
3269 if (xstate_bv & ~XSTATE_FPSSE)
3270 return -EINVAL;
3271 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3272 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3273 }
3274 return 0;
3275 }
3276
3277 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3278 struct kvm_xcrs *guest_xcrs)
3279 {
3280 if (!cpu_has_xsave) {
3281 guest_xcrs->nr_xcrs = 0;
3282 return;
3283 }
3284
3285 guest_xcrs->nr_xcrs = 1;
3286 guest_xcrs->flags = 0;
3287 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3288 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3289 }
3290
3291 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3292 struct kvm_xcrs *guest_xcrs)
3293 {
3294 int i, r = 0;
3295
3296 if (!cpu_has_xsave)
3297 return -EINVAL;
3298
3299 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3300 return -EINVAL;
3301
3302 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3303 /* Only support XCR0 currently */
3304 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3305 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3306 guest_xcrs->xcrs[i].value);
3307 break;
3308 }
3309 if (r)
3310 r = -EINVAL;
3311 return r;
3312 }
3313
3314 /*
3315 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3316 * stopped by the hypervisor. This function will be called from the host only.
3317 * EINVAL is returned when the host attempts to set the flag for a guest that
3318 * does not support pv clocks.
3319 */
3320 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3321 {
3322 if (!vcpu->arch.pv_time_enabled)
3323 return -EINVAL;
3324 vcpu->arch.pvclock_set_guest_stopped_request = true;
3325 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3326 return 0;
3327 }
3328
3329 long kvm_arch_vcpu_ioctl(struct file *filp,
3330 unsigned int ioctl, unsigned long arg)
3331 {
3332 struct kvm_vcpu *vcpu = filp->private_data;
3333 void __user *argp = (void __user *)arg;
3334 int r;
3335 union {
3336 struct kvm_lapic_state *lapic;
3337 struct kvm_xsave *xsave;
3338 struct kvm_xcrs *xcrs;
3339 void *buffer;
3340 } u;
3341
3342 u.buffer = NULL;
3343 switch (ioctl) {
3344 case KVM_GET_LAPIC: {
3345 r = -EINVAL;
3346 if (!vcpu->arch.apic)
3347 goto out;
3348 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3349
3350 r = -ENOMEM;
3351 if (!u.lapic)
3352 goto out;
3353 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3354 if (r)
3355 goto out;
3356 r = -EFAULT;
3357 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3358 goto out;
3359 r = 0;
3360 break;
3361 }
3362 case KVM_SET_LAPIC: {
3363 r = -EINVAL;
3364 if (!vcpu->arch.apic)
3365 goto out;
3366 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3367 if (IS_ERR(u.lapic))
3368 return PTR_ERR(u.lapic);
3369
3370 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3371 break;
3372 }
3373 case KVM_INTERRUPT: {
3374 struct kvm_interrupt irq;
3375
3376 r = -EFAULT;
3377 if (copy_from_user(&irq, argp, sizeof irq))
3378 goto out;
3379 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3380 break;
3381 }
3382 case KVM_NMI: {
3383 r = kvm_vcpu_ioctl_nmi(vcpu);
3384 break;
3385 }
3386 case KVM_SET_CPUID: {
3387 struct kvm_cpuid __user *cpuid_arg = argp;
3388 struct kvm_cpuid cpuid;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3392 goto out;
3393 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3394 break;
3395 }
3396 case KVM_SET_CPUID2: {
3397 struct kvm_cpuid2 __user *cpuid_arg = argp;
3398 struct kvm_cpuid2 cpuid;
3399
3400 r = -EFAULT;
3401 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3402 goto out;
3403 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3404 cpuid_arg->entries);
3405 break;
3406 }
3407 case KVM_GET_CPUID2: {
3408 struct kvm_cpuid2 __user *cpuid_arg = argp;
3409 struct kvm_cpuid2 cpuid;
3410
3411 r = -EFAULT;
3412 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3413 goto out;
3414 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3415 cpuid_arg->entries);
3416 if (r)
3417 goto out;
3418 r = -EFAULT;
3419 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3420 goto out;
3421 r = 0;
3422 break;
3423 }
3424 case KVM_GET_MSRS:
3425 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3426 break;
3427 case KVM_SET_MSRS:
3428 r = msr_io(vcpu, argp, do_set_msr, 0);
3429 break;
3430 case KVM_TPR_ACCESS_REPORTING: {
3431 struct kvm_tpr_access_ctl tac;
3432
3433 r = -EFAULT;
3434 if (copy_from_user(&tac, argp, sizeof tac))
3435 goto out;
3436 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3437 if (r)
3438 goto out;
3439 r = -EFAULT;
3440 if (copy_to_user(argp, &tac, sizeof tac))
3441 goto out;
3442 r = 0;
3443 break;
3444 };
3445 case KVM_SET_VAPIC_ADDR: {
3446 struct kvm_vapic_addr va;
3447
3448 r = -EINVAL;
3449 if (!irqchip_in_kernel(vcpu->kvm))
3450 goto out;
3451 r = -EFAULT;
3452 if (copy_from_user(&va, argp, sizeof va))
3453 goto out;
3454 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3455 break;
3456 }
3457 case KVM_X86_SETUP_MCE: {
3458 u64 mcg_cap;
3459
3460 r = -EFAULT;
3461 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3462 goto out;
3463 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3464 break;
3465 }
3466 case KVM_X86_SET_MCE: {
3467 struct kvm_x86_mce mce;
3468
3469 r = -EFAULT;
3470 if (copy_from_user(&mce, argp, sizeof mce))
3471 goto out;
3472 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3473 break;
3474 }
3475 case KVM_GET_VCPU_EVENTS: {
3476 struct kvm_vcpu_events events;
3477
3478 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3479
3480 r = -EFAULT;
3481 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3482 break;
3483 r = 0;
3484 break;
3485 }
3486 case KVM_SET_VCPU_EVENTS: {
3487 struct kvm_vcpu_events events;
3488
3489 r = -EFAULT;
3490 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3491 break;
3492
3493 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3494 break;
3495 }
3496 case KVM_GET_DEBUGREGS: {
3497 struct kvm_debugregs dbgregs;
3498
3499 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3500
3501 r = -EFAULT;
3502 if (copy_to_user(argp, &dbgregs,
3503 sizeof(struct kvm_debugregs)))
3504 break;
3505 r = 0;
3506 break;
3507 }
3508 case KVM_SET_DEBUGREGS: {
3509 struct kvm_debugregs dbgregs;
3510
3511 r = -EFAULT;
3512 if (copy_from_user(&dbgregs, argp,
3513 sizeof(struct kvm_debugregs)))
3514 break;
3515
3516 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3517 break;
3518 }
3519 case KVM_GET_XSAVE: {
3520 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3521 r = -ENOMEM;
3522 if (!u.xsave)
3523 break;
3524
3525 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3526
3527 r = -EFAULT;
3528 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3529 break;
3530 r = 0;
3531 break;
3532 }
3533 case KVM_SET_XSAVE: {
3534 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3535 if (IS_ERR(u.xsave))
3536 return PTR_ERR(u.xsave);
3537
3538 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3539 break;
3540 }
3541 case KVM_GET_XCRS: {
3542 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3543 r = -ENOMEM;
3544 if (!u.xcrs)
3545 break;
3546
3547 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3548
3549 r = -EFAULT;
3550 if (copy_to_user(argp, u.xcrs,
3551 sizeof(struct kvm_xcrs)))
3552 break;
3553 r = 0;
3554 break;
3555 }
3556 case KVM_SET_XCRS: {
3557 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3558 if (IS_ERR(u.xcrs))
3559 return PTR_ERR(u.xcrs);
3560
3561 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3562 break;
3563 }
3564 case KVM_SET_TSC_KHZ: {
3565 u32 user_tsc_khz;
3566
3567 r = -EINVAL;
3568 user_tsc_khz = (u32)arg;
3569
3570 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3571 goto out;
3572
3573 if (user_tsc_khz == 0)
3574 user_tsc_khz = tsc_khz;
3575
3576 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3577
3578 r = 0;
3579 goto out;
3580 }
3581 case KVM_GET_TSC_KHZ: {
3582 r = vcpu->arch.virtual_tsc_khz;
3583 goto out;
3584 }
3585 case KVM_KVMCLOCK_CTRL: {
3586 r = kvm_set_guest_paused(vcpu);
3587 goto out;
3588 }
3589 default:
3590 r = -EINVAL;
3591 }
3592 out:
3593 kfree(u.buffer);
3594 return r;
3595 }
3596
3597 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3598 {
3599 return VM_FAULT_SIGBUS;
3600 }
3601
3602 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3603 {
3604 int ret;
3605
3606 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3607 return -EINVAL;
3608 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3609 return ret;
3610 }
3611
3612 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3613 u64 ident_addr)
3614 {
3615 kvm->arch.ept_identity_map_addr = ident_addr;
3616 return 0;
3617 }
3618
3619 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3620 u32 kvm_nr_mmu_pages)
3621 {
3622 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3623 return -EINVAL;
3624
3625 mutex_lock(&kvm->slots_lock);
3626
3627 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3628 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3629
3630 mutex_unlock(&kvm->slots_lock);
3631 return 0;
3632 }
3633
3634 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3635 {
3636 return kvm->arch.n_max_mmu_pages;
3637 }
3638
3639 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3640 {
3641 int r;
3642
3643 r = 0;
3644 switch (chip->chip_id) {
3645 case KVM_IRQCHIP_PIC_MASTER:
3646 memcpy(&chip->chip.pic,
3647 &pic_irqchip(kvm)->pics[0],
3648 sizeof(struct kvm_pic_state));
3649 break;
3650 case KVM_IRQCHIP_PIC_SLAVE:
3651 memcpy(&chip->chip.pic,
3652 &pic_irqchip(kvm)->pics[1],
3653 sizeof(struct kvm_pic_state));
3654 break;
3655 case KVM_IRQCHIP_IOAPIC:
3656 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3657 break;
3658 default:
3659 r = -EINVAL;
3660 break;
3661 }
3662 return r;
3663 }
3664
3665 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3666 {
3667 int r;
3668
3669 r = 0;
3670 switch (chip->chip_id) {
3671 case KVM_IRQCHIP_PIC_MASTER:
3672 spin_lock(&pic_irqchip(kvm)->lock);
3673 memcpy(&pic_irqchip(kvm)->pics[0],
3674 &chip->chip.pic,
3675 sizeof(struct kvm_pic_state));
3676 spin_unlock(&pic_irqchip(kvm)->lock);
3677 break;
3678 case KVM_IRQCHIP_PIC_SLAVE:
3679 spin_lock(&pic_irqchip(kvm)->lock);
3680 memcpy(&pic_irqchip(kvm)->pics[1],
3681 &chip->chip.pic,
3682 sizeof(struct kvm_pic_state));
3683 spin_unlock(&pic_irqchip(kvm)->lock);
3684 break;
3685 case KVM_IRQCHIP_IOAPIC:
3686 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3687 break;
3688 default:
3689 r = -EINVAL;
3690 break;
3691 }
3692 kvm_pic_update_irq(pic_irqchip(kvm));
3693 return r;
3694 }
3695
3696 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3697 {
3698 int r = 0;
3699
3700 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3701 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3702 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3703 return r;
3704 }
3705
3706 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3707 {
3708 int r = 0;
3709
3710 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3711 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3712 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3713 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3714 return r;
3715 }
3716
3717 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3718 {
3719 int r = 0;
3720
3721 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3722 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3723 sizeof(ps->channels));
3724 ps->flags = kvm->arch.vpit->pit_state.flags;
3725 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3726 memset(&ps->reserved, 0, sizeof(ps->reserved));
3727 return r;
3728 }
3729
3730 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3731 {
3732 int r = 0, start = 0;
3733 u32 prev_legacy, cur_legacy;
3734 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3735 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3736 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3737 if (!prev_legacy && cur_legacy)
3738 start = 1;
3739 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3740 sizeof(kvm->arch.vpit->pit_state.channels));
3741 kvm->arch.vpit->pit_state.flags = ps->flags;
3742 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3743 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3744 return r;
3745 }
3746
3747 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3748 struct kvm_reinject_control *control)
3749 {
3750 if (!kvm->arch.vpit)
3751 return -ENXIO;
3752 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3753 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3754 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3755 return 0;
3756 }
3757
3758 /**
3759 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3760 * @kvm: kvm instance
3761 * @log: slot id and address to which we copy the log
3762 *
3763 * Steps 1-4 below provide general overview of dirty page logging. See
3764 * kvm_get_dirty_log_protect() function description for additional details.
3765 *
3766 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3767 * always flush the TLB (step 4) even if previous step failed and the dirty
3768 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3769 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3770 * writes will be marked dirty for next log read.
3771 *
3772 * 1. Take a snapshot of the bit and clear it if needed.
3773 * 2. Write protect the corresponding page.
3774 * 3. Copy the snapshot to the userspace.
3775 * 4. Flush TLB's if needed.
3776 */
3777 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3778 {
3779 bool is_dirty = false;
3780 int r;
3781
3782 mutex_lock(&kvm->slots_lock);
3783
3784 /*
3785 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3786 */
3787 if (kvm_x86_ops->flush_log_dirty)
3788 kvm_x86_ops->flush_log_dirty(kvm);
3789
3790 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3791
3792 /*
3793 * All the TLBs can be flushed out of mmu lock, see the comments in
3794 * kvm_mmu_slot_remove_write_access().
3795 */
3796 lockdep_assert_held(&kvm->slots_lock);
3797 if (is_dirty)
3798 kvm_flush_remote_tlbs(kvm);
3799
3800 mutex_unlock(&kvm->slots_lock);
3801 return r;
3802 }
3803
3804 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3805 bool line_status)
3806 {
3807 if (!irqchip_in_kernel(kvm))
3808 return -ENXIO;
3809
3810 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3811 irq_event->irq, irq_event->level,
3812 line_status);
3813 return 0;
3814 }
3815
3816 long kvm_arch_vm_ioctl(struct file *filp,
3817 unsigned int ioctl, unsigned long arg)
3818 {
3819 struct kvm *kvm = filp->private_data;
3820 void __user *argp = (void __user *)arg;
3821 int r = -ENOTTY;
3822 /*
3823 * This union makes it completely explicit to gcc-3.x
3824 * that these two variables' stack usage should be
3825 * combined, not added together.
3826 */
3827 union {
3828 struct kvm_pit_state ps;
3829 struct kvm_pit_state2 ps2;
3830 struct kvm_pit_config pit_config;
3831 } u;
3832
3833 switch (ioctl) {
3834 case KVM_SET_TSS_ADDR:
3835 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3836 break;
3837 case KVM_SET_IDENTITY_MAP_ADDR: {
3838 u64 ident_addr;
3839
3840 r = -EFAULT;
3841 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3842 goto out;
3843 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3844 break;
3845 }
3846 case KVM_SET_NR_MMU_PAGES:
3847 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3848 break;
3849 case KVM_GET_NR_MMU_PAGES:
3850 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3851 break;
3852 case KVM_CREATE_IRQCHIP: {
3853 struct kvm_pic *vpic;
3854
3855 mutex_lock(&kvm->lock);
3856 r = -EEXIST;
3857 if (kvm->arch.vpic)
3858 goto create_irqchip_unlock;
3859 r = -EINVAL;
3860 if (atomic_read(&kvm->online_vcpus))
3861 goto create_irqchip_unlock;
3862 r = -ENOMEM;
3863 vpic = kvm_create_pic(kvm);
3864 if (vpic) {
3865 r = kvm_ioapic_init(kvm);
3866 if (r) {
3867 mutex_lock(&kvm->slots_lock);
3868 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3869 &vpic->dev_master);
3870 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3871 &vpic->dev_slave);
3872 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3873 &vpic->dev_eclr);
3874 mutex_unlock(&kvm->slots_lock);
3875 kfree(vpic);
3876 goto create_irqchip_unlock;
3877 }
3878 } else
3879 goto create_irqchip_unlock;
3880 smp_wmb();
3881 kvm->arch.vpic = vpic;
3882 smp_wmb();
3883 r = kvm_setup_default_irq_routing(kvm);
3884 if (r) {
3885 mutex_lock(&kvm->slots_lock);
3886 mutex_lock(&kvm->irq_lock);
3887 kvm_ioapic_destroy(kvm);
3888 kvm_destroy_pic(kvm);
3889 mutex_unlock(&kvm->irq_lock);
3890 mutex_unlock(&kvm->slots_lock);
3891 }
3892 create_irqchip_unlock:
3893 mutex_unlock(&kvm->lock);
3894 break;
3895 }
3896 case KVM_CREATE_PIT:
3897 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3898 goto create_pit;
3899 case KVM_CREATE_PIT2:
3900 r = -EFAULT;
3901 if (copy_from_user(&u.pit_config, argp,
3902 sizeof(struct kvm_pit_config)))
3903 goto out;
3904 create_pit:
3905 mutex_lock(&kvm->slots_lock);
3906 r = -EEXIST;
3907 if (kvm->arch.vpit)
3908 goto create_pit_unlock;
3909 r = -ENOMEM;
3910 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3911 if (kvm->arch.vpit)
3912 r = 0;
3913 create_pit_unlock:
3914 mutex_unlock(&kvm->slots_lock);
3915 break;
3916 case KVM_GET_IRQCHIP: {
3917 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3918 struct kvm_irqchip *chip;
3919
3920 chip = memdup_user(argp, sizeof(*chip));
3921 if (IS_ERR(chip)) {
3922 r = PTR_ERR(chip);
3923 goto out;
3924 }
3925
3926 r = -ENXIO;
3927 if (!irqchip_in_kernel(kvm))
3928 goto get_irqchip_out;
3929 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3930 if (r)
3931 goto get_irqchip_out;
3932 r = -EFAULT;
3933 if (copy_to_user(argp, chip, sizeof *chip))
3934 goto get_irqchip_out;
3935 r = 0;
3936 get_irqchip_out:
3937 kfree(chip);
3938 break;
3939 }
3940 case KVM_SET_IRQCHIP: {
3941 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3942 struct kvm_irqchip *chip;
3943
3944 chip = memdup_user(argp, sizeof(*chip));
3945 if (IS_ERR(chip)) {
3946 r = PTR_ERR(chip);
3947 goto out;
3948 }
3949
3950 r = -ENXIO;
3951 if (!irqchip_in_kernel(kvm))
3952 goto set_irqchip_out;
3953 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3954 if (r)
3955 goto set_irqchip_out;
3956 r = 0;
3957 set_irqchip_out:
3958 kfree(chip);
3959 break;
3960 }
3961 case KVM_GET_PIT: {
3962 r = -EFAULT;
3963 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3964 goto out;
3965 r = -ENXIO;
3966 if (!kvm->arch.vpit)
3967 goto out;
3968 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3969 if (r)
3970 goto out;
3971 r = -EFAULT;
3972 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3973 goto out;
3974 r = 0;
3975 break;
3976 }
3977 case KVM_SET_PIT: {
3978 r = -EFAULT;
3979 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3980 goto out;
3981 r = -ENXIO;
3982 if (!kvm->arch.vpit)
3983 goto out;
3984 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3985 break;
3986 }
3987 case KVM_GET_PIT2: {
3988 r = -ENXIO;
3989 if (!kvm->arch.vpit)
3990 goto out;
3991 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3992 if (r)
3993 goto out;
3994 r = -EFAULT;
3995 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3996 goto out;
3997 r = 0;
3998 break;
3999 }
4000 case KVM_SET_PIT2: {
4001 r = -EFAULT;
4002 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4003 goto out;
4004 r = -ENXIO;
4005 if (!kvm->arch.vpit)
4006 goto out;
4007 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4008 break;
4009 }
4010 case KVM_REINJECT_CONTROL: {
4011 struct kvm_reinject_control control;
4012 r = -EFAULT;
4013 if (copy_from_user(&control, argp, sizeof(control)))
4014 goto out;
4015 r = kvm_vm_ioctl_reinject(kvm, &control);
4016 break;
4017 }
4018 case KVM_XEN_HVM_CONFIG: {
4019 r = -EFAULT;
4020 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4021 sizeof(struct kvm_xen_hvm_config)))
4022 goto out;
4023 r = -EINVAL;
4024 if (kvm->arch.xen_hvm_config.flags)
4025 goto out;
4026 r = 0;
4027 break;
4028 }
4029 case KVM_SET_CLOCK: {
4030 struct kvm_clock_data user_ns;
4031 u64 now_ns;
4032 s64 delta;
4033
4034 r = -EFAULT;
4035 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4036 goto out;
4037
4038 r = -EINVAL;
4039 if (user_ns.flags)
4040 goto out;
4041
4042 r = 0;
4043 local_irq_disable();
4044 now_ns = get_kernel_ns();
4045 delta = user_ns.clock - now_ns;
4046 local_irq_enable();
4047 kvm->arch.kvmclock_offset = delta;
4048 kvm_gen_update_masterclock(kvm);
4049 break;
4050 }
4051 case KVM_GET_CLOCK: {
4052 struct kvm_clock_data user_ns;
4053 u64 now_ns;
4054
4055 local_irq_disable();
4056 now_ns = get_kernel_ns();
4057 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4058 local_irq_enable();
4059 user_ns.flags = 0;
4060 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4061
4062 r = -EFAULT;
4063 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4064 goto out;
4065 r = 0;
4066 break;
4067 }
4068
4069 default:
4070 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4071 }
4072 out:
4073 return r;
4074 }
4075
4076 static void kvm_init_msr_list(void)
4077 {
4078 u32 dummy[2];
4079 unsigned i, j;
4080
4081 /* skip the first msrs in the list. KVM-specific */
4082 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
4083 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4084 continue;
4085
4086 /*
4087 * Even MSRs that are valid in the host may not be exposed
4088 * to the guests in some cases. We could work around this
4089 * in VMX with the generic MSR save/load machinery, but it
4090 * is not really worthwhile since it will really only
4091 * happen with nested virtualization.
4092 */
4093 switch (msrs_to_save[i]) {
4094 case MSR_IA32_BNDCFGS:
4095 if (!kvm_x86_ops->mpx_supported())
4096 continue;
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 if (j < i)
4103 msrs_to_save[j] = msrs_to_save[i];
4104 j++;
4105 }
4106 num_msrs_to_save = j;
4107 }
4108
4109 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4110 const void *v)
4111 {
4112 int handled = 0;
4113 int n;
4114
4115 do {
4116 n = min(len, 8);
4117 if (!(vcpu->arch.apic &&
4118 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4119 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4120 break;
4121 handled += n;
4122 addr += n;
4123 len -= n;
4124 v += n;
4125 } while (len);
4126
4127 return handled;
4128 }
4129
4130 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4131 {
4132 int handled = 0;
4133 int n;
4134
4135 do {
4136 n = min(len, 8);
4137 if (!(vcpu->arch.apic &&
4138 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4139 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4140 break;
4141 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4142 handled += n;
4143 addr += n;
4144 len -= n;
4145 v += n;
4146 } while (len);
4147
4148 return handled;
4149 }
4150
4151 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4152 struct kvm_segment *var, int seg)
4153 {
4154 kvm_x86_ops->set_segment(vcpu, var, seg);
4155 }
4156
4157 void kvm_get_segment(struct kvm_vcpu *vcpu,
4158 struct kvm_segment *var, int seg)
4159 {
4160 kvm_x86_ops->get_segment(vcpu, var, seg);
4161 }
4162
4163 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4164 struct x86_exception *exception)
4165 {
4166 gpa_t t_gpa;
4167
4168 BUG_ON(!mmu_is_nested(vcpu));
4169
4170 /* NPT walks are always user-walks */
4171 access |= PFERR_USER_MASK;
4172 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4173
4174 return t_gpa;
4175 }
4176
4177 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4178 struct x86_exception *exception)
4179 {
4180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4181 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4182 }
4183
4184 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4185 struct x86_exception *exception)
4186 {
4187 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4188 access |= PFERR_FETCH_MASK;
4189 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4190 }
4191
4192 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4193 struct x86_exception *exception)
4194 {
4195 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4196 access |= PFERR_WRITE_MASK;
4197 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4198 }
4199
4200 /* uses this to access any guest's mapped memory without checking CPL */
4201 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4202 struct x86_exception *exception)
4203 {
4204 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4205 }
4206
4207 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4208 struct kvm_vcpu *vcpu, u32 access,
4209 struct x86_exception *exception)
4210 {
4211 void *data = val;
4212 int r = X86EMUL_CONTINUE;
4213
4214 while (bytes) {
4215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4216 exception);
4217 unsigned offset = addr & (PAGE_SIZE-1);
4218 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4219 int ret;
4220
4221 if (gpa == UNMAPPED_GVA)
4222 return X86EMUL_PROPAGATE_FAULT;
4223 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4224 offset, toread);
4225 if (ret < 0) {
4226 r = X86EMUL_IO_NEEDED;
4227 goto out;
4228 }
4229
4230 bytes -= toread;
4231 data += toread;
4232 addr += toread;
4233 }
4234 out:
4235 return r;
4236 }
4237
4238 /* used for instruction fetching */
4239 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4240 gva_t addr, void *val, unsigned int bytes,
4241 struct x86_exception *exception)
4242 {
4243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4244 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4245 unsigned offset;
4246 int ret;
4247
4248 /* Inline kvm_read_guest_virt_helper for speed. */
4249 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4250 exception);
4251 if (unlikely(gpa == UNMAPPED_GVA))
4252 return X86EMUL_PROPAGATE_FAULT;
4253
4254 offset = addr & (PAGE_SIZE-1);
4255 if (WARN_ON(offset + bytes > PAGE_SIZE))
4256 bytes = (unsigned)PAGE_SIZE - offset;
4257 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4258 offset, bytes);
4259 if (unlikely(ret < 0))
4260 return X86EMUL_IO_NEEDED;
4261
4262 return X86EMUL_CONTINUE;
4263 }
4264
4265 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4266 gva_t addr, void *val, unsigned int bytes,
4267 struct x86_exception *exception)
4268 {
4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4271
4272 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4273 exception);
4274 }
4275 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4276
4277 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4278 gva_t addr, void *val, unsigned int bytes,
4279 struct x86_exception *exception)
4280 {
4281 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4282 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4283 }
4284
4285 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4286 gva_t addr, void *val,
4287 unsigned int bytes,
4288 struct x86_exception *exception)
4289 {
4290 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4291 void *data = val;
4292 int r = X86EMUL_CONTINUE;
4293
4294 while (bytes) {
4295 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4296 PFERR_WRITE_MASK,
4297 exception);
4298 unsigned offset = addr & (PAGE_SIZE-1);
4299 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4300 int ret;
4301
4302 if (gpa == UNMAPPED_GVA)
4303 return X86EMUL_PROPAGATE_FAULT;
4304 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4305 if (ret < 0) {
4306 r = X86EMUL_IO_NEEDED;
4307 goto out;
4308 }
4309
4310 bytes -= towrite;
4311 data += towrite;
4312 addr += towrite;
4313 }
4314 out:
4315 return r;
4316 }
4317 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4318
4319 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4320 gpa_t *gpa, struct x86_exception *exception,
4321 bool write)
4322 {
4323 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4324 | (write ? PFERR_WRITE_MASK : 0);
4325
4326 if (vcpu_match_mmio_gva(vcpu, gva)
4327 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4328 vcpu->arch.access, access)) {
4329 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4330 (gva & (PAGE_SIZE - 1));
4331 trace_vcpu_match_mmio(gva, *gpa, write, false);
4332 return 1;
4333 }
4334
4335 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4336
4337 if (*gpa == UNMAPPED_GVA)
4338 return -1;
4339
4340 /* For APIC access vmexit */
4341 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4342 return 1;
4343
4344 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4345 trace_vcpu_match_mmio(gva, *gpa, write, true);
4346 return 1;
4347 }
4348
4349 return 0;
4350 }
4351
4352 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4353 const void *val, int bytes)
4354 {
4355 int ret;
4356
4357 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4358 if (ret < 0)
4359 return 0;
4360 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4361 return 1;
4362 }
4363
4364 struct read_write_emulator_ops {
4365 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4366 int bytes);
4367 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4368 void *val, int bytes);
4369 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4370 int bytes, void *val);
4371 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 void *val, int bytes);
4373 bool write;
4374 };
4375
4376 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4377 {
4378 if (vcpu->mmio_read_completed) {
4379 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4380 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4381 vcpu->mmio_read_completed = 0;
4382 return 1;
4383 }
4384
4385 return 0;
4386 }
4387
4388 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 void *val, int bytes)
4390 {
4391 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4392 }
4393
4394 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4395 void *val, int bytes)
4396 {
4397 return emulator_write_phys(vcpu, gpa, val, bytes);
4398 }
4399
4400 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4401 {
4402 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4403 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4404 }
4405
4406 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4407 void *val, int bytes)
4408 {
4409 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4410 return X86EMUL_IO_NEEDED;
4411 }
4412
4413 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4415 {
4416 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4417
4418 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4419 return X86EMUL_CONTINUE;
4420 }
4421
4422 static const struct read_write_emulator_ops read_emultor = {
4423 .read_write_prepare = read_prepare,
4424 .read_write_emulate = read_emulate,
4425 .read_write_mmio = vcpu_mmio_read,
4426 .read_write_exit_mmio = read_exit_mmio,
4427 };
4428
4429 static const struct read_write_emulator_ops write_emultor = {
4430 .read_write_emulate = write_emulate,
4431 .read_write_mmio = write_mmio,
4432 .read_write_exit_mmio = write_exit_mmio,
4433 .write = true,
4434 };
4435
4436 static int emulator_read_write_onepage(unsigned long addr, void *val,
4437 unsigned int bytes,
4438 struct x86_exception *exception,
4439 struct kvm_vcpu *vcpu,
4440 const struct read_write_emulator_ops *ops)
4441 {
4442 gpa_t gpa;
4443 int handled, ret;
4444 bool write = ops->write;
4445 struct kvm_mmio_fragment *frag;
4446
4447 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4448
4449 if (ret < 0)
4450 return X86EMUL_PROPAGATE_FAULT;
4451
4452 /* For APIC access vmexit */
4453 if (ret)
4454 goto mmio;
4455
4456 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4457 return X86EMUL_CONTINUE;
4458
4459 mmio:
4460 /*
4461 * Is this MMIO handled locally?
4462 */
4463 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4464 if (handled == bytes)
4465 return X86EMUL_CONTINUE;
4466
4467 gpa += handled;
4468 bytes -= handled;
4469 val += handled;
4470
4471 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4472 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4473 frag->gpa = gpa;
4474 frag->data = val;
4475 frag->len = bytes;
4476 return X86EMUL_CONTINUE;
4477 }
4478
4479 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4480 void *val, unsigned int bytes,
4481 struct x86_exception *exception,
4482 const struct read_write_emulator_ops *ops)
4483 {
4484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4485 gpa_t gpa;
4486 int rc;
4487
4488 if (ops->read_write_prepare &&
4489 ops->read_write_prepare(vcpu, val, bytes))
4490 return X86EMUL_CONTINUE;
4491
4492 vcpu->mmio_nr_fragments = 0;
4493
4494 /* Crossing a page boundary? */
4495 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4496 int now;
4497
4498 now = -addr & ~PAGE_MASK;
4499 rc = emulator_read_write_onepage(addr, val, now, exception,
4500 vcpu, ops);
4501
4502 if (rc != X86EMUL_CONTINUE)
4503 return rc;
4504 addr += now;
4505 if (ctxt->mode != X86EMUL_MODE_PROT64)
4506 addr = (u32)addr;
4507 val += now;
4508 bytes -= now;
4509 }
4510
4511 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4512 vcpu, ops);
4513 if (rc != X86EMUL_CONTINUE)
4514 return rc;
4515
4516 if (!vcpu->mmio_nr_fragments)
4517 return rc;
4518
4519 gpa = vcpu->mmio_fragments[0].gpa;
4520
4521 vcpu->mmio_needed = 1;
4522 vcpu->mmio_cur_fragment = 0;
4523
4524 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4525 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4526 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4527 vcpu->run->mmio.phys_addr = gpa;
4528
4529 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4530 }
4531
4532 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4533 unsigned long addr,
4534 void *val,
4535 unsigned int bytes,
4536 struct x86_exception *exception)
4537 {
4538 return emulator_read_write(ctxt, addr, val, bytes,
4539 exception, &read_emultor);
4540 }
4541
4542 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4543 unsigned long addr,
4544 const void *val,
4545 unsigned int bytes,
4546 struct x86_exception *exception)
4547 {
4548 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4549 exception, &write_emultor);
4550 }
4551
4552 #define CMPXCHG_TYPE(t, ptr, old, new) \
4553 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4554
4555 #ifdef CONFIG_X86_64
4556 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4557 #else
4558 # define CMPXCHG64(ptr, old, new) \
4559 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4560 #endif
4561
4562 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4563 unsigned long addr,
4564 const void *old,
4565 const void *new,
4566 unsigned int bytes,
4567 struct x86_exception *exception)
4568 {
4569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4570 gpa_t gpa;
4571 struct page *page;
4572 char *kaddr;
4573 bool exchanged;
4574
4575 /* guests cmpxchg8b have to be emulated atomically */
4576 if (bytes > 8 || (bytes & (bytes - 1)))
4577 goto emul_write;
4578
4579 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4580
4581 if (gpa == UNMAPPED_GVA ||
4582 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4583 goto emul_write;
4584
4585 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4586 goto emul_write;
4587
4588 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4589 if (is_error_page(page))
4590 goto emul_write;
4591
4592 kaddr = kmap_atomic(page);
4593 kaddr += offset_in_page(gpa);
4594 switch (bytes) {
4595 case 1:
4596 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4597 break;
4598 case 2:
4599 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4600 break;
4601 case 4:
4602 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4603 break;
4604 case 8:
4605 exchanged = CMPXCHG64(kaddr, old, new);
4606 break;
4607 default:
4608 BUG();
4609 }
4610 kunmap_atomic(kaddr);
4611 kvm_release_page_dirty(page);
4612
4613 if (!exchanged)
4614 return X86EMUL_CMPXCHG_FAILED;
4615
4616 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4617 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4618
4619 return X86EMUL_CONTINUE;
4620
4621 emul_write:
4622 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4623
4624 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4625 }
4626
4627 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4628 {
4629 /* TODO: String I/O for in kernel device */
4630 int r;
4631
4632 if (vcpu->arch.pio.in)
4633 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4634 vcpu->arch.pio.size, pd);
4635 else
4636 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4637 vcpu->arch.pio.port, vcpu->arch.pio.size,
4638 pd);
4639 return r;
4640 }
4641
4642 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4643 unsigned short port, void *val,
4644 unsigned int count, bool in)
4645 {
4646 vcpu->arch.pio.port = port;
4647 vcpu->arch.pio.in = in;
4648 vcpu->arch.pio.count = count;
4649 vcpu->arch.pio.size = size;
4650
4651 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4652 vcpu->arch.pio.count = 0;
4653 return 1;
4654 }
4655
4656 vcpu->run->exit_reason = KVM_EXIT_IO;
4657 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4658 vcpu->run->io.size = size;
4659 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4660 vcpu->run->io.count = count;
4661 vcpu->run->io.port = port;
4662
4663 return 0;
4664 }
4665
4666 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4667 int size, unsigned short port, void *val,
4668 unsigned int count)
4669 {
4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4671 int ret;
4672
4673 if (vcpu->arch.pio.count)
4674 goto data_avail;
4675
4676 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4677 if (ret) {
4678 data_avail:
4679 memcpy(val, vcpu->arch.pio_data, size * count);
4680 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4681 vcpu->arch.pio.count = 0;
4682 return 1;
4683 }
4684
4685 return 0;
4686 }
4687
4688 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4689 int size, unsigned short port,
4690 const void *val, unsigned int count)
4691 {
4692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4693
4694 memcpy(vcpu->arch.pio_data, val, size * count);
4695 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4696 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4697 }
4698
4699 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4700 {
4701 return kvm_x86_ops->get_segment_base(vcpu, seg);
4702 }
4703
4704 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4705 {
4706 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4707 }
4708
4709 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4710 {
4711 if (!need_emulate_wbinvd(vcpu))
4712 return X86EMUL_CONTINUE;
4713
4714 if (kvm_x86_ops->has_wbinvd_exit()) {
4715 int cpu = get_cpu();
4716
4717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4718 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4719 wbinvd_ipi, NULL, 1);
4720 put_cpu();
4721 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4722 } else
4723 wbinvd();
4724 return X86EMUL_CONTINUE;
4725 }
4726 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4727
4728 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4729 {
4730 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4731 }
4732
4733 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4734 {
4735 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4736 }
4737
4738 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4739 {
4740
4741 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4742 }
4743
4744 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4745 {
4746 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4747 }
4748
4749 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4750 {
4751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4752 unsigned long value;
4753
4754 switch (cr) {
4755 case 0:
4756 value = kvm_read_cr0(vcpu);
4757 break;
4758 case 2:
4759 value = vcpu->arch.cr2;
4760 break;
4761 case 3:
4762 value = kvm_read_cr3(vcpu);
4763 break;
4764 case 4:
4765 value = kvm_read_cr4(vcpu);
4766 break;
4767 case 8:
4768 value = kvm_get_cr8(vcpu);
4769 break;
4770 default:
4771 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4772 return 0;
4773 }
4774
4775 return value;
4776 }
4777
4778 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4779 {
4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4781 int res = 0;
4782
4783 switch (cr) {
4784 case 0:
4785 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4786 break;
4787 case 2:
4788 vcpu->arch.cr2 = val;
4789 break;
4790 case 3:
4791 res = kvm_set_cr3(vcpu, val);
4792 break;
4793 case 4:
4794 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4795 break;
4796 case 8:
4797 res = kvm_set_cr8(vcpu, val);
4798 break;
4799 default:
4800 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4801 res = -1;
4802 }
4803
4804 return res;
4805 }
4806
4807 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4808 {
4809 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4810 }
4811
4812 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4813 {
4814 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4815 }
4816
4817 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4818 {
4819 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4820 }
4821
4822 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4823 {
4824 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4825 }
4826
4827 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4828 {
4829 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4830 }
4831
4832 static unsigned long emulator_get_cached_segment_base(
4833 struct x86_emulate_ctxt *ctxt, int seg)
4834 {
4835 return get_segment_base(emul_to_vcpu(ctxt), seg);
4836 }
4837
4838 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4839 struct desc_struct *desc, u32 *base3,
4840 int seg)
4841 {
4842 struct kvm_segment var;
4843
4844 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4845 *selector = var.selector;
4846
4847 if (var.unusable) {
4848 memset(desc, 0, sizeof(*desc));
4849 return false;
4850 }
4851
4852 if (var.g)
4853 var.limit >>= 12;
4854 set_desc_limit(desc, var.limit);
4855 set_desc_base(desc, (unsigned long)var.base);
4856 #ifdef CONFIG_X86_64
4857 if (base3)
4858 *base3 = var.base >> 32;
4859 #endif
4860 desc->type = var.type;
4861 desc->s = var.s;
4862 desc->dpl = var.dpl;
4863 desc->p = var.present;
4864 desc->avl = var.avl;
4865 desc->l = var.l;
4866 desc->d = var.db;
4867 desc->g = var.g;
4868
4869 return true;
4870 }
4871
4872 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4873 struct desc_struct *desc, u32 base3,
4874 int seg)
4875 {
4876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4877 struct kvm_segment var;
4878
4879 var.selector = selector;
4880 var.base = get_desc_base(desc);
4881 #ifdef CONFIG_X86_64
4882 var.base |= ((u64)base3) << 32;
4883 #endif
4884 var.limit = get_desc_limit(desc);
4885 if (desc->g)
4886 var.limit = (var.limit << 12) | 0xfff;
4887 var.type = desc->type;
4888 var.dpl = desc->dpl;
4889 var.db = desc->d;
4890 var.s = desc->s;
4891 var.l = desc->l;
4892 var.g = desc->g;
4893 var.avl = desc->avl;
4894 var.present = desc->p;
4895 var.unusable = !var.present;
4896 var.padding = 0;
4897
4898 kvm_set_segment(vcpu, &var, seg);
4899 return;
4900 }
4901
4902 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4903 u32 msr_index, u64 *pdata)
4904 {
4905 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4906 }
4907
4908 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4909 u32 msr_index, u64 data)
4910 {
4911 struct msr_data msr;
4912
4913 msr.data = data;
4914 msr.index = msr_index;
4915 msr.host_initiated = false;
4916 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4917 }
4918
4919 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4920 u32 pmc)
4921 {
4922 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4923 }
4924
4925 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4926 u32 pmc, u64 *pdata)
4927 {
4928 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4929 }
4930
4931 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4932 {
4933 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4934 }
4935
4936 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4937 {
4938 preempt_disable();
4939 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4940 /*
4941 * CR0.TS may reference the host fpu state, not the guest fpu state,
4942 * so it may be clear at this point.
4943 */
4944 clts();
4945 }
4946
4947 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4948 {
4949 preempt_enable();
4950 }
4951
4952 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4953 struct x86_instruction_info *info,
4954 enum x86_intercept_stage stage)
4955 {
4956 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4957 }
4958
4959 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4960 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4961 {
4962 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4963 }
4964
4965 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4966 {
4967 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4968 }
4969
4970 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4971 {
4972 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4973 }
4974
4975 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4976 {
4977 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4978 }
4979
4980 static const struct x86_emulate_ops emulate_ops = {
4981 .read_gpr = emulator_read_gpr,
4982 .write_gpr = emulator_write_gpr,
4983 .read_std = kvm_read_guest_virt_system,
4984 .write_std = kvm_write_guest_virt_system,
4985 .fetch = kvm_fetch_guest_virt,
4986 .read_emulated = emulator_read_emulated,
4987 .write_emulated = emulator_write_emulated,
4988 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4989 .invlpg = emulator_invlpg,
4990 .pio_in_emulated = emulator_pio_in_emulated,
4991 .pio_out_emulated = emulator_pio_out_emulated,
4992 .get_segment = emulator_get_segment,
4993 .set_segment = emulator_set_segment,
4994 .get_cached_segment_base = emulator_get_cached_segment_base,
4995 .get_gdt = emulator_get_gdt,
4996 .get_idt = emulator_get_idt,
4997 .set_gdt = emulator_set_gdt,
4998 .set_idt = emulator_set_idt,
4999 .get_cr = emulator_get_cr,
5000 .set_cr = emulator_set_cr,
5001 .cpl = emulator_get_cpl,
5002 .get_dr = emulator_get_dr,
5003 .set_dr = emulator_set_dr,
5004 .set_msr = emulator_set_msr,
5005 .get_msr = emulator_get_msr,
5006 .check_pmc = emulator_check_pmc,
5007 .read_pmc = emulator_read_pmc,
5008 .halt = emulator_halt,
5009 .wbinvd = emulator_wbinvd,
5010 .fix_hypercall = emulator_fix_hypercall,
5011 .get_fpu = emulator_get_fpu,
5012 .put_fpu = emulator_put_fpu,
5013 .intercept = emulator_intercept,
5014 .get_cpuid = emulator_get_cpuid,
5015 .set_nmi_mask = emulator_set_nmi_mask,
5016 };
5017
5018 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5019 {
5020 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5021 /*
5022 * an sti; sti; sequence only disable interrupts for the first
5023 * instruction. So, if the last instruction, be it emulated or
5024 * not, left the system with the INT_STI flag enabled, it
5025 * means that the last instruction is an sti. We should not
5026 * leave the flag on in this case. The same goes for mov ss
5027 */
5028 if (int_shadow & mask)
5029 mask = 0;
5030 if (unlikely(int_shadow || mask)) {
5031 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5032 if (!mask)
5033 kvm_make_request(KVM_REQ_EVENT, vcpu);
5034 }
5035 }
5036
5037 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5038 {
5039 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5040 if (ctxt->exception.vector == PF_VECTOR)
5041 return kvm_propagate_fault(vcpu, &ctxt->exception);
5042
5043 if (ctxt->exception.error_code_valid)
5044 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5045 ctxt->exception.error_code);
5046 else
5047 kvm_queue_exception(vcpu, ctxt->exception.vector);
5048 return false;
5049 }
5050
5051 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5052 {
5053 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5054 int cs_db, cs_l;
5055
5056 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5057
5058 ctxt->eflags = kvm_get_rflags(vcpu);
5059 ctxt->eip = kvm_rip_read(vcpu);
5060 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5061 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5062 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5063 cs_db ? X86EMUL_MODE_PROT32 :
5064 X86EMUL_MODE_PROT16;
5065 ctxt->guest_mode = is_guest_mode(vcpu);
5066
5067 init_decode_cache(ctxt);
5068 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5069 }
5070
5071 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5072 {
5073 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5074 int ret;
5075
5076 init_emulate_ctxt(vcpu);
5077
5078 ctxt->op_bytes = 2;
5079 ctxt->ad_bytes = 2;
5080 ctxt->_eip = ctxt->eip + inc_eip;
5081 ret = emulate_int_real(ctxt, irq);
5082
5083 if (ret != X86EMUL_CONTINUE)
5084 return EMULATE_FAIL;
5085
5086 ctxt->eip = ctxt->_eip;
5087 kvm_rip_write(vcpu, ctxt->eip);
5088 kvm_set_rflags(vcpu, ctxt->eflags);
5089
5090 if (irq == NMI_VECTOR)
5091 vcpu->arch.nmi_pending = 0;
5092 else
5093 vcpu->arch.interrupt.pending = false;
5094
5095 return EMULATE_DONE;
5096 }
5097 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5098
5099 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5100 {
5101 int r = EMULATE_DONE;
5102
5103 ++vcpu->stat.insn_emulation_fail;
5104 trace_kvm_emulate_insn_failed(vcpu);
5105 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5106 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5107 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5108 vcpu->run->internal.ndata = 0;
5109 r = EMULATE_FAIL;
5110 }
5111 kvm_queue_exception(vcpu, UD_VECTOR);
5112
5113 return r;
5114 }
5115
5116 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5117 bool write_fault_to_shadow_pgtable,
5118 int emulation_type)
5119 {
5120 gpa_t gpa = cr2;
5121 pfn_t pfn;
5122
5123 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5124 return false;
5125
5126 if (!vcpu->arch.mmu.direct_map) {
5127 /*
5128 * Write permission should be allowed since only
5129 * write access need to be emulated.
5130 */
5131 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5132
5133 /*
5134 * If the mapping is invalid in guest, let cpu retry
5135 * it to generate fault.
5136 */
5137 if (gpa == UNMAPPED_GVA)
5138 return true;
5139 }
5140
5141 /*
5142 * Do not retry the unhandleable instruction if it faults on the
5143 * readonly host memory, otherwise it will goto a infinite loop:
5144 * retry instruction -> write #PF -> emulation fail -> retry
5145 * instruction -> ...
5146 */
5147 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5148
5149 /*
5150 * If the instruction failed on the error pfn, it can not be fixed,
5151 * report the error to userspace.
5152 */
5153 if (is_error_noslot_pfn(pfn))
5154 return false;
5155
5156 kvm_release_pfn_clean(pfn);
5157
5158 /* The instructions are well-emulated on direct mmu. */
5159 if (vcpu->arch.mmu.direct_map) {
5160 unsigned int indirect_shadow_pages;
5161
5162 spin_lock(&vcpu->kvm->mmu_lock);
5163 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5164 spin_unlock(&vcpu->kvm->mmu_lock);
5165
5166 if (indirect_shadow_pages)
5167 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5168
5169 return true;
5170 }
5171
5172 /*
5173 * if emulation was due to access to shadowed page table
5174 * and it failed try to unshadow page and re-enter the
5175 * guest to let CPU execute the instruction.
5176 */
5177 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5178
5179 /*
5180 * If the access faults on its page table, it can not
5181 * be fixed by unprotecting shadow page and it should
5182 * be reported to userspace.
5183 */
5184 return !write_fault_to_shadow_pgtable;
5185 }
5186
5187 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5188 unsigned long cr2, int emulation_type)
5189 {
5190 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5191 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5192
5193 last_retry_eip = vcpu->arch.last_retry_eip;
5194 last_retry_addr = vcpu->arch.last_retry_addr;
5195
5196 /*
5197 * If the emulation is caused by #PF and it is non-page_table
5198 * writing instruction, it means the VM-EXIT is caused by shadow
5199 * page protected, we can zap the shadow page and retry this
5200 * instruction directly.
5201 *
5202 * Note: if the guest uses a non-page-table modifying instruction
5203 * on the PDE that points to the instruction, then we will unmap
5204 * the instruction and go to an infinite loop. So, we cache the
5205 * last retried eip and the last fault address, if we meet the eip
5206 * and the address again, we can break out of the potential infinite
5207 * loop.
5208 */
5209 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5210
5211 if (!(emulation_type & EMULTYPE_RETRY))
5212 return false;
5213
5214 if (x86_page_table_writing_insn(ctxt))
5215 return false;
5216
5217 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5218 return false;
5219
5220 vcpu->arch.last_retry_eip = ctxt->eip;
5221 vcpu->arch.last_retry_addr = cr2;
5222
5223 if (!vcpu->arch.mmu.direct_map)
5224 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5225
5226 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5227
5228 return true;
5229 }
5230
5231 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5232 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5233
5234 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5235 unsigned long *db)
5236 {
5237 u32 dr6 = 0;
5238 int i;
5239 u32 enable, rwlen;
5240
5241 enable = dr7;
5242 rwlen = dr7 >> 16;
5243 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5244 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5245 dr6 |= (1 << i);
5246 return dr6;
5247 }
5248
5249 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5250 {
5251 struct kvm_run *kvm_run = vcpu->run;
5252
5253 /*
5254 * rflags is the old, "raw" value of the flags. The new value has
5255 * not been saved yet.
5256 *
5257 * This is correct even for TF set by the guest, because "the
5258 * processor will not generate this exception after the instruction
5259 * that sets the TF flag".
5260 */
5261 if (unlikely(rflags & X86_EFLAGS_TF)) {
5262 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5263 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5264 DR6_RTM;
5265 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5266 kvm_run->debug.arch.exception = DB_VECTOR;
5267 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5268 *r = EMULATE_USER_EXIT;
5269 } else {
5270 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5271 /*
5272 * "Certain debug exceptions may clear bit 0-3. The
5273 * remaining contents of the DR6 register are never
5274 * cleared by the processor".
5275 */
5276 vcpu->arch.dr6 &= ~15;
5277 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5278 kvm_queue_exception(vcpu, DB_VECTOR);
5279 }
5280 }
5281 }
5282
5283 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5284 {
5285 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5286 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5287 struct kvm_run *kvm_run = vcpu->run;
5288 unsigned long eip = kvm_get_linear_rip(vcpu);
5289 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5290 vcpu->arch.guest_debug_dr7,
5291 vcpu->arch.eff_db);
5292
5293 if (dr6 != 0) {
5294 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5295 kvm_run->debug.arch.pc = eip;
5296 kvm_run->debug.arch.exception = DB_VECTOR;
5297 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5298 *r = EMULATE_USER_EXIT;
5299 return true;
5300 }
5301 }
5302
5303 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5304 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5305 unsigned long eip = kvm_get_linear_rip(vcpu);
5306 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5307 vcpu->arch.dr7,
5308 vcpu->arch.db);
5309
5310 if (dr6 != 0) {
5311 vcpu->arch.dr6 &= ~15;
5312 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5313 kvm_queue_exception(vcpu, DB_VECTOR);
5314 *r = EMULATE_DONE;
5315 return true;
5316 }
5317 }
5318
5319 return false;
5320 }
5321
5322 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5323 unsigned long cr2,
5324 int emulation_type,
5325 void *insn,
5326 int insn_len)
5327 {
5328 int r;
5329 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5330 bool writeback = true;
5331 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5332
5333 /*
5334 * Clear write_fault_to_shadow_pgtable here to ensure it is
5335 * never reused.
5336 */
5337 vcpu->arch.write_fault_to_shadow_pgtable = false;
5338 kvm_clear_exception_queue(vcpu);
5339
5340 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5341 init_emulate_ctxt(vcpu);
5342
5343 /*
5344 * We will reenter on the same instruction since
5345 * we do not set complete_userspace_io. This does not
5346 * handle watchpoints yet, those would be handled in
5347 * the emulate_ops.
5348 */
5349 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5350 return r;
5351
5352 ctxt->interruptibility = 0;
5353 ctxt->have_exception = false;
5354 ctxt->exception.vector = -1;
5355 ctxt->perm_ok = false;
5356
5357 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5358
5359 r = x86_decode_insn(ctxt, insn, insn_len);
5360
5361 trace_kvm_emulate_insn_start(vcpu);
5362 ++vcpu->stat.insn_emulation;
5363 if (r != EMULATION_OK) {
5364 if (emulation_type & EMULTYPE_TRAP_UD)
5365 return EMULATE_FAIL;
5366 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5367 emulation_type))
5368 return EMULATE_DONE;
5369 if (emulation_type & EMULTYPE_SKIP)
5370 return EMULATE_FAIL;
5371 return handle_emulation_failure(vcpu);
5372 }
5373 }
5374
5375 if (emulation_type & EMULTYPE_SKIP) {
5376 kvm_rip_write(vcpu, ctxt->_eip);
5377 if (ctxt->eflags & X86_EFLAGS_RF)
5378 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5379 return EMULATE_DONE;
5380 }
5381
5382 if (retry_instruction(ctxt, cr2, emulation_type))
5383 return EMULATE_DONE;
5384
5385 /* this is needed for vmware backdoor interface to work since it
5386 changes registers values during IO operation */
5387 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5388 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5389 emulator_invalidate_register_cache(ctxt);
5390 }
5391
5392 restart:
5393 r = x86_emulate_insn(ctxt);
5394
5395 if (r == EMULATION_INTERCEPTED)
5396 return EMULATE_DONE;
5397
5398 if (r == EMULATION_FAILED) {
5399 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5400 emulation_type))
5401 return EMULATE_DONE;
5402
5403 return handle_emulation_failure(vcpu);
5404 }
5405
5406 if (ctxt->have_exception) {
5407 r = EMULATE_DONE;
5408 if (inject_emulated_exception(vcpu))
5409 return r;
5410 } else if (vcpu->arch.pio.count) {
5411 if (!vcpu->arch.pio.in) {
5412 /* FIXME: return into emulator if single-stepping. */
5413 vcpu->arch.pio.count = 0;
5414 } else {
5415 writeback = false;
5416 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5417 }
5418 r = EMULATE_USER_EXIT;
5419 } else if (vcpu->mmio_needed) {
5420 if (!vcpu->mmio_is_write)
5421 writeback = false;
5422 r = EMULATE_USER_EXIT;
5423 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5424 } else if (r == EMULATION_RESTART)
5425 goto restart;
5426 else
5427 r = EMULATE_DONE;
5428
5429 if (writeback) {
5430 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5431 toggle_interruptibility(vcpu, ctxt->interruptibility);
5432 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5433 kvm_rip_write(vcpu, ctxt->eip);
5434 if (r == EMULATE_DONE)
5435 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5436 if (!ctxt->have_exception ||
5437 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5438 __kvm_set_rflags(vcpu, ctxt->eflags);
5439
5440 /*
5441 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5442 * do nothing, and it will be requested again as soon as
5443 * the shadow expires. But we still need to check here,
5444 * because POPF has no interrupt shadow.
5445 */
5446 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5447 kvm_make_request(KVM_REQ_EVENT, vcpu);
5448 } else
5449 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5450
5451 return r;
5452 }
5453 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5454
5455 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5456 {
5457 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5458 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5459 size, port, &val, 1);
5460 /* do not return to emulator after return from userspace */
5461 vcpu->arch.pio.count = 0;
5462 return ret;
5463 }
5464 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5465
5466 static void tsc_bad(void *info)
5467 {
5468 __this_cpu_write(cpu_tsc_khz, 0);
5469 }
5470
5471 static void tsc_khz_changed(void *data)
5472 {
5473 struct cpufreq_freqs *freq = data;
5474 unsigned long khz = 0;
5475
5476 if (data)
5477 khz = freq->new;
5478 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5479 khz = cpufreq_quick_get(raw_smp_processor_id());
5480 if (!khz)
5481 khz = tsc_khz;
5482 __this_cpu_write(cpu_tsc_khz, khz);
5483 }
5484
5485 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5486 void *data)
5487 {
5488 struct cpufreq_freqs *freq = data;
5489 struct kvm *kvm;
5490 struct kvm_vcpu *vcpu;
5491 int i, send_ipi = 0;
5492
5493 /*
5494 * We allow guests to temporarily run on slowing clocks,
5495 * provided we notify them after, or to run on accelerating
5496 * clocks, provided we notify them before. Thus time never
5497 * goes backwards.
5498 *
5499 * However, we have a problem. We can't atomically update
5500 * the frequency of a given CPU from this function; it is
5501 * merely a notifier, which can be called from any CPU.
5502 * Changing the TSC frequency at arbitrary points in time
5503 * requires a recomputation of local variables related to
5504 * the TSC for each VCPU. We must flag these local variables
5505 * to be updated and be sure the update takes place with the
5506 * new frequency before any guests proceed.
5507 *
5508 * Unfortunately, the combination of hotplug CPU and frequency
5509 * change creates an intractable locking scenario; the order
5510 * of when these callouts happen is undefined with respect to
5511 * CPU hotplug, and they can race with each other. As such,
5512 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5513 * undefined; you can actually have a CPU frequency change take
5514 * place in between the computation of X and the setting of the
5515 * variable. To protect against this problem, all updates of
5516 * the per_cpu tsc_khz variable are done in an interrupt
5517 * protected IPI, and all callers wishing to update the value
5518 * must wait for a synchronous IPI to complete (which is trivial
5519 * if the caller is on the CPU already). This establishes the
5520 * necessary total order on variable updates.
5521 *
5522 * Note that because a guest time update may take place
5523 * anytime after the setting of the VCPU's request bit, the
5524 * correct TSC value must be set before the request. However,
5525 * to ensure the update actually makes it to any guest which
5526 * starts running in hardware virtualization between the set
5527 * and the acquisition of the spinlock, we must also ping the
5528 * CPU after setting the request bit.
5529 *
5530 */
5531
5532 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5533 return 0;
5534 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5535 return 0;
5536
5537 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5538
5539 spin_lock(&kvm_lock);
5540 list_for_each_entry(kvm, &vm_list, vm_list) {
5541 kvm_for_each_vcpu(i, vcpu, kvm) {
5542 if (vcpu->cpu != freq->cpu)
5543 continue;
5544 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5545 if (vcpu->cpu != smp_processor_id())
5546 send_ipi = 1;
5547 }
5548 }
5549 spin_unlock(&kvm_lock);
5550
5551 if (freq->old < freq->new && send_ipi) {
5552 /*
5553 * We upscale the frequency. Must make the guest
5554 * doesn't see old kvmclock values while running with
5555 * the new frequency, otherwise we risk the guest sees
5556 * time go backwards.
5557 *
5558 * In case we update the frequency for another cpu
5559 * (which might be in guest context) send an interrupt
5560 * to kick the cpu out of guest context. Next time
5561 * guest context is entered kvmclock will be updated,
5562 * so the guest will not see stale values.
5563 */
5564 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5565 }
5566 return 0;
5567 }
5568
5569 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5570 .notifier_call = kvmclock_cpufreq_notifier
5571 };
5572
5573 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5574 unsigned long action, void *hcpu)
5575 {
5576 unsigned int cpu = (unsigned long)hcpu;
5577
5578 switch (action) {
5579 case CPU_ONLINE:
5580 case CPU_DOWN_FAILED:
5581 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5582 break;
5583 case CPU_DOWN_PREPARE:
5584 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5585 break;
5586 }
5587 return NOTIFY_OK;
5588 }
5589
5590 static struct notifier_block kvmclock_cpu_notifier_block = {
5591 .notifier_call = kvmclock_cpu_notifier,
5592 .priority = -INT_MAX
5593 };
5594
5595 static void kvm_timer_init(void)
5596 {
5597 int cpu;
5598
5599 max_tsc_khz = tsc_khz;
5600
5601 cpu_notifier_register_begin();
5602 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5603 #ifdef CONFIG_CPU_FREQ
5604 struct cpufreq_policy policy;
5605 memset(&policy, 0, sizeof(policy));
5606 cpu = get_cpu();
5607 cpufreq_get_policy(&policy, cpu);
5608 if (policy.cpuinfo.max_freq)
5609 max_tsc_khz = policy.cpuinfo.max_freq;
5610 put_cpu();
5611 #endif
5612 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5613 CPUFREQ_TRANSITION_NOTIFIER);
5614 }
5615 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5616 for_each_online_cpu(cpu)
5617 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5618
5619 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5620 cpu_notifier_register_done();
5621
5622 }
5623
5624 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5625
5626 int kvm_is_in_guest(void)
5627 {
5628 return __this_cpu_read(current_vcpu) != NULL;
5629 }
5630
5631 static int kvm_is_user_mode(void)
5632 {
5633 int user_mode = 3;
5634
5635 if (__this_cpu_read(current_vcpu))
5636 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5637
5638 return user_mode != 0;
5639 }
5640
5641 static unsigned long kvm_get_guest_ip(void)
5642 {
5643 unsigned long ip = 0;
5644
5645 if (__this_cpu_read(current_vcpu))
5646 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5647
5648 return ip;
5649 }
5650
5651 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5652 .is_in_guest = kvm_is_in_guest,
5653 .is_user_mode = kvm_is_user_mode,
5654 .get_guest_ip = kvm_get_guest_ip,
5655 };
5656
5657 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5658 {
5659 __this_cpu_write(current_vcpu, vcpu);
5660 }
5661 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5662
5663 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5664 {
5665 __this_cpu_write(current_vcpu, NULL);
5666 }
5667 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5668
5669 static void kvm_set_mmio_spte_mask(void)
5670 {
5671 u64 mask;
5672 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5673
5674 /*
5675 * Set the reserved bits and the present bit of an paging-structure
5676 * entry to generate page fault with PFER.RSV = 1.
5677 */
5678 /* Mask the reserved physical address bits. */
5679 mask = rsvd_bits(maxphyaddr, 51);
5680
5681 /* Bit 62 is always reserved for 32bit host. */
5682 mask |= 0x3ull << 62;
5683
5684 /* Set the present bit. */
5685 mask |= 1ull;
5686
5687 #ifdef CONFIG_X86_64
5688 /*
5689 * If reserved bit is not supported, clear the present bit to disable
5690 * mmio page fault.
5691 */
5692 if (maxphyaddr == 52)
5693 mask &= ~1ull;
5694 #endif
5695
5696 kvm_mmu_set_mmio_spte_mask(mask);
5697 }
5698
5699 #ifdef CONFIG_X86_64
5700 static void pvclock_gtod_update_fn(struct work_struct *work)
5701 {
5702 struct kvm *kvm;
5703
5704 struct kvm_vcpu *vcpu;
5705 int i;
5706
5707 spin_lock(&kvm_lock);
5708 list_for_each_entry(kvm, &vm_list, vm_list)
5709 kvm_for_each_vcpu(i, vcpu, kvm)
5710 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5711 atomic_set(&kvm_guest_has_master_clock, 0);
5712 spin_unlock(&kvm_lock);
5713 }
5714
5715 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5716
5717 /*
5718 * Notification about pvclock gtod data update.
5719 */
5720 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5721 void *priv)
5722 {
5723 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5724 struct timekeeper *tk = priv;
5725
5726 update_pvclock_gtod(tk);
5727
5728 /* disable master clock if host does not trust, or does not
5729 * use, TSC clocksource
5730 */
5731 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5732 atomic_read(&kvm_guest_has_master_clock) != 0)
5733 queue_work(system_long_wq, &pvclock_gtod_work);
5734
5735 return 0;
5736 }
5737
5738 static struct notifier_block pvclock_gtod_notifier = {
5739 .notifier_call = pvclock_gtod_notify,
5740 };
5741 #endif
5742
5743 int kvm_arch_init(void *opaque)
5744 {
5745 int r;
5746 struct kvm_x86_ops *ops = opaque;
5747
5748 if (kvm_x86_ops) {
5749 printk(KERN_ERR "kvm: already loaded the other module\n");
5750 r = -EEXIST;
5751 goto out;
5752 }
5753
5754 if (!ops->cpu_has_kvm_support()) {
5755 printk(KERN_ERR "kvm: no hardware support\n");
5756 r = -EOPNOTSUPP;
5757 goto out;
5758 }
5759 if (ops->disabled_by_bios()) {
5760 printk(KERN_ERR "kvm: disabled by bios\n");
5761 r = -EOPNOTSUPP;
5762 goto out;
5763 }
5764
5765 r = -ENOMEM;
5766 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5767 if (!shared_msrs) {
5768 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5769 goto out;
5770 }
5771
5772 r = kvm_mmu_module_init();
5773 if (r)
5774 goto out_free_percpu;
5775
5776 kvm_set_mmio_spte_mask();
5777
5778 kvm_x86_ops = ops;
5779 kvm_init_msr_list();
5780
5781 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5782 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5783
5784 kvm_timer_init();
5785
5786 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5787
5788 if (cpu_has_xsave)
5789 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5790
5791 kvm_lapic_init();
5792 #ifdef CONFIG_X86_64
5793 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5794 #endif
5795
5796 return 0;
5797
5798 out_free_percpu:
5799 free_percpu(shared_msrs);
5800 out:
5801 return r;
5802 }
5803
5804 void kvm_arch_exit(void)
5805 {
5806 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5807
5808 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5809 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5810 CPUFREQ_TRANSITION_NOTIFIER);
5811 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5812 #ifdef CONFIG_X86_64
5813 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5814 #endif
5815 kvm_x86_ops = NULL;
5816 kvm_mmu_module_exit();
5817 free_percpu(shared_msrs);
5818 }
5819
5820 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5821 {
5822 ++vcpu->stat.halt_exits;
5823 if (irqchip_in_kernel(vcpu->kvm)) {
5824 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5825 return 1;
5826 } else {
5827 vcpu->run->exit_reason = KVM_EXIT_HLT;
5828 return 0;
5829 }
5830 }
5831 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5832
5833 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5834 {
5835 u64 param, ingpa, outgpa, ret;
5836 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5837 bool fast, longmode;
5838
5839 /*
5840 * hypercall generates UD from non zero cpl and real mode
5841 * per HYPER-V spec
5842 */
5843 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5844 kvm_queue_exception(vcpu, UD_VECTOR);
5845 return 0;
5846 }
5847
5848 longmode = is_64_bit_mode(vcpu);
5849
5850 if (!longmode) {
5851 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5852 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5853 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5854 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5855 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5856 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5857 }
5858 #ifdef CONFIG_X86_64
5859 else {
5860 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5861 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5862 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5863 }
5864 #endif
5865
5866 code = param & 0xffff;
5867 fast = (param >> 16) & 0x1;
5868 rep_cnt = (param >> 32) & 0xfff;
5869 rep_idx = (param >> 48) & 0xfff;
5870
5871 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5872
5873 switch (code) {
5874 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5875 kvm_vcpu_on_spin(vcpu);
5876 break;
5877 default:
5878 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5879 break;
5880 }
5881
5882 ret = res | (((u64)rep_done & 0xfff) << 32);
5883 if (longmode) {
5884 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5885 } else {
5886 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5887 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5888 }
5889
5890 return 1;
5891 }
5892
5893 /*
5894 * kvm_pv_kick_cpu_op: Kick a vcpu.
5895 *
5896 * @apicid - apicid of vcpu to be kicked.
5897 */
5898 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5899 {
5900 struct kvm_lapic_irq lapic_irq;
5901
5902 lapic_irq.shorthand = 0;
5903 lapic_irq.dest_mode = 0;
5904 lapic_irq.dest_id = apicid;
5905
5906 lapic_irq.delivery_mode = APIC_DM_REMRD;
5907 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5908 }
5909
5910 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5911 {
5912 unsigned long nr, a0, a1, a2, a3, ret;
5913 int op_64_bit, r = 1;
5914
5915 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5916 return kvm_hv_hypercall(vcpu);
5917
5918 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5919 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5920 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5921 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5922 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5923
5924 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5925
5926 op_64_bit = is_64_bit_mode(vcpu);
5927 if (!op_64_bit) {
5928 nr &= 0xFFFFFFFF;
5929 a0 &= 0xFFFFFFFF;
5930 a1 &= 0xFFFFFFFF;
5931 a2 &= 0xFFFFFFFF;
5932 a3 &= 0xFFFFFFFF;
5933 }
5934
5935 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5936 ret = -KVM_EPERM;
5937 goto out;
5938 }
5939
5940 switch (nr) {
5941 case KVM_HC_VAPIC_POLL_IRQ:
5942 ret = 0;
5943 break;
5944 case KVM_HC_KICK_CPU:
5945 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5946 ret = 0;
5947 break;
5948 default:
5949 ret = -KVM_ENOSYS;
5950 break;
5951 }
5952 out:
5953 if (!op_64_bit)
5954 ret = (u32)ret;
5955 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5956 ++vcpu->stat.hypercalls;
5957 return r;
5958 }
5959 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5960
5961 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5962 {
5963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5964 char instruction[3];
5965 unsigned long rip = kvm_rip_read(vcpu);
5966
5967 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5968
5969 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5970 }
5971
5972 /*
5973 * Check if userspace requested an interrupt window, and that the
5974 * interrupt window is open.
5975 *
5976 * No need to exit to userspace if we already have an interrupt queued.
5977 */
5978 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5979 {
5980 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5981 vcpu->run->request_interrupt_window &&
5982 kvm_arch_interrupt_allowed(vcpu));
5983 }
5984
5985 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5986 {
5987 struct kvm_run *kvm_run = vcpu->run;
5988
5989 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5990 kvm_run->cr8 = kvm_get_cr8(vcpu);
5991 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5992 if (irqchip_in_kernel(vcpu->kvm))
5993 kvm_run->ready_for_interrupt_injection = 1;
5994 else
5995 kvm_run->ready_for_interrupt_injection =
5996 kvm_arch_interrupt_allowed(vcpu) &&
5997 !kvm_cpu_has_interrupt(vcpu) &&
5998 !kvm_event_needs_reinjection(vcpu);
5999 }
6000
6001 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6002 {
6003 int max_irr, tpr;
6004
6005 if (!kvm_x86_ops->update_cr8_intercept)
6006 return;
6007
6008 if (!vcpu->arch.apic)
6009 return;
6010
6011 if (!vcpu->arch.apic->vapic_addr)
6012 max_irr = kvm_lapic_find_highest_irr(vcpu);
6013 else
6014 max_irr = -1;
6015
6016 if (max_irr != -1)
6017 max_irr >>= 4;
6018
6019 tpr = kvm_lapic_get_cr8(vcpu);
6020
6021 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6022 }
6023
6024 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6025 {
6026 int r;
6027
6028 /* try to reinject previous events if any */
6029 if (vcpu->arch.exception.pending) {
6030 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6031 vcpu->arch.exception.has_error_code,
6032 vcpu->arch.exception.error_code);
6033
6034 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6035 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6036 X86_EFLAGS_RF);
6037
6038 if (vcpu->arch.exception.nr == DB_VECTOR &&
6039 (vcpu->arch.dr7 & DR7_GD)) {
6040 vcpu->arch.dr7 &= ~DR7_GD;
6041 kvm_update_dr7(vcpu);
6042 }
6043
6044 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6045 vcpu->arch.exception.has_error_code,
6046 vcpu->arch.exception.error_code,
6047 vcpu->arch.exception.reinject);
6048 return 0;
6049 }
6050
6051 if (vcpu->arch.nmi_injected) {
6052 kvm_x86_ops->set_nmi(vcpu);
6053 return 0;
6054 }
6055
6056 if (vcpu->arch.interrupt.pending) {
6057 kvm_x86_ops->set_irq(vcpu);
6058 return 0;
6059 }
6060
6061 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6062 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6063 if (r != 0)
6064 return r;
6065 }
6066
6067 /* try to inject new event if pending */
6068 if (vcpu->arch.nmi_pending) {
6069 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6070 --vcpu->arch.nmi_pending;
6071 vcpu->arch.nmi_injected = true;
6072 kvm_x86_ops->set_nmi(vcpu);
6073 }
6074 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6075 /*
6076 * Because interrupts can be injected asynchronously, we are
6077 * calling check_nested_events again here to avoid a race condition.
6078 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6079 * proposal and current concerns. Perhaps we should be setting
6080 * KVM_REQ_EVENT only on certain events and not unconditionally?
6081 */
6082 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6083 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6084 if (r != 0)
6085 return r;
6086 }
6087 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6088 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6089 false);
6090 kvm_x86_ops->set_irq(vcpu);
6091 }
6092 }
6093 return 0;
6094 }
6095
6096 static void process_nmi(struct kvm_vcpu *vcpu)
6097 {
6098 unsigned limit = 2;
6099
6100 /*
6101 * x86 is limited to one NMI running, and one NMI pending after it.
6102 * If an NMI is already in progress, limit further NMIs to just one.
6103 * Otherwise, allow two (and we'll inject the first one immediately).
6104 */
6105 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6106 limit = 1;
6107
6108 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6109 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6110 kvm_make_request(KVM_REQ_EVENT, vcpu);
6111 }
6112
6113 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6114 {
6115 u64 eoi_exit_bitmap[4];
6116 u32 tmr[8];
6117
6118 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6119 return;
6120
6121 memset(eoi_exit_bitmap, 0, 32);
6122 memset(tmr, 0, 32);
6123
6124 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6125 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6126 kvm_apic_update_tmr(vcpu, tmr);
6127 }
6128
6129 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6130 {
6131 ++vcpu->stat.tlb_flush;
6132 kvm_x86_ops->tlb_flush(vcpu);
6133 }
6134
6135 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6136 {
6137 struct page *page = NULL;
6138
6139 if (!irqchip_in_kernel(vcpu->kvm))
6140 return;
6141
6142 if (!kvm_x86_ops->set_apic_access_page_addr)
6143 return;
6144
6145 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6146 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6147
6148 /*
6149 * Do not pin apic access page in memory, the MMU notifier
6150 * will call us again if it is migrated or swapped out.
6151 */
6152 put_page(page);
6153 }
6154 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6155
6156 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6157 unsigned long address)
6158 {
6159 /*
6160 * The physical address of apic access page is stored in the VMCS.
6161 * Update it when it becomes invalid.
6162 */
6163 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6164 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6165 }
6166
6167 /*
6168 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6169 * exiting to the userspace. Otherwise, the value will be returned to the
6170 * userspace.
6171 */
6172 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6173 {
6174 int r;
6175 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6176 vcpu->run->request_interrupt_window;
6177 bool req_immediate_exit = false;
6178
6179 if (vcpu->requests) {
6180 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6181 kvm_mmu_unload(vcpu);
6182 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6183 __kvm_migrate_timers(vcpu);
6184 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6185 kvm_gen_update_masterclock(vcpu->kvm);
6186 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6187 kvm_gen_kvmclock_update(vcpu);
6188 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6189 r = kvm_guest_time_update(vcpu);
6190 if (unlikely(r))
6191 goto out;
6192 }
6193 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6194 kvm_mmu_sync_roots(vcpu);
6195 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6196 kvm_vcpu_flush_tlb(vcpu);
6197 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6198 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6199 r = 0;
6200 goto out;
6201 }
6202 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6203 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6204 r = 0;
6205 goto out;
6206 }
6207 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6208 vcpu->fpu_active = 0;
6209 kvm_x86_ops->fpu_deactivate(vcpu);
6210 }
6211 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6212 /* Page is swapped out. Do synthetic halt */
6213 vcpu->arch.apf.halted = true;
6214 r = 1;
6215 goto out;
6216 }
6217 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6218 record_steal_time(vcpu);
6219 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6220 process_nmi(vcpu);
6221 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6222 kvm_handle_pmu_event(vcpu);
6223 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6224 kvm_deliver_pmi(vcpu);
6225 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6226 vcpu_scan_ioapic(vcpu);
6227 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6228 kvm_vcpu_reload_apic_access_page(vcpu);
6229 }
6230
6231 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6232 kvm_apic_accept_events(vcpu);
6233 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6234 r = 1;
6235 goto out;
6236 }
6237
6238 if (inject_pending_event(vcpu, req_int_win) != 0)
6239 req_immediate_exit = true;
6240 /* enable NMI/IRQ window open exits if needed */
6241 else if (vcpu->arch.nmi_pending)
6242 kvm_x86_ops->enable_nmi_window(vcpu);
6243 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6244 kvm_x86_ops->enable_irq_window(vcpu);
6245
6246 if (kvm_lapic_enabled(vcpu)) {
6247 /*
6248 * Update architecture specific hints for APIC
6249 * virtual interrupt delivery.
6250 */
6251 if (kvm_x86_ops->hwapic_irr_update)
6252 kvm_x86_ops->hwapic_irr_update(vcpu,
6253 kvm_lapic_find_highest_irr(vcpu));
6254 update_cr8_intercept(vcpu);
6255 kvm_lapic_sync_to_vapic(vcpu);
6256 }
6257 }
6258
6259 r = kvm_mmu_reload(vcpu);
6260 if (unlikely(r)) {
6261 goto cancel_injection;
6262 }
6263
6264 preempt_disable();
6265
6266 kvm_x86_ops->prepare_guest_switch(vcpu);
6267 if (vcpu->fpu_active)
6268 kvm_load_guest_fpu(vcpu);
6269 kvm_load_guest_xcr0(vcpu);
6270
6271 vcpu->mode = IN_GUEST_MODE;
6272
6273 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6274
6275 /* We should set ->mode before check ->requests,
6276 * see the comment in make_all_cpus_request.
6277 */
6278 smp_mb__after_srcu_read_unlock();
6279
6280 local_irq_disable();
6281
6282 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6283 || need_resched() || signal_pending(current)) {
6284 vcpu->mode = OUTSIDE_GUEST_MODE;
6285 smp_wmb();
6286 local_irq_enable();
6287 preempt_enable();
6288 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6289 r = 1;
6290 goto cancel_injection;
6291 }
6292
6293 if (req_immediate_exit)
6294 smp_send_reschedule(vcpu->cpu);
6295
6296 kvm_guest_enter();
6297
6298 if (unlikely(vcpu->arch.switch_db_regs)) {
6299 set_debugreg(0, 7);
6300 set_debugreg(vcpu->arch.eff_db[0], 0);
6301 set_debugreg(vcpu->arch.eff_db[1], 1);
6302 set_debugreg(vcpu->arch.eff_db[2], 2);
6303 set_debugreg(vcpu->arch.eff_db[3], 3);
6304 set_debugreg(vcpu->arch.dr6, 6);
6305 }
6306
6307 trace_kvm_entry(vcpu->vcpu_id);
6308 wait_lapic_expire(vcpu);
6309 kvm_x86_ops->run(vcpu);
6310
6311 /*
6312 * Do this here before restoring debug registers on the host. And
6313 * since we do this before handling the vmexit, a DR access vmexit
6314 * can (a) read the correct value of the debug registers, (b) set
6315 * KVM_DEBUGREG_WONT_EXIT again.
6316 */
6317 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6318 int i;
6319
6320 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6321 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6322 for (i = 0; i < KVM_NR_DB_REGS; i++)
6323 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6324 }
6325
6326 /*
6327 * If the guest has used debug registers, at least dr7
6328 * will be disabled while returning to the host.
6329 * If we don't have active breakpoints in the host, we don't
6330 * care about the messed up debug address registers. But if
6331 * we have some of them active, restore the old state.
6332 */
6333 if (hw_breakpoint_active())
6334 hw_breakpoint_restore();
6335
6336 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6337 native_read_tsc());
6338
6339 vcpu->mode = OUTSIDE_GUEST_MODE;
6340 smp_wmb();
6341
6342 /* Interrupt is enabled by handle_external_intr() */
6343 kvm_x86_ops->handle_external_intr(vcpu);
6344
6345 ++vcpu->stat.exits;
6346
6347 /*
6348 * We must have an instruction between local_irq_enable() and
6349 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6350 * the interrupt shadow. The stat.exits increment will do nicely.
6351 * But we need to prevent reordering, hence this barrier():
6352 */
6353 barrier();
6354
6355 kvm_guest_exit();
6356
6357 preempt_enable();
6358
6359 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6360
6361 /*
6362 * Profile KVM exit RIPs:
6363 */
6364 if (unlikely(prof_on == KVM_PROFILING)) {
6365 unsigned long rip = kvm_rip_read(vcpu);
6366 profile_hit(KVM_PROFILING, (void *)rip);
6367 }
6368
6369 if (unlikely(vcpu->arch.tsc_always_catchup))
6370 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6371
6372 if (vcpu->arch.apic_attention)
6373 kvm_lapic_sync_from_vapic(vcpu);
6374
6375 r = kvm_x86_ops->handle_exit(vcpu);
6376 return r;
6377
6378 cancel_injection:
6379 kvm_x86_ops->cancel_injection(vcpu);
6380 if (unlikely(vcpu->arch.apic_attention))
6381 kvm_lapic_sync_from_vapic(vcpu);
6382 out:
6383 return r;
6384 }
6385
6386
6387 static int __vcpu_run(struct kvm_vcpu *vcpu)
6388 {
6389 int r;
6390 struct kvm *kvm = vcpu->kvm;
6391
6392 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6393
6394 r = 1;
6395 while (r > 0) {
6396 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6397 !vcpu->arch.apf.halted)
6398 r = vcpu_enter_guest(vcpu);
6399 else {
6400 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6401 kvm_vcpu_block(vcpu);
6402 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6403 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6404 kvm_apic_accept_events(vcpu);
6405 switch(vcpu->arch.mp_state) {
6406 case KVM_MP_STATE_HALTED:
6407 vcpu->arch.pv.pv_unhalted = false;
6408 vcpu->arch.mp_state =
6409 KVM_MP_STATE_RUNNABLE;
6410 case KVM_MP_STATE_RUNNABLE:
6411 vcpu->arch.apf.halted = false;
6412 break;
6413 case KVM_MP_STATE_INIT_RECEIVED:
6414 break;
6415 default:
6416 r = -EINTR;
6417 break;
6418 }
6419 }
6420 }
6421
6422 if (r <= 0)
6423 break;
6424
6425 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6426 if (kvm_cpu_has_pending_timer(vcpu))
6427 kvm_inject_pending_timer_irqs(vcpu);
6428
6429 if (dm_request_for_irq_injection(vcpu)) {
6430 r = -EINTR;
6431 vcpu->run->exit_reason = KVM_EXIT_INTR;
6432 ++vcpu->stat.request_irq_exits;
6433 }
6434
6435 kvm_check_async_pf_completion(vcpu);
6436
6437 if (signal_pending(current)) {
6438 r = -EINTR;
6439 vcpu->run->exit_reason = KVM_EXIT_INTR;
6440 ++vcpu->stat.signal_exits;
6441 }
6442 if (need_resched()) {
6443 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6444 cond_resched();
6445 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6446 }
6447 }
6448
6449 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6450
6451 return r;
6452 }
6453
6454 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6455 {
6456 int r;
6457 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6458 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6459 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6460 if (r != EMULATE_DONE)
6461 return 0;
6462 return 1;
6463 }
6464
6465 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6466 {
6467 BUG_ON(!vcpu->arch.pio.count);
6468
6469 return complete_emulated_io(vcpu);
6470 }
6471
6472 /*
6473 * Implements the following, as a state machine:
6474 *
6475 * read:
6476 * for each fragment
6477 * for each mmio piece in the fragment
6478 * write gpa, len
6479 * exit
6480 * copy data
6481 * execute insn
6482 *
6483 * write:
6484 * for each fragment
6485 * for each mmio piece in the fragment
6486 * write gpa, len
6487 * copy data
6488 * exit
6489 */
6490 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6491 {
6492 struct kvm_run *run = vcpu->run;
6493 struct kvm_mmio_fragment *frag;
6494 unsigned len;
6495
6496 BUG_ON(!vcpu->mmio_needed);
6497
6498 /* Complete previous fragment */
6499 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6500 len = min(8u, frag->len);
6501 if (!vcpu->mmio_is_write)
6502 memcpy(frag->data, run->mmio.data, len);
6503
6504 if (frag->len <= 8) {
6505 /* Switch to the next fragment. */
6506 frag++;
6507 vcpu->mmio_cur_fragment++;
6508 } else {
6509 /* Go forward to the next mmio piece. */
6510 frag->data += len;
6511 frag->gpa += len;
6512 frag->len -= len;
6513 }
6514
6515 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6516 vcpu->mmio_needed = 0;
6517
6518 /* FIXME: return into emulator if single-stepping. */
6519 if (vcpu->mmio_is_write)
6520 return 1;
6521 vcpu->mmio_read_completed = 1;
6522 return complete_emulated_io(vcpu);
6523 }
6524
6525 run->exit_reason = KVM_EXIT_MMIO;
6526 run->mmio.phys_addr = frag->gpa;
6527 if (vcpu->mmio_is_write)
6528 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6529 run->mmio.len = min(8u, frag->len);
6530 run->mmio.is_write = vcpu->mmio_is_write;
6531 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6532 return 0;
6533 }
6534
6535
6536 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6537 {
6538 int r;
6539 sigset_t sigsaved;
6540
6541 if (!tsk_used_math(current) && init_fpu(current))
6542 return -ENOMEM;
6543
6544 if (vcpu->sigset_active)
6545 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6546
6547 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6548 kvm_vcpu_block(vcpu);
6549 kvm_apic_accept_events(vcpu);
6550 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6551 r = -EAGAIN;
6552 goto out;
6553 }
6554
6555 /* re-sync apic's tpr */
6556 if (!irqchip_in_kernel(vcpu->kvm)) {
6557 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6558 r = -EINVAL;
6559 goto out;
6560 }
6561 }
6562
6563 if (unlikely(vcpu->arch.complete_userspace_io)) {
6564 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6565 vcpu->arch.complete_userspace_io = NULL;
6566 r = cui(vcpu);
6567 if (r <= 0)
6568 goto out;
6569 } else
6570 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6571
6572 r = __vcpu_run(vcpu);
6573
6574 out:
6575 post_kvm_run_save(vcpu);
6576 if (vcpu->sigset_active)
6577 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6578
6579 return r;
6580 }
6581
6582 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6583 {
6584 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6585 /*
6586 * We are here if userspace calls get_regs() in the middle of
6587 * instruction emulation. Registers state needs to be copied
6588 * back from emulation context to vcpu. Userspace shouldn't do
6589 * that usually, but some bad designed PV devices (vmware
6590 * backdoor interface) need this to work
6591 */
6592 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6593 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6594 }
6595 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6596 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6597 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6598 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6599 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6600 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6601 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6602 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6603 #ifdef CONFIG_X86_64
6604 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6605 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6606 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6607 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6608 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6609 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6610 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6611 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6612 #endif
6613
6614 regs->rip = kvm_rip_read(vcpu);
6615 regs->rflags = kvm_get_rflags(vcpu);
6616
6617 return 0;
6618 }
6619
6620 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6621 {
6622 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6623 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6624
6625 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6626 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6627 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6628 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6629 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6630 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6631 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6632 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6633 #ifdef CONFIG_X86_64
6634 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6635 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6636 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6637 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6638 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6639 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6640 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6641 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6642 #endif
6643
6644 kvm_rip_write(vcpu, regs->rip);
6645 kvm_set_rflags(vcpu, regs->rflags);
6646
6647 vcpu->arch.exception.pending = false;
6648
6649 kvm_make_request(KVM_REQ_EVENT, vcpu);
6650
6651 return 0;
6652 }
6653
6654 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6655 {
6656 struct kvm_segment cs;
6657
6658 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6659 *db = cs.db;
6660 *l = cs.l;
6661 }
6662 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6663
6664 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6665 struct kvm_sregs *sregs)
6666 {
6667 struct desc_ptr dt;
6668
6669 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6670 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6671 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6672 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6673 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6674 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6675
6676 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6677 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6678
6679 kvm_x86_ops->get_idt(vcpu, &dt);
6680 sregs->idt.limit = dt.size;
6681 sregs->idt.base = dt.address;
6682 kvm_x86_ops->get_gdt(vcpu, &dt);
6683 sregs->gdt.limit = dt.size;
6684 sregs->gdt.base = dt.address;
6685
6686 sregs->cr0 = kvm_read_cr0(vcpu);
6687 sregs->cr2 = vcpu->arch.cr2;
6688 sregs->cr3 = kvm_read_cr3(vcpu);
6689 sregs->cr4 = kvm_read_cr4(vcpu);
6690 sregs->cr8 = kvm_get_cr8(vcpu);
6691 sregs->efer = vcpu->arch.efer;
6692 sregs->apic_base = kvm_get_apic_base(vcpu);
6693
6694 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6695
6696 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6697 set_bit(vcpu->arch.interrupt.nr,
6698 (unsigned long *)sregs->interrupt_bitmap);
6699
6700 return 0;
6701 }
6702
6703 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6704 struct kvm_mp_state *mp_state)
6705 {
6706 kvm_apic_accept_events(vcpu);
6707 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6708 vcpu->arch.pv.pv_unhalted)
6709 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6710 else
6711 mp_state->mp_state = vcpu->arch.mp_state;
6712
6713 return 0;
6714 }
6715
6716 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6717 struct kvm_mp_state *mp_state)
6718 {
6719 if (!kvm_vcpu_has_lapic(vcpu) &&
6720 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6721 return -EINVAL;
6722
6723 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6724 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6725 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6726 } else
6727 vcpu->arch.mp_state = mp_state->mp_state;
6728 kvm_make_request(KVM_REQ_EVENT, vcpu);
6729 return 0;
6730 }
6731
6732 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6733 int reason, bool has_error_code, u32 error_code)
6734 {
6735 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6736 int ret;
6737
6738 init_emulate_ctxt(vcpu);
6739
6740 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6741 has_error_code, error_code);
6742
6743 if (ret)
6744 return EMULATE_FAIL;
6745
6746 kvm_rip_write(vcpu, ctxt->eip);
6747 kvm_set_rflags(vcpu, ctxt->eflags);
6748 kvm_make_request(KVM_REQ_EVENT, vcpu);
6749 return EMULATE_DONE;
6750 }
6751 EXPORT_SYMBOL_GPL(kvm_task_switch);
6752
6753 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6754 struct kvm_sregs *sregs)
6755 {
6756 struct msr_data apic_base_msr;
6757 int mmu_reset_needed = 0;
6758 int pending_vec, max_bits, idx;
6759 struct desc_ptr dt;
6760
6761 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6762 return -EINVAL;
6763
6764 dt.size = sregs->idt.limit;
6765 dt.address = sregs->idt.base;
6766 kvm_x86_ops->set_idt(vcpu, &dt);
6767 dt.size = sregs->gdt.limit;
6768 dt.address = sregs->gdt.base;
6769 kvm_x86_ops->set_gdt(vcpu, &dt);
6770
6771 vcpu->arch.cr2 = sregs->cr2;
6772 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6773 vcpu->arch.cr3 = sregs->cr3;
6774 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6775
6776 kvm_set_cr8(vcpu, sregs->cr8);
6777
6778 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6779 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6780 apic_base_msr.data = sregs->apic_base;
6781 apic_base_msr.host_initiated = true;
6782 kvm_set_apic_base(vcpu, &apic_base_msr);
6783
6784 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6785 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6786 vcpu->arch.cr0 = sregs->cr0;
6787
6788 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6789 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6790 if (sregs->cr4 & X86_CR4_OSXSAVE)
6791 kvm_update_cpuid(vcpu);
6792
6793 idx = srcu_read_lock(&vcpu->kvm->srcu);
6794 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6795 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6796 mmu_reset_needed = 1;
6797 }
6798 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6799
6800 if (mmu_reset_needed)
6801 kvm_mmu_reset_context(vcpu);
6802
6803 max_bits = KVM_NR_INTERRUPTS;
6804 pending_vec = find_first_bit(
6805 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6806 if (pending_vec < max_bits) {
6807 kvm_queue_interrupt(vcpu, pending_vec, false);
6808 pr_debug("Set back pending irq %d\n", pending_vec);
6809 }
6810
6811 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6812 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6813 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6814 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6815 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6816 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6817
6818 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6819 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6820
6821 update_cr8_intercept(vcpu);
6822
6823 /* Older userspace won't unhalt the vcpu on reset. */
6824 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6825 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6826 !is_protmode(vcpu))
6827 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6828
6829 kvm_make_request(KVM_REQ_EVENT, vcpu);
6830
6831 return 0;
6832 }
6833
6834 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6835 struct kvm_guest_debug *dbg)
6836 {
6837 unsigned long rflags;
6838 int i, r;
6839
6840 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6841 r = -EBUSY;
6842 if (vcpu->arch.exception.pending)
6843 goto out;
6844 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6845 kvm_queue_exception(vcpu, DB_VECTOR);
6846 else
6847 kvm_queue_exception(vcpu, BP_VECTOR);
6848 }
6849
6850 /*
6851 * Read rflags as long as potentially injected trace flags are still
6852 * filtered out.
6853 */
6854 rflags = kvm_get_rflags(vcpu);
6855
6856 vcpu->guest_debug = dbg->control;
6857 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6858 vcpu->guest_debug = 0;
6859
6860 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6861 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6862 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6863 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6864 } else {
6865 for (i = 0; i < KVM_NR_DB_REGS; i++)
6866 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6867 }
6868 kvm_update_dr7(vcpu);
6869
6870 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6871 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6872 get_segment_base(vcpu, VCPU_SREG_CS);
6873
6874 /*
6875 * Trigger an rflags update that will inject or remove the trace
6876 * flags.
6877 */
6878 kvm_set_rflags(vcpu, rflags);
6879
6880 kvm_x86_ops->update_db_bp_intercept(vcpu);
6881
6882 r = 0;
6883
6884 out:
6885
6886 return r;
6887 }
6888
6889 /*
6890 * Translate a guest virtual address to a guest physical address.
6891 */
6892 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6893 struct kvm_translation *tr)
6894 {
6895 unsigned long vaddr = tr->linear_address;
6896 gpa_t gpa;
6897 int idx;
6898
6899 idx = srcu_read_lock(&vcpu->kvm->srcu);
6900 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6901 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6902 tr->physical_address = gpa;
6903 tr->valid = gpa != UNMAPPED_GVA;
6904 tr->writeable = 1;
6905 tr->usermode = 0;
6906
6907 return 0;
6908 }
6909
6910 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6911 {
6912 struct i387_fxsave_struct *fxsave =
6913 &vcpu->arch.guest_fpu.state->fxsave;
6914
6915 memcpy(fpu->fpr, fxsave->st_space, 128);
6916 fpu->fcw = fxsave->cwd;
6917 fpu->fsw = fxsave->swd;
6918 fpu->ftwx = fxsave->twd;
6919 fpu->last_opcode = fxsave->fop;
6920 fpu->last_ip = fxsave->rip;
6921 fpu->last_dp = fxsave->rdp;
6922 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6923
6924 return 0;
6925 }
6926
6927 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6928 {
6929 struct i387_fxsave_struct *fxsave =
6930 &vcpu->arch.guest_fpu.state->fxsave;
6931
6932 memcpy(fxsave->st_space, fpu->fpr, 128);
6933 fxsave->cwd = fpu->fcw;
6934 fxsave->swd = fpu->fsw;
6935 fxsave->twd = fpu->ftwx;
6936 fxsave->fop = fpu->last_opcode;
6937 fxsave->rip = fpu->last_ip;
6938 fxsave->rdp = fpu->last_dp;
6939 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6940
6941 return 0;
6942 }
6943
6944 int fx_init(struct kvm_vcpu *vcpu)
6945 {
6946 int err;
6947
6948 err = fpu_alloc(&vcpu->arch.guest_fpu);
6949 if (err)
6950 return err;
6951
6952 fpu_finit(&vcpu->arch.guest_fpu);
6953 if (cpu_has_xsaves)
6954 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6955 host_xcr0 | XSTATE_COMPACTION_ENABLED;
6956
6957 /*
6958 * Ensure guest xcr0 is valid for loading
6959 */
6960 vcpu->arch.xcr0 = XSTATE_FP;
6961
6962 vcpu->arch.cr0 |= X86_CR0_ET;
6963
6964 return 0;
6965 }
6966 EXPORT_SYMBOL_GPL(fx_init);
6967
6968 static void fx_free(struct kvm_vcpu *vcpu)
6969 {
6970 fpu_free(&vcpu->arch.guest_fpu);
6971 }
6972
6973 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6974 {
6975 if (vcpu->guest_fpu_loaded)
6976 return;
6977
6978 /*
6979 * Restore all possible states in the guest,
6980 * and assume host would use all available bits.
6981 * Guest xcr0 would be loaded later.
6982 */
6983 kvm_put_guest_xcr0(vcpu);
6984 vcpu->guest_fpu_loaded = 1;
6985 __kernel_fpu_begin();
6986 fpu_restore_checking(&vcpu->arch.guest_fpu);
6987 trace_kvm_fpu(1);
6988 }
6989
6990 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6991 {
6992 kvm_put_guest_xcr0(vcpu);
6993
6994 if (!vcpu->guest_fpu_loaded)
6995 return;
6996
6997 vcpu->guest_fpu_loaded = 0;
6998 fpu_save_init(&vcpu->arch.guest_fpu);
6999 __kernel_fpu_end();
7000 ++vcpu->stat.fpu_reload;
7001 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7002 trace_kvm_fpu(0);
7003 }
7004
7005 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7006 {
7007 kvmclock_reset(vcpu);
7008
7009 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7010 fx_free(vcpu);
7011 kvm_x86_ops->vcpu_free(vcpu);
7012 }
7013
7014 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7015 unsigned int id)
7016 {
7017 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7018 printk_once(KERN_WARNING
7019 "kvm: SMP vm created on host with unstable TSC; "
7020 "guest TSC will not be reliable\n");
7021 return kvm_x86_ops->vcpu_create(kvm, id);
7022 }
7023
7024 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7025 {
7026 int r;
7027
7028 vcpu->arch.mtrr_state.have_fixed = 1;
7029 r = vcpu_load(vcpu);
7030 if (r)
7031 return r;
7032 kvm_vcpu_reset(vcpu);
7033 kvm_mmu_setup(vcpu);
7034 vcpu_put(vcpu);
7035
7036 return r;
7037 }
7038
7039 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7040 {
7041 struct msr_data msr;
7042 struct kvm *kvm = vcpu->kvm;
7043
7044 if (vcpu_load(vcpu))
7045 return;
7046 msr.data = 0x0;
7047 msr.index = MSR_IA32_TSC;
7048 msr.host_initiated = true;
7049 kvm_write_tsc(vcpu, &msr);
7050 vcpu_put(vcpu);
7051
7052 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7053 KVMCLOCK_SYNC_PERIOD);
7054 }
7055
7056 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7057 {
7058 int r;
7059 vcpu->arch.apf.msr_val = 0;
7060
7061 r = vcpu_load(vcpu);
7062 BUG_ON(r);
7063 kvm_mmu_unload(vcpu);
7064 vcpu_put(vcpu);
7065
7066 fx_free(vcpu);
7067 kvm_x86_ops->vcpu_free(vcpu);
7068 }
7069
7070 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
7071 {
7072 atomic_set(&vcpu->arch.nmi_queued, 0);
7073 vcpu->arch.nmi_pending = 0;
7074 vcpu->arch.nmi_injected = false;
7075 kvm_clear_interrupt_queue(vcpu);
7076 kvm_clear_exception_queue(vcpu);
7077
7078 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7079 vcpu->arch.dr6 = DR6_INIT;
7080 kvm_update_dr6(vcpu);
7081 vcpu->arch.dr7 = DR7_FIXED_1;
7082 kvm_update_dr7(vcpu);
7083
7084 kvm_make_request(KVM_REQ_EVENT, vcpu);
7085 vcpu->arch.apf.msr_val = 0;
7086 vcpu->arch.st.msr_val = 0;
7087
7088 kvmclock_reset(vcpu);
7089
7090 kvm_clear_async_pf_completion_queue(vcpu);
7091 kvm_async_pf_hash_reset(vcpu);
7092 vcpu->arch.apf.halted = false;
7093
7094 kvm_pmu_reset(vcpu);
7095
7096 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7097 vcpu->arch.regs_avail = ~0;
7098 vcpu->arch.regs_dirty = ~0;
7099
7100 kvm_x86_ops->vcpu_reset(vcpu);
7101 }
7102
7103 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7104 {
7105 struct kvm_segment cs;
7106
7107 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7108 cs.selector = vector << 8;
7109 cs.base = vector << 12;
7110 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7111 kvm_rip_write(vcpu, 0);
7112 }
7113
7114 int kvm_arch_hardware_enable(void)
7115 {
7116 struct kvm *kvm;
7117 struct kvm_vcpu *vcpu;
7118 int i;
7119 int ret;
7120 u64 local_tsc;
7121 u64 max_tsc = 0;
7122 bool stable, backwards_tsc = false;
7123
7124 kvm_shared_msr_cpu_online();
7125 ret = kvm_x86_ops->hardware_enable();
7126 if (ret != 0)
7127 return ret;
7128
7129 local_tsc = native_read_tsc();
7130 stable = !check_tsc_unstable();
7131 list_for_each_entry(kvm, &vm_list, vm_list) {
7132 kvm_for_each_vcpu(i, vcpu, kvm) {
7133 if (!stable && vcpu->cpu == smp_processor_id())
7134 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7135 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7136 backwards_tsc = true;
7137 if (vcpu->arch.last_host_tsc > max_tsc)
7138 max_tsc = vcpu->arch.last_host_tsc;
7139 }
7140 }
7141 }
7142
7143 /*
7144 * Sometimes, even reliable TSCs go backwards. This happens on
7145 * platforms that reset TSC during suspend or hibernate actions, but
7146 * maintain synchronization. We must compensate. Fortunately, we can
7147 * detect that condition here, which happens early in CPU bringup,
7148 * before any KVM threads can be running. Unfortunately, we can't
7149 * bring the TSCs fully up to date with real time, as we aren't yet far
7150 * enough into CPU bringup that we know how much real time has actually
7151 * elapsed; our helper function, get_kernel_ns() will be using boot
7152 * variables that haven't been updated yet.
7153 *
7154 * So we simply find the maximum observed TSC above, then record the
7155 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7156 * the adjustment will be applied. Note that we accumulate
7157 * adjustments, in case multiple suspend cycles happen before some VCPU
7158 * gets a chance to run again. In the event that no KVM threads get a
7159 * chance to run, we will miss the entire elapsed period, as we'll have
7160 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7161 * loose cycle time. This isn't too big a deal, since the loss will be
7162 * uniform across all VCPUs (not to mention the scenario is extremely
7163 * unlikely). It is possible that a second hibernate recovery happens
7164 * much faster than a first, causing the observed TSC here to be
7165 * smaller; this would require additional padding adjustment, which is
7166 * why we set last_host_tsc to the local tsc observed here.
7167 *
7168 * N.B. - this code below runs only on platforms with reliable TSC,
7169 * as that is the only way backwards_tsc is set above. Also note
7170 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7171 * have the same delta_cyc adjustment applied if backwards_tsc
7172 * is detected. Note further, this adjustment is only done once,
7173 * as we reset last_host_tsc on all VCPUs to stop this from being
7174 * called multiple times (one for each physical CPU bringup).
7175 *
7176 * Platforms with unreliable TSCs don't have to deal with this, they
7177 * will be compensated by the logic in vcpu_load, which sets the TSC to
7178 * catchup mode. This will catchup all VCPUs to real time, but cannot
7179 * guarantee that they stay in perfect synchronization.
7180 */
7181 if (backwards_tsc) {
7182 u64 delta_cyc = max_tsc - local_tsc;
7183 backwards_tsc_observed = true;
7184 list_for_each_entry(kvm, &vm_list, vm_list) {
7185 kvm_for_each_vcpu(i, vcpu, kvm) {
7186 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7187 vcpu->arch.last_host_tsc = local_tsc;
7188 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7189 }
7190
7191 /*
7192 * We have to disable TSC offset matching.. if you were
7193 * booting a VM while issuing an S4 host suspend....
7194 * you may have some problem. Solving this issue is
7195 * left as an exercise to the reader.
7196 */
7197 kvm->arch.last_tsc_nsec = 0;
7198 kvm->arch.last_tsc_write = 0;
7199 }
7200
7201 }
7202 return 0;
7203 }
7204
7205 void kvm_arch_hardware_disable(void)
7206 {
7207 kvm_x86_ops->hardware_disable();
7208 drop_user_return_notifiers();
7209 }
7210
7211 int kvm_arch_hardware_setup(void)
7212 {
7213 return kvm_x86_ops->hardware_setup();
7214 }
7215
7216 void kvm_arch_hardware_unsetup(void)
7217 {
7218 kvm_x86_ops->hardware_unsetup();
7219 }
7220
7221 void kvm_arch_check_processor_compat(void *rtn)
7222 {
7223 kvm_x86_ops->check_processor_compatibility(rtn);
7224 }
7225
7226 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7227 {
7228 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7229 }
7230
7231 struct static_key kvm_no_apic_vcpu __read_mostly;
7232
7233 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7234 {
7235 struct page *page;
7236 struct kvm *kvm;
7237 int r;
7238
7239 BUG_ON(vcpu->kvm == NULL);
7240 kvm = vcpu->kvm;
7241
7242 vcpu->arch.pv.pv_unhalted = false;
7243 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7244 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7245 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7246 else
7247 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7248
7249 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7250 if (!page) {
7251 r = -ENOMEM;
7252 goto fail;
7253 }
7254 vcpu->arch.pio_data = page_address(page);
7255
7256 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7257
7258 r = kvm_mmu_create(vcpu);
7259 if (r < 0)
7260 goto fail_free_pio_data;
7261
7262 if (irqchip_in_kernel(kvm)) {
7263 r = kvm_create_lapic(vcpu);
7264 if (r < 0)
7265 goto fail_mmu_destroy;
7266 } else
7267 static_key_slow_inc(&kvm_no_apic_vcpu);
7268
7269 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7270 GFP_KERNEL);
7271 if (!vcpu->arch.mce_banks) {
7272 r = -ENOMEM;
7273 goto fail_free_lapic;
7274 }
7275 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7276
7277 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7278 r = -ENOMEM;
7279 goto fail_free_mce_banks;
7280 }
7281
7282 r = fx_init(vcpu);
7283 if (r)
7284 goto fail_free_wbinvd_dirty_mask;
7285
7286 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7287 vcpu->arch.pv_time_enabled = false;
7288
7289 vcpu->arch.guest_supported_xcr0 = 0;
7290 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7291
7292 kvm_async_pf_hash_reset(vcpu);
7293 kvm_pmu_init(vcpu);
7294
7295 return 0;
7296 fail_free_wbinvd_dirty_mask:
7297 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7298 fail_free_mce_banks:
7299 kfree(vcpu->arch.mce_banks);
7300 fail_free_lapic:
7301 kvm_free_lapic(vcpu);
7302 fail_mmu_destroy:
7303 kvm_mmu_destroy(vcpu);
7304 fail_free_pio_data:
7305 free_page((unsigned long)vcpu->arch.pio_data);
7306 fail:
7307 return r;
7308 }
7309
7310 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7311 {
7312 int idx;
7313
7314 kvm_pmu_destroy(vcpu);
7315 kfree(vcpu->arch.mce_banks);
7316 kvm_free_lapic(vcpu);
7317 idx = srcu_read_lock(&vcpu->kvm->srcu);
7318 kvm_mmu_destroy(vcpu);
7319 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7320 free_page((unsigned long)vcpu->arch.pio_data);
7321 if (!irqchip_in_kernel(vcpu->kvm))
7322 static_key_slow_dec(&kvm_no_apic_vcpu);
7323 }
7324
7325 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7326 {
7327 kvm_x86_ops->sched_in(vcpu, cpu);
7328 }
7329
7330 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7331 {
7332 if (type)
7333 return -EINVAL;
7334
7335 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7336 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7337 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7338 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7339 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7340
7341 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7342 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7343 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7344 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7345 &kvm->arch.irq_sources_bitmap);
7346
7347 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7348 mutex_init(&kvm->arch.apic_map_lock);
7349 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7350
7351 pvclock_update_vm_gtod_copy(kvm);
7352
7353 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7354 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7355
7356 return 0;
7357 }
7358
7359 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7360 {
7361 int r;
7362 r = vcpu_load(vcpu);
7363 BUG_ON(r);
7364 kvm_mmu_unload(vcpu);
7365 vcpu_put(vcpu);
7366 }
7367
7368 static void kvm_free_vcpus(struct kvm *kvm)
7369 {
7370 unsigned int i;
7371 struct kvm_vcpu *vcpu;
7372
7373 /*
7374 * Unpin any mmu pages first.
7375 */
7376 kvm_for_each_vcpu(i, vcpu, kvm) {
7377 kvm_clear_async_pf_completion_queue(vcpu);
7378 kvm_unload_vcpu_mmu(vcpu);
7379 }
7380 kvm_for_each_vcpu(i, vcpu, kvm)
7381 kvm_arch_vcpu_free(vcpu);
7382
7383 mutex_lock(&kvm->lock);
7384 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7385 kvm->vcpus[i] = NULL;
7386
7387 atomic_set(&kvm->online_vcpus, 0);
7388 mutex_unlock(&kvm->lock);
7389 }
7390
7391 void kvm_arch_sync_events(struct kvm *kvm)
7392 {
7393 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7394 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7395 kvm_free_all_assigned_devices(kvm);
7396 kvm_free_pit(kvm);
7397 }
7398
7399 void kvm_arch_destroy_vm(struct kvm *kvm)
7400 {
7401 if (current->mm == kvm->mm) {
7402 /*
7403 * Free memory regions allocated on behalf of userspace,
7404 * unless the the memory map has changed due to process exit
7405 * or fd copying.
7406 */
7407 struct kvm_userspace_memory_region mem;
7408 memset(&mem, 0, sizeof(mem));
7409 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7410 kvm_set_memory_region(kvm, &mem);
7411
7412 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7413 kvm_set_memory_region(kvm, &mem);
7414
7415 mem.slot = TSS_PRIVATE_MEMSLOT;
7416 kvm_set_memory_region(kvm, &mem);
7417 }
7418 kvm_iommu_unmap_guest(kvm);
7419 kfree(kvm->arch.vpic);
7420 kfree(kvm->arch.vioapic);
7421 kvm_free_vcpus(kvm);
7422 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7423 }
7424
7425 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7426 struct kvm_memory_slot *dont)
7427 {
7428 int i;
7429
7430 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7431 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7432 kvm_kvfree(free->arch.rmap[i]);
7433 free->arch.rmap[i] = NULL;
7434 }
7435 if (i == 0)
7436 continue;
7437
7438 if (!dont || free->arch.lpage_info[i - 1] !=
7439 dont->arch.lpage_info[i - 1]) {
7440 kvm_kvfree(free->arch.lpage_info[i - 1]);
7441 free->arch.lpage_info[i - 1] = NULL;
7442 }
7443 }
7444 }
7445
7446 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7447 unsigned long npages)
7448 {
7449 int i;
7450
7451 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7452 unsigned long ugfn;
7453 int lpages;
7454 int level = i + 1;
7455
7456 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7457 slot->base_gfn, level) + 1;
7458
7459 slot->arch.rmap[i] =
7460 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7461 if (!slot->arch.rmap[i])
7462 goto out_free;
7463 if (i == 0)
7464 continue;
7465
7466 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7467 sizeof(*slot->arch.lpage_info[i - 1]));
7468 if (!slot->arch.lpage_info[i - 1])
7469 goto out_free;
7470
7471 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7472 slot->arch.lpage_info[i - 1][0].write_count = 1;
7473 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7474 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7475 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7476 /*
7477 * If the gfn and userspace address are not aligned wrt each
7478 * other, or if explicitly asked to, disable large page
7479 * support for this slot
7480 */
7481 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7482 !kvm_largepages_enabled()) {
7483 unsigned long j;
7484
7485 for (j = 0; j < lpages; ++j)
7486 slot->arch.lpage_info[i - 1][j].write_count = 1;
7487 }
7488 }
7489
7490 return 0;
7491
7492 out_free:
7493 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7494 kvm_kvfree(slot->arch.rmap[i]);
7495 slot->arch.rmap[i] = NULL;
7496 if (i == 0)
7497 continue;
7498
7499 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7500 slot->arch.lpage_info[i - 1] = NULL;
7501 }
7502 return -ENOMEM;
7503 }
7504
7505 void kvm_arch_memslots_updated(struct kvm *kvm)
7506 {
7507 /*
7508 * memslots->generation has been incremented.
7509 * mmio generation may have reached its maximum value.
7510 */
7511 kvm_mmu_invalidate_mmio_sptes(kvm);
7512 }
7513
7514 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7515 struct kvm_memory_slot *memslot,
7516 struct kvm_userspace_memory_region *mem,
7517 enum kvm_mr_change change)
7518 {
7519 /*
7520 * Only private memory slots need to be mapped here since
7521 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7522 */
7523 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7524 unsigned long userspace_addr;
7525
7526 /*
7527 * MAP_SHARED to prevent internal slot pages from being moved
7528 * by fork()/COW.
7529 */
7530 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7531 PROT_READ | PROT_WRITE,
7532 MAP_SHARED | MAP_ANONYMOUS, 0);
7533
7534 if (IS_ERR((void *)userspace_addr))
7535 return PTR_ERR((void *)userspace_addr);
7536
7537 memslot->userspace_addr = userspace_addr;
7538 }
7539
7540 return 0;
7541 }
7542
7543 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7544 struct kvm_memory_slot *new)
7545 {
7546 /* Still write protect RO slot */
7547 if (new->flags & KVM_MEM_READONLY) {
7548 kvm_mmu_slot_remove_write_access(kvm, new);
7549 return;
7550 }
7551
7552 /*
7553 * Call kvm_x86_ops dirty logging hooks when they are valid.
7554 *
7555 * kvm_x86_ops->slot_disable_log_dirty is called when:
7556 *
7557 * - KVM_MR_CREATE with dirty logging is disabled
7558 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7559 *
7560 * The reason is, in case of PML, we need to set D-bit for any slots
7561 * with dirty logging disabled in order to eliminate unnecessary GPA
7562 * logging in PML buffer (and potential PML buffer full VMEXT). This
7563 * guarantees leaving PML enabled during guest's lifetime won't have
7564 * any additonal overhead from PML when guest is running with dirty
7565 * logging disabled for memory slots.
7566 *
7567 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7568 * to dirty logging mode.
7569 *
7570 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7571 *
7572 * In case of write protect:
7573 *
7574 * Write protect all pages for dirty logging.
7575 *
7576 * All the sptes including the large sptes which point to this
7577 * slot are set to readonly. We can not create any new large
7578 * spte on this slot until the end of the logging.
7579 *
7580 * See the comments in fast_page_fault().
7581 */
7582 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7583 if (kvm_x86_ops->slot_enable_log_dirty)
7584 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7585 else
7586 kvm_mmu_slot_remove_write_access(kvm, new);
7587 } else {
7588 if (kvm_x86_ops->slot_disable_log_dirty)
7589 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7590 }
7591 }
7592
7593 void kvm_arch_commit_memory_region(struct kvm *kvm,
7594 struct kvm_userspace_memory_region *mem,
7595 const struct kvm_memory_slot *old,
7596 enum kvm_mr_change change)
7597 {
7598 struct kvm_memory_slot *new;
7599 int nr_mmu_pages = 0;
7600
7601 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7602 int ret;
7603
7604 ret = vm_munmap(old->userspace_addr,
7605 old->npages * PAGE_SIZE);
7606 if (ret < 0)
7607 printk(KERN_WARNING
7608 "kvm_vm_ioctl_set_memory_region: "
7609 "failed to munmap memory\n");
7610 }
7611
7612 if (!kvm->arch.n_requested_mmu_pages)
7613 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7614
7615 if (nr_mmu_pages)
7616 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7617
7618 /* It's OK to get 'new' slot here as it has already been installed */
7619 new = id_to_memslot(kvm->memslots, mem->slot);
7620
7621 /*
7622 * Set up write protection and/or dirty logging for the new slot.
7623 *
7624 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7625 * been zapped so no dirty logging staff is needed for old slot. For
7626 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7627 * new and it's also covered when dealing with the new slot.
7628 */
7629 if (change != KVM_MR_DELETE)
7630 kvm_mmu_slot_apply_flags(kvm, new);
7631 }
7632
7633 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7634 {
7635 kvm_mmu_invalidate_zap_all_pages(kvm);
7636 }
7637
7638 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7639 struct kvm_memory_slot *slot)
7640 {
7641 kvm_mmu_invalidate_zap_all_pages(kvm);
7642 }
7643
7644 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7645 {
7646 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7647 kvm_x86_ops->check_nested_events(vcpu, false);
7648
7649 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7650 !vcpu->arch.apf.halted)
7651 || !list_empty_careful(&vcpu->async_pf.done)
7652 || kvm_apic_has_events(vcpu)
7653 || vcpu->arch.pv.pv_unhalted
7654 || atomic_read(&vcpu->arch.nmi_queued) ||
7655 (kvm_arch_interrupt_allowed(vcpu) &&
7656 kvm_cpu_has_interrupt(vcpu));
7657 }
7658
7659 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7660 {
7661 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7662 }
7663
7664 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7665 {
7666 return kvm_x86_ops->interrupt_allowed(vcpu);
7667 }
7668
7669 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7670 {
7671 if (is_64_bit_mode(vcpu))
7672 return kvm_rip_read(vcpu);
7673 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7674 kvm_rip_read(vcpu));
7675 }
7676 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7677
7678 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7679 {
7680 return kvm_get_linear_rip(vcpu) == linear_rip;
7681 }
7682 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7683
7684 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7685 {
7686 unsigned long rflags;
7687
7688 rflags = kvm_x86_ops->get_rflags(vcpu);
7689 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7690 rflags &= ~X86_EFLAGS_TF;
7691 return rflags;
7692 }
7693 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7694
7695 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7696 {
7697 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7698 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7699 rflags |= X86_EFLAGS_TF;
7700 kvm_x86_ops->set_rflags(vcpu, rflags);
7701 }
7702
7703 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7704 {
7705 __kvm_set_rflags(vcpu, rflags);
7706 kvm_make_request(KVM_REQ_EVENT, vcpu);
7707 }
7708 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7709
7710 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7711 {
7712 int r;
7713
7714 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7715 work->wakeup_all)
7716 return;
7717
7718 r = kvm_mmu_reload(vcpu);
7719 if (unlikely(r))
7720 return;
7721
7722 if (!vcpu->arch.mmu.direct_map &&
7723 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7724 return;
7725
7726 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7727 }
7728
7729 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7730 {
7731 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7732 }
7733
7734 static inline u32 kvm_async_pf_next_probe(u32 key)
7735 {
7736 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7737 }
7738
7739 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7740 {
7741 u32 key = kvm_async_pf_hash_fn(gfn);
7742
7743 while (vcpu->arch.apf.gfns[key] != ~0)
7744 key = kvm_async_pf_next_probe(key);
7745
7746 vcpu->arch.apf.gfns[key] = gfn;
7747 }
7748
7749 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7750 {
7751 int i;
7752 u32 key = kvm_async_pf_hash_fn(gfn);
7753
7754 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7755 (vcpu->arch.apf.gfns[key] != gfn &&
7756 vcpu->arch.apf.gfns[key] != ~0); i++)
7757 key = kvm_async_pf_next_probe(key);
7758
7759 return key;
7760 }
7761
7762 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7763 {
7764 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7765 }
7766
7767 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7768 {
7769 u32 i, j, k;
7770
7771 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7772 while (true) {
7773 vcpu->arch.apf.gfns[i] = ~0;
7774 do {
7775 j = kvm_async_pf_next_probe(j);
7776 if (vcpu->arch.apf.gfns[j] == ~0)
7777 return;
7778 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7779 /*
7780 * k lies cyclically in ]i,j]
7781 * | i.k.j |
7782 * |....j i.k.| or |.k..j i...|
7783 */
7784 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7785 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7786 i = j;
7787 }
7788 }
7789
7790 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7791 {
7792
7793 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7794 sizeof(val));
7795 }
7796
7797 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7798 struct kvm_async_pf *work)
7799 {
7800 struct x86_exception fault;
7801
7802 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7803 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7804
7805 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7806 (vcpu->arch.apf.send_user_only &&
7807 kvm_x86_ops->get_cpl(vcpu) == 0))
7808 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7809 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7810 fault.vector = PF_VECTOR;
7811 fault.error_code_valid = true;
7812 fault.error_code = 0;
7813 fault.nested_page_fault = false;
7814 fault.address = work->arch.token;
7815 kvm_inject_page_fault(vcpu, &fault);
7816 }
7817 }
7818
7819 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7820 struct kvm_async_pf *work)
7821 {
7822 struct x86_exception fault;
7823
7824 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7825 if (work->wakeup_all)
7826 work->arch.token = ~0; /* broadcast wakeup */
7827 else
7828 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7829
7830 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7831 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7832 fault.vector = PF_VECTOR;
7833 fault.error_code_valid = true;
7834 fault.error_code = 0;
7835 fault.nested_page_fault = false;
7836 fault.address = work->arch.token;
7837 kvm_inject_page_fault(vcpu, &fault);
7838 }
7839 vcpu->arch.apf.halted = false;
7840 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7841 }
7842
7843 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7844 {
7845 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7846 return true;
7847 else
7848 return !kvm_event_needs_reinjection(vcpu) &&
7849 kvm_x86_ops->interrupt_allowed(vcpu);
7850 }
7851
7852 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7853 {
7854 atomic_inc(&kvm->arch.noncoherent_dma_count);
7855 }
7856 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7857
7858 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7859 {
7860 atomic_dec(&kvm->arch.noncoherent_dma_count);
7861 }
7862 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7863
7864 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7865 {
7866 return atomic_read(&kvm->arch.noncoherent_dma_count);
7867 }
7868 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7869
7870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7872 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7873 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7874 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7875 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7876 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7877 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7878 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7879 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7880 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7881 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7882 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7883 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
7884 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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