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KVM: x86: Add EOI exit bitmap inference
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <trace/events/kvm.h>
55
56 #define CREATE_TRACE_POINTS
57 #include "trace.h"
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 static bool __read_mostly kvmclock_periodic_sync = true;
103 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
105 bool kvm_has_tsc_control;
106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107 u32 kvm_max_guest_tsc_khz;
108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111 static u32 tsc_tolerance_ppm = 250;
112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
115 unsigned int lapic_timer_advance_ns = 0;
116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
118 static bool backwards_tsc_observed = false;
119
120 #define KVM_NR_SHARED_MSRS 16
121
122 struct kvm_shared_msrs_global {
123 int nr;
124 u32 msrs[KVM_NR_SHARED_MSRS];
125 };
126
127 struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
134 };
135
136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
137 static struct kvm_shared_msrs __percpu *shared_msrs;
138
139 struct kvm_stats_debugfs_item debugfs_entries[] = {
140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
150 { "halt_exits", VCPU_STAT(halt_exits) },
151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
154 { "hypercalls", VCPU_STAT(hypercalls) },
155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
162 { "irq_injections", VCPU_STAT(irq_injections) },
163 { "nmi_injections", VCPU_STAT(nmi_injections) },
164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
171 { "mmu_unsync", VM_STAT(mmu_unsync) },
172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
173 { "largepages", VM_STAT(lpages) },
174 { NULL }
175 };
176
177 u64 __read_mostly host_xcr0;
178
179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
180
181 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182 {
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186 }
187
188 static void kvm_on_user_return(struct user_return_notifier *urn)
189 {
190 unsigned slot;
191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
193 struct kvm_shared_msr_values *values;
194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204 }
205
206 static void shared_msr_update(unsigned slot, u32 msr)
207 {
208 u64 value;
209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
211
212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221 }
222
223 void kvm_define_shared_msr(unsigned slot, u32 msr)
224 {
225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
226 shared_msrs_global.msrs[slot] = msr;
227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
229 }
230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232 static void kvm_shared_msr_cpu_online(void)
233 {
234 unsigned i;
235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
237 shared_msr_update(i, shared_msrs_global.msrs[i]);
238 }
239
240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
241 {
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 int err;
245
246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
247 return 0;
248 smsr->values[slot].curr = value;
249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
258 return 0;
259 }
260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
262 static void drop_user_return_notifiers(void)
263 {
264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269 }
270
271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272 {
273 return vcpu->arch.apic_base;
274 }
275 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278 {
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
297 }
298 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
300 asmlinkage __visible void kvm_spurious_fault(void)
301 {
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304 }
305 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
307 #define EXCPT_BENIGN 0
308 #define EXCPT_CONTRIBUTORY 1
309 #define EXCPT_PF 2
310
311 static int exception_class(int vector)
312 {
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326 }
327
328 #define EXCPT_FAULT 0
329 #define EXCPT_TRAP 1
330 #define EXCPT_ABORT 2
331 #define EXCPT_INTERRUPT 3
332
333 static int exception_type(int vector)
334 {
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351 }
352
353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
356 {
357 u32 prev_nr;
358 int class1, class2;
359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
362 if (!vcpu->arch.exception.pending) {
363 queue:
364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
370 vcpu->arch.exception.reinject = reinject;
371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395 }
396
397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398 {
399 kvm_multiple_exception(vcpu, nr, false, 0, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404 {
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
410 {
411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415 }
416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
417
418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
419 {
420 ++vcpu->stat.pf_guest;
421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
423 }
424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
425
426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
430 else
431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
432
433 return fault->nested_page_fault;
434 }
435
436 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437 {
438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
440 }
441 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444 {
445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
446 }
447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450 {
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452 }
453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
455 /*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
460 {
461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
465 }
466 EXPORT_SYMBOL_GPL(kvm_require_cpl);
467
468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469 {
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475 }
476 EXPORT_SYMBOL_GPL(kvm_require_dr);
477
478 /*
479 * This function will be used to read from the physical memory of the currently
480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
481 * can read from guest physical or from the guest's guest physical memory.
482 */
483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486 {
487 struct x86_exception exception;
488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
499 }
500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
503 void *data, int offset, int len, u32 access)
504 {
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507 }
508
509 /*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
513 {
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
519
520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
528 if (is_present_gpte(pdpte[i]) &&
529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
542 out:
543
544 return ret;
545 }
546 EXPORT_SYMBOL_GPL(load_pdptrs);
547
548 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549 {
550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
551 bool changed = true;
552 int offset;
553 gfn_t gfn;
554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
567 if (r < 0)
568 goto out;
569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
570 out:
571
572 return changed;
573 }
574
575 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
576 {
577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
579
580 cr0 |= X86_CR0_ET;
581
582 #ifdef CONFIG_X86_64
583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
585 #endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
588
589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
591
592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596 #ifdef CONFIG_X86_64
597 if ((vcpu->arch.efer & EFER_LME)) {
598 int cs_db, cs_l;
599
600 if (!is_pae(vcpu))
601 return 1;
602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
603 if (cs_l)
604 return 1;
605 } else
606 #endif
607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
608 kvm_read_cr3(vcpu)))
609 return 1;
610 }
611
612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
615 kvm_x86_ops->set_cr0(vcpu, cr0);
616
617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
618 kvm_clear_async_pf_completion_queue(vcpu);
619 kvm_async_pf_hash_reset(vcpu);
620 }
621
622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
628 return 0;
629 }
630 EXPORT_SYMBOL_GPL(kvm_set_cr0);
631
632 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
633 {
634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
635 }
636 EXPORT_SYMBOL_GPL(kvm_lmsw);
637
638 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639 {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646 }
647
648 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655 }
656
657 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
658 {
659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
661 u64 valid_bits;
662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
678 return 1;
679
680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
689 kvm_put_guest_xcr0(vcpu);
690 vcpu->arch.xcr0 = xcr0;
691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
694 return 0;
695 }
696
697 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698 {
699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
708 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
709 {
710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
716
717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
727 return 1;
728
729 if (is_long_mode(vcpu)) {
730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
736 return 1;
737
738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
748 return 1;
749
750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
752 kvm_mmu_reset_context(vcpu);
753
754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
755 kvm_update_cpuid(vcpu);
756
757 return 0;
758 }
759 EXPORT_SYMBOL_GPL(kvm_set_cr4);
760
761 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
762 {
763 #ifdef CONFIG_X86_64
764 cr3 &= ~CR3_PCID_INVD;
765 #endif
766
767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
768 kvm_mmu_sync_roots(vcpu);
769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
770 return 0;
771 }
772
773 if (is_long_mode(vcpu)) {
774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
778 return 1;
779
780 vcpu->arch.cr3 = cr3;
781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
782 kvm_mmu_new_cr3(vcpu);
783 return 0;
784 }
785 EXPORT_SYMBOL_GPL(kvm_set_cr3);
786
787 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
788 {
789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
791 if (lapic_in_kernel(vcpu))
792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
794 vcpu->arch.cr8 = cr8;
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_set_cr8);
798
799 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
800 {
801 if (lapic_in_kernel(vcpu))
802 return kvm_lapic_get_cr8(vcpu);
803 else
804 return vcpu->arch.cr8;
805 }
806 EXPORT_SYMBOL_GPL(kvm_get_cr8);
807
808 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809 {
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817 }
818
819 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820 {
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823 }
824
825 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826 {
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
837 }
838
839 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840 {
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846 }
847
848 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
849 {
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
857 /* fall through */
858 case 6:
859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
862 kvm_update_dr6(vcpu);
863 break;
864 case 5:
865 /* fall through */
866 default: /* 7 */
867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
870 kvm_update_dr7(vcpu);
871 break;
872 }
873
874 return 0;
875 }
876
877 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878 {
879 if (__kvm_set_dr(vcpu, dr, val)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884 }
885 EXPORT_SYMBOL_GPL(kvm_set_dr);
886
887 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
888 {
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
894 /* fall through */
895 case 6:
896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
900 break;
901 case 5:
902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(kvm_get_dr);
910
911 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912 {
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923 }
924 EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
926 /*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
931 * capabilities of the host cpu. This capabilities test skips MSRs that are
932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
934 */
935
936 static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
938 MSR_STAR,
939 #ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 #endif
942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
944 };
945
946 static unsigned num_msrs_to_save;
947
948 static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
955 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
956 MSR_KVM_PV_EOI_EN,
957
958 MSR_IA32_TSC_ADJUST,
959 MSR_IA32_TSCDEADLINE,
960 MSR_IA32_MISC_ENABLE,
961 MSR_IA32_MCG_STATUS,
962 MSR_IA32_MCG_CTL,
963 MSR_IA32_SMBASE,
964 };
965
966 static unsigned num_emulated_msrs;
967
968 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
969 {
970 if (efer & efer_reserved_bits)
971 return false;
972
973 if (efer & EFER_FFXSR) {
974 struct kvm_cpuid_entry2 *feat;
975
976 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
977 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
978 return false;
979 }
980
981 if (efer & EFER_SVME) {
982 struct kvm_cpuid_entry2 *feat;
983
984 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
985 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
986 return false;
987 }
988
989 return true;
990 }
991 EXPORT_SYMBOL_GPL(kvm_valid_efer);
992
993 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
994 {
995 u64 old_efer = vcpu->arch.efer;
996
997 if (!kvm_valid_efer(vcpu, efer))
998 return 1;
999
1000 if (is_paging(vcpu)
1001 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1002 return 1;
1003
1004 efer &= ~EFER_LMA;
1005 efer |= vcpu->arch.efer & EFER_LMA;
1006
1007 kvm_x86_ops->set_efer(vcpu, efer);
1008
1009 /* Update reserved bits */
1010 if ((efer ^ old_efer) & EFER_NX)
1011 kvm_mmu_reset_context(vcpu);
1012
1013 return 0;
1014 }
1015
1016 void kvm_enable_efer_bits(u64 mask)
1017 {
1018 efer_reserved_bits &= ~mask;
1019 }
1020 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1021
1022 /*
1023 * Writes msr value into into the appropriate "register".
1024 * Returns 0 on success, non-0 otherwise.
1025 * Assumes vcpu_load() was already called.
1026 */
1027 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1028 {
1029 switch (msr->index) {
1030 case MSR_FS_BASE:
1031 case MSR_GS_BASE:
1032 case MSR_KERNEL_GS_BASE:
1033 case MSR_CSTAR:
1034 case MSR_LSTAR:
1035 if (is_noncanonical_address(msr->data))
1036 return 1;
1037 break;
1038 case MSR_IA32_SYSENTER_EIP:
1039 case MSR_IA32_SYSENTER_ESP:
1040 /*
1041 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1042 * non-canonical address is written on Intel but not on
1043 * AMD (which ignores the top 32-bits, because it does
1044 * not implement 64-bit SYSENTER).
1045 *
1046 * 64-bit code should hence be able to write a non-canonical
1047 * value on AMD. Making the address canonical ensures that
1048 * vmentry does not fail on Intel after writing a non-canonical
1049 * value, and that something deterministic happens if the guest
1050 * invokes 64-bit SYSENTER.
1051 */
1052 msr->data = get_canonical(msr->data);
1053 }
1054 return kvm_x86_ops->set_msr(vcpu, msr);
1055 }
1056 EXPORT_SYMBOL_GPL(kvm_set_msr);
1057
1058 /*
1059 * Adapt set_msr() to msr_io()'s calling convention
1060 */
1061 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1062 {
1063 struct msr_data msr;
1064 int r;
1065
1066 msr.index = index;
1067 msr.host_initiated = true;
1068 r = kvm_get_msr(vcpu, &msr);
1069 if (r)
1070 return r;
1071
1072 *data = msr.data;
1073 return 0;
1074 }
1075
1076 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1077 {
1078 struct msr_data msr;
1079
1080 msr.data = *data;
1081 msr.index = index;
1082 msr.host_initiated = true;
1083 return kvm_set_msr(vcpu, &msr);
1084 }
1085
1086 #ifdef CONFIG_X86_64
1087 struct pvclock_gtod_data {
1088 seqcount_t seq;
1089
1090 struct { /* extract of a clocksource struct */
1091 int vclock_mode;
1092 cycle_t cycle_last;
1093 cycle_t mask;
1094 u32 mult;
1095 u32 shift;
1096 } clock;
1097
1098 u64 boot_ns;
1099 u64 nsec_base;
1100 };
1101
1102 static struct pvclock_gtod_data pvclock_gtod_data;
1103
1104 static void update_pvclock_gtod(struct timekeeper *tk)
1105 {
1106 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1107 u64 boot_ns;
1108
1109 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1110
1111 write_seqcount_begin(&vdata->seq);
1112
1113 /* copy pvclock gtod data */
1114 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1115 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1116 vdata->clock.mask = tk->tkr_mono.mask;
1117 vdata->clock.mult = tk->tkr_mono.mult;
1118 vdata->clock.shift = tk->tkr_mono.shift;
1119
1120 vdata->boot_ns = boot_ns;
1121 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1122
1123 write_seqcount_end(&vdata->seq);
1124 }
1125 #endif
1126
1127 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1128 {
1129 /*
1130 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1131 * vcpu_enter_guest. This function is only called from
1132 * the physical CPU that is running vcpu.
1133 */
1134 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1135 }
1136
1137 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1138 {
1139 int version;
1140 int r;
1141 struct pvclock_wall_clock wc;
1142 struct timespec boot;
1143
1144 if (!wall_clock)
1145 return;
1146
1147 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1148 if (r)
1149 return;
1150
1151 if (version & 1)
1152 ++version; /* first time write, random junk */
1153
1154 ++version;
1155
1156 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1157
1158 /*
1159 * The guest calculates current wall clock time by adding
1160 * system time (updated by kvm_guest_time_update below) to the
1161 * wall clock specified here. guest system time equals host
1162 * system time for us, thus we must fill in host boot time here.
1163 */
1164 getboottime(&boot);
1165
1166 if (kvm->arch.kvmclock_offset) {
1167 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1168 boot = timespec_sub(boot, ts);
1169 }
1170 wc.sec = boot.tv_sec;
1171 wc.nsec = boot.tv_nsec;
1172 wc.version = version;
1173
1174 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1175
1176 version++;
1177 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1178 }
1179
1180 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1181 {
1182 uint32_t quotient, remainder;
1183
1184 /* Don't try to replace with do_div(), this one calculates
1185 * "(dividend << 32) / divisor" */
1186 __asm__ ( "divl %4"
1187 : "=a" (quotient), "=d" (remainder)
1188 : "0" (0), "1" (dividend), "r" (divisor) );
1189 return quotient;
1190 }
1191
1192 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1193 s8 *pshift, u32 *pmultiplier)
1194 {
1195 uint64_t scaled64;
1196 int32_t shift = 0;
1197 uint64_t tps64;
1198 uint32_t tps32;
1199
1200 tps64 = base_khz * 1000LL;
1201 scaled64 = scaled_khz * 1000LL;
1202 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1203 tps64 >>= 1;
1204 shift--;
1205 }
1206
1207 tps32 = (uint32_t)tps64;
1208 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1209 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1210 scaled64 >>= 1;
1211 else
1212 tps32 <<= 1;
1213 shift++;
1214 }
1215
1216 *pshift = shift;
1217 *pmultiplier = div_frac(scaled64, tps32);
1218
1219 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1220 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1221 }
1222
1223 #ifdef CONFIG_X86_64
1224 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1225 #endif
1226
1227 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1228 static unsigned long max_tsc_khz;
1229
1230 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1231 {
1232 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1233 vcpu->arch.virtual_tsc_shift);
1234 }
1235
1236 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1237 {
1238 u64 v = (u64)khz * (1000000 + ppm);
1239 do_div(v, 1000000);
1240 return v;
1241 }
1242
1243 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1244 {
1245 u32 thresh_lo, thresh_hi;
1246 int use_scaling = 0;
1247
1248 /* tsc_khz can be zero if TSC calibration fails */
1249 if (this_tsc_khz == 0)
1250 return;
1251
1252 /* Compute a scale to convert nanoseconds in TSC cycles */
1253 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1254 &vcpu->arch.virtual_tsc_shift,
1255 &vcpu->arch.virtual_tsc_mult);
1256 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1257
1258 /*
1259 * Compute the variation in TSC rate which is acceptable
1260 * within the range of tolerance and decide if the
1261 * rate being applied is within that bounds of the hardware
1262 * rate. If so, no scaling or compensation need be done.
1263 */
1264 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1265 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1266 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1267 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1268 use_scaling = 1;
1269 }
1270 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1271 }
1272
1273 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1274 {
1275 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1276 vcpu->arch.virtual_tsc_mult,
1277 vcpu->arch.virtual_tsc_shift);
1278 tsc += vcpu->arch.this_tsc_write;
1279 return tsc;
1280 }
1281
1282 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1283 {
1284 #ifdef CONFIG_X86_64
1285 bool vcpus_matched;
1286 struct kvm_arch *ka = &vcpu->kvm->arch;
1287 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1288
1289 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1290 atomic_read(&vcpu->kvm->online_vcpus));
1291
1292 /*
1293 * Once the masterclock is enabled, always perform request in
1294 * order to update it.
1295 *
1296 * In order to enable masterclock, the host clocksource must be TSC
1297 * and the vcpus need to have matched TSCs. When that happens,
1298 * perform request to enable masterclock.
1299 */
1300 if (ka->use_master_clock ||
1301 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1302 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1303
1304 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1305 atomic_read(&vcpu->kvm->online_vcpus),
1306 ka->use_master_clock, gtod->clock.vclock_mode);
1307 #endif
1308 }
1309
1310 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1311 {
1312 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1313 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1314 }
1315
1316 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1317 {
1318 struct kvm *kvm = vcpu->kvm;
1319 u64 offset, ns, elapsed;
1320 unsigned long flags;
1321 s64 usdiff;
1322 bool matched;
1323 bool already_matched;
1324 u64 data = msr->data;
1325
1326 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1327 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1328 ns = get_kernel_ns();
1329 elapsed = ns - kvm->arch.last_tsc_nsec;
1330
1331 if (vcpu->arch.virtual_tsc_khz) {
1332 int faulted = 0;
1333
1334 /* n.b - signed multiplication and division required */
1335 usdiff = data - kvm->arch.last_tsc_write;
1336 #ifdef CONFIG_X86_64
1337 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1338 #else
1339 /* do_div() only does unsigned */
1340 asm("1: idivl %[divisor]\n"
1341 "2: xor %%edx, %%edx\n"
1342 " movl $0, %[faulted]\n"
1343 "3:\n"
1344 ".section .fixup,\"ax\"\n"
1345 "4: movl $1, %[faulted]\n"
1346 " jmp 3b\n"
1347 ".previous\n"
1348
1349 _ASM_EXTABLE(1b, 4b)
1350
1351 : "=A"(usdiff), [faulted] "=r" (faulted)
1352 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1353
1354 #endif
1355 do_div(elapsed, 1000);
1356 usdiff -= elapsed;
1357 if (usdiff < 0)
1358 usdiff = -usdiff;
1359
1360 /* idivl overflow => difference is larger than USEC_PER_SEC */
1361 if (faulted)
1362 usdiff = USEC_PER_SEC;
1363 } else
1364 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1365
1366 /*
1367 * Special case: TSC write with a small delta (1 second) of virtual
1368 * cycle time against real time is interpreted as an attempt to
1369 * synchronize the CPU.
1370 *
1371 * For a reliable TSC, we can match TSC offsets, and for an unstable
1372 * TSC, we add elapsed time in this computation. We could let the
1373 * compensation code attempt to catch up if we fall behind, but
1374 * it's better to try to match offsets from the beginning.
1375 */
1376 if (usdiff < USEC_PER_SEC &&
1377 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1378 if (!check_tsc_unstable()) {
1379 offset = kvm->arch.cur_tsc_offset;
1380 pr_debug("kvm: matched tsc offset for %llu\n", data);
1381 } else {
1382 u64 delta = nsec_to_cycles(vcpu, elapsed);
1383 data += delta;
1384 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1385 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1386 }
1387 matched = true;
1388 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1389 } else {
1390 /*
1391 * We split periods of matched TSC writes into generations.
1392 * For each generation, we track the original measured
1393 * nanosecond time, offset, and write, so if TSCs are in
1394 * sync, we can match exact offset, and if not, we can match
1395 * exact software computation in compute_guest_tsc()
1396 *
1397 * These values are tracked in kvm->arch.cur_xxx variables.
1398 */
1399 kvm->arch.cur_tsc_generation++;
1400 kvm->arch.cur_tsc_nsec = ns;
1401 kvm->arch.cur_tsc_write = data;
1402 kvm->arch.cur_tsc_offset = offset;
1403 matched = false;
1404 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1405 kvm->arch.cur_tsc_generation, data);
1406 }
1407
1408 /*
1409 * We also track th most recent recorded KHZ, write and time to
1410 * allow the matching interval to be extended at each write.
1411 */
1412 kvm->arch.last_tsc_nsec = ns;
1413 kvm->arch.last_tsc_write = data;
1414 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1415
1416 vcpu->arch.last_guest_tsc = data;
1417
1418 /* Keep track of which generation this VCPU has synchronized to */
1419 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1420 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1421 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1422
1423 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1424 update_ia32_tsc_adjust_msr(vcpu, offset);
1425 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1426 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1427
1428 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1429 if (!matched) {
1430 kvm->arch.nr_vcpus_matched_tsc = 0;
1431 } else if (!already_matched) {
1432 kvm->arch.nr_vcpus_matched_tsc++;
1433 }
1434
1435 kvm_track_tsc_matching(vcpu);
1436 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1437 }
1438
1439 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1440
1441 #ifdef CONFIG_X86_64
1442
1443 static cycle_t read_tsc(void)
1444 {
1445 cycle_t ret = (cycle_t)rdtsc_ordered();
1446 u64 last = pvclock_gtod_data.clock.cycle_last;
1447
1448 if (likely(ret >= last))
1449 return ret;
1450
1451 /*
1452 * GCC likes to generate cmov here, but this branch is extremely
1453 * predictable (it's just a funciton of time and the likely is
1454 * very likely) and there's a data dependence, so force GCC
1455 * to generate a branch instead. I don't barrier() because
1456 * we don't actually need a barrier, and if this function
1457 * ever gets inlined it will generate worse code.
1458 */
1459 asm volatile ("");
1460 return last;
1461 }
1462
1463 static inline u64 vgettsc(cycle_t *cycle_now)
1464 {
1465 long v;
1466 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1467
1468 *cycle_now = read_tsc();
1469
1470 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1471 return v * gtod->clock.mult;
1472 }
1473
1474 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1475 {
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477 unsigned long seq;
1478 int mode;
1479 u64 ns;
1480
1481 do {
1482 seq = read_seqcount_begin(&gtod->seq);
1483 mode = gtod->clock.vclock_mode;
1484 ns = gtod->nsec_base;
1485 ns += vgettsc(cycle_now);
1486 ns >>= gtod->clock.shift;
1487 ns += gtod->boot_ns;
1488 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1489 *t = ns;
1490
1491 return mode;
1492 }
1493
1494 /* returns true if host is using tsc clocksource */
1495 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1496 {
1497 /* checked again under seqlock below */
1498 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1499 return false;
1500
1501 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1502 }
1503 #endif
1504
1505 /*
1506 *
1507 * Assuming a stable TSC across physical CPUS, and a stable TSC
1508 * across virtual CPUs, the following condition is possible.
1509 * Each numbered line represents an event visible to both
1510 * CPUs at the next numbered event.
1511 *
1512 * "timespecX" represents host monotonic time. "tscX" represents
1513 * RDTSC value.
1514 *
1515 * VCPU0 on CPU0 | VCPU1 on CPU1
1516 *
1517 * 1. read timespec0,tsc0
1518 * 2. | timespec1 = timespec0 + N
1519 * | tsc1 = tsc0 + M
1520 * 3. transition to guest | transition to guest
1521 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1522 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1523 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1524 *
1525 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1526 *
1527 * - ret0 < ret1
1528 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1529 * ...
1530 * - 0 < N - M => M < N
1531 *
1532 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1533 * always the case (the difference between two distinct xtime instances
1534 * might be smaller then the difference between corresponding TSC reads,
1535 * when updating guest vcpus pvclock areas).
1536 *
1537 * To avoid that problem, do not allow visibility of distinct
1538 * system_timestamp/tsc_timestamp values simultaneously: use a master
1539 * copy of host monotonic time values. Update that master copy
1540 * in lockstep.
1541 *
1542 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1543 *
1544 */
1545
1546 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1547 {
1548 #ifdef CONFIG_X86_64
1549 struct kvm_arch *ka = &kvm->arch;
1550 int vclock_mode;
1551 bool host_tsc_clocksource, vcpus_matched;
1552
1553 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1554 atomic_read(&kvm->online_vcpus));
1555
1556 /*
1557 * If the host uses TSC clock, then passthrough TSC as stable
1558 * to the guest.
1559 */
1560 host_tsc_clocksource = kvm_get_time_and_clockread(
1561 &ka->master_kernel_ns,
1562 &ka->master_cycle_now);
1563
1564 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1565 && !backwards_tsc_observed
1566 && !ka->boot_vcpu_runs_old_kvmclock;
1567
1568 if (ka->use_master_clock)
1569 atomic_set(&kvm_guest_has_master_clock, 1);
1570
1571 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1572 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1573 vcpus_matched);
1574 #endif
1575 }
1576
1577 static void kvm_gen_update_masterclock(struct kvm *kvm)
1578 {
1579 #ifdef CONFIG_X86_64
1580 int i;
1581 struct kvm_vcpu *vcpu;
1582 struct kvm_arch *ka = &kvm->arch;
1583
1584 spin_lock(&ka->pvclock_gtod_sync_lock);
1585 kvm_make_mclock_inprogress_request(kvm);
1586 /* no guest entries from this point */
1587 pvclock_update_vm_gtod_copy(kvm);
1588
1589 kvm_for_each_vcpu(i, vcpu, kvm)
1590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1591
1592 /* guest entries allowed */
1593 kvm_for_each_vcpu(i, vcpu, kvm)
1594 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1595
1596 spin_unlock(&ka->pvclock_gtod_sync_lock);
1597 #endif
1598 }
1599
1600 static int kvm_guest_time_update(struct kvm_vcpu *v)
1601 {
1602 unsigned long flags, this_tsc_khz;
1603 struct kvm_vcpu_arch *vcpu = &v->arch;
1604 struct kvm_arch *ka = &v->kvm->arch;
1605 s64 kernel_ns;
1606 u64 tsc_timestamp, host_tsc;
1607 struct pvclock_vcpu_time_info guest_hv_clock;
1608 u8 pvclock_flags;
1609 bool use_master_clock;
1610
1611 kernel_ns = 0;
1612 host_tsc = 0;
1613
1614 /*
1615 * If the host uses TSC clock, then passthrough TSC as stable
1616 * to the guest.
1617 */
1618 spin_lock(&ka->pvclock_gtod_sync_lock);
1619 use_master_clock = ka->use_master_clock;
1620 if (use_master_clock) {
1621 host_tsc = ka->master_cycle_now;
1622 kernel_ns = ka->master_kernel_ns;
1623 }
1624 spin_unlock(&ka->pvclock_gtod_sync_lock);
1625
1626 /* Keep irq disabled to prevent changes to the clock */
1627 local_irq_save(flags);
1628 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1629 if (unlikely(this_tsc_khz == 0)) {
1630 local_irq_restore(flags);
1631 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1632 return 1;
1633 }
1634 if (!use_master_clock) {
1635 host_tsc = rdtsc();
1636 kernel_ns = get_kernel_ns();
1637 }
1638
1639 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1640
1641 /*
1642 * We may have to catch up the TSC to match elapsed wall clock
1643 * time for two reasons, even if kvmclock is used.
1644 * 1) CPU could have been running below the maximum TSC rate
1645 * 2) Broken TSC compensation resets the base at each VCPU
1646 * entry to avoid unknown leaps of TSC even when running
1647 * again on the same CPU. This may cause apparent elapsed
1648 * time to disappear, and the guest to stand still or run
1649 * very slowly.
1650 */
1651 if (vcpu->tsc_catchup) {
1652 u64 tsc = compute_guest_tsc(v, kernel_ns);
1653 if (tsc > tsc_timestamp) {
1654 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1655 tsc_timestamp = tsc;
1656 }
1657 }
1658
1659 local_irq_restore(flags);
1660
1661 if (!vcpu->pv_time_enabled)
1662 return 0;
1663
1664 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1665 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1666 &vcpu->hv_clock.tsc_shift,
1667 &vcpu->hv_clock.tsc_to_system_mul);
1668 vcpu->hw_tsc_khz = this_tsc_khz;
1669 }
1670
1671 /* With all the info we got, fill in the values */
1672 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1673 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1674 vcpu->last_guest_tsc = tsc_timestamp;
1675
1676 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1677 &guest_hv_clock, sizeof(guest_hv_clock))))
1678 return 0;
1679
1680 /* This VCPU is paused, but it's legal for a guest to read another
1681 * VCPU's kvmclock, so we really have to follow the specification where
1682 * it says that version is odd if data is being modified, and even after
1683 * it is consistent.
1684 *
1685 * Version field updates must be kept separate. This is because
1686 * kvm_write_guest_cached might use a "rep movs" instruction, and
1687 * writes within a string instruction are weakly ordered. So there
1688 * are three writes overall.
1689 *
1690 * As a small optimization, only write the version field in the first
1691 * and third write. The vcpu->pv_time cache is still valid, because the
1692 * version field is the first in the struct.
1693 */
1694 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1695
1696 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1697 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1698 &vcpu->hv_clock,
1699 sizeof(vcpu->hv_clock.version));
1700
1701 smp_wmb();
1702
1703 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1704 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1705
1706 if (vcpu->pvclock_set_guest_stopped_request) {
1707 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1708 vcpu->pvclock_set_guest_stopped_request = false;
1709 }
1710
1711 /* If the host uses TSC clocksource, then it is stable */
1712 if (use_master_clock)
1713 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1714
1715 vcpu->hv_clock.flags = pvclock_flags;
1716
1717 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1718
1719 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1720 &vcpu->hv_clock,
1721 sizeof(vcpu->hv_clock));
1722
1723 smp_wmb();
1724
1725 vcpu->hv_clock.version++;
1726 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1727 &vcpu->hv_clock,
1728 sizeof(vcpu->hv_clock.version));
1729 return 0;
1730 }
1731
1732 /*
1733 * kvmclock updates which are isolated to a given vcpu, such as
1734 * vcpu->cpu migration, should not allow system_timestamp from
1735 * the rest of the vcpus to remain static. Otherwise ntp frequency
1736 * correction applies to one vcpu's system_timestamp but not
1737 * the others.
1738 *
1739 * So in those cases, request a kvmclock update for all vcpus.
1740 * We need to rate-limit these requests though, as they can
1741 * considerably slow guests that have a large number of vcpus.
1742 * The time for a remote vcpu to update its kvmclock is bound
1743 * by the delay we use to rate-limit the updates.
1744 */
1745
1746 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1747
1748 static void kvmclock_update_fn(struct work_struct *work)
1749 {
1750 int i;
1751 struct delayed_work *dwork = to_delayed_work(work);
1752 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1753 kvmclock_update_work);
1754 struct kvm *kvm = container_of(ka, struct kvm, arch);
1755 struct kvm_vcpu *vcpu;
1756
1757 kvm_for_each_vcpu(i, vcpu, kvm) {
1758 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1759 kvm_vcpu_kick(vcpu);
1760 }
1761 }
1762
1763 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1764 {
1765 struct kvm *kvm = v->kvm;
1766
1767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1768 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1769 KVMCLOCK_UPDATE_DELAY);
1770 }
1771
1772 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1773
1774 static void kvmclock_sync_fn(struct work_struct *work)
1775 {
1776 struct delayed_work *dwork = to_delayed_work(work);
1777 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1778 kvmclock_sync_work);
1779 struct kvm *kvm = container_of(ka, struct kvm, arch);
1780
1781 if (!kvmclock_periodic_sync)
1782 return;
1783
1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1785 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1786 KVMCLOCK_SYNC_PERIOD);
1787 }
1788
1789 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1790 {
1791 u64 mcg_cap = vcpu->arch.mcg_cap;
1792 unsigned bank_num = mcg_cap & 0xff;
1793
1794 switch (msr) {
1795 case MSR_IA32_MCG_STATUS:
1796 vcpu->arch.mcg_status = data;
1797 break;
1798 case MSR_IA32_MCG_CTL:
1799 if (!(mcg_cap & MCG_CTL_P))
1800 return 1;
1801 if (data != 0 && data != ~(u64)0)
1802 return -1;
1803 vcpu->arch.mcg_ctl = data;
1804 break;
1805 default:
1806 if (msr >= MSR_IA32_MC0_CTL &&
1807 msr < MSR_IA32_MCx_CTL(bank_num)) {
1808 u32 offset = msr - MSR_IA32_MC0_CTL;
1809 /* only 0 or all 1s can be written to IA32_MCi_CTL
1810 * some Linux kernels though clear bit 10 in bank 4 to
1811 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1812 * this to avoid an uncatched #GP in the guest
1813 */
1814 if ((offset & 0x3) == 0 &&
1815 data != 0 && (data | (1 << 10)) != ~(u64)0)
1816 return -1;
1817 vcpu->arch.mce_banks[offset] = data;
1818 break;
1819 }
1820 return 1;
1821 }
1822 return 0;
1823 }
1824
1825 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1826 {
1827 struct kvm *kvm = vcpu->kvm;
1828 int lm = is_long_mode(vcpu);
1829 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1830 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1831 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1832 : kvm->arch.xen_hvm_config.blob_size_32;
1833 u32 page_num = data & ~PAGE_MASK;
1834 u64 page_addr = data & PAGE_MASK;
1835 u8 *page;
1836 int r;
1837
1838 r = -E2BIG;
1839 if (page_num >= blob_size)
1840 goto out;
1841 r = -ENOMEM;
1842 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1843 if (IS_ERR(page)) {
1844 r = PTR_ERR(page);
1845 goto out;
1846 }
1847 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1848 goto out_free;
1849 r = 0;
1850 out_free:
1851 kfree(page);
1852 out:
1853 return r;
1854 }
1855
1856 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1857 {
1858 gpa_t gpa = data & ~0x3f;
1859
1860 /* Bits 2:5 are reserved, Should be zero */
1861 if (data & 0x3c)
1862 return 1;
1863
1864 vcpu->arch.apf.msr_val = data;
1865
1866 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1867 kvm_clear_async_pf_completion_queue(vcpu);
1868 kvm_async_pf_hash_reset(vcpu);
1869 return 0;
1870 }
1871
1872 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1873 sizeof(u32)))
1874 return 1;
1875
1876 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1877 kvm_async_pf_wakeup_all(vcpu);
1878 return 0;
1879 }
1880
1881 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1882 {
1883 vcpu->arch.pv_time_enabled = false;
1884 }
1885
1886 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1887 {
1888 u64 delta;
1889
1890 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1891 return;
1892
1893 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1894 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1895 vcpu->arch.st.accum_steal = delta;
1896 }
1897
1898 static void record_steal_time(struct kvm_vcpu *vcpu)
1899 {
1900 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1901 return;
1902
1903 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1904 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1905 return;
1906
1907 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1908 vcpu->arch.st.steal.version += 2;
1909 vcpu->arch.st.accum_steal = 0;
1910
1911 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1912 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1913 }
1914
1915 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1916 {
1917 bool pr = false;
1918 u32 msr = msr_info->index;
1919 u64 data = msr_info->data;
1920
1921 switch (msr) {
1922 case MSR_AMD64_NB_CFG:
1923 case MSR_IA32_UCODE_REV:
1924 case MSR_IA32_UCODE_WRITE:
1925 case MSR_VM_HSAVE_PA:
1926 case MSR_AMD64_PATCH_LOADER:
1927 case MSR_AMD64_BU_CFG2:
1928 break;
1929
1930 case MSR_EFER:
1931 return set_efer(vcpu, data);
1932 case MSR_K7_HWCR:
1933 data &= ~(u64)0x40; /* ignore flush filter disable */
1934 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1935 data &= ~(u64)0x8; /* ignore TLB cache disable */
1936 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1937 if (data != 0) {
1938 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1939 data);
1940 return 1;
1941 }
1942 break;
1943 case MSR_FAM10H_MMIO_CONF_BASE:
1944 if (data != 0) {
1945 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1946 "0x%llx\n", data);
1947 return 1;
1948 }
1949 break;
1950 case MSR_IA32_DEBUGCTLMSR:
1951 if (!data) {
1952 /* We support the non-activated case already */
1953 break;
1954 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1955 /* Values other than LBR and BTF are vendor-specific,
1956 thus reserved and should throw a #GP */
1957 return 1;
1958 }
1959 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1960 __func__, data);
1961 break;
1962 case 0x200 ... 0x2ff:
1963 return kvm_mtrr_set_msr(vcpu, msr, data);
1964 case MSR_IA32_APICBASE:
1965 return kvm_set_apic_base(vcpu, msr_info);
1966 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1967 return kvm_x2apic_msr_write(vcpu, msr, data);
1968 case MSR_IA32_TSCDEADLINE:
1969 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1970 break;
1971 case MSR_IA32_TSC_ADJUST:
1972 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1973 if (!msr_info->host_initiated) {
1974 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1975 adjust_tsc_offset_guest(vcpu, adj);
1976 }
1977 vcpu->arch.ia32_tsc_adjust_msr = data;
1978 }
1979 break;
1980 case MSR_IA32_MISC_ENABLE:
1981 vcpu->arch.ia32_misc_enable_msr = data;
1982 break;
1983 case MSR_IA32_SMBASE:
1984 if (!msr_info->host_initiated)
1985 return 1;
1986 vcpu->arch.smbase = data;
1987 break;
1988 case MSR_KVM_WALL_CLOCK_NEW:
1989 case MSR_KVM_WALL_CLOCK:
1990 vcpu->kvm->arch.wall_clock = data;
1991 kvm_write_wall_clock(vcpu->kvm, data);
1992 break;
1993 case MSR_KVM_SYSTEM_TIME_NEW:
1994 case MSR_KVM_SYSTEM_TIME: {
1995 u64 gpa_offset;
1996 struct kvm_arch *ka = &vcpu->kvm->arch;
1997
1998 kvmclock_reset(vcpu);
1999
2000 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2001 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2002
2003 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2004 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2005 &vcpu->requests);
2006
2007 ka->boot_vcpu_runs_old_kvmclock = tmp;
2008 }
2009
2010 vcpu->arch.time = data;
2011 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2012
2013 /* we verify if the enable bit is set... */
2014 if (!(data & 1))
2015 break;
2016
2017 gpa_offset = data & ~(PAGE_MASK | 1);
2018
2019 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2020 &vcpu->arch.pv_time, data & ~1ULL,
2021 sizeof(struct pvclock_vcpu_time_info)))
2022 vcpu->arch.pv_time_enabled = false;
2023 else
2024 vcpu->arch.pv_time_enabled = true;
2025
2026 break;
2027 }
2028 case MSR_KVM_ASYNC_PF_EN:
2029 if (kvm_pv_enable_async_pf(vcpu, data))
2030 return 1;
2031 break;
2032 case MSR_KVM_STEAL_TIME:
2033
2034 if (unlikely(!sched_info_on()))
2035 return 1;
2036
2037 if (data & KVM_STEAL_RESERVED_MASK)
2038 return 1;
2039
2040 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2041 data & KVM_STEAL_VALID_BITS,
2042 sizeof(struct kvm_steal_time)))
2043 return 1;
2044
2045 vcpu->arch.st.msr_val = data;
2046
2047 if (!(data & KVM_MSR_ENABLED))
2048 break;
2049
2050 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2051
2052 preempt_disable();
2053 accumulate_steal_time(vcpu);
2054 preempt_enable();
2055
2056 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2057
2058 break;
2059 case MSR_KVM_PV_EOI_EN:
2060 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2061 return 1;
2062 break;
2063
2064 case MSR_IA32_MCG_CTL:
2065 case MSR_IA32_MCG_STATUS:
2066 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2067 return set_msr_mce(vcpu, msr, data);
2068
2069 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2070 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2071 pr = true; /* fall through */
2072 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2073 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2074 if (kvm_pmu_is_valid_msr(vcpu, msr))
2075 return kvm_pmu_set_msr(vcpu, msr_info);
2076
2077 if (pr || data != 0)
2078 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2079 "0x%x data 0x%llx\n", msr, data);
2080 break;
2081 case MSR_K7_CLK_CTL:
2082 /*
2083 * Ignore all writes to this no longer documented MSR.
2084 * Writes are only relevant for old K7 processors,
2085 * all pre-dating SVM, but a recommended workaround from
2086 * AMD for these chips. It is possible to specify the
2087 * affected processor models on the command line, hence
2088 * the need to ignore the workaround.
2089 */
2090 break;
2091 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2092 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2093 case HV_X64_MSR_CRASH_CTL:
2094 return kvm_hv_set_msr_common(vcpu, msr, data,
2095 msr_info->host_initiated);
2096 case MSR_IA32_BBL_CR_CTL3:
2097 /* Drop writes to this legacy MSR -- see rdmsr
2098 * counterpart for further detail.
2099 */
2100 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2101 break;
2102 case MSR_AMD64_OSVW_ID_LENGTH:
2103 if (!guest_cpuid_has_osvw(vcpu))
2104 return 1;
2105 vcpu->arch.osvw.length = data;
2106 break;
2107 case MSR_AMD64_OSVW_STATUS:
2108 if (!guest_cpuid_has_osvw(vcpu))
2109 return 1;
2110 vcpu->arch.osvw.status = data;
2111 break;
2112 default:
2113 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2114 return xen_hvm_config(vcpu, data);
2115 if (kvm_pmu_is_valid_msr(vcpu, msr))
2116 return kvm_pmu_set_msr(vcpu, msr_info);
2117 if (!ignore_msrs) {
2118 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2119 msr, data);
2120 return 1;
2121 } else {
2122 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2123 msr, data);
2124 break;
2125 }
2126 }
2127 return 0;
2128 }
2129 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2130
2131
2132 /*
2133 * Reads an msr value (of 'msr_index') into 'pdata'.
2134 * Returns 0 on success, non-0 otherwise.
2135 * Assumes vcpu_load() was already called.
2136 */
2137 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2138 {
2139 return kvm_x86_ops->get_msr(vcpu, msr);
2140 }
2141 EXPORT_SYMBOL_GPL(kvm_get_msr);
2142
2143 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2144 {
2145 u64 data;
2146 u64 mcg_cap = vcpu->arch.mcg_cap;
2147 unsigned bank_num = mcg_cap & 0xff;
2148
2149 switch (msr) {
2150 case MSR_IA32_P5_MC_ADDR:
2151 case MSR_IA32_P5_MC_TYPE:
2152 data = 0;
2153 break;
2154 case MSR_IA32_MCG_CAP:
2155 data = vcpu->arch.mcg_cap;
2156 break;
2157 case MSR_IA32_MCG_CTL:
2158 if (!(mcg_cap & MCG_CTL_P))
2159 return 1;
2160 data = vcpu->arch.mcg_ctl;
2161 break;
2162 case MSR_IA32_MCG_STATUS:
2163 data = vcpu->arch.mcg_status;
2164 break;
2165 default:
2166 if (msr >= MSR_IA32_MC0_CTL &&
2167 msr < MSR_IA32_MCx_CTL(bank_num)) {
2168 u32 offset = msr - MSR_IA32_MC0_CTL;
2169 data = vcpu->arch.mce_banks[offset];
2170 break;
2171 }
2172 return 1;
2173 }
2174 *pdata = data;
2175 return 0;
2176 }
2177
2178 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2179 {
2180 switch (msr_info->index) {
2181 case MSR_IA32_PLATFORM_ID:
2182 case MSR_IA32_EBL_CR_POWERON:
2183 case MSR_IA32_DEBUGCTLMSR:
2184 case MSR_IA32_LASTBRANCHFROMIP:
2185 case MSR_IA32_LASTBRANCHTOIP:
2186 case MSR_IA32_LASTINTFROMIP:
2187 case MSR_IA32_LASTINTTOIP:
2188 case MSR_K8_SYSCFG:
2189 case MSR_K8_TSEG_ADDR:
2190 case MSR_K8_TSEG_MASK:
2191 case MSR_K7_HWCR:
2192 case MSR_VM_HSAVE_PA:
2193 case MSR_K8_INT_PENDING_MSG:
2194 case MSR_AMD64_NB_CFG:
2195 case MSR_FAM10H_MMIO_CONF_BASE:
2196 case MSR_AMD64_BU_CFG2:
2197 msr_info->data = 0;
2198 break;
2199 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2200 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2201 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2202 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2203 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2204 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2205 msr_info->data = 0;
2206 break;
2207 case MSR_IA32_UCODE_REV:
2208 msr_info->data = 0x100000000ULL;
2209 break;
2210 case MSR_MTRRcap:
2211 case 0x200 ... 0x2ff:
2212 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2213 case 0xcd: /* fsb frequency */
2214 msr_info->data = 3;
2215 break;
2216 /*
2217 * MSR_EBC_FREQUENCY_ID
2218 * Conservative value valid for even the basic CPU models.
2219 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2220 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2221 * and 266MHz for model 3, or 4. Set Core Clock
2222 * Frequency to System Bus Frequency Ratio to 1 (bits
2223 * 31:24) even though these are only valid for CPU
2224 * models > 2, however guests may end up dividing or
2225 * multiplying by zero otherwise.
2226 */
2227 case MSR_EBC_FREQUENCY_ID:
2228 msr_info->data = 1 << 24;
2229 break;
2230 case MSR_IA32_APICBASE:
2231 msr_info->data = kvm_get_apic_base(vcpu);
2232 break;
2233 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2234 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2235 break;
2236 case MSR_IA32_TSCDEADLINE:
2237 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2238 break;
2239 case MSR_IA32_TSC_ADJUST:
2240 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2241 break;
2242 case MSR_IA32_MISC_ENABLE:
2243 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2244 break;
2245 case MSR_IA32_SMBASE:
2246 if (!msr_info->host_initiated)
2247 return 1;
2248 msr_info->data = vcpu->arch.smbase;
2249 break;
2250 case MSR_IA32_PERF_STATUS:
2251 /* TSC increment by tick */
2252 msr_info->data = 1000ULL;
2253 /* CPU multiplier */
2254 msr_info->data |= (((uint64_t)4ULL) << 40);
2255 break;
2256 case MSR_EFER:
2257 msr_info->data = vcpu->arch.efer;
2258 break;
2259 case MSR_KVM_WALL_CLOCK:
2260 case MSR_KVM_WALL_CLOCK_NEW:
2261 msr_info->data = vcpu->kvm->arch.wall_clock;
2262 break;
2263 case MSR_KVM_SYSTEM_TIME:
2264 case MSR_KVM_SYSTEM_TIME_NEW:
2265 msr_info->data = vcpu->arch.time;
2266 break;
2267 case MSR_KVM_ASYNC_PF_EN:
2268 msr_info->data = vcpu->arch.apf.msr_val;
2269 break;
2270 case MSR_KVM_STEAL_TIME:
2271 msr_info->data = vcpu->arch.st.msr_val;
2272 break;
2273 case MSR_KVM_PV_EOI_EN:
2274 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2275 break;
2276 case MSR_IA32_P5_MC_ADDR:
2277 case MSR_IA32_P5_MC_TYPE:
2278 case MSR_IA32_MCG_CAP:
2279 case MSR_IA32_MCG_CTL:
2280 case MSR_IA32_MCG_STATUS:
2281 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2282 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2283 case MSR_K7_CLK_CTL:
2284 /*
2285 * Provide expected ramp-up count for K7. All other
2286 * are set to zero, indicating minimum divisors for
2287 * every field.
2288 *
2289 * This prevents guest kernels on AMD host with CPU
2290 * type 6, model 8 and higher from exploding due to
2291 * the rdmsr failing.
2292 */
2293 msr_info->data = 0x20000000;
2294 break;
2295 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2296 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2297 case HV_X64_MSR_CRASH_CTL:
2298 return kvm_hv_get_msr_common(vcpu,
2299 msr_info->index, &msr_info->data);
2300 break;
2301 case MSR_IA32_BBL_CR_CTL3:
2302 /* This legacy MSR exists but isn't fully documented in current
2303 * silicon. It is however accessed by winxp in very narrow
2304 * scenarios where it sets bit #19, itself documented as
2305 * a "reserved" bit. Best effort attempt to source coherent
2306 * read data here should the balance of the register be
2307 * interpreted by the guest:
2308 *
2309 * L2 cache control register 3: 64GB range, 256KB size,
2310 * enabled, latency 0x1, configured
2311 */
2312 msr_info->data = 0xbe702111;
2313 break;
2314 case MSR_AMD64_OSVW_ID_LENGTH:
2315 if (!guest_cpuid_has_osvw(vcpu))
2316 return 1;
2317 msr_info->data = vcpu->arch.osvw.length;
2318 break;
2319 case MSR_AMD64_OSVW_STATUS:
2320 if (!guest_cpuid_has_osvw(vcpu))
2321 return 1;
2322 msr_info->data = vcpu->arch.osvw.status;
2323 break;
2324 default:
2325 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2326 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2327 if (!ignore_msrs) {
2328 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2329 return 1;
2330 } else {
2331 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2332 msr_info->data = 0;
2333 }
2334 break;
2335 }
2336 return 0;
2337 }
2338 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2339
2340 /*
2341 * Read or write a bunch of msrs. All parameters are kernel addresses.
2342 *
2343 * @return number of msrs set successfully.
2344 */
2345 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2346 struct kvm_msr_entry *entries,
2347 int (*do_msr)(struct kvm_vcpu *vcpu,
2348 unsigned index, u64 *data))
2349 {
2350 int i, idx;
2351
2352 idx = srcu_read_lock(&vcpu->kvm->srcu);
2353 for (i = 0; i < msrs->nmsrs; ++i)
2354 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2355 break;
2356 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2357
2358 return i;
2359 }
2360
2361 /*
2362 * Read or write a bunch of msrs. Parameters are user addresses.
2363 *
2364 * @return number of msrs set successfully.
2365 */
2366 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2367 int (*do_msr)(struct kvm_vcpu *vcpu,
2368 unsigned index, u64 *data),
2369 int writeback)
2370 {
2371 struct kvm_msrs msrs;
2372 struct kvm_msr_entry *entries;
2373 int r, n;
2374 unsigned size;
2375
2376 r = -EFAULT;
2377 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2378 goto out;
2379
2380 r = -E2BIG;
2381 if (msrs.nmsrs >= MAX_IO_MSRS)
2382 goto out;
2383
2384 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2385 entries = memdup_user(user_msrs->entries, size);
2386 if (IS_ERR(entries)) {
2387 r = PTR_ERR(entries);
2388 goto out;
2389 }
2390
2391 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2392 if (r < 0)
2393 goto out_free;
2394
2395 r = -EFAULT;
2396 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2397 goto out_free;
2398
2399 r = n;
2400
2401 out_free:
2402 kfree(entries);
2403 out:
2404 return r;
2405 }
2406
2407 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2408 {
2409 int r;
2410
2411 switch (ext) {
2412 case KVM_CAP_IRQCHIP:
2413 case KVM_CAP_HLT:
2414 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2415 case KVM_CAP_SET_TSS_ADDR:
2416 case KVM_CAP_EXT_CPUID:
2417 case KVM_CAP_EXT_EMUL_CPUID:
2418 case KVM_CAP_CLOCKSOURCE:
2419 case KVM_CAP_PIT:
2420 case KVM_CAP_NOP_IO_DELAY:
2421 case KVM_CAP_MP_STATE:
2422 case KVM_CAP_SYNC_MMU:
2423 case KVM_CAP_USER_NMI:
2424 case KVM_CAP_REINJECT_CONTROL:
2425 case KVM_CAP_IRQ_INJECT_STATUS:
2426 case KVM_CAP_IOEVENTFD:
2427 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2428 case KVM_CAP_PIT2:
2429 case KVM_CAP_PIT_STATE2:
2430 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2431 case KVM_CAP_XEN_HVM:
2432 case KVM_CAP_ADJUST_CLOCK:
2433 case KVM_CAP_VCPU_EVENTS:
2434 case KVM_CAP_HYPERV:
2435 case KVM_CAP_HYPERV_VAPIC:
2436 case KVM_CAP_HYPERV_SPIN:
2437 case KVM_CAP_PCI_SEGMENT:
2438 case KVM_CAP_DEBUGREGS:
2439 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2440 case KVM_CAP_XSAVE:
2441 case KVM_CAP_ASYNC_PF:
2442 case KVM_CAP_GET_TSC_KHZ:
2443 case KVM_CAP_KVMCLOCK_CTRL:
2444 case KVM_CAP_READONLY_MEM:
2445 case KVM_CAP_HYPERV_TIME:
2446 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2447 case KVM_CAP_TSC_DEADLINE_TIMER:
2448 case KVM_CAP_ENABLE_CAP_VM:
2449 case KVM_CAP_DISABLE_QUIRKS:
2450 case KVM_CAP_SET_BOOT_CPU_ID:
2451 case KVM_CAP_SPLIT_IRQCHIP:
2452 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2453 case KVM_CAP_ASSIGN_DEV_IRQ:
2454 case KVM_CAP_PCI_2_3:
2455 #endif
2456 r = 1;
2457 break;
2458 case KVM_CAP_X86_SMM:
2459 /* SMBASE is usually relocated above 1M on modern chipsets,
2460 * and SMM handlers might indeed rely on 4G segment limits,
2461 * so do not report SMM to be available if real mode is
2462 * emulated via vm86 mode. Still, do not go to great lengths
2463 * to avoid userspace's usage of the feature, because it is a
2464 * fringe case that is not enabled except via specific settings
2465 * of the module parameters.
2466 */
2467 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2468 break;
2469 case KVM_CAP_COALESCED_MMIO:
2470 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2471 break;
2472 case KVM_CAP_VAPIC:
2473 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2474 break;
2475 case KVM_CAP_NR_VCPUS:
2476 r = KVM_SOFT_MAX_VCPUS;
2477 break;
2478 case KVM_CAP_MAX_VCPUS:
2479 r = KVM_MAX_VCPUS;
2480 break;
2481 case KVM_CAP_NR_MEMSLOTS:
2482 r = KVM_USER_MEM_SLOTS;
2483 break;
2484 case KVM_CAP_PV_MMU: /* obsolete */
2485 r = 0;
2486 break;
2487 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2488 case KVM_CAP_IOMMU:
2489 r = iommu_present(&pci_bus_type);
2490 break;
2491 #endif
2492 case KVM_CAP_MCE:
2493 r = KVM_MAX_MCE_BANKS;
2494 break;
2495 case KVM_CAP_XCRS:
2496 r = cpu_has_xsave;
2497 break;
2498 case KVM_CAP_TSC_CONTROL:
2499 r = kvm_has_tsc_control;
2500 break;
2501 default:
2502 r = 0;
2503 break;
2504 }
2505 return r;
2506
2507 }
2508
2509 long kvm_arch_dev_ioctl(struct file *filp,
2510 unsigned int ioctl, unsigned long arg)
2511 {
2512 void __user *argp = (void __user *)arg;
2513 long r;
2514
2515 switch (ioctl) {
2516 case KVM_GET_MSR_INDEX_LIST: {
2517 struct kvm_msr_list __user *user_msr_list = argp;
2518 struct kvm_msr_list msr_list;
2519 unsigned n;
2520
2521 r = -EFAULT;
2522 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2523 goto out;
2524 n = msr_list.nmsrs;
2525 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2526 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2527 goto out;
2528 r = -E2BIG;
2529 if (n < msr_list.nmsrs)
2530 goto out;
2531 r = -EFAULT;
2532 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2533 num_msrs_to_save * sizeof(u32)))
2534 goto out;
2535 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2536 &emulated_msrs,
2537 num_emulated_msrs * sizeof(u32)))
2538 goto out;
2539 r = 0;
2540 break;
2541 }
2542 case KVM_GET_SUPPORTED_CPUID:
2543 case KVM_GET_EMULATED_CPUID: {
2544 struct kvm_cpuid2 __user *cpuid_arg = argp;
2545 struct kvm_cpuid2 cpuid;
2546
2547 r = -EFAULT;
2548 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2549 goto out;
2550
2551 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2552 ioctl);
2553 if (r)
2554 goto out;
2555
2556 r = -EFAULT;
2557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2558 goto out;
2559 r = 0;
2560 break;
2561 }
2562 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2563 u64 mce_cap;
2564
2565 mce_cap = KVM_MCE_CAP_SUPPORTED;
2566 r = -EFAULT;
2567 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2568 goto out;
2569 r = 0;
2570 break;
2571 }
2572 default:
2573 r = -EINVAL;
2574 }
2575 out:
2576 return r;
2577 }
2578
2579 static void wbinvd_ipi(void *garbage)
2580 {
2581 wbinvd();
2582 }
2583
2584 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2585 {
2586 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2587 }
2588
2589 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2590 {
2591 /* Address WBINVD may be executed by guest */
2592 if (need_emulate_wbinvd(vcpu)) {
2593 if (kvm_x86_ops->has_wbinvd_exit())
2594 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2595 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2596 smp_call_function_single(vcpu->cpu,
2597 wbinvd_ipi, NULL, 1);
2598 }
2599
2600 kvm_x86_ops->vcpu_load(vcpu, cpu);
2601
2602 /* Apply any externally detected TSC adjustments (due to suspend) */
2603 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2604 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2605 vcpu->arch.tsc_offset_adjustment = 0;
2606 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2607 }
2608
2609 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2610 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2611 rdtsc() - vcpu->arch.last_host_tsc;
2612 if (tsc_delta < 0)
2613 mark_tsc_unstable("KVM discovered backwards TSC");
2614 if (check_tsc_unstable()) {
2615 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2616 vcpu->arch.last_guest_tsc);
2617 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2618 vcpu->arch.tsc_catchup = 1;
2619 }
2620 /*
2621 * On a host with synchronized TSC, there is no need to update
2622 * kvmclock on vcpu->cpu migration
2623 */
2624 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2625 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2626 if (vcpu->cpu != cpu)
2627 kvm_migrate_timers(vcpu);
2628 vcpu->cpu = cpu;
2629 }
2630
2631 accumulate_steal_time(vcpu);
2632 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2633 }
2634
2635 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2636 {
2637 kvm_x86_ops->vcpu_put(vcpu);
2638 kvm_put_guest_fpu(vcpu);
2639 vcpu->arch.last_host_tsc = rdtsc();
2640 }
2641
2642 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2643 struct kvm_lapic_state *s)
2644 {
2645 kvm_x86_ops->sync_pir_to_irr(vcpu);
2646 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2647
2648 return 0;
2649 }
2650
2651 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2652 struct kvm_lapic_state *s)
2653 {
2654 kvm_apic_post_state_restore(vcpu, s);
2655 update_cr8_intercept(vcpu);
2656
2657 return 0;
2658 }
2659
2660 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2661 struct kvm_interrupt *irq)
2662 {
2663 if (irq->irq >= KVM_NR_INTERRUPTS)
2664 return -EINVAL;
2665 if (irqchip_in_kernel(vcpu->kvm))
2666 return -ENXIO;
2667
2668 kvm_queue_interrupt(vcpu, irq->irq, false);
2669 kvm_make_request(KVM_REQ_EVENT, vcpu);
2670
2671 return 0;
2672 }
2673
2674 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2675 {
2676 kvm_inject_nmi(vcpu);
2677
2678 return 0;
2679 }
2680
2681 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2682 {
2683 kvm_make_request(KVM_REQ_SMI, vcpu);
2684
2685 return 0;
2686 }
2687
2688 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2689 struct kvm_tpr_access_ctl *tac)
2690 {
2691 if (tac->flags)
2692 return -EINVAL;
2693 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2694 return 0;
2695 }
2696
2697 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2698 u64 mcg_cap)
2699 {
2700 int r;
2701 unsigned bank_num = mcg_cap & 0xff, bank;
2702
2703 r = -EINVAL;
2704 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2705 goto out;
2706 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2707 goto out;
2708 r = 0;
2709 vcpu->arch.mcg_cap = mcg_cap;
2710 /* Init IA32_MCG_CTL to all 1s */
2711 if (mcg_cap & MCG_CTL_P)
2712 vcpu->arch.mcg_ctl = ~(u64)0;
2713 /* Init IA32_MCi_CTL to all 1s */
2714 for (bank = 0; bank < bank_num; bank++)
2715 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2716 out:
2717 return r;
2718 }
2719
2720 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2721 struct kvm_x86_mce *mce)
2722 {
2723 u64 mcg_cap = vcpu->arch.mcg_cap;
2724 unsigned bank_num = mcg_cap & 0xff;
2725 u64 *banks = vcpu->arch.mce_banks;
2726
2727 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2728 return -EINVAL;
2729 /*
2730 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2731 * reporting is disabled
2732 */
2733 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2734 vcpu->arch.mcg_ctl != ~(u64)0)
2735 return 0;
2736 banks += 4 * mce->bank;
2737 /*
2738 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2739 * reporting is disabled for the bank
2740 */
2741 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2742 return 0;
2743 if (mce->status & MCI_STATUS_UC) {
2744 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2745 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2746 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2747 return 0;
2748 }
2749 if (banks[1] & MCI_STATUS_VAL)
2750 mce->status |= MCI_STATUS_OVER;
2751 banks[2] = mce->addr;
2752 banks[3] = mce->misc;
2753 vcpu->arch.mcg_status = mce->mcg_status;
2754 banks[1] = mce->status;
2755 kvm_queue_exception(vcpu, MC_VECTOR);
2756 } else if (!(banks[1] & MCI_STATUS_VAL)
2757 || !(banks[1] & MCI_STATUS_UC)) {
2758 if (banks[1] & MCI_STATUS_VAL)
2759 mce->status |= MCI_STATUS_OVER;
2760 banks[2] = mce->addr;
2761 banks[3] = mce->misc;
2762 banks[1] = mce->status;
2763 } else
2764 banks[1] |= MCI_STATUS_OVER;
2765 return 0;
2766 }
2767
2768 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2769 struct kvm_vcpu_events *events)
2770 {
2771 process_nmi(vcpu);
2772 events->exception.injected =
2773 vcpu->arch.exception.pending &&
2774 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2775 events->exception.nr = vcpu->arch.exception.nr;
2776 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2777 events->exception.pad = 0;
2778 events->exception.error_code = vcpu->arch.exception.error_code;
2779
2780 events->interrupt.injected =
2781 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2782 events->interrupt.nr = vcpu->arch.interrupt.nr;
2783 events->interrupt.soft = 0;
2784 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2785
2786 events->nmi.injected = vcpu->arch.nmi_injected;
2787 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2788 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2789 events->nmi.pad = 0;
2790
2791 events->sipi_vector = 0; /* never valid when reporting to user space */
2792
2793 events->smi.smm = is_smm(vcpu);
2794 events->smi.pending = vcpu->arch.smi_pending;
2795 events->smi.smm_inside_nmi =
2796 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2797 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2798
2799 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2800 | KVM_VCPUEVENT_VALID_SHADOW
2801 | KVM_VCPUEVENT_VALID_SMM);
2802 memset(&events->reserved, 0, sizeof(events->reserved));
2803 }
2804
2805 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2806 struct kvm_vcpu_events *events)
2807 {
2808 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2809 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2810 | KVM_VCPUEVENT_VALID_SHADOW
2811 | KVM_VCPUEVENT_VALID_SMM))
2812 return -EINVAL;
2813
2814 process_nmi(vcpu);
2815 vcpu->arch.exception.pending = events->exception.injected;
2816 vcpu->arch.exception.nr = events->exception.nr;
2817 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2818 vcpu->arch.exception.error_code = events->exception.error_code;
2819
2820 vcpu->arch.interrupt.pending = events->interrupt.injected;
2821 vcpu->arch.interrupt.nr = events->interrupt.nr;
2822 vcpu->arch.interrupt.soft = events->interrupt.soft;
2823 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2824 kvm_x86_ops->set_interrupt_shadow(vcpu,
2825 events->interrupt.shadow);
2826
2827 vcpu->arch.nmi_injected = events->nmi.injected;
2828 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2829 vcpu->arch.nmi_pending = events->nmi.pending;
2830 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2831
2832 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2833 kvm_vcpu_has_lapic(vcpu))
2834 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2835
2836 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2837 if (events->smi.smm)
2838 vcpu->arch.hflags |= HF_SMM_MASK;
2839 else
2840 vcpu->arch.hflags &= ~HF_SMM_MASK;
2841 vcpu->arch.smi_pending = events->smi.pending;
2842 if (events->smi.smm_inside_nmi)
2843 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2844 else
2845 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2846 if (kvm_vcpu_has_lapic(vcpu)) {
2847 if (events->smi.latched_init)
2848 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2849 else
2850 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2851 }
2852 }
2853
2854 kvm_make_request(KVM_REQ_EVENT, vcpu);
2855
2856 return 0;
2857 }
2858
2859 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2860 struct kvm_debugregs *dbgregs)
2861 {
2862 unsigned long val;
2863
2864 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2865 kvm_get_dr(vcpu, 6, &val);
2866 dbgregs->dr6 = val;
2867 dbgregs->dr7 = vcpu->arch.dr7;
2868 dbgregs->flags = 0;
2869 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2870 }
2871
2872 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2873 struct kvm_debugregs *dbgregs)
2874 {
2875 if (dbgregs->flags)
2876 return -EINVAL;
2877
2878 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2879 kvm_update_dr0123(vcpu);
2880 vcpu->arch.dr6 = dbgregs->dr6;
2881 kvm_update_dr6(vcpu);
2882 vcpu->arch.dr7 = dbgregs->dr7;
2883 kvm_update_dr7(vcpu);
2884
2885 return 0;
2886 }
2887
2888 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2889
2890 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2891 {
2892 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2893 u64 xstate_bv = xsave->header.xfeatures;
2894 u64 valid;
2895
2896 /*
2897 * Copy legacy XSAVE area, to avoid complications with CPUID
2898 * leaves 0 and 1 in the loop below.
2899 */
2900 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2901
2902 /* Set XSTATE_BV */
2903 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2904
2905 /*
2906 * Copy each region from the possibly compacted offset to the
2907 * non-compacted offset.
2908 */
2909 valid = xstate_bv & ~XSTATE_FPSSE;
2910 while (valid) {
2911 u64 feature = valid & -valid;
2912 int index = fls64(feature) - 1;
2913 void *src = get_xsave_addr(xsave, feature);
2914
2915 if (src) {
2916 u32 size, offset, ecx, edx;
2917 cpuid_count(XSTATE_CPUID, index,
2918 &size, &offset, &ecx, &edx);
2919 memcpy(dest + offset, src, size);
2920 }
2921
2922 valid -= feature;
2923 }
2924 }
2925
2926 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2927 {
2928 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2929 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2930 u64 valid;
2931
2932 /*
2933 * Copy legacy XSAVE area, to avoid complications with CPUID
2934 * leaves 0 and 1 in the loop below.
2935 */
2936 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2937
2938 /* Set XSTATE_BV and possibly XCOMP_BV. */
2939 xsave->header.xfeatures = xstate_bv;
2940 if (cpu_has_xsaves)
2941 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2942
2943 /*
2944 * Copy each region from the non-compacted offset to the
2945 * possibly compacted offset.
2946 */
2947 valid = xstate_bv & ~XSTATE_FPSSE;
2948 while (valid) {
2949 u64 feature = valid & -valid;
2950 int index = fls64(feature) - 1;
2951 void *dest = get_xsave_addr(xsave, feature);
2952
2953 if (dest) {
2954 u32 size, offset, ecx, edx;
2955 cpuid_count(XSTATE_CPUID, index,
2956 &size, &offset, &ecx, &edx);
2957 memcpy(dest, src + offset, size);
2958 }
2959
2960 valid -= feature;
2961 }
2962 }
2963
2964 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2965 struct kvm_xsave *guest_xsave)
2966 {
2967 if (cpu_has_xsave) {
2968 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2969 fill_xsave((u8 *) guest_xsave->region, vcpu);
2970 } else {
2971 memcpy(guest_xsave->region,
2972 &vcpu->arch.guest_fpu.state.fxsave,
2973 sizeof(struct fxregs_state));
2974 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2975 XSTATE_FPSSE;
2976 }
2977 }
2978
2979 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2980 struct kvm_xsave *guest_xsave)
2981 {
2982 u64 xstate_bv =
2983 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2984
2985 if (cpu_has_xsave) {
2986 /*
2987 * Here we allow setting states that are not present in
2988 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
2989 * with old userspace.
2990 */
2991 if (xstate_bv & ~kvm_supported_xcr0())
2992 return -EINVAL;
2993 load_xsave(vcpu, (u8 *)guest_xsave->region);
2994 } else {
2995 if (xstate_bv & ~XSTATE_FPSSE)
2996 return -EINVAL;
2997 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
2998 guest_xsave->region, sizeof(struct fxregs_state));
2999 }
3000 return 0;
3001 }
3002
3003 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3004 struct kvm_xcrs *guest_xcrs)
3005 {
3006 if (!cpu_has_xsave) {
3007 guest_xcrs->nr_xcrs = 0;
3008 return;
3009 }
3010
3011 guest_xcrs->nr_xcrs = 1;
3012 guest_xcrs->flags = 0;
3013 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3014 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3015 }
3016
3017 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3018 struct kvm_xcrs *guest_xcrs)
3019 {
3020 int i, r = 0;
3021
3022 if (!cpu_has_xsave)
3023 return -EINVAL;
3024
3025 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3026 return -EINVAL;
3027
3028 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3029 /* Only support XCR0 currently */
3030 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3031 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3032 guest_xcrs->xcrs[i].value);
3033 break;
3034 }
3035 if (r)
3036 r = -EINVAL;
3037 return r;
3038 }
3039
3040 /*
3041 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3042 * stopped by the hypervisor. This function will be called from the host only.
3043 * EINVAL is returned when the host attempts to set the flag for a guest that
3044 * does not support pv clocks.
3045 */
3046 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3047 {
3048 if (!vcpu->arch.pv_time_enabled)
3049 return -EINVAL;
3050 vcpu->arch.pvclock_set_guest_stopped_request = true;
3051 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3052 return 0;
3053 }
3054
3055 long kvm_arch_vcpu_ioctl(struct file *filp,
3056 unsigned int ioctl, unsigned long arg)
3057 {
3058 struct kvm_vcpu *vcpu = filp->private_data;
3059 void __user *argp = (void __user *)arg;
3060 int r;
3061 union {
3062 struct kvm_lapic_state *lapic;
3063 struct kvm_xsave *xsave;
3064 struct kvm_xcrs *xcrs;
3065 void *buffer;
3066 } u;
3067
3068 u.buffer = NULL;
3069 switch (ioctl) {
3070 case KVM_GET_LAPIC: {
3071 r = -EINVAL;
3072 if (!vcpu->arch.apic)
3073 goto out;
3074 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3075
3076 r = -ENOMEM;
3077 if (!u.lapic)
3078 goto out;
3079 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3080 if (r)
3081 goto out;
3082 r = -EFAULT;
3083 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3084 goto out;
3085 r = 0;
3086 break;
3087 }
3088 case KVM_SET_LAPIC: {
3089 r = -EINVAL;
3090 if (!vcpu->arch.apic)
3091 goto out;
3092 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3093 if (IS_ERR(u.lapic))
3094 return PTR_ERR(u.lapic);
3095
3096 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3097 break;
3098 }
3099 case KVM_INTERRUPT: {
3100 struct kvm_interrupt irq;
3101
3102 r = -EFAULT;
3103 if (copy_from_user(&irq, argp, sizeof irq))
3104 goto out;
3105 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3106 break;
3107 }
3108 case KVM_NMI: {
3109 r = kvm_vcpu_ioctl_nmi(vcpu);
3110 break;
3111 }
3112 case KVM_SMI: {
3113 r = kvm_vcpu_ioctl_smi(vcpu);
3114 break;
3115 }
3116 case KVM_SET_CPUID: {
3117 struct kvm_cpuid __user *cpuid_arg = argp;
3118 struct kvm_cpuid cpuid;
3119
3120 r = -EFAULT;
3121 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3122 goto out;
3123 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3124 break;
3125 }
3126 case KVM_SET_CPUID2: {
3127 struct kvm_cpuid2 __user *cpuid_arg = argp;
3128 struct kvm_cpuid2 cpuid;
3129
3130 r = -EFAULT;
3131 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3132 goto out;
3133 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3134 cpuid_arg->entries);
3135 break;
3136 }
3137 case KVM_GET_CPUID2: {
3138 struct kvm_cpuid2 __user *cpuid_arg = argp;
3139 struct kvm_cpuid2 cpuid;
3140
3141 r = -EFAULT;
3142 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 goto out;
3144 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3145 cpuid_arg->entries);
3146 if (r)
3147 goto out;
3148 r = -EFAULT;
3149 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3150 goto out;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_GET_MSRS:
3155 r = msr_io(vcpu, argp, do_get_msr, 1);
3156 break;
3157 case KVM_SET_MSRS:
3158 r = msr_io(vcpu, argp, do_set_msr, 0);
3159 break;
3160 case KVM_TPR_ACCESS_REPORTING: {
3161 struct kvm_tpr_access_ctl tac;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&tac, argp, sizeof tac))
3165 goto out;
3166 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3167 if (r)
3168 goto out;
3169 r = -EFAULT;
3170 if (copy_to_user(argp, &tac, sizeof tac))
3171 goto out;
3172 r = 0;
3173 break;
3174 };
3175 case KVM_SET_VAPIC_ADDR: {
3176 struct kvm_vapic_addr va;
3177
3178 r = -EINVAL;
3179 if (!lapic_in_kernel(vcpu))
3180 goto out;
3181 r = -EFAULT;
3182 if (copy_from_user(&va, argp, sizeof va))
3183 goto out;
3184 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3185 break;
3186 }
3187 case KVM_X86_SETUP_MCE: {
3188 u64 mcg_cap;
3189
3190 r = -EFAULT;
3191 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3192 goto out;
3193 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3194 break;
3195 }
3196 case KVM_X86_SET_MCE: {
3197 struct kvm_x86_mce mce;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&mce, argp, sizeof mce))
3201 goto out;
3202 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3203 break;
3204 }
3205 case KVM_GET_VCPU_EVENTS: {
3206 struct kvm_vcpu_events events;
3207
3208 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3209
3210 r = -EFAULT;
3211 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3212 break;
3213 r = 0;
3214 break;
3215 }
3216 case KVM_SET_VCPU_EVENTS: {
3217 struct kvm_vcpu_events events;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3221 break;
3222
3223 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3224 break;
3225 }
3226 case KVM_GET_DEBUGREGS: {
3227 struct kvm_debugregs dbgregs;
3228
3229 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3230
3231 r = -EFAULT;
3232 if (copy_to_user(argp, &dbgregs,
3233 sizeof(struct kvm_debugregs)))
3234 break;
3235 r = 0;
3236 break;
3237 }
3238 case KVM_SET_DEBUGREGS: {
3239 struct kvm_debugregs dbgregs;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&dbgregs, argp,
3243 sizeof(struct kvm_debugregs)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3247 break;
3248 }
3249 case KVM_GET_XSAVE: {
3250 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3251 r = -ENOMEM;
3252 if (!u.xsave)
3253 break;
3254
3255 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3256
3257 r = -EFAULT;
3258 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3259 break;
3260 r = 0;
3261 break;
3262 }
3263 case KVM_SET_XSAVE: {
3264 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3265 if (IS_ERR(u.xsave))
3266 return PTR_ERR(u.xsave);
3267
3268 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3269 break;
3270 }
3271 case KVM_GET_XCRS: {
3272 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3273 r = -ENOMEM;
3274 if (!u.xcrs)
3275 break;
3276
3277 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3278
3279 r = -EFAULT;
3280 if (copy_to_user(argp, u.xcrs,
3281 sizeof(struct kvm_xcrs)))
3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XCRS: {
3287 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3288 if (IS_ERR(u.xcrs))
3289 return PTR_ERR(u.xcrs);
3290
3291 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3292 break;
3293 }
3294 case KVM_SET_TSC_KHZ: {
3295 u32 user_tsc_khz;
3296
3297 r = -EINVAL;
3298 user_tsc_khz = (u32)arg;
3299
3300 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3301 goto out;
3302
3303 if (user_tsc_khz == 0)
3304 user_tsc_khz = tsc_khz;
3305
3306 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3307
3308 r = 0;
3309 goto out;
3310 }
3311 case KVM_GET_TSC_KHZ: {
3312 r = vcpu->arch.virtual_tsc_khz;
3313 goto out;
3314 }
3315 case KVM_KVMCLOCK_CTRL: {
3316 r = kvm_set_guest_paused(vcpu);
3317 goto out;
3318 }
3319 default:
3320 r = -EINVAL;
3321 }
3322 out:
3323 kfree(u.buffer);
3324 return r;
3325 }
3326
3327 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3328 {
3329 return VM_FAULT_SIGBUS;
3330 }
3331
3332 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3333 {
3334 int ret;
3335
3336 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3337 return -EINVAL;
3338 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3339 return ret;
3340 }
3341
3342 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3343 u64 ident_addr)
3344 {
3345 kvm->arch.ept_identity_map_addr = ident_addr;
3346 return 0;
3347 }
3348
3349 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3350 u32 kvm_nr_mmu_pages)
3351 {
3352 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3353 return -EINVAL;
3354
3355 mutex_lock(&kvm->slots_lock);
3356
3357 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3358 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3359
3360 mutex_unlock(&kvm->slots_lock);
3361 return 0;
3362 }
3363
3364 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3365 {
3366 return kvm->arch.n_max_mmu_pages;
3367 }
3368
3369 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3370 {
3371 int r;
3372
3373 r = 0;
3374 switch (chip->chip_id) {
3375 case KVM_IRQCHIP_PIC_MASTER:
3376 memcpy(&chip->chip.pic,
3377 &pic_irqchip(kvm)->pics[0],
3378 sizeof(struct kvm_pic_state));
3379 break;
3380 case KVM_IRQCHIP_PIC_SLAVE:
3381 memcpy(&chip->chip.pic,
3382 &pic_irqchip(kvm)->pics[1],
3383 sizeof(struct kvm_pic_state));
3384 break;
3385 case KVM_IRQCHIP_IOAPIC:
3386 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3387 break;
3388 default:
3389 r = -EINVAL;
3390 break;
3391 }
3392 return r;
3393 }
3394
3395 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3396 {
3397 int r;
3398
3399 r = 0;
3400 switch (chip->chip_id) {
3401 case KVM_IRQCHIP_PIC_MASTER:
3402 spin_lock(&pic_irqchip(kvm)->lock);
3403 memcpy(&pic_irqchip(kvm)->pics[0],
3404 &chip->chip.pic,
3405 sizeof(struct kvm_pic_state));
3406 spin_unlock(&pic_irqchip(kvm)->lock);
3407 break;
3408 case KVM_IRQCHIP_PIC_SLAVE:
3409 spin_lock(&pic_irqchip(kvm)->lock);
3410 memcpy(&pic_irqchip(kvm)->pics[1],
3411 &chip->chip.pic,
3412 sizeof(struct kvm_pic_state));
3413 spin_unlock(&pic_irqchip(kvm)->lock);
3414 break;
3415 case KVM_IRQCHIP_IOAPIC:
3416 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3417 break;
3418 default:
3419 r = -EINVAL;
3420 break;
3421 }
3422 kvm_pic_update_irq(pic_irqchip(kvm));
3423 return r;
3424 }
3425
3426 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3427 {
3428 int r = 0;
3429
3430 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3431 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3432 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3433 return r;
3434 }
3435
3436 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3437 {
3438 int r = 0;
3439
3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3441 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3442 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3444 return r;
3445 }
3446
3447 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3448 {
3449 int r = 0;
3450
3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3452 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3453 sizeof(ps->channels));
3454 ps->flags = kvm->arch.vpit->pit_state.flags;
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3456 memset(&ps->reserved, 0, sizeof(ps->reserved));
3457 return r;
3458 }
3459
3460 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461 {
3462 int r = 0, start = 0;
3463 u32 prev_legacy, cur_legacy;
3464 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3465 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3466 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3467 if (!prev_legacy && cur_legacy)
3468 start = 1;
3469 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3470 sizeof(kvm->arch.vpit->pit_state.channels));
3471 kvm->arch.vpit->pit_state.flags = ps->flags;
3472 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3473 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3474 return r;
3475 }
3476
3477 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3478 struct kvm_reinject_control *control)
3479 {
3480 if (!kvm->arch.vpit)
3481 return -ENXIO;
3482 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3483 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3484 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3485 return 0;
3486 }
3487
3488 /**
3489 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3490 * @kvm: kvm instance
3491 * @log: slot id and address to which we copy the log
3492 *
3493 * Steps 1-4 below provide general overview of dirty page logging. See
3494 * kvm_get_dirty_log_protect() function description for additional details.
3495 *
3496 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3497 * always flush the TLB (step 4) even if previous step failed and the dirty
3498 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3499 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3500 * writes will be marked dirty for next log read.
3501 *
3502 * 1. Take a snapshot of the bit and clear it if needed.
3503 * 2. Write protect the corresponding page.
3504 * 3. Copy the snapshot to the userspace.
3505 * 4. Flush TLB's if needed.
3506 */
3507 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3508 {
3509 bool is_dirty = false;
3510 int r;
3511
3512 mutex_lock(&kvm->slots_lock);
3513
3514 /*
3515 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3516 */
3517 if (kvm_x86_ops->flush_log_dirty)
3518 kvm_x86_ops->flush_log_dirty(kvm);
3519
3520 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3521
3522 /*
3523 * All the TLBs can be flushed out of mmu lock, see the comments in
3524 * kvm_mmu_slot_remove_write_access().
3525 */
3526 lockdep_assert_held(&kvm->slots_lock);
3527 if (is_dirty)
3528 kvm_flush_remote_tlbs(kvm);
3529
3530 mutex_unlock(&kvm->slots_lock);
3531 return r;
3532 }
3533
3534 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3535 bool line_status)
3536 {
3537 if (!irqchip_in_kernel(kvm))
3538 return -ENXIO;
3539
3540 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3541 irq_event->irq, irq_event->level,
3542 line_status);
3543 return 0;
3544 }
3545
3546 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3547 struct kvm_enable_cap *cap)
3548 {
3549 int r;
3550
3551 if (cap->flags)
3552 return -EINVAL;
3553
3554 switch (cap->cap) {
3555 case KVM_CAP_DISABLE_QUIRKS:
3556 kvm->arch.disabled_quirks = cap->args[0];
3557 r = 0;
3558 break;
3559 case KVM_CAP_SPLIT_IRQCHIP: {
3560 mutex_lock(&kvm->lock);
3561 r = -EINVAL;
3562 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3563 goto split_irqchip_unlock;
3564 r = -EEXIST;
3565 if (irqchip_in_kernel(kvm))
3566 goto split_irqchip_unlock;
3567 if (atomic_read(&kvm->online_vcpus))
3568 goto split_irqchip_unlock;
3569 r = kvm_setup_empty_irq_routing(kvm);
3570 if (r)
3571 goto split_irqchip_unlock;
3572 /* Pairs with irqchip_in_kernel. */
3573 smp_wmb();
3574 kvm->arch.irqchip_split = true;
3575 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3576 r = 0;
3577 split_irqchip_unlock:
3578 mutex_unlock(&kvm->lock);
3579 break;
3580 }
3581 default:
3582 r = -EINVAL;
3583 break;
3584 }
3585 return r;
3586 }
3587
3588 long kvm_arch_vm_ioctl(struct file *filp,
3589 unsigned int ioctl, unsigned long arg)
3590 {
3591 struct kvm *kvm = filp->private_data;
3592 void __user *argp = (void __user *)arg;
3593 int r = -ENOTTY;
3594 /*
3595 * This union makes it completely explicit to gcc-3.x
3596 * that these two variables' stack usage should be
3597 * combined, not added together.
3598 */
3599 union {
3600 struct kvm_pit_state ps;
3601 struct kvm_pit_state2 ps2;
3602 struct kvm_pit_config pit_config;
3603 } u;
3604
3605 switch (ioctl) {
3606 case KVM_SET_TSS_ADDR:
3607 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3608 break;
3609 case KVM_SET_IDENTITY_MAP_ADDR: {
3610 u64 ident_addr;
3611
3612 r = -EFAULT;
3613 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3614 goto out;
3615 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3616 break;
3617 }
3618 case KVM_SET_NR_MMU_PAGES:
3619 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3620 break;
3621 case KVM_GET_NR_MMU_PAGES:
3622 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3623 break;
3624 case KVM_CREATE_IRQCHIP: {
3625 struct kvm_pic *vpic;
3626
3627 mutex_lock(&kvm->lock);
3628 r = -EEXIST;
3629 if (kvm->arch.vpic)
3630 goto create_irqchip_unlock;
3631 r = -EINVAL;
3632 if (atomic_read(&kvm->online_vcpus))
3633 goto create_irqchip_unlock;
3634 r = -ENOMEM;
3635 vpic = kvm_create_pic(kvm);
3636 if (vpic) {
3637 r = kvm_ioapic_init(kvm);
3638 if (r) {
3639 mutex_lock(&kvm->slots_lock);
3640 kvm_destroy_pic(vpic);
3641 mutex_unlock(&kvm->slots_lock);
3642 goto create_irqchip_unlock;
3643 }
3644 } else
3645 goto create_irqchip_unlock;
3646 r = kvm_setup_default_irq_routing(kvm);
3647 if (r) {
3648 mutex_lock(&kvm->slots_lock);
3649 mutex_lock(&kvm->irq_lock);
3650 kvm_ioapic_destroy(kvm);
3651 kvm_destroy_pic(vpic);
3652 mutex_unlock(&kvm->irq_lock);
3653 mutex_unlock(&kvm->slots_lock);
3654 goto create_irqchip_unlock;
3655 }
3656 /* Write kvm->irq_routing before kvm->arch.vpic. */
3657 smp_wmb();
3658 kvm->arch.vpic = vpic;
3659 create_irqchip_unlock:
3660 mutex_unlock(&kvm->lock);
3661 break;
3662 }
3663 case KVM_CREATE_PIT:
3664 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3665 goto create_pit;
3666 case KVM_CREATE_PIT2:
3667 r = -EFAULT;
3668 if (copy_from_user(&u.pit_config, argp,
3669 sizeof(struct kvm_pit_config)))
3670 goto out;
3671 create_pit:
3672 mutex_lock(&kvm->slots_lock);
3673 r = -EEXIST;
3674 if (kvm->arch.vpit)
3675 goto create_pit_unlock;
3676 r = -ENOMEM;
3677 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3678 if (kvm->arch.vpit)
3679 r = 0;
3680 create_pit_unlock:
3681 mutex_unlock(&kvm->slots_lock);
3682 break;
3683 case KVM_GET_IRQCHIP: {
3684 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3685 struct kvm_irqchip *chip;
3686
3687 chip = memdup_user(argp, sizeof(*chip));
3688 if (IS_ERR(chip)) {
3689 r = PTR_ERR(chip);
3690 goto out;
3691 }
3692
3693 r = -ENXIO;
3694 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3695 goto get_irqchip_out;
3696 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3697 if (r)
3698 goto get_irqchip_out;
3699 r = -EFAULT;
3700 if (copy_to_user(argp, chip, sizeof *chip))
3701 goto get_irqchip_out;
3702 r = 0;
3703 get_irqchip_out:
3704 kfree(chip);
3705 break;
3706 }
3707 case KVM_SET_IRQCHIP: {
3708 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3709 struct kvm_irqchip *chip;
3710
3711 chip = memdup_user(argp, sizeof(*chip));
3712 if (IS_ERR(chip)) {
3713 r = PTR_ERR(chip);
3714 goto out;
3715 }
3716
3717 r = -ENXIO;
3718 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3719 goto set_irqchip_out;
3720 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3721 if (r)
3722 goto set_irqchip_out;
3723 r = 0;
3724 set_irqchip_out:
3725 kfree(chip);
3726 break;
3727 }
3728 case KVM_GET_PIT: {
3729 r = -EFAULT;
3730 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3731 goto out;
3732 r = -ENXIO;
3733 if (!kvm->arch.vpit)
3734 goto out;
3735 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3736 if (r)
3737 goto out;
3738 r = -EFAULT;
3739 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3740 goto out;
3741 r = 0;
3742 break;
3743 }
3744 case KVM_SET_PIT: {
3745 r = -EFAULT;
3746 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3747 goto out;
3748 r = -ENXIO;
3749 if (!kvm->arch.vpit)
3750 goto out;
3751 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3752 break;
3753 }
3754 case KVM_GET_PIT2: {
3755 r = -ENXIO;
3756 if (!kvm->arch.vpit)
3757 goto out;
3758 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3759 if (r)
3760 goto out;
3761 r = -EFAULT;
3762 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3763 goto out;
3764 r = 0;
3765 break;
3766 }
3767 case KVM_SET_PIT2: {
3768 r = -EFAULT;
3769 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3770 goto out;
3771 r = -ENXIO;
3772 if (!kvm->arch.vpit)
3773 goto out;
3774 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3775 break;
3776 }
3777 case KVM_REINJECT_CONTROL: {
3778 struct kvm_reinject_control control;
3779 r = -EFAULT;
3780 if (copy_from_user(&control, argp, sizeof(control)))
3781 goto out;
3782 r = kvm_vm_ioctl_reinject(kvm, &control);
3783 break;
3784 }
3785 case KVM_SET_BOOT_CPU_ID:
3786 r = 0;
3787 mutex_lock(&kvm->lock);
3788 if (atomic_read(&kvm->online_vcpus) != 0)
3789 r = -EBUSY;
3790 else
3791 kvm->arch.bsp_vcpu_id = arg;
3792 mutex_unlock(&kvm->lock);
3793 break;
3794 case KVM_XEN_HVM_CONFIG: {
3795 r = -EFAULT;
3796 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3797 sizeof(struct kvm_xen_hvm_config)))
3798 goto out;
3799 r = -EINVAL;
3800 if (kvm->arch.xen_hvm_config.flags)
3801 goto out;
3802 r = 0;
3803 break;
3804 }
3805 case KVM_SET_CLOCK: {
3806 struct kvm_clock_data user_ns;
3807 u64 now_ns;
3808 s64 delta;
3809
3810 r = -EFAULT;
3811 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3812 goto out;
3813
3814 r = -EINVAL;
3815 if (user_ns.flags)
3816 goto out;
3817
3818 r = 0;
3819 local_irq_disable();
3820 now_ns = get_kernel_ns();
3821 delta = user_ns.clock - now_ns;
3822 local_irq_enable();
3823 kvm->arch.kvmclock_offset = delta;
3824 kvm_gen_update_masterclock(kvm);
3825 break;
3826 }
3827 case KVM_GET_CLOCK: {
3828 struct kvm_clock_data user_ns;
3829 u64 now_ns;
3830
3831 local_irq_disable();
3832 now_ns = get_kernel_ns();
3833 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3834 local_irq_enable();
3835 user_ns.flags = 0;
3836 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3837
3838 r = -EFAULT;
3839 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3840 goto out;
3841 r = 0;
3842 break;
3843 }
3844 case KVM_ENABLE_CAP: {
3845 struct kvm_enable_cap cap;
3846
3847 r = -EFAULT;
3848 if (copy_from_user(&cap, argp, sizeof(cap)))
3849 goto out;
3850 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3851 break;
3852 }
3853 default:
3854 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3855 }
3856 out:
3857 return r;
3858 }
3859
3860 static void kvm_init_msr_list(void)
3861 {
3862 u32 dummy[2];
3863 unsigned i, j;
3864
3865 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3866 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3867 continue;
3868
3869 /*
3870 * Even MSRs that are valid in the host may not be exposed
3871 * to the guests in some cases. We could work around this
3872 * in VMX with the generic MSR save/load machinery, but it
3873 * is not really worthwhile since it will really only
3874 * happen with nested virtualization.
3875 */
3876 switch (msrs_to_save[i]) {
3877 case MSR_IA32_BNDCFGS:
3878 if (!kvm_x86_ops->mpx_supported())
3879 continue;
3880 break;
3881 default:
3882 break;
3883 }
3884
3885 if (j < i)
3886 msrs_to_save[j] = msrs_to_save[i];
3887 j++;
3888 }
3889 num_msrs_to_save = j;
3890
3891 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3892 switch (emulated_msrs[i]) {
3893 case MSR_IA32_SMBASE:
3894 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3895 continue;
3896 break;
3897 default:
3898 break;
3899 }
3900
3901 if (j < i)
3902 emulated_msrs[j] = emulated_msrs[i];
3903 j++;
3904 }
3905 num_emulated_msrs = j;
3906 }
3907
3908 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3909 const void *v)
3910 {
3911 int handled = 0;
3912 int n;
3913
3914 do {
3915 n = min(len, 8);
3916 if (!(vcpu->arch.apic &&
3917 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3918 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3919 break;
3920 handled += n;
3921 addr += n;
3922 len -= n;
3923 v += n;
3924 } while (len);
3925
3926 return handled;
3927 }
3928
3929 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3930 {
3931 int handled = 0;
3932 int n;
3933
3934 do {
3935 n = min(len, 8);
3936 if (!(vcpu->arch.apic &&
3937 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3938 addr, n, v))
3939 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3940 break;
3941 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3942 handled += n;
3943 addr += n;
3944 len -= n;
3945 v += n;
3946 } while (len);
3947
3948 return handled;
3949 }
3950
3951 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3952 struct kvm_segment *var, int seg)
3953 {
3954 kvm_x86_ops->set_segment(vcpu, var, seg);
3955 }
3956
3957 void kvm_get_segment(struct kvm_vcpu *vcpu,
3958 struct kvm_segment *var, int seg)
3959 {
3960 kvm_x86_ops->get_segment(vcpu, var, seg);
3961 }
3962
3963 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3964 struct x86_exception *exception)
3965 {
3966 gpa_t t_gpa;
3967
3968 BUG_ON(!mmu_is_nested(vcpu));
3969
3970 /* NPT walks are always user-walks */
3971 access |= PFERR_USER_MASK;
3972 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3973
3974 return t_gpa;
3975 }
3976
3977 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3978 struct x86_exception *exception)
3979 {
3980 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3981 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3982 }
3983
3984 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3985 struct x86_exception *exception)
3986 {
3987 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3988 access |= PFERR_FETCH_MASK;
3989 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3990 }
3991
3992 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3993 struct x86_exception *exception)
3994 {
3995 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3996 access |= PFERR_WRITE_MASK;
3997 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3998 }
3999
4000 /* uses this to access any guest's mapped memory without checking CPL */
4001 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4002 struct x86_exception *exception)
4003 {
4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4005 }
4006
4007 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4008 struct kvm_vcpu *vcpu, u32 access,
4009 struct x86_exception *exception)
4010 {
4011 void *data = val;
4012 int r = X86EMUL_CONTINUE;
4013
4014 while (bytes) {
4015 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4016 exception);
4017 unsigned offset = addr & (PAGE_SIZE-1);
4018 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4019 int ret;
4020
4021 if (gpa == UNMAPPED_GVA)
4022 return X86EMUL_PROPAGATE_FAULT;
4023 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4024 offset, toread);
4025 if (ret < 0) {
4026 r = X86EMUL_IO_NEEDED;
4027 goto out;
4028 }
4029
4030 bytes -= toread;
4031 data += toread;
4032 addr += toread;
4033 }
4034 out:
4035 return r;
4036 }
4037
4038 /* used for instruction fetching */
4039 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4040 gva_t addr, void *val, unsigned int bytes,
4041 struct x86_exception *exception)
4042 {
4043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4044 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4045 unsigned offset;
4046 int ret;
4047
4048 /* Inline kvm_read_guest_virt_helper for speed. */
4049 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4050 exception);
4051 if (unlikely(gpa == UNMAPPED_GVA))
4052 return X86EMUL_PROPAGATE_FAULT;
4053
4054 offset = addr & (PAGE_SIZE-1);
4055 if (WARN_ON(offset + bytes > PAGE_SIZE))
4056 bytes = (unsigned)PAGE_SIZE - offset;
4057 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4058 offset, bytes);
4059 if (unlikely(ret < 0))
4060 return X86EMUL_IO_NEEDED;
4061
4062 return X86EMUL_CONTINUE;
4063 }
4064
4065 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4066 gva_t addr, void *val, unsigned int bytes,
4067 struct x86_exception *exception)
4068 {
4069 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4070 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4071
4072 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4073 exception);
4074 }
4075 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4076
4077 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4078 gva_t addr, void *val, unsigned int bytes,
4079 struct x86_exception *exception)
4080 {
4081 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4082 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4083 }
4084
4085 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4086 gva_t addr, void *val,
4087 unsigned int bytes,
4088 struct x86_exception *exception)
4089 {
4090 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4091 void *data = val;
4092 int r = X86EMUL_CONTINUE;
4093
4094 while (bytes) {
4095 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4096 PFERR_WRITE_MASK,
4097 exception);
4098 unsigned offset = addr & (PAGE_SIZE-1);
4099 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4100 int ret;
4101
4102 if (gpa == UNMAPPED_GVA)
4103 return X86EMUL_PROPAGATE_FAULT;
4104 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4105 if (ret < 0) {
4106 r = X86EMUL_IO_NEEDED;
4107 goto out;
4108 }
4109
4110 bytes -= towrite;
4111 data += towrite;
4112 addr += towrite;
4113 }
4114 out:
4115 return r;
4116 }
4117 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4118
4119 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4120 gpa_t *gpa, struct x86_exception *exception,
4121 bool write)
4122 {
4123 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4124 | (write ? PFERR_WRITE_MASK : 0);
4125
4126 if (vcpu_match_mmio_gva(vcpu, gva)
4127 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4128 vcpu->arch.access, access)) {
4129 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4130 (gva & (PAGE_SIZE - 1));
4131 trace_vcpu_match_mmio(gva, *gpa, write, false);
4132 return 1;
4133 }
4134
4135 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4136
4137 if (*gpa == UNMAPPED_GVA)
4138 return -1;
4139
4140 /* For APIC access vmexit */
4141 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4142 return 1;
4143
4144 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4145 trace_vcpu_match_mmio(gva, *gpa, write, true);
4146 return 1;
4147 }
4148
4149 return 0;
4150 }
4151
4152 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4153 const void *val, int bytes)
4154 {
4155 int ret;
4156
4157 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4158 if (ret < 0)
4159 return 0;
4160 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4161 return 1;
4162 }
4163
4164 struct read_write_emulator_ops {
4165 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4166 int bytes);
4167 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4168 void *val, int bytes);
4169 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4170 int bytes, void *val);
4171 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4172 void *val, int bytes);
4173 bool write;
4174 };
4175
4176 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4177 {
4178 if (vcpu->mmio_read_completed) {
4179 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4180 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4181 vcpu->mmio_read_completed = 0;
4182 return 1;
4183 }
4184
4185 return 0;
4186 }
4187
4188 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4189 void *val, int bytes)
4190 {
4191 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4192 }
4193
4194 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4195 void *val, int bytes)
4196 {
4197 return emulator_write_phys(vcpu, gpa, val, bytes);
4198 }
4199
4200 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4201 {
4202 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4203 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4204 }
4205
4206 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes)
4208 {
4209 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4210 return X86EMUL_IO_NEEDED;
4211 }
4212
4213 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4214 void *val, int bytes)
4215 {
4216 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4217
4218 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4219 return X86EMUL_CONTINUE;
4220 }
4221
4222 static const struct read_write_emulator_ops read_emultor = {
4223 .read_write_prepare = read_prepare,
4224 .read_write_emulate = read_emulate,
4225 .read_write_mmio = vcpu_mmio_read,
4226 .read_write_exit_mmio = read_exit_mmio,
4227 };
4228
4229 static const struct read_write_emulator_ops write_emultor = {
4230 .read_write_emulate = write_emulate,
4231 .read_write_mmio = write_mmio,
4232 .read_write_exit_mmio = write_exit_mmio,
4233 .write = true,
4234 };
4235
4236 static int emulator_read_write_onepage(unsigned long addr, void *val,
4237 unsigned int bytes,
4238 struct x86_exception *exception,
4239 struct kvm_vcpu *vcpu,
4240 const struct read_write_emulator_ops *ops)
4241 {
4242 gpa_t gpa;
4243 int handled, ret;
4244 bool write = ops->write;
4245 struct kvm_mmio_fragment *frag;
4246
4247 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4248
4249 if (ret < 0)
4250 return X86EMUL_PROPAGATE_FAULT;
4251
4252 /* For APIC access vmexit */
4253 if (ret)
4254 goto mmio;
4255
4256 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4257 return X86EMUL_CONTINUE;
4258
4259 mmio:
4260 /*
4261 * Is this MMIO handled locally?
4262 */
4263 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4264 if (handled == bytes)
4265 return X86EMUL_CONTINUE;
4266
4267 gpa += handled;
4268 bytes -= handled;
4269 val += handled;
4270
4271 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4272 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4273 frag->gpa = gpa;
4274 frag->data = val;
4275 frag->len = bytes;
4276 return X86EMUL_CONTINUE;
4277 }
4278
4279 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4280 unsigned long addr,
4281 void *val, unsigned int bytes,
4282 struct x86_exception *exception,
4283 const struct read_write_emulator_ops *ops)
4284 {
4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4286 gpa_t gpa;
4287 int rc;
4288
4289 if (ops->read_write_prepare &&
4290 ops->read_write_prepare(vcpu, val, bytes))
4291 return X86EMUL_CONTINUE;
4292
4293 vcpu->mmio_nr_fragments = 0;
4294
4295 /* Crossing a page boundary? */
4296 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4297 int now;
4298
4299 now = -addr & ~PAGE_MASK;
4300 rc = emulator_read_write_onepage(addr, val, now, exception,
4301 vcpu, ops);
4302
4303 if (rc != X86EMUL_CONTINUE)
4304 return rc;
4305 addr += now;
4306 if (ctxt->mode != X86EMUL_MODE_PROT64)
4307 addr = (u32)addr;
4308 val += now;
4309 bytes -= now;
4310 }
4311
4312 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4313 vcpu, ops);
4314 if (rc != X86EMUL_CONTINUE)
4315 return rc;
4316
4317 if (!vcpu->mmio_nr_fragments)
4318 return rc;
4319
4320 gpa = vcpu->mmio_fragments[0].gpa;
4321
4322 vcpu->mmio_needed = 1;
4323 vcpu->mmio_cur_fragment = 0;
4324
4325 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4326 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4327 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4328 vcpu->run->mmio.phys_addr = gpa;
4329
4330 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4331 }
4332
4333 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4334 unsigned long addr,
4335 void *val,
4336 unsigned int bytes,
4337 struct x86_exception *exception)
4338 {
4339 return emulator_read_write(ctxt, addr, val, bytes,
4340 exception, &read_emultor);
4341 }
4342
4343 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4344 unsigned long addr,
4345 const void *val,
4346 unsigned int bytes,
4347 struct x86_exception *exception)
4348 {
4349 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4350 exception, &write_emultor);
4351 }
4352
4353 #define CMPXCHG_TYPE(t, ptr, old, new) \
4354 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4355
4356 #ifdef CONFIG_X86_64
4357 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4358 #else
4359 # define CMPXCHG64(ptr, old, new) \
4360 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4361 #endif
4362
4363 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4364 unsigned long addr,
4365 const void *old,
4366 const void *new,
4367 unsigned int bytes,
4368 struct x86_exception *exception)
4369 {
4370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4371 gpa_t gpa;
4372 struct page *page;
4373 char *kaddr;
4374 bool exchanged;
4375
4376 /* guests cmpxchg8b have to be emulated atomically */
4377 if (bytes > 8 || (bytes & (bytes - 1)))
4378 goto emul_write;
4379
4380 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4381
4382 if (gpa == UNMAPPED_GVA ||
4383 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4384 goto emul_write;
4385
4386 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4387 goto emul_write;
4388
4389 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4390 if (is_error_page(page))
4391 goto emul_write;
4392
4393 kaddr = kmap_atomic(page);
4394 kaddr += offset_in_page(gpa);
4395 switch (bytes) {
4396 case 1:
4397 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4398 break;
4399 case 2:
4400 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4401 break;
4402 case 4:
4403 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4404 break;
4405 case 8:
4406 exchanged = CMPXCHG64(kaddr, old, new);
4407 break;
4408 default:
4409 BUG();
4410 }
4411 kunmap_atomic(kaddr);
4412 kvm_release_page_dirty(page);
4413
4414 if (!exchanged)
4415 return X86EMUL_CMPXCHG_FAILED;
4416
4417 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4418 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4419
4420 return X86EMUL_CONTINUE;
4421
4422 emul_write:
4423 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4424
4425 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4426 }
4427
4428 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4429 {
4430 /* TODO: String I/O for in kernel device */
4431 int r;
4432
4433 if (vcpu->arch.pio.in)
4434 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4435 vcpu->arch.pio.size, pd);
4436 else
4437 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4438 vcpu->arch.pio.port, vcpu->arch.pio.size,
4439 pd);
4440 return r;
4441 }
4442
4443 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4444 unsigned short port, void *val,
4445 unsigned int count, bool in)
4446 {
4447 vcpu->arch.pio.port = port;
4448 vcpu->arch.pio.in = in;
4449 vcpu->arch.pio.count = count;
4450 vcpu->arch.pio.size = size;
4451
4452 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4453 vcpu->arch.pio.count = 0;
4454 return 1;
4455 }
4456
4457 vcpu->run->exit_reason = KVM_EXIT_IO;
4458 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4459 vcpu->run->io.size = size;
4460 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4461 vcpu->run->io.count = count;
4462 vcpu->run->io.port = port;
4463
4464 return 0;
4465 }
4466
4467 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4468 int size, unsigned short port, void *val,
4469 unsigned int count)
4470 {
4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4472 int ret;
4473
4474 if (vcpu->arch.pio.count)
4475 goto data_avail;
4476
4477 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4478 if (ret) {
4479 data_avail:
4480 memcpy(val, vcpu->arch.pio_data, size * count);
4481 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4482 vcpu->arch.pio.count = 0;
4483 return 1;
4484 }
4485
4486 return 0;
4487 }
4488
4489 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4490 int size, unsigned short port,
4491 const void *val, unsigned int count)
4492 {
4493 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4494
4495 memcpy(vcpu->arch.pio_data, val, size * count);
4496 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4497 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4498 }
4499
4500 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4501 {
4502 return kvm_x86_ops->get_segment_base(vcpu, seg);
4503 }
4504
4505 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4506 {
4507 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4508 }
4509
4510 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4511 {
4512 if (!need_emulate_wbinvd(vcpu))
4513 return X86EMUL_CONTINUE;
4514
4515 if (kvm_x86_ops->has_wbinvd_exit()) {
4516 int cpu = get_cpu();
4517
4518 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4519 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4520 wbinvd_ipi, NULL, 1);
4521 put_cpu();
4522 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4523 } else
4524 wbinvd();
4525 return X86EMUL_CONTINUE;
4526 }
4527
4528 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4529 {
4530 kvm_x86_ops->skip_emulated_instruction(vcpu);
4531 return kvm_emulate_wbinvd_noskip(vcpu);
4532 }
4533 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4534
4535
4536
4537 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4538 {
4539 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4540 }
4541
4542 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4543 unsigned long *dest)
4544 {
4545 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4546 }
4547
4548 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4549 unsigned long value)
4550 {
4551
4552 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4553 }
4554
4555 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4556 {
4557 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4558 }
4559
4560 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4561 {
4562 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4563 unsigned long value;
4564
4565 switch (cr) {
4566 case 0:
4567 value = kvm_read_cr0(vcpu);
4568 break;
4569 case 2:
4570 value = vcpu->arch.cr2;
4571 break;
4572 case 3:
4573 value = kvm_read_cr3(vcpu);
4574 break;
4575 case 4:
4576 value = kvm_read_cr4(vcpu);
4577 break;
4578 case 8:
4579 value = kvm_get_cr8(vcpu);
4580 break;
4581 default:
4582 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4583 return 0;
4584 }
4585
4586 return value;
4587 }
4588
4589 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4590 {
4591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4592 int res = 0;
4593
4594 switch (cr) {
4595 case 0:
4596 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4597 break;
4598 case 2:
4599 vcpu->arch.cr2 = val;
4600 break;
4601 case 3:
4602 res = kvm_set_cr3(vcpu, val);
4603 break;
4604 case 4:
4605 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4606 break;
4607 case 8:
4608 res = kvm_set_cr8(vcpu, val);
4609 break;
4610 default:
4611 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4612 res = -1;
4613 }
4614
4615 return res;
4616 }
4617
4618 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4619 {
4620 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4621 }
4622
4623 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4624 {
4625 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4626 }
4627
4628 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4629 {
4630 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4631 }
4632
4633 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4634 {
4635 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4636 }
4637
4638 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4639 {
4640 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4641 }
4642
4643 static unsigned long emulator_get_cached_segment_base(
4644 struct x86_emulate_ctxt *ctxt, int seg)
4645 {
4646 return get_segment_base(emul_to_vcpu(ctxt), seg);
4647 }
4648
4649 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4650 struct desc_struct *desc, u32 *base3,
4651 int seg)
4652 {
4653 struct kvm_segment var;
4654
4655 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4656 *selector = var.selector;
4657
4658 if (var.unusable) {
4659 memset(desc, 0, sizeof(*desc));
4660 return false;
4661 }
4662
4663 if (var.g)
4664 var.limit >>= 12;
4665 set_desc_limit(desc, var.limit);
4666 set_desc_base(desc, (unsigned long)var.base);
4667 #ifdef CONFIG_X86_64
4668 if (base3)
4669 *base3 = var.base >> 32;
4670 #endif
4671 desc->type = var.type;
4672 desc->s = var.s;
4673 desc->dpl = var.dpl;
4674 desc->p = var.present;
4675 desc->avl = var.avl;
4676 desc->l = var.l;
4677 desc->d = var.db;
4678 desc->g = var.g;
4679
4680 return true;
4681 }
4682
4683 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4684 struct desc_struct *desc, u32 base3,
4685 int seg)
4686 {
4687 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4688 struct kvm_segment var;
4689
4690 var.selector = selector;
4691 var.base = get_desc_base(desc);
4692 #ifdef CONFIG_X86_64
4693 var.base |= ((u64)base3) << 32;
4694 #endif
4695 var.limit = get_desc_limit(desc);
4696 if (desc->g)
4697 var.limit = (var.limit << 12) | 0xfff;
4698 var.type = desc->type;
4699 var.dpl = desc->dpl;
4700 var.db = desc->d;
4701 var.s = desc->s;
4702 var.l = desc->l;
4703 var.g = desc->g;
4704 var.avl = desc->avl;
4705 var.present = desc->p;
4706 var.unusable = !var.present;
4707 var.padding = 0;
4708
4709 kvm_set_segment(vcpu, &var, seg);
4710 return;
4711 }
4712
4713 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4714 u32 msr_index, u64 *pdata)
4715 {
4716 struct msr_data msr;
4717 int r;
4718
4719 msr.index = msr_index;
4720 msr.host_initiated = false;
4721 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4722 if (r)
4723 return r;
4724
4725 *pdata = msr.data;
4726 return 0;
4727 }
4728
4729 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4730 u32 msr_index, u64 data)
4731 {
4732 struct msr_data msr;
4733
4734 msr.data = data;
4735 msr.index = msr_index;
4736 msr.host_initiated = false;
4737 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4738 }
4739
4740 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4741 {
4742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4743
4744 return vcpu->arch.smbase;
4745 }
4746
4747 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4748 {
4749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4750
4751 vcpu->arch.smbase = smbase;
4752 }
4753
4754 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4755 u32 pmc)
4756 {
4757 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4758 }
4759
4760 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4761 u32 pmc, u64 *pdata)
4762 {
4763 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4764 }
4765
4766 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4767 {
4768 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4769 }
4770
4771 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4772 {
4773 preempt_disable();
4774 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4775 /*
4776 * CR0.TS may reference the host fpu state, not the guest fpu state,
4777 * so it may be clear at this point.
4778 */
4779 clts();
4780 }
4781
4782 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4783 {
4784 preempt_enable();
4785 }
4786
4787 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4788 struct x86_instruction_info *info,
4789 enum x86_intercept_stage stage)
4790 {
4791 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4792 }
4793
4794 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4795 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4796 {
4797 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4798 }
4799
4800 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4801 {
4802 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4803 }
4804
4805 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4806 {
4807 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4808 }
4809
4810 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4811 {
4812 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4813 }
4814
4815 static const struct x86_emulate_ops emulate_ops = {
4816 .read_gpr = emulator_read_gpr,
4817 .write_gpr = emulator_write_gpr,
4818 .read_std = kvm_read_guest_virt_system,
4819 .write_std = kvm_write_guest_virt_system,
4820 .fetch = kvm_fetch_guest_virt,
4821 .read_emulated = emulator_read_emulated,
4822 .write_emulated = emulator_write_emulated,
4823 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4824 .invlpg = emulator_invlpg,
4825 .pio_in_emulated = emulator_pio_in_emulated,
4826 .pio_out_emulated = emulator_pio_out_emulated,
4827 .get_segment = emulator_get_segment,
4828 .set_segment = emulator_set_segment,
4829 .get_cached_segment_base = emulator_get_cached_segment_base,
4830 .get_gdt = emulator_get_gdt,
4831 .get_idt = emulator_get_idt,
4832 .set_gdt = emulator_set_gdt,
4833 .set_idt = emulator_set_idt,
4834 .get_cr = emulator_get_cr,
4835 .set_cr = emulator_set_cr,
4836 .cpl = emulator_get_cpl,
4837 .get_dr = emulator_get_dr,
4838 .set_dr = emulator_set_dr,
4839 .get_smbase = emulator_get_smbase,
4840 .set_smbase = emulator_set_smbase,
4841 .set_msr = emulator_set_msr,
4842 .get_msr = emulator_get_msr,
4843 .check_pmc = emulator_check_pmc,
4844 .read_pmc = emulator_read_pmc,
4845 .halt = emulator_halt,
4846 .wbinvd = emulator_wbinvd,
4847 .fix_hypercall = emulator_fix_hypercall,
4848 .get_fpu = emulator_get_fpu,
4849 .put_fpu = emulator_put_fpu,
4850 .intercept = emulator_intercept,
4851 .get_cpuid = emulator_get_cpuid,
4852 .set_nmi_mask = emulator_set_nmi_mask,
4853 };
4854
4855 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4856 {
4857 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4858 /*
4859 * an sti; sti; sequence only disable interrupts for the first
4860 * instruction. So, if the last instruction, be it emulated or
4861 * not, left the system with the INT_STI flag enabled, it
4862 * means that the last instruction is an sti. We should not
4863 * leave the flag on in this case. The same goes for mov ss
4864 */
4865 if (int_shadow & mask)
4866 mask = 0;
4867 if (unlikely(int_shadow || mask)) {
4868 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4869 if (!mask)
4870 kvm_make_request(KVM_REQ_EVENT, vcpu);
4871 }
4872 }
4873
4874 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4875 {
4876 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4877 if (ctxt->exception.vector == PF_VECTOR)
4878 return kvm_propagate_fault(vcpu, &ctxt->exception);
4879
4880 if (ctxt->exception.error_code_valid)
4881 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4882 ctxt->exception.error_code);
4883 else
4884 kvm_queue_exception(vcpu, ctxt->exception.vector);
4885 return false;
4886 }
4887
4888 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4889 {
4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4891 int cs_db, cs_l;
4892
4893 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4894
4895 ctxt->eflags = kvm_get_rflags(vcpu);
4896 ctxt->eip = kvm_rip_read(vcpu);
4897 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4898 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4899 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4900 cs_db ? X86EMUL_MODE_PROT32 :
4901 X86EMUL_MODE_PROT16;
4902 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4903 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4904 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4905 ctxt->emul_flags = vcpu->arch.hflags;
4906
4907 init_decode_cache(ctxt);
4908 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4909 }
4910
4911 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4912 {
4913 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4914 int ret;
4915
4916 init_emulate_ctxt(vcpu);
4917
4918 ctxt->op_bytes = 2;
4919 ctxt->ad_bytes = 2;
4920 ctxt->_eip = ctxt->eip + inc_eip;
4921 ret = emulate_int_real(ctxt, irq);
4922
4923 if (ret != X86EMUL_CONTINUE)
4924 return EMULATE_FAIL;
4925
4926 ctxt->eip = ctxt->_eip;
4927 kvm_rip_write(vcpu, ctxt->eip);
4928 kvm_set_rflags(vcpu, ctxt->eflags);
4929
4930 if (irq == NMI_VECTOR)
4931 vcpu->arch.nmi_pending = 0;
4932 else
4933 vcpu->arch.interrupt.pending = false;
4934
4935 return EMULATE_DONE;
4936 }
4937 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4938
4939 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4940 {
4941 int r = EMULATE_DONE;
4942
4943 ++vcpu->stat.insn_emulation_fail;
4944 trace_kvm_emulate_insn_failed(vcpu);
4945 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4946 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4947 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4948 vcpu->run->internal.ndata = 0;
4949 r = EMULATE_FAIL;
4950 }
4951 kvm_queue_exception(vcpu, UD_VECTOR);
4952
4953 return r;
4954 }
4955
4956 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4957 bool write_fault_to_shadow_pgtable,
4958 int emulation_type)
4959 {
4960 gpa_t gpa = cr2;
4961 pfn_t pfn;
4962
4963 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4964 return false;
4965
4966 if (!vcpu->arch.mmu.direct_map) {
4967 /*
4968 * Write permission should be allowed since only
4969 * write access need to be emulated.
4970 */
4971 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4972
4973 /*
4974 * If the mapping is invalid in guest, let cpu retry
4975 * it to generate fault.
4976 */
4977 if (gpa == UNMAPPED_GVA)
4978 return true;
4979 }
4980
4981 /*
4982 * Do not retry the unhandleable instruction if it faults on the
4983 * readonly host memory, otherwise it will goto a infinite loop:
4984 * retry instruction -> write #PF -> emulation fail -> retry
4985 * instruction -> ...
4986 */
4987 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4988
4989 /*
4990 * If the instruction failed on the error pfn, it can not be fixed,
4991 * report the error to userspace.
4992 */
4993 if (is_error_noslot_pfn(pfn))
4994 return false;
4995
4996 kvm_release_pfn_clean(pfn);
4997
4998 /* The instructions are well-emulated on direct mmu. */
4999 if (vcpu->arch.mmu.direct_map) {
5000 unsigned int indirect_shadow_pages;
5001
5002 spin_lock(&vcpu->kvm->mmu_lock);
5003 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5004 spin_unlock(&vcpu->kvm->mmu_lock);
5005
5006 if (indirect_shadow_pages)
5007 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5008
5009 return true;
5010 }
5011
5012 /*
5013 * if emulation was due to access to shadowed page table
5014 * and it failed try to unshadow page and re-enter the
5015 * guest to let CPU execute the instruction.
5016 */
5017 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5018
5019 /*
5020 * If the access faults on its page table, it can not
5021 * be fixed by unprotecting shadow page and it should
5022 * be reported to userspace.
5023 */
5024 return !write_fault_to_shadow_pgtable;
5025 }
5026
5027 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5028 unsigned long cr2, int emulation_type)
5029 {
5030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5031 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5032
5033 last_retry_eip = vcpu->arch.last_retry_eip;
5034 last_retry_addr = vcpu->arch.last_retry_addr;
5035
5036 /*
5037 * If the emulation is caused by #PF and it is non-page_table
5038 * writing instruction, it means the VM-EXIT is caused by shadow
5039 * page protected, we can zap the shadow page and retry this
5040 * instruction directly.
5041 *
5042 * Note: if the guest uses a non-page-table modifying instruction
5043 * on the PDE that points to the instruction, then we will unmap
5044 * the instruction and go to an infinite loop. So, we cache the
5045 * last retried eip and the last fault address, if we meet the eip
5046 * and the address again, we can break out of the potential infinite
5047 * loop.
5048 */
5049 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5050
5051 if (!(emulation_type & EMULTYPE_RETRY))
5052 return false;
5053
5054 if (x86_page_table_writing_insn(ctxt))
5055 return false;
5056
5057 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5058 return false;
5059
5060 vcpu->arch.last_retry_eip = ctxt->eip;
5061 vcpu->arch.last_retry_addr = cr2;
5062
5063 if (!vcpu->arch.mmu.direct_map)
5064 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5065
5066 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5067
5068 return true;
5069 }
5070
5071 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5072 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5073
5074 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5075 {
5076 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5077 /* This is a good place to trace that we are exiting SMM. */
5078 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5079
5080 if (unlikely(vcpu->arch.smi_pending)) {
5081 kvm_make_request(KVM_REQ_SMI, vcpu);
5082 vcpu->arch.smi_pending = 0;
5083 } else {
5084 /* Process a latched INIT, if any. */
5085 kvm_make_request(KVM_REQ_EVENT, vcpu);
5086 }
5087 }
5088
5089 kvm_mmu_reset_context(vcpu);
5090 }
5091
5092 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5093 {
5094 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5095
5096 vcpu->arch.hflags = emul_flags;
5097
5098 if (changed & HF_SMM_MASK)
5099 kvm_smm_changed(vcpu);
5100 }
5101
5102 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5103 unsigned long *db)
5104 {
5105 u32 dr6 = 0;
5106 int i;
5107 u32 enable, rwlen;
5108
5109 enable = dr7;
5110 rwlen = dr7 >> 16;
5111 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5112 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5113 dr6 |= (1 << i);
5114 return dr6;
5115 }
5116
5117 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5118 {
5119 struct kvm_run *kvm_run = vcpu->run;
5120
5121 /*
5122 * rflags is the old, "raw" value of the flags. The new value has
5123 * not been saved yet.
5124 *
5125 * This is correct even for TF set by the guest, because "the
5126 * processor will not generate this exception after the instruction
5127 * that sets the TF flag".
5128 */
5129 if (unlikely(rflags & X86_EFLAGS_TF)) {
5130 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5131 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5132 DR6_RTM;
5133 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5134 kvm_run->debug.arch.exception = DB_VECTOR;
5135 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5136 *r = EMULATE_USER_EXIT;
5137 } else {
5138 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5139 /*
5140 * "Certain debug exceptions may clear bit 0-3. The
5141 * remaining contents of the DR6 register are never
5142 * cleared by the processor".
5143 */
5144 vcpu->arch.dr6 &= ~15;
5145 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5146 kvm_queue_exception(vcpu, DB_VECTOR);
5147 }
5148 }
5149 }
5150
5151 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5152 {
5153 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5154 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5155 struct kvm_run *kvm_run = vcpu->run;
5156 unsigned long eip = kvm_get_linear_rip(vcpu);
5157 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5158 vcpu->arch.guest_debug_dr7,
5159 vcpu->arch.eff_db);
5160
5161 if (dr6 != 0) {
5162 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5163 kvm_run->debug.arch.pc = eip;
5164 kvm_run->debug.arch.exception = DB_VECTOR;
5165 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5166 *r = EMULATE_USER_EXIT;
5167 return true;
5168 }
5169 }
5170
5171 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5172 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5173 unsigned long eip = kvm_get_linear_rip(vcpu);
5174 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5175 vcpu->arch.dr7,
5176 vcpu->arch.db);
5177
5178 if (dr6 != 0) {
5179 vcpu->arch.dr6 &= ~15;
5180 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5181 kvm_queue_exception(vcpu, DB_VECTOR);
5182 *r = EMULATE_DONE;
5183 return true;
5184 }
5185 }
5186
5187 return false;
5188 }
5189
5190 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5191 unsigned long cr2,
5192 int emulation_type,
5193 void *insn,
5194 int insn_len)
5195 {
5196 int r;
5197 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5198 bool writeback = true;
5199 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5200
5201 /*
5202 * Clear write_fault_to_shadow_pgtable here to ensure it is
5203 * never reused.
5204 */
5205 vcpu->arch.write_fault_to_shadow_pgtable = false;
5206 kvm_clear_exception_queue(vcpu);
5207
5208 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5209 init_emulate_ctxt(vcpu);
5210
5211 /*
5212 * We will reenter on the same instruction since
5213 * we do not set complete_userspace_io. This does not
5214 * handle watchpoints yet, those would be handled in
5215 * the emulate_ops.
5216 */
5217 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5218 return r;
5219
5220 ctxt->interruptibility = 0;
5221 ctxt->have_exception = false;
5222 ctxt->exception.vector = -1;
5223 ctxt->perm_ok = false;
5224
5225 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5226
5227 r = x86_decode_insn(ctxt, insn, insn_len);
5228
5229 trace_kvm_emulate_insn_start(vcpu);
5230 ++vcpu->stat.insn_emulation;
5231 if (r != EMULATION_OK) {
5232 if (emulation_type & EMULTYPE_TRAP_UD)
5233 return EMULATE_FAIL;
5234 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5235 emulation_type))
5236 return EMULATE_DONE;
5237 if (emulation_type & EMULTYPE_SKIP)
5238 return EMULATE_FAIL;
5239 return handle_emulation_failure(vcpu);
5240 }
5241 }
5242
5243 if (emulation_type & EMULTYPE_SKIP) {
5244 kvm_rip_write(vcpu, ctxt->_eip);
5245 if (ctxt->eflags & X86_EFLAGS_RF)
5246 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5247 return EMULATE_DONE;
5248 }
5249
5250 if (retry_instruction(ctxt, cr2, emulation_type))
5251 return EMULATE_DONE;
5252
5253 /* this is needed for vmware backdoor interface to work since it
5254 changes registers values during IO operation */
5255 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5256 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5257 emulator_invalidate_register_cache(ctxt);
5258 }
5259
5260 restart:
5261 r = x86_emulate_insn(ctxt);
5262
5263 if (r == EMULATION_INTERCEPTED)
5264 return EMULATE_DONE;
5265
5266 if (r == EMULATION_FAILED) {
5267 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5268 emulation_type))
5269 return EMULATE_DONE;
5270
5271 return handle_emulation_failure(vcpu);
5272 }
5273
5274 if (ctxt->have_exception) {
5275 r = EMULATE_DONE;
5276 if (inject_emulated_exception(vcpu))
5277 return r;
5278 } else if (vcpu->arch.pio.count) {
5279 if (!vcpu->arch.pio.in) {
5280 /* FIXME: return into emulator if single-stepping. */
5281 vcpu->arch.pio.count = 0;
5282 } else {
5283 writeback = false;
5284 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5285 }
5286 r = EMULATE_USER_EXIT;
5287 } else if (vcpu->mmio_needed) {
5288 if (!vcpu->mmio_is_write)
5289 writeback = false;
5290 r = EMULATE_USER_EXIT;
5291 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5292 } else if (r == EMULATION_RESTART)
5293 goto restart;
5294 else
5295 r = EMULATE_DONE;
5296
5297 if (writeback) {
5298 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5299 toggle_interruptibility(vcpu, ctxt->interruptibility);
5300 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5301 if (vcpu->arch.hflags != ctxt->emul_flags)
5302 kvm_set_hflags(vcpu, ctxt->emul_flags);
5303 kvm_rip_write(vcpu, ctxt->eip);
5304 if (r == EMULATE_DONE)
5305 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5306 if (!ctxt->have_exception ||
5307 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5308 __kvm_set_rflags(vcpu, ctxt->eflags);
5309
5310 /*
5311 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5312 * do nothing, and it will be requested again as soon as
5313 * the shadow expires. But we still need to check here,
5314 * because POPF has no interrupt shadow.
5315 */
5316 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5317 kvm_make_request(KVM_REQ_EVENT, vcpu);
5318 } else
5319 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5320
5321 return r;
5322 }
5323 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5324
5325 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5326 {
5327 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5328 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5329 size, port, &val, 1);
5330 /* do not return to emulator after return from userspace */
5331 vcpu->arch.pio.count = 0;
5332 return ret;
5333 }
5334 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5335
5336 static void tsc_bad(void *info)
5337 {
5338 __this_cpu_write(cpu_tsc_khz, 0);
5339 }
5340
5341 static void tsc_khz_changed(void *data)
5342 {
5343 struct cpufreq_freqs *freq = data;
5344 unsigned long khz = 0;
5345
5346 if (data)
5347 khz = freq->new;
5348 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5349 khz = cpufreq_quick_get(raw_smp_processor_id());
5350 if (!khz)
5351 khz = tsc_khz;
5352 __this_cpu_write(cpu_tsc_khz, khz);
5353 }
5354
5355 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5356 void *data)
5357 {
5358 struct cpufreq_freqs *freq = data;
5359 struct kvm *kvm;
5360 struct kvm_vcpu *vcpu;
5361 int i, send_ipi = 0;
5362
5363 /*
5364 * We allow guests to temporarily run on slowing clocks,
5365 * provided we notify them after, or to run on accelerating
5366 * clocks, provided we notify them before. Thus time never
5367 * goes backwards.
5368 *
5369 * However, we have a problem. We can't atomically update
5370 * the frequency of a given CPU from this function; it is
5371 * merely a notifier, which can be called from any CPU.
5372 * Changing the TSC frequency at arbitrary points in time
5373 * requires a recomputation of local variables related to
5374 * the TSC for each VCPU. We must flag these local variables
5375 * to be updated and be sure the update takes place with the
5376 * new frequency before any guests proceed.
5377 *
5378 * Unfortunately, the combination of hotplug CPU and frequency
5379 * change creates an intractable locking scenario; the order
5380 * of when these callouts happen is undefined with respect to
5381 * CPU hotplug, and they can race with each other. As such,
5382 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5383 * undefined; you can actually have a CPU frequency change take
5384 * place in between the computation of X and the setting of the
5385 * variable. To protect against this problem, all updates of
5386 * the per_cpu tsc_khz variable are done in an interrupt
5387 * protected IPI, and all callers wishing to update the value
5388 * must wait for a synchronous IPI to complete (which is trivial
5389 * if the caller is on the CPU already). This establishes the
5390 * necessary total order on variable updates.
5391 *
5392 * Note that because a guest time update may take place
5393 * anytime after the setting of the VCPU's request bit, the
5394 * correct TSC value must be set before the request. However,
5395 * to ensure the update actually makes it to any guest which
5396 * starts running in hardware virtualization between the set
5397 * and the acquisition of the spinlock, we must also ping the
5398 * CPU after setting the request bit.
5399 *
5400 */
5401
5402 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5403 return 0;
5404 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5405 return 0;
5406
5407 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5408
5409 spin_lock(&kvm_lock);
5410 list_for_each_entry(kvm, &vm_list, vm_list) {
5411 kvm_for_each_vcpu(i, vcpu, kvm) {
5412 if (vcpu->cpu != freq->cpu)
5413 continue;
5414 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5415 if (vcpu->cpu != smp_processor_id())
5416 send_ipi = 1;
5417 }
5418 }
5419 spin_unlock(&kvm_lock);
5420
5421 if (freq->old < freq->new && send_ipi) {
5422 /*
5423 * We upscale the frequency. Must make the guest
5424 * doesn't see old kvmclock values while running with
5425 * the new frequency, otherwise we risk the guest sees
5426 * time go backwards.
5427 *
5428 * In case we update the frequency for another cpu
5429 * (which might be in guest context) send an interrupt
5430 * to kick the cpu out of guest context. Next time
5431 * guest context is entered kvmclock will be updated,
5432 * so the guest will not see stale values.
5433 */
5434 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5435 }
5436 return 0;
5437 }
5438
5439 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5440 .notifier_call = kvmclock_cpufreq_notifier
5441 };
5442
5443 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5444 unsigned long action, void *hcpu)
5445 {
5446 unsigned int cpu = (unsigned long)hcpu;
5447
5448 switch (action) {
5449 case CPU_ONLINE:
5450 case CPU_DOWN_FAILED:
5451 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5452 break;
5453 case CPU_DOWN_PREPARE:
5454 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5455 break;
5456 }
5457 return NOTIFY_OK;
5458 }
5459
5460 static struct notifier_block kvmclock_cpu_notifier_block = {
5461 .notifier_call = kvmclock_cpu_notifier,
5462 .priority = -INT_MAX
5463 };
5464
5465 static void kvm_timer_init(void)
5466 {
5467 int cpu;
5468
5469 max_tsc_khz = tsc_khz;
5470
5471 cpu_notifier_register_begin();
5472 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5473 #ifdef CONFIG_CPU_FREQ
5474 struct cpufreq_policy policy;
5475 memset(&policy, 0, sizeof(policy));
5476 cpu = get_cpu();
5477 cpufreq_get_policy(&policy, cpu);
5478 if (policy.cpuinfo.max_freq)
5479 max_tsc_khz = policy.cpuinfo.max_freq;
5480 put_cpu();
5481 #endif
5482 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5483 CPUFREQ_TRANSITION_NOTIFIER);
5484 }
5485 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5486 for_each_online_cpu(cpu)
5487 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5488
5489 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5490 cpu_notifier_register_done();
5491
5492 }
5493
5494 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5495
5496 int kvm_is_in_guest(void)
5497 {
5498 return __this_cpu_read(current_vcpu) != NULL;
5499 }
5500
5501 static int kvm_is_user_mode(void)
5502 {
5503 int user_mode = 3;
5504
5505 if (__this_cpu_read(current_vcpu))
5506 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5507
5508 return user_mode != 0;
5509 }
5510
5511 static unsigned long kvm_get_guest_ip(void)
5512 {
5513 unsigned long ip = 0;
5514
5515 if (__this_cpu_read(current_vcpu))
5516 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5517
5518 return ip;
5519 }
5520
5521 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5522 .is_in_guest = kvm_is_in_guest,
5523 .is_user_mode = kvm_is_user_mode,
5524 .get_guest_ip = kvm_get_guest_ip,
5525 };
5526
5527 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5528 {
5529 __this_cpu_write(current_vcpu, vcpu);
5530 }
5531 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5532
5533 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5534 {
5535 __this_cpu_write(current_vcpu, NULL);
5536 }
5537 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5538
5539 static void kvm_set_mmio_spte_mask(void)
5540 {
5541 u64 mask;
5542 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5543
5544 /*
5545 * Set the reserved bits and the present bit of an paging-structure
5546 * entry to generate page fault with PFER.RSV = 1.
5547 */
5548 /* Mask the reserved physical address bits. */
5549 mask = rsvd_bits(maxphyaddr, 51);
5550
5551 /* Bit 62 is always reserved for 32bit host. */
5552 mask |= 0x3ull << 62;
5553
5554 /* Set the present bit. */
5555 mask |= 1ull;
5556
5557 #ifdef CONFIG_X86_64
5558 /*
5559 * If reserved bit is not supported, clear the present bit to disable
5560 * mmio page fault.
5561 */
5562 if (maxphyaddr == 52)
5563 mask &= ~1ull;
5564 #endif
5565
5566 kvm_mmu_set_mmio_spte_mask(mask);
5567 }
5568
5569 #ifdef CONFIG_X86_64
5570 static void pvclock_gtod_update_fn(struct work_struct *work)
5571 {
5572 struct kvm *kvm;
5573
5574 struct kvm_vcpu *vcpu;
5575 int i;
5576
5577 spin_lock(&kvm_lock);
5578 list_for_each_entry(kvm, &vm_list, vm_list)
5579 kvm_for_each_vcpu(i, vcpu, kvm)
5580 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5581 atomic_set(&kvm_guest_has_master_clock, 0);
5582 spin_unlock(&kvm_lock);
5583 }
5584
5585 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5586
5587 /*
5588 * Notification about pvclock gtod data update.
5589 */
5590 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5591 void *priv)
5592 {
5593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5594 struct timekeeper *tk = priv;
5595
5596 update_pvclock_gtod(tk);
5597
5598 /* disable master clock if host does not trust, or does not
5599 * use, TSC clocksource
5600 */
5601 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5602 atomic_read(&kvm_guest_has_master_clock) != 0)
5603 queue_work(system_long_wq, &pvclock_gtod_work);
5604
5605 return 0;
5606 }
5607
5608 static struct notifier_block pvclock_gtod_notifier = {
5609 .notifier_call = pvclock_gtod_notify,
5610 };
5611 #endif
5612
5613 int kvm_arch_init(void *opaque)
5614 {
5615 int r;
5616 struct kvm_x86_ops *ops = opaque;
5617
5618 if (kvm_x86_ops) {
5619 printk(KERN_ERR "kvm: already loaded the other module\n");
5620 r = -EEXIST;
5621 goto out;
5622 }
5623
5624 if (!ops->cpu_has_kvm_support()) {
5625 printk(KERN_ERR "kvm: no hardware support\n");
5626 r = -EOPNOTSUPP;
5627 goto out;
5628 }
5629 if (ops->disabled_by_bios()) {
5630 printk(KERN_ERR "kvm: disabled by bios\n");
5631 r = -EOPNOTSUPP;
5632 goto out;
5633 }
5634
5635 r = -ENOMEM;
5636 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5637 if (!shared_msrs) {
5638 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5639 goto out;
5640 }
5641
5642 r = kvm_mmu_module_init();
5643 if (r)
5644 goto out_free_percpu;
5645
5646 kvm_set_mmio_spte_mask();
5647
5648 kvm_x86_ops = ops;
5649
5650 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5651 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5652
5653 kvm_timer_init();
5654
5655 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5656
5657 if (cpu_has_xsave)
5658 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5659
5660 kvm_lapic_init();
5661 #ifdef CONFIG_X86_64
5662 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5663 #endif
5664
5665 return 0;
5666
5667 out_free_percpu:
5668 free_percpu(shared_msrs);
5669 out:
5670 return r;
5671 }
5672
5673 void kvm_arch_exit(void)
5674 {
5675 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5676
5677 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5678 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5679 CPUFREQ_TRANSITION_NOTIFIER);
5680 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5681 #ifdef CONFIG_X86_64
5682 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5683 #endif
5684 kvm_x86_ops = NULL;
5685 kvm_mmu_module_exit();
5686 free_percpu(shared_msrs);
5687 }
5688
5689 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5690 {
5691 ++vcpu->stat.halt_exits;
5692 if (lapic_in_kernel(vcpu)) {
5693 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5694 return 1;
5695 } else {
5696 vcpu->run->exit_reason = KVM_EXIT_HLT;
5697 return 0;
5698 }
5699 }
5700 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5701
5702 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5703 {
5704 kvm_x86_ops->skip_emulated_instruction(vcpu);
5705 return kvm_vcpu_halt(vcpu);
5706 }
5707 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5708
5709 /*
5710 * kvm_pv_kick_cpu_op: Kick a vcpu.
5711 *
5712 * @apicid - apicid of vcpu to be kicked.
5713 */
5714 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5715 {
5716 struct kvm_lapic_irq lapic_irq;
5717
5718 lapic_irq.shorthand = 0;
5719 lapic_irq.dest_mode = 0;
5720 lapic_irq.dest_id = apicid;
5721 lapic_irq.msi_redir_hint = false;
5722
5723 lapic_irq.delivery_mode = APIC_DM_REMRD;
5724 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5725 }
5726
5727 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5728 {
5729 unsigned long nr, a0, a1, a2, a3, ret;
5730 int op_64_bit, r = 1;
5731
5732 kvm_x86_ops->skip_emulated_instruction(vcpu);
5733
5734 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5735 return kvm_hv_hypercall(vcpu);
5736
5737 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5738 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5739 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5740 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5741 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5742
5743 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5744
5745 op_64_bit = is_64_bit_mode(vcpu);
5746 if (!op_64_bit) {
5747 nr &= 0xFFFFFFFF;
5748 a0 &= 0xFFFFFFFF;
5749 a1 &= 0xFFFFFFFF;
5750 a2 &= 0xFFFFFFFF;
5751 a3 &= 0xFFFFFFFF;
5752 }
5753
5754 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5755 ret = -KVM_EPERM;
5756 goto out;
5757 }
5758
5759 switch (nr) {
5760 case KVM_HC_VAPIC_POLL_IRQ:
5761 ret = 0;
5762 break;
5763 case KVM_HC_KICK_CPU:
5764 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5765 ret = 0;
5766 break;
5767 default:
5768 ret = -KVM_ENOSYS;
5769 break;
5770 }
5771 out:
5772 if (!op_64_bit)
5773 ret = (u32)ret;
5774 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5775 ++vcpu->stat.hypercalls;
5776 return r;
5777 }
5778 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5779
5780 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5781 {
5782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5783 char instruction[3];
5784 unsigned long rip = kvm_rip_read(vcpu);
5785
5786 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5787
5788 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5789 }
5790
5791 /*
5792 * Check if userspace requested an interrupt window, and that the
5793 * interrupt window is open.
5794 *
5795 * No need to exit to userspace if we already have an interrupt queued.
5796 */
5797 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5798 {
5799 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5800 vcpu->run->request_interrupt_window &&
5801 kvm_arch_interrupt_allowed(vcpu));
5802 }
5803
5804 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5805 {
5806 struct kvm_run *kvm_run = vcpu->run;
5807
5808 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5809 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5810 kvm_run->cr8 = kvm_get_cr8(vcpu);
5811 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5812 if (irqchip_in_kernel(vcpu->kvm))
5813 kvm_run->ready_for_interrupt_injection = 1;
5814 else
5815 kvm_run->ready_for_interrupt_injection =
5816 kvm_arch_interrupt_allowed(vcpu) &&
5817 !kvm_cpu_has_interrupt(vcpu) &&
5818 !kvm_event_needs_reinjection(vcpu);
5819 }
5820
5821 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5822 {
5823 int max_irr, tpr;
5824
5825 if (!kvm_x86_ops->update_cr8_intercept)
5826 return;
5827
5828 if (!vcpu->arch.apic)
5829 return;
5830
5831 if (!vcpu->arch.apic->vapic_addr)
5832 max_irr = kvm_lapic_find_highest_irr(vcpu);
5833 else
5834 max_irr = -1;
5835
5836 if (max_irr != -1)
5837 max_irr >>= 4;
5838
5839 tpr = kvm_lapic_get_cr8(vcpu);
5840
5841 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5842 }
5843
5844 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5845 {
5846 int r;
5847
5848 /* try to reinject previous events if any */
5849 if (vcpu->arch.exception.pending) {
5850 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5851 vcpu->arch.exception.has_error_code,
5852 vcpu->arch.exception.error_code);
5853
5854 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5855 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5856 X86_EFLAGS_RF);
5857
5858 if (vcpu->arch.exception.nr == DB_VECTOR &&
5859 (vcpu->arch.dr7 & DR7_GD)) {
5860 vcpu->arch.dr7 &= ~DR7_GD;
5861 kvm_update_dr7(vcpu);
5862 }
5863
5864 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5865 vcpu->arch.exception.has_error_code,
5866 vcpu->arch.exception.error_code,
5867 vcpu->arch.exception.reinject);
5868 return 0;
5869 }
5870
5871 if (vcpu->arch.nmi_injected) {
5872 kvm_x86_ops->set_nmi(vcpu);
5873 return 0;
5874 }
5875
5876 if (vcpu->arch.interrupt.pending) {
5877 kvm_x86_ops->set_irq(vcpu);
5878 return 0;
5879 }
5880
5881 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5882 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5883 if (r != 0)
5884 return r;
5885 }
5886
5887 /* try to inject new event if pending */
5888 if (vcpu->arch.nmi_pending) {
5889 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5890 --vcpu->arch.nmi_pending;
5891 vcpu->arch.nmi_injected = true;
5892 kvm_x86_ops->set_nmi(vcpu);
5893 }
5894 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5895 /*
5896 * Because interrupts can be injected asynchronously, we are
5897 * calling check_nested_events again here to avoid a race condition.
5898 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5899 * proposal and current concerns. Perhaps we should be setting
5900 * KVM_REQ_EVENT only on certain events and not unconditionally?
5901 */
5902 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5903 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5904 if (r != 0)
5905 return r;
5906 }
5907 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5908 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5909 false);
5910 kvm_x86_ops->set_irq(vcpu);
5911 }
5912 }
5913 return 0;
5914 }
5915
5916 static void process_nmi(struct kvm_vcpu *vcpu)
5917 {
5918 unsigned limit = 2;
5919
5920 /*
5921 * x86 is limited to one NMI running, and one NMI pending after it.
5922 * If an NMI is already in progress, limit further NMIs to just one.
5923 * Otherwise, allow two (and we'll inject the first one immediately).
5924 */
5925 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5926 limit = 1;
5927
5928 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5929 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5930 kvm_make_request(KVM_REQ_EVENT, vcpu);
5931 }
5932
5933 #define put_smstate(type, buf, offset, val) \
5934 *(type *)((buf) + (offset) - 0x7e00) = val
5935
5936 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5937 {
5938 u32 flags = 0;
5939 flags |= seg->g << 23;
5940 flags |= seg->db << 22;
5941 flags |= seg->l << 21;
5942 flags |= seg->avl << 20;
5943 flags |= seg->present << 15;
5944 flags |= seg->dpl << 13;
5945 flags |= seg->s << 12;
5946 flags |= seg->type << 8;
5947 return flags;
5948 }
5949
5950 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5951 {
5952 struct kvm_segment seg;
5953 int offset;
5954
5955 kvm_get_segment(vcpu, &seg, n);
5956 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5957
5958 if (n < 3)
5959 offset = 0x7f84 + n * 12;
5960 else
5961 offset = 0x7f2c + (n - 3) * 12;
5962
5963 put_smstate(u32, buf, offset + 8, seg.base);
5964 put_smstate(u32, buf, offset + 4, seg.limit);
5965 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5966 }
5967
5968 #ifdef CONFIG_X86_64
5969 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5970 {
5971 struct kvm_segment seg;
5972 int offset;
5973 u16 flags;
5974
5975 kvm_get_segment(vcpu, &seg, n);
5976 offset = 0x7e00 + n * 16;
5977
5978 flags = process_smi_get_segment_flags(&seg) >> 8;
5979 put_smstate(u16, buf, offset, seg.selector);
5980 put_smstate(u16, buf, offset + 2, flags);
5981 put_smstate(u32, buf, offset + 4, seg.limit);
5982 put_smstate(u64, buf, offset + 8, seg.base);
5983 }
5984 #endif
5985
5986 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5987 {
5988 struct desc_ptr dt;
5989 struct kvm_segment seg;
5990 unsigned long val;
5991 int i;
5992
5993 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5994 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5995 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5996 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5997
5998 for (i = 0; i < 8; i++)
5999 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6000
6001 kvm_get_dr(vcpu, 6, &val);
6002 put_smstate(u32, buf, 0x7fcc, (u32)val);
6003 kvm_get_dr(vcpu, 7, &val);
6004 put_smstate(u32, buf, 0x7fc8, (u32)val);
6005
6006 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6007 put_smstate(u32, buf, 0x7fc4, seg.selector);
6008 put_smstate(u32, buf, 0x7f64, seg.base);
6009 put_smstate(u32, buf, 0x7f60, seg.limit);
6010 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6011
6012 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6013 put_smstate(u32, buf, 0x7fc0, seg.selector);
6014 put_smstate(u32, buf, 0x7f80, seg.base);
6015 put_smstate(u32, buf, 0x7f7c, seg.limit);
6016 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6017
6018 kvm_x86_ops->get_gdt(vcpu, &dt);
6019 put_smstate(u32, buf, 0x7f74, dt.address);
6020 put_smstate(u32, buf, 0x7f70, dt.size);
6021
6022 kvm_x86_ops->get_idt(vcpu, &dt);
6023 put_smstate(u32, buf, 0x7f58, dt.address);
6024 put_smstate(u32, buf, 0x7f54, dt.size);
6025
6026 for (i = 0; i < 6; i++)
6027 process_smi_save_seg_32(vcpu, buf, i);
6028
6029 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6030
6031 /* revision id */
6032 put_smstate(u32, buf, 0x7efc, 0x00020000);
6033 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6034 }
6035
6036 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6037 {
6038 #ifdef CONFIG_X86_64
6039 struct desc_ptr dt;
6040 struct kvm_segment seg;
6041 unsigned long val;
6042 int i;
6043
6044 for (i = 0; i < 16; i++)
6045 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6046
6047 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6048 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6049
6050 kvm_get_dr(vcpu, 6, &val);
6051 put_smstate(u64, buf, 0x7f68, val);
6052 kvm_get_dr(vcpu, 7, &val);
6053 put_smstate(u64, buf, 0x7f60, val);
6054
6055 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6056 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6057 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6058
6059 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6060
6061 /* revision id */
6062 put_smstate(u32, buf, 0x7efc, 0x00020064);
6063
6064 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6065
6066 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6067 put_smstate(u16, buf, 0x7e90, seg.selector);
6068 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6069 put_smstate(u32, buf, 0x7e94, seg.limit);
6070 put_smstate(u64, buf, 0x7e98, seg.base);
6071
6072 kvm_x86_ops->get_idt(vcpu, &dt);
6073 put_smstate(u32, buf, 0x7e84, dt.size);
6074 put_smstate(u64, buf, 0x7e88, dt.address);
6075
6076 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6077 put_smstate(u16, buf, 0x7e70, seg.selector);
6078 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6079 put_smstate(u32, buf, 0x7e74, seg.limit);
6080 put_smstate(u64, buf, 0x7e78, seg.base);
6081
6082 kvm_x86_ops->get_gdt(vcpu, &dt);
6083 put_smstate(u32, buf, 0x7e64, dt.size);
6084 put_smstate(u64, buf, 0x7e68, dt.address);
6085
6086 for (i = 0; i < 6; i++)
6087 process_smi_save_seg_64(vcpu, buf, i);
6088 #else
6089 WARN_ON_ONCE(1);
6090 #endif
6091 }
6092
6093 static void process_smi(struct kvm_vcpu *vcpu)
6094 {
6095 struct kvm_segment cs, ds;
6096 struct desc_ptr dt;
6097 char buf[512];
6098 u32 cr0;
6099
6100 if (is_smm(vcpu)) {
6101 vcpu->arch.smi_pending = true;
6102 return;
6103 }
6104
6105 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6106 vcpu->arch.hflags |= HF_SMM_MASK;
6107 memset(buf, 0, 512);
6108 if (guest_cpuid_has_longmode(vcpu))
6109 process_smi_save_state_64(vcpu, buf);
6110 else
6111 process_smi_save_state_32(vcpu, buf);
6112
6113 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6114
6115 if (kvm_x86_ops->get_nmi_mask(vcpu))
6116 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6117 else
6118 kvm_x86_ops->set_nmi_mask(vcpu, true);
6119
6120 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6121 kvm_rip_write(vcpu, 0x8000);
6122
6123 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6124 kvm_x86_ops->set_cr0(vcpu, cr0);
6125 vcpu->arch.cr0 = cr0;
6126
6127 kvm_x86_ops->set_cr4(vcpu, 0);
6128
6129 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6130 dt.address = dt.size = 0;
6131 kvm_x86_ops->set_idt(vcpu, &dt);
6132
6133 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6134
6135 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6136 cs.base = vcpu->arch.smbase;
6137
6138 ds.selector = 0;
6139 ds.base = 0;
6140
6141 cs.limit = ds.limit = 0xffffffff;
6142 cs.type = ds.type = 0x3;
6143 cs.dpl = ds.dpl = 0;
6144 cs.db = ds.db = 0;
6145 cs.s = ds.s = 1;
6146 cs.l = ds.l = 0;
6147 cs.g = ds.g = 1;
6148 cs.avl = ds.avl = 0;
6149 cs.present = ds.present = 1;
6150 cs.unusable = ds.unusable = 0;
6151 cs.padding = ds.padding = 0;
6152
6153 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6154 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6155 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6156 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6157 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6158 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6159
6160 if (guest_cpuid_has_longmode(vcpu))
6161 kvm_x86_ops->set_efer(vcpu, 0);
6162
6163 kvm_update_cpuid(vcpu);
6164 kvm_mmu_reset_context(vcpu);
6165 }
6166
6167 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6168 {
6169 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6170 return;
6171
6172 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
6173
6174 if (irqchip_split(vcpu->kvm))
6175 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6176 else
6177 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
6178 kvm_x86_ops->load_eoi_exitmap(vcpu);
6179 }
6180
6181 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6182 {
6183 ++vcpu->stat.tlb_flush;
6184 kvm_x86_ops->tlb_flush(vcpu);
6185 }
6186
6187 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6188 {
6189 struct page *page = NULL;
6190
6191 if (!lapic_in_kernel(vcpu))
6192 return;
6193
6194 if (!kvm_x86_ops->set_apic_access_page_addr)
6195 return;
6196
6197 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6198 if (is_error_page(page))
6199 return;
6200 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6201
6202 /*
6203 * Do not pin apic access page in memory, the MMU notifier
6204 * will call us again if it is migrated or swapped out.
6205 */
6206 put_page(page);
6207 }
6208 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6209
6210 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6211 unsigned long address)
6212 {
6213 /*
6214 * The physical address of apic access page is stored in the VMCS.
6215 * Update it when it becomes invalid.
6216 */
6217 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6218 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6219 }
6220
6221 /*
6222 * Returns 1 to let vcpu_run() continue the guest execution loop without
6223 * exiting to the userspace. Otherwise, the value will be returned to the
6224 * userspace.
6225 */
6226 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6227 {
6228 int r;
6229 bool req_int_win = !lapic_in_kernel(vcpu) &&
6230 vcpu->run->request_interrupt_window;
6231 bool req_immediate_exit = false;
6232
6233 if (vcpu->requests) {
6234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6235 kvm_mmu_unload(vcpu);
6236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6237 __kvm_migrate_timers(vcpu);
6238 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6239 kvm_gen_update_masterclock(vcpu->kvm);
6240 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6241 kvm_gen_kvmclock_update(vcpu);
6242 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6243 r = kvm_guest_time_update(vcpu);
6244 if (unlikely(r))
6245 goto out;
6246 }
6247 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6248 kvm_mmu_sync_roots(vcpu);
6249 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6250 kvm_vcpu_flush_tlb(vcpu);
6251 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6252 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6253 r = 0;
6254 goto out;
6255 }
6256 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6257 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6258 r = 0;
6259 goto out;
6260 }
6261 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6262 vcpu->fpu_active = 0;
6263 kvm_x86_ops->fpu_deactivate(vcpu);
6264 }
6265 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6266 /* Page is swapped out. Do synthetic halt */
6267 vcpu->arch.apf.halted = true;
6268 r = 1;
6269 goto out;
6270 }
6271 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6272 record_steal_time(vcpu);
6273 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6274 process_smi(vcpu);
6275 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6276 process_nmi(vcpu);
6277 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6278 kvm_pmu_handle_event(vcpu);
6279 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6280 kvm_pmu_deliver_pmi(vcpu);
6281 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6282 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6283 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6284 (void *) vcpu->arch.eoi_exit_bitmap)) {
6285 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6286 vcpu->run->eoi.vector =
6287 vcpu->arch.pending_ioapic_eoi;
6288 r = 0;
6289 goto out;
6290 }
6291 }
6292 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6293 vcpu_scan_ioapic(vcpu);
6294 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6295 kvm_vcpu_reload_apic_access_page(vcpu);
6296 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6297 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6298 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6299 r = 0;
6300 goto out;
6301 }
6302 }
6303
6304 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6305 kvm_apic_accept_events(vcpu);
6306 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6307 r = 1;
6308 goto out;
6309 }
6310
6311 if (inject_pending_event(vcpu, req_int_win) != 0)
6312 req_immediate_exit = true;
6313 /* enable NMI/IRQ window open exits if needed */
6314 else if (vcpu->arch.nmi_pending)
6315 kvm_x86_ops->enable_nmi_window(vcpu);
6316 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6317 kvm_x86_ops->enable_irq_window(vcpu);
6318
6319 if (kvm_lapic_enabled(vcpu)) {
6320 /*
6321 * Update architecture specific hints for APIC
6322 * virtual interrupt delivery.
6323 */
6324 if (kvm_x86_ops->hwapic_irr_update)
6325 kvm_x86_ops->hwapic_irr_update(vcpu,
6326 kvm_lapic_find_highest_irr(vcpu));
6327 update_cr8_intercept(vcpu);
6328 kvm_lapic_sync_to_vapic(vcpu);
6329 }
6330 }
6331
6332 r = kvm_mmu_reload(vcpu);
6333 if (unlikely(r)) {
6334 goto cancel_injection;
6335 }
6336
6337 preempt_disable();
6338
6339 kvm_x86_ops->prepare_guest_switch(vcpu);
6340 if (vcpu->fpu_active)
6341 kvm_load_guest_fpu(vcpu);
6342 kvm_load_guest_xcr0(vcpu);
6343
6344 vcpu->mode = IN_GUEST_MODE;
6345
6346 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6347
6348 /* We should set ->mode before check ->requests,
6349 * see the comment in make_all_cpus_request.
6350 */
6351 smp_mb__after_srcu_read_unlock();
6352
6353 local_irq_disable();
6354
6355 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6356 || need_resched() || signal_pending(current)) {
6357 vcpu->mode = OUTSIDE_GUEST_MODE;
6358 smp_wmb();
6359 local_irq_enable();
6360 preempt_enable();
6361 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6362 r = 1;
6363 goto cancel_injection;
6364 }
6365
6366 if (req_immediate_exit)
6367 smp_send_reschedule(vcpu->cpu);
6368
6369 __kvm_guest_enter();
6370
6371 if (unlikely(vcpu->arch.switch_db_regs)) {
6372 set_debugreg(0, 7);
6373 set_debugreg(vcpu->arch.eff_db[0], 0);
6374 set_debugreg(vcpu->arch.eff_db[1], 1);
6375 set_debugreg(vcpu->arch.eff_db[2], 2);
6376 set_debugreg(vcpu->arch.eff_db[3], 3);
6377 set_debugreg(vcpu->arch.dr6, 6);
6378 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6379 }
6380
6381 trace_kvm_entry(vcpu->vcpu_id);
6382 wait_lapic_expire(vcpu);
6383 kvm_x86_ops->run(vcpu);
6384
6385 /*
6386 * Do this here before restoring debug registers on the host. And
6387 * since we do this before handling the vmexit, a DR access vmexit
6388 * can (a) read the correct value of the debug registers, (b) set
6389 * KVM_DEBUGREG_WONT_EXIT again.
6390 */
6391 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6392 int i;
6393
6394 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6395 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6396 for (i = 0; i < KVM_NR_DB_REGS; i++)
6397 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6398 }
6399
6400 /*
6401 * If the guest has used debug registers, at least dr7
6402 * will be disabled while returning to the host.
6403 * If we don't have active breakpoints in the host, we don't
6404 * care about the messed up debug address registers. But if
6405 * we have some of them active, restore the old state.
6406 */
6407 if (hw_breakpoint_active())
6408 hw_breakpoint_restore();
6409
6410 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6411 rdtsc());
6412
6413 vcpu->mode = OUTSIDE_GUEST_MODE;
6414 smp_wmb();
6415
6416 /* Interrupt is enabled by handle_external_intr() */
6417 kvm_x86_ops->handle_external_intr(vcpu);
6418
6419 ++vcpu->stat.exits;
6420
6421 /*
6422 * We must have an instruction between local_irq_enable() and
6423 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6424 * the interrupt shadow. The stat.exits increment will do nicely.
6425 * But we need to prevent reordering, hence this barrier():
6426 */
6427 barrier();
6428
6429 kvm_guest_exit();
6430
6431 preempt_enable();
6432
6433 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6434
6435 /*
6436 * Profile KVM exit RIPs:
6437 */
6438 if (unlikely(prof_on == KVM_PROFILING)) {
6439 unsigned long rip = kvm_rip_read(vcpu);
6440 profile_hit(KVM_PROFILING, (void *)rip);
6441 }
6442
6443 if (unlikely(vcpu->arch.tsc_always_catchup))
6444 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6445
6446 if (vcpu->arch.apic_attention)
6447 kvm_lapic_sync_from_vapic(vcpu);
6448
6449 r = kvm_x86_ops->handle_exit(vcpu);
6450 return r;
6451
6452 cancel_injection:
6453 kvm_x86_ops->cancel_injection(vcpu);
6454 if (unlikely(vcpu->arch.apic_attention))
6455 kvm_lapic_sync_from_vapic(vcpu);
6456 out:
6457 return r;
6458 }
6459
6460 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6461 {
6462 if (!kvm_arch_vcpu_runnable(vcpu)) {
6463 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6464 kvm_vcpu_block(vcpu);
6465 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6466 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6467 return 1;
6468 }
6469
6470 kvm_apic_accept_events(vcpu);
6471 switch(vcpu->arch.mp_state) {
6472 case KVM_MP_STATE_HALTED:
6473 vcpu->arch.pv.pv_unhalted = false;
6474 vcpu->arch.mp_state =
6475 KVM_MP_STATE_RUNNABLE;
6476 case KVM_MP_STATE_RUNNABLE:
6477 vcpu->arch.apf.halted = false;
6478 break;
6479 case KVM_MP_STATE_INIT_RECEIVED:
6480 break;
6481 default:
6482 return -EINTR;
6483 break;
6484 }
6485 return 1;
6486 }
6487
6488 static int vcpu_run(struct kvm_vcpu *vcpu)
6489 {
6490 int r;
6491 struct kvm *kvm = vcpu->kvm;
6492
6493 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6494
6495 for (;;) {
6496 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6497 !vcpu->arch.apf.halted)
6498 r = vcpu_enter_guest(vcpu);
6499 else
6500 r = vcpu_block(kvm, vcpu);
6501 if (r <= 0)
6502 break;
6503
6504 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6505 if (kvm_cpu_has_pending_timer(vcpu))
6506 kvm_inject_pending_timer_irqs(vcpu);
6507
6508 if (dm_request_for_irq_injection(vcpu)) {
6509 r = 0;
6510 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6511 ++vcpu->stat.request_irq_exits;
6512 break;
6513 }
6514
6515 kvm_check_async_pf_completion(vcpu);
6516
6517 if (signal_pending(current)) {
6518 r = -EINTR;
6519 vcpu->run->exit_reason = KVM_EXIT_INTR;
6520 ++vcpu->stat.signal_exits;
6521 break;
6522 }
6523 if (need_resched()) {
6524 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6525 cond_resched();
6526 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6527 }
6528 }
6529
6530 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6531
6532 return r;
6533 }
6534
6535 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6536 {
6537 int r;
6538 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6539 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6540 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6541 if (r != EMULATE_DONE)
6542 return 0;
6543 return 1;
6544 }
6545
6546 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6547 {
6548 BUG_ON(!vcpu->arch.pio.count);
6549
6550 return complete_emulated_io(vcpu);
6551 }
6552
6553 /*
6554 * Implements the following, as a state machine:
6555 *
6556 * read:
6557 * for each fragment
6558 * for each mmio piece in the fragment
6559 * write gpa, len
6560 * exit
6561 * copy data
6562 * execute insn
6563 *
6564 * write:
6565 * for each fragment
6566 * for each mmio piece in the fragment
6567 * write gpa, len
6568 * copy data
6569 * exit
6570 */
6571 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6572 {
6573 struct kvm_run *run = vcpu->run;
6574 struct kvm_mmio_fragment *frag;
6575 unsigned len;
6576
6577 BUG_ON(!vcpu->mmio_needed);
6578
6579 /* Complete previous fragment */
6580 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6581 len = min(8u, frag->len);
6582 if (!vcpu->mmio_is_write)
6583 memcpy(frag->data, run->mmio.data, len);
6584
6585 if (frag->len <= 8) {
6586 /* Switch to the next fragment. */
6587 frag++;
6588 vcpu->mmio_cur_fragment++;
6589 } else {
6590 /* Go forward to the next mmio piece. */
6591 frag->data += len;
6592 frag->gpa += len;
6593 frag->len -= len;
6594 }
6595
6596 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6597 vcpu->mmio_needed = 0;
6598
6599 /* FIXME: return into emulator if single-stepping. */
6600 if (vcpu->mmio_is_write)
6601 return 1;
6602 vcpu->mmio_read_completed = 1;
6603 return complete_emulated_io(vcpu);
6604 }
6605
6606 run->exit_reason = KVM_EXIT_MMIO;
6607 run->mmio.phys_addr = frag->gpa;
6608 if (vcpu->mmio_is_write)
6609 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6610 run->mmio.len = min(8u, frag->len);
6611 run->mmio.is_write = vcpu->mmio_is_write;
6612 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6613 return 0;
6614 }
6615
6616
6617 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6618 {
6619 struct fpu *fpu = &current->thread.fpu;
6620 int r;
6621 sigset_t sigsaved;
6622
6623 fpu__activate_curr(fpu);
6624
6625 if (vcpu->sigset_active)
6626 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6627
6628 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6629 kvm_vcpu_block(vcpu);
6630 kvm_apic_accept_events(vcpu);
6631 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6632 r = -EAGAIN;
6633 goto out;
6634 }
6635
6636 /* re-sync apic's tpr */
6637 if (!lapic_in_kernel(vcpu)) {
6638 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6639 r = -EINVAL;
6640 goto out;
6641 }
6642 }
6643
6644 if (unlikely(vcpu->arch.complete_userspace_io)) {
6645 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6646 vcpu->arch.complete_userspace_io = NULL;
6647 r = cui(vcpu);
6648 if (r <= 0)
6649 goto out;
6650 } else
6651 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6652
6653 r = vcpu_run(vcpu);
6654
6655 out:
6656 post_kvm_run_save(vcpu);
6657 if (vcpu->sigset_active)
6658 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6659
6660 return r;
6661 }
6662
6663 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6664 {
6665 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6666 /*
6667 * We are here if userspace calls get_regs() in the middle of
6668 * instruction emulation. Registers state needs to be copied
6669 * back from emulation context to vcpu. Userspace shouldn't do
6670 * that usually, but some bad designed PV devices (vmware
6671 * backdoor interface) need this to work
6672 */
6673 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6674 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6675 }
6676 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6677 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6678 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6679 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6680 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6681 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6682 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6683 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6684 #ifdef CONFIG_X86_64
6685 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6686 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6687 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6688 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6689 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6690 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6691 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6692 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6693 #endif
6694
6695 regs->rip = kvm_rip_read(vcpu);
6696 regs->rflags = kvm_get_rflags(vcpu);
6697
6698 return 0;
6699 }
6700
6701 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6702 {
6703 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6704 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6705
6706 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6707 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6708 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6709 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6710 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6711 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6712 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6713 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6714 #ifdef CONFIG_X86_64
6715 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6716 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6717 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6718 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6719 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6720 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6721 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6722 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6723 #endif
6724
6725 kvm_rip_write(vcpu, regs->rip);
6726 kvm_set_rflags(vcpu, regs->rflags);
6727
6728 vcpu->arch.exception.pending = false;
6729
6730 kvm_make_request(KVM_REQ_EVENT, vcpu);
6731
6732 return 0;
6733 }
6734
6735 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6736 {
6737 struct kvm_segment cs;
6738
6739 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6740 *db = cs.db;
6741 *l = cs.l;
6742 }
6743 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6744
6745 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6746 struct kvm_sregs *sregs)
6747 {
6748 struct desc_ptr dt;
6749
6750 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6751 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6752 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6753 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6754 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6755 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6756
6757 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6758 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6759
6760 kvm_x86_ops->get_idt(vcpu, &dt);
6761 sregs->idt.limit = dt.size;
6762 sregs->idt.base = dt.address;
6763 kvm_x86_ops->get_gdt(vcpu, &dt);
6764 sregs->gdt.limit = dt.size;
6765 sregs->gdt.base = dt.address;
6766
6767 sregs->cr0 = kvm_read_cr0(vcpu);
6768 sregs->cr2 = vcpu->arch.cr2;
6769 sregs->cr3 = kvm_read_cr3(vcpu);
6770 sregs->cr4 = kvm_read_cr4(vcpu);
6771 sregs->cr8 = kvm_get_cr8(vcpu);
6772 sregs->efer = vcpu->arch.efer;
6773 sregs->apic_base = kvm_get_apic_base(vcpu);
6774
6775 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6776
6777 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6778 set_bit(vcpu->arch.interrupt.nr,
6779 (unsigned long *)sregs->interrupt_bitmap);
6780
6781 return 0;
6782 }
6783
6784 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6785 struct kvm_mp_state *mp_state)
6786 {
6787 kvm_apic_accept_events(vcpu);
6788 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6789 vcpu->arch.pv.pv_unhalted)
6790 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6791 else
6792 mp_state->mp_state = vcpu->arch.mp_state;
6793
6794 return 0;
6795 }
6796
6797 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6798 struct kvm_mp_state *mp_state)
6799 {
6800 if (!kvm_vcpu_has_lapic(vcpu) &&
6801 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6802 return -EINVAL;
6803
6804 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6805 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6806 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6807 } else
6808 vcpu->arch.mp_state = mp_state->mp_state;
6809 kvm_make_request(KVM_REQ_EVENT, vcpu);
6810 return 0;
6811 }
6812
6813 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6814 int reason, bool has_error_code, u32 error_code)
6815 {
6816 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6817 int ret;
6818
6819 init_emulate_ctxt(vcpu);
6820
6821 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6822 has_error_code, error_code);
6823
6824 if (ret)
6825 return EMULATE_FAIL;
6826
6827 kvm_rip_write(vcpu, ctxt->eip);
6828 kvm_set_rflags(vcpu, ctxt->eflags);
6829 kvm_make_request(KVM_REQ_EVENT, vcpu);
6830 return EMULATE_DONE;
6831 }
6832 EXPORT_SYMBOL_GPL(kvm_task_switch);
6833
6834 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6835 struct kvm_sregs *sregs)
6836 {
6837 struct msr_data apic_base_msr;
6838 int mmu_reset_needed = 0;
6839 int pending_vec, max_bits, idx;
6840 struct desc_ptr dt;
6841
6842 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6843 return -EINVAL;
6844
6845 dt.size = sregs->idt.limit;
6846 dt.address = sregs->idt.base;
6847 kvm_x86_ops->set_idt(vcpu, &dt);
6848 dt.size = sregs->gdt.limit;
6849 dt.address = sregs->gdt.base;
6850 kvm_x86_ops->set_gdt(vcpu, &dt);
6851
6852 vcpu->arch.cr2 = sregs->cr2;
6853 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6854 vcpu->arch.cr3 = sregs->cr3;
6855 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6856
6857 kvm_set_cr8(vcpu, sregs->cr8);
6858
6859 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6860 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6861 apic_base_msr.data = sregs->apic_base;
6862 apic_base_msr.host_initiated = true;
6863 kvm_set_apic_base(vcpu, &apic_base_msr);
6864
6865 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6866 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6867 vcpu->arch.cr0 = sregs->cr0;
6868
6869 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6870 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6871 if (sregs->cr4 & X86_CR4_OSXSAVE)
6872 kvm_update_cpuid(vcpu);
6873
6874 idx = srcu_read_lock(&vcpu->kvm->srcu);
6875 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6876 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6877 mmu_reset_needed = 1;
6878 }
6879 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6880
6881 if (mmu_reset_needed)
6882 kvm_mmu_reset_context(vcpu);
6883
6884 max_bits = KVM_NR_INTERRUPTS;
6885 pending_vec = find_first_bit(
6886 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6887 if (pending_vec < max_bits) {
6888 kvm_queue_interrupt(vcpu, pending_vec, false);
6889 pr_debug("Set back pending irq %d\n", pending_vec);
6890 }
6891
6892 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6893 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6894 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6895 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6896 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6897 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6898
6899 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6900 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6901
6902 update_cr8_intercept(vcpu);
6903
6904 /* Older userspace won't unhalt the vcpu on reset. */
6905 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6906 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6907 !is_protmode(vcpu))
6908 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6909
6910 kvm_make_request(KVM_REQ_EVENT, vcpu);
6911
6912 return 0;
6913 }
6914
6915 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6916 struct kvm_guest_debug *dbg)
6917 {
6918 unsigned long rflags;
6919 int i, r;
6920
6921 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6922 r = -EBUSY;
6923 if (vcpu->arch.exception.pending)
6924 goto out;
6925 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6926 kvm_queue_exception(vcpu, DB_VECTOR);
6927 else
6928 kvm_queue_exception(vcpu, BP_VECTOR);
6929 }
6930
6931 /*
6932 * Read rflags as long as potentially injected trace flags are still
6933 * filtered out.
6934 */
6935 rflags = kvm_get_rflags(vcpu);
6936
6937 vcpu->guest_debug = dbg->control;
6938 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6939 vcpu->guest_debug = 0;
6940
6941 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6942 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6943 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6944 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6945 } else {
6946 for (i = 0; i < KVM_NR_DB_REGS; i++)
6947 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6948 }
6949 kvm_update_dr7(vcpu);
6950
6951 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6952 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6953 get_segment_base(vcpu, VCPU_SREG_CS);
6954
6955 /*
6956 * Trigger an rflags update that will inject or remove the trace
6957 * flags.
6958 */
6959 kvm_set_rflags(vcpu, rflags);
6960
6961 kvm_x86_ops->update_db_bp_intercept(vcpu);
6962
6963 r = 0;
6964
6965 out:
6966
6967 return r;
6968 }
6969
6970 /*
6971 * Translate a guest virtual address to a guest physical address.
6972 */
6973 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6974 struct kvm_translation *tr)
6975 {
6976 unsigned long vaddr = tr->linear_address;
6977 gpa_t gpa;
6978 int idx;
6979
6980 idx = srcu_read_lock(&vcpu->kvm->srcu);
6981 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6982 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6983 tr->physical_address = gpa;
6984 tr->valid = gpa != UNMAPPED_GVA;
6985 tr->writeable = 1;
6986 tr->usermode = 0;
6987
6988 return 0;
6989 }
6990
6991 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6992 {
6993 struct fxregs_state *fxsave =
6994 &vcpu->arch.guest_fpu.state.fxsave;
6995
6996 memcpy(fpu->fpr, fxsave->st_space, 128);
6997 fpu->fcw = fxsave->cwd;
6998 fpu->fsw = fxsave->swd;
6999 fpu->ftwx = fxsave->twd;
7000 fpu->last_opcode = fxsave->fop;
7001 fpu->last_ip = fxsave->rip;
7002 fpu->last_dp = fxsave->rdp;
7003 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7004
7005 return 0;
7006 }
7007
7008 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7009 {
7010 struct fxregs_state *fxsave =
7011 &vcpu->arch.guest_fpu.state.fxsave;
7012
7013 memcpy(fxsave->st_space, fpu->fpr, 128);
7014 fxsave->cwd = fpu->fcw;
7015 fxsave->swd = fpu->fsw;
7016 fxsave->twd = fpu->ftwx;
7017 fxsave->fop = fpu->last_opcode;
7018 fxsave->rip = fpu->last_ip;
7019 fxsave->rdp = fpu->last_dp;
7020 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7021
7022 return 0;
7023 }
7024
7025 static void fx_init(struct kvm_vcpu *vcpu)
7026 {
7027 fpstate_init(&vcpu->arch.guest_fpu.state);
7028 if (cpu_has_xsaves)
7029 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7030 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7031
7032 /*
7033 * Ensure guest xcr0 is valid for loading
7034 */
7035 vcpu->arch.xcr0 = XSTATE_FP;
7036
7037 vcpu->arch.cr0 |= X86_CR0_ET;
7038 }
7039
7040 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7041 {
7042 if (vcpu->guest_fpu_loaded)
7043 return;
7044
7045 /*
7046 * Restore all possible states in the guest,
7047 * and assume host would use all available bits.
7048 * Guest xcr0 would be loaded later.
7049 */
7050 kvm_put_guest_xcr0(vcpu);
7051 vcpu->guest_fpu_loaded = 1;
7052 __kernel_fpu_begin();
7053 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7054 trace_kvm_fpu(1);
7055 }
7056
7057 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7058 {
7059 kvm_put_guest_xcr0(vcpu);
7060
7061 if (!vcpu->guest_fpu_loaded) {
7062 vcpu->fpu_counter = 0;
7063 return;
7064 }
7065
7066 vcpu->guest_fpu_loaded = 0;
7067 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7068 __kernel_fpu_end();
7069 ++vcpu->stat.fpu_reload;
7070 /*
7071 * If using eager FPU mode, or if the guest is a frequent user
7072 * of the FPU, just leave the FPU active for next time.
7073 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7074 * the FPU in bursts will revert to loading it on demand.
7075 */
7076 if (!vcpu->arch.eager_fpu) {
7077 if (++vcpu->fpu_counter < 5)
7078 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7079 }
7080 trace_kvm_fpu(0);
7081 }
7082
7083 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7084 {
7085 kvmclock_reset(vcpu);
7086
7087 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7088 kvm_x86_ops->vcpu_free(vcpu);
7089 }
7090
7091 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7092 unsigned int id)
7093 {
7094 struct kvm_vcpu *vcpu;
7095
7096 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7097 printk_once(KERN_WARNING
7098 "kvm: SMP vm created on host with unstable TSC; "
7099 "guest TSC will not be reliable\n");
7100
7101 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7102
7103 return vcpu;
7104 }
7105
7106 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7107 {
7108 int r;
7109
7110 kvm_vcpu_mtrr_init(vcpu);
7111 r = vcpu_load(vcpu);
7112 if (r)
7113 return r;
7114 kvm_vcpu_reset(vcpu, false);
7115 kvm_mmu_setup(vcpu);
7116 vcpu_put(vcpu);
7117 return r;
7118 }
7119
7120 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7121 {
7122 struct msr_data msr;
7123 struct kvm *kvm = vcpu->kvm;
7124
7125 if (vcpu_load(vcpu))
7126 return;
7127 msr.data = 0x0;
7128 msr.index = MSR_IA32_TSC;
7129 msr.host_initiated = true;
7130 kvm_write_tsc(vcpu, &msr);
7131 vcpu_put(vcpu);
7132
7133 if (!kvmclock_periodic_sync)
7134 return;
7135
7136 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7137 KVMCLOCK_SYNC_PERIOD);
7138 }
7139
7140 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7141 {
7142 int r;
7143 vcpu->arch.apf.msr_val = 0;
7144
7145 r = vcpu_load(vcpu);
7146 BUG_ON(r);
7147 kvm_mmu_unload(vcpu);
7148 vcpu_put(vcpu);
7149
7150 kvm_x86_ops->vcpu_free(vcpu);
7151 }
7152
7153 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7154 {
7155 vcpu->arch.hflags = 0;
7156
7157 atomic_set(&vcpu->arch.nmi_queued, 0);
7158 vcpu->arch.nmi_pending = 0;
7159 vcpu->arch.nmi_injected = false;
7160 kvm_clear_interrupt_queue(vcpu);
7161 kvm_clear_exception_queue(vcpu);
7162
7163 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7164 kvm_update_dr0123(vcpu);
7165 vcpu->arch.dr6 = DR6_INIT;
7166 kvm_update_dr6(vcpu);
7167 vcpu->arch.dr7 = DR7_FIXED_1;
7168 kvm_update_dr7(vcpu);
7169
7170 vcpu->arch.cr2 = 0;
7171
7172 kvm_make_request(KVM_REQ_EVENT, vcpu);
7173 vcpu->arch.apf.msr_val = 0;
7174 vcpu->arch.st.msr_val = 0;
7175
7176 kvmclock_reset(vcpu);
7177
7178 kvm_clear_async_pf_completion_queue(vcpu);
7179 kvm_async_pf_hash_reset(vcpu);
7180 vcpu->arch.apf.halted = false;
7181
7182 if (!init_event) {
7183 kvm_pmu_reset(vcpu);
7184 vcpu->arch.smbase = 0x30000;
7185 }
7186
7187 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7188 vcpu->arch.regs_avail = ~0;
7189 vcpu->arch.regs_dirty = ~0;
7190
7191 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7192 }
7193
7194 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7195 {
7196 struct kvm_segment cs;
7197
7198 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7199 cs.selector = vector << 8;
7200 cs.base = vector << 12;
7201 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7202 kvm_rip_write(vcpu, 0);
7203 }
7204
7205 int kvm_arch_hardware_enable(void)
7206 {
7207 struct kvm *kvm;
7208 struct kvm_vcpu *vcpu;
7209 int i;
7210 int ret;
7211 u64 local_tsc;
7212 u64 max_tsc = 0;
7213 bool stable, backwards_tsc = false;
7214
7215 kvm_shared_msr_cpu_online();
7216 ret = kvm_x86_ops->hardware_enable();
7217 if (ret != 0)
7218 return ret;
7219
7220 local_tsc = rdtsc();
7221 stable = !check_tsc_unstable();
7222 list_for_each_entry(kvm, &vm_list, vm_list) {
7223 kvm_for_each_vcpu(i, vcpu, kvm) {
7224 if (!stable && vcpu->cpu == smp_processor_id())
7225 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7226 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7227 backwards_tsc = true;
7228 if (vcpu->arch.last_host_tsc > max_tsc)
7229 max_tsc = vcpu->arch.last_host_tsc;
7230 }
7231 }
7232 }
7233
7234 /*
7235 * Sometimes, even reliable TSCs go backwards. This happens on
7236 * platforms that reset TSC during suspend or hibernate actions, but
7237 * maintain synchronization. We must compensate. Fortunately, we can
7238 * detect that condition here, which happens early in CPU bringup,
7239 * before any KVM threads can be running. Unfortunately, we can't
7240 * bring the TSCs fully up to date with real time, as we aren't yet far
7241 * enough into CPU bringup that we know how much real time has actually
7242 * elapsed; our helper function, get_kernel_ns() will be using boot
7243 * variables that haven't been updated yet.
7244 *
7245 * So we simply find the maximum observed TSC above, then record the
7246 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7247 * the adjustment will be applied. Note that we accumulate
7248 * adjustments, in case multiple suspend cycles happen before some VCPU
7249 * gets a chance to run again. In the event that no KVM threads get a
7250 * chance to run, we will miss the entire elapsed period, as we'll have
7251 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7252 * loose cycle time. This isn't too big a deal, since the loss will be
7253 * uniform across all VCPUs (not to mention the scenario is extremely
7254 * unlikely). It is possible that a second hibernate recovery happens
7255 * much faster than a first, causing the observed TSC here to be
7256 * smaller; this would require additional padding adjustment, which is
7257 * why we set last_host_tsc to the local tsc observed here.
7258 *
7259 * N.B. - this code below runs only on platforms with reliable TSC,
7260 * as that is the only way backwards_tsc is set above. Also note
7261 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7262 * have the same delta_cyc adjustment applied if backwards_tsc
7263 * is detected. Note further, this adjustment is only done once,
7264 * as we reset last_host_tsc on all VCPUs to stop this from being
7265 * called multiple times (one for each physical CPU bringup).
7266 *
7267 * Platforms with unreliable TSCs don't have to deal with this, they
7268 * will be compensated by the logic in vcpu_load, which sets the TSC to
7269 * catchup mode. This will catchup all VCPUs to real time, but cannot
7270 * guarantee that they stay in perfect synchronization.
7271 */
7272 if (backwards_tsc) {
7273 u64 delta_cyc = max_tsc - local_tsc;
7274 backwards_tsc_observed = true;
7275 list_for_each_entry(kvm, &vm_list, vm_list) {
7276 kvm_for_each_vcpu(i, vcpu, kvm) {
7277 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7278 vcpu->arch.last_host_tsc = local_tsc;
7279 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7280 }
7281
7282 /*
7283 * We have to disable TSC offset matching.. if you were
7284 * booting a VM while issuing an S4 host suspend....
7285 * you may have some problem. Solving this issue is
7286 * left as an exercise to the reader.
7287 */
7288 kvm->arch.last_tsc_nsec = 0;
7289 kvm->arch.last_tsc_write = 0;
7290 }
7291
7292 }
7293 return 0;
7294 }
7295
7296 void kvm_arch_hardware_disable(void)
7297 {
7298 kvm_x86_ops->hardware_disable();
7299 drop_user_return_notifiers();
7300 }
7301
7302 int kvm_arch_hardware_setup(void)
7303 {
7304 int r;
7305
7306 r = kvm_x86_ops->hardware_setup();
7307 if (r != 0)
7308 return r;
7309
7310 kvm_init_msr_list();
7311 return 0;
7312 }
7313
7314 void kvm_arch_hardware_unsetup(void)
7315 {
7316 kvm_x86_ops->hardware_unsetup();
7317 }
7318
7319 void kvm_arch_check_processor_compat(void *rtn)
7320 {
7321 kvm_x86_ops->check_processor_compatibility(rtn);
7322 }
7323
7324 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7325 {
7326 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7327 }
7328 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7329
7330 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7331 {
7332 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7333 }
7334
7335 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7336 {
7337 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7338 }
7339
7340 struct static_key kvm_no_apic_vcpu __read_mostly;
7341
7342 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7343 {
7344 struct page *page;
7345 struct kvm *kvm;
7346 int r;
7347
7348 BUG_ON(vcpu->kvm == NULL);
7349 kvm = vcpu->kvm;
7350
7351 vcpu->arch.pv.pv_unhalted = false;
7352 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7353 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7354 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7355 else
7356 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7357
7358 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7359 if (!page) {
7360 r = -ENOMEM;
7361 goto fail;
7362 }
7363 vcpu->arch.pio_data = page_address(page);
7364
7365 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7366
7367 r = kvm_mmu_create(vcpu);
7368 if (r < 0)
7369 goto fail_free_pio_data;
7370
7371 if (irqchip_in_kernel(kvm)) {
7372 r = kvm_create_lapic(vcpu);
7373 if (r < 0)
7374 goto fail_mmu_destroy;
7375 } else
7376 static_key_slow_inc(&kvm_no_apic_vcpu);
7377
7378 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7379 GFP_KERNEL);
7380 if (!vcpu->arch.mce_banks) {
7381 r = -ENOMEM;
7382 goto fail_free_lapic;
7383 }
7384 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7385
7386 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7387 r = -ENOMEM;
7388 goto fail_free_mce_banks;
7389 }
7390
7391 fx_init(vcpu);
7392
7393 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7394 vcpu->arch.pv_time_enabled = false;
7395
7396 vcpu->arch.guest_supported_xcr0 = 0;
7397 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7398
7399 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7400
7401 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7402
7403 kvm_async_pf_hash_reset(vcpu);
7404 kvm_pmu_init(vcpu);
7405
7406 return 0;
7407
7408 fail_free_mce_banks:
7409 kfree(vcpu->arch.mce_banks);
7410 fail_free_lapic:
7411 kvm_free_lapic(vcpu);
7412 fail_mmu_destroy:
7413 kvm_mmu_destroy(vcpu);
7414 fail_free_pio_data:
7415 free_page((unsigned long)vcpu->arch.pio_data);
7416 fail:
7417 return r;
7418 }
7419
7420 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7421 {
7422 int idx;
7423
7424 kvm_pmu_destroy(vcpu);
7425 kfree(vcpu->arch.mce_banks);
7426 kvm_free_lapic(vcpu);
7427 idx = srcu_read_lock(&vcpu->kvm->srcu);
7428 kvm_mmu_destroy(vcpu);
7429 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7430 free_page((unsigned long)vcpu->arch.pio_data);
7431 if (!lapic_in_kernel(vcpu))
7432 static_key_slow_dec(&kvm_no_apic_vcpu);
7433 }
7434
7435 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7436 {
7437 kvm_x86_ops->sched_in(vcpu, cpu);
7438 }
7439
7440 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7441 {
7442 if (type)
7443 return -EINVAL;
7444
7445 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7446 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7447 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7448 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7449 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7450
7451 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7452 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7453 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7454 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7455 &kvm->arch.irq_sources_bitmap);
7456
7457 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7458 mutex_init(&kvm->arch.apic_map_lock);
7459 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7460
7461 pvclock_update_vm_gtod_copy(kvm);
7462
7463 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7464 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7465
7466 return 0;
7467 }
7468
7469 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7470 {
7471 int r;
7472 r = vcpu_load(vcpu);
7473 BUG_ON(r);
7474 kvm_mmu_unload(vcpu);
7475 vcpu_put(vcpu);
7476 }
7477
7478 static void kvm_free_vcpus(struct kvm *kvm)
7479 {
7480 unsigned int i;
7481 struct kvm_vcpu *vcpu;
7482
7483 /*
7484 * Unpin any mmu pages first.
7485 */
7486 kvm_for_each_vcpu(i, vcpu, kvm) {
7487 kvm_clear_async_pf_completion_queue(vcpu);
7488 kvm_unload_vcpu_mmu(vcpu);
7489 }
7490 kvm_for_each_vcpu(i, vcpu, kvm)
7491 kvm_arch_vcpu_free(vcpu);
7492
7493 mutex_lock(&kvm->lock);
7494 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7495 kvm->vcpus[i] = NULL;
7496
7497 atomic_set(&kvm->online_vcpus, 0);
7498 mutex_unlock(&kvm->lock);
7499 }
7500
7501 void kvm_arch_sync_events(struct kvm *kvm)
7502 {
7503 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7504 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7505 kvm_free_all_assigned_devices(kvm);
7506 kvm_free_pit(kvm);
7507 }
7508
7509 int __x86_set_memory_region(struct kvm *kvm,
7510 const struct kvm_userspace_memory_region *mem)
7511 {
7512 int i, r;
7513
7514 /* Called with kvm->slots_lock held. */
7515 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7516
7517 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7518 struct kvm_userspace_memory_region m = *mem;
7519
7520 m.slot |= i << 16;
7521 r = __kvm_set_memory_region(kvm, &m);
7522 if (r < 0)
7523 return r;
7524 }
7525
7526 return 0;
7527 }
7528 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7529
7530 int x86_set_memory_region(struct kvm *kvm,
7531 const struct kvm_userspace_memory_region *mem)
7532 {
7533 int r;
7534
7535 mutex_lock(&kvm->slots_lock);
7536 r = __x86_set_memory_region(kvm, mem);
7537 mutex_unlock(&kvm->slots_lock);
7538
7539 return r;
7540 }
7541 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7542
7543 void kvm_arch_destroy_vm(struct kvm *kvm)
7544 {
7545 if (current->mm == kvm->mm) {
7546 /*
7547 * Free memory regions allocated on behalf of userspace,
7548 * unless the the memory map has changed due to process exit
7549 * or fd copying.
7550 */
7551 struct kvm_userspace_memory_region mem;
7552 memset(&mem, 0, sizeof(mem));
7553 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7554 x86_set_memory_region(kvm, &mem);
7555
7556 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7557 x86_set_memory_region(kvm, &mem);
7558
7559 mem.slot = TSS_PRIVATE_MEMSLOT;
7560 x86_set_memory_region(kvm, &mem);
7561 }
7562 kvm_iommu_unmap_guest(kvm);
7563 kfree(kvm->arch.vpic);
7564 kfree(kvm->arch.vioapic);
7565 kvm_free_vcpus(kvm);
7566 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7567 }
7568
7569 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7570 struct kvm_memory_slot *dont)
7571 {
7572 int i;
7573
7574 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7575 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7576 kvfree(free->arch.rmap[i]);
7577 free->arch.rmap[i] = NULL;
7578 }
7579 if (i == 0)
7580 continue;
7581
7582 if (!dont || free->arch.lpage_info[i - 1] !=
7583 dont->arch.lpage_info[i - 1]) {
7584 kvfree(free->arch.lpage_info[i - 1]);
7585 free->arch.lpage_info[i - 1] = NULL;
7586 }
7587 }
7588 }
7589
7590 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7591 unsigned long npages)
7592 {
7593 int i;
7594
7595 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7596 unsigned long ugfn;
7597 int lpages;
7598 int level = i + 1;
7599
7600 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7601 slot->base_gfn, level) + 1;
7602
7603 slot->arch.rmap[i] =
7604 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7605 if (!slot->arch.rmap[i])
7606 goto out_free;
7607 if (i == 0)
7608 continue;
7609
7610 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7611 sizeof(*slot->arch.lpage_info[i - 1]));
7612 if (!slot->arch.lpage_info[i - 1])
7613 goto out_free;
7614
7615 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7616 slot->arch.lpage_info[i - 1][0].write_count = 1;
7617 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7618 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7619 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7620 /*
7621 * If the gfn and userspace address are not aligned wrt each
7622 * other, or if explicitly asked to, disable large page
7623 * support for this slot
7624 */
7625 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7626 !kvm_largepages_enabled()) {
7627 unsigned long j;
7628
7629 for (j = 0; j < lpages; ++j)
7630 slot->arch.lpage_info[i - 1][j].write_count = 1;
7631 }
7632 }
7633
7634 return 0;
7635
7636 out_free:
7637 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7638 kvfree(slot->arch.rmap[i]);
7639 slot->arch.rmap[i] = NULL;
7640 if (i == 0)
7641 continue;
7642
7643 kvfree(slot->arch.lpage_info[i - 1]);
7644 slot->arch.lpage_info[i - 1] = NULL;
7645 }
7646 return -ENOMEM;
7647 }
7648
7649 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7650 {
7651 /*
7652 * memslots->generation has been incremented.
7653 * mmio generation may have reached its maximum value.
7654 */
7655 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7656 }
7657
7658 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7659 struct kvm_memory_slot *memslot,
7660 const struct kvm_userspace_memory_region *mem,
7661 enum kvm_mr_change change)
7662 {
7663 /*
7664 * Only private memory slots need to be mapped here since
7665 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7666 */
7667 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7668 unsigned long userspace_addr;
7669
7670 /*
7671 * MAP_SHARED to prevent internal slot pages from being moved
7672 * by fork()/COW.
7673 */
7674 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7675 PROT_READ | PROT_WRITE,
7676 MAP_SHARED | MAP_ANONYMOUS, 0);
7677
7678 if (IS_ERR((void *)userspace_addr))
7679 return PTR_ERR((void *)userspace_addr);
7680
7681 memslot->userspace_addr = userspace_addr;
7682 }
7683
7684 return 0;
7685 }
7686
7687 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7688 struct kvm_memory_slot *new)
7689 {
7690 /* Still write protect RO slot */
7691 if (new->flags & KVM_MEM_READONLY) {
7692 kvm_mmu_slot_remove_write_access(kvm, new);
7693 return;
7694 }
7695
7696 /*
7697 * Call kvm_x86_ops dirty logging hooks when they are valid.
7698 *
7699 * kvm_x86_ops->slot_disable_log_dirty is called when:
7700 *
7701 * - KVM_MR_CREATE with dirty logging is disabled
7702 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7703 *
7704 * The reason is, in case of PML, we need to set D-bit for any slots
7705 * with dirty logging disabled in order to eliminate unnecessary GPA
7706 * logging in PML buffer (and potential PML buffer full VMEXT). This
7707 * guarantees leaving PML enabled during guest's lifetime won't have
7708 * any additonal overhead from PML when guest is running with dirty
7709 * logging disabled for memory slots.
7710 *
7711 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7712 * to dirty logging mode.
7713 *
7714 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7715 *
7716 * In case of write protect:
7717 *
7718 * Write protect all pages for dirty logging.
7719 *
7720 * All the sptes including the large sptes which point to this
7721 * slot are set to readonly. We can not create any new large
7722 * spte on this slot until the end of the logging.
7723 *
7724 * See the comments in fast_page_fault().
7725 */
7726 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7727 if (kvm_x86_ops->slot_enable_log_dirty)
7728 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7729 else
7730 kvm_mmu_slot_remove_write_access(kvm, new);
7731 } else {
7732 if (kvm_x86_ops->slot_disable_log_dirty)
7733 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7734 }
7735 }
7736
7737 void kvm_arch_commit_memory_region(struct kvm *kvm,
7738 const struct kvm_userspace_memory_region *mem,
7739 const struct kvm_memory_slot *old,
7740 const struct kvm_memory_slot *new,
7741 enum kvm_mr_change change)
7742 {
7743 int nr_mmu_pages = 0;
7744
7745 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7746 int ret;
7747
7748 ret = vm_munmap(old->userspace_addr,
7749 old->npages * PAGE_SIZE);
7750 if (ret < 0)
7751 printk(KERN_WARNING
7752 "kvm_vm_ioctl_set_memory_region: "
7753 "failed to munmap memory\n");
7754 }
7755
7756 if (!kvm->arch.n_requested_mmu_pages)
7757 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7758
7759 if (nr_mmu_pages)
7760 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7761
7762 /*
7763 * Dirty logging tracks sptes in 4k granularity, meaning that large
7764 * sptes have to be split. If live migration is successful, the guest
7765 * in the source machine will be destroyed and large sptes will be
7766 * created in the destination. However, if the guest continues to run
7767 * in the source machine (for example if live migration fails), small
7768 * sptes will remain around and cause bad performance.
7769 *
7770 * Scan sptes if dirty logging has been stopped, dropping those
7771 * which can be collapsed into a single large-page spte. Later
7772 * page faults will create the large-page sptes.
7773 */
7774 if ((change != KVM_MR_DELETE) &&
7775 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7776 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7777 kvm_mmu_zap_collapsible_sptes(kvm, new);
7778
7779 /*
7780 * Set up write protection and/or dirty logging for the new slot.
7781 *
7782 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7783 * been zapped so no dirty logging staff is needed for old slot. For
7784 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7785 * new and it's also covered when dealing with the new slot.
7786 *
7787 * FIXME: const-ify all uses of struct kvm_memory_slot.
7788 */
7789 if (change != KVM_MR_DELETE)
7790 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7791 }
7792
7793 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7794 {
7795 kvm_mmu_invalidate_zap_all_pages(kvm);
7796 }
7797
7798 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7799 struct kvm_memory_slot *slot)
7800 {
7801 kvm_mmu_invalidate_zap_all_pages(kvm);
7802 }
7803
7804 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7805 {
7806 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7807 kvm_x86_ops->check_nested_events(vcpu, false);
7808
7809 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7810 !vcpu->arch.apf.halted)
7811 || !list_empty_careful(&vcpu->async_pf.done)
7812 || kvm_apic_has_events(vcpu)
7813 || vcpu->arch.pv.pv_unhalted
7814 || atomic_read(&vcpu->arch.nmi_queued) ||
7815 (kvm_arch_interrupt_allowed(vcpu) &&
7816 kvm_cpu_has_interrupt(vcpu));
7817 }
7818
7819 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7820 {
7821 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7822 }
7823
7824 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7825 {
7826 return kvm_x86_ops->interrupt_allowed(vcpu);
7827 }
7828
7829 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7830 {
7831 if (is_64_bit_mode(vcpu))
7832 return kvm_rip_read(vcpu);
7833 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7834 kvm_rip_read(vcpu));
7835 }
7836 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7837
7838 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7839 {
7840 return kvm_get_linear_rip(vcpu) == linear_rip;
7841 }
7842 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7843
7844 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7845 {
7846 unsigned long rflags;
7847
7848 rflags = kvm_x86_ops->get_rflags(vcpu);
7849 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7850 rflags &= ~X86_EFLAGS_TF;
7851 return rflags;
7852 }
7853 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7854
7855 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7856 {
7857 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7858 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7859 rflags |= X86_EFLAGS_TF;
7860 kvm_x86_ops->set_rflags(vcpu, rflags);
7861 }
7862
7863 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7864 {
7865 __kvm_set_rflags(vcpu, rflags);
7866 kvm_make_request(KVM_REQ_EVENT, vcpu);
7867 }
7868 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7869
7870 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7871 {
7872 int r;
7873
7874 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7875 work->wakeup_all)
7876 return;
7877
7878 r = kvm_mmu_reload(vcpu);
7879 if (unlikely(r))
7880 return;
7881
7882 if (!vcpu->arch.mmu.direct_map &&
7883 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7884 return;
7885
7886 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7887 }
7888
7889 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7890 {
7891 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7892 }
7893
7894 static inline u32 kvm_async_pf_next_probe(u32 key)
7895 {
7896 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7897 }
7898
7899 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7900 {
7901 u32 key = kvm_async_pf_hash_fn(gfn);
7902
7903 while (vcpu->arch.apf.gfns[key] != ~0)
7904 key = kvm_async_pf_next_probe(key);
7905
7906 vcpu->arch.apf.gfns[key] = gfn;
7907 }
7908
7909 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7910 {
7911 int i;
7912 u32 key = kvm_async_pf_hash_fn(gfn);
7913
7914 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7915 (vcpu->arch.apf.gfns[key] != gfn &&
7916 vcpu->arch.apf.gfns[key] != ~0); i++)
7917 key = kvm_async_pf_next_probe(key);
7918
7919 return key;
7920 }
7921
7922 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7923 {
7924 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7925 }
7926
7927 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7928 {
7929 u32 i, j, k;
7930
7931 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7932 while (true) {
7933 vcpu->arch.apf.gfns[i] = ~0;
7934 do {
7935 j = kvm_async_pf_next_probe(j);
7936 if (vcpu->arch.apf.gfns[j] == ~0)
7937 return;
7938 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7939 /*
7940 * k lies cyclically in ]i,j]
7941 * | i.k.j |
7942 * |....j i.k.| or |.k..j i...|
7943 */
7944 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7945 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7946 i = j;
7947 }
7948 }
7949
7950 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7951 {
7952
7953 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7954 sizeof(val));
7955 }
7956
7957 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7958 struct kvm_async_pf *work)
7959 {
7960 struct x86_exception fault;
7961
7962 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7963 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7964
7965 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7966 (vcpu->arch.apf.send_user_only &&
7967 kvm_x86_ops->get_cpl(vcpu) == 0))
7968 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7969 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7970 fault.vector = PF_VECTOR;
7971 fault.error_code_valid = true;
7972 fault.error_code = 0;
7973 fault.nested_page_fault = false;
7974 fault.address = work->arch.token;
7975 kvm_inject_page_fault(vcpu, &fault);
7976 }
7977 }
7978
7979 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7980 struct kvm_async_pf *work)
7981 {
7982 struct x86_exception fault;
7983
7984 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7985 if (work->wakeup_all)
7986 work->arch.token = ~0; /* broadcast wakeup */
7987 else
7988 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7989
7990 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7991 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7992 fault.vector = PF_VECTOR;
7993 fault.error_code_valid = true;
7994 fault.error_code = 0;
7995 fault.nested_page_fault = false;
7996 fault.address = work->arch.token;
7997 kvm_inject_page_fault(vcpu, &fault);
7998 }
7999 vcpu->arch.apf.halted = false;
8000 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8001 }
8002
8003 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8004 {
8005 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8006 return true;
8007 else
8008 return !kvm_event_needs_reinjection(vcpu) &&
8009 kvm_x86_ops->interrupt_allowed(vcpu);
8010 }
8011
8012 void kvm_arch_start_assignment(struct kvm *kvm)
8013 {
8014 atomic_inc(&kvm->arch.assigned_device_count);
8015 }
8016 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8017
8018 void kvm_arch_end_assignment(struct kvm *kvm)
8019 {
8020 atomic_dec(&kvm->arch.assigned_device_count);
8021 }
8022 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8023
8024 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8025 {
8026 return atomic_read(&kvm->arch.assigned_device_count);
8027 }
8028 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8029
8030 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8031 {
8032 atomic_inc(&kvm->arch.noncoherent_dma_count);
8033 }
8034 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8035
8036 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8037 {
8038 atomic_dec(&kvm->arch.noncoherent_dma_count);
8039 }
8040 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8041
8042 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8043 {
8044 return atomic_read(&kvm->arch.noncoherent_dma_count);
8045 }
8046 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8047
8048 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8049 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8050 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8051 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8052 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8053 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8054 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8055 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8056 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8057 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8058 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8059 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8060 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8061 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8062 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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