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Merge branch 'for-4.3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <trace/events/kvm.h>
55
56 #define CREATE_TRACE_POINTS
57 #include "trace.h"
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 static bool __read_mostly kvmclock_periodic_sync = true;
103 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
105 bool kvm_has_tsc_control;
106 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107 u32 kvm_max_guest_tsc_khz;
108 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
110 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111 static u32 tsc_tolerance_ppm = 250;
112 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
114 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
115 unsigned int lapic_timer_advance_ns = 0;
116 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
118 static bool backwards_tsc_observed = false;
119
120 #define KVM_NR_SHARED_MSRS 16
121
122 struct kvm_shared_msrs_global {
123 int nr;
124 u32 msrs[KVM_NR_SHARED_MSRS];
125 };
126
127 struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
134 };
135
136 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
137 static struct kvm_shared_msrs __percpu *shared_msrs;
138
139 struct kvm_stats_debugfs_item debugfs_entries[] = {
140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
150 { "halt_exits", VCPU_STAT(halt_exits) },
151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
154 { "hypercalls", VCPU_STAT(hypercalls) },
155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
162 { "irq_injections", VCPU_STAT(irq_injections) },
163 { "nmi_injections", VCPU_STAT(nmi_injections) },
164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
171 { "mmu_unsync", VM_STAT(mmu_unsync) },
172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
173 { "largepages", VM_STAT(lpages) },
174 { NULL }
175 };
176
177 u64 __read_mostly host_xcr0;
178
179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
180
181 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182 {
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186 }
187
188 static void kvm_on_user_return(struct user_return_notifier *urn)
189 {
190 unsigned slot;
191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
193 struct kvm_shared_msr_values *values;
194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204 }
205
206 static void shared_msr_update(unsigned slot, u32 msr)
207 {
208 u64 value;
209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
211
212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221 }
222
223 void kvm_define_shared_msr(unsigned slot, u32 msr)
224 {
225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
226 shared_msrs_global.msrs[slot] = msr;
227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
229 }
230 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232 static void kvm_shared_msr_cpu_online(void)
233 {
234 unsigned i;
235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
237 shared_msr_update(i, shared_msrs_global.msrs[i]);
238 }
239
240 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
241 {
242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
244 int err;
245
246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
247 return 0;
248 smsr->values[slot].curr = value;
249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
258 return 0;
259 }
260 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
262 static void drop_user_return_notifiers(void)
263 {
264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269 }
270
271 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272 {
273 return vcpu->arch.apic_base;
274 }
275 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
277 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278 {
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
297 }
298 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
300 asmlinkage __visible void kvm_spurious_fault(void)
301 {
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304 }
305 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
307 #define EXCPT_BENIGN 0
308 #define EXCPT_CONTRIBUTORY 1
309 #define EXCPT_PF 2
310
311 static int exception_class(int vector)
312 {
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326 }
327
328 #define EXCPT_FAULT 0
329 #define EXCPT_TRAP 1
330 #define EXCPT_ABORT 2
331 #define EXCPT_INTERRUPT 3
332
333 static int exception_type(int vector)
334 {
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351 }
352
353 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
356 {
357 u32 prev_nr;
358 int class1, class2;
359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
362 if (!vcpu->arch.exception.pending) {
363 queue:
364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
370 vcpu->arch.exception.reinject = reinject;
371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395 }
396
397 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398 {
399 kvm_multiple_exception(vcpu, nr, false, 0, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
403 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404 {
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
409 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
410 {
411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415 }
416 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
417
418 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
419 {
420 ++vcpu->stat.pf_guest;
421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
423 }
424 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
425
426 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
430 else
431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
432
433 return fault->nested_page_fault;
434 }
435
436 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437 {
438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
440 }
441 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
443 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444 {
445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
446 }
447 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
449 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450 {
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452 }
453 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
455 /*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
460 {
461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
465 }
466 EXPORT_SYMBOL_GPL(kvm_require_cpl);
467
468 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469 {
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475 }
476 EXPORT_SYMBOL_GPL(kvm_require_dr);
477
478 /*
479 * This function will be used to read from the physical memory of the currently
480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
481 * can read from guest physical or from the guest's guest physical memory.
482 */
483 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486 {
487 struct x86_exception exception;
488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
499 }
500 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
502 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
503 void *data, int offset, int len, u32 access)
504 {
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507 }
508
509 /*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
512 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
513 {
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
519
520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
528 if (is_present_gpte(pdpte[i]) &&
529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
542 out:
543
544 return ret;
545 }
546 EXPORT_SYMBOL_GPL(load_pdptrs);
547
548 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549 {
550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
551 bool changed = true;
552 int offset;
553 gfn_t gfn;
554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
567 if (r < 0)
568 goto out;
569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
570 out:
571
572 return changed;
573 }
574
575 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
576 {
577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
579
580 cr0 |= X86_CR0_ET;
581
582 #ifdef CONFIG_X86_64
583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
585 #endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
588
589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
591
592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596 #ifdef CONFIG_X86_64
597 if ((vcpu->arch.efer & EFER_LME)) {
598 int cs_db, cs_l;
599
600 if (!is_pae(vcpu))
601 return 1;
602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
603 if (cs_l)
604 return 1;
605 } else
606 #endif
607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
608 kvm_read_cr3(vcpu)))
609 return 1;
610 }
611
612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
615 kvm_x86_ops->set_cr0(vcpu, cr0);
616
617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
618 kvm_clear_async_pf_completion_queue(vcpu);
619 kvm_async_pf_hash_reset(vcpu);
620 }
621
622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
628 return 0;
629 }
630 EXPORT_SYMBOL_GPL(kvm_set_cr0);
631
632 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
633 {
634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
635 }
636 EXPORT_SYMBOL_GPL(kvm_lmsw);
637
638 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639 {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646 }
647
648 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655 }
656
657 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
658 {
659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
661 u64 valid_bits;
662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
678 return 1;
679
680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
689 kvm_put_guest_xcr0(vcpu);
690 vcpu->arch.xcr0 = xcr0;
691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
694 return 0;
695 }
696
697 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698 {
699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705 }
706 EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
708 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
709 {
710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
716
717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
727 return 1;
728
729 if (is_long_mode(vcpu)) {
730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
736 return 1;
737
738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
748 return 1;
749
750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
752 kvm_mmu_reset_context(vcpu);
753
754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
755 kvm_update_cpuid(vcpu);
756
757 return 0;
758 }
759 EXPORT_SYMBOL_GPL(kvm_set_cr4);
760
761 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
762 {
763 #ifdef CONFIG_X86_64
764 cr3 &= ~CR3_PCID_INVD;
765 #endif
766
767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
768 kvm_mmu_sync_roots(vcpu);
769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
770 return 0;
771 }
772
773 if (is_long_mode(vcpu)) {
774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
778 return 1;
779
780 vcpu->arch.cr3 = cr3;
781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
782 kvm_mmu_new_cr3(vcpu);
783 return 0;
784 }
785 EXPORT_SYMBOL_GPL(kvm_set_cr3);
786
787 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
788 {
789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
791 if (irqchip_in_kernel(vcpu->kvm))
792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
794 vcpu->arch.cr8 = cr8;
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_set_cr8);
798
799 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
800 {
801 if (irqchip_in_kernel(vcpu->kvm))
802 return kvm_lapic_get_cr8(vcpu);
803 else
804 return vcpu->arch.cr8;
805 }
806 EXPORT_SYMBOL_GPL(kvm_get_cr8);
807
808 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809 {
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817 }
818
819 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820 {
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823 }
824
825 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826 {
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
837 }
838
839 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840 {
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846 }
847
848 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
849 {
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
857 /* fall through */
858 case 6:
859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
862 kvm_update_dr6(vcpu);
863 break;
864 case 5:
865 /* fall through */
866 default: /* 7 */
867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
870 kvm_update_dr7(vcpu);
871 break;
872 }
873
874 return 0;
875 }
876
877 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878 {
879 if (__kvm_set_dr(vcpu, dr, val)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884 }
885 EXPORT_SYMBOL_GPL(kvm_set_dr);
886
887 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
888 {
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
894 /* fall through */
895 case 6:
896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
900 break;
901 case 5:
902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(kvm_get_dr);
910
911 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912 {
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923 }
924 EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
926 /*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
931 * capabilities of the host cpu. This capabilities test skips MSRs that are
932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
934 */
935
936 static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
938 MSR_STAR,
939 #ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 #endif
942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
944 };
945
946 static unsigned num_msrs_to_save;
947
948 static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
955 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
956 MSR_KVM_PV_EOI_EN,
957
958 MSR_IA32_TSC_ADJUST,
959 MSR_IA32_TSCDEADLINE,
960 MSR_IA32_MISC_ENABLE,
961 MSR_IA32_MCG_STATUS,
962 MSR_IA32_MCG_CTL,
963 MSR_IA32_SMBASE,
964 };
965
966 static unsigned num_emulated_msrs;
967
968 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
969 {
970 if (efer & efer_reserved_bits)
971 return false;
972
973 if (efer & EFER_FFXSR) {
974 struct kvm_cpuid_entry2 *feat;
975
976 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
977 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
978 return false;
979 }
980
981 if (efer & EFER_SVME) {
982 struct kvm_cpuid_entry2 *feat;
983
984 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
985 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
986 return false;
987 }
988
989 return true;
990 }
991 EXPORT_SYMBOL_GPL(kvm_valid_efer);
992
993 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
994 {
995 u64 old_efer = vcpu->arch.efer;
996
997 if (!kvm_valid_efer(vcpu, efer))
998 return 1;
999
1000 if (is_paging(vcpu)
1001 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1002 return 1;
1003
1004 efer &= ~EFER_LMA;
1005 efer |= vcpu->arch.efer & EFER_LMA;
1006
1007 kvm_x86_ops->set_efer(vcpu, efer);
1008
1009 /* Update reserved bits */
1010 if ((efer ^ old_efer) & EFER_NX)
1011 kvm_mmu_reset_context(vcpu);
1012
1013 return 0;
1014 }
1015
1016 void kvm_enable_efer_bits(u64 mask)
1017 {
1018 efer_reserved_bits &= ~mask;
1019 }
1020 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1021
1022 /*
1023 * Writes msr value into into the appropriate "register".
1024 * Returns 0 on success, non-0 otherwise.
1025 * Assumes vcpu_load() was already called.
1026 */
1027 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1028 {
1029 switch (msr->index) {
1030 case MSR_FS_BASE:
1031 case MSR_GS_BASE:
1032 case MSR_KERNEL_GS_BASE:
1033 case MSR_CSTAR:
1034 case MSR_LSTAR:
1035 if (is_noncanonical_address(msr->data))
1036 return 1;
1037 break;
1038 case MSR_IA32_SYSENTER_EIP:
1039 case MSR_IA32_SYSENTER_ESP:
1040 /*
1041 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1042 * non-canonical address is written on Intel but not on
1043 * AMD (which ignores the top 32-bits, because it does
1044 * not implement 64-bit SYSENTER).
1045 *
1046 * 64-bit code should hence be able to write a non-canonical
1047 * value on AMD. Making the address canonical ensures that
1048 * vmentry does not fail on Intel after writing a non-canonical
1049 * value, and that something deterministic happens if the guest
1050 * invokes 64-bit SYSENTER.
1051 */
1052 msr->data = get_canonical(msr->data);
1053 }
1054 return kvm_x86_ops->set_msr(vcpu, msr);
1055 }
1056 EXPORT_SYMBOL_GPL(kvm_set_msr);
1057
1058 /*
1059 * Adapt set_msr() to msr_io()'s calling convention
1060 */
1061 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1062 {
1063 struct msr_data msr;
1064 int r;
1065
1066 msr.index = index;
1067 msr.host_initiated = true;
1068 r = kvm_get_msr(vcpu, &msr);
1069 if (r)
1070 return r;
1071
1072 *data = msr.data;
1073 return 0;
1074 }
1075
1076 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1077 {
1078 struct msr_data msr;
1079
1080 msr.data = *data;
1081 msr.index = index;
1082 msr.host_initiated = true;
1083 return kvm_set_msr(vcpu, &msr);
1084 }
1085
1086 #ifdef CONFIG_X86_64
1087 struct pvclock_gtod_data {
1088 seqcount_t seq;
1089
1090 struct { /* extract of a clocksource struct */
1091 int vclock_mode;
1092 cycle_t cycle_last;
1093 cycle_t mask;
1094 u32 mult;
1095 u32 shift;
1096 } clock;
1097
1098 u64 boot_ns;
1099 u64 nsec_base;
1100 };
1101
1102 static struct pvclock_gtod_data pvclock_gtod_data;
1103
1104 static void update_pvclock_gtod(struct timekeeper *tk)
1105 {
1106 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1107 u64 boot_ns;
1108
1109 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1110
1111 write_seqcount_begin(&vdata->seq);
1112
1113 /* copy pvclock gtod data */
1114 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1115 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1116 vdata->clock.mask = tk->tkr_mono.mask;
1117 vdata->clock.mult = tk->tkr_mono.mult;
1118 vdata->clock.shift = tk->tkr_mono.shift;
1119
1120 vdata->boot_ns = boot_ns;
1121 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1122
1123 write_seqcount_end(&vdata->seq);
1124 }
1125 #endif
1126
1127 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1128 {
1129 /*
1130 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1131 * vcpu_enter_guest. This function is only called from
1132 * the physical CPU that is running vcpu.
1133 */
1134 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1135 }
1136
1137 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1138 {
1139 int version;
1140 int r;
1141 struct pvclock_wall_clock wc;
1142 struct timespec boot;
1143
1144 if (!wall_clock)
1145 return;
1146
1147 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1148 if (r)
1149 return;
1150
1151 if (version & 1)
1152 ++version; /* first time write, random junk */
1153
1154 ++version;
1155
1156 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1157
1158 /*
1159 * The guest calculates current wall clock time by adding
1160 * system time (updated by kvm_guest_time_update below) to the
1161 * wall clock specified here. guest system time equals host
1162 * system time for us, thus we must fill in host boot time here.
1163 */
1164 getboottime(&boot);
1165
1166 if (kvm->arch.kvmclock_offset) {
1167 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1168 boot = timespec_sub(boot, ts);
1169 }
1170 wc.sec = boot.tv_sec;
1171 wc.nsec = boot.tv_nsec;
1172 wc.version = version;
1173
1174 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1175
1176 version++;
1177 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1178 }
1179
1180 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1181 {
1182 uint32_t quotient, remainder;
1183
1184 /* Don't try to replace with do_div(), this one calculates
1185 * "(dividend << 32) / divisor" */
1186 __asm__ ( "divl %4"
1187 : "=a" (quotient), "=d" (remainder)
1188 : "0" (0), "1" (dividend), "r" (divisor) );
1189 return quotient;
1190 }
1191
1192 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1193 s8 *pshift, u32 *pmultiplier)
1194 {
1195 uint64_t scaled64;
1196 int32_t shift = 0;
1197 uint64_t tps64;
1198 uint32_t tps32;
1199
1200 tps64 = base_khz * 1000LL;
1201 scaled64 = scaled_khz * 1000LL;
1202 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1203 tps64 >>= 1;
1204 shift--;
1205 }
1206
1207 tps32 = (uint32_t)tps64;
1208 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1209 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1210 scaled64 >>= 1;
1211 else
1212 tps32 <<= 1;
1213 shift++;
1214 }
1215
1216 *pshift = shift;
1217 *pmultiplier = div_frac(scaled64, tps32);
1218
1219 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1220 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1221 }
1222
1223 #ifdef CONFIG_X86_64
1224 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1225 #endif
1226
1227 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1228 static unsigned long max_tsc_khz;
1229
1230 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1231 {
1232 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1233 vcpu->arch.virtual_tsc_shift);
1234 }
1235
1236 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1237 {
1238 u64 v = (u64)khz * (1000000 + ppm);
1239 do_div(v, 1000000);
1240 return v;
1241 }
1242
1243 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1244 {
1245 u32 thresh_lo, thresh_hi;
1246 int use_scaling = 0;
1247
1248 /* tsc_khz can be zero if TSC calibration fails */
1249 if (this_tsc_khz == 0)
1250 return;
1251
1252 /* Compute a scale to convert nanoseconds in TSC cycles */
1253 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1254 &vcpu->arch.virtual_tsc_shift,
1255 &vcpu->arch.virtual_tsc_mult);
1256 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1257
1258 /*
1259 * Compute the variation in TSC rate which is acceptable
1260 * within the range of tolerance and decide if the
1261 * rate being applied is within that bounds of the hardware
1262 * rate. If so, no scaling or compensation need be done.
1263 */
1264 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1265 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1266 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1267 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1268 use_scaling = 1;
1269 }
1270 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1271 }
1272
1273 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1274 {
1275 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1276 vcpu->arch.virtual_tsc_mult,
1277 vcpu->arch.virtual_tsc_shift);
1278 tsc += vcpu->arch.this_tsc_write;
1279 return tsc;
1280 }
1281
1282 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1283 {
1284 #ifdef CONFIG_X86_64
1285 bool vcpus_matched;
1286 struct kvm_arch *ka = &vcpu->kvm->arch;
1287 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1288
1289 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1290 atomic_read(&vcpu->kvm->online_vcpus));
1291
1292 /*
1293 * Once the masterclock is enabled, always perform request in
1294 * order to update it.
1295 *
1296 * In order to enable masterclock, the host clocksource must be TSC
1297 * and the vcpus need to have matched TSCs. When that happens,
1298 * perform request to enable masterclock.
1299 */
1300 if (ka->use_master_clock ||
1301 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1302 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1303
1304 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1305 atomic_read(&vcpu->kvm->online_vcpus),
1306 ka->use_master_clock, gtod->clock.vclock_mode);
1307 #endif
1308 }
1309
1310 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1311 {
1312 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1313 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1314 }
1315
1316 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1317 {
1318 struct kvm *kvm = vcpu->kvm;
1319 u64 offset, ns, elapsed;
1320 unsigned long flags;
1321 s64 usdiff;
1322 bool matched;
1323 bool already_matched;
1324 u64 data = msr->data;
1325
1326 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1327 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1328 ns = get_kernel_ns();
1329 elapsed = ns - kvm->arch.last_tsc_nsec;
1330
1331 if (vcpu->arch.virtual_tsc_khz) {
1332 int faulted = 0;
1333
1334 /* n.b - signed multiplication and division required */
1335 usdiff = data - kvm->arch.last_tsc_write;
1336 #ifdef CONFIG_X86_64
1337 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1338 #else
1339 /* do_div() only does unsigned */
1340 asm("1: idivl %[divisor]\n"
1341 "2: xor %%edx, %%edx\n"
1342 " movl $0, %[faulted]\n"
1343 "3:\n"
1344 ".section .fixup,\"ax\"\n"
1345 "4: movl $1, %[faulted]\n"
1346 " jmp 3b\n"
1347 ".previous\n"
1348
1349 _ASM_EXTABLE(1b, 4b)
1350
1351 : "=A"(usdiff), [faulted] "=r" (faulted)
1352 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1353
1354 #endif
1355 do_div(elapsed, 1000);
1356 usdiff -= elapsed;
1357 if (usdiff < 0)
1358 usdiff = -usdiff;
1359
1360 /* idivl overflow => difference is larger than USEC_PER_SEC */
1361 if (faulted)
1362 usdiff = USEC_PER_SEC;
1363 } else
1364 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1365
1366 /*
1367 * Special case: TSC write with a small delta (1 second) of virtual
1368 * cycle time against real time is interpreted as an attempt to
1369 * synchronize the CPU.
1370 *
1371 * For a reliable TSC, we can match TSC offsets, and for an unstable
1372 * TSC, we add elapsed time in this computation. We could let the
1373 * compensation code attempt to catch up if we fall behind, but
1374 * it's better to try to match offsets from the beginning.
1375 */
1376 if (usdiff < USEC_PER_SEC &&
1377 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1378 if (!check_tsc_unstable()) {
1379 offset = kvm->arch.cur_tsc_offset;
1380 pr_debug("kvm: matched tsc offset for %llu\n", data);
1381 } else {
1382 u64 delta = nsec_to_cycles(vcpu, elapsed);
1383 data += delta;
1384 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1385 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1386 }
1387 matched = true;
1388 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1389 } else {
1390 /*
1391 * We split periods of matched TSC writes into generations.
1392 * For each generation, we track the original measured
1393 * nanosecond time, offset, and write, so if TSCs are in
1394 * sync, we can match exact offset, and if not, we can match
1395 * exact software computation in compute_guest_tsc()
1396 *
1397 * These values are tracked in kvm->arch.cur_xxx variables.
1398 */
1399 kvm->arch.cur_tsc_generation++;
1400 kvm->arch.cur_tsc_nsec = ns;
1401 kvm->arch.cur_tsc_write = data;
1402 kvm->arch.cur_tsc_offset = offset;
1403 matched = false;
1404 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1405 kvm->arch.cur_tsc_generation, data);
1406 }
1407
1408 /*
1409 * We also track th most recent recorded KHZ, write and time to
1410 * allow the matching interval to be extended at each write.
1411 */
1412 kvm->arch.last_tsc_nsec = ns;
1413 kvm->arch.last_tsc_write = data;
1414 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1415
1416 vcpu->arch.last_guest_tsc = data;
1417
1418 /* Keep track of which generation this VCPU has synchronized to */
1419 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1420 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1421 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1422
1423 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1424 update_ia32_tsc_adjust_msr(vcpu, offset);
1425 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1426 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1427
1428 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1429 if (!matched) {
1430 kvm->arch.nr_vcpus_matched_tsc = 0;
1431 } else if (!already_matched) {
1432 kvm->arch.nr_vcpus_matched_tsc++;
1433 }
1434
1435 kvm_track_tsc_matching(vcpu);
1436 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1437 }
1438
1439 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1440
1441 #ifdef CONFIG_X86_64
1442
1443 static cycle_t read_tsc(void)
1444 {
1445 cycle_t ret = (cycle_t)rdtsc_ordered();
1446 u64 last = pvclock_gtod_data.clock.cycle_last;
1447
1448 if (likely(ret >= last))
1449 return ret;
1450
1451 /*
1452 * GCC likes to generate cmov here, but this branch is extremely
1453 * predictable (it's just a funciton of time and the likely is
1454 * very likely) and there's a data dependence, so force GCC
1455 * to generate a branch instead. I don't barrier() because
1456 * we don't actually need a barrier, and if this function
1457 * ever gets inlined it will generate worse code.
1458 */
1459 asm volatile ("");
1460 return last;
1461 }
1462
1463 static inline u64 vgettsc(cycle_t *cycle_now)
1464 {
1465 long v;
1466 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1467
1468 *cycle_now = read_tsc();
1469
1470 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1471 return v * gtod->clock.mult;
1472 }
1473
1474 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1475 {
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477 unsigned long seq;
1478 int mode;
1479 u64 ns;
1480
1481 do {
1482 seq = read_seqcount_begin(&gtod->seq);
1483 mode = gtod->clock.vclock_mode;
1484 ns = gtod->nsec_base;
1485 ns += vgettsc(cycle_now);
1486 ns >>= gtod->clock.shift;
1487 ns += gtod->boot_ns;
1488 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1489 *t = ns;
1490
1491 return mode;
1492 }
1493
1494 /* returns true if host is using tsc clocksource */
1495 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1496 {
1497 /* checked again under seqlock below */
1498 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1499 return false;
1500
1501 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1502 }
1503 #endif
1504
1505 /*
1506 *
1507 * Assuming a stable TSC across physical CPUS, and a stable TSC
1508 * across virtual CPUs, the following condition is possible.
1509 * Each numbered line represents an event visible to both
1510 * CPUs at the next numbered event.
1511 *
1512 * "timespecX" represents host monotonic time. "tscX" represents
1513 * RDTSC value.
1514 *
1515 * VCPU0 on CPU0 | VCPU1 on CPU1
1516 *
1517 * 1. read timespec0,tsc0
1518 * 2. | timespec1 = timespec0 + N
1519 * | tsc1 = tsc0 + M
1520 * 3. transition to guest | transition to guest
1521 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1522 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1523 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1524 *
1525 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1526 *
1527 * - ret0 < ret1
1528 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1529 * ...
1530 * - 0 < N - M => M < N
1531 *
1532 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1533 * always the case (the difference between two distinct xtime instances
1534 * might be smaller then the difference between corresponding TSC reads,
1535 * when updating guest vcpus pvclock areas).
1536 *
1537 * To avoid that problem, do not allow visibility of distinct
1538 * system_timestamp/tsc_timestamp values simultaneously: use a master
1539 * copy of host monotonic time values. Update that master copy
1540 * in lockstep.
1541 *
1542 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1543 *
1544 */
1545
1546 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1547 {
1548 #ifdef CONFIG_X86_64
1549 struct kvm_arch *ka = &kvm->arch;
1550 int vclock_mode;
1551 bool host_tsc_clocksource, vcpus_matched;
1552
1553 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1554 atomic_read(&kvm->online_vcpus));
1555
1556 /*
1557 * If the host uses TSC clock, then passthrough TSC as stable
1558 * to the guest.
1559 */
1560 host_tsc_clocksource = kvm_get_time_and_clockread(
1561 &ka->master_kernel_ns,
1562 &ka->master_cycle_now);
1563
1564 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1565 && !backwards_tsc_observed
1566 && !ka->boot_vcpu_runs_old_kvmclock;
1567
1568 if (ka->use_master_clock)
1569 atomic_set(&kvm_guest_has_master_clock, 1);
1570
1571 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1572 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1573 vcpus_matched);
1574 #endif
1575 }
1576
1577 static void kvm_gen_update_masterclock(struct kvm *kvm)
1578 {
1579 #ifdef CONFIG_X86_64
1580 int i;
1581 struct kvm_vcpu *vcpu;
1582 struct kvm_arch *ka = &kvm->arch;
1583
1584 spin_lock(&ka->pvclock_gtod_sync_lock);
1585 kvm_make_mclock_inprogress_request(kvm);
1586 /* no guest entries from this point */
1587 pvclock_update_vm_gtod_copy(kvm);
1588
1589 kvm_for_each_vcpu(i, vcpu, kvm)
1590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1591
1592 /* guest entries allowed */
1593 kvm_for_each_vcpu(i, vcpu, kvm)
1594 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1595
1596 spin_unlock(&ka->pvclock_gtod_sync_lock);
1597 #endif
1598 }
1599
1600 static int kvm_guest_time_update(struct kvm_vcpu *v)
1601 {
1602 unsigned long flags, this_tsc_khz;
1603 struct kvm_vcpu_arch *vcpu = &v->arch;
1604 struct kvm_arch *ka = &v->kvm->arch;
1605 s64 kernel_ns;
1606 u64 tsc_timestamp, host_tsc;
1607 struct pvclock_vcpu_time_info guest_hv_clock;
1608 u8 pvclock_flags;
1609 bool use_master_clock;
1610
1611 kernel_ns = 0;
1612 host_tsc = 0;
1613
1614 /*
1615 * If the host uses TSC clock, then passthrough TSC as stable
1616 * to the guest.
1617 */
1618 spin_lock(&ka->pvclock_gtod_sync_lock);
1619 use_master_clock = ka->use_master_clock;
1620 if (use_master_clock) {
1621 host_tsc = ka->master_cycle_now;
1622 kernel_ns = ka->master_kernel_ns;
1623 }
1624 spin_unlock(&ka->pvclock_gtod_sync_lock);
1625
1626 /* Keep irq disabled to prevent changes to the clock */
1627 local_irq_save(flags);
1628 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1629 if (unlikely(this_tsc_khz == 0)) {
1630 local_irq_restore(flags);
1631 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1632 return 1;
1633 }
1634 if (!use_master_clock) {
1635 host_tsc = rdtsc();
1636 kernel_ns = get_kernel_ns();
1637 }
1638
1639 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1640
1641 /*
1642 * We may have to catch up the TSC to match elapsed wall clock
1643 * time for two reasons, even if kvmclock is used.
1644 * 1) CPU could have been running below the maximum TSC rate
1645 * 2) Broken TSC compensation resets the base at each VCPU
1646 * entry to avoid unknown leaps of TSC even when running
1647 * again on the same CPU. This may cause apparent elapsed
1648 * time to disappear, and the guest to stand still or run
1649 * very slowly.
1650 */
1651 if (vcpu->tsc_catchup) {
1652 u64 tsc = compute_guest_tsc(v, kernel_ns);
1653 if (tsc > tsc_timestamp) {
1654 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1655 tsc_timestamp = tsc;
1656 }
1657 }
1658
1659 local_irq_restore(flags);
1660
1661 if (!vcpu->pv_time_enabled)
1662 return 0;
1663
1664 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1665 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1666 &vcpu->hv_clock.tsc_shift,
1667 &vcpu->hv_clock.tsc_to_system_mul);
1668 vcpu->hw_tsc_khz = this_tsc_khz;
1669 }
1670
1671 /* With all the info we got, fill in the values */
1672 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1673 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1674 vcpu->last_guest_tsc = tsc_timestamp;
1675
1676 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1677 &guest_hv_clock, sizeof(guest_hv_clock))))
1678 return 0;
1679
1680 /* This VCPU is paused, but it's legal for a guest to read another
1681 * VCPU's kvmclock, so we really have to follow the specification where
1682 * it says that version is odd if data is being modified, and even after
1683 * it is consistent.
1684 *
1685 * Version field updates must be kept separate. This is because
1686 * kvm_write_guest_cached might use a "rep movs" instruction, and
1687 * writes within a string instruction are weakly ordered. So there
1688 * are three writes overall.
1689 *
1690 * As a small optimization, only write the version field in the first
1691 * and third write. The vcpu->pv_time cache is still valid, because the
1692 * version field is the first in the struct.
1693 */
1694 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1695
1696 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1697 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1698 &vcpu->hv_clock,
1699 sizeof(vcpu->hv_clock.version));
1700
1701 smp_wmb();
1702
1703 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1704 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1705
1706 if (vcpu->pvclock_set_guest_stopped_request) {
1707 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1708 vcpu->pvclock_set_guest_stopped_request = false;
1709 }
1710
1711 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1712
1713 /* If the host uses TSC clocksource, then it is stable */
1714 if (use_master_clock)
1715 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1716
1717 vcpu->hv_clock.flags = pvclock_flags;
1718
1719 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1720
1721 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1722 &vcpu->hv_clock,
1723 sizeof(vcpu->hv_clock));
1724
1725 smp_wmb();
1726
1727 vcpu->hv_clock.version++;
1728 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1729 &vcpu->hv_clock,
1730 sizeof(vcpu->hv_clock.version));
1731 return 0;
1732 }
1733
1734 /*
1735 * kvmclock updates which are isolated to a given vcpu, such as
1736 * vcpu->cpu migration, should not allow system_timestamp from
1737 * the rest of the vcpus to remain static. Otherwise ntp frequency
1738 * correction applies to one vcpu's system_timestamp but not
1739 * the others.
1740 *
1741 * So in those cases, request a kvmclock update for all vcpus.
1742 * We need to rate-limit these requests though, as they can
1743 * considerably slow guests that have a large number of vcpus.
1744 * The time for a remote vcpu to update its kvmclock is bound
1745 * by the delay we use to rate-limit the updates.
1746 */
1747
1748 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1749
1750 static void kvmclock_update_fn(struct work_struct *work)
1751 {
1752 int i;
1753 struct delayed_work *dwork = to_delayed_work(work);
1754 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1755 kvmclock_update_work);
1756 struct kvm *kvm = container_of(ka, struct kvm, arch);
1757 struct kvm_vcpu *vcpu;
1758
1759 kvm_for_each_vcpu(i, vcpu, kvm) {
1760 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1761 kvm_vcpu_kick(vcpu);
1762 }
1763 }
1764
1765 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1766 {
1767 struct kvm *kvm = v->kvm;
1768
1769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1771 KVMCLOCK_UPDATE_DELAY);
1772 }
1773
1774 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1775
1776 static void kvmclock_sync_fn(struct work_struct *work)
1777 {
1778 struct delayed_work *dwork = to_delayed_work(work);
1779 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1780 kvmclock_sync_work);
1781 struct kvm *kvm = container_of(ka, struct kvm, arch);
1782
1783 if (!kvmclock_periodic_sync)
1784 return;
1785
1786 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1787 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1788 KVMCLOCK_SYNC_PERIOD);
1789 }
1790
1791 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1792 {
1793 u64 mcg_cap = vcpu->arch.mcg_cap;
1794 unsigned bank_num = mcg_cap & 0xff;
1795
1796 switch (msr) {
1797 case MSR_IA32_MCG_STATUS:
1798 vcpu->arch.mcg_status = data;
1799 break;
1800 case MSR_IA32_MCG_CTL:
1801 if (!(mcg_cap & MCG_CTL_P))
1802 return 1;
1803 if (data != 0 && data != ~(u64)0)
1804 return -1;
1805 vcpu->arch.mcg_ctl = data;
1806 break;
1807 default:
1808 if (msr >= MSR_IA32_MC0_CTL &&
1809 msr < MSR_IA32_MCx_CTL(bank_num)) {
1810 u32 offset = msr - MSR_IA32_MC0_CTL;
1811 /* only 0 or all 1s can be written to IA32_MCi_CTL
1812 * some Linux kernels though clear bit 10 in bank 4 to
1813 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1814 * this to avoid an uncatched #GP in the guest
1815 */
1816 if ((offset & 0x3) == 0 &&
1817 data != 0 && (data | (1 << 10)) != ~(u64)0)
1818 return -1;
1819 vcpu->arch.mce_banks[offset] = data;
1820 break;
1821 }
1822 return 1;
1823 }
1824 return 0;
1825 }
1826
1827 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1828 {
1829 struct kvm *kvm = vcpu->kvm;
1830 int lm = is_long_mode(vcpu);
1831 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1832 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1833 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1834 : kvm->arch.xen_hvm_config.blob_size_32;
1835 u32 page_num = data & ~PAGE_MASK;
1836 u64 page_addr = data & PAGE_MASK;
1837 u8 *page;
1838 int r;
1839
1840 r = -E2BIG;
1841 if (page_num >= blob_size)
1842 goto out;
1843 r = -ENOMEM;
1844 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1845 if (IS_ERR(page)) {
1846 r = PTR_ERR(page);
1847 goto out;
1848 }
1849 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1850 goto out_free;
1851 r = 0;
1852 out_free:
1853 kfree(page);
1854 out:
1855 return r;
1856 }
1857
1858 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1859 {
1860 gpa_t gpa = data & ~0x3f;
1861
1862 /* Bits 2:5 are reserved, Should be zero */
1863 if (data & 0x3c)
1864 return 1;
1865
1866 vcpu->arch.apf.msr_val = data;
1867
1868 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1869 kvm_clear_async_pf_completion_queue(vcpu);
1870 kvm_async_pf_hash_reset(vcpu);
1871 return 0;
1872 }
1873
1874 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1875 sizeof(u32)))
1876 return 1;
1877
1878 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1879 kvm_async_pf_wakeup_all(vcpu);
1880 return 0;
1881 }
1882
1883 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1884 {
1885 vcpu->arch.pv_time_enabled = false;
1886 }
1887
1888 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1889 {
1890 u64 delta;
1891
1892 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1893 return;
1894
1895 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1896 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1897 vcpu->arch.st.accum_steal = delta;
1898 }
1899
1900 static void record_steal_time(struct kvm_vcpu *vcpu)
1901 {
1902 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1903 return;
1904
1905 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1906 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1907 return;
1908
1909 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1910 vcpu->arch.st.steal.version += 2;
1911 vcpu->arch.st.accum_steal = 0;
1912
1913 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1914 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1915 }
1916
1917 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1918 {
1919 bool pr = false;
1920 u32 msr = msr_info->index;
1921 u64 data = msr_info->data;
1922
1923 switch (msr) {
1924 case MSR_AMD64_NB_CFG:
1925 case MSR_IA32_UCODE_REV:
1926 case MSR_IA32_UCODE_WRITE:
1927 case MSR_VM_HSAVE_PA:
1928 case MSR_AMD64_PATCH_LOADER:
1929 case MSR_AMD64_BU_CFG2:
1930 break;
1931
1932 case MSR_EFER:
1933 return set_efer(vcpu, data);
1934 case MSR_K7_HWCR:
1935 data &= ~(u64)0x40; /* ignore flush filter disable */
1936 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1937 data &= ~(u64)0x8; /* ignore TLB cache disable */
1938 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1939 if (data != 0) {
1940 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1941 data);
1942 return 1;
1943 }
1944 break;
1945 case MSR_FAM10H_MMIO_CONF_BASE:
1946 if (data != 0) {
1947 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1948 "0x%llx\n", data);
1949 return 1;
1950 }
1951 break;
1952 case MSR_IA32_DEBUGCTLMSR:
1953 if (!data) {
1954 /* We support the non-activated case already */
1955 break;
1956 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1957 /* Values other than LBR and BTF are vendor-specific,
1958 thus reserved and should throw a #GP */
1959 return 1;
1960 }
1961 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1962 __func__, data);
1963 break;
1964 case 0x200 ... 0x2ff:
1965 return kvm_mtrr_set_msr(vcpu, msr, data);
1966 case MSR_IA32_APICBASE:
1967 return kvm_set_apic_base(vcpu, msr_info);
1968 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1969 return kvm_x2apic_msr_write(vcpu, msr, data);
1970 case MSR_IA32_TSCDEADLINE:
1971 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1972 break;
1973 case MSR_IA32_TSC_ADJUST:
1974 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1975 if (!msr_info->host_initiated) {
1976 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1977 adjust_tsc_offset_guest(vcpu, adj);
1978 }
1979 vcpu->arch.ia32_tsc_adjust_msr = data;
1980 }
1981 break;
1982 case MSR_IA32_MISC_ENABLE:
1983 vcpu->arch.ia32_misc_enable_msr = data;
1984 break;
1985 case MSR_IA32_SMBASE:
1986 if (!msr_info->host_initiated)
1987 return 1;
1988 vcpu->arch.smbase = data;
1989 break;
1990 case MSR_KVM_WALL_CLOCK_NEW:
1991 case MSR_KVM_WALL_CLOCK:
1992 vcpu->kvm->arch.wall_clock = data;
1993 kvm_write_wall_clock(vcpu->kvm, data);
1994 break;
1995 case MSR_KVM_SYSTEM_TIME_NEW:
1996 case MSR_KVM_SYSTEM_TIME: {
1997 u64 gpa_offset;
1998 struct kvm_arch *ka = &vcpu->kvm->arch;
1999
2000 kvmclock_reset(vcpu);
2001
2002 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2003 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2004
2005 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2006 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2007 &vcpu->requests);
2008
2009 ka->boot_vcpu_runs_old_kvmclock = tmp;
2010
2011 ka->kvmclock_offset = -get_kernel_ns();
2012 }
2013
2014 vcpu->arch.time = data;
2015 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2016
2017 /* we verify if the enable bit is set... */
2018 if (!(data & 1))
2019 break;
2020
2021 gpa_offset = data & ~(PAGE_MASK | 1);
2022
2023 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2024 &vcpu->arch.pv_time, data & ~1ULL,
2025 sizeof(struct pvclock_vcpu_time_info)))
2026 vcpu->arch.pv_time_enabled = false;
2027 else
2028 vcpu->arch.pv_time_enabled = true;
2029
2030 break;
2031 }
2032 case MSR_KVM_ASYNC_PF_EN:
2033 if (kvm_pv_enable_async_pf(vcpu, data))
2034 return 1;
2035 break;
2036 case MSR_KVM_STEAL_TIME:
2037
2038 if (unlikely(!sched_info_on()))
2039 return 1;
2040
2041 if (data & KVM_STEAL_RESERVED_MASK)
2042 return 1;
2043
2044 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2045 data & KVM_STEAL_VALID_BITS,
2046 sizeof(struct kvm_steal_time)))
2047 return 1;
2048
2049 vcpu->arch.st.msr_val = data;
2050
2051 if (!(data & KVM_MSR_ENABLED))
2052 break;
2053
2054 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2055
2056 preempt_disable();
2057 accumulate_steal_time(vcpu);
2058 preempt_enable();
2059
2060 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2061
2062 break;
2063 case MSR_KVM_PV_EOI_EN:
2064 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2065 return 1;
2066 break;
2067
2068 case MSR_IA32_MCG_CTL:
2069 case MSR_IA32_MCG_STATUS:
2070 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2071 return set_msr_mce(vcpu, msr, data);
2072
2073 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2074 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2075 pr = true; /* fall through */
2076 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2077 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2078 if (kvm_pmu_is_valid_msr(vcpu, msr))
2079 return kvm_pmu_set_msr(vcpu, msr_info);
2080
2081 if (pr || data != 0)
2082 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2083 "0x%x data 0x%llx\n", msr, data);
2084 break;
2085 case MSR_K7_CLK_CTL:
2086 /*
2087 * Ignore all writes to this no longer documented MSR.
2088 * Writes are only relevant for old K7 processors,
2089 * all pre-dating SVM, but a recommended workaround from
2090 * AMD for these chips. It is possible to specify the
2091 * affected processor models on the command line, hence
2092 * the need to ignore the workaround.
2093 */
2094 break;
2095 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2096 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2097 case HV_X64_MSR_CRASH_CTL:
2098 return kvm_hv_set_msr_common(vcpu, msr, data,
2099 msr_info->host_initiated);
2100 case MSR_IA32_BBL_CR_CTL3:
2101 /* Drop writes to this legacy MSR -- see rdmsr
2102 * counterpart for further detail.
2103 */
2104 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2105 break;
2106 case MSR_AMD64_OSVW_ID_LENGTH:
2107 if (!guest_cpuid_has_osvw(vcpu))
2108 return 1;
2109 vcpu->arch.osvw.length = data;
2110 break;
2111 case MSR_AMD64_OSVW_STATUS:
2112 if (!guest_cpuid_has_osvw(vcpu))
2113 return 1;
2114 vcpu->arch.osvw.status = data;
2115 break;
2116 default:
2117 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2118 return xen_hvm_config(vcpu, data);
2119 if (kvm_pmu_is_valid_msr(vcpu, msr))
2120 return kvm_pmu_set_msr(vcpu, msr_info);
2121 if (!ignore_msrs) {
2122 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2123 msr, data);
2124 return 1;
2125 } else {
2126 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2127 msr, data);
2128 break;
2129 }
2130 }
2131 return 0;
2132 }
2133 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2134
2135
2136 /*
2137 * Reads an msr value (of 'msr_index') into 'pdata'.
2138 * Returns 0 on success, non-0 otherwise.
2139 * Assumes vcpu_load() was already called.
2140 */
2141 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2142 {
2143 return kvm_x86_ops->get_msr(vcpu, msr);
2144 }
2145 EXPORT_SYMBOL_GPL(kvm_get_msr);
2146
2147 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2148 {
2149 u64 data;
2150 u64 mcg_cap = vcpu->arch.mcg_cap;
2151 unsigned bank_num = mcg_cap & 0xff;
2152
2153 switch (msr) {
2154 case MSR_IA32_P5_MC_ADDR:
2155 case MSR_IA32_P5_MC_TYPE:
2156 data = 0;
2157 break;
2158 case MSR_IA32_MCG_CAP:
2159 data = vcpu->arch.mcg_cap;
2160 break;
2161 case MSR_IA32_MCG_CTL:
2162 if (!(mcg_cap & MCG_CTL_P))
2163 return 1;
2164 data = vcpu->arch.mcg_ctl;
2165 break;
2166 case MSR_IA32_MCG_STATUS:
2167 data = vcpu->arch.mcg_status;
2168 break;
2169 default:
2170 if (msr >= MSR_IA32_MC0_CTL &&
2171 msr < MSR_IA32_MCx_CTL(bank_num)) {
2172 u32 offset = msr - MSR_IA32_MC0_CTL;
2173 data = vcpu->arch.mce_banks[offset];
2174 break;
2175 }
2176 return 1;
2177 }
2178 *pdata = data;
2179 return 0;
2180 }
2181
2182 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2183 {
2184 switch (msr_info->index) {
2185 case MSR_IA32_PLATFORM_ID:
2186 case MSR_IA32_EBL_CR_POWERON:
2187 case MSR_IA32_DEBUGCTLMSR:
2188 case MSR_IA32_LASTBRANCHFROMIP:
2189 case MSR_IA32_LASTBRANCHTOIP:
2190 case MSR_IA32_LASTINTFROMIP:
2191 case MSR_IA32_LASTINTTOIP:
2192 case MSR_K8_SYSCFG:
2193 case MSR_K7_HWCR:
2194 case MSR_VM_HSAVE_PA:
2195 case MSR_K8_INT_PENDING_MSG:
2196 case MSR_AMD64_NB_CFG:
2197 case MSR_FAM10H_MMIO_CONF_BASE:
2198 case MSR_AMD64_BU_CFG2:
2199 msr_info->data = 0;
2200 break;
2201 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2202 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2203 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2204 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2205 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2206 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2207 msr_info->data = 0;
2208 break;
2209 case MSR_IA32_UCODE_REV:
2210 msr_info->data = 0x100000000ULL;
2211 break;
2212 case MSR_MTRRcap:
2213 case 0x200 ... 0x2ff:
2214 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2215 case 0xcd: /* fsb frequency */
2216 msr_info->data = 3;
2217 break;
2218 /*
2219 * MSR_EBC_FREQUENCY_ID
2220 * Conservative value valid for even the basic CPU models.
2221 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2222 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2223 * and 266MHz for model 3, or 4. Set Core Clock
2224 * Frequency to System Bus Frequency Ratio to 1 (bits
2225 * 31:24) even though these are only valid for CPU
2226 * models > 2, however guests may end up dividing or
2227 * multiplying by zero otherwise.
2228 */
2229 case MSR_EBC_FREQUENCY_ID:
2230 msr_info->data = 1 << 24;
2231 break;
2232 case MSR_IA32_APICBASE:
2233 msr_info->data = kvm_get_apic_base(vcpu);
2234 break;
2235 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2236 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2237 break;
2238 case MSR_IA32_TSCDEADLINE:
2239 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2240 break;
2241 case MSR_IA32_TSC_ADJUST:
2242 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2243 break;
2244 case MSR_IA32_MISC_ENABLE:
2245 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2246 break;
2247 case MSR_IA32_SMBASE:
2248 if (!msr_info->host_initiated)
2249 return 1;
2250 msr_info->data = vcpu->arch.smbase;
2251 break;
2252 case MSR_IA32_PERF_STATUS:
2253 /* TSC increment by tick */
2254 msr_info->data = 1000ULL;
2255 /* CPU multiplier */
2256 msr_info->data |= (((uint64_t)4ULL) << 40);
2257 break;
2258 case MSR_EFER:
2259 msr_info->data = vcpu->arch.efer;
2260 break;
2261 case MSR_KVM_WALL_CLOCK:
2262 case MSR_KVM_WALL_CLOCK_NEW:
2263 msr_info->data = vcpu->kvm->arch.wall_clock;
2264 break;
2265 case MSR_KVM_SYSTEM_TIME:
2266 case MSR_KVM_SYSTEM_TIME_NEW:
2267 msr_info->data = vcpu->arch.time;
2268 break;
2269 case MSR_KVM_ASYNC_PF_EN:
2270 msr_info->data = vcpu->arch.apf.msr_val;
2271 break;
2272 case MSR_KVM_STEAL_TIME:
2273 msr_info->data = vcpu->arch.st.msr_val;
2274 break;
2275 case MSR_KVM_PV_EOI_EN:
2276 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2277 break;
2278 case MSR_IA32_P5_MC_ADDR:
2279 case MSR_IA32_P5_MC_TYPE:
2280 case MSR_IA32_MCG_CAP:
2281 case MSR_IA32_MCG_CTL:
2282 case MSR_IA32_MCG_STATUS:
2283 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2284 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2285 case MSR_K7_CLK_CTL:
2286 /*
2287 * Provide expected ramp-up count for K7. All other
2288 * are set to zero, indicating minimum divisors for
2289 * every field.
2290 *
2291 * This prevents guest kernels on AMD host with CPU
2292 * type 6, model 8 and higher from exploding due to
2293 * the rdmsr failing.
2294 */
2295 msr_info->data = 0x20000000;
2296 break;
2297 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 case HV_X64_MSR_CRASH_CTL:
2300 return kvm_hv_get_msr_common(vcpu,
2301 msr_info->index, &msr_info->data);
2302 break;
2303 case MSR_IA32_BBL_CR_CTL3:
2304 /* This legacy MSR exists but isn't fully documented in current
2305 * silicon. It is however accessed by winxp in very narrow
2306 * scenarios where it sets bit #19, itself documented as
2307 * a "reserved" bit. Best effort attempt to source coherent
2308 * read data here should the balance of the register be
2309 * interpreted by the guest:
2310 *
2311 * L2 cache control register 3: 64GB range, 256KB size,
2312 * enabled, latency 0x1, configured
2313 */
2314 msr_info->data = 0xbe702111;
2315 break;
2316 case MSR_AMD64_OSVW_ID_LENGTH:
2317 if (!guest_cpuid_has_osvw(vcpu))
2318 return 1;
2319 msr_info->data = vcpu->arch.osvw.length;
2320 break;
2321 case MSR_AMD64_OSVW_STATUS:
2322 if (!guest_cpuid_has_osvw(vcpu))
2323 return 1;
2324 msr_info->data = vcpu->arch.osvw.status;
2325 break;
2326 default:
2327 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2328 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2329 if (!ignore_msrs) {
2330 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2331 return 1;
2332 } else {
2333 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2334 msr_info->data = 0;
2335 }
2336 break;
2337 }
2338 return 0;
2339 }
2340 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2341
2342 /*
2343 * Read or write a bunch of msrs. All parameters are kernel addresses.
2344 *
2345 * @return number of msrs set successfully.
2346 */
2347 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2348 struct kvm_msr_entry *entries,
2349 int (*do_msr)(struct kvm_vcpu *vcpu,
2350 unsigned index, u64 *data))
2351 {
2352 int i, idx;
2353
2354 idx = srcu_read_lock(&vcpu->kvm->srcu);
2355 for (i = 0; i < msrs->nmsrs; ++i)
2356 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2357 break;
2358 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2359
2360 return i;
2361 }
2362
2363 /*
2364 * Read or write a bunch of msrs. Parameters are user addresses.
2365 *
2366 * @return number of msrs set successfully.
2367 */
2368 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2369 int (*do_msr)(struct kvm_vcpu *vcpu,
2370 unsigned index, u64 *data),
2371 int writeback)
2372 {
2373 struct kvm_msrs msrs;
2374 struct kvm_msr_entry *entries;
2375 int r, n;
2376 unsigned size;
2377
2378 r = -EFAULT;
2379 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2380 goto out;
2381
2382 r = -E2BIG;
2383 if (msrs.nmsrs >= MAX_IO_MSRS)
2384 goto out;
2385
2386 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2387 entries = memdup_user(user_msrs->entries, size);
2388 if (IS_ERR(entries)) {
2389 r = PTR_ERR(entries);
2390 goto out;
2391 }
2392
2393 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2394 if (r < 0)
2395 goto out_free;
2396
2397 r = -EFAULT;
2398 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2399 goto out_free;
2400
2401 r = n;
2402
2403 out_free:
2404 kfree(entries);
2405 out:
2406 return r;
2407 }
2408
2409 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2410 {
2411 int r;
2412
2413 switch (ext) {
2414 case KVM_CAP_IRQCHIP:
2415 case KVM_CAP_HLT:
2416 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2417 case KVM_CAP_SET_TSS_ADDR:
2418 case KVM_CAP_EXT_CPUID:
2419 case KVM_CAP_EXT_EMUL_CPUID:
2420 case KVM_CAP_CLOCKSOURCE:
2421 case KVM_CAP_PIT:
2422 case KVM_CAP_NOP_IO_DELAY:
2423 case KVM_CAP_MP_STATE:
2424 case KVM_CAP_SYNC_MMU:
2425 case KVM_CAP_USER_NMI:
2426 case KVM_CAP_REINJECT_CONTROL:
2427 case KVM_CAP_IRQ_INJECT_STATUS:
2428 case KVM_CAP_IOEVENTFD:
2429 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2430 case KVM_CAP_PIT2:
2431 case KVM_CAP_PIT_STATE2:
2432 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2433 case KVM_CAP_XEN_HVM:
2434 case KVM_CAP_ADJUST_CLOCK:
2435 case KVM_CAP_VCPU_EVENTS:
2436 case KVM_CAP_HYPERV:
2437 case KVM_CAP_HYPERV_VAPIC:
2438 case KVM_CAP_HYPERV_SPIN:
2439 case KVM_CAP_PCI_SEGMENT:
2440 case KVM_CAP_DEBUGREGS:
2441 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2442 case KVM_CAP_XSAVE:
2443 case KVM_CAP_ASYNC_PF:
2444 case KVM_CAP_GET_TSC_KHZ:
2445 case KVM_CAP_KVMCLOCK_CTRL:
2446 case KVM_CAP_READONLY_MEM:
2447 case KVM_CAP_HYPERV_TIME:
2448 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2449 case KVM_CAP_TSC_DEADLINE_TIMER:
2450 case KVM_CAP_ENABLE_CAP_VM:
2451 case KVM_CAP_DISABLE_QUIRKS:
2452 case KVM_CAP_SET_BOOT_CPU_ID:
2453 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2454 case KVM_CAP_ASSIGN_DEV_IRQ:
2455 case KVM_CAP_PCI_2_3:
2456 #endif
2457 r = 1;
2458 break;
2459 case KVM_CAP_X86_SMM:
2460 /* SMBASE is usually relocated above 1M on modern chipsets,
2461 * and SMM handlers might indeed rely on 4G segment limits,
2462 * so do not report SMM to be available if real mode is
2463 * emulated via vm86 mode. Still, do not go to great lengths
2464 * to avoid userspace's usage of the feature, because it is a
2465 * fringe case that is not enabled except via specific settings
2466 * of the module parameters.
2467 */
2468 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2469 break;
2470 case KVM_CAP_COALESCED_MMIO:
2471 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2472 break;
2473 case KVM_CAP_VAPIC:
2474 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2475 break;
2476 case KVM_CAP_NR_VCPUS:
2477 r = KVM_SOFT_MAX_VCPUS;
2478 break;
2479 case KVM_CAP_MAX_VCPUS:
2480 r = KVM_MAX_VCPUS;
2481 break;
2482 case KVM_CAP_NR_MEMSLOTS:
2483 r = KVM_USER_MEM_SLOTS;
2484 break;
2485 case KVM_CAP_PV_MMU: /* obsolete */
2486 r = 0;
2487 break;
2488 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2489 case KVM_CAP_IOMMU:
2490 r = iommu_present(&pci_bus_type);
2491 break;
2492 #endif
2493 case KVM_CAP_MCE:
2494 r = KVM_MAX_MCE_BANKS;
2495 break;
2496 case KVM_CAP_XCRS:
2497 r = cpu_has_xsave;
2498 break;
2499 case KVM_CAP_TSC_CONTROL:
2500 r = kvm_has_tsc_control;
2501 break;
2502 default:
2503 r = 0;
2504 break;
2505 }
2506 return r;
2507
2508 }
2509
2510 long kvm_arch_dev_ioctl(struct file *filp,
2511 unsigned int ioctl, unsigned long arg)
2512 {
2513 void __user *argp = (void __user *)arg;
2514 long r;
2515
2516 switch (ioctl) {
2517 case KVM_GET_MSR_INDEX_LIST: {
2518 struct kvm_msr_list __user *user_msr_list = argp;
2519 struct kvm_msr_list msr_list;
2520 unsigned n;
2521
2522 r = -EFAULT;
2523 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2524 goto out;
2525 n = msr_list.nmsrs;
2526 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2527 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2528 goto out;
2529 r = -E2BIG;
2530 if (n < msr_list.nmsrs)
2531 goto out;
2532 r = -EFAULT;
2533 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2534 num_msrs_to_save * sizeof(u32)))
2535 goto out;
2536 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2537 &emulated_msrs,
2538 num_emulated_msrs * sizeof(u32)))
2539 goto out;
2540 r = 0;
2541 break;
2542 }
2543 case KVM_GET_SUPPORTED_CPUID:
2544 case KVM_GET_EMULATED_CPUID: {
2545 struct kvm_cpuid2 __user *cpuid_arg = argp;
2546 struct kvm_cpuid2 cpuid;
2547
2548 r = -EFAULT;
2549 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2550 goto out;
2551
2552 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2553 ioctl);
2554 if (r)
2555 goto out;
2556
2557 r = -EFAULT;
2558 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2559 goto out;
2560 r = 0;
2561 break;
2562 }
2563 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2564 u64 mce_cap;
2565
2566 mce_cap = KVM_MCE_CAP_SUPPORTED;
2567 r = -EFAULT;
2568 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2569 goto out;
2570 r = 0;
2571 break;
2572 }
2573 default:
2574 r = -EINVAL;
2575 }
2576 out:
2577 return r;
2578 }
2579
2580 static void wbinvd_ipi(void *garbage)
2581 {
2582 wbinvd();
2583 }
2584
2585 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2586 {
2587 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2588 }
2589
2590 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2591 {
2592 /* Address WBINVD may be executed by guest */
2593 if (need_emulate_wbinvd(vcpu)) {
2594 if (kvm_x86_ops->has_wbinvd_exit())
2595 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2596 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2597 smp_call_function_single(vcpu->cpu,
2598 wbinvd_ipi, NULL, 1);
2599 }
2600
2601 kvm_x86_ops->vcpu_load(vcpu, cpu);
2602
2603 /* Apply any externally detected TSC adjustments (due to suspend) */
2604 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2605 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2606 vcpu->arch.tsc_offset_adjustment = 0;
2607 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2608 }
2609
2610 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2611 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2612 rdtsc() - vcpu->arch.last_host_tsc;
2613 if (tsc_delta < 0)
2614 mark_tsc_unstable("KVM discovered backwards TSC");
2615 if (check_tsc_unstable()) {
2616 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2617 vcpu->arch.last_guest_tsc);
2618 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2619 vcpu->arch.tsc_catchup = 1;
2620 }
2621 /*
2622 * On a host with synchronized TSC, there is no need to update
2623 * kvmclock on vcpu->cpu migration
2624 */
2625 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2626 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2627 if (vcpu->cpu != cpu)
2628 kvm_migrate_timers(vcpu);
2629 vcpu->cpu = cpu;
2630 }
2631
2632 accumulate_steal_time(vcpu);
2633 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2634 }
2635
2636 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2637 {
2638 kvm_x86_ops->vcpu_put(vcpu);
2639 kvm_put_guest_fpu(vcpu);
2640 vcpu->arch.last_host_tsc = rdtsc();
2641 }
2642
2643 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2644 struct kvm_lapic_state *s)
2645 {
2646 kvm_x86_ops->sync_pir_to_irr(vcpu);
2647 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2648
2649 return 0;
2650 }
2651
2652 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2653 struct kvm_lapic_state *s)
2654 {
2655 kvm_apic_post_state_restore(vcpu, s);
2656 update_cr8_intercept(vcpu);
2657
2658 return 0;
2659 }
2660
2661 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2662 struct kvm_interrupt *irq)
2663 {
2664 if (irq->irq >= KVM_NR_INTERRUPTS)
2665 return -EINVAL;
2666 if (irqchip_in_kernel(vcpu->kvm))
2667 return -ENXIO;
2668
2669 kvm_queue_interrupt(vcpu, irq->irq, false);
2670 kvm_make_request(KVM_REQ_EVENT, vcpu);
2671
2672 return 0;
2673 }
2674
2675 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2676 {
2677 kvm_inject_nmi(vcpu);
2678
2679 return 0;
2680 }
2681
2682 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2683 {
2684 kvm_make_request(KVM_REQ_SMI, vcpu);
2685
2686 return 0;
2687 }
2688
2689 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2690 struct kvm_tpr_access_ctl *tac)
2691 {
2692 if (tac->flags)
2693 return -EINVAL;
2694 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2695 return 0;
2696 }
2697
2698 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2699 u64 mcg_cap)
2700 {
2701 int r;
2702 unsigned bank_num = mcg_cap & 0xff, bank;
2703
2704 r = -EINVAL;
2705 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2706 goto out;
2707 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2708 goto out;
2709 r = 0;
2710 vcpu->arch.mcg_cap = mcg_cap;
2711 /* Init IA32_MCG_CTL to all 1s */
2712 if (mcg_cap & MCG_CTL_P)
2713 vcpu->arch.mcg_ctl = ~(u64)0;
2714 /* Init IA32_MCi_CTL to all 1s */
2715 for (bank = 0; bank < bank_num; bank++)
2716 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2717 out:
2718 return r;
2719 }
2720
2721 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2722 struct kvm_x86_mce *mce)
2723 {
2724 u64 mcg_cap = vcpu->arch.mcg_cap;
2725 unsigned bank_num = mcg_cap & 0xff;
2726 u64 *banks = vcpu->arch.mce_banks;
2727
2728 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2729 return -EINVAL;
2730 /*
2731 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2732 * reporting is disabled
2733 */
2734 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2735 vcpu->arch.mcg_ctl != ~(u64)0)
2736 return 0;
2737 banks += 4 * mce->bank;
2738 /*
2739 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2740 * reporting is disabled for the bank
2741 */
2742 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2743 return 0;
2744 if (mce->status & MCI_STATUS_UC) {
2745 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2746 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2747 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2748 return 0;
2749 }
2750 if (banks[1] & MCI_STATUS_VAL)
2751 mce->status |= MCI_STATUS_OVER;
2752 banks[2] = mce->addr;
2753 banks[3] = mce->misc;
2754 vcpu->arch.mcg_status = mce->mcg_status;
2755 banks[1] = mce->status;
2756 kvm_queue_exception(vcpu, MC_VECTOR);
2757 } else if (!(banks[1] & MCI_STATUS_VAL)
2758 || !(banks[1] & MCI_STATUS_UC)) {
2759 if (banks[1] & MCI_STATUS_VAL)
2760 mce->status |= MCI_STATUS_OVER;
2761 banks[2] = mce->addr;
2762 banks[3] = mce->misc;
2763 banks[1] = mce->status;
2764 } else
2765 banks[1] |= MCI_STATUS_OVER;
2766 return 0;
2767 }
2768
2769 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2770 struct kvm_vcpu_events *events)
2771 {
2772 process_nmi(vcpu);
2773 events->exception.injected =
2774 vcpu->arch.exception.pending &&
2775 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2776 events->exception.nr = vcpu->arch.exception.nr;
2777 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2778 events->exception.pad = 0;
2779 events->exception.error_code = vcpu->arch.exception.error_code;
2780
2781 events->interrupt.injected =
2782 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2783 events->interrupt.nr = vcpu->arch.interrupt.nr;
2784 events->interrupt.soft = 0;
2785 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2786
2787 events->nmi.injected = vcpu->arch.nmi_injected;
2788 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2789 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2790 events->nmi.pad = 0;
2791
2792 events->sipi_vector = 0; /* never valid when reporting to user space */
2793
2794 events->smi.smm = is_smm(vcpu);
2795 events->smi.pending = vcpu->arch.smi_pending;
2796 events->smi.smm_inside_nmi =
2797 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2798 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2799
2800 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2801 | KVM_VCPUEVENT_VALID_SHADOW
2802 | KVM_VCPUEVENT_VALID_SMM);
2803 memset(&events->reserved, 0, sizeof(events->reserved));
2804 }
2805
2806 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2807 struct kvm_vcpu_events *events)
2808 {
2809 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2810 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2811 | KVM_VCPUEVENT_VALID_SHADOW
2812 | KVM_VCPUEVENT_VALID_SMM))
2813 return -EINVAL;
2814
2815 process_nmi(vcpu);
2816 vcpu->arch.exception.pending = events->exception.injected;
2817 vcpu->arch.exception.nr = events->exception.nr;
2818 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2819 vcpu->arch.exception.error_code = events->exception.error_code;
2820
2821 vcpu->arch.interrupt.pending = events->interrupt.injected;
2822 vcpu->arch.interrupt.nr = events->interrupt.nr;
2823 vcpu->arch.interrupt.soft = events->interrupt.soft;
2824 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2825 kvm_x86_ops->set_interrupt_shadow(vcpu,
2826 events->interrupt.shadow);
2827
2828 vcpu->arch.nmi_injected = events->nmi.injected;
2829 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2830 vcpu->arch.nmi_pending = events->nmi.pending;
2831 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2832
2833 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2834 kvm_vcpu_has_lapic(vcpu))
2835 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2836
2837 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2838 if (events->smi.smm)
2839 vcpu->arch.hflags |= HF_SMM_MASK;
2840 else
2841 vcpu->arch.hflags &= ~HF_SMM_MASK;
2842 vcpu->arch.smi_pending = events->smi.pending;
2843 if (events->smi.smm_inside_nmi)
2844 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2845 else
2846 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2847 if (kvm_vcpu_has_lapic(vcpu)) {
2848 if (events->smi.latched_init)
2849 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2850 else
2851 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2852 }
2853 }
2854
2855 kvm_make_request(KVM_REQ_EVENT, vcpu);
2856
2857 return 0;
2858 }
2859
2860 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2861 struct kvm_debugregs *dbgregs)
2862 {
2863 unsigned long val;
2864
2865 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2866 kvm_get_dr(vcpu, 6, &val);
2867 dbgregs->dr6 = val;
2868 dbgregs->dr7 = vcpu->arch.dr7;
2869 dbgregs->flags = 0;
2870 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2871 }
2872
2873 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2874 struct kvm_debugregs *dbgregs)
2875 {
2876 if (dbgregs->flags)
2877 return -EINVAL;
2878
2879 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2880 kvm_update_dr0123(vcpu);
2881 vcpu->arch.dr6 = dbgregs->dr6;
2882 kvm_update_dr6(vcpu);
2883 vcpu->arch.dr7 = dbgregs->dr7;
2884 kvm_update_dr7(vcpu);
2885
2886 return 0;
2887 }
2888
2889 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2890
2891 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2892 {
2893 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2894 u64 xstate_bv = xsave->header.xfeatures;
2895 u64 valid;
2896
2897 /*
2898 * Copy legacy XSAVE area, to avoid complications with CPUID
2899 * leaves 0 and 1 in the loop below.
2900 */
2901 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2902
2903 /* Set XSTATE_BV */
2904 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2905
2906 /*
2907 * Copy each region from the possibly compacted offset to the
2908 * non-compacted offset.
2909 */
2910 valid = xstate_bv & ~XSTATE_FPSSE;
2911 while (valid) {
2912 u64 feature = valid & -valid;
2913 int index = fls64(feature) - 1;
2914 void *src = get_xsave_addr(xsave, feature);
2915
2916 if (src) {
2917 u32 size, offset, ecx, edx;
2918 cpuid_count(XSTATE_CPUID, index,
2919 &size, &offset, &ecx, &edx);
2920 memcpy(dest + offset, src, size);
2921 }
2922
2923 valid -= feature;
2924 }
2925 }
2926
2927 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2928 {
2929 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2930 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2931 u64 valid;
2932
2933 /*
2934 * Copy legacy XSAVE area, to avoid complications with CPUID
2935 * leaves 0 and 1 in the loop below.
2936 */
2937 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2938
2939 /* Set XSTATE_BV and possibly XCOMP_BV. */
2940 xsave->header.xfeatures = xstate_bv;
2941 if (cpu_has_xsaves)
2942 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2943
2944 /*
2945 * Copy each region from the non-compacted offset to the
2946 * possibly compacted offset.
2947 */
2948 valid = xstate_bv & ~XSTATE_FPSSE;
2949 while (valid) {
2950 u64 feature = valid & -valid;
2951 int index = fls64(feature) - 1;
2952 void *dest = get_xsave_addr(xsave, feature);
2953
2954 if (dest) {
2955 u32 size, offset, ecx, edx;
2956 cpuid_count(XSTATE_CPUID, index,
2957 &size, &offset, &ecx, &edx);
2958 memcpy(dest, src + offset, size);
2959 }
2960
2961 valid -= feature;
2962 }
2963 }
2964
2965 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2966 struct kvm_xsave *guest_xsave)
2967 {
2968 if (cpu_has_xsave) {
2969 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2970 fill_xsave((u8 *) guest_xsave->region, vcpu);
2971 } else {
2972 memcpy(guest_xsave->region,
2973 &vcpu->arch.guest_fpu.state.fxsave,
2974 sizeof(struct fxregs_state));
2975 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2976 XSTATE_FPSSE;
2977 }
2978 }
2979
2980 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2981 struct kvm_xsave *guest_xsave)
2982 {
2983 u64 xstate_bv =
2984 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2985
2986 if (cpu_has_xsave) {
2987 /*
2988 * Here we allow setting states that are not present in
2989 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
2990 * with old userspace.
2991 */
2992 if (xstate_bv & ~kvm_supported_xcr0())
2993 return -EINVAL;
2994 load_xsave(vcpu, (u8 *)guest_xsave->region);
2995 } else {
2996 if (xstate_bv & ~XSTATE_FPSSE)
2997 return -EINVAL;
2998 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
2999 guest_xsave->region, sizeof(struct fxregs_state));
3000 }
3001 return 0;
3002 }
3003
3004 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3005 struct kvm_xcrs *guest_xcrs)
3006 {
3007 if (!cpu_has_xsave) {
3008 guest_xcrs->nr_xcrs = 0;
3009 return;
3010 }
3011
3012 guest_xcrs->nr_xcrs = 1;
3013 guest_xcrs->flags = 0;
3014 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3015 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3016 }
3017
3018 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3019 struct kvm_xcrs *guest_xcrs)
3020 {
3021 int i, r = 0;
3022
3023 if (!cpu_has_xsave)
3024 return -EINVAL;
3025
3026 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3027 return -EINVAL;
3028
3029 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3030 /* Only support XCR0 currently */
3031 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3032 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3033 guest_xcrs->xcrs[i].value);
3034 break;
3035 }
3036 if (r)
3037 r = -EINVAL;
3038 return r;
3039 }
3040
3041 /*
3042 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3043 * stopped by the hypervisor. This function will be called from the host only.
3044 * EINVAL is returned when the host attempts to set the flag for a guest that
3045 * does not support pv clocks.
3046 */
3047 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3048 {
3049 if (!vcpu->arch.pv_time_enabled)
3050 return -EINVAL;
3051 vcpu->arch.pvclock_set_guest_stopped_request = true;
3052 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3053 return 0;
3054 }
3055
3056 long kvm_arch_vcpu_ioctl(struct file *filp,
3057 unsigned int ioctl, unsigned long arg)
3058 {
3059 struct kvm_vcpu *vcpu = filp->private_data;
3060 void __user *argp = (void __user *)arg;
3061 int r;
3062 union {
3063 struct kvm_lapic_state *lapic;
3064 struct kvm_xsave *xsave;
3065 struct kvm_xcrs *xcrs;
3066 void *buffer;
3067 } u;
3068
3069 u.buffer = NULL;
3070 switch (ioctl) {
3071 case KVM_GET_LAPIC: {
3072 r = -EINVAL;
3073 if (!vcpu->arch.apic)
3074 goto out;
3075 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3076
3077 r = -ENOMEM;
3078 if (!u.lapic)
3079 goto out;
3080 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3081 if (r)
3082 goto out;
3083 r = -EFAULT;
3084 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3085 goto out;
3086 r = 0;
3087 break;
3088 }
3089 case KVM_SET_LAPIC: {
3090 r = -EINVAL;
3091 if (!vcpu->arch.apic)
3092 goto out;
3093 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3094 if (IS_ERR(u.lapic))
3095 return PTR_ERR(u.lapic);
3096
3097 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3098 break;
3099 }
3100 case KVM_INTERRUPT: {
3101 struct kvm_interrupt irq;
3102
3103 r = -EFAULT;
3104 if (copy_from_user(&irq, argp, sizeof irq))
3105 goto out;
3106 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3107 break;
3108 }
3109 case KVM_NMI: {
3110 r = kvm_vcpu_ioctl_nmi(vcpu);
3111 break;
3112 }
3113 case KVM_SMI: {
3114 r = kvm_vcpu_ioctl_smi(vcpu);
3115 break;
3116 }
3117 case KVM_SET_CPUID: {
3118 struct kvm_cpuid __user *cpuid_arg = argp;
3119 struct kvm_cpuid cpuid;
3120
3121 r = -EFAULT;
3122 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3123 goto out;
3124 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3125 break;
3126 }
3127 case KVM_SET_CPUID2: {
3128 struct kvm_cpuid2 __user *cpuid_arg = argp;
3129 struct kvm_cpuid2 cpuid;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3133 goto out;
3134 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3135 cpuid_arg->entries);
3136 break;
3137 }
3138 case KVM_GET_CPUID2: {
3139 struct kvm_cpuid2 __user *cpuid_arg = argp;
3140 struct kvm_cpuid2 cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3146 cpuid_arg->entries);
3147 if (r)
3148 goto out;
3149 r = -EFAULT;
3150 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3151 goto out;
3152 r = 0;
3153 break;
3154 }
3155 case KVM_GET_MSRS:
3156 r = msr_io(vcpu, argp, do_get_msr, 1);
3157 break;
3158 case KVM_SET_MSRS:
3159 r = msr_io(vcpu, argp, do_set_msr, 0);
3160 break;
3161 case KVM_TPR_ACCESS_REPORTING: {
3162 struct kvm_tpr_access_ctl tac;
3163
3164 r = -EFAULT;
3165 if (copy_from_user(&tac, argp, sizeof tac))
3166 goto out;
3167 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3168 if (r)
3169 goto out;
3170 r = -EFAULT;
3171 if (copy_to_user(argp, &tac, sizeof tac))
3172 goto out;
3173 r = 0;
3174 break;
3175 };
3176 case KVM_SET_VAPIC_ADDR: {
3177 struct kvm_vapic_addr va;
3178
3179 r = -EINVAL;
3180 if (!irqchip_in_kernel(vcpu->kvm))
3181 goto out;
3182 r = -EFAULT;
3183 if (copy_from_user(&va, argp, sizeof va))
3184 goto out;
3185 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3186 break;
3187 }
3188 case KVM_X86_SETUP_MCE: {
3189 u64 mcg_cap;
3190
3191 r = -EFAULT;
3192 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3193 goto out;
3194 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3195 break;
3196 }
3197 case KVM_X86_SET_MCE: {
3198 struct kvm_x86_mce mce;
3199
3200 r = -EFAULT;
3201 if (copy_from_user(&mce, argp, sizeof mce))
3202 goto out;
3203 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3204 break;
3205 }
3206 case KVM_GET_VCPU_EVENTS: {
3207 struct kvm_vcpu_events events;
3208
3209 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3210
3211 r = -EFAULT;
3212 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3213 break;
3214 r = 0;
3215 break;
3216 }
3217 case KVM_SET_VCPU_EVENTS: {
3218 struct kvm_vcpu_events events;
3219
3220 r = -EFAULT;
3221 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3222 break;
3223
3224 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3225 break;
3226 }
3227 case KVM_GET_DEBUGREGS: {
3228 struct kvm_debugregs dbgregs;
3229
3230 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3231
3232 r = -EFAULT;
3233 if (copy_to_user(argp, &dbgregs,
3234 sizeof(struct kvm_debugregs)))
3235 break;
3236 r = 0;
3237 break;
3238 }
3239 case KVM_SET_DEBUGREGS: {
3240 struct kvm_debugregs dbgregs;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&dbgregs, argp,
3244 sizeof(struct kvm_debugregs)))
3245 break;
3246
3247 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3248 break;
3249 }
3250 case KVM_GET_XSAVE: {
3251 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3252 r = -ENOMEM;
3253 if (!u.xsave)
3254 break;
3255
3256 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3257
3258 r = -EFAULT;
3259 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3260 break;
3261 r = 0;
3262 break;
3263 }
3264 case KVM_SET_XSAVE: {
3265 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3266 if (IS_ERR(u.xsave))
3267 return PTR_ERR(u.xsave);
3268
3269 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3270 break;
3271 }
3272 case KVM_GET_XCRS: {
3273 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3274 r = -ENOMEM;
3275 if (!u.xcrs)
3276 break;
3277
3278 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3279
3280 r = -EFAULT;
3281 if (copy_to_user(argp, u.xcrs,
3282 sizeof(struct kvm_xcrs)))
3283 break;
3284 r = 0;
3285 break;
3286 }
3287 case KVM_SET_XCRS: {
3288 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3289 if (IS_ERR(u.xcrs))
3290 return PTR_ERR(u.xcrs);
3291
3292 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3293 break;
3294 }
3295 case KVM_SET_TSC_KHZ: {
3296 u32 user_tsc_khz;
3297
3298 r = -EINVAL;
3299 user_tsc_khz = (u32)arg;
3300
3301 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3302 goto out;
3303
3304 if (user_tsc_khz == 0)
3305 user_tsc_khz = tsc_khz;
3306
3307 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3308
3309 r = 0;
3310 goto out;
3311 }
3312 case KVM_GET_TSC_KHZ: {
3313 r = vcpu->arch.virtual_tsc_khz;
3314 goto out;
3315 }
3316 case KVM_KVMCLOCK_CTRL: {
3317 r = kvm_set_guest_paused(vcpu);
3318 goto out;
3319 }
3320 default:
3321 r = -EINVAL;
3322 }
3323 out:
3324 kfree(u.buffer);
3325 return r;
3326 }
3327
3328 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3329 {
3330 return VM_FAULT_SIGBUS;
3331 }
3332
3333 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3334 {
3335 int ret;
3336
3337 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3338 return -EINVAL;
3339 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3340 return ret;
3341 }
3342
3343 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3344 u64 ident_addr)
3345 {
3346 kvm->arch.ept_identity_map_addr = ident_addr;
3347 return 0;
3348 }
3349
3350 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3351 u32 kvm_nr_mmu_pages)
3352 {
3353 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3354 return -EINVAL;
3355
3356 mutex_lock(&kvm->slots_lock);
3357
3358 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3359 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3360
3361 mutex_unlock(&kvm->slots_lock);
3362 return 0;
3363 }
3364
3365 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3366 {
3367 return kvm->arch.n_max_mmu_pages;
3368 }
3369
3370 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3371 {
3372 int r;
3373
3374 r = 0;
3375 switch (chip->chip_id) {
3376 case KVM_IRQCHIP_PIC_MASTER:
3377 memcpy(&chip->chip.pic,
3378 &pic_irqchip(kvm)->pics[0],
3379 sizeof(struct kvm_pic_state));
3380 break;
3381 case KVM_IRQCHIP_PIC_SLAVE:
3382 memcpy(&chip->chip.pic,
3383 &pic_irqchip(kvm)->pics[1],
3384 sizeof(struct kvm_pic_state));
3385 break;
3386 case KVM_IRQCHIP_IOAPIC:
3387 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3388 break;
3389 default:
3390 r = -EINVAL;
3391 break;
3392 }
3393 return r;
3394 }
3395
3396 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3397 {
3398 int r;
3399
3400 r = 0;
3401 switch (chip->chip_id) {
3402 case KVM_IRQCHIP_PIC_MASTER:
3403 spin_lock(&pic_irqchip(kvm)->lock);
3404 memcpy(&pic_irqchip(kvm)->pics[0],
3405 &chip->chip.pic,
3406 sizeof(struct kvm_pic_state));
3407 spin_unlock(&pic_irqchip(kvm)->lock);
3408 break;
3409 case KVM_IRQCHIP_PIC_SLAVE:
3410 spin_lock(&pic_irqchip(kvm)->lock);
3411 memcpy(&pic_irqchip(kvm)->pics[1],
3412 &chip->chip.pic,
3413 sizeof(struct kvm_pic_state));
3414 spin_unlock(&pic_irqchip(kvm)->lock);
3415 break;
3416 case KVM_IRQCHIP_IOAPIC:
3417 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3418 break;
3419 default:
3420 r = -EINVAL;
3421 break;
3422 }
3423 kvm_pic_update_irq(pic_irqchip(kvm));
3424 return r;
3425 }
3426
3427 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3428 {
3429 int r = 0;
3430
3431 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3432 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3433 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3434 return r;
3435 }
3436
3437 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3438 {
3439 int r = 0;
3440
3441 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3442 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3443 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3444 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3445 return r;
3446 }
3447
3448 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3449 {
3450 int r = 0;
3451
3452 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3453 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3454 sizeof(ps->channels));
3455 ps->flags = kvm->arch.vpit->pit_state.flags;
3456 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3457 memset(&ps->reserved, 0, sizeof(ps->reserved));
3458 return r;
3459 }
3460
3461 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3462 {
3463 int r = 0, start = 0;
3464 u32 prev_legacy, cur_legacy;
3465 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3466 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3467 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3468 if (!prev_legacy && cur_legacy)
3469 start = 1;
3470 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3471 sizeof(kvm->arch.vpit->pit_state.channels));
3472 kvm->arch.vpit->pit_state.flags = ps->flags;
3473 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3474 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3475 return r;
3476 }
3477
3478 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3479 struct kvm_reinject_control *control)
3480 {
3481 if (!kvm->arch.vpit)
3482 return -ENXIO;
3483 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3484 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3485 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3486 return 0;
3487 }
3488
3489 /**
3490 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3491 * @kvm: kvm instance
3492 * @log: slot id and address to which we copy the log
3493 *
3494 * Steps 1-4 below provide general overview of dirty page logging. See
3495 * kvm_get_dirty_log_protect() function description for additional details.
3496 *
3497 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3498 * always flush the TLB (step 4) even if previous step failed and the dirty
3499 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3500 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3501 * writes will be marked dirty for next log read.
3502 *
3503 * 1. Take a snapshot of the bit and clear it if needed.
3504 * 2. Write protect the corresponding page.
3505 * 3. Copy the snapshot to the userspace.
3506 * 4. Flush TLB's if needed.
3507 */
3508 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3509 {
3510 bool is_dirty = false;
3511 int r;
3512
3513 mutex_lock(&kvm->slots_lock);
3514
3515 /*
3516 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3517 */
3518 if (kvm_x86_ops->flush_log_dirty)
3519 kvm_x86_ops->flush_log_dirty(kvm);
3520
3521 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3522
3523 /*
3524 * All the TLBs can be flushed out of mmu lock, see the comments in
3525 * kvm_mmu_slot_remove_write_access().
3526 */
3527 lockdep_assert_held(&kvm->slots_lock);
3528 if (is_dirty)
3529 kvm_flush_remote_tlbs(kvm);
3530
3531 mutex_unlock(&kvm->slots_lock);
3532 return r;
3533 }
3534
3535 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3536 bool line_status)
3537 {
3538 if (!irqchip_in_kernel(kvm))
3539 return -ENXIO;
3540
3541 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3542 irq_event->irq, irq_event->level,
3543 line_status);
3544 return 0;
3545 }
3546
3547 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3548 struct kvm_enable_cap *cap)
3549 {
3550 int r;
3551
3552 if (cap->flags)
3553 return -EINVAL;
3554
3555 switch (cap->cap) {
3556 case KVM_CAP_DISABLE_QUIRKS:
3557 kvm->arch.disabled_quirks = cap->args[0];
3558 r = 0;
3559 break;
3560 default:
3561 r = -EINVAL;
3562 break;
3563 }
3564 return r;
3565 }
3566
3567 long kvm_arch_vm_ioctl(struct file *filp,
3568 unsigned int ioctl, unsigned long arg)
3569 {
3570 struct kvm *kvm = filp->private_data;
3571 void __user *argp = (void __user *)arg;
3572 int r = -ENOTTY;
3573 /*
3574 * This union makes it completely explicit to gcc-3.x
3575 * that these two variables' stack usage should be
3576 * combined, not added together.
3577 */
3578 union {
3579 struct kvm_pit_state ps;
3580 struct kvm_pit_state2 ps2;
3581 struct kvm_pit_config pit_config;
3582 } u;
3583
3584 switch (ioctl) {
3585 case KVM_SET_TSS_ADDR:
3586 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3587 break;
3588 case KVM_SET_IDENTITY_MAP_ADDR: {
3589 u64 ident_addr;
3590
3591 r = -EFAULT;
3592 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3593 goto out;
3594 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3595 break;
3596 }
3597 case KVM_SET_NR_MMU_PAGES:
3598 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3599 break;
3600 case KVM_GET_NR_MMU_PAGES:
3601 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3602 break;
3603 case KVM_CREATE_IRQCHIP: {
3604 struct kvm_pic *vpic;
3605
3606 mutex_lock(&kvm->lock);
3607 r = -EEXIST;
3608 if (kvm->arch.vpic)
3609 goto create_irqchip_unlock;
3610 r = -EINVAL;
3611 if (atomic_read(&kvm->online_vcpus))
3612 goto create_irqchip_unlock;
3613 r = -ENOMEM;
3614 vpic = kvm_create_pic(kvm);
3615 if (vpic) {
3616 r = kvm_ioapic_init(kvm);
3617 if (r) {
3618 mutex_lock(&kvm->slots_lock);
3619 kvm_destroy_pic(vpic);
3620 mutex_unlock(&kvm->slots_lock);
3621 goto create_irqchip_unlock;
3622 }
3623 } else
3624 goto create_irqchip_unlock;
3625 r = kvm_setup_default_irq_routing(kvm);
3626 if (r) {
3627 mutex_lock(&kvm->slots_lock);
3628 mutex_lock(&kvm->irq_lock);
3629 kvm_ioapic_destroy(kvm);
3630 kvm_destroy_pic(vpic);
3631 mutex_unlock(&kvm->irq_lock);
3632 mutex_unlock(&kvm->slots_lock);
3633 goto create_irqchip_unlock;
3634 }
3635 /* Write kvm->irq_routing before kvm->arch.vpic. */
3636 smp_wmb();
3637 kvm->arch.vpic = vpic;
3638 create_irqchip_unlock:
3639 mutex_unlock(&kvm->lock);
3640 break;
3641 }
3642 case KVM_CREATE_PIT:
3643 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3644 goto create_pit;
3645 case KVM_CREATE_PIT2:
3646 r = -EFAULT;
3647 if (copy_from_user(&u.pit_config, argp,
3648 sizeof(struct kvm_pit_config)))
3649 goto out;
3650 create_pit:
3651 mutex_lock(&kvm->slots_lock);
3652 r = -EEXIST;
3653 if (kvm->arch.vpit)
3654 goto create_pit_unlock;
3655 r = -ENOMEM;
3656 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3657 if (kvm->arch.vpit)
3658 r = 0;
3659 create_pit_unlock:
3660 mutex_unlock(&kvm->slots_lock);
3661 break;
3662 case KVM_GET_IRQCHIP: {
3663 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3664 struct kvm_irqchip *chip;
3665
3666 chip = memdup_user(argp, sizeof(*chip));
3667 if (IS_ERR(chip)) {
3668 r = PTR_ERR(chip);
3669 goto out;
3670 }
3671
3672 r = -ENXIO;
3673 if (!irqchip_in_kernel(kvm))
3674 goto get_irqchip_out;
3675 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3676 if (r)
3677 goto get_irqchip_out;
3678 r = -EFAULT;
3679 if (copy_to_user(argp, chip, sizeof *chip))
3680 goto get_irqchip_out;
3681 r = 0;
3682 get_irqchip_out:
3683 kfree(chip);
3684 break;
3685 }
3686 case KVM_SET_IRQCHIP: {
3687 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3688 struct kvm_irqchip *chip;
3689
3690 chip = memdup_user(argp, sizeof(*chip));
3691 if (IS_ERR(chip)) {
3692 r = PTR_ERR(chip);
3693 goto out;
3694 }
3695
3696 r = -ENXIO;
3697 if (!irqchip_in_kernel(kvm))
3698 goto set_irqchip_out;
3699 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3700 if (r)
3701 goto set_irqchip_out;
3702 r = 0;
3703 set_irqchip_out:
3704 kfree(chip);
3705 break;
3706 }
3707 case KVM_GET_PIT: {
3708 r = -EFAULT;
3709 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3710 goto out;
3711 r = -ENXIO;
3712 if (!kvm->arch.vpit)
3713 goto out;
3714 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3715 if (r)
3716 goto out;
3717 r = -EFAULT;
3718 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3719 goto out;
3720 r = 0;
3721 break;
3722 }
3723 case KVM_SET_PIT: {
3724 r = -EFAULT;
3725 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3726 goto out;
3727 r = -ENXIO;
3728 if (!kvm->arch.vpit)
3729 goto out;
3730 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3731 break;
3732 }
3733 case KVM_GET_PIT2: {
3734 r = -ENXIO;
3735 if (!kvm->arch.vpit)
3736 goto out;
3737 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3738 if (r)
3739 goto out;
3740 r = -EFAULT;
3741 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3742 goto out;
3743 r = 0;
3744 break;
3745 }
3746 case KVM_SET_PIT2: {
3747 r = -EFAULT;
3748 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3749 goto out;
3750 r = -ENXIO;
3751 if (!kvm->arch.vpit)
3752 goto out;
3753 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3754 break;
3755 }
3756 case KVM_REINJECT_CONTROL: {
3757 struct kvm_reinject_control control;
3758 r = -EFAULT;
3759 if (copy_from_user(&control, argp, sizeof(control)))
3760 goto out;
3761 r = kvm_vm_ioctl_reinject(kvm, &control);
3762 break;
3763 }
3764 case KVM_SET_BOOT_CPU_ID:
3765 r = 0;
3766 mutex_lock(&kvm->lock);
3767 if (atomic_read(&kvm->online_vcpus) != 0)
3768 r = -EBUSY;
3769 else
3770 kvm->arch.bsp_vcpu_id = arg;
3771 mutex_unlock(&kvm->lock);
3772 break;
3773 case KVM_XEN_HVM_CONFIG: {
3774 r = -EFAULT;
3775 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3776 sizeof(struct kvm_xen_hvm_config)))
3777 goto out;
3778 r = -EINVAL;
3779 if (kvm->arch.xen_hvm_config.flags)
3780 goto out;
3781 r = 0;
3782 break;
3783 }
3784 case KVM_SET_CLOCK: {
3785 struct kvm_clock_data user_ns;
3786 u64 now_ns;
3787 s64 delta;
3788
3789 r = -EFAULT;
3790 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3791 goto out;
3792
3793 r = -EINVAL;
3794 if (user_ns.flags)
3795 goto out;
3796
3797 r = 0;
3798 local_irq_disable();
3799 now_ns = get_kernel_ns();
3800 delta = user_ns.clock - now_ns;
3801 local_irq_enable();
3802 kvm->arch.kvmclock_offset = delta;
3803 kvm_gen_update_masterclock(kvm);
3804 break;
3805 }
3806 case KVM_GET_CLOCK: {
3807 struct kvm_clock_data user_ns;
3808 u64 now_ns;
3809
3810 local_irq_disable();
3811 now_ns = get_kernel_ns();
3812 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3813 local_irq_enable();
3814 user_ns.flags = 0;
3815 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3816
3817 r = -EFAULT;
3818 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3819 goto out;
3820 r = 0;
3821 break;
3822 }
3823 case KVM_ENABLE_CAP: {
3824 struct kvm_enable_cap cap;
3825
3826 r = -EFAULT;
3827 if (copy_from_user(&cap, argp, sizeof(cap)))
3828 goto out;
3829 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3830 break;
3831 }
3832 default:
3833 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3834 }
3835 out:
3836 return r;
3837 }
3838
3839 static void kvm_init_msr_list(void)
3840 {
3841 u32 dummy[2];
3842 unsigned i, j;
3843
3844 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3845 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3846 continue;
3847
3848 /*
3849 * Even MSRs that are valid in the host may not be exposed
3850 * to the guests in some cases. We could work around this
3851 * in VMX with the generic MSR save/load machinery, but it
3852 * is not really worthwhile since it will really only
3853 * happen with nested virtualization.
3854 */
3855 switch (msrs_to_save[i]) {
3856 case MSR_IA32_BNDCFGS:
3857 if (!kvm_x86_ops->mpx_supported())
3858 continue;
3859 break;
3860 default:
3861 break;
3862 }
3863
3864 if (j < i)
3865 msrs_to_save[j] = msrs_to_save[i];
3866 j++;
3867 }
3868 num_msrs_to_save = j;
3869
3870 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3871 switch (emulated_msrs[i]) {
3872 case MSR_IA32_SMBASE:
3873 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3874 continue;
3875 break;
3876 default:
3877 break;
3878 }
3879
3880 if (j < i)
3881 emulated_msrs[j] = emulated_msrs[i];
3882 j++;
3883 }
3884 num_emulated_msrs = j;
3885 }
3886
3887 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3888 const void *v)
3889 {
3890 int handled = 0;
3891 int n;
3892
3893 do {
3894 n = min(len, 8);
3895 if (!(vcpu->arch.apic &&
3896 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3897 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3898 break;
3899 handled += n;
3900 addr += n;
3901 len -= n;
3902 v += n;
3903 } while (len);
3904
3905 return handled;
3906 }
3907
3908 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3909 {
3910 int handled = 0;
3911 int n;
3912
3913 do {
3914 n = min(len, 8);
3915 if (!(vcpu->arch.apic &&
3916 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3917 addr, n, v))
3918 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3919 break;
3920 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3921 handled += n;
3922 addr += n;
3923 len -= n;
3924 v += n;
3925 } while (len);
3926
3927 return handled;
3928 }
3929
3930 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3931 struct kvm_segment *var, int seg)
3932 {
3933 kvm_x86_ops->set_segment(vcpu, var, seg);
3934 }
3935
3936 void kvm_get_segment(struct kvm_vcpu *vcpu,
3937 struct kvm_segment *var, int seg)
3938 {
3939 kvm_x86_ops->get_segment(vcpu, var, seg);
3940 }
3941
3942 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3943 struct x86_exception *exception)
3944 {
3945 gpa_t t_gpa;
3946
3947 BUG_ON(!mmu_is_nested(vcpu));
3948
3949 /* NPT walks are always user-walks */
3950 access |= PFERR_USER_MASK;
3951 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3952
3953 return t_gpa;
3954 }
3955
3956 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3957 struct x86_exception *exception)
3958 {
3959 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3960 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3961 }
3962
3963 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3964 struct x86_exception *exception)
3965 {
3966 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3967 access |= PFERR_FETCH_MASK;
3968 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3969 }
3970
3971 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3972 struct x86_exception *exception)
3973 {
3974 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3975 access |= PFERR_WRITE_MASK;
3976 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3977 }
3978
3979 /* uses this to access any guest's mapped memory without checking CPL */
3980 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3981 struct x86_exception *exception)
3982 {
3983 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3984 }
3985
3986 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3987 struct kvm_vcpu *vcpu, u32 access,
3988 struct x86_exception *exception)
3989 {
3990 void *data = val;
3991 int r = X86EMUL_CONTINUE;
3992
3993 while (bytes) {
3994 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3995 exception);
3996 unsigned offset = addr & (PAGE_SIZE-1);
3997 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3998 int ret;
3999
4000 if (gpa == UNMAPPED_GVA)
4001 return X86EMUL_PROPAGATE_FAULT;
4002 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4003 offset, toread);
4004 if (ret < 0) {
4005 r = X86EMUL_IO_NEEDED;
4006 goto out;
4007 }
4008
4009 bytes -= toread;
4010 data += toread;
4011 addr += toread;
4012 }
4013 out:
4014 return r;
4015 }
4016
4017 /* used for instruction fetching */
4018 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4019 gva_t addr, void *val, unsigned int bytes,
4020 struct x86_exception *exception)
4021 {
4022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4023 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4024 unsigned offset;
4025 int ret;
4026
4027 /* Inline kvm_read_guest_virt_helper for speed. */
4028 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4029 exception);
4030 if (unlikely(gpa == UNMAPPED_GVA))
4031 return X86EMUL_PROPAGATE_FAULT;
4032
4033 offset = addr & (PAGE_SIZE-1);
4034 if (WARN_ON(offset + bytes > PAGE_SIZE))
4035 bytes = (unsigned)PAGE_SIZE - offset;
4036 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4037 offset, bytes);
4038 if (unlikely(ret < 0))
4039 return X86EMUL_IO_NEEDED;
4040
4041 return X86EMUL_CONTINUE;
4042 }
4043
4044 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4045 gva_t addr, void *val, unsigned int bytes,
4046 struct x86_exception *exception)
4047 {
4048 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4049 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4050
4051 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4052 exception);
4053 }
4054 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4055
4056 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4057 gva_t addr, void *val, unsigned int bytes,
4058 struct x86_exception *exception)
4059 {
4060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4061 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4062 }
4063
4064 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4065 gva_t addr, void *val,
4066 unsigned int bytes,
4067 struct x86_exception *exception)
4068 {
4069 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4070 void *data = val;
4071 int r = X86EMUL_CONTINUE;
4072
4073 while (bytes) {
4074 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4075 PFERR_WRITE_MASK,
4076 exception);
4077 unsigned offset = addr & (PAGE_SIZE-1);
4078 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4079 int ret;
4080
4081 if (gpa == UNMAPPED_GVA)
4082 return X86EMUL_PROPAGATE_FAULT;
4083 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4084 if (ret < 0) {
4085 r = X86EMUL_IO_NEEDED;
4086 goto out;
4087 }
4088
4089 bytes -= towrite;
4090 data += towrite;
4091 addr += towrite;
4092 }
4093 out:
4094 return r;
4095 }
4096 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4097
4098 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4099 gpa_t *gpa, struct x86_exception *exception,
4100 bool write)
4101 {
4102 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4103 | (write ? PFERR_WRITE_MASK : 0);
4104
4105 if (vcpu_match_mmio_gva(vcpu, gva)
4106 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4107 vcpu->arch.access, access)) {
4108 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4109 (gva & (PAGE_SIZE - 1));
4110 trace_vcpu_match_mmio(gva, *gpa, write, false);
4111 return 1;
4112 }
4113
4114 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4115
4116 if (*gpa == UNMAPPED_GVA)
4117 return -1;
4118
4119 /* For APIC access vmexit */
4120 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4121 return 1;
4122
4123 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4124 trace_vcpu_match_mmio(gva, *gpa, write, true);
4125 return 1;
4126 }
4127
4128 return 0;
4129 }
4130
4131 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4132 const void *val, int bytes)
4133 {
4134 int ret;
4135
4136 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4137 if (ret < 0)
4138 return 0;
4139 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4140 return 1;
4141 }
4142
4143 struct read_write_emulator_ops {
4144 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4145 int bytes);
4146 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4147 void *val, int bytes);
4148 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4149 int bytes, void *val);
4150 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4151 void *val, int bytes);
4152 bool write;
4153 };
4154
4155 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4156 {
4157 if (vcpu->mmio_read_completed) {
4158 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4159 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4160 vcpu->mmio_read_completed = 0;
4161 return 1;
4162 }
4163
4164 return 0;
4165 }
4166
4167 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4168 void *val, int bytes)
4169 {
4170 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4171 }
4172
4173 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4174 void *val, int bytes)
4175 {
4176 return emulator_write_phys(vcpu, gpa, val, bytes);
4177 }
4178
4179 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4180 {
4181 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4182 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4183 }
4184
4185 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 void *val, int bytes)
4187 {
4188 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4189 return X86EMUL_IO_NEEDED;
4190 }
4191
4192 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4193 void *val, int bytes)
4194 {
4195 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4196
4197 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4198 return X86EMUL_CONTINUE;
4199 }
4200
4201 static const struct read_write_emulator_ops read_emultor = {
4202 .read_write_prepare = read_prepare,
4203 .read_write_emulate = read_emulate,
4204 .read_write_mmio = vcpu_mmio_read,
4205 .read_write_exit_mmio = read_exit_mmio,
4206 };
4207
4208 static const struct read_write_emulator_ops write_emultor = {
4209 .read_write_emulate = write_emulate,
4210 .read_write_mmio = write_mmio,
4211 .read_write_exit_mmio = write_exit_mmio,
4212 .write = true,
4213 };
4214
4215 static int emulator_read_write_onepage(unsigned long addr, void *val,
4216 unsigned int bytes,
4217 struct x86_exception *exception,
4218 struct kvm_vcpu *vcpu,
4219 const struct read_write_emulator_ops *ops)
4220 {
4221 gpa_t gpa;
4222 int handled, ret;
4223 bool write = ops->write;
4224 struct kvm_mmio_fragment *frag;
4225
4226 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4227
4228 if (ret < 0)
4229 return X86EMUL_PROPAGATE_FAULT;
4230
4231 /* For APIC access vmexit */
4232 if (ret)
4233 goto mmio;
4234
4235 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4236 return X86EMUL_CONTINUE;
4237
4238 mmio:
4239 /*
4240 * Is this MMIO handled locally?
4241 */
4242 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4243 if (handled == bytes)
4244 return X86EMUL_CONTINUE;
4245
4246 gpa += handled;
4247 bytes -= handled;
4248 val += handled;
4249
4250 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4251 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4252 frag->gpa = gpa;
4253 frag->data = val;
4254 frag->len = bytes;
4255 return X86EMUL_CONTINUE;
4256 }
4257
4258 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4259 unsigned long addr,
4260 void *val, unsigned int bytes,
4261 struct x86_exception *exception,
4262 const struct read_write_emulator_ops *ops)
4263 {
4264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4265 gpa_t gpa;
4266 int rc;
4267
4268 if (ops->read_write_prepare &&
4269 ops->read_write_prepare(vcpu, val, bytes))
4270 return X86EMUL_CONTINUE;
4271
4272 vcpu->mmio_nr_fragments = 0;
4273
4274 /* Crossing a page boundary? */
4275 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4276 int now;
4277
4278 now = -addr & ~PAGE_MASK;
4279 rc = emulator_read_write_onepage(addr, val, now, exception,
4280 vcpu, ops);
4281
4282 if (rc != X86EMUL_CONTINUE)
4283 return rc;
4284 addr += now;
4285 if (ctxt->mode != X86EMUL_MODE_PROT64)
4286 addr = (u32)addr;
4287 val += now;
4288 bytes -= now;
4289 }
4290
4291 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4292 vcpu, ops);
4293 if (rc != X86EMUL_CONTINUE)
4294 return rc;
4295
4296 if (!vcpu->mmio_nr_fragments)
4297 return rc;
4298
4299 gpa = vcpu->mmio_fragments[0].gpa;
4300
4301 vcpu->mmio_needed = 1;
4302 vcpu->mmio_cur_fragment = 0;
4303
4304 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4305 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4306 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4307 vcpu->run->mmio.phys_addr = gpa;
4308
4309 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4310 }
4311
4312 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
4314 void *val,
4315 unsigned int bytes,
4316 struct x86_exception *exception)
4317 {
4318 return emulator_read_write(ctxt, addr, val, bytes,
4319 exception, &read_emultor);
4320 }
4321
4322 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4323 unsigned long addr,
4324 const void *val,
4325 unsigned int bytes,
4326 struct x86_exception *exception)
4327 {
4328 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4329 exception, &write_emultor);
4330 }
4331
4332 #define CMPXCHG_TYPE(t, ptr, old, new) \
4333 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4334
4335 #ifdef CONFIG_X86_64
4336 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4337 #else
4338 # define CMPXCHG64(ptr, old, new) \
4339 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4340 #endif
4341
4342 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4343 unsigned long addr,
4344 const void *old,
4345 const void *new,
4346 unsigned int bytes,
4347 struct x86_exception *exception)
4348 {
4349 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4350 gpa_t gpa;
4351 struct page *page;
4352 char *kaddr;
4353 bool exchanged;
4354
4355 /* guests cmpxchg8b have to be emulated atomically */
4356 if (bytes > 8 || (bytes & (bytes - 1)))
4357 goto emul_write;
4358
4359 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4360
4361 if (gpa == UNMAPPED_GVA ||
4362 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4363 goto emul_write;
4364
4365 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4366 goto emul_write;
4367
4368 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4369 if (is_error_page(page))
4370 goto emul_write;
4371
4372 kaddr = kmap_atomic(page);
4373 kaddr += offset_in_page(gpa);
4374 switch (bytes) {
4375 case 1:
4376 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4377 break;
4378 case 2:
4379 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4380 break;
4381 case 4:
4382 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4383 break;
4384 case 8:
4385 exchanged = CMPXCHG64(kaddr, old, new);
4386 break;
4387 default:
4388 BUG();
4389 }
4390 kunmap_atomic(kaddr);
4391 kvm_release_page_dirty(page);
4392
4393 if (!exchanged)
4394 return X86EMUL_CMPXCHG_FAILED;
4395
4396 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4397 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4398
4399 return X86EMUL_CONTINUE;
4400
4401 emul_write:
4402 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4403
4404 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4405 }
4406
4407 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4408 {
4409 /* TODO: String I/O for in kernel device */
4410 int r;
4411
4412 if (vcpu->arch.pio.in)
4413 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4414 vcpu->arch.pio.size, pd);
4415 else
4416 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4417 vcpu->arch.pio.port, vcpu->arch.pio.size,
4418 pd);
4419 return r;
4420 }
4421
4422 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4423 unsigned short port, void *val,
4424 unsigned int count, bool in)
4425 {
4426 vcpu->arch.pio.port = port;
4427 vcpu->arch.pio.in = in;
4428 vcpu->arch.pio.count = count;
4429 vcpu->arch.pio.size = size;
4430
4431 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4432 vcpu->arch.pio.count = 0;
4433 return 1;
4434 }
4435
4436 vcpu->run->exit_reason = KVM_EXIT_IO;
4437 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4438 vcpu->run->io.size = size;
4439 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4440 vcpu->run->io.count = count;
4441 vcpu->run->io.port = port;
4442
4443 return 0;
4444 }
4445
4446 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4447 int size, unsigned short port, void *val,
4448 unsigned int count)
4449 {
4450 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4451 int ret;
4452
4453 if (vcpu->arch.pio.count)
4454 goto data_avail;
4455
4456 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4457 if (ret) {
4458 data_avail:
4459 memcpy(val, vcpu->arch.pio_data, size * count);
4460 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4461 vcpu->arch.pio.count = 0;
4462 return 1;
4463 }
4464
4465 return 0;
4466 }
4467
4468 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4469 int size, unsigned short port,
4470 const void *val, unsigned int count)
4471 {
4472 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4473
4474 memcpy(vcpu->arch.pio_data, val, size * count);
4475 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4476 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4477 }
4478
4479 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4480 {
4481 return kvm_x86_ops->get_segment_base(vcpu, seg);
4482 }
4483
4484 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4485 {
4486 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4487 }
4488
4489 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4490 {
4491 if (!need_emulate_wbinvd(vcpu))
4492 return X86EMUL_CONTINUE;
4493
4494 if (kvm_x86_ops->has_wbinvd_exit()) {
4495 int cpu = get_cpu();
4496
4497 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4498 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4499 wbinvd_ipi, NULL, 1);
4500 put_cpu();
4501 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4502 } else
4503 wbinvd();
4504 return X86EMUL_CONTINUE;
4505 }
4506
4507 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4508 {
4509 kvm_x86_ops->skip_emulated_instruction(vcpu);
4510 return kvm_emulate_wbinvd_noskip(vcpu);
4511 }
4512 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4513
4514
4515
4516 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4517 {
4518 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4519 }
4520
4521 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4522 unsigned long *dest)
4523 {
4524 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4525 }
4526
4527 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4528 unsigned long value)
4529 {
4530
4531 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4532 }
4533
4534 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4535 {
4536 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4537 }
4538
4539 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4540 {
4541 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4542 unsigned long value;
4543
4544 switch (cr) {
4545 case 0:
4546 value = kvm_read_cr0(vcpu);
4547 break;
4548 case 2:
4549 value = vcpu->arch.cr2;
4550 break;
4551 case 3:
4552 value = kvm_read_cr3(vcpu);
4553 break;
4554 case 4:
4555 value = kvm_read_cr4(vcpu);
4556 break;
4557 case 8:
4558 value = kvm_get_cr8(vcpu);
4559 break;
4560 default:
4561 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4562 return 0;
4563 }
4564
4565 return value;
4566 }
4567
4568 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4569 {
4570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4571 int res = 0;
4572
4573 switch (cr) {
4574 case 0:
4575 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4576 break;
4577 case 2:
4578 vcpu->arch.cr2 = val;
4579 break;
4580 case 3:
4581 res = kvm_set_cr3(vcpu, val);
4582 break;
4583 case 4:
4584 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4585 break;
4586 case 8:
4587 res = kvm_set_cr8(vcpu, val);
4588 break;
4589 default:
4590 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4591 res = -1;
4592 }
4593
4594 return res;
4595 }
4596
4597 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4598 {
4599 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4600 }
4601
4602 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4603 {
4604 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4605 }
4606
4607 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4608 {
4609 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4610 }
4611
4612 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4613 {
4614 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4615 }
4616
4617 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4618 {
4619 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4620 }
4621
4622 static unsigned long emulator_get_cached_segment_base(
4623 struct x86_emulate_ctxt *ctxt, int seg)
4624 {
4625 return get_segment_base(emul_to_vcpu(ctxt), seg);
4626 }
4627
4628 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4629 struct desc_struct *desc, u32 *base3,
4630 int seg)
4631 {
4632 struct kvm_segment var;
4633
4634 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4635 *selector = var.selector;
4636
4637 if (var.unusable) {
4638 memset(desc, 0, sizeof(*desc));
4639 return false;
4640 }
4641
4642 if (var.g)
4643 var.limit >>= 12;
4644 set_desc_limit(desc, var.limit);
4645 set_desc_base(desc, (unsigned long)var.base);
4646 #ifdef CONFIG_X86_64
4647 if (base3)
4648 *base3 = var.base >> 32;
4649 #endif
4650 desc->type = var.type;
4651 desc->s = var.s;
4652 desc->dpl = var.dpl;
4653 desc->p = var.present;
4654 desc->avl = var.avl;
4655 desc->l = var.l;
4656 desc->d = var.db;
4657 desc->g = var.g;
4658
4659 return true;
4660 }
4661
4662 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4663 struct desc_struct *desc, u32 base3,
4664 int seg)
4665 {
4666 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4667 struct kvm_segment var;
4668
4669 var.selector = selector;
4670 var.base = get_desc_base(desc);
4671 #ifdef CONFIG_X86_64
4672 var.base |= ((u64)base3) << 32;
4673 #endif
4674 var.limit = get_desc_limit(desc);
4675 if (desc->g)
4676 var.limit = (var.limit << 12) | 0xfff;
4677 var.type = desc->type;
4678 var.dpl = desc->dpl;
4679 var.db = desc->d;
4680 var.s = desc->s;
4681 var.l = desc->l;
4682 var.g = desc->g;
4683 var.avl = desc->avl;
4684 var.present = desc->p;
4685 var.unusable = !var.present;
4686 var.padding = 0;
4687
4688 kvm_set_segment(vcpu, &var, seg);
4689 return;
4690 }
4691
4692 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4693 u32 msr_index, u64 *pdata)
4694 {
4695 struct msr_data msr;
4696 int r;
4697
4698 msr.index = msr_index;
4699 msr.host_initiated = false;
4700 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4701 if (r)
4702 return r;
4703
4704 *pdata = msr.data;
4705 return 0;
4706 }
4707
4708 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4709 u32 msr_index, u64 data)
4710 {
4711 struct msr_data msr;
4712
4713 msr.data = data;
4714 msr.index = msr_index;
4715 msr.host_initiated = false;
4716 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4717 }
4718
4719 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4720 {
4721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4722
4723 return vcpu->arch.smbase;
4724 }
4725
4726 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4727 {
4728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4729
4730 vcpu->arch.smbase = smbase;
4731 }
4732
4733 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4734 u32 pmc)
4735 {
4736 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4737 }
4738
4739 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4740 u32 pmc, u64 *pdata)
4741 {
4742 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4743 }
4744
4745 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4746 {
4747 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4748 }
4749
4750 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4751 {
4752 preempt_disable();
4753 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4754 /*
4755 * CR0.TS may reference the host fpu state, not the guest fpu state,
4756 * so it may be clear at this point.
4757 */
4758 clts();
4759 }
4760
4761 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4762 {
4763 preempt_enable();
4764 }
4765
4766 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4767 struct x86_instruction_info *info,
4768 enum x86_intercept_stage stage)
4769 {
4770 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4771 }
4772
4773 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4774 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4775 {
4776 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4777 }
4778
4779 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4780 {
4781 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4782 }
4783
4784 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4785 {
4786 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4787 }
4788
4789 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4790 {
4791 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4792 }
4793
4794 static const struct x86_emulate_ops emulate_ops = {
4795 .read_gpr = emulator_read_gpr,
4796 .write_gpr = emulator_write_gpr,
4797 .read_std = kvm_read_guest_virt_system,
4798 .write_std = kvm_write_guest_virt_system,
4799 .fetch = kvm_fetch_guest_virt,
4800 .read_emulated = emulator_read_emulated,
4801 .write_emulated = emulator_write_emulated,
4802 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4803 .invlpg = emulator_invlpg,
4804 .pio_in_emulated = emulator_pio_in_emulated,
4805 .pio_out_emulated = emulator_pio_out_emulated,
4806 .get_segment = emulator_get_segment,
4807 .set_segment = emulator_set_segment,
4808 .get_cached_segment_base = emulator_get_cached_segment_base,
4809 .get_gdt = emulator_get_gdt,
4810 .get_idt = emulator_get_idt,
4811 .set_gdt = emulator_set_gdt,
4812 .set_idt = emulator_set_idt,
4813 .get_cr = emulator_get_cr,
4814 .set_cr = emulator_set_cr,
4815 .cpl = emulator_get_cpl,
4816 .get_dr = emulator_get_dr,
4817 .set_dr = emulator_set_dr,
4818 .get_smbase = emulator_get_smbase,
4819 .set_smbase = emulator_set_smbase,
4820 .set_msr = emulator_set_msr,
4821 .get_msr = emulator_get_msr,
4822 .check_pmc = emulator_check_pmc,
4823 .read_pmc = emulator_read_pmc,
4824 .halt = emulator_halt,
4825 .wbinvd = emulator_wbinvd,
4826 .fix_hypercall = emulator_fix_hypercall,
4827 .get_fpu = emulator_get_fpu,
4828 .put_fpu = emulator_put_fpu,
4829 .intercept = emulator_intercept,
4830 .get_cpuid = emulator_get_cpuid,
4831 .set_nmi_mask = emulator_set_nmi_mask,
4832 };
4833
4834 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4835 {
4836 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4837 /*
4838 * an sti; sti; sequence only disable interrupts for the first
4839 * instruction. So, if the last instruction, be it emulated or
4840 * not, left the system with the INT_STI flag enabled, it
4841 * means that the last instruction is an sti. We should not
4842 * leave the flag on in this case. The same goes for mov ss
4843 */
4844 if (int_shadow & mask)
4845 mask = 0;
4846 if (unlikely(int_shadow || mask)) {
4847 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4848 if (!mask)
4849 kvm_make_request(KVM_REQ_EVENT, vcpu);
4850 }
4851 }
4852
4853 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4854 {
4855 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4856 if (ctxt->exception.vector == PF_VECTOR)
4857 return kvm_propagate_fault(vcpu, &ctxt->exception);
4858
4859 if (ctxt->exception.error_code_valid)
4860 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4861 ctxt->exception.error_code);
4862 else
4863 kvm_queue_exception(vcpu, ctxt->exception.vector);
4864 return false;
4865 }
4866
4867 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4868 {
4869 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4870 int cs_db, cs_l;
4871
4872 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4873
4874 ctxt->eflags = kvm_get_rflags(vcpu);
4875 ctxt->eip = kvm_rip_read(vcpu);
4876 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4877 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4878 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4879 cs_db ? X86EMUL_MODE_PROT32 :
4880 X86EMUL_MODE_PROT16;
4881 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4882 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4883 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4884 ctxt->emul_flags = vcpu->arch.hflags;
4885
4886 init_decode_cache(ctxt);
4887 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4888 }
4889
4890 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4891 {
4892 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4893 int ret;
4894
4895 init_emulate_ctxt(vcpu);
4896
4897 ctxt->op_bytes = 2;
4898 ctxt->ad_bytes = 2;
4899 ctxt->_eip = ctxt->eip + inc_eip;
4900 ret = emulate_int_real(ctxt, irq);
4901
4902 if (ret != X86EMUL_CONTINUE)
4903 return EMULATE_FAIL;
4904
4905 ctxt->eip = ctxt->_eip;
4906 kvm_rip_write(vcpu, ctxt->eip);
4907 kvm_set_rflags(vcpu, ctxt->eflags);
4908
4909 if (irq == NMI_VECTOR)
4910 vcpu->arch.nmi_pending = 0;
4911 else
4912 vcpu->arch.interrupt.pending = false;
4913
4914 return EMULATE_DONE;
4915 }
4916 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4917
4918 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4919 {
4920 int r = EMULATE_DONE;
4921
4922 ++vcpu->stat.insn_emulation_fail;
4923 trace_kvm_emulate_insn_failed(vcpu);
4924 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4925 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4926 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4927 vcpu->run->internal.ndata = 0;
4928 r = EMULATE_FAIL;
4929 }
4930 kvm_queue_exception(vcpu, UD_VECTOR);
4931
4932 return r;
4933 }
4934
4935 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4936 bool write_fault_to_shadow_pgtable,
4937 int emulation_type)
4938 {
4939 gpa_t gpa = cr2;
4940 pfn_t pfn;
4941
4942 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4943 return false;
4944
4945 if (!vcpu->arch.mmu.direct_map) {
4946 /*
4947 * Write permission should be allowed since only
4948 * write access need to be emulated.
4949 */
4950 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4951
4952 /*
4953 * If the mapping is invalid in guest, let cpu retry
4954 * it to generate fault.
4955 */
4956 if (gpa == UNMAPPED_GVA)
4957 return true;
4958 }
4959
4960 /*
4961 * Do not retry the unhandleable instruction if it faults on the
4962 * readonly host memory, otherwise it will goto a infinite loop:
4963 * retry instruction -> write #PF -> emulation fail -> retry
4964 * instruction -> ...
4965 */
4966 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4967
4968 /*
4969 * If the instruction failed on the error pfn, it can not be fixed,
4970 * report the error to userspace.
4971 */
4972 if (is_error_noslot_pfn(pfn))
4973 return false;
4974
4975 kvm_release_pfn_clean(pfn);
4976
4977 /* The instructions are well-emulated on direct mmu. */
4978 if (vcpu->arch.mmu.direct_map) {
4979 unsigned int indirect_shadow_pages;
4980
4981 spin_lock(&vcpu->kvm->mmu_lock);
4982 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4983 spin_unlock(&vcpu->kvm->mmu_lock);
4984
4985 if (indirect_shadow_pages)
4986 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4987
4988 return true;
4989 }
4990
4991 /*
4992 * if emulation was due to access to shadowed page table
4993 * and it failed try to unshadow page and re-enter the
4994 * guest to let CPU execute the instruction.
4995 */
4996 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4997
4998 /*
4999 * If the access faults on its page table, it can not
5000 * be fixed by unprotecting shadow page and it should
5001 * be reported to userspace.
5002 */
5003 return !write_fault_to_shadow_pgtable;
5004 }
5005
5006 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5007 unsigned long cr2, int emulation_type)
5008 {
5009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5010 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5011
5012 last_retry_eip = vcpu->arch.last_retry_eip;
5013 last_retry_addr = vcpu->arch.last_retry_addr;
5014
5015 /*
5016 * If the emulation is caused by #PF and it is non-page_table
5017 * writing instruction, it means the VM-EXIT is caused by shadow
5018 * page protected, we can zap the shadow page and retry this
5019 * instruction directly.
5020 *
5021 * Note: if the guest uses a non-page-table modifying instruction
5022 * on the PDE that points to the instruction, then we will unmap
5023 * the instruction and go to an infinite loop. So, we cache the
5024 * last retried eip and the last fault address, if we meet the eip
5025 * and the address again, we can break out of the potential infinite
5026 * loop.
5027 */
5028 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5029
5030 if (!(emulation_type & EMULTYPE_RETRY))
5031 return false;
5032
5033 if (x86_page_table_writing_insn(ctxt))
5034 return false;
5035
5036 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5037 return false;
5038
5039 vcpu->arch.last_retry_eip = ctxt->eip;
5040 vcpu->arch.last_retry_addr = cr2;
5041
5042 if (!vcpu->arch.mmu.direct_map)
5043 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5044
5045 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5046
5047 return true;
5048 }
5049
5050 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5051 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5052
5053 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5054 {
5055 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5056 /* This is a good place to trace that we are exiting SMM. */
5057 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5058
5059 if (unlikely(vcpu->arch.smi_pending)) {
5060 kvm_make_request(KVM_REQ_SMI, vcpu);
5061 vcpu->arch.smi_pending = 0;
5062 } else {
5063 /* Process a latched INIT, if any. */
5064 kvm_make_request(KVM_REQ_EVENT, vcpu);
5065 }
5066 }
5067
5068 kvm_mmu_reset_context(vcpu);
5069 }
5070
5071 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5072 {
5073 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5074
5075 vcpu->arch.hflags = emul_flags;
5076
5077 if (changed & HF_SMM_MASK)
5078 kvm_smm_changed(vcpu);
5079 }
5080
5081 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5082 unsigned long *db)
5083 {
5084 u32 dr6 = 0;
5085 int i;
5086 u32 enable, rwlen;
5087
5088 enable = dr7;
5089 rwlen = dr7 >> 16;
5090 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5091 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5092 dr6 |= (1 << i);
5093 return dr6;
5094 }
5095
5096 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5097 {
5098 struct kvm_run *kvm_run = vcpu->run;
5099
5100 /*
5101 * rflags is the old, "raw" value of the flags. The new value has
5102 * not been saved yet.
5103 *
5104 * This is correct even for TF set by the guest, because "the
5105 * processor will not generate this exception after the instruction
5106 * that sets the TF flag".
5107 */
5108 if (unlikely(rflags & X86_EFLAGS_TF)) {
5109 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5110 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5111 DR6_RTM;
5112 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5113 kvm_run->debug.arch.exception = DB_VECTOR;
5114 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5115 *r = EMULATE_USER_EXIT;
5116 } else {
5117 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5118 /*
5119 * "Certain debug exceptions may clear bit 0-3. The
5120 * remaining contents of the DR6 register are never
5121 * cleared by the processor".
5122 */
5123 vcpu->arch.dr6 &= ~15;
5124 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5125 kvm_queue_exception(vcpu, DB_VECTOR);
5126 }
5127 }
5128 }
5129
5130 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5131 {
5132 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5133 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5134 struct kvm_run *kvm_run = vcpu->run;
5135 unsigned long eip = kvm_get_linear_rip(vcpu);
5136 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5137 vcpu->arch.guest_debug_dr7,
5138 vcpu->arch.eff_db);
5139
5140 if (dr6 != 0) {
5141 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5142 kvm_run->debug.arch.pc = eip;
5143 kvm_run->debug.arch.exception = DB_VECTOR;
5144 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5145 *r = EMULATE_USER_EXIT;
5146 return true;
5147 }
5148 }
5149
5150 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5151 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5152 unsigned long eip = kvm_get_linear_rip(vcpu);
5153 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5154 vcpu->arch.dr7,
5155 vcpu->arch.db);
5156
5157 if (dr6 != 0) {
5158 vcpu->arch.dr6 &= ~15;
5159 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5160 kvm_queue_exception(vcpu, DB_VECTOR);
5161 *r = EMULATE_DONE;
5162 return true;
5163 }
5164 }
5165
5166 return false;
5167 }
5168
5169 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5170 unsigned long cr2,
5171 int emulation_type,
5172 void *insn,
5173 int insn_len)
5174 {
5175 int r;
5176 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5177 bool writeback = true;
5178 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5179
5180 /*
5181 * Clear write_fault_to_shadow_pgtable here to ensure it is
5182 * never reused.
5183 */
5184 vcpu->arch.write_fault_to_shadow_pgtable = false;
5185 kvm_clear_exception_queue(vcpu);
5186
5187 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5188 init_emulate_ctxt(vcpu);
5189
5190 /*
5191 * We will reenter on the same instruction since
5192 * we do not set complete_userspace_io. This does not
5193 * handle watchpoints yet, those would be handled in
5194 * the emulate_ops.
5195 */
5196 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5197 return r;
5198
5199 ctxt->interruptibility = 0;
5200 ctxt->have_exception = false;
5201 ctxt->exception.vector = -1;
5202 ctxt->perm_ok = false;
5203
5204 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5205
5206 r = x86_decode_insn(ctxt, insn, insn_len);
5207
5208 trace_kvm_emulate_insn_start(vcpu);
5209 ++vcpu->stat.insn_emulation;
5210 if (r != EMULATION_OK) {
5211 if (emulation_type & EMULTYPE_TRAP_UD)
5212 return EMULATE_FAIL;
5213 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5214 emulation_type))
5215 return EMULATE_DONE;
5216 if (emulation_type & EMULTYPE_SKIP)
5217 return EMULATE_FAIL;
5218 return handle_emulation_failure(vcpu);
5219 }
5220 }
5221
5222 if (emulation_type & EMULTYPE_SKIP) {
5223 kvm_rip_write(vcpu, ctxt->_eip);
5224 if (ctxt->eflags & X86_EFLAGS_RF)
5225 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5226 return EMULATE_DONE;
5227 }
5228
5229 if (retry_instruction(ctxt, cr2, emulation_type))
5230 return EMULATE_DONE;
5231
5232 /* this is needed for vmware backdoor interface to work since it
5233 changes registers values during IO operation */
5234 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5235 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5236 emulator_invalidate_register_cache(ctxt);
5237 }
5238
5239 restart:
5240 r = x86_emulate_insn(ctxt);
5241
5242 if (r == EMULATION_INTERCEPTED)
5243 return EMULATE_DONE;
5244
5245 if (r == EMULATION_FAILED) {
5246 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5247 emulation_type))
5248 return EMULATE_DONE;
5249
5250 return handle_emulation_failure(vcpu);
5251 }
5252
5253 if (ctxt->have_exception) {
5254 r = EMULATE_DONE;
5255 if (inject_emulated_exception(vcpu))
5256 return r;
5257 } else if (vcpu->arch.pio.count) {
5258 if (!vcpu->arch.pio.in) {
5259 /* FIXME: return into emulator if single-stepping. */
5260 vcpu->arch.pio.count = 0;
5261 } else {
5262 writeback = false;
5263 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5264 }
5265 r = EMULATE_USER_EXIT;
5266 } else if (vcpu->mmio_needed) {
5267 if (!vcpu->mmio_is_write)
5268 writeback = false;
5269 r = EMULATE_USER_EXIT;
5270 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5271 } else if (r == EMULATION_RESTART)
5272 goto restart;
5273 else
5274 r = EMULATE_DONE;
5275
5276 if (writeback) {
5277 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5278 toggle_interruptibility(vcpu, ctxt->interruptibility);
5279 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5280 if (vcpu->arch.hflags != ctxt->emul_flags)
5281 kvm_set_hflags(vcpu, ctxt->emul_flags);
5282 kvm_rip_write(vcpu, ctxt->eip);
5283 if (r == EMULATE_DONE)
5284 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5285 if (!ctxt->have_exception ||
5286 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5287 __kvm_set_rflags(vcpu, ctxt->eflags);
5288
5289 /*
5290 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5291 * do nothing, and it will be requested again as soon as
5292 * the shadow expires. But we still need to check here,
5293 * because POPF has no interrupt shadow.
5294 */
5295 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5296 kvm_make_request(KVM_REQ_EVENT, vcpu);
5297 } else
5298 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5299
5300 return r;
5301 }
5302 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5303
5304 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5305 {
5306 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5307 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5308 size, port, &val, 1);
5309 /* do not return to emulator after return from userspace */
5310 vcpu->arch.pio.count = 0;
5311 return ret;
5312 }
5313 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5314
5315 static void tsc_bad(void *info)
5316 {
5317 __this_cpu_write(cpu_tsc_khz, 0);
5318 }
5319
5320 static void tsc_khz_changed(void *data)
5321 {
5322 struct cpufreq_freqs *freq = data;
5323 unsigned long khz = 0;
5324
5325 if (data)
5326 khz = freq->new;
5327 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5328 khz = cpufreq_quick_get(raw_smp_processor_id());
5329 if (!khz)
5330 khz = tsc_khz;
5331 __this_cpu_write(cpu_tsc_khz, khz);
5332 }
5333
5334 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5335 void *data)
5336 {
5337 struct cpufreq_freqs *freq = data;
5338 struct kvm *kvm;
5339 struct kvm_vcpu *vcpu;
5340 int i, send_ipi = 0;
5341
5342 /*
5343 * We allow guests to temporarily run on slowing clocks,
5344 * provided we notify them after, or to run on accelerating
5345 * clocks, provided we notify them before. Thus time never
5346 * goes backwards.
5347 *
5348 * However, we have a problem. We can't atomically update
5349 * the frequency of a given CPU from this function; it is
5350 * merely a notifier, which can be called from any CPU.
5351 * Changing the TSC frequency at arbitrary points in time
5352 * requires a recomputation of local variables related to
5353 * the TSC for each VCPU. We must flag these local variables
5354 * to be updated and be sure the update takes place with the
5355 * new frequency before any guests proceed.
5356 *
5357 * Unfortunately, the combination of hotplug CPU and frequency
5358 * change creates an intractable locking scenario; the order
5359 * of when these callouts happen is undefined with respect to
5360 * CPU hotplug, and they can race with each other. As such,
5361 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5362 * undefined; you can actually have a CPU frequency change take
5363 * place in between the computation of X and the setting of the
5364 * variable. To protect against this problem, all updates of
5365 * the per_cpu tsc_khz variable are done in an interrupt
5366 * protected IPI, and all callers wishing to update the value
5367 * must wait for a synchronous IPI to complete (which is trivial
5368 * if the caller is on the CPU already). This establishes the
5369 * necessary total order on variable updates.
5370 *
5371 * Note that because a guest time update may take place
5372 * anytime after the setting of the VCPU's request bit, the
5373 * correct TSC value must be set before the request. However,
5374 * to ensure the update actually makes it to any guest which
5375 * starts running in hardware virtualization between the set
5376 * and the acquisition of the spinlock, we must also ping the
5377 * CPU after setting the request bit.
5378 *
5379 */
5380
5381 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5382 return 0;
5383 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5384 return 0;
5385
5386 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5387
5388 spin_lock(&kvm_lock);
5389 list_for_each_entry(kvm, &vm_list, vm_list) {
5390 kvm_for_each_vcpu(i, vcpu, kvm) {
5391 if (vcpu->cpu != freq->cpu)
5392 continue;
5393 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5394 if (vcpu->cpu != smp_processor_id())
5395 send_ipi = 1;
5396 }
5397 }
5398 spin_unlock(&kvm_lock);
5399
5400 if (freq->old < freq->new && send_ipi) {
5401 /*
5402 * We upscale the frequency. Must make the guest
5403 * doesn't see old kvmclock values while running with
5404 * the new frequency, otherwise we risk the guest sees
5405 * time go backwards.
5406 *
5407 * In case we update the frequency for another cpu
5408 * (which might be in guest context) send an interrupt
5409 * to kick the cpu out of guest context. Next time
5410 * guest context is entered kvmclock will be updated,
5411 * so the guest will not see stale values.
5412 */
5413 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5414 }
5415 return 0;
5416 }
5417
5418 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5419 .notifier_call = kvmclock_cpufreq_notifier
5420 };
5421
5422 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5423 unsigned long action, void *hcpu)
5424 {
5425 unsigned int cpu = (unsigned long)hcpu;
5426
5427 switch (action) {
5428 case CPU_ONLINE:
5429 case CPU_DOWN_FAILED:
5430 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5431 break;
5432 case CPU_DOWN_PREPARE:
5433 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5434 break;
5435 }
5436 return NOTIFY_OK;
5437 }
5438
5439 static struct notifier_block kvmclock_cpu_notifier_block = {
5440 .notifier_call = kvmclock_cpu_notifier,
5441 .priority = -INT_MAX
5442 };
5443
5444 static void kvm_timer_init(void)
5445 {
5446 int cpu;
5447
5448 max_tsc_khz = tsc_khz;
5449
5450 cpu_notifier_register_begin();
5451 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5452 #ifdef CONFIG_CPU_FREQ
5453 struct cpufreq_policy policy;
5454 memset(&policy, 0, sizeof(policy));
5455 cpu = get_cpu();
5456 cpufreq_get_policy(&policy, cpu);
5457 if (policy.cpuinfo.max_freq)
5458 max_tsc_khz = policy.cpuinfo.max_freq;
5459 put_cpu();
5460 #endif
5461 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5462 CPUFREQ_TRANSITION_NOTIFIER);
5463 }
5464 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5465 for_each_online_cpu(cpu)
5466 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5467
5468 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5469 cpu_notifier_register_done();
5470
5471 }
5472
5473 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5474
5475 int kvm_is_in_guest(void)
5476 {
5477 return __this_cpu_read(current_vcpu) != NULL;
5478 }
5479
5480 static int kvm_is_user_mode(void)
5481 {
5482 int user_mode = 3;
5483
5484 if (__this_cpu_read(current_vcpu))
5485 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5486
5487 return user_mode != 0;
5488 }
5489
5490 static unsigned long kvm_get_guest_ip(void)
5491 {
5492 unsigned long ip = 0;
5493
5494 if (__this_cpu_read(current_vcpu))
5495 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5496
5497 return ip;
5498 }
5499
5500 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5501 .is_in_guest = kvm_is_in_guest,
5502 .is_user_mode = kvm_is_user_mode,
5503 .get_guest_ip = kvm_get_guest_ip,
5504 };
5505
5506 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5507 {
5508 __this_cpu_write(current_vcpu, vcpu);
5509 }
5510 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5511
5512 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5513 {
5514 __this_cpu_write(current_vcpu, NULL);
5515 }
5516 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5517
5518 static void kvm_set_mmio_spte_mask(void)
5519 {
5520 u64 mask;
5521 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5522
5523 /*
5524 * Set the reserved bits and the present bit of an paging-structure
5525 * entry to generate page fault with PFER.RSV = 1.
5526 */
5527 /* Mask the reserved physical address bits. */
5528 mask = rsvd_bits(maxphyaddr, 51);
5529
5530 /* Bit 62 is always reserved for 32bit host. */
5531 mask |= 0x3ull << 62;
5532
5533 /* Set the present bit. */
5534 mask |= 1ull;
5535
5536 #ifdef CONFIG_X86_64
5537 /*
5538 * If reserved bit is not supported, clear the present bit to disable
5539 * mmio page fault.
5540 */
5541 if (maxphyaddr == 52)
5542 mask &= ~1ull;
5543 #endif
5544
5545 kvm_mmu_set_mmio_spte_mask(mask);
5546 }
5547
5548 #ifdef CONFIG_X86_64
5549 static void pvclock_gtod_update_fn(struct work_struct *work)
5550 {
5551 struct kvm *kvm;
5552
5553 struct kvm_vcpu *vcpu;
5554 int i;
5555
5556 spin_lock(&kvm_lock);
5557 list_for_each_entry(kvm, &vm_list, vm_list)
5558 kvm_for_each_vcpu(i, vcpu, kvm)
5559 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5560 atomic_set(&kvm_guest_has_master_clock, 0);
5561 spin_unlock(&kvm_lock);
5562 }
5563
5564 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5565
5566 /*
5567 * Notification about pvclock gtod data update.
5568 */
5569 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5570 void *priv)
5571 {
5572 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5573 struct timekeeper *tk = priv;
5574
5575 update_pvclock_gtod(tk);
5576
5577 /* disable master clock if host does not trust, or does not
5578 * use, TSC clocksource
5579 */
5580 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5581 atomic_read(&kvm_guest_has_master_clock) != 0)
5582 queue_work(system_long_wq, &pvclock_gtod_work);
5583
5584 return 0;
5585 }
5586
5587 static struct notifier_block pvclock_gtod_notifier = {
5588 .notifier_call = pvclock_gtod_notify,
5589 };
5590 #endif
5591
5592 int kvm_arch_init(void *opaque)
5593 {
5594 int r;
5595 struct kvm_x86_ops *ops = opaque;
5596
5597 if (kvm_x86_ops) {
5598 printk(KERN_ERR "kvm: already loaded the other module\n");
5599 r = -EEXIST;
5600 goto out;
5601 }
5602
5603 if (!ops->cpu_has_kvm_support()) {
5604 printk(KERN_ERR "kvm: no hardware support\n");
5605 r = -EOPNOTSUPP;
5606 goto out;
5607 }
5608 if (ops->disabled_by_bios()) {
5609 printk(KERN_ERR "kvm: disabled by bios\n");
5610 r = -EOPNOTSUPP;
5611 goto out;
5612 }
5613
5614 r = -ENOMEM;
5615 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5616 if (!shared_msrs) {
5617 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5618 goto out;
5619 }
5620
5621 r = kvm_mmu_module_init();
5622 if (r)
5623 goto out_free_percpu;
5624
5625 kvm_set_mmio_spte_mask();
5626
5627 kvm_x86_ops = ops;
5628
5629 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5630 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5631
5632 kvm_timer_init();
5633
5634 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5635
5636 if (cpu_has_xsave)
5637 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5638
5639 kvm_lapic_init();
5640 #ifdef CONFIG_X86_64
5641 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5642 #endif
5643
5644 return 0;
5645
5646 out_free_percpu:
5647 free_percpu(shared_msrs);
5648 out:
5649 return r;
5650 }
5651
5652 void kvm_arch_exit(void)
5653 {
5654 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5655
5656 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5657 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5658 CPUFREQ_TRANSITION_NOTIFIER);
5659 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5660 #ifdef CONFIG_X86_64
5661 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5662 #endif
5663 kvm_x86_ops = NULL;
5664 kvm_mmu_module_exit();
5665 free_percpu(shared_msrs);
5666 }
5667
5668 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5669 {
5670 ++vcpu->stat.halt_exits;
5671 if (irqchip_in_kernel(vcpu->kvm)) {
5672 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5673 return 1;
5674 } else {
5675 vcpu->run->exit_reason = KVM_EXIT_HLT;
5676 return 0;
5677 }
5678 }
5679 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5680
5681 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5682 {
5683 kvm_x86_ops->skip_emulated_instruction(vcpu);
5684 return kvm_vcpu_halt(vcpu);
5685 }
5686 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5687
5688 /*
5689 * kvm_pv_kick_cpu_op: Kick a vcpu.
5690 *
5691 * @apicid - apicid of vcpu to be kicked.
5692 */
5693 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5694 {
5695 struct kvm_lapic_irq lapic_irq;
5696
5697 lapic_irq.shorthand = 0;
5698 lapic_irq.dest_mode = 0;
5699 lapic_irq.dest_id = apicid;
5700 lapic_irq.msi_redir_hint = false;
5701
5702 lapic_irq.delivery_mode = APIC_DM_REMRD;
5703 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5704 }
5705
5706 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5707 {
5708 unsigned long nr, a0, a1, a2, a3, ret;
5709 int op_64_bit, r = 1;
5710
5711 kvm_x86_ops->skip_emulated_instruction(vcpu);
5712
5713 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5714 return kvm_hv_hypercall(vcpu);
5715
5716 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5717 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5718 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5719 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5720 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5721
5722 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5723
5724 op_64_bit = is_64_bit_mode(vcpu);
5725 if (!op_64_bit) {
5726 nr &= 0xFFFFFFFF;
5727 a0 &= 0xFFFFFFFF;
5728 a1 &= 0xFFFFFFFF;
5729 a2 &= 0xFFFFFFFF;
5730 a3 &= 0xFFFFFFFF;
5731 }
5732
5733 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5734 ret = -KVM_EPERM;
5735 goto out;
5736 }
5737
5738 switch (nr) {
5739 case KVM_HC_VAPIC_POLL_IRQ:
5740 ret = 0;
5741 break;
5742 case KVM_HC_KICK_CPU:
5743 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5744 ret = 0;
5745 break;
5746 default:
5747 ret = -KVM_ENOSYS;
5748 break;
5749 }
5750 out:
5751 if (!op_64_bit)
5752 ret = (u32)ret;
5753 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5754 ++vcpu->stat.hypercalls;
5755 return r;
5756 }
5757 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5758
5759 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5760 {
5761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5762 char instruction[3];
5763 unsigned long rip = kvm_rip_read(vcpu);
5764
5765 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5766
5767 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5768 }
5769
5770 /*
5771 * Check if userspace requested an interrupt window, and that the
5772 * interrupt window is open.
5773 *
5774 * No need to exit to userspace if we already have an interrupt queued.
5775 */
5776 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5777 {
5778 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5779 vcpu->run->request_interrupt_window &&
5780 kvm_arch_interrupt_allowed(vcpu));
5781 }
5782
5783 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5784 {
5785 struct kvm_run *kvm_run = vcpu->run;
5786
5787 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5788 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5789 kvm_run->cr8 = kvm_get_cr8(vcpu);
5790 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5791 if (irqchip_in_kernel(vcpu->kvm))
5792 kvm_run->ready_for_interrupt_injection = 1;
5793 else
5794 kvm_run->ready_for_interrupt_injection =
5795 kvm_arch_interrupt_allowed(vcpu) &&
5796 !kvm_cpu_has_interrupt(vcpu) &&
5797 !kvm_event_needs_reinjection(vcpu);
5798 }
5799
5800 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5801 {
5802 int max_irr, tpr;
5803
5804 if (!kvm_x86_ops->update_cr8_intercept)
5805 return;
5806
5807 if (!vcpu->arch.apic)
5808 return;
5809
5810 if (!vcpu->arch.apic->vapic_addr)
5811 max_irr = kvm_lapic_find_highest_irr(vcpu);
5812 else
5813 max_irr = -1;
5814
5815 if (max_irr != -1)
5816 max_irr >>= 4;
5817
5818 tpr = kvm_lapic_get_cr8(vcpu);
5819
5820 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5821 }
5822
5823 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5824 {
5825 int r;
5826
5827 /* try to reinject previous events if any */
5828 if (vcpu->arch.exception.pending) {
5829 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5830 vcpu->arch.exception.has_error_code,
5831 vcpu->arch.exception.error_code);
5832
5833 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5834 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5835 X86_EFLAGS_RF);
5836
5837 if (vcpu->arch.exception.nr == DB_VECTOR &&
5838 (vcpu->arch.dr7 & DR7_GD)) {
5839 vcpu->arch.dr7 &= ~DR7_GD;
5840 kvm_update_dr7(vcpu);
5841 }
5842
5843 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5844 vcpu->arch.exception.has_error_code,
5845 vcpu->arch.exception.error_code,
5846 vcpu->arch.exception.reinject);
5847 return 0;
5848 }
5849
5850 if (vcpu->arch.nmi_injected) {
5851 kvm_x86_ops->set_nmi(vcpu);
5852 return 0;
5853 }
5854
5855 if (vcpu->arch.interrupt.pending) {
5856 kvm_x86_ops->set_irq(vcpu);
5857 return 0;
5858 }
5859
5860 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5861 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5862 if (r != 0)
5863 return r;
5864 }
5865
5866 /* try to inject new event if pending */
5867 if (vcpu->arch.nmi_pending) {
5868 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5869 --vcpu->arch.nmi_pending;
5870 vcpu->arch.nmi_injected = true;
5871 kvm_x86_ops->set_nmi(vcpu);
5872 }
5873 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5874 /*
5875 * Because interrupts can be injected asynchronously, we are
5876 * calling check_nested_events again here to avoid a race condition.
5877 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5878 * proposal and current concerns. Perhaps we should be setting
5879 * KVM_REQ_EVENT only on certain events and not unconditionally?
5880 */
5881 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5882 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5883 if (r != 0)
5884 return r;
5885 }
5886 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5887 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5888 false);
5889 kvm_x86_ops->set_irq(vcpu);
5890 }
5891 }
5892 return 0;
5893 }
5894
5895 static void process_nmi(struct kvm_vcpu *vcpu)
5896 {
5897 unsigned limit = 2;
5898
5899 /*
5900 * x86 is limited to one NMI running, and one NMI pending after it.
5901 * If an NMI is already in progress, limit further NMIs to just one.
5902 * Otherwise, allow two (and we'll inject the first one immediately).
5903 */
5904 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5905 limit = 1;
5906
5907 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5908 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5909 kvm_make_request(KVM_REQ_EVENT, vcpu);
5910 }
5911
5912 #define put_smstate(type, buf, offset, val) \
5913 *(type *)((buf) + (offset) - 0x7e00) = val
5914
5915 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5916 {
5917 u32 flags = 0;
5918 flags |= seg->g << 23;
5919 flags |= seg->db << 22;
5920 flags |= seg->l << 21;
5921 flags |= seg->avl << 20;
5922 flags |= seg->present << 15;
5923 flags |= seg->dpl << 13;
5924 flags |= seg->s << 12;
5925 flags |= seg->type << 8;
5926 return flags;
5927 }
5928
5929 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5930 {
5931 struct kvm_segment seg;
5932 int offset;
5933
5934 kvm_get_segment(vcpu, &seg, n);
5935 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5936
5937 if (n < 3)
5938 offset = 0x7f84 + n * 12;
5939 else
5940 offset = 0x7f2c + (n - 3) * 12;
5941
5942 put_smstate(u32, buf, offset + 8, seg.base);
5943 put_smstate(u32, buf, offset + 4, seg.limit);
5944 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5945 }
5946
5947 #ifdef CONFIG_X86_64
5948 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5949 {
5950 struct kvm_segment seg;
5951 int offset;
5952 u16 flags;
5953
5954 kvm_get_segment(vcpu, &seg, n);
5955 offset = 0x7e00 + n * 16;
5956
5957 flags = process_smi_get_segment_flags(&seg) >> 8;
5958 put_smstate(u16, buf, offset, seg.selector);
5959 put_smstate(u16, buf, offset + 2, flags);
5960 put_smstate(u32, buf, offset + 4, seg.limit);
5961 put_smstate(u64, buf, offset + 8, seg.base);
5962 }
5963 #endif
5964
5965 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5966 {
5967 struct desc_ptr dt;
5968 struct kvm_segment seg;
5969 unsigned long val;
5970 int i;
5971
5972 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5973 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5974 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5975 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5976
5977 for (i = 0; i < 8; i++)
5978 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
5979
5980 kvm_get_dr(vcpu, 6, &val);
5981 put_smstate(u32, buf, 0x7fcc, (u32)val);
5982 kvm_get_dr(vcpu, 7, &val);
5983 put_smstate(u32, buf, 0x7fc8, (u32)val);
5984
5985 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
5986 put_smstate(u32, buf, 0x7fc4, seg.selector);
5987 put_smstate(u32, buf, 0x7f64, seg.base);
5988 put_smstate(u32, buf, 0x7f60, seg.limit);
5989 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
5990
5991 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
5992 put_smstate(u32, buf, 0x7fc0, seg.selector);
5993 put_smstate(u32, buf, 0x7f80, seg.base);
5994 put_smstate(u32, buf, 0x7f7c, seg.limit);
5995 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
5996
5997 kvm_x86_ops->get_gdt(vcpu, &dt);
5998 put_smstate(u32, buf, 0x7f74, dt.address);
5999 put_smstate(u32, buf, 0x7f70, dt.size);
6000
6001 kvm_x86_ops->get_idt(vcpu, &dt);
6002 put_smstate(u32, buf, 0x7f58, dt.address);
6003 put_smstate(u32, buf, 0x7f54, dt.size);
6004
6005 for (i = 0; i < 6; i++)
6006 process_smi_save_seg_32(vcpu, buf, i);
6007
6008 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6009
6010 /* revision id */
6011 put_smstate(u32, buf, 0x7efc, 0x00020000);
6012 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6013 }
6014
6015 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6016 {
6017 #ifdef CONFIG_X86_64
6018 struct desc_ptr dt;
6019 struct kvm_segment seg;
6020 unsigned long val;
6021 int i;
6022
6023 for (i = 0; i < 16; i++)
6024 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6025
6026 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6027 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6028
6029 kvm_get_dr(vcpu, 6, &val);
6030 put_smstate(u64, buf, 0x7f68, val);
6031 kvm_get_dr(vcpu, 7, &val);
6032 put_smstate(u64, buf, 0x7f60, val);
6033
6034 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6035 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6036 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6037
6038 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6039
6040 /* revision id */
6041 put_smstate(u32, buf, 0x7efc, 0x00020064);
6042
6043 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6044
6045 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6046 put_smstate(u16, buf, 0x7e90, seg.selector);
6047 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6048 put_smstate(u32, buf, 0x7e94, seg.limit);
6049 put_smstate(u64, buf, 0x7e98, seg.base);
6050
6051 kvm_x86_ops->get_idt(vcpu, &dt);
6052 put_smstate(u32, buf, 0x7e84, dt.size);
6053 put_smstate(u64, buf, 0x7e88, dt.address);
6054
6055 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6056 put_smstate(u16, buf, 0x7e70, seg.selector);
6057 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6058 put_smstate(u32, buf, 0x7e74, seg.limit);
6059 put_smstate(u64, buf, 0x7e78, seg.base);
6060
6061 kvm_x86_ops->get_gdt(vcpu, &dt);
6062 put_smstate(u32, buf, 0x7e64, dt.size);
6063 put_smstate(u64, buf, 0x7e68, dt.address);
6064
6065 for (i = 0; i < 6; i++)
6066 process_smi_save_seg_64(vcpu, buf, i);
6067 #else
6068 WARN_ON_ONCE(1);
6069 #endif
6070 }
6071
6072 static void process_smi(struct kvm_vcpu *vcpu)
6073 {
6074 struct kvm_segment cs, ds;
6075 struct desc_ptr dt;
6076 char buf[512];
6077 u32 cr0;
6078
6079 if (is_smm(vcpu)) {
6080 vcpu->arch.smi_pending = true;
6081 return;
6082 }
6083
6084 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6085 vcpu->arch.hflags |= HF_SMM_MASK;
6086 memset(buf, 0, 512);
6087 if (guest_cpuid_has_longmode(vcpu))
6088 process_smi_save_state_64(vcpu, buf);
6089 else
6090 process_smi_save_state_32(vcpu, buf);
6091
6092 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6093
6094 if (kvm_x86_ops->get_nmi_mask(vcpu))
6095 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6096 else
6097 kvm_x86_ops->set_nmi_mask(vcpu, true);
6098
6099 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6100 kvm_rip_write(vcpu, 0x8000);
6101
6102 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6103 kvm_x86_ops->set_cr0(vcpu, cr0);
6104 vcpu->arch.cr0 = cr0;
6105
6106 kvm_x86_ops->set_cr4(vcpu, 0);
6107
6108 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6109 dt.address = dt.size = 0;
6110 kvm_x86_ops->set_idt(vcpu, &dt);
6111
6112 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6113
6114 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6115 cs.base = vcpu->arch.smbase;
6116
6117 ds.selector = 0;
6118 ds.base = 0;
6119
6120 cs.limit = ds.limit = 0xffffffff;
6121 cs.type = ds.type = 0x3;
6122 cs.dpl = ds.dpl = 0;
6123 cs.db = ds.db = 0;
6124 cs.s = ds.s = 1;
6125 cs.l = ds.l = 0;
6126 cs.g = ds.g = 1;
6127 cs.avl = ds.avl = 0;
6128 cs.present = ds.present = 1;
6129 cs.unusable = ds.unusable = 0;
6130 cs.padding = ds.padding = 0;
6131
6132 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6133 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6134 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6135 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6136 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6137 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6138
6139 if (guest_cpuid_has_longmode(vcpu))
6140 kvm_x86_ops->set_efer(vcpu, 0);
6141
6142 kvm_update_cpuid(vcpu);
6143 kvm_mmu_reset_context(vcpu);
6144 }
6145
6146 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6147 {
6148 u64 eoi_exit_bitmap[4];
6149 u32 tmr[8];
6150
6151 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6152 return;
6153
6154 memset(eoi_exit_bitmap, 0, 32);
6155 memset(tmr, 0, 32);
6156
6157 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6158 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6159 kvm_apic_update_tmr(vcpu, tmr);
6160 }
6161
6162 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6163 {
6164 ++vcpu->stat.tlb_flush;
6165 kvm_x86_ops->tlb_flush(vcpu);
6166 }
6167
6168 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6169 {
6170 struct page *page = NULL;
6171
6172 if (!irqchip_in_kernel(vcpu->kvm))
6173 return;
6174
6175 if (!kvm_x86_ops->set_apic_access_page_addr)
6176 return;
6177
6178 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6179 if (is_error_page(page))
6180 return;
6181 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6182
6183 /*
6184 * Do not pin apic access page in memory, the MMU notifier
6185 * will call us again if it is migrated or swapped out.
6186 */
6187 put_page(page);
6188 }
6189 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6190
6191 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6192 unsigned long address)
6193 {
6194 /*
6195 * The physical address of apic access page is stored in the VMCS.
6196 * Update it when it becomes invalid.
6197 */
6198 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6199 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6200 }
6201
6202 /*
6203 * Returns 1 to let vcpu_run() continue the guest execution loop without
6204 * exiting to the userspace. Otherwise, the value will be returned to the
6205 * userspace.
6206 */
6207 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6208 {
6209 int r;
6210 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6211 vcpu->run->request_interrupt_window;
6212 bool req_immediate_exit = false;
6213
6214 if (vcpu->requests) {
6215 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6216 kvm_mmu_unload(vcpu);
6217 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6218 __kvm_migrate_timers(vcpu);
6219 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6220 kvm_gen_update_masterclock(vcpu->kvm);
6221 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6222 kvm_gen_kvmclock_update(vcpu);
6223 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6224 r = kvm_guest_time_update(vcpu);
6225 if (unlikely(r))
6226 goto out;
6227 }
6228 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6229 kvm_mmu_sync_roots(vcpu);
6230 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6231 kvm_vcpu_flush_tlb(vcpu);
6232 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6233 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6234 r = 0;
6235 goto out;
6236 }
6237 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6238 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6239 r = 0;
6240 goto out;
6241 }
6242 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6243 vcpu->fpu_active = 0;
6244 kvm_x86_ops->fpu_deactivate(vcpu);
6245 }
6246 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6247 /* Page is swapped out. Do synthetic halt */
6248 vcpu->arch.apf.halted = true;
6249 r = 1;
6250 goto out;
6251 }
6252 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6253 record_steal_time(vcpu);
6254 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6255 process_smi(vcpu);
6256 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6257 process_nmi(vcpu);
6258 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6259 kvm_pmu_handle_event(vcpu);
6260 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6261 kvm_pmu_deliver_pmi(vcpu);
6262 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6263 vcpu_scan_ioapic(vcpu);
6264 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6265 kvm_vcpu_reload_apic_access_page(vcpu);
6266 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6267 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6268 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6269 r = 0;
6270 goto out;
6271 }
6272 }
6273
6274 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6275 kvm_apic_accept_events(vcpu);
6276 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6277 r = 1;
6278 goto out;
6279 }
6280
6281 if (inject_pending_event(vcpu, req_int_win) != 0)
6282 req_immediate_exit = true;
6283 /* enable NMI/IRQ window open exits if needed */
6284 else if (vcpu->arch.nmi_pending)
6285 kvm_x86_ops->enable_nmi_window(vcpu);
6286 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6287 kvm_x86_ops->enable_irq_window(vcpu);
6288
6289 if (kvm_lapic_enabled(vcpu)) {
6290 /*
6291 * Update architecture specific hints for APIC
6292 * virtual interrupt delivery.
6293 */
6294 if (kvm_x86_ops->hwapic_irr_update)
6295 kvm_x86_ops->hwapic_irr_update(vcpu,
6296 kvm_lapic_find_highest_irr(vcpu));
6297 update_cr8_intercept(vcpu);
6298 kvm_lapic_sync_to_vapic(vcpu);
6299 }
6300 }
6301
6302 r = kvm_mmu_reload(vcpu);
6303 if (unlikely(r)) {
6304 goto cancel_injection;
6305 }
6306
6307 preempt_disable();
6308
6309 kvm_x86_ops->prepare_guest_switch(vcpu);
6310 if (vcpu->fpu_active)
6311 kvm_load_guest_fpu(vcpu);
6312 kvm_load_guest_xcr0(vcpu);
6313
6314 vcpu->mode = IN_GUEST_MODE;
6315
6316 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6317
6318 /* We should set ->mode before check ->requests,
6319 * see the comment in make_all_cpus_request.
6320 */
6321 smp_mb__after_srcu_read_unlock();
6322
6323 local_irq_disable();
6324
6325 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6326 || need_resched() || signal_pending(current)) {
6327 vcpu->mode = OUTSIDE_GUEST_MODE;
6328 smp_wmb();
6329 local_irq_enable();
6330 preempt_enable();
6331 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6332 r = 1;
6333 goto cancel_injection;
6334 }
6335
6336 if (req_immediate_exit)
6337 smp_send_reschedule(vcpu->cpu);
6338
6339 __kvm_guest_enter();
6340
6341 if (unlikely(vcpu->arch.switch_db_regs)) {
6342 set_debugreg(0, 7);
6343 set_debugreg(vcpu->arch.eff_db[0], 0);
6344 set_debugreg(vcpu->arch.eff_db[1], 1);
6345 set_debugreg(vcpu->arch.eff_db[2], 2);
6346 set_debugreg(vcpu->arch.eff_db[3], 3);
6347 set_debugreg(vcpu->arch.dr6, 6);
6348 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6349 }
6350
6351 trace_kvm_entry(vcpu->vcpu_id);
6352 wait_lapic_expire(vcpu);
6353 kvm_x86_ops->run(vcpu);
6354
6355 /*
6356 * Do this here before restoring debug registers on the host. And
6357 * since we do this before handling the vmexit, a DR access vmexit
6358 * can (a) read the correct value of the debug registers, (b) set
6359 * KVM_DEBUGREG_WONT_EXIT again.
6360 */
6361 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6362 int i;
6363
6364 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6365 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6366 for (i = 0; i < KVM_NR_DB_REGS; i++)
6367 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6368 }
6369
6370 /*
6371 * If the guest has used debug registers, at least dr7
6372 * will be disabled while returning to the host.
6373 * If we don't have active breakpoints in the host, we don't
6374 * care about the messed up debug address registers. But if
6375 * we have some of them active, restore the old state.
6376 */
6377 if (hw_breakpoint_active())
6378 hw_breakpoint_restore();
6379
6380 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6381 rdtsc());
6382
6383 vcpu->mode = OUTSIDE_GUEST_MODE;
6384 smp_wmb();
6385
6386 /* Interrupt is enabled by handle_external_intr() */
6387 kvm_x86_ops->handle_external_intr(vcpu);
6388
6389 ++vcpu->stat.exits;
6390
6391 /*
6392 * We must have an instruction between local_irq_enable() and
6393 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6394 * the interrupt shadow. The stat.exits increment will do nicely.
6395 * But we need to prevent reordering, hence this barrier():
6396 */
6397 barrier();
6398
6399 kvm_guest_exit();
6400
6401 preempt_enable();
6402
6403 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6404
6405 /*
6406 * Profile KVM exit RIPs:
6407 */
6408 if (unlikely(prof_on == KVM_PROFILING)) {
6409 unsigned long rip = kvm_rip_read(vcpu);
6410 profile_hit(KVM_PROFILING, (void *)rip);
6411 }
6412
6413 if (unlikely(vcpu->arch.tsc_always_catchup))
6414 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6415
6416 if (vcpu->arch.apic_attention)
6417 kvm_lapic_sync_from_vapic(vcpu);
6418
6419 r = kvm_x86_ops->handle_exit(vcpu);
6420 return r;
6421
6422 cancel_injection:
6423 kvm_x86_ops->cancel_injection(vcpu);
6424 if (unlikely(vcpu->arch.apic_attention))
6425 kvm_lapic_sync_from_vapic(vcpu);
6426 out:
6427 return r;
6428 }
6429
6430 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6431 {
6432 if (!kvm_arch_vcpu_runnable(vcpu)) {
6433 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6434 kvm_vcpu_block(vcpu);
6435 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6436 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6437 return 1;
6438 }
6439
6440 kvm_apic_accept_events(vcpu);
6441 switch(vcpu->arch.mp_state) {
6442 case KVM_MP_STATE_HALTED:
6443 vcpu->arch.pv.pv_unhalted = false;
6444 vcpu->arch.mp_state =
6445 KVM_MP_STATE_RUNNABLE;
6446 case KVM_MP_STATE_RUNNABLE:
6447 vcpu->arch.apf.halted = false;
6448 break;
6449 case KVM_MP_STATE_INIT_RECEIVED:
6450 break;
6451 default:
6452 return -EINTR;
6453 break;
6454 }
6455 return 1;
6456 }
6457
6458 static int vcpu_run(struct kvm_vcpu *vcpu)
6459 {
6460 int r;
6461 struct kvm *kvm = vcpu->kvm;
6462
6463 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6464
6465 for (;;) {
6466 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6467 !vcpu->arch.apf.halted)
6468 r = vcpu_enter_guest(vcpu);
6469 else
6470 r = vcpu_block(kvm, vcpu);
6471 if (r <= 0)
6472 break;
6473
6474 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6475 if (kvm_cpu_has_pending_timer(vcpu))
6476 kvm_inject_pending_timer_irqs(vcpu);
6477
6478 if (dm_request_for_irq_injection(vcpu)) {
6479 r = -EINTR;
6480 vcpu->run->exit_reason = KVM_EXIT_INTR;
6481 ++vcpu->stat.request_irq_exits;
6482 break;
6483 }
6484
6485 kvm_check_async_pf_completion(vcpu);
6486
6487 if (signal_pending(current)) {
6488 r = -EINTR;
6489 vcpu->run->exit_reason = KVM_EXIT_INTR;
6490 ++vcpu->stat.signal_exits;
6491 break;
6492 }
6493 if (need_resched()) {
6494 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6495 cond_resched();
6496 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6497 }
6498 }
6499
6500 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6501
6502 return r;
6503 }
6504
6505 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6506 {
6507 int r;
6508 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6509 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6510 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6511 if (r != EMULATE_DONE)
6512 return 0;
6513 return 1;
6514 }
6515
6516 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6517 {
6518 BUG_ON(!vcpu->arch.pio.count);
6519
6520 return complete_emulated_io(vcpu);
6521 }
6522
6523 /*
6524 * Implements the following, as a state machine:
6525 *
6526 * read:
6527 * for each fragment
6528 * for each mmio piece in the fragment
6529 * write gpa, len
6530 * exit
6531 * copy data
6532 * execute insn
6533 *
6534 * write:
6535 * for each fragment
6536 * for each mmio piece in the fragment
6537 * write gpa, len
6538 * copy data
6539 * exit
6540 */
6541 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6542 {
6543 struct kvm_run *run = vcpu->run;
6544 struct kvm_mmio_fragment *frag;
6545 unsigned len;
6546
6547 BUG_ON(!vcpu->mmio_needed);
6548
6549 /* Complete previous fragment */
6550 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6551 len = min(8u, frag->len);
6552 if (!vcpu->mmio_is_write)
6553 memcpy(frag->data, run->mmio.data, len);
6554
6555 if (frag->len <= 8) {
6556 /* Switch to the next fragment. */
6557 frag++;
6558 vcpu->mmio_cur_fragment++;
6559 } else {
6560 /* Go forward to the next mmio piece. */
6561 frag->data += len;
6562 frag->gpa += len;
6563 frag->len -= len;
6564 }
6565
6566 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6567 vcpu->mmio_needed = 0;
6568
6569 /* FIXME: return into emulator if single-stepping. */
6570 if (vcpu->mmio_is_write)
6571 return 1;
6572 vcpu->mmio_read_completed = 1;
6573 return complete_emulated_io(vcpu);
6574 }
6575
6576 run->exit_reason = KVM_EXIT_MMIO;
6577 run->mmio.phys_addr = frag->gpa;
6578 if (vcpu->mmio_is_write)
6579 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6580 run->mmio.len = min(8u, frag->len);
6581 run->mmio.is_write = vcpu->mmio_is_write;
6582 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6583 return 0;
6584 }
6585
6586
6587 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6588 {
6589 struct fpu *fpu = &current->thread.fpu;
6590 int r;
6591 sigset_t sigsaved;
6592
6593 fpu__activate_curr(fpu);
6594
6595 if (vcpu->sigset_active)
6596 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6597
6598 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6599 kvm_vcpu_block(vcpu);
6600 kvm_apic_accept_events(vcpu);
6601 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6602 r = -EAGAIN;
6603 goto out;
6604 }
6605
6606 /* re-sync apic's tpr */
6607 if (!irqchip_in_kernel(vcpu->kvm)) {
6608 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6609 r = -EINVAL;
6610 goto out;
6611 }
6612 }
6613
6614 if (unlikely(vcpu->arch.complete_userspace_io)) {
6615 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6616 vcpu->arch.complete_userspace_io = NULL;
6617 r = cui(vcpu);
6618 if (r <= 0)
6619 goto out;
6620 } else
6621 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6622
6623 r = vcpu_run(vcpu);
6624
6625 out:
6626 post_kvm_run_save(vcpu);
6627 if (vcpu->sigset_active)
6628 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6629
6630 return r;
6631 }
6632
6633 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6634 {
6635 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6636 /*
6637 * We are here if userspace calls get_regs() in the middle of
6638 * instruction emulation. Registers state needs to be copied
6639 * back from emulation context to vcpu. Userspace shouldn't do
6640 * that usually, but some bad designed PV devices (vmware
6641 * backdoor interface) need this to work
6642 */
6643 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6644 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6645 }
6646 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6647 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6648 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6649 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6650 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6651 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6652 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6653 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6654 #ifdef CONFIG_X86_64
6655 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6656 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6657 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6658 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6659 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6660 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6661 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6662 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6663 #endif
6664
6665 regs->rip = kvm_rip_read(vcpu);
6666 regs->rflags = kvm_get_rflags(vcpu);
6667
6668 return 0;
6669 }
6670
6671 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6672 {
6673 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6674 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6675
6676 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6677 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6678 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6679 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6680 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6681 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6682 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6683 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6684 #ifdef CONFIG_X86_64
6685 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6686 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6687 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6688 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6689 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6690 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6691 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6692 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6693 #endif
6694
6695 kvm_rip_write(vcpu, regs->rip);
6696 kvm_set_rflags(vcpu, regs->rflags);
6697
6698 vcpu->arch.exception.pending = false;
6699
6700 kvm_make_request(KVM_REQ_EVENT, vcpu);
6701
6702 return 0;
6703 }
6704
6705 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6706 {
6707 struct kvm_segment cs;
6708
6709 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6710 *db = cs.db;
6711 *l = cs.l;
6712 }
6713 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6714
6715 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6716 struct kvm_sregs *sregs)
6717 {
6718 struct desc_ptr dt;
6719
6720 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6721 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6722 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6723 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6724 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6725 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6726
6727 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6728 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6729
6730 kvm_x86_ops->get_idt(vcpu, &dt);
6731 sregs->idt.limit = dt.size;
6732 sregs->idt.base = dt.address;
6733 kvm_x86_ops->get_gdt(vcpu, &dt);
6734 sregs->gdt.limit = dt.size;
6735 sregs->gdt.base = dt.address;
6736
6737 sregs->cr0 = kvm_read_cr0(vcpu);
6738 sregs->cr2 = vcpu->arch.cr2;
6739 sregs->cr3 = kvm_read_cr3(vcpu);
6740 sregs->cr4 = kvm_read_cr4(vcpu);
6741 sregs->cr8 = kvm_get_cr8(vcpu);
6742 sregs->efer = vcpu->arch.efer;
6743 sregs->apic_base = kvm_get_apic_base(vcpu);
6744
6745 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6746
6747 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6748 set_bit(vcpu->arch.interrupt.nr,
6749 (unsigned long *)sregs->interrupt_bitmap);
6750
6751 return 0;
6752 }
6753
6754 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6755 struct kvm_mp_state *mp_state)
6756 {
6757 kvm_apic_accept_events(vcpu);
6758 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6759 vcpu->arch.pv.pv_unhalted)
6760 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6761 else
6762 mp_state->mp_state = vcpu->arch.mp_state;
6763
6764 return 0;
6765 }
6766
6767 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6768 struct kvm_mp_state *mp_state)
6769 {
6770 if (!kvm_vcpu_has_lapic(vcpu) &&
6771 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6772 return -EINVAL;
6773
6774 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6775 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6776 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6777 } else
6778 vcpu->arch.mp_state = mp_state->mp_state;
6779 kvm_make_request(KVM_REQ_EVENT, vcpu);
6780 return 0;
6781 }
6782
6783 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6784 int reason, bool has_error_code, u32 error_code)
6785 {
6786 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6787 int ret;
6788
6789 init_emulate_ctxt(vcpu);
6790
6791 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6792 has_error_code, error_code);
6793
6794 if (ret)
6795 return EMULATE_FAIL;
6796
6797 kvm_rip_write(vcpu, ctxt->eip);
6798 kvm_set_rflags(vcpu, ctxt->eflags);
6799 kvm_make_request(KVM_REQ_EVENT, vcpu);
6800 return EMULATE_DONE;
6801 }
6802 EXPORT_SYMBOL_GPL(kvm_task_switch);
6803
6804 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6805 struct kvm_sregs *sregs)
6806 {
6807 struct msr_data apic_base_msr;
6808 int mmu_reset_needed = 0;
6809 int pending_vec, max_bits, idx;
6810 struct desc_ptr dt;
6811
6812 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6813 return -EINVAL;
6814
6815 dt.size = sregs->idt.limit;
6816 dt.address = sregs->idt.base;
6817 kvm_x86_ops->set_idt(vcpu, &dt);
6818 dt.size = sregs->gdt.limit;
6819 dt.address = sregs->gdt.base;
6820 kvm_x86_ops->set_gdt(vcpu, &dt);
6821
6822 vcpu->arch.cr2 = sregs->cr2;
6823 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6824 vcpu->arch.cr3 = sregs->cr3;
6825 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6826
6827 kvm_set_cr8(vcpu, sregs->cr8);
6828
6829 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6830 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6831 apic_base_msr.data = sregs->apic_base;
6832 apic_base_msr.host_initiated = true;
6833 kvm_set_apic_base(vcpu, &apic_base_msr);
6834
6835 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6836 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6837 vcpu->arch.cr0 = sregs->cr0;
6838
6839 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6840 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6841 if (sregs->cr4 & X86_CR4_OSXSAVE)
6842 kvm_update_cpuid(vcpu);
6843
6844 idx = srcu_read_lock(&vcpu->kvm->srcu);
6845 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6846 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6847 mmu_reset_needed = 1;
6848 }
6849 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6850
6851 if (mmu_reset_needed)
6852 kvm_mmu_reset_context(vcpu);
6853
6854 max_bits = KVM_NR_INTERRUPTS;
6855 pending_vec = find_first_bit(
6856 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6857 if (pending_vec < max_bits) {
6858 kvm_queue_interrupt(vcpu, pending_vec, false);
6859 pr_debug("Set back pending irq %d\n", pending_vec);
6860 }
6861
6862 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6863 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6864 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6865 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6866 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6867 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6868
6869 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6870 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6871
6872 update_cr8_intercept(vcpu);
6873
6874 /* Older userspace won't unhalt the vcpu on reset. */
6875 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6876 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6877 !is_protmode(vcpu))
6878 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6879
6880 kvm_make_request(KVM_REQ_EVENT, vcpu);
6881
6882 return 0;
6883 }
6884
6885 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6886 struct kvm_guest_debug *dbg)
6887 {
6888 unsigned long rflags;
6889 int i, r;
6890
6891 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6892 r = -EBUSY;
6893 if (vcpu->arch.exception.pending)
6894 goto out;
6895 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6896 kvm_queue_exception(vcpu, DB_VECTOR);
6897 else
6898 kvm_queue_exception(vcpu, BP_VECTOR);
6899 }
6900
6901 /*
6902 * Read rflags as long as potentially injected trace flags are still
6903 * filtered out.
6904 */
6905 rflags = kvm_get_rflags(vcpu);
6906
6907 vcpu->guest_debug = dbg->control;
6908 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6909 vcpu->guest_debug = 0;
6910
6911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6912 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6913 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6914 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6915 } else {
6916 for (i = 0; i < KVM_NR_DB_REGS; i++)
6917 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6918 }
6919 kvm_update_dr7(vcpu);
6920
6921 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6922 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6923 get_segment_base(vcpu, VCPU_SREG_CS);
6924
6925 /*
6926 * Trigger an rflags update that will inject or remove the trace
6927 * flags.
6928 */
6929 kvm_set_rflags(vcpu, rflags);
6930
6931 kvm_x86_ops->update_db_bp_intercept(vcpu);
6932
6933 r = 0;
6934
6935 out:
6936
6937 return r;
6938 }
6939
6940 /*
6941 * Translate a guest virtual address to a guest physical address.
6942 */
6943 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6944 struct kvm_translation *tr)
6945 {
6946 unsigned long vaddr = tr->linear_address;
6947 gpa_t gpa;
6948 int idx;
6949
6950 idx = srcu_read_lock(&vcpu->kvm->srcu);
6951 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6952 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6953 tr->physical_address = gpa;
6954 tr->valid = gpa != UNMAPPED_GVA;
6955 tr->writeable = 1;
6956 tr->usermode = 0;
6957
6958 return 0;
6959 }
6960
6961 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6962 {
6963 struct fxregs_state *fxsave =
6964 &vcpu->arch.guest_fpu.state.fxsave;
6965
6966 memcpy(fpu->fpr, fxsave->st_space, 128);
6967 fpu->fcw = fxsave->cwd;
6968 fpu->fsw = fxsave->swd;
6969 fpu->ftwx = fxsave->twd;
6970 fpu->last_opcode = fxsave->fop;
6971 fpu->last_ip = fxsave->rip;
6972 fpu->last_dp = fxsave->rdp;
6973 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6974
6975 return 0;
6976 }
6977
6978 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6979 {
6980 struct fxregs_state *fxsave =
6981 &vcpu->arch.guest_fpu.state.fxsave;
6982
6983 memcpy(fxsave->st_space, fpu->fpr, 128);
6984 fxsave->cwd = fpu->fcw;
6985 fxsave->swd = fpu->fsw;
6986 fxsave->twd = fpu->ftwx;
6987 fxsave->fop = fpu->last_opcode;
6988 fxsave->rip = fpu->last_ip;
6989 fxsave->rdp = fpu->last_dp;
6990 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6991
6992 return 0;
6993 }
6994
6995 static void fx_init(struct kvm_vcpu *vcpu)
6996 {
6997 fpstate_init(&vcpu->arch.guest_fpu.state);
6998 if (cpu_has_xsaves)
6999 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7000 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7001
7002 /*
7003 * Ensure guest xcr0 is valid for loading
7004 */
7005 vcpu->arch.xcr0 = XSTATE_FP;
7006
7007 vcpu->arch.cr0 |= X86_CR0_ET;
7008 }
7009
7010 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7011 {
7012 if (vcpu->guest_fpu_loaded)
7013 return;
7014
7015 /*
7016 * Restore all possible states in the guest,
7017 * and assume host would use all available bits.
7018 * Guest xcr0 would be loaded later.
7019 */
7020 kvm_put_guest_xcr0(vcpu);
7021 vcpu->guest_fpu_loaded = 1;
7022 __kernel_fpu_begin();
7023 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7024 trace_kvm_fpu(1);
7025 }
7026
7027 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7028 {
7029 kvm_put_guest_xcr0(vcpu);
7030
7031 if (!vcpu->guest_fpu_loaded) {
7032 vcpu->fpu_counter = 0;
7033 return;
7034 }
7035
7036 vcpu->guest_fpu_loaded = 0;
7037 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7038 __kernel_fpu_end();
7039 ++vcpu->stat.fpu_reload;
7040 /*
7041 * If using eager FPU mode, or if the guest is a frequent user
7042 * of the FPU, just leave the FPU active for next time.
7043 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7044 * the FPU in bursts will revert to loading it on demand.
7045 */
7046 if (!vcpu->arch.eager_fpu) {
7047 if (++vcpu->fpu_counter < 5)
7048 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7049 }
7050 trace_kvm_fpu(0);
7051 }
7052
7053 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7054 {
7055 kvmclock_reset(vcpu);
7056
7057 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7058 kvm_x86_ops->vcpu_free(vcpu);
7059 }
7060
7061 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7062 unsigned int id)
7063 {
7064 struct kvm_vcpu *vcpu;
7065
7066 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7067 printk_once(KERN_WARNING
7068 "kvm: SMP vm created on host with unstable TSC; "
7069 "guest TSC will not be reliable\n");
7070
7071 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7072
7073 return vcpu;
7074 }
7075
7076 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7077 {
7078 int r;
7079
7080 kvm_vcpu_mtrr_init(vcpu);
7081 r = vcpu_load(vcpu);
7082 if (r)
7083 return r;
7084 kvm_vcpu_reset(vcpu, false);
7085 kvm_mmu_setup(vcpu);
7086 vcpu_put(vcpu);
7087 return r;
7088 }
7089
7090 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7091 {
7092 struct msr_data msr;
7093 struct kvm *kvm = vcpu->kvm;
7094
7095 if (vcpu_load(vcpu))
7096 return;
7097 msr.data = 0x0;
7098 msr.index = MSR_IA32_TSC;
7099 msr.host_initiated = true;
7100 kvm_write_tsc(vcpu, &msr);
7101 vcpu_put(vcpu);
7102
7103 if (!kvmclock_periodic_sync)
7104 return;
7105
7106 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7107 KVMCLOCK_SYNC_PERIOD);
7108 }
7109
7110 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7111 {
7112 int r;
7113 vcpu->arch.apf.msr_val = 0;
7114
7115 r = vcpu_load(vcpu);
7116 BUG_ON(r);
7117 kvm_mmu_unload(vcpu);
7118 vcpu_put(vcpu);
7119
7120 kvm_x86_ops->vcpu_free(vcpu);
7121 }
7122
7123 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7124 {
7125 vcpu->arch.hflags = 0;
7126
7127 atomic_set(&vcpu->arch.nmi_queued, 0);
7128 vcpu->arch.nmi_pending = 0;
7129 vcpu->arch.nmi_injected = false;
7130 kvm_clear_interrupt_queue(vcpu);
7131 kvm_clear_exception_queue(vcpu);
7132
7133 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7134 kvm_update_dr0123(vcpu);
7135 vcpu->arch.dr6 = DR6_INIT;
7136 kvm_update_dr6(vcpu);
7137 vcpu->arch.dr7 = DR7_FIXED_1;
7138 kvm_update_dr7(vcpu);
7139
7140 vcpu->arch.cr2 = 0;
7141
7142 kvm_make_request(KVM_REQ_EVENT, vcpu);
7143 vcpu->arch.apf.msr_val = 0;
7144 vcpu->arch.st.msr_val = 0;
7145
7146 kvmclock_reset(vcpu);
7147
7148 kvm_clear_async_pf_completion_queue(vcpu);
7149 kvm_async_pf_hash_reset(vcpu);
7150 vcpu->arch.apf.halted = false;
7151
7152 if (!init_event) {
7153 kvm_pmu_reset(vcpu);
7154 vcpu->arch.smbase = 0x30000;
7155 }
7156
7157 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7158 vcpu->arch.regs_avail = ~0;
7159 vcpu->arch.regs_dirty = ~0;
7160
7161 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7162 }
7163
7164 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7165 {
7166 struct kvm_segment cs;
7167
7168 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7169 cs.selector = vector << 8;
7170 cs.base = vector << 12;
7171 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7172 kvm_rip_write(vcpu, 0);
7173 }
7174
7175 int kvm_arch_hardware_enable(void)
7176 {
7177 struct kvm *kvm;
7178 struct kvm_vcpu *vcpu;
7179 int i;
7180 int ret;
7181 u64 local_tsc;
7182 u64 max_tsc = 0;
7183 bool stable, backwards_tsc = false;
7184
7185 kvm_shared_msr_cpu_online();
7186 ret = kvm_x86_ops->hardware_enable();
7187 if (ret != 0)
7188 return ret;
7189
7190 local_tsc = rdtsc();
7191 stable = !check_tsc_unstable();
7192 list_for_each_entry(kvm, &vm_list, vm_list) {
7193 kvm_for_each_vcpu(i, vcpu, kvm) {
7194 if (!stable && vcpu->cpu == smp_processor_id())
7195 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7196 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7197 backwards_tsc = true;
7198 if (vcpu->arch.last_host_tsc > max_tsc)
7199 max_tsc = vcpu->arch.last_host_tsc;
7200 }
7201 }
7202 }
7203
7204 /*
7205 * Sometimes, even reliable TSCs go backwards. This happens on
7206 * platforms that reset TSC during suspend or hibernate actions, but
7207 * maintain synchronization. We must compensate. Fortunately, we can
7208 * detect that condition here, which happens early in CPU bringup,
7209 * before any KVM threads can be running. Unfortunately, we can't
7210 * bring the TSCs fully up to date with real time, as we aren't yet far
7211 * enough into CPU bringup that we know how much real time has actually
7212 * elapsed; our helper function, get_kernel_ns() will be using boot
7213 * variables that haven't been updated yet.
7214 *
7215 * So we simply find the maximum observed TSC above, then record the
7216 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7217 * the adjustment will be applied. Note that we accumulate
7218 * adjustments, in case multiple suspend cycles happen before some VCPU
7219 * gets a chance to run again. In the event that no KVM threads get a
7220 * chance to run, we will miss the entire elapsed period, as we'll have
7221 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7222 * loose cycle time. This isn't too big a deal, since the loss will be
7223 * uniform across all VCPUs (not to mention the scenario is extremely
7224 * unlikely). It is possible that a second hibernate recovery happens
7225 * much faster than a first, causing the observed TSC here to be
7226 * smaller; this would require additional padding adjustment, which is
7227 * why we set last_host_tsc to the local tsc observed here.
7228 *
7229 * N.B. - this code below runs only on platforms with reliable TSC,
7230 * as that is the only way backwards_tsc is set above. Also note
7231 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7232 * have the same delta_cyc adjustment applied if backwards_tsc
7233 * is detected. Note further, this adjustment is only done once,
7234 * as we reset last_host_tsc on all VCPUs to stop this from being
7235 * called multiple times (one for each physical CPU bringup).
7236 *
7237 * Platforms with unreliable TSCs don't have to deal with this, they
7238 * will be compensated by the logic in vcpu_load, which sets the TSC to
7239 * catchup mode. This will catchup all VCPUs to real time, but cannot
7240 * guarantee that they stay in perfect synchronization.
7241 */
7242 if (backwards_tsc) {
7243 u64 delta_cyc = max_tsc - local_tsc;
7244 backwards_tsc_observed = true;
7245 list_for_each_entry(kvm, &vm_list, vm_list) {
7246 kvm_for_each_vcpu(i, vcpu, kvm) {
7247 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7248 vcpu->arch.last_host_tsc = local_tsc;
7249 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7250 }
7251
7252 /*
7253 * We have to disable TSC offset matching.. if you were
7254 * booting a VM while issuing an S4 host suspend....
7255 * you may have some problem. Solving this issue is
7256 * left as an exercise to the reader.
7257 */
7258 kvm->arch.last_tsc_nsec = 0;
7259 kvm->arch.last_tsc_write = 0;
7260 }
7261
7262 }
7263 return 0;
7264 }
7265
7266 void kvm_arch_hardware_disable(void)
7267 {
7268 kvm_x86_ops->hardware_disable();
7269 drop_user_return_notifiers();
7270 }
7271
7272 int kvm_arch_hardware_setup(void)
7273 {
7274 int r;
7275
7276 r = kvm_x86_ops->hardware_setup();
7277 if (r != 0)
7278 return r;
7279
7280 kvm_init_msr_list();
7281 return 0;
7282 }
7283
7284 void kvm_arch_hardware_unsetup(void)
7285 {
7286 kvm_x86_ops->hardware_unsetup();
7287 }
7288
7289 void kvm_arch_check_processor_compat(void *rtn)
7290 {
7291 kvm_x86_ops->check_processor_compatibility(rtn);
7292 }
7293
7294 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7295 {
7296 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7297 }
7298 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7299
7300 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7301 {
7302 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7303 }
7304
7305 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7306 {
7307 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7308 }
7309
7310 struct static_key kvm_no_apic_vcpu __read_mostly;
7311
7312 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7313 {
7314 struct page *page;
7315 struct kvm *kvm;
7316 int r;
7317
7318 BUG_ON(vcpu->kvm == NULL);
7319 kvm = vcpu->kvm;
7320
7321 vcpu->arch.pv.pv_unhalted = false;
7322 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7323 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7324 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7325 else
7326 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7327
7328 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7329 if (!page) {
7330 r = -ENOMEM;
7331 goto fail;
7332 }
7333 vcpu->arch.pio_data = page_address(page);
7334
7335 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7336
7337 r = kvm_mmu_create(vcpu);
7338 if (r < 0)
7339 goto fail_free_pio_data;
7340
7341 if (irqchip_in_kernel(kvm)) {
7342 r = kvm_create_lapic(vcpu);
7343 if (r < 0)
7344 goto fail_mmu_destroy;
7345 } else
7346 static_key_slow_inc(&kvm_no_apic_vcpu);
7347
7348 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7349 GFP_KERNEL);
7350 if (!vcpu->arch.mce_banks) {
7351 r = -ENOMEM;
7352 goto fail_free_lapic;
7353 }
7354 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7355
7356 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7357 r = -ENOMEM;
7358 goto fail_free_mce_banks;
7359 }
7360
7361 fx_init(vcpu);
7362
7363 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7364 vcpu->arch.pv_time_enabled = false;
7365
7366 vcpu->arch.guest_supported_xcr0 = 0;
7367 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7368
7369 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7370
7371 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7372
7373 kvm_async_pf_hash_reset(vcpu);
7374 kvm_pmu_init(vcpu);
7375
7376 return 0;
7377
7378 fail_free_mce_banks:
7379 kfree(vcpu->arch.mce_banks);
7380 fail_free_lapic:
7381 kvm_free_lapic(vcpu);
7382 fail_mmu_destroy:
7383 kvm_mmu_destroy(vcpu);
7384 fail_free_pio_data:
7385 free_page((unsigned long)vcpu->arch.pio_data);
7386 fail:
7387 return r;
7388 }
7389
7390 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7391 {
7392 int idx;
7393
7394 kvm_pmu_destroy(vcpu);
7395 kfree(vcpu->arch.mce_banks);
7396 kvm_free_lapic(vcpu);
7397 idx = srcu_read_lock(&vcpu->kvm->srcu);
7398 kvm_mmu_destroy(vcpu);
7399 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7400 free_page((unsigned long)vcpu->arch.pio_data);
7401 if (!irqchip_in_kernel(vcpu->kvm))
7402 static_key_slow_dec(&kvm_no_apic_vcpu);
7403 }
7404
7405 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7406 {
7407 kvm_x86_ops->sched_in(vcpu, cpu);
7408 }
7409
7410 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7411 {
7412 if (type)
7413 return -EINVAL;
7414
7415 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7416 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7417 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7418 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7419 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7420
7421 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7422 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7423 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7424 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7425 &kvm->arch.irq_sources_bitmap);
7426
7427 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7428 mutex_init(&kvm->arch.apic_map_lock);
7429 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7430
7431 pvclock_update_vm_gtod_copy(kvm);
7432
7433 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7434 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7435
7436 return 0;
7437 }
7438
7439 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7440 {
7441 int r;
7442 r = vcpu_load(vcpu);
7443 BUG_ON(r);
7444 kvm_mmu_unload(vcpu);
7445 vcpu_put(vcpu);
7446 }
7447
7448 static void kvm_free_vcpus(struct kvm *kvm)
7449 {
7450 unsigned int i;
7451 struct kvm_vcpu *vcpu;
7452
7453 /*
7454 * Unpin any mmu pages first.
7455 */
7456 kvm_for_each_vcpu(i, vcpu, kvm) {
7457 kvm_clear_async_pf_completion_queue(vcpu);
7458 kvm_unload_vcpu_mmu(vcpu);
7459 }
7460 kvm_for_each_vcpu(i, vcpu, kvm)
7461 kvm_arch_vcpu_free(vcpu);
7462
7463 mutex_lock(&kvm->lock);
7464 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7465 kvm->vcpus[i] = NULL;
7466
7467 atomic_set(&kvm->online_vcpus, 0);
7468 mutex_unlock(&kvm->lock);
7469 }
7470
7471 void kvm_arch_sync_events(struct kvm *kvm)
7472 {
7473 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7474 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7475 kvm_free_all_assigned_devices(kvm);
7476 kvm_free_pit(kvm);
7477 }
7478
7479 int __x86_set_memory_region(struct kvm *kvm,
7480 const struct kvm_userspace_memory_region *mem)
7481 {
7482 int i, r;
7483
7484 /* Called with kvm->slots_lock held. */
7485 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7486
7487 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7488 struct kvm_userspace_memory_region m = *mem;
7489
7490 m.slot |= i << 16;
7491 r = __kvm_set_memory_region(kvm, &m);
7492 if (r < 0)
7493 return r;
7494 }
7495
7496 return 0;
7497 }
7498 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7499
7500 int x86_set_memory_region(struct kvm *kvm,
7501 const struct kvm_userspace_memory_region *mem)
7502 {
7503 int r;
7504
7505 mutex_lock(&kvm->slots_lock);
7506 r = __x86_set_memory_region(kvm, mem);
7507 mutex_unlock(&kvm->slots_lock);
7508
7509 return r;
7510 }
7511 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7512
7513 void kvm_arch_destroy_vm(struct kvm *kvm)
7514 {
7515 if (current->mm == kvm->mm) {
7516 /*
7517 * Free memory regions allocated on behalf of userspace,
7518 * unless the the memory map has changed due to process exit
7519 * or fd copying.
7520 */
7521 struct kvm_userspace_memory_region mem;
7522 memset(&mem, 0, sizeof(mem));
7523 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7524 x86_set_memory_region(kvm, &mem);
7525
7526 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7527 x86_set_memory_region(kvm, &mem);
7528
7529 mem.slot = TSS_PRIVATE_MEMSLOT;
7530 x86_set_memory_region(kvm, &mem);
7531 }
7532 kvm_iommu_unmap_guest(kvm);
7533 kfree(kvm->arch.vpic);
7534 kfree(kvm->arch.vioapic);
7535 kvm_free_vcpus(kvm);
7536 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7537 }
7538
7539 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7540 struct kvm_memory_slot *dont)
7541 {
7542 int i;
7543
7544 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7545 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7546 kvfree(free->arch.rmap[i]);
7547 free->arch.rmap[i] = NULL;
7548 }
7549 if (i == 0)
7550 continue;
7551
7552 if (!dont || free->arch.lpage_info[i - 1] !=
7553 dont->arch.lpage_info[i - 1]) {
7554 kvfree(free->arch.lpage_info[i - 1]);
7555 free->arch.lpage_info[i - 1] = NULL;
7556 }
7557 }
7558 }
7559
7560 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7561 unsigned long npages)
7562 {
7563 int i;
7564
7565 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7566 unsigned long ugfn;
7567 int lpages;
7568 int level = i + 1;
7569
7570 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7571 slot->base_gfn, level) + 1;
7572
7573 slot->arch.rmap[i] =
7574 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7575 if (!slot->arch.rmap[i])
7576 goto out_free;
7577 if (i == 0)
7578 continue;
7579
7580 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7581 sizeof(*slot->arch.lpage_info[i - 1]));
7582 if (!slot->arch.lpage_info[i - 1])
7583 goto out_free;
7584
7585 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7586 slot->arch.lpage_info[i - 1][0].write_count = 1;
7587 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7588 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7589 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7590 /*
7591 * If the gfn and userspace address are not aligned wrt each
7592 * other, or if explicitly asked to, disable large page
7593 * support for this slot
7594 */
7595 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7596 !kvm_largepages_enabled()) {
7597 unsigned long j;
7598
7599 for (j = 0; j < lpages; ++j)
7600 slot->arch.lpage_info[i - 1][j].write_count = 1;
7601 }
7602 }
7603
7604 return 0;
7605
7606 out_free:
7607 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7608 kvfree(slot->arch.rmap[i]);
7609 slot->arch.rmap[i] = NULL;
7610 if (i == 0)
7611 continue;
7612
7613 kvfree(slot->arch.lpage_info[i - 1]);
7614 slot->arch.lpage_info[i - 1] = NULL;
7615 }
7616 return -ENOMEM;
7617 }
7618
7619 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7620 {
7621 /*
7622 * memslots->generation has been incremented.
7623 * mmio generation may have reached its maximum value.
7624 */
7625 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7626 }
7627
7628 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7629 struct kvm_memory_slot *memslot,
7630 const struct kvm_userspace_memory_region *mem,
7631 enum kvm_mr_change change)
7632 {
7633 /*
7634 * Only private memory slots need to be mapped here since
7635 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7636 */
7637 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7638 unsigned long userspace_addr;
7639
7640 /*
7641 * MAP_SHARED to prevent internal slot pages from being moved
7642 * by fork()/COW.
7643 */
7644 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7645 PROT_READ | PROT_WRITE,
7646 MAP_SHARED | MAP_ANONYMOUS, 0);
7647
7648 if (IS_ERR((void *)userspace_addr))
7649 return PTR_ERR((void *)userspace_addr);
7650
7651 memslot->userspace_addr = userspace_addr;
7652 }
7653
7654 return 0;
7655 }
7656
7657 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7658 struct kvm_memory_slot *new)
7659 {
7660 /* Still write protect RO slot */
7661 if (new->flags & KVM_MEM_READONLY) {
7662 kvm_mmu_slot_remove_write_access(kvm, new);
7663 return;
7664 }
7665
7666 /*
7667 * Call kvm_x86_ops dirty logging hooks when they are valid.
7668 *
7669 * kvm_x86_ops->slot_disable_log_dirty is called when:
7670 *
7671 * - KVM_MR_CREATE with dirty logging is disabled
7672 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7673 *
7674 * The reason is, in case of PML, we need to set D-bit for any slots
7675 * with dirty logging disabled in order to eliminate unnecessary GPA
7676 * logging in PML buffer (and potential PML buffer full VMEXT). This
7677 * guarantees leaving PML enabled during guest's lifetime won't have
7678 * any additonal overhead from PML when guest is running with dirty
7679 * logging disabled for memory slots.
7680 *
7681 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7682 * to dirty logging mode.
7683 *
7684 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7685 *
7686 * In case of write protect:
7687 *
7688 * Write protect all pages for dirty logging.
7689 *
7690 * All the sptes including the large sptes which point to this
7691 * slot are set to readonly. We can not create any new large
7692 * spte on this slot until the end of the logging.
7693 *
7694 * See the comments in fast_page_fault().
7695 */
7696 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7697 if (kvm_x86_ops->slot_enable_log_dirty)
7698 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7699 else
7700 kvm_mmu_slot_remove_write_access(kvm, new);
7701 } else {
7702 if (kvm_x86_ops->slot_disable_log_dirty)
7703 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7704 }
7705 }
7706
7707 void kvm_arch_commit_memory_region(struct kvm *kvm,
7708 const struct kvm_userspace_memory_region *mem,
7709 const struct kvm_memory_slot *old,
7710 const struct kvm_memory_slot *new,
7711 enum kvm_mr_change change)
7712 {
7713 int nr_mmu_pages = 0;
7714
7715 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
7716 int ret;
7717
7718 ret = vm_munmap(old->userspace_addr,
7719 old->npages * PAGE_SIZE);
7720 if (ret < 0)
7721 printk(KERN_WARNING
7722 "kvm_vm_ioctl_set_memory_region: "
7723 "failed to munmap memory\n");
7724 }
7725
7726 if (!kvm->arch.n_requested_mmu_pages)
7727 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7728
7729 if (nr_mmu_pages)
7730 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7731
7732 /*
7733 * Dirty logging tracks sptes in 4k granularity, meaning that large
7734 * sptes have to be split. If live migration is successful, the guest
7735 * in the source machine will be destroyed and large sptes will be
7736 * created in the destination. However, if the guest continues to run
7737 * in the source machine (for example if live migration fails), small
7738 * sptes will remain around and cause bad performance.
7739 *
7740 * Scan sptes if dirty logging has been stopped, dropping those
7741 * which can be collapsed into a single large-page spte. Later
7742 * page faults will create the large-page sptes.
7743 */
7744 if ((change != KVM_MR_DELETE) &&
7745 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7746 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7747 kvm_mmu_zap_collapsible_sptes(kvm, new);
7748
7749 /*
7750 * Set up write protection and/or dirty logging for the new slot.
7751 *
7752 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7753 * been zapped so no dirty logging staff is needed for old slot. For
7754 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7755 * new and it's also covered when dealing with the new slot.
7756 *
7757 * FIXME: const-ify all uses of struct kvm_memory_slot.
7758 */
7759 if (change != KVM_MR_DELETE)
7760 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7761 }
7762
7763 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7764 {
7765 kvm_mmu_invalidate_zap_all_pages(kvm);
7766 }
7767
7768 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7769 struct kvm_memory_slot *slot)
7770 {
7771 kvm_mmu_invalidate_zap_all_pages(kvm);
7772 }
7773
7774 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7775 {
7776 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7777 kvm_x86_ops->check_nested_events(vcpu, false);
7778
7779 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7780 !vcpu->arch.apf.halted)
7781 || !list_empty_careful(&vcpu->async_pf.done)
7782 || kvm_apic_has_events(vcpu)
7783 || vcpu->arch.pv.pv_unhalted
7784 || atomic_read(&vcpu->arch.nmi_queued) ||
7785 (kvm_arch_interrupt_allowed(vcpu) &&
7786 kvm_cpu_has_interrupt(vcpu));
7787 }
7788
7789 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7790 {
7791 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7792 }
7793
7794 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7795 {
7796 return kvm_x86_ops->interrupt_allowed(vcpu);
7797 }
7798
7799 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7800 {
7801 if (is_64_bit_mode(vcpu))
7802 return kvm_rip_read(vcpu);
7803 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7804 kvm_rip_read(vcpu));
7805 }
7806 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7807
7808 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7809 {
7810 return kvm_get_linear_rip(vcpu) == linear_rip;
7811 }
7812 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7813
7814 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7815 {
7816 unsigned long rflags;
7817
7818 rflags = kvm_x86_ops->get_rflags(vcpu);
7819 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7820 rflags &= ~X86_EFLAGS_TF;
7821 return rflags;
7822 }
7823 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7824
7825 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7826 {
7827 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7828 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7829 rflags |= X86_EFLAGS_TF;
7830 kvm_x86_ops->set_rflags(vcpu, rflags);
7831 }
7832
7833 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7834 {
7835 __kvm_set_rflags(vcpu, rflags);
7836 kvm_make_request(KVM_REQ_EVENT, vcpu);
7837 }
7838 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7839
7840 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7841 {
7842 int r;
7843
7844 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7845 work->wakeup_all)
7846 return;
7847
7848 r = kvm_mmu_reload(vcpu);
7849 if (unlikely(r))
7850 return;
7851
7852 if (!vcpu->arch.mmu.direct_map &&
7853 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7854 return;
7855
7856 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7857 }
7858
7859 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7860 {
7861 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7862 }
7863
7864 static inline u32 kvm_async_pf_next_probe(u32 key)
7865 {
7866 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7867 }
7868
7869 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7870 {
7871 u32 key = kvm_async_pf_hash_fn(gfn);
7872
7873 while (vcpu->arch.apf.gfns[key] != ~0)
7874 key = kvm_async_pf_next_probe(key);
7875
7876 vcpu->arch.apf.gfns[key] = gfn;
7877 }
7878
7879 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7880 {
7881 int i;
7882 u32 key = kvm_async_pf_hash_fn(gfn);
7883
7884 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7885 (vcpu->arch.apf.gfns[key] != gfn &&
7886 vcpu->arch.apf.gfns[key] != ~0); i++)
7887 key = kvm_async_pf_next_probe(key);
7888
7889 return key;
7890 }
7891
7892 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7893 {
7894 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7895 }
7896
7897 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7898 {
7899 u32 i, j, k;
7900
7901 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7902 while (true) {
7903 vcpu->arch.apf.gfns[i] = ~0;
7904 do {
7905 j = kvm_async_pf_next_probe(j);
7906 if (vcpu->arch.apf.gfns[j] == ~0)
7907 return;
7908 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7909 /*
7910 * k lies cyclically in ]i,j]
7911 * | i.k.j |
7912 * |....j i.k.| or |.k..j i...|
7913 */
7914 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7915 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7916 i = j;
7917 }
7918 }
7919
7920 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7921 {
7922
7923 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7924 sizeof(val));
7925 }
7926
7927 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7928 struct kvm_async_pf *work)
7929 {
7930 struct x86_exception fault;
7931
7932 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7933 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7934
7935 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7936 (vcpu->arch.apf.send_user_only &&
7937 kvm_x86_ops->get_cpl(vcpu) == 0))
7938 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7939 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7940 fault.vector = PF_VECTOR;
7941 fault.error_code_valid = true;
7942 fault.error_code = 0;
7943 fault.nested_page_fault = false;
7944 fault.address = work->arch.token;
7945 kvm_inject_page_fault(vcpu, &fault);
7946 }
7947 }
7948
7949 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7950 struct kvm_async_pf *work)
7951 {
7952 struct x86_exception fault;
7953
7954 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7955 if (work->wakeup_all)
7956 work->arch.token = ~0; /* broadcast wakeup */
7957 else
7958 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7959
7960 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7961 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7962 fault.vector = PF_VECTOR;
7963 fault.error_code_valid = true;
7964 fault.error_code = 0;
7965 fault.nested_page_fault = false;
7966 fault.address = work->arch.token;
7967 kvm_inject_page_fault(vcpu, &fault);
7968 }
7969 vcpu->arch.apf.halted = false;
7970 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7971 }
7972
7973 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7974 {
7975 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7976 return true;
7977 else
7978 return !kvm_event_needs_reinjection(vcpu) &&
7979 kvm_x86_ops->interrupt_allowed(vcpu);
7980 }
7981
7982 void kvm_arch_start_assignment(struct kvm *kvm)
7983 {
7984 atomic_inc(&kvm->arch.assigned_device_count);
7985 }
7986 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
7987
7988 void kvm_arch_end_assignment(struct kvm *kvm)
7989 {
7990 atomic_dec(&kvm->arch.assigned_device_count);
7991 }
7992 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
7993
7994 bool kvm_arch_has_assigned_device(struct kvm *kvm)
7995 {
7996 return atomic_read(&kvm->arch.assigned_device_count);
7997 }
7998 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
7999
8000 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8001 {
8002 atomic_inc(&kvm->arch.noncoherent_dma_count);
8003 }
8004 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8005
8006 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8007 {
8008 atomic_dec(&kvm->arch.noncoherent_dma_count);
8009 }
8010 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8011
8012 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8013 {
8014 return atomic_read(&kvm->arch.noncoherent_dma_count);
8015 }
8016 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8017
8018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8019 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8020 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8027 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8028 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8029 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8030 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8032 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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