x86, apic: refactor ->apic_id_mask & APIC_ID_MASK
[deliverable/linux.git] / arch / x86 / mach-generic / numaq.c
1 /*
2 * APIC driver for the IBM NUMAQ chipset.
3 */
4 #define APIC_DEFINITION 1
5 #include <linux/threads.h>
6 #include <linux/cpumask.h>
7 #include <asm/mpspec.h>
8 #include <asm/genapic.h>
9 #include <asm/fixmap.h>
10 #include <asm/apicdef.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <asm/numaq/apicdef.h>
15 #include <linux/smp.h>
16 #include <asm/numaq/apic.h>
17 #include <asm/numaq/ipi.h>
18 #include <asm/numaq/mpparse.h>
19 #include <asm/numaq/wakecpu.h>
20 #include <asm/numaq.h>
21
22 static int __numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
23 {
24 numaq_mps_oem_check(mpc, oem, productid);
25 return found_numaq;
26 }
27
28 static int probe_numaq(void)
29 {
30 /* already know from get_memcfg_numaq() */
31 return found_numaq;
32 }
33
34 static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask)
35 {
36 /* Careful. Some cpus do not strictly honor the set of cpus
37 * specified in the interrupt destination when using lowest
38 * priority interrupt delivery mode.
39 *
40 * In particular there was a hyperthreading cpu observed to
41 * deliver interrupts to the wrong hyperthread when only one
42 * hyperthread was specified in the interrupt desitination.
43 */
44 *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
45 }
46
47 static void numaq_setup_portio_remap(void)
48 {
49 int num_quads = num_online_nodes();
50
51 if (num_quads <= 1)
52 return;
53
54 printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
55 xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
56 printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
57 (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
58 }
59
60 struct genapic apic_numaq = {
61
62 .name = "NUMAQ",
63 .probe = probe_numaq,
64 .acpi_madt_oem_check = NULL,
65 .apic_id_registered = numaq_apic_id_registered,
66
67 .irq_delivery_mode = dest_LowestPrio,
68 /* physical delivery on LOCAL quad: */
69 .irq_dest_mode = 0,
70
71 .target_cpus = numaq_target_cpus,
72 .disable_esr = 1,
73 .dest_logical = APIC_DEST_LOGICAL,
74 .check_apicid_used = numaq_check_apicid_used,
75 .check_apicid_present = numaq_check_apicid_present,
76
77 .vector_allocation_domain = numaq_vector_allocation_domain,
78 .init_apic_ldr = numaq_init_apic_ldr,
79
80 .ioapic_phys_id_map = numaq_ioapic_phys_id_map,
81 .setup_apic_routing = numaq_setup_apic_routing,
82 .multi_timer_check = numaq_multi_timer_check,
83 .apicid_to_node = numaq_apicid_to_node,
84 .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid,
85 .cpu_present_to_apicid = numaq_cpu_present_to_apicid,
86 .apicid_to_cpu_present = numaq_apicid_to_cpu_present,
87 .setup_portio_remap = numaq_setup_portio_remap,
88 .check_phys_apicid_present = numaq_check_phys_apicid_present,
89 .enable_apic_mode = NULL,
90 .phys_pkg_id = numaq_phys_pkg_id,
91 .mps_oem_check = __numaq_mps_oem_check,
92
93 .get_apic_id = numaq_get_apic_id,
94 .set_apic_id = NULL,
95 .apic_id_mask = NUMAQ_APIC_ID_MASK,
96
97 .cpu_mask_to_apicid = cpu_mask_to_apicid,
98 .cpu_mask_to_apicid_and = cpu_mask_to_apicid_and,
99
100 .send_IPI_mask = send_IPI_mask,
101 .send_IPI_mask_allbutself = NULL,
102 .send_IPI_allbutself = send_IPI_allbutself,
103 .send_IPI_all = send_IPI_all,
104 .send_IPI_self = NULL,
105
106 .wakeup_cpu = NULL,
107 .trampoline_phys_low = TRAMPOLINE_PHYS_LOW,
108 .trampoline_phys_high = TRAMPOLINE_PHYS_HIGH,
109 .wait_for_init_deassert = wait_for_init_deassert,
110 .smp_callin_clear_local_apic = smp_callin_clear_local_apic,
111 .store_NMI_vector = store_NMI_vector,
112 .restore_NMI_vector = restore_NMI_vector,
113 .inquire_remote_apic = inquire_remote_apic,
114 };
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