2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
38 unsigned force_split
: 1;
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
49 static DEFINE_SPINLOCK(cpa_lock
);
51 #define CPA_FLUSHTLB 1
53 #define CPA_PAGES_ARRAY 4
56 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
58 void update_page_count(int level
, unsigned long pages
)
62 /* Protect against CPA */
63 spin_lock_irqsave(&pgd_lock
, flags
);
64 direct_pages_count
[level
] += pages
;
65 spin_unlock_irqrestore(&pgd_lock
, flags
);
68 static void split_page_count(int level
)
70 direct_pages_count
[level
]--;
71 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
74 void arch_report_meminfo(struct seq_file
*m
)
76 seq_printf(m
, "DirectMap4k: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_4K
] << 2);
78 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
79 seq_printf(m
, "DirectMap2M: %8lu kB\n",
80 direct_pages_count
[PG_LEVEL_2M
] << 11);
82 seq_printf(m
, "DirectMap4M: %8lu kB\n",
83 direct_pages_count
[PG_LEVEL_2M
] << 12);
87 seq_printf(m
, "DirectMap1G: %8lu kB\n",
88 direct_pages_count
[PG_LEVEL_1G
] << 20);
92 static inline void split_page_count(int level
) { }
97 static inline unsigned long highmap_start_pfn(void)
99 return __pa(_text
) >> PAGE_SHIFT
;
102 static inline unsigned long highmap_end_pfn(void)
104 return __pa(roundup(_brk_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
109 #ifdef CONFIG_DEBUG_PAGEALLOC
110 # define debug_pagealloc 1
112 # define debug_pagealloc 0
116 within(unsigned long addr
, unsigned long start
, unsigned long end
)
118 return addr
>= start
&& addr
< end
;
126 * clflush_cache_range - flush a cache range with clflush
127 * @addr: virtual start address
128 * @size: number of bytes to flush
130 * clflush is an unordered instruction which needs fencing with mfence
131 * to avoid ordering issues.
133 void clflush_cache_range(void *vaddr
, unsigned int size
)
135 void *vend
= vaddr
+ size
- 1;
139 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
142 * Flush any possible final partial cacheline:
148 EXPORT_SYMBOL_GPL(clflush_cache_range
);
150 static void __cpa_flush_all(void *arg
)
152 unsigned long cache
= (unsigned long)arg
;
155 * Flush all to work around Errata in early athlons regarding
156 * large page flushing.
160 if (cache
&& boot_cpu_data
.x86
>= 4)
164 static void cpa_flush_all(unsigned long cache
)
166 BUG_ON(irqs_disabled());
168 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
171 static void __cpa_flush_range(void *arg
)
174 * We could optimize that further and do individual per page
175 * tlb invalidates for a low number of pages. Caveat: we must
176 * flush the high aliases on 64bit as well.
181 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
183 unsigned int i
, level
;
186 BUG_ON(irqs_disabled());
187 WARN_ON(PAGE_ALIGN(start
) != start
);
189 on_each_cpu(__cpa_flush_range
, NULL
, 1);
195 * We only need to flush on one CPU,
196 * clflush is a MESI-coherent instruction that
197 * will cause all other CPUs to flush the same
200 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
201 pte_t
*pte
= lookup_address(addr
, &level
);
204 * Only flush present addresses:
206 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
207 clflush_cache_range((void *) addr
, PAGE_SIZE
);
211 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
,
212 int in_flags
, struct page
**pages
)
214 unsigned int i
, level
;
215 unsigned long do_wbinvd
= cache
&& numpages
>= 1024; /* 4M threshold */
217 BUG_ON(irqs_disabled());
219 on_each_cpu(__cpa_flush_all
, (void *) do_wbinvd
, 1);
221 if (!cache
|| do_wbinvd
)
225 * We only need to flush on one CPU,
226 * clflush is a MESI-coherent instruction that
227 * will cause all other CPUs to flush the same
230 for (i
= 0; i
< numpages
; i
++) {
234 if (in_flags
& CPA_PAGES_ARRAY
)
235 addr
= (unsigned long)page_address(pages
[i
]);
239 pte
= lookup_address(addr
, &level
);
242 * Only flush present addresses:
244 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
245 clflush_cache_range((void *)addr
, PAGE_SIZE
);
250 * Certain areas of memory on x86 require very specific protection flags,
251 * for example the BIOS area or kernel text. Callers don't always get this
252 * right (again, ioremap() on BIOS memory is not uncommon) so this function
253 * checks and fixes these known static required protection bits.
255 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
258 pgprot_t forbidden
= __pgprot(0);
261 * The BIOS area between 640k and 1Mb needs to be executable for
262 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
264 #ifdef CONFIG_PCI_BIOS
265 if (pcibios_enabled
&& within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
266 pgprot_val(forbidden
) |= _PAGE_NX
;
270 * The kernel text needs to be executable for obvious reasons
271 * Does not cover __inittext since that is gone later on. On
272 * 64bit we do not enforce !NX on the low mapping
274 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
275 pgprot_val(forbidden
) |= _PAGE_NX
;
278 * The .rodata section needs to be read-only. Using the pfn
279 * catches all aliases.
281 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
282 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
283 pgprot_val(forbidden
) |= _PAGE_RW
;
285 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
287 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
288 * kernel text mappings for the large page aligned text, rodata sections
289 * will be always read-only. For the kernel identity mappings covering
290 * the holes caused by this alignment can be anything that user asks.
292 * This will preserve the large page mappings for kernel text/data
295 if (kernel_set_to_readonly
&&
296 within(address
, (unsigned long)_text
,
297 (unsigned long)__end_rodata_hpage_align
)) {
301 * Don't enforce the !RW mapping for the kernel text mapping,
302 * if the current mapping is already using small page mapping.
303 * No need to work hard to preserve large page mappings in this
306 * This also fixes the Linux Xen paravirt guest boot failure
307 * (because of unexpected read-only mappings for kernel identity
308 * mappings). In this paravirt guest case, the kernel text
309 * mapping and the kernel identity mapping share the same
310 * page-table pages. Thus we can't really use different
311 * protections for the kernel text and identity mappings. Also,
312 * these shared mappings are made of small page mappings.
313 * Thus this don't enforce !RW mapping for small page kernel
314 * text mapping logic will help Linux Xen parvirt guest boot
317 if (lookup_address(address
, &level
) && (level
!= PG_LEVEL_4K
))
318 pgprot_val(forbidden
) |= _PAGE_RW
;
322 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
328 * Lookup the page table entry for a virtual address. Return a pointer
329 * to the entry and the level of the mapping.
331 * Note: We return pud and pmd either when the entry is marked large
332 * or when the present bit is not set. Otherwise we would return a
333 * pointer to a nonexisting mapping.
335 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
337 pgd_t
*pgd
= pgd_offset_k(address
);
341 *level
= PG_LEVEL_NONE
;
346 pud
= pud_offset(pgd
, address
);
350 *level
= PG_LEVEL_1G
;
351 if (pud_large(*pud
) || !pud_present(*pud
))
354 pmd
= pmd_offset(pud
, address
);
358 *level
= PG_LEVEL_2M
;
359 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
362 *level
= PG_LEVEL_4K
;
364 return pte_offset_kernel(pmd
, address
);
366 EXPORT_SYMBOL_GPL(lookup_address
);
369 * Set the new pmd in all the pgds we know about:
371 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
374 set_pte_atomic(kpte
, pte
);
376 if (!SHARED_KERNEL_PMD
) {
379 list_for_each_entry(page
, &pgd_list
, lru
) {
384 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
385 pud
= pud_offset(pgd
, address
);
386 pmd
= pmd_offset(pud
, address
);
387 set_pte_atomic((pte_t
*)pmd
, pte
);
394 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
395 struct cpa_data
*cpa
)
397 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
398 pte_t new_pte
, old_pte
, *tmp
;
399 pgprot_t old_prot
, new_prot
, req_prot
;
403 if (cpa
->force_split
)
406 spin_lock_irqsave(&pgd_lock
, flags
);
408 * Check for races, another CPU might have split this page
411 tmp
= lookup_address(address
, &level
);
417 psize
= PMD_PAGE_SIZE
;
418 pmask
= PMD_PAGE_MASK
;
422 psize
= PUD_PAGE_SIZE
;
423 pmask
= PUD_PAGE_MASK
;
432 * Calculate the number of pages, which fit into this large
433 * page starting at address:
435 nextpage_addr
= (address
+ psize
) & pmask
;
436 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
437 if (numpages
< cpa
->numpages
)
438 cpa
->numpages
= numpages
;
441 * We are safe now. Check whether the new pgprot is the same:
444 old_prot
= new_prot
= req_prot
= pte_pgprot(old_pte
);
446 pgprot_val(req_prot
) &= ~pgprot_val(cpa
->mask_clr
);
447 pgprot_val(req_prot
) |= pgprot_val(cpa
->mask_set
);
450 * old_pte points to the large page base address. So we need
451 * to add the offset of the virtual address:
453 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
456 new_prot
= static_protections(req_prot
, address
, pfn
);
459 * We need to check the full range, whether
460 * static_protection() requires a different pgprot for one of
461 * the pages in the range we try to preserve:
463 addr
= address
& pmask
;
464 pfn
= pte_pfn(old_pte
);
465 for (i
= 0; i
< (psize
>> PAGE_SHIFT
); i
++, addr
+= PAGE_SIZE
, pfn
++) {
466 pgprot_t chk_prot
= static_protections(req_prot
, addr
, pfn
);
468 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
473 * If there are no changes, return. maxpages has been updated
476 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
482 * We need to change the attributes. Check, whether we can
483 * change the large page in one go. We request a split, when
484 * the address is not aligned and the number of pages is
485 * smaller than the number of pages in the large page. Note
486 * that we limited the number of possible pages already to
487 * the number of pages in the large page.
489 if (address
== (address
& pmask
) && cpa
->numpages
== (psize
>> PAGE_SHIFT
)) {
491 * The address is aligned and the number of pages
492 * covers the full page.
494 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
495 __set_pmd_pte(kpte
, address
, new_pte
);
496 cpa
->flags
|= CPA_FLUSHTLB
;
501 spin_unlock_irqrestore(&pgd_lock
, flags
);
506 static int split_large_page(pte_t
*kpte
, unsigned long address
)
508 unsigned long flags
, pfn
, pfninc
= 1;
509 unsigned int i
, level
;
514 if (!debug_pagealloc
)
515 spin_unlock(&cpa_lock
);
516 base
= alloc_pages(GFP_KERNEL
| __GFP_NOTRACK
, 0);
517 if (!debug_pagealloc
)
518 spin_lock(&cpa_lock
);
522 spin_lock_irqsave(&pgd_lock
, flags
);
524 * Check for races, another CPU might have split this page
527 tmp
= lookup_address(address
, &level
);
531 pbase
= (pte_t
*)page_address(base
);
532 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
533 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
535 * If we ever want to utilize the PAT bit, we need to
536 * update this function to make sure it's converted from
537 * bit 12 to bit 7 when we cross from the 2MB level to
540 WARN_ON_ONCE(pgprot_val(ref_prot
) & _PAGE_PAT_LARGE
);
543 if (level
== PG_LEVEL_1G
) {
544 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
545 pgprot_val(ref_prot
) |= _PAGE_PSE
;
550 * Get the target pfn from the original entry:
552 pfn
= pte_pfn(*kpte
);
553 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
554 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
556 if (address
>= (unsigned long)__va(0) &&
557 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
558 split_page_count(level
);
561 if (address
>= (unsigned long)__va(1UL<<32) &&
562 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
563 split_page_count(level
);
567 * Install the new, split up pagetable.
569 * We use the standard kernel pagetable protections for the new
570 * pagetable protections, the actual ptes set above control the
571 * primary protection behavior:
573 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
576 * Intel Atom errata AAH41 workaround.
578 * The real fix should be in hw or in a microcode update, but
579 * we also probabilistically try to reduce the window of having
580 * a large TLB mixed with 4K TLBs while instruction fetches are
589 * If we dropped out via the lookup_address check under
590 * pgd_lock then stick the page back into the pool:
594 spin_unlock_irqrestore(&pgd_lock
, flags
);
599 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
603 * Ignore all non primary paths.
609 * Ignore the NULL PTE for kernel identity mapping, as it is expected
611 * Also set numpages to '1' indicating that we processed cpa req for
612 * one virtual address page and its pfn. TBD: numpages can be set based
613 * on the initial value and the level returned by lookup_address().
615 if (within(vaddr
, PAGE_OFFSET
,
616 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
618 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
621 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
622 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
629 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
631 unsigned long address
;
634 pte_t
*kpte
, old_pte
;
636 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
637 struct page
*page
= cpa
->pages
[cpa
->curpage
];
638 if (unlikely(PageHighMem(page
)))
640 address
= (unsigned long)page_address(page
);
641 } else if (cpa
->flags
& CPA_ARRAY
)
642 address
= cpa
->vaddr
[cpa
->curpage
];
644 address
= *cpa
->vaddr
;
646 kpte
= lookup_address(address
, &level
);
648 return __cpa_process_fault(cpa
, address
, primary
);
651 if (!pte_val(old_pte
))
652 return __cpa_process_fault(cpa
, address
, primary
);
654 if (level
== PG_LEVEL_4K
) {
656 pgprot_t new_prot
= pte_pgprot(old_pte
);
657 unsigned long pfn
= pte_pfn(old_pte
);
659 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
660 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
662 new_prot
= static_protections(new_prot
, address
, pfn
);
665 * We need to keep the pfn from the existing PTE,
666 * after all we're only going to change it's attributes
667 * not the memory it points to
669 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
672 * Do we really change anything ?
674 if (pte_val(old_pte
) != pte_val(new_pte
)) {
675 set_pte_atomic(kpte
, new_pte
);
676 cpa
->flags
|= CPA_FLUSHTLB
;
683 * Check, whether we can keep the large page intact
684 * and just change the pte:
686 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
688 * When the range fits into the existing large page,
689 * return. cp->numpages and cpa->tlbflush have been updated in
696 * We have to split the large page:
698 err
= split_large_page(kpte
, address
);
701 * Do a global flush tlb after splitting the large page
702 * and before we do the actual change page attribute in the PTE.
704 * With out this, we violate the TLB application note, that says
705 * "The TLBs may contain both ordinary and large-page
706 * translations for a 4-KByte range of linear addresses. This
707 * may occur if software modifies the paging structures so that
708 * the page size used for the address range changes. If the two
709 * translations differ with respect to page frame or attributes
710 * (e.g., permissions), processor behavior is undefined and may
711 * be implementation-specific."
713 * We do this global tlb flush inside the cpa_lock, so that we
714 * don't allow any other cpu, with stale tlb entries change the
715 * page attribute in parallel, that also falls into the
716 * just split large page entry.
725 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
727 static int cpa_process_alias(struct cpa_data
*cpa
)
729 struct cpa_data alias_cpa
;
730 unsigned long laddr
= (unsigned long)__va(cpa
->pfn
<< PAGE_SHIFT
);
734 if (cpa
->pfn
>= max_pfn_mapped
)
738 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
742 * No need to redo, when the primary call touched the direct
745 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
746 struct page
*page
= cpa
->pages
[cpa
->curpage
];
747 if (unlikely(PageHighMem(page
)))
749 vaddr
= (unsigned long)page_address(page
);
750 } else if (cpa
->flags
& CPA_ARRAY
)
751 vaddr
= cpa
->vaddr
[cpa
->curpage
];
755 if (!(within(vaddr
, PAGE_OFFSET
,
756 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
759 alias_cpa
.vaddr
= &laddr
;
760 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
762 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
769 * If the primary call didn't touch the high mapping already
770 * and the physical address is inside the kernel map, we need
771 * to touch the high mapped kernel as well:
773 if (!within(vaddr
, (unsigned long)_text
, _brk_end
) &&
774 within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn())) {
775 unsigned long temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) +
776 __START_KERNEL_map
- phys_base
;
778 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
779 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
782 * The high mapping range is imprecise, so ignore the
785 __change_page_attr_set_clr(&alias_cpa
, 0);
792 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
794 int ret
, numpages
= cpa
->numpages
;
798 * Store the remaining nr of pages for the large page
799 * preservation check.
801 cpa
->numpages
= numpages
;
802 /* for array changes, we can't use large page */
803 if (cpa
->flags
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
806 if (!debug_pagealloc
)
807 spin_lock(&cpa_lock
);
808 ret
= __change_page_attr(cpa
, checkalias
);
809 if (!debug_pagealloc
)
810 spin_unlock(&cpa_lock
);
815 ret
= cpa_process_alias(cpa
);
821 * Adjust the number of pages with the result of the
822 * CPA operation. Either a large page has been
823 * preserved or a single page update happened.
825 BUG_ON(cpa
->numpages
> numpages
);
826 numpages
-= cpa
->numpages
;
827 if (cpa
->flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
))
830 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
836 static inline int cache_attr(pgprot_t attr
)
838 return pgprot_val(attr
) &
839 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
842 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
843 pgprot_t mask_set
, pgprot_t mask_clr
,
844 int force_split
, int in_flag
,
848 int ret
, cache
, checkalias
;
849 unsigned long baddr
= 0;
852 * Check, if we are requested to change a not supported
855 mask_set
= canon_pgprot(mask_set
);
856 mask_clr
= canon_pgprot(mask_clr
);
857 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
860 /* Ensure we are PAGE_SIZE aligned */
861 if (in_flag
& CPA_ARRAY
) {
863 for (i
= 0; i
< numpages
; i
++) {
864 if (addr
[i
] & ~PAGE_MASK
) {
865 addr
[i
] &= PAGE_MASK
;
869 } else if (!(in_flag
& CPA_PAGES_ARRAY
)) {
871 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
872 * No need to cehck in that case
874 if (*addr
& ~PAGE_MASK
) {
877 * People should not be passing in unaligned addresses:
882 * Save address for cache flush. *addr is modified in the call
883 * to __change_page_attr_set_clr() below.
888 /* Must avoid aliasing mappings in the highmem code */
895 cpa
.numpages
= numpages
;
896 cpa
.mask_set
= mask_set
;
897 cpa
.mask_clr
= mask_clr
;
900 cpa
.force_split
= force_split
;
902 if (in_flag
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
903 cpa
.flags
|= in_flag
;
905 /* No alias checking for _NX bit modifications */
906 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
908 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
911 * Check whether we really changed something:
913 if (!(cpa
.flags
& CPA_FLUSHTLB
))
917 * No need to flush, when we did not set any of the caching
920 cache
= cache_attr(mask_set
);
923 * On success we use clflush, when the CPU supports it to
924 * avoid the wbindv. If the CPU does not support it and in the
925 * error case we fall back to cpa_flush_all (which uses
928 if (!ret
&& cpu_has_clflush
) {
929 if (cpa
.flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
)) {
930 cpa_flush_array(addr
, numpages
, cache
,
933 cpa_flush_range(baddr
, numpages
, cache
);
935 cpa_flush_all(cache
);
941 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
942 pgprot_t mask
, int array
)
944 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
945 (array
? CPA_ARRAY
: 0), NULL
);
948 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
949 pgprot_t mask
, int array
)
951 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
952 (array
? CPA_ARRAY
: 0), NULL
);
955 static inline int cpa_set_pages_array(struct page
**pages
, int numpages
,
958 return change_page_attr_set_clr(NULL
, numpages
, mask
, __pgprot(0), 0,
959 CPA_PAGES_ARRAY
, pages
);
962 static inline int cpa_clear_pages_array(struct page
**pages
, int numpages
,
965 return change_page_attr_set_clr(NULL
, numpages
, __pgprot(0), mask
, 0,
966 CPA_PAGES_ARRAY
, pages
);
969 int _set_memory_uc(unsigned long addr
, int numpages
)
972 * for now UC MINUS. see comments in ioremap_nocache()
974 return change_page_attr_set(&addr
, numpages
,
975 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
978 int set_memory_uc(unsigned long addr
, int numpages
)
983 * for now UC MINUS. see comments in ioremap_nocache()
985 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
986 _PAGE_CACHE_UC_MINUS
, NULL
);
990 ret
= _set_memory_uc(addr
, numpages
);
997 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1001 EXPORT_SYMBOL(set_memory_uc
);
1003 int _set_memory_array(unsigned long *addr
, int addrinarray
,
1004 unsigned long new_type
)
1010 * for now UC MINUS. see comments in ioremap_nocache()
1012 for (i
= 0; i
< addrinarray
; i
++) {
1013 ret
= reserve_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
,
1019 ret
= change_page_attr_set(addr
, addrinarray
,
1020 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
1022 if (!ret
&& new_type
== _PAGE_CACHE_WC
)
1023 ret
= change_page_attr_set_clr(addr
, addrinarray
,
1024 __pgprot(_PAGE_CACHE_WC
),
1025 __pgprot(_PAGE_CACHE_MASK
),
1026 0, CPA_ARRAY
, NULL
);
1033 for (j
= 0; j
< i
; j
++)
1034 free_memtype(__pa(addr
[j
]), __pa(addr
[j
]) + PAGE_SIZE
);
1039 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
1041 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_UC_MINUS
);
1043 EXPORT_SYMBOL(set_memory_array_uc
);
1045 int set_memory_array_wc(unsigned long *addr
, int addrinarray
)
1047 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_WC
);
1049 EXPORT_SYMBOL(set_memory_array_wc
);
1051 int _set_memory_wc(unsigned long addr
, int numpages
)
1054 unsigned long addr_copy
= addr
;
1056 ret
= change_page_attr_set(&addr
, numpages
,
1057 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
1059 ret
= change_page_attr_set_clr(&addr_copy
, numpages
,
1060 __pgprot(_PAGE_CACHE_WC
),
1061 __pgprot(_PAGE_CACHE_MASK
),
1067 int set_memory_wc(unsigned long addr
, int numpages
)
1072 return set_memory_uc(addr
, numpages
);
1074 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1075 _PAGE_CACHE_WC
, NULL
);
1079 ret
= _set_memory_wc(addr
, numpages
);
1086 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1090 EXPORT_SYMBOL(set_memory_wc
);
1092 int _set_memory_wb(unsigned long addr
, int numpages
)
1094 return change_page_attr_clear(&addr
, numpages
,
1095 __pgprot(_PAGE_CACHE_MASK
), 0);
1098 int set_memory_wb(unsigned long addr
, int numpages
)
1102 ret
= _set_memory_wb(addr
, numpages
);
1106 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1109 EXPORT_SYMBOL(set_memory_wb
);
1111 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
1116 ret
= change_page_attr_clear(addr
, addrinarray
,
1117 __pgprot(_PAGE_CACHE_MASK
), 1);
1121 for (i
= 0; i
< addrinarray
; i
++)
1122 free_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
);
1126 EXPORT_SYMBOL(set_memory_array_wb
);
1128 int set_memory_x(unsigned long addr
, int numpages
)
1130 if (!(__supported_pte_mask
& _PAGE_NX
))
1133 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1135 EXPORT_SYMBOL(set_memory_x
);
1137 int set_memory_nx(unsigned long addr
, int numpages
)
1139 if (!(__supported_pte_mask
& _PAGE_NX
))
1142 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1144 EXPORT_SYMBOL(set_memory_nx
);
1146 int set_memory_ro(unsigned long addr
, int numpages
)
1148 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1150 EXPORT_SYMBOL_GPL(set_memory_ro
);
1152 int set_memory_rw(unsigned long addr
, int numpages
)
1154 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1156 EXPORT_SYMBOL_GPL(set_memory_rw
);
1158 int set_memory_np(unsigned long addr
, int numpages
)
1160 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1163 int set_memory_4k(unsigned long addr
, int numpages
)
1165 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1166 __pgprot(0), 1, 0, NULL
);
1169 int set_pages_uc(struct page
*page
, int numpages
)
1171 unsigned long addr
= (unsigned long)page_address(page
);
1173 return set_memory_uc(addr
, numpages
);
1175 EXPORT_SYMBOL(set_pages_uc
);
1177 static int _set_pages_array(struct page
**pages
, int addrinarray
,
1178 unsigned long new_type
)
1180 unsigned long start
;
1186 for (i
= 0; i
< addrinarray
; i
++) {
1187 if (PageHighMem(pages
[i
]))
1189 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1190 end
= start
+ PAGE_SIZE
;
1191 if (reserve_memtype(start
, end
, new_type
, NULL
))
1195 ret
= cpa_set_pages_array(pages
, addrinarray
,
1196 __pgprot(_PAGE_CACHE_UC_MINUS
));
1197 if (!ret
&& new_type
== _PAGE_CACHE_WC
)
1198 ret
= change_page_attr_set_clr(NULL
, addrinarray
,
1199 __pgprot(_PAGE_CACHE_WC
),
1200 __pgprot(_PAGE_CACHE_MASK
),
1201 0, CPA_PAGES_ARRAY
, pages
);
1204 return 0; /* Success */
1207 for (i
= 0; i
< free_idx
; i
++) {
1208 if (PageHighMem(pages
[i
]))
1210 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1211 end
= start
+ PAGE_SIZE
;
1212 free_memtype(start
, end
);
1217 int set_pages_array_uc(struct page
**pages
, int addrinarray
)
1219 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_UC_MINUS
);
1221 EXPORT_SYMBOL(set_pages_array_uc
);
1223 int set_pages_array_wc(struct page
**pages
, int addrinarray
)
1225 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_WC
);
1227 EXPORT_SYMBOL(set_pages_array_wc
);
1229 int set_pages_wb(struct page
*page
, int numpages
)
1231 unsigned long addr
= (unsigned long)page_address(page
);
1233 return set_memory_wb(addr
, numpages
);
1235 EXPORT_SYMBOL(set_pages_wb
);
1237 int set_pages_array_wb(struct page
**pages
, int addrinarray
)
1240 unsigned long start
;
1244 retval
= cpa_clear_pages_array(pages
, addrinarray
,
1245 __pgprot(_PAGE_CACHE_MASK
));
1249 for (i
= 0; i
< addrinarray
; i
++) {
1250 if (PageHighMem(pages
[i
]))
1252 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1253 end
= start
+ PAGE_SIZE
;
1254 free_memtype(start
, end
);
1259 EXPORT_SYMBOL(set_pages_array_wb
);
1261 int set_pages_x(struct page
*page
, int numpages
)
1263 unsigned long addr
= (unsigned long)page_address(page
);
1265 return set_memory_x(addr
, numpages
);
1267 EXPORT_SYMBOL(set_pages_x
);
1269 int set_pages_nx(struct page
*page
, int numpages
)
1271 unsigned long addr
= (unsigned long)page_address(page
);
1273 return set_memory_nx(addr
, numpages
);
1275 EXPORT_SYMBOL(set_pages_nx
);
1277 int set_pages_ro(struct page
*page
, int numpages
)
1279 unsigned long addr
= (unsigned long)page_address(page
);
1281 return set_memory_ro(addr
, numpages
);
1284 int set_pages_rw(struct page
*page
, int numpages
)
1286 unsigned long addr
= (unsigned long)page_address(page
);
1288 return set_memory_rw(addr
, numpages
);
1291 #ifdef CONFIG_DEBUG_PAGEALLOC
1293 static int __set_pages_p(struct page
*page
, int numpages
)
1295 unsigned long tempaddr
= (unsigned long) page_address(page
);
1296 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1297 .numpages
= numpages
,
1298 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1299 .mask_clr
= __pgprot(0),
1303 * No alias checking needed for setting present flag. otherwise,
1304 * we may need to break large pages for 64-bit kernel text
1305 * mappings (this adds to complexity if we want to do this from
1306 * atomic context especially). Let's keep it simple!
1308 return __change_page_attr_set_clr(&cpa
, 0);
1311 static int __set_pages_np(struct page
*page
, int numpages
)
1313 unsigned long tempaddr
= (unsigned long) page_address(page
);
1314 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1315 .numpages
= numpages
,
1316 .mask_set
= __pgprot(0),
1317 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1321 * No alias checking needed for setting not present flag. otherwise,
1322 * we may need to break large pages for 64-bit kernel text
1323 * mappings (this adds to complexity if we want to do this from
1324 * atomic context especially). Let's keep it simple!
1326 return __change_page_attr_set_clr(&cpa
, 0);
1329 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1331 if (PageHighMem(page
))
1334 debug_check_no_locks_freed(page_address(page
),
1335 numpages
* PAGE_SIZE
);
1339 * If page allocator is not up yet then do not call c_p_a():
1341 if (!debug_pagealloc_enabled
)
1345 * The return value is ignored as the calls cannot fail.
1346 * Large pages for identity mappings are not used at boot time
1347 * and hence no memory allocations during large page split.
1350 __set_pages_p(page
, numpages
);
1352 __set_pages_np(page
, numpages
);
1355 * We should perform an IPI and flush all tlbs,
1356 * but that can deadlock->flush only current cpu:
1361 #ifdef CONFIG_HIBERNATION
1363 bool kernel_page_present(struct page
*page
)
1368 if (PageHighMem(page
))
1371 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1372 return (pte_val(*pte
) & _PAGE_PRESENT
);
1375 #endif /* CONFIG_HIBERNATION */
1377 #endif /* CONFIG_DEBUG_PAGEALLOC */
1380 * The testcases use internal knowledge of the implementation that shouldn't
1381 * be exposed to the rest of the kernel. Include these directly here.
1383 #ifdef CONFIG_CPA_DEBUG
1384 #include "pageattr-test.c"
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