4 * @remark Copyright 2002 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
10 #include <linux/init.h>
11 #include <linux/notifier.h>
12 #include <linux/smp.h>
13 #include <linux/oprofile.h>
14 #include <linux/sysdev.h>
15 #include <linux/slab.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kdebug.h>
18 #include <linux/cpu.h>
23 #include "op_counter.h"
24 #include "op_x86_model.h"
26 static struct op_x86_model_spec
const *model
;
27 static DEFINE_PER_CPU(struct op_msrs
, cpu_msrs
);
28 static DEFINE_PER_CPU(unsigned long, saved_lvtpc
);
30 static int nmi_start(void);
31 static void nmi_stop(void);
32 static void nmi_cpu_start(void *dummy
);
33 static void nmi_cpu_stop(void *dummy
);
35 /* 0 == registered but off, 1 == registered and on */
36 static int nmi_enabled
= 0;
39 static int oprofile_cpu_notifier(struct notifier_block
*b
, unsigned long action
,
42 int cpu
= (unsigned long)data
;
46 smp_call_function_single(cpu
, nmi_cpu_start
, NULL
, 0);
48 case CPU_DOWN_PREPARE
:
49 smp_call_function_single(cpu
, nmi_cpu_stop
, NULL
, 1);
55 static struct notifier_block oprofile_cpu_nb
= {
56 .notifier_call
= oprofile_cpu_notifier
62 static int nmi_suspend(struct sys_device
*dev
, pm_message_t state
)
64 /* Only one CPU left, just stop that one */
70 static int nmi_resume(struct sys_device
*dev
)
77 static struct sysdev_class oprofile_sysclass
= {
80 .suspend
= nmi_suspend
,
83 static struct sys_device device_oprofile
= {
85 .cls
= &oprofile_sysclass
,
88 static int __init
init_sysfs(void)
92 error
= sysdev_class_register(&oprofile_sysclass
);
94 error
= sysdev_register(&device_oprofile
);
98 static void exit_sysfs(void)
100 sysdev_unregister(&device_oprofile
);
101 sysdev_class_unregister(&oprofile_sysclass
);
105 #define init_sysfs() do { } while (0)
106 #define exit_sysfs() do { } while (0)
107 #endif /* CONFIG_PM */
109 static int profile_exceptions_notify(struct notifier_block
*self
,
110 unsigned long val
, void *data
)
112 struct die_args
*args
= (struct die_args
*)data
;
113 int ret
= NOTIFY_DONE
;
114 int cpu
= smp_processor_id();
118 if (model
->check_ctrs(args
->regs
, &per_cpu(cpu_msrs
, cpu
)))
127 static void nmi_cpu_save_registers(struct op_msrs
*msrs
)
129 unsigned int const nr_ctrs
= model
->num_counters
;
130 unsigned int const nr_ctrls
= model
->num_controls
;
131 struct op_msr
*counters
= msrs
->counters
;
132 struct op_msr
*controls
= msrs
->controls
;
135 for (i
= 0; i
< nr_ctrs
; ++i
) {
136 if (counters
[i
].addr
) {
137 rdmsr(counters
[i
].addr
,
138 counters
[i
].saved
.low
,
139 counters
[i
].saved
.high
);
143 for (i
= 0; i
< nr_ctrls
; ++i
) {
144 if (controls
[i
].addr
) {
145 rdmsr(controls
[i
].addr
,
146 controls
[i
].saved
.low
,
147 controls
[i
].saved
.high
);
152 static void nmi_save_registers(void *dummy
)
154 int cpu
= smp_processor_id();
155 struct op_msrs
*msrs
= &per_cpu(cpu_msrs
, cpu
);
156 nmi_cpu_save_registers(msrs
);
159 static void free_msrs(void)
162 for_each_possible_cpu(i
) {
163 kfree(per_cpu(cpu_msrs
, i
).counters
);
164 per_cpu(cpu_msrs
, i
).counters
= NULL
;
165 kfree(per_cpu(cpu_msrs
, i
).controls
);
166 per_cpu(cpu_msrs
, i
).controls
= NULL
;
170 static int allocate_msrs(void)
173 size_t controls_size
= sizeof(struct op_msr
) * model
->num_controls
;
174 size_t counters_size
= sizeof(struct op_msr
) * model
->num_counters
;
177 for_each_possible_cpu(i
) {
178 per_cpu(cpu_msrs
, i
).counters
= kmalloc(counters_size
,
180 if (!per_cpu(cpu_msrs
, i
).counters
) {
184 per_cpu(cpu_msrs
, i
).controls
= kmalloc(controls_size
,
186 if (!per_cpu(cpu_msrs
, i
).controls
) {
198 static void nmi_cpu_setup(void *dummy
)
200 int cpu
= smp_processor_id();
201 struct op_msrs
*msrs
= &per_cpu(cpu_msrs
, cpu
);
202 spin_lock(&oprofilefs_lock
);
203 model
->setup_ctrs(msrs
);
204 spin_unlock(&oprofilefs_lock
);
205 per_cpu(saved_lvtpc
, cpu
) = apic_read(APIC_LVTPC
);
206 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
209 static struct notifier_block profile_exceptions_nb
= {
210 .notifier_call
= profile_exceptions_notify
,
215 static int nmi_setup(void)
220 if (!allocate_msrs())
223 err
= register_die_notifier(&profile_exceptions_nb
);
229 /* We need to serialize save and setup for HT because the subset
230 * of msrs are distinct for save and setup operations
233 /* Assume saved/restored counters are the same on all CPUs */
234 model
->fill_in_addresses(&per_cpu(cpu_msrs
, 0));
235 for_each_possible_cpu(cpu
) {
237 memcpy(per_cpu(cpu_msrs
, cpu
).counters
,
238 per_cpu(cpu_msrs
, 0).counters
,
239 sizeof(struct op_msr
) * model
->num_counters
);
241 memcpy(per_cpu(cpu_msrs
, cpu
).controls
,
242 per_cpu(cpu_msrs
, 0).controls
,
243 sizeof(struct op_msr
) * model
->num_controls
);
247 on_each_cpu(nmi_save_registers
, NULL
, 1);
248 on_each_cpu(nmi_cpu_setup
, NULL
, 1);
253 static void nmi_restore_registers(struct op_msrs
*msrs
)
255 unsigned int const nr_ctrs
= model
->num_counters
;
256 unsigned int const nr_ctrls
= model
->num_controls
;
257 struct op_msr
*counters
= msrs
->counters
;
258 struct op_msr
*controls
= msrs
->controls
;
261 for (i
= 0; i
< nr_ctrls
; ++i
) {
262 if (controls
[i
].addr
) {
263 wrmsr(controls
[i
].addr
,
264 controls
[i
].saved
.low
,
265 controls
[i
].saved
.high
);
269 for (i
= 0; i
< nr_ctrs
; ++i
) {
270 if (counters
[i
].addr
) {
271 wrmsr(counters
[i
].addr
,
272 counters
[i
].saved
.low
,
273 counters
[i
].saved
.high
);
278 static void nmi_cpu_shutdown(void *dummy
)
281 int cpu
= smp_processor_id();
282 struct op_msrs
*msrs
= &__get_cpu_var(cpu_msrs
);
284 /* restoring APIC_LVTPC can trigger an apic error because the delivery
285 * mode and vector nr combination can be illegal. That's by design: on
286 * power on apic lvt contain a zero vector nr which are legal only for
287 * NMI delivery mode. So inhibit apic err before restoring lvtpc
289 v
= apic_read(APIC_LVTERR
);
290 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
291 apic_write(APIC_LVTPC
, per_cpu(saved_lvtpc
, cpu
));
292 apic_write(APIC_LVTERR
, v
);
293 nmi_restore_registers(msrs
);
296 static void nmi_shutdown(void)
298 struct op_msrs
*msrs
= &get_cpu_var(cpu_msrs
);
300 on_each_cpu(nmi_cpu_shutdown
, NULL
, 1);
301 unregister_die_notifier(&profile_exceptions_nb
);
302 model
->shutdown(msrs
);
304 put_cpu_var(cpu_msrs
);
307 static void nmi_cpu_start(void *dummy
)
309 struct op_msrs
const *msrs
= &__get_cpu_var(cpu_msrs
);
313 static int nmi_start(void)
315 on_each_cpu(nmi_cpu_start
, NULL
, 1);
319 static void nmi_cpu_stop(void *dummy
)
321 struct op_msrs
const *msrs
= &__get_cpu_var(cpu_msrs
);
325 static void nmi_stop(void)
327 on_each_cpu(nmi_cpu_stop
, NULL
, 1);
330 struct op_counter_config counter_config
[OP_MAX_COUNTER
];
332 static int nmi_create_files(struct super_block
*sb
, struct dentry
*root
)
336 for (i
= 0; i
< model
->num_counters
; ++i
) {
340 /* quick little hack to _not_ expose a counter if it is not
341 * available for use. This should protect userspace app.
342 * NOTE: assumes 1:1 mapping here (that counters are organized
343 * sequentially in their struct assignment).
345 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i
)))
348 snprintf(buf
, sizeof(buf
), "%d", i
);
349 dir
= oprofilefs_mkdir(sb
, root
, buf
);
350 oprofilefs_create_ulong(sb
, dir
, "enabled", &counter_config
[i
].enabled
);
351 oprofilefs_create_ulong(sb
, dir
, "event", &counter_config
[i
].event
);
352 oprofilefs_create_ulong(sb
, dir
, "count", &counter_config
[i
].count
);
353 oprofilefs_create_ulong(sb
, dir
, "unit_mask", &counter_config
[i
].unit_mask
);
354 oprofilefs_create_ulong(sb
, dir
, "kernel", &counter_config
[i
].kernel
);
355 oprofilefs_create_ulong(sb
, dir
, "user", &counter_config
[i
].user
);
362 module_param(p4force
, int, 0);
364 static int __init
p4_init(char **cpu_type
)
366 __u8 cpu_model
= boot_cpu_data
.x86_model
;
368 if (!p4force
&& (cpu_model
> 6 || cpu_model
== 5))
372 *cpu_type
= "i386/p4";
376 switch (smp_num_siblings
) {
378 *cpu_type
= "i386/p4";
383 *cpu_type
= "i386/p4-ht";
384 model
= &op_p4_ht2_spec
;
389 printk(KERN_INFO
"oprofile: P4 HyperThreading detected with > 2 threads\n");
390 printk(KERN_INFO
"oprofile: Reverting to timer mode.\n");
394 static int __init
ppro_init(char **cpu_type
)
396 __u8 cpu_model
= boot_cpu_data
.x86_model
;
400 *cpu_type
= "i386/ppro";
403 *cpu_type
= "i386/pii";
406 *cpu_type
= "i386/piii";
409 *cpu_type
= "i386/p6_mobile";
412 *cpu_type
= "i386/p6";
415 *cpu_type
= "i386/core";
418 *cpu_type
= "i386/core_2";
421 *cpu_type
= "i386/core_2";
428 model
= &op_ppro_spec
;
432 /* in order to get sysfs right */
433 static int using_nmi
;
435 int __init
op_nmi_init(struct oprofile_operations
*ops
)
437 __u8 vendor
= boot_cpu_data
.x86_vendor
;
438 __u8 family
= boot_cpu_data
.x86
;
446 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
452 model
= &op_athlon_spec
;
453 cpu_type
= "i386/athlon";
456 model
= &op_athlon_spec
;
457 /* Actually it could be i386/hammer too, but give
458 user space an consistent name. */
459 cpu_type
= "x86-64/hammer";
462 model
= &op_athlon_spec
;
463 cpu_type
= "x86-64/family10";
468 case X86_VENDOR_INTEL
:
472 if (!p4_init(&cpu_type
))
476 /* A P6-class processor */
478 if (!ppro_init(&cpu_type
))
493 register_cpu_notifier(&oprofile_cpu_nb
);
496 ops
->create_files
= nmi_create_files
;
497 ops
->setup
= nmi_setup
;
498 ops
->shutdown
= nmi_shutdown
;
499 ops
->start
= nmi_start
;
500 ops
->stop
= nmi_stop
;
501 ops
->cpu_type
= cpu_type
;
502 printk(KERN_INFO
"oprofile: using NMI interrupt.\n");
506 void op_nmi_exit(void)
511 unregister_cpu_notifier(&oprofile_cpu_nb
);