arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37
  38 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  39 extern atomic_t multiplex_counter;
  40 #endif
  41
  42 struct op_counter_config counter_config[OP_MAX_COUNTER];
  43
  44 /* common functions */
  45
  46 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  47                     struct op_counter_config *counter_config)
  48 {
  49         u64 val = 0;
  50         u16 event = (u16)counter_config->event;
  51
  52         val |= ARCH_PERFMON_EVENTSEL_INT;
  53         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  54         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  55         val |= (counter_config->unit_mask & 0xFF) << 8;
  56         event &= model->event_mask ? model->event_mask : 0xFF;
  57         val |= event & 0xFF;
  58         val |= (event & 0x0F00) << 24;
  59
  60         return val;
  61 }
  62
  63
  64 static int profile_exceptions_notify(struct notifier_block *self,
  65                                      unsigned long val, void *data)
  66 {
  67         struct die_args *args = (struct die_args *)data;
  68         int ret = NOTIFY_DONE;
  69         int cpu = smp_processor_id();
  70
  71         switch (val) {
  72         case DIE_NMI:
  73         case DIE_NMI_IPI:
  74                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  75                 ret = NOTIFY_STOP;
  76                 break;
  77         default:
  78                 break;
  79         }
  80         return ret;
  81 }
  82
  83 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  84 {
  85         struct op_msr *counters = msrs->counters;
  86         struct op_msr *controls = msrs->controls;
  87         unsigned int i;
  88
  89         for (i = 0; i < model->num_counters; ++i) {
  90                 if (counters[i].addr)
  91                         rdmsrl(counters[i].addr, counters[i].saved);
  92         }
  93
  94         for (i = 0; i < model->num_controls; ++i) {
  95                 if (controls[i].addr)
  96                         rdmsrl(controls[i].addr, controls[i].saved);
  97         }
  98 }
  99
 100 static void nmi_cpu_start(void *dummy)
 101 {
 102         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 103         model->start(msrs);
 104 }
 105
 106 static int nmi_start(void)
 107 {
 108         on_each_cpu(nmi_cpu_start, NULL, 1);
 109         return 0;
 110 }
 111
 112 static void nmi_cpu_stop(void *dummy)
 113 {
 114         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 115         model->stop(msrs);
 116 }
 117
 118 static void nmi_stop(void)
 119 {
 120         on_each_cpu(nmi_cpu_stop, NULL, 1);
 121 }
 122
 123 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 124
 125 static DEFINE_PER_CPU(int, switch_index);
 126
 127 static inline int has_mux(void)
 128 {
 129         return !!model->switch_ctrl;
 130 }
 131
 132 inline int op_x86_phys_to_virt(int phys)
 133 {
 134         return __get_cpu_var(switch_index) + phys;
 135 }
 136
 137 static void nmi_shutdown_mux(void)
 138 {
 139         int i;
 140
 141         if (!has_mux())
 142                 return;
 143
 144         for_each_possible_cpu(i) {
 145                 kfree(per_cpu(cpu_msrs, i).multiplex);
 146                 per_cpu(cpu_msrs, i).multiplex = NULL;
 147                 per_cpu(switch_index, i) = 0;
 148         }
 149 }
 150
 151 static int nmi_setup_mux(void)
 152 {
 153         size_t multiplex_size =
 154                 sizeof(struct op_msr) * model->num_virt_counters;
 155         int i;
 156
 157         if (!has_mux())
 158                 return 1;
 159
 160         for_each_possible_cpu(i) {
 161                 per_cpu(cpu_msrs, i).multiplex =
 162                         kmalloc(multiplex_size, GFP_KERNEL);
 163                 if (!per_cpu(cpu_msrs, i).multiplex)
 164                         return 0;
 165         }
 166
 167         return 1;
 168 }
 169
 170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 171 {
 172         int i;
 173         struct op_msr *multiplex = msrs->multiplex;
 174
 175         if (!has_mux())
 176                 return;
 177
 178         for (i = 0; i < model->num_virt_counters; ++i) {
 179                 if (counter_config[i].enabled) {
 180                         multiplex[i].saved = -(u64)counter_config[i].count;
 181                 } else {
 182                         multiplex[i].addr  = 0;
 183                         multiplex[i].saved = 0;
 184                 }
 185         }
 186
 187         per_cpu(switch_index, cpu) = 0;
 188 }
 189
 190 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 191 {
 192         struct op_msr *multiplex = msrs->multiplex;
 193         int i;
 194
 195         for (i = 0; i < model->num_counters; ++i) {
 196                 int virt = op_x86_phys_to_virt(i);
 197                 if (multiplex[virt].addr)
 198                         rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
 199         }
 200 }
 201
 202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 203 {
 204         struct op_msr *multiplex = msrs->multiplex;
 205         int i;
 206
 207         for (i = 0; i < model->num_counters; ++i) {
 208                 int virt = op_x86_phys_to_virt(i);
 209                 if (multiplex[virt].addr)
 210                         wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
 211         }
 212 }
 213
 214 static void nmi_cpu_switch(void *dummy)
 215 {
 216         int cpu = smp_processor_id();
 217         int si = per_cpu(switch_index, cpu);
 218         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 219
 220         nmi_cpu_stop(NULL);
 221         nmi_cpu_save_mpx_registers(msrs);
 222
 223         /* move to next set */
 224         si += model->num_counters;
 225         if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
 226                 per_cpu(switch_index, cpu) = 0;
 227         else
 228                 per_cpu(switch_index, cpu) = si;
 229
 230         model->switch_ctrl(model, msrs);
 231         nmi_cpu_restore_mpx_registers(msrs);
 232
 233         nmi_cpu_start(NULL);
 234 }
 235
 236
 237 /*
 238  * Quick check to see if multiplexing is necessary.
 239  * The check should be sufficient since counters are used
 240  * in ordre.
 241  */
 242 static int nmi_multiplex_on(void)
 243 {
 244         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 245 }
 246
 247 static int nmi_switch_event(void)
 248 {
 249         if (!has_mux())
 250                 return -ENOSYS;         /* not implemented */
 251         if (nmi_multiplex_on() < 0)
 252                 return -EINVAL;         /* not necessary */
 253
 254         on_each_cpu(nmi_cpu_switch, NULL, 1);
 255
 256         atomic_inc(&multiplex_counter);
 257
 258         return 0;
 259 }
 260
 261 static inline void mux_init(struct oprofile_operations *ops)
 262 {
 263         if (has_mux())
 264                 ops->switch_events = nmi_switch_event;
 265 }
 266
 267 static void mux_clone(int cpu)
 268 {
 269         if (!has_mux())
 270                 return;
 271
 272         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 273                per_cpu(cpu_msrs, 0).multiplex,
 274                sizeof(struct op_msr) * model->num_virt_counters);
 275 }
 276
 277 #else
 278
 279 inline int op_x86_phys_to_virt(int phys) { return phys; }
 280 static inline void nmi_shutdown_mux(void) { }
 281 static inline int nmi_setup_mux(void) { return 1; }
 282 static inline void
 283 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 284 static inline void mux_init(struct oprofile_operations *ops) { }
 285 static void mux_clone(int cpu) { }
 286
 287 #endif
 288
 289 static void free_msrs(void)
 290 {
 291         int i;
 292         for_each_possible_cpu(i) {
 293                 kfree(per_cpu(cpu_msrs, i).counters);
 294                 per_cpu(cpu_msrs, i).counters = NULL;
 295                 kfree(per_cpu(cpu_msrs, i).controls);
 296                 per_cpu(cpu_msrs, i).controls = NULL;
 297         }
 298 }
 299
 300 static int allocate_msrs(void)
 301 {
 302         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 303         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 304
 305         int i;
 306         for_each_possible_cpu(i) {
 307                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 308                                                         GFP_KERNEL);
 309                 if (!per_cpu(cpu_msrs, i).counters)
 310                         return 0;
 311                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 312                                                         GFP_KERNEL);
 313                 if (!per_cpu(cpu_msrs, i).controls)
 314                         return 0;
 315         }
 316
 317         return 1;
 318 }
 319
 320 static void nmi_cpu_setup(void *dummy)
 321 {
 322         int cpu = smp_processor_id();
 323         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 324         nmi_cpu_save_registers(msrs);
 325         spin_lock(&oprofilefs_lock);
 326         model->setup_ctrs(model, msrs);
 327         nmi_cpu_setup_mux(cpu, msrs);
 328         spin_unlock(&oprofilefs_lock);
 329         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 330         apic_write(APIC_LVTPC, APIC_DM_NMI);
 331 }
 332
 333 static struct notifier_block profile_exceptions_nb = {
 334         .notifier_call = profile_exceptions_notify,
 335         .next = NULL,
 336         .priority = 2
 337 };
 338
 339 static int nmi_setup(void)
 340 {
 341         int err = 0;
 342         int cpu;
 343
 344         if (!allocate_msrs())
 345                 err = -ENOMEM;
 346         else if (!nmi_setup_mux())
 347                 err = -ENOMEM;
 348         else
 349                 err = register_die_notifier(&profile_exceptions_nb);
 350
 351         if (err) {
 352                 free_msrs();
 353                 nmi_shutdown_mux();
 354                 return err;
 355         }
 356
 357         /* We need to serialize save and setup for HT because the subset
 358          * of msrs are distinct for save and setup operations
 359          */
 360
 361         /* Assume saved/restored counters are the same on all CPUs */
 362         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 363         for_each_possible_cpu(cpu) {
 364                 if (!cpu)
 365                         continue;
 366
 367                 memcpy(per_cpu(cpu_msrs, cpu).counters,
 368                        per_cpu(cpu_msrs, 0).counters,
 369                        sizeof(struct op_msr) * model->num_counters);
 370
 371                 memcpy(per_cpu(cpu_msrs, cpu).controls,
 372                        per_cpu(cpu_msrs, 0).controls,
 373                        sizeof(struct op_msr) * model->num_controls);
 374
 375                 mux_clone(cpu);
 376         }
 377         on_each_cpu(nmi_cpu_setup, NULL, 1);
 378         nmi_enabled = 1;
 379         return 0;
 380 }
 381
 382 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 383 {
 384         struct op_msr *counters = msrs->counters;
 385         struct op_msr *controls = msrs->controls;
 386         unsigned int i;
 387
 388         for (i = 0; i < model->num_controls; ++i) {
 389                 if (controls[i].addr)
 390                         wrmsrl(controls[i].addr, controls[i].saved);
 391         }
 392
 393         for (i = 0; i < model->num_counters; ++i) {
 394                 if (counters[i].addr)
 395                         wrmsrl(counters[i].addr, counters[i].saved);
 396         }
 397 }
 398
 399 static void nmi_cpu_shutdown(void *dummy)
 400 {
 401         unsigned int v;
 402         int cpu = smp_processor_id();
 403         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 404
 405         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 406          * mode and vector nr combination can be illegal. That's by design: on
 407          * power on apic lvt contain a zero vector nr which are legal only for
 408          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 409          */
 410         v = apic_read(APIC_LVTERR);
 411         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 412         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 413         apic_write(APIC_LVTERR, v);
 414         nmi_cpu_restore_registers(msrs);
 415 }
 416
 417 static void nmi_shutdown(void)
 418 {
 419         struct op_msrs *msrs;
 420
 421         nmi_enabled = 0;
 422         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 423         unregister_die_notifier(&profile_exceptions_nb);
 424         nmi_shutdown_mux();
 425         msrs = &get_cpu_var(cpu_msrs);
 426         model->shutdown(msrs);
 427         free_msrs();
 428         put_cpu_var(cpu_msrs);
 429 }
 430
 431 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 432 {
 433         unsigned int i;
 434
 435         for (i = 0; i < model->num_virt_counters; ++i) {
 436                 struct dentry *dir;
 437                 char buf[4];
 438
 439 #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
 440                 /* quick little hack to _not_ expose a counter if it is not
 441                  * available for use.  This should protect userspace app.
 442                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 443                  *        sequentially in their struct assignment).
 444                  */
 445                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 446                         continue;
 447 #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
 448
 449                 snprintf(buf,  sizeof(buf), "%d", i);
 450                 dir = oprofilefs_mkdir(sb, root, buf);
 451                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 452                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 453                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 454                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 455                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 456                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 457         }
 458
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_SMP
 463 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 464                                  void *data)
 465 {
 466         int cpu = (unsigned long)data;
 467         switch (action) {
 468         case CPU_DOWN_FAILED:
 469         case CPU_ONLINE:
 470                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 471                 break;
 472         case CPU_DOWN_PREPARE:
 473                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 474                 break;
 475         }
 476         return NOTIFY_DONE;
 477 }
 478
 479 static struct notifier_block oprofile_cpu_nb = {
 480         .notifier_call = oprofile_cpu_notifier
 481 };
 482 #endif
 483
 484 #ifdef CONFIG_PM
 485
 486 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 487 {
 488         /* Only one CPU left, just stop that one */
 489         if (nmi_enabled == 1)
 490                 nmi_cpu_stop(NULL);
 491         return 0;
 492 }
 493
 494 static int nmi_resume(struct sys_device *dev)
 495 {
 496         if (nmi_enabled == 1)
 497                 nmi_cpu_start(NULL);
 498         return 0;
 499 }
 500
 501 static struct sysdev_class oprofile_sysclass = {
 502         .name           = "oprofile",
 503         .resume         = nmi_resume,
 504         .suspend        = nmi_suspend,
 505 };
 506
 507 static struct sys_device device_oprofile = {
 508         .id     = 0,
 509         .cls    = &oprofile_sysclass,
 510 };
 511
 512 static int __init init_sysfs(void)
 513 {
 514         int error;
 515
 516         error = sysdev_class_register(&oprofile_sysclass);
 517         if (!error)
 518                 error = sysdev_register(&device_oprofile);
 519         return error;
 520 }
 521
 522 static void exit_sysfs(void)
 523 {
 524         sysdev_unregister(&device_oprofile);
 525         sysdev_class_unregister(&oprofile_sysclass);
 526 }
 527
 528 #else
 529 #define init_sysfs() do { } while (0)
 530 #define exit_sysfs() do { } while (0)
 531 #endif /* CONFIG_PM */
 532
 533 static int __init p4_init(char **cpu_type)
 534 {
 535         __u8 cpu_model = boot_cpu_data.x86_model;
 536
 537         if (cpu_model > 6 || cpu_model == 5)
 538                 return 0;
 539
 540 #ifndef CONFIG_SMP
 541         *cpu_type = "i386/p4";
 542         model = &op_p4_spec;
 543         return 1;
 544 #else
 545         switch (smp_num_siblings) {
 546         case 1:
 547                 *cpu_type = "i386/p4";
 548                 model = &op_p4_spec;
 549                 return 1;
 550
 551         case 2:
 552                 *cpu_type = "i386/p4-ht";
 553                 model = &op_p4_ht2_spec;
 554                 return 1;
 555         }
 556 #endif
 557
 558         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 559         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 560         return 0;
 561 }
 562
 563 static int force_arch_perfmon;
 564 static int force_cpu_type(const char *str, struct kernel_param *kp)
 565 {
 566         if (!strcmp(str, "arch_perfmon")) {
 567                 force_arch_perfmon = 1;
 568                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 569         }
 570
 571         return 0;
 572 }
 573 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 574
 575 static int __init ppro_init(char **cpu_type)
 576 {
 577         __u8 cpu_model = boot_cpu_data.x86_model;
 578         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 579
 580         if (force_arch_perfmon && cpu_has_arch_perfmon)
 581                 return 0;
 582
 583         switch (cpu_model) {
 584         case 0 ... 2:
 585                 *cpu_type = "i386/ppro";
 586                 break;
 587         case 3 ... 5:
 588                 *cpu_type = "i386/pii";
 589                 break;
 590         case 6 ... 8:
 591         case 10 ... 11:
 592                 *cpu_type = "i386/piii";
 593                 break;
 594         case 9:
 595         case 13:
 596                 *cpu_type = "i386/p6_mobile";
 597                 break;
 598         case 14:
 599                 *cpu_type = "i386/core";
 600                 break;
 601         case 15: case 23:
 602                 *cpu_type = "i386/core_2";
 603                 break;
 604         case 26:
 605                 spec = &op_arch_perfmon_spec;
 606                 *cpu_type = "i386/core_i7";
 607                 break;
 608         case 28:
 609                 *cpu_type = "i386/atom";
 610                 break;
 611         default:
 612                 /* Unknown */
 613                 return 0;
 614         }
 615
 616         model = spec;
 617         return 1;
 618 }
 619
 620 /* in order to get sysfs right */
 621 static int using_nmi;
 622
 623 int __init op_nmi_init(struct oprofile_operations *ops)
 624 {
 625         __u8 vendor = boot_cpu_data.x86_vendor;
 626         __u8 family = boot_cpu_data.x86;
 627         char *cpu_type = NULL;
 628         int ret = 0;
 629
 630         if (!cpu_has_apic)
 631                 return -ENODEV;
 632
 633         switch (vendor) {
 634         case X86_VENDOR_AMD:
 635                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 636
 637                 switch (family) {
 638                 case 6:
 639                         cpu_type = "i386/athlon";
 640                         break;
 641                 case 0xf:
 642                         /*
 643                          * Actually it could be i386/hammer too, but
 644                          * give user space an consistent name.
 645                          */
 646                         cpu_type = "x86-64/hammer";
 647                         break;
 648                 case 0x10:
 649                         cpu_type = "x86-64/family10";
 650                         break;
 651                 case 0x11:
 652                         cpu_type = "x86-64/family11h";
 653                         break;
 654                 default:
 655                         return -ENODEV;
 656                 }
 657                 model = &op_amd_spec;
 658                 break;
 659
 660         case X86_VENDOR_INTEL:
 661                 switch (family) {
 662                         /* Pentium IV */
 663                 case 0xf:
 664                         p4_init(&cpu_type);
 665                         break;
 666
 667                         /* A P6-class processor */
 668                 case 6:
 669                         ppro_init(&cpu_type);
 670                         break;
 671
 672                 default:
 673                         break;
 674                 }
 675
 676                 if (cpu_type)
 677                         break;
 678
 679                 if (!cpu_has_arch_perfmon)
 680                         return -ENODEV;
 681
 682                 /* use arch perfmon as fallback */
 683                 cpu_type = "i386/arch_perfmon";
 684                 model = &op_arch_perfmon_spec;
 685                 break;
 686
 687         default:
 688                 return -ENODEV;
 689         }
 690
 691 #ifdef CONFIG_SMP
 692         register_cpu_notifier(&oprofile_cpu_nb);
 693 #endif
 694         /* default values, can be overwritten by model */
 695         ops->create_files       = nmi_create_files;
 696         ops->setup              = nmi_setup;
 697         ops->shutdown           = nmi_shutdown;
 698         ops->start              = nmi_start;
 699         ops->stop               = nmi_stop;
 700         ops->cpu_type           = cpu_type;
 701
 702         if (model->init)
 703                 ret = model->init(ops);
 704         if (ret)
 705                 return ret;
 706
 707         if (!model->num_virt_counters)
 708                 model->num_virt_counters = model->num_counters;
 709
 710         mux_init(ops);
 711
 712         init_sysfs();
 713         using_nmi = 1;
 714         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 715         return 0;
 716 }
 717
 718 void op_nmi_exit(void)
 719 {
 720         if (using_nmi) {
 721                 exit_sysfs();
 722 #ifdef CONFIG_SMP
 723                 unregister_cpu_notifier(&oprofile_cpu_nb);
 724 #endif
 725         }
 726         if (model->exit)
 727                 model->exit();
 728 }