arch/x86/pci/acpi.c

   1 #include <linux/pci.h>
   2 #include <linux/acpi.h>
   3 #include <linux/init.h>
   4 #include <linux/irq.h>
   5 #include <linux/dmi.h>
   6 #include <linux/slab.h>
   7 #include <asm/numa.h>
   8 #include <asm/pci_x86.h>
   9
  10 struct pci_root_info {
  11         struct acpi_device *bridge;
  12         char name[16];
  13         struct pci_sysdata sd;
  14 #ifdef  CONFIG_PCI_MMCONFIG
  15         bool mcfg_added;
  16         u16 segment;
  17         u8 start_bus;
  18         u8 end_bus;
  19 #endif
  20 };
  21
  22 static bool pci_use_crs = true;
  23 static bool pci_ignore_seg = false;
  24
  25 static int __init set_use_crs(const struct dmi_system_id *id)
  26 {
  27         pci_use_crs = true;
  28         return 0;
  29 }
  30
  31 static int __init set_nouse_crs(const struct dmi_system_id *id)
  32 {
  33         pci_use_crs = false;
  34         return 0;
  35 }
  36
  37 static int __init set_ignore_seg(const struct dmi_system_id *id)
  38 {
  39         printk(KERN_INFO "PCI: %s detected: ignoring ACPI _SEG\n", id->ident);
  40         pci_ignore_seg = true;
  41         return 0;
  42 }
  43
  44 static const struct dmi_system_id pci_crs_quirks[] __initconst = {
  45         /* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
  46         {
  47                 .callback = set_use_crs,
  48                 .ident = "IBM System x3800",
  49                 .matches = {
  50                         DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
  51                         DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
  52                 },
  53         },
  54         /* https://bugzilla.kernel.org/show_bug.cgi?id=16007 */
  55         /* 2006 AMD HT/VIA system with two host bridges */
  56         {
  57                 .callback = set_use_crs,
  58                 .ident = "ASRock ALiveSATA2-GLAN",
  59                 .matches = {
  60                         DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
  61                 },
  62         },
  63         /* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
  64         /* 2006 AMD HT/VIA system with two host bridges */
  65         {
  66                 .callback = set_use_crs,
  67                 .ident = "ASUS M2V-MX SE",
  68                 .matches = {
  69                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
  70                         DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
  71                         DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
  72                 },
  73         },
  74         /* https://bugzilla.kernel.org/show_bug.cgi?id=42619 */
  75         {
  76                 .callback = set_use_crs,
  77                 .ident = "MSI MS-7253",
  78                 .matches = {
  79                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
  80                         DMI_MATCH(DMI_BOARD_NAME, "MS-7253"),
  81                         DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
  82                 },
  83         },
  84
  85         /* Now for the blacklist.. */
  86
  87         /* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
  88         {
  89                 .callback = set_nouse_crs,
  90                 .ident = "Dell Studio 1557",
  91                 .matches = {
  92                         DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
  93                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1557"),
  94                         DMI_MATCH(DMI_BIOS_VERSION, "A09"),
  95                 },
  96         },
  97         /* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
  98         {
  99                 .callback = set_nouse_crs,
 100                 .ident = "Thinkpad SL510",
 101                 .matches = {
 102                         DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
 103                         DMI_MATCH(DMI_BOARD_NAME, "2847DFG"),
 104                         DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
 105                 },
 106         },
 107
 108         /* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
 109         {
 110                 .callback = set_ignore_seg,
 111                 .ident = "HP xw9300",
 112                 .matches = {
 113                         DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 114                         DMI_MATCH(DMI_PRODUCT_NAME, "HP xw9300 Workstation"),
 115                 },
 116         },
 117         {}
 118 };
 119
 120 void __init pci_acpi_crs_quirks(void)
 121 {
 122         int year;
 123
 124         if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && year < 2008)
 125                 pci_use_crs = false;
 126
 127         dmi_check_system(pci_crs_quirks);
 128
 129         /*
 130          * If the user specifies "pci=use_crs" or "pci=nocrs" explicitly, that
 131          * takes precedence over anything we figured out above.
 132          */
 133         if (pci_probe & PCI_ROOT_NO_CRS)
 134                 pci_use_crs = false;
 135         else if (pci_probe & PCI_USE__CRS)
 136                 pci_use_crs = true;
 137
 138         printk(KERN_INFO "PCI: %s host bridge windows from ACPI; "
 139                "if necessary, use \"pci=%s\" and report a bug\n",
 140                pci_use_crs ? "Using" : "Ignoring",
 141                pci_use_crs ? "nocrs" : "use_crs");
 142 }
 143
 144 #ifdef  CONFIG_PCI_MMCONFIG
 145 static int check_segment(u16 seg, struct device *dev, char *estr)
 146 {
 147         if (seg) {
 148                 dev_err(dev,
 149                         "%s can't access PCI configuration "
 150                         "space under this host bridge.\n",
 151                         estr);
 152                 return -EIO;
 153         }
 154
 155         /*
 156          * Failure in adding MMCFG information is not fatal,
 157          * just can't access extended configuration space of
 158          * devices under this host bridge.
 159          */
 160         dev_warn(dev,
 161                  "%s can't access extended PCI configuration "
 162                  "space under this bridge.\n",
 163                  estr);
 164
 165         return 0;
 166 }
 167
 168 static int setup_mcfg_map(struct pci_root_info *info, u16 seg, u8 start,
 169                           u8 end, phys_addr_t addr)
 170 {
 171         int result;
 172         struct device *dev = &info->bridge->dev;
 173
 174         info->start_bus = start;
 175         info->end_bus = end;
 176         info->mcfg_added = false;
 177
 178         /* return success if MMCFG is not in use */
 179         if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
 180                 return 0;
 181
 182         if (!(pci_probe & PCI_PROBE_MMCONF))
 183                 return check_segment(seg, dev, "MMCONFIG is disabled,");
 184
 185         result = pci_mmconfig_insert(dev, seg, start, end, addr);
 186         if (result == 0) {
 187                 /* enable MMCFG if it hasn't been enabled yet */
 188                 if (raw_pci_ext_ops == NULL)
 189                         raw_pci_ext_ops = &pci_mmcfg;
 190                 info->mcfg_added = true;
 191         } else if (result != -EEXIST)
 192                 return check_segment(seg, dev,
 193                          "fail to add MMCONFIG information,");
 194
 195         return 0;
 196 }
 197
 198 static void teardown_mcfg_map(struct pci_root_info *info)
 199 {
 200         if (info->mcfg_added) {
 201                 pci_mmconfig_delete(info->segment, info->start_bus,
 202                                     info->end_bus);
 203                 info->mcfg_added = false;
 204         }
 205 }
 206 #else
 207 static int setup_mcfg_map(struct pci_root_info *info,
 208                                     u16 seg, u8 start, u8 end,
 209                                     phys_addr_t addr)
 210 {
 211         return 0;
 212 }
 213 static void teardown_mcfg_map(struct pci_root_info *info)
 214 {
 215 }
 216 #endif
 217
 218 static void validate_resources(struct device *dev, struct list_head *crs_res,
 219                                unsigned long type)
 220 {
 221         LIST_HEAD(list);
 222         struct resource *res1, *res2, *root = NULL;
 223         struct resource_entry *tmp, *entry, *entry2;
 224
 225         BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
 226         root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
 227
 228         list_splice_init(crs_res, &list);
 229         resource_list_for_each_entry_safe(entry, tmp, &list) {
 230                 bool free = false;
 231                 resource_size_t end;
 232
 233                 res1 = entry->res;
 234                 if (!(res1->flags & type))
 235                         goto next;
 236
 237                 /* Exclude non-addressable range or non-addressable portion */
 238                 end = min(res1->end, root->end);
 239                 if (end <= res1->start) {
 240                         dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
 241                                  res1);
 242                         free = true;
 243                         goto next;
 244                 } else if (res1->end != end) {
 245                         dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
 246                                  res1, (unsigned long long)end + 1,
 247                                  (unsigned long long)res1->end);
 248                         res1->end = end;
 249                 }
 250
 251                 resource_list_for_each_entry(entry2, crs_res) {
 252                         res2 = entry2->res;
 253                         if (!(res2->flags & type))
 254                                 continue;
 255
 256                         /*
 257                          * I don't like throwing away windows because then
 258                          * our resources no longer match the ACPI _CRS, but
 259                          * the kernel resource tree doesn't allow overlaps.
 260                          */
 261                         if (resource_overlaps(res1, res2)) {
 262                                 res2->start = min(res1->start, res2->start);
 263                                 res2->end = max(res1->end, res2->end);
 264                                 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
 265                                          res2, res1);
 266                                 free = true;
 267                                 goto next;
 268                         }
 269                 }
 270
 271 next:
 272                 resource_list_del(entry);
 273                 if (free)
 274                         resource_list_free_entry(entry);
 275                 else
 276                         resource_list_add_tail(entry, crs_res);
 277         }
 278 }
 279
 280 static void add_resources(struct pci_root_info *info,
 281                           struct list_head *resources,
 282                           struct list_head *crs_res)
 283 {
 284         struct resource_entry *entry, *tmp;
 285         struct resource *res, *conflict, *root = NULL;
 286
 287         validate_resources(&info->bridge->dev, crs_res, IORESOURCE_MEM);
 288         validate_resources(&info->bridge->dev, crs_res, IORESOURCE_IO);
 289
 290         resource_list_for_each_entry_safe(entry, tmp, crs_res) {
 291                 res = entry->res;
 292                 if (res->flags & IORESOURCE_MEM)
 293                         root = &iomem_resource;
 294                 else if (res->flags & IORESOURCE_IO)
 295                         root = &ioport_resource;
 296                 else
 297                         BUG_ON(res);
 298
 299                 conflict = insert_resource_conflict(root, res);
 300                 if (conflict) {
 301                         dev_info(&info->bridge->dev,
 302                                  "ignoring host bridge window %pR (conflicts with %s %pR)\n",
 303                                  res, conflict->name, conflict);
 304                         resource_list_destroy_entry(entry);
 305                 }
 306         }
 307
 308         list_splice_tail(crs_res, resources);
 309 }
 310
 311 static void release_pci_root_info(struct pci_host_bridge *bridge)
 312 {
 313         struct resource *res;
 314         struct resource_entry *entry;
 315         struct pci_root_info *info = bridge->release_data;
 316
 317         resource_list_for_each_entry(entry, &bridge->windows) {
 318                 res = entry->res;
 319                 if (res->parent &&
 320                     (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 321                         release_resource(res);
 322         }
 323
 324         teardown_mcfg_map(info);
 325         kfree(info);
 326 }
 327
 328 static void probe_pci_root_info(struct pci_root_info *info,
 329                                 struct acpi_device *device,
 330                                 int busnum, int domain,
 331                                 struct list_head *list)
 332 {
 333         int ret;
 334         struct resource_entry *entry;
 335
 336         sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
 337         info->bridge = device;
 338         ret = acpi_dev_get_resources(device, list,
 339                                      acpi_dev_filter_resource_type_cb,
 340                                      (void *)(IORESOURCE_IO | IORESOURCE_MEM));
 341         if (ret < 0)
 342                 dev_warn(&device->dev,
 343                          "failed to parse _CRS method, error code %d\n", ret);
 344         else if (ret == 0)
 345                 dev_dbg(&device->dev,
 346                         "no IO and memory resources present in _CRS\n");
 347         else
 348                 resource_list_for_each_entry(entry, list)
 349                         entry->res->name = info->name;
 350 }
 351
 352 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 353 {
 354         struct acpi_device *device = root->device;
 355         struct pci_root_info *info;
 356         int domain = root->segment;
 357         int busnum = root->secondary.start;
 358         struct resource_entry *res_entry;
 359         LIST_HEAD(crs_res);
 360         LIST_HEAD(resources);
 361         struct pci_bus *bus;
 362         struct pci_sysdata *sd;
 363         int node;
 364
 365         if (pci_ignore_seg)
 366                 domain = 0;
 367
 368         if (domain && !pci_domains_supported) {
 369                 printk(KERN_WARNING "pci_bus %04x:%02x: "
 370                        "ignored (multiple domains not supported)\n",
 371                        domain, busnum);
 372                 return NULL;
 373         }
 374
 375         node = acpi_get_node(device->handle);
 376         if (node == NUMA_NO_NODE) {
 377                 node = x86_pci_root_bus_node(busnum);
 378                 if (node != 0 && node != NUMA_NO_NODE)
 379                         dev_info(&device->dev, FW_BUG "no _PXM; falling back to node %d from hardware (may be inconsistent with ACPI node numbers)\n",
 380                                 node);
 381         }
 382
 383         if (node != NUMA_NO_NODE && !node_online(node))
 384                 node = NUMA_NO_NODE;
 385
 386         info = kzalloc_node(sizeof(*info), GFP_KERNEL, node);
 387         if (!info) {
 388                 printk(KERN_WARNING "pci_bus %04x:%02x: "
 389                        "ignored (out of memory)\n", domain, busnum);
 390                 return NULL;
 391         }
 392
 393         sd = &info->sd;
 394         sd->domain = domain;
 395         sd->node = node;
 396         sd->companion = device;
 397
 398         bus = pci_find_bus(domain, busnum);
 399         if (bus) {
 400                 /*
 401                  * If the desired bus has been scanned already, replace
 402                  * its bus->sysdata.
 403                  */
 404                 memcpy(bus->sysdata, sd, sizeof(*sd));
 405                 kfree(info);
 406         } else {
 407                 /* insert busn res at first */
 408                 pci_add_resource(&resources,  &root->secondary);
 409
 410                 /*
 411                  * _CRS with no apertures is normal, so only fall back to
 412                  * defaults or native bridge info if we're ignoring _CRS.
 413                  */
 414                 probe_pci_root_info(info, device, busnum, domain, &crs_res);
 415                 if (pci_use_crs) {
 416                         add_resources(info, &resources, &crs_res);
 417                 } else {
 418                         resource_list_for_each_entry(res_entry, &crs_res)
 419                                 dev_printk(KERN_DEBUG, &device->dev,
 420                                            "host bridge window %pR (ignored)\n",
 421                                            res_entry->res);
 422                         resource_list_free(&crs_res);
 423                         x86_pci_root_bus_resources(busnum, &resources);
 424                 }
 425
 426                 if (!setup_mcfg_map(info, domain, (u8)root->secondary.start,
 427                                     (u8)root->secondary.end, root->mcfg_addr))
 428                         bus = pci_create_root_bus(NULL, busnum, &pci_root_ops,
 429                                                   sd, &resources);
 430
 431                 if (bus) {
 432                         pci_scan_child_bus(bus);
 433                         pci_set_host_bridge_release(
 434                                 to_pci_host_bridge(bus->bridge),
 435                                 release_pci_root_info, info);
 436                 } else {
 437                         resource_list_free(&resources);
 438                         teardown_mcfg_map(info);
 439                         kfree(info);
 440                 }
 441         }
 442
 443         /* After the PCI-E bus has been walked and all devices discovered,
 444          * configure any settings of the fabric that might be necessary.
 445          */
 446         if (bus) {
 447                 struct pci_bus *child;
 448                 list_for_each_entry(child, &bus->children, node)
 449                         pcie_bus_configure_settings(child);
 450         }
 451
 452         if (bus && node != NUMA_NO_NODE)
 453                 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
 454
 455         return bus;
 456 }
 457
 458 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
 459 {
 460         struct pci_sysdata *sd = bridge->bus->sysdata;
 461
 462         ACPI_COMPANION_SET(&bridge->dev, sd->companion);
 463         return 0;
 464 }
 465
 466 int __init pci_acpi_init(void)
 467 {
 468         struct pci_dev *dev = NULL;
 469
 470         if (acpi_noirq)
 471                 return -ENODEV;
 472
 473         printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
 474         acpi_irq_penalty_init();
 475         pcibios_enable_irq = acpi_pci_irq_enable;
 476         pcibios_disable_irq = acpi_pci_irq_disable;
 477         x86_init.pci.init_irq = x86_init_noop;
 478
 479         if (pci_routeirq) {
 480                 /*
 481                  * PCI IRQ routing is set up by pci_enable_device(), but we
 482                  * also do it here in case there are still broken drivers that
 483                  * don't use pci_enable_device().
 484                  */
 485                 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
 486                 for_each_pci_dev(dev)
 487                         acpi_pci_irq_enable(dev);
 488         }
 489
 490         return 0;
 491 }