arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/sfi_acpi.h>
  16 #include <linux/bitmap.h>
  17 #include <linux/dmi.h>
  18 #include <linux/slab.h>
  19 #include <linux/mutex.h>
  20 #include <linux/rculist.h>
  21 #include <asm/e820.h>
  22 #include <asm/pci_x86.h>
  23 #include <asm/acpi.h>
  24
  25 #define PREFIX "PCI: "
  26
  27 /* Indicate if the mmcfg resources have been placed into the resource table. */
  28 static bool pci_mmcfg_running_state;
  29 static bool pci_mmcfg_arch_init_failed;
  30 static DEFINE_MUTEX(pci_mmcfg_lock);
  31
  32 LIST_HEAD(pci_mmcfg_list);
  33
  34 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
  35 {
  36         if (cfg->res.parent)
  37                 release_resource(&cfg->res);
  38         list_del(&cfg->list);
  39         kfree(cfg);
  40 }
  41
  42 static __init void free_all_mmcfg(void)
  43 {
  44         struct pci_mmcfg_region *cfg, *tmp;
  45
  46         pci_mmcfg_arch_free();
  47         list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
  48                 pci_mmconfig_remove(cfg);
  49 }
  50
  51 static void list_add_sorted(struct pci_mmcfg_region *new)
  52 {
  53         struct pci_mmcfg_region *cfg;
  54
  55         /* keep list sorted by segment and starting bus number */
  56         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
  57                 if (cfg->segment > new->segment ||
  58                     (cfg->segment == new->segment &&
  59                      cfg->start_bus >= new->start_bus)) {
  60                         list_add_tail_rcu(&new->list, &cfg->list);
  61                         return;
  62                 }
  63         }
  64         list_add_tail_rcu(&new->list, &pci_mmcfg_list);
  65 }
  66
  67 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
  68                                                    int end, u64 addr)
  69 {
  70         struct pci_mmcfg_region *new;
  71         struct resource *res;
  72
  73         if (addr == 0)
  74                 return NULL;
  75
  76         new = kzalloc(sizeof(*new), GFP_KERNEL);
  77         if (!new)
  78                 return NULL;
  79
  80         new->address = addr;
  81         new->segment = segment;
  82         new->start_bus = start;
  83         new->end_bus = end;
  84
  85         res = &new->res;
  86         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
  87         res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
  88         res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  89         snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
  90                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
  91         res->name = new->name;
  92
  93         return new;
  94 }
  95
  96 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
  97                                                         int end, u64 addr)
  98 {
  99         struct pci_mmcfg_region *new;
 100
 101         new = pci_mmconfig_alloc(segment, start, end, addr);
 102         if (new) {
 103                 mutex_lock(&pci_mmcfg_lock);
 104                 list_add_sorted(new);
 105                 mutex_unlock(&pci_mmcfg_lock);
 106
 107                 pr_info(PREFIX
 108                        "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
 109                        "(base %#lx)\n",
 110                        segment, start, end, &new->res, (unsigned long)addr);
 111         }
 112
 113         return new;
 114 }
 115
 116 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 117 {
 118         struct pci_mmcfg_region *cfg;
 119
 120         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 121                 if (cfg->segment == segment &&
 122                     cfg->start_bus <= bus && bus <= cfg->end_bus)
 123                         return cfg;
 124
 125         return NULL;
 126 }
 127
 128 static const char __init *pci_mmcfg_e7520(void)
 129 {
 130         u32 win;
 131         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
 132
 133         win = win & 0xf000;
 134         if (win == 0x0000 || win == 0xf000)
 135                 return NULL;
 136
 137         if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
 138                 return NULL;
 139
 140         return "Intel Corporation E7520 Memory Controller Hub";
 141 }
 142
 143 static const char __init *pci_mmcfg_intel_945(void)
 144 {
 145         u32 pciexbar, mask = 0, len = 0;
 146
 147         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 148
 149         /* Enable bit */
 150         if (!(pciexbar & 1))
 151                 return NULL;
 152
 153         /* Size bits */
 154         switch ((pciexbar >> 1) & 3) {
 155         case 0:
 156                 mask = 0xf0000000U;
 157                 len  = 0x10000000U;
 158                 break;
 159         case 1:
 160                 mask = 0xf8000000U;
 161                 len  = 0x08000000U;
 162                 break;
 163         case 2:
 164                 mask = 0xfc000000U;
 165                 len  = 0x04000000U;
 166                 break;
 167         default:
 168                 return NULL;
 169         }
 170
 171         /* Errata #2, things break when not aligned on a 256Mb boundary */
 172         /* Can only happen in 64M/128M mode */
 173
 174         if ((pciexbar & mask) & 0x0fffffffU)
 175                 return NULL;
 176
 177         /* Don't hit the APIC registers and their friends */
 178         if ((pciexbar & mask) >= 0xf0000000U)
 179                 return NULL;
 180
 181         if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 182                 return NULL;
 183
 184         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 185 }
 186
 187 static const char __init *pci_mmcfg_amd_fam10h(void)
 188 {
 189         u32 low, high, address;
 190         u64 base, msr;
 191         int i;
 192         unsigned segnbits = 0, busnbits, end_bus;
 193
 194         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 195                 return NULL;
 196
 197         address = MSR_FAM10H_MMIO_CONF_BASE;
 198         if (rdmsr_safe(address, &low, &high))
 199                 return NULL;
 200
 201         msr = high;
 202         msr <<= 32;
 203         msr |= low;
 204
 205         /* mmconfig is not enable */
 206         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 207                 return NULL;
 208
 209         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 210
 211         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 212                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 213
 214         /*
 215          * only handle bus 0 ?
 216          * need to skip it
 217          */
 218         if (!busnbits)
 219                 return NULL;
 220
 221         if (busnbits > 8) {
 222                 segnbits = busnbits - 8;
 223                 busnbits = 8;
 224         }
 225
 226         end_bus = (1 << busnbits) - 1;
 227         for (i = 0; i < (1 << segnbits); i++)
 228                 if (pci_mmconfig_add(i, 0, end_bus,
 229                                      base + (1<<28) * i) == NULL) {
 230                         free_all_mmcfg();
 231                         return NULL;
 232                 }
 233
 234         return "AMD Family 10h NB";
 235 }
 236
 237 static bool __initdata mcp55_checked;
 238 static const char __init *pci_mmcfg_nvidia_mcp55(void)
 239 {
 240         int bus;
 241         int mcp55_mmconf_found = 0;
 242
 243         static const u32 extcfg_regnum          = 0x90;
 244         static const u32 extcfg_regsize         = 4;
 245         static const u32 extcfg_enable_mask     = 1<<31;
 246         static const u32 extcfg_start_mask      = 0xff<<16;
 247         static const int extcfg_start_shift     = 16;
 248         static const u32 extcfg_size_mask       = 0x3<<28;
 249         static const int extcfg_size_shift      = 28;
 250         static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
 251         static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
 252         static const int extcfg_base_lshift     = 25;
 253
 254         /*
 255          * do check if amd fam10h already took over
 256          */
 257         if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
 258                 return NULL;
 259
 260         mcp55_checked = true;
 261         for (bus = 0; bus < 256; bus++) {
 262                 u64 base;
 263                 u32 l, extcfg;
 264                 u16 vendor, device;
 265                 int start, size_index, end;
 266
 267                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 268                 vendor = l & 0xffff;
 269                 device = (l >> 16) & 0xffff;
 270
 271                 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 272                         continue;
 273
 274                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 275                                   extcfg_regsize, &extcfg);
 276
 277                 if (!(extcfg & extcfg_enable_mask))
 278                         continue;
 279
 280                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 281                 base = extcfg & extcfg_base_mask[size_index];
 282                 /* base could > 4G */
 283                 base <<= extcfg_base_lshift;
 284                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 285                 end = start + extcfg_sizebus[size_index] - 1;
 286                 if (pci_mmconfig_add(0, start, end, base) == NULL)
 287                         continue;
 288                 mcp55_mmconf_found++;
 289         }
 290
 291         if (!mcp55_mmconf_found)
 292                 return NULL;
 293
 294         return "nVidia MCP55";
 295 }
 296
 297 struct pci_mmcfg_hostbridge_probe {
 298         u32 bus;
 299         u32 devfn;
 300         u32 vendor;
 301         u32 device;
 302         const char *(*probe)(void);
 303 };
 304
 305 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 306         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 307           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 308         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 309           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 310         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 311           0x1200, pci_mmcfg_amd_fam10h },
 312         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 313           0x1200, pci_mmcfg_amd_fam10h },
 314         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 315           0x0369, pci_mmcfg_nvidia_mcp55 },
 316 };
 317
 318 static void __init pci_mmcfg_check_end_bus_number(void)
 319 {
 320         struct pci_mmcfg_region *cfg, *cfgx;
 321
 322         /* Fixup overlaps */
 323         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 324                 if (cfg->end_bus < cfg->start_bus)
 325                         cfg->end_bus = 255;
 326
 327                 /* Don't access the list head ! */
 328                 if (cfg->list.next == &pci_mmcfg_list)
 329                         break;
 330
 331                 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
 332                 if (cfg->end_bus >= cfgx->start_bus)
 333                         cfg->end_bus = cfgx->start_bus - 1;
 334         }
 335 }
 336
 337 static int __init pci_mmcfg_check_hostbridge(void)
 338 {
 339         u32 l;
 340         u32 bus, devfn;
 341         u16 vendor, device;
 342         int i;
 343         const char *name;
 344
 345         if (!raw_pci_ops)
 346                 return 0;
 347
 348         free_all_mmcfg();
 349
 350         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 351                 bus =  pci_mmcfg_probes[i].bus;
 352                 devfn = pci_mmcfg_probes[i].devfn;
 353                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 354                 vendor = l & 0xffff;
 355                 device = (l >> 16) & 0xffff;
 356
 357                 name = NULL;
 358                 if (pci_mmcfg_probes[i].vendor == vendor &&
 359                     pci_mmcfg_probes[i].device == device)
 360                         name = pci_mmcfg_probes[i].probe();
 361
 362                 if (name)
 363                         pr_info(PREFIX "%s with MMCONFIG support\n", name);
 364         }
 365
 366         /* some end_bus_number is crazy, fix it */
 367         pci_mmcfg_check_end_bus_number();
 368
 369         return !list_empty(&pci_mmcfg_list);
 370 }
 371
 372 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
 373 {
 374         struct resource *mcfg_res = data;
 375         struct acpi_resource_address64 address;
 376         acpi_status status;
 377
 378         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 379                 struct acpi_resource_fixed_memory32 *fixmem32 =
 380                         &res->data.fixed_memory32;
 381                 if (!fixmem32)
 382                         return AE_OK;
 383                 if ((mcfg_res->start >= fixmem32->address) &&
 384                     (mcfg_res->end < (fixmem32->address +
 385                                       fixmem32->address_length))) {
 386                         mcfg_res->flags = 1;
 387                         return AE_CTRL_TERMINATE;
 388                 }
 389         }
 390         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 391             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 392                 return AE_OK;
 393
 394         status = acpi_resource_to_address64(res, &address);
 395         if (ACPI_FAILURE(status) ||
 396            (address.address_length <= 0) ||
 397            (address.resource_type != ACPI_MEMORY_RANGE))
 398                 return AE_OK;
 399
 400         if ((mcfg_res->start >= address.minimum) &&
 401             (mcfg_res->end < (address.minimum + address.address_length))) {
 402                 mcfg_res->flags = 1;
 403                 return AE_CTRL_TERMINATE;
 404         }
 405         return AE_OK;
 406 }
 407
 408 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
 409                                         void *context, void **rv)
 410 {
 411         struct resource *mcfg_res = context;
 412
 413         acpi_walk_resources(handle, METHOD_NAME__CRS,
 414                             check_mcfg_resource, context);
 415
 416         if (mcfg_res->flags)
 417                 return AE_CTRL_TERMINATE;
 418
 419         return AE_OK;
 420 }
 421
 422 static int is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 423 {
 424         struct resource mcfg_res;
 425
 426         mcfg_res.start = start;
 427         mcfg_res.end = end - 1;
 428         mcfg_res.flags = 0;
 429
 430         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 431
 432         if (!mcfg_res.flags)
 433                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 434                                  NULL);
 435
 436         return mcfg_res.flags;
 437 }
 438
 439 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 440
 441 static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
 442                                     struct pci_mmcfg_region *cfg,
 443                                     struct device *dev, int with_e820)
 444 {
 445         u64 addr = cfg->res.start;
 446         u64 size = resource_size(&cfg->res);
 447         u64 old_size = size;
 448         int num_buses;
 449         char *method = with_e820 ? "E820" : "ACPI motherboard resources";
 450
 451         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
 452                 size >>= 1;
 453                 if (size < (16UL<<20))
 454                         break;
 455         }
 456
 457         if (size < (16UL<<20) && size != old_size)
 458                 return 0;
 459
 460         if (dev)
 461                 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
 462                          &cfg->res, method);
 463         else
 464                 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
 465                        &cfg->res, method);
 466
 467         if (old_size != size) {
 468                 /* update end_bus */
 469                 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
 470                 num_buses = cfg->end_bus - cfg->start_bus + 1;
 471                 cfg->res.end = cfg->res.start +
 472                     PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
 473                 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
 474                          "PCI MMCONFIG %04x [bus %02x-%02x]",
 475                          cfg->segment, cfg->start_bus, cfg->end_bus);
 476
 477                 if (dev)
 478                         dev_info(dev,
 479                                 "MMCONFIG "
 480                                 "at %pR (base %#lx) (size reduced!)\n",
 481                                 &cfg->res, (unsigned long) cfg->address);
 482                 else
 483                         pr_info(PREFIX
 484                                 "MMCONFIG for %04x [bus%02x-%02x] "
 485                                 "at %pR (base %#lx) (size reduced!)\n",
 486                                 cfg->segment, cfg->start_bus, cfg->end_bus,
 487                                 &cfg->res, (unsigned long) cfg->address);
 488         }
 489
 490         return 1;
 491 }
 492
 493 static int __ref pci_mmcfg_check_reserved(struct device *dev,
 494                   struct pci_mmcfg_region *cfg, int early)
 495 {
 496         if (!early && !acpi_disabled) {
 497                 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
 498                         return 1;
 499
 500                 if (dev)
 501                         dev_info(dev, FW_INFO
 502                                  "MMCONFIG at %pR not reserved in "
 503                                  "ACPI motherboard resources\n",
 504                                  &cfg->res);
 505                 else
 506                         pr_info(FW_INFO PREFIX
 507                                "MMCONFIG at %pR not reserved in "
 508                                "ACPI motherboard resources\n",
 509                                &cfg->res);
 510         }
 511
 512         /*
 513          * e820_all_mapped() is marked as __init.
 514          * All entries from ACPI MCFG table have been checked at boot time.
 515          * For MCFG information constructed from hotpluggable host bridge's
 516          * _CBA method, just assume it's reserved.
 517          */
 518         if (pci_mmcfg_running_state)
 519                 return 1;
 520
 521         /* Don't try to do this check unless configuration
 522            type 1 is available. how about type 2 ?*/
 523         if (raw_pci_ops)
 524                 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
 525
 526         return 0;
 527 }
 528
 529 static void __init pci_mmcfg_reject_broken(int early)
 530 {
 531         struct pci_mmcfg_region *cfg;
 532
 533         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 534                 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
 535                         pr_info(PREFIX "not using MMCONFIG\n");
 536                         free_all_mmcfg();
 537                         return;
 538                 }
 539         }
 540 }
 541
 542 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 543                                         struct acpi_mcfg_allocation *cfg)
 544 {
 545         int year;
 546
 547         if (cfg->address < 0xFFFFFFFF)
 548                 return 0;
 549
 550         if (!strncmp(mcfg->header.oem_id, "SGI", 3))
 551                 return 0;
 552
 553         if (mcfg->header.revision >= 1) {
 554                 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 555                     year >= 2010)
 556                         return 0;
 557         }
 558
 559         pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
 560                "is above 4GB, ignored\n", cfg->pci_segment,
 561                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 562         return -EINVAL;
 563 }
 564
 565 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 566 {
 567         struct acpi_table_mcfg *mcfg;
 568         struct acpi_mcfg_allocation *cfg_table, *cfg;
 569         unsigned long i;
 570         int entries;
 571
 572         if (!header)
 573                 return -EINVAL;
 574
 575         mcfg = (struct acpi_table_mcfg *)header;
 576
 577         /* how many config structures do we have */
 578         free_all_mmcfg();
 579         entries = 0;
 580         i = header->length - sizeof(struct acpi_table_mcfg);
 581         while (i >= sizeof(struct acpi_mcfg_allocation)) {
 582                 entries++;
 583                 i -= sizeof(struct acpi_mcfg_allocation);
 584         }
 585         if (entries == 0) {
 586                 pr_err(PREFIX "MMCONFIG has no entries\n");
 587                 return -ENODEV;
 588         }
 589
 590         cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 591         for (i = 0; i < entries; i++) {
 592                 cfg = &cfg_table[i];
 593                 if (acpi_mcfg_check_entry(mcfg, cfg)) {
 594                         free_all_mmcfg();
 595                         return -ENODEV;
 596                 }
 597
 598                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 599                                    cfg->end_bus_number, cfg->address) == NULL) {
 600                         pr_warn(PREFIX "no memory for MCFG entries\n");
 601                         free_all_mmcfg();
 602                         return -ENOMEM;
 603                 }
 604         }
 605
 606         return 0;
 607 }
 608
 609 static void __init __pci_mmcfg_init(int early)
 610 {
 611         pci_mmcfg_reject_broken(early);
 612         if (list_empty(&pci_mmcfg_list))
 613                 return;
 614
 615         if (pcibios_last_bus < 0) {
 616                 const struct pci_mmcfg_region *cfg;
 617
 618                 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 619                         if (cfg->segment)
 620                                 break;
 621                         pcibios_last_bus = cfg->end_bus;
 622                 }
 623         }
 624
 625         if (pci_mmcfg_arch_init())
 626                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 627         else {
 628                 free_all_mmcfg();
 629                 pci_mmcfg_arch_init_failed = true;
 630         }
 631 }
 632
 633 static int __initdata known_bridge;
 634
 635 void __init pci_mmcfg_early_init(void)
 636 {
 637         if (pci_probe & PCI_PROBE_MMCONF) {
 638                 if (pci_mmcfg_check_hostbridge())
 639                         known_bridge = 1;
 640                 else
 641                         acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 642                 __pci_mmcfg_init(1);
 643         }
 644 }
 645
 646 void __init pci_mmcfg_late_init(void)
 647 {
 648         /* MMCONFIG disabled */
 649         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 650                 return;
 651
 652         if (known_bridge)
 653                 return;
 654
 655         /* MMCONFIG hasn't been enabled yet, try again */
 656         if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
 657                 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 658                 __pci_mmcfg_init(0);
 659         }
 660 }
 661
 662 static int __init pci_mmcfg_late_insert_resources(void)
 663 {
 664         struct pci_mmcfg_region *cfg;
 665
 666         pci_mmcfg_running_state = true;
 667
 668         /* If we are not using MMCONFIG, don't insert the resources. */
 669         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 670                 return 1;
 671
 672         /*
 673          * Attempt to insert the mmcfg resources but not with the busy flag
 674          * marked so it won't cause request errors when __request_region is
 675          * called.
 676          */
 677         list_for_each_entry(cfg, &pci_mmcfg_list, list)
 678                 if (!cfg->res.parent)
 679                         insert_resource(&iomem_resource, &cfg->res);
 680
 681         return 0;
 682 }
 683
 684 /*
 685  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 686  * misprogrammed MCFG tables that state larger sizes but actually conflict
 687  * with other system resources.
 688  */
 689 late_initcall(pci_mmcfg_late_insert_resources);
 690
 691 /* Add MMCFG information for host bridges */
 692 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
 693                         phys_addr_t addr)
 694 {
 695         int rc;
 696         struct resource *tmp = NULL;
 697         struct pci_mmcfg_region *cfg;
 698
 699         if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
 700                 return -ENODEV;
 701
 702         if (start > end)
 703                 return -EINVAL;
 704
 705         mutex_lock(&pci_mmcfg_lock);
 706         cfg = pci_mmconfig_lookup(seg, start);
 707         if (cfg) {
 708                 if (cfg->end_bus < end)
 709                         dev_info(dev, FW_INFO
 710                                  "MMCONFIG for "
 711                                  "domain %04x [bus %02x-%02x] "
 712                                  "only partially covers this bridge\n",
 713                                   cfg->segment, cfg->start_bus, cfg->end_bus);
 714                 mutex_unlock(&pci_mmcfg_lock);
 715                 return -EEXIST;
 716         }
 717
 718         if (!addr) {
 719                 mutex_unlock(&pci_mmcfg_lock);
 720                 return -EINVAL;
 721         }
 722
 723         rc = -EBUSY;
 724         cfg = pci_mmconfig_alloc(seg, start, end, addr);
 725         if (cfg == NULL) {
 726                 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
 727                 rc = -ENOMEM;
 728         } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
 729                 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
 730                          &cfg->res);
 731         } else {
 732                 /* Insert resource if it's not in boot stage */
 733                 if (pci_mmcfg_running_state)
 734                         tmp = insert_resource_conflict(&iomem_resource,
 735                                                        &cfg->res);
 736
 737                 if (tmp) {
 738                         dev_warn(dev,
 739                                  "MMCONFIG %pR conflicts with "
 740                                  "%s %pR\n",
 741                                  &cfg->res, tmp->name, tmp);
 742                 } else if (pci_mmcfg_arch_map(cfg)) {
 743                         dev_warn(dev, "fail to map MMCONFIG %pR.\n",
 744                                  &cfg->res);
 745                 } else {
 746                         list_add_sorted(cfg);
 747                         dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
 748                                  &cfg->res, (unsigned long)addr);
 749                         cfg = NULL;
 750                         rc = 0;
 751                 }
 752         }
 753
 754         if (cfg) {
 755                 if (cfg->res.parent)
 756                         release_resource(&cfg->res);
 757                 kfree(cfg);
 758         }
 759
 760         mutex_unlock(&pci_mmcfg_lock);
 761
 762         return rc;
 763 }
 764
 765 /* Delete MMCFG information for host bridges */
 766 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
 767 {
 768         struct pci_mmcfg_region *cfg;
 769
 770         mutex_lock(&pci_mmcfg_lock);
 771         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 772                 if (cfg->segment == seg && cfg->start_bus == start &&
 773                     cfg->end_bus == end) {
 774                         list_del_rcu(&cfg->list);
 775                         synchronize_rcu();
 776                         pci_mmcfg_arch_unmap(cfg);
 777                         if (cfg->res.parent)
 778                                 release_resource(&cfg->res);
 779                         mutex_unlock(&pci_mmcfg_lock);
 780                         kfree(cfg);
 781                         return 0;
 782                 }
 783         mutex_unlock(&pci_mmcfg_lock);
 784
 785         return -ENOENT;
 786 }