arch/x86/platform/uv/uv_time.c

   1 /*
   2  * SGI RTC clock/timer routines.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  *  Copyright (c) 2009 Silicon Graphics, Inc.  All Rights Reserved.
  19  *  Copyright (c) Dimitri Sivanich
  20  */
  21 #include <linux/clockchips.h>
  22 #include <linux/slab.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/uv/bios.h>
  27 #include <asm/uv/uv.h>
  28 #include <asm/apic.h>
  29 #include <asm/cpu.h>
  30
  31 #define RTC_NAME                "sgi_rtc"
  32
  33 static cycle_t uv_read_rtc(struct clocksource *cs);
  34 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
  35 static void uv_rtc_timer_setup(enum clock_event_mode,
  36                                 struct clock_event_device *);
  37
  38 static struct clocksource clocksource_uv = {
  39         .name           = RTC_NAME,
  40         .rating         = 400,
  41         .read           = uv_read_rtc,
  42         .mask           = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
  43         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  44 };
  45
  46 static struct clock_event_device clock_event_device_uv = {
  47         .name           = RTC_NAME,
  48         .features       = CLOCK_EVT_FEAT_ONESHOT,
  49         .shift          = 20,
  50         .rating         = 400,
  51         .irq            = -1,
  52         .set_next_event = uv_rtc_next_event,
  53         .set_mode       = uv_rtc_timer_setup,
  54         .event_handler  = NULL,
  55 };
  56
  57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
  58
  59 /* There is one of these allocated per node */
  60 struct uv_rtc_timer_head {
  61         spinlock_t      lock;
  62         /* next cpu waiting for timer, local node relative: */
  63         int             next_cpu;
  64         /* number of cpus on this node: */
  65         int             ncpus;
  66         struct {
  67                 int     lcpu;           /* systemwide logical cpu number */
  68                 u64     expires;        /* next timer expiration for this cpu */
  69         } cpu[1];
  70 };
  71
  72 /*
  73  * Access to uv_rtc_timer_head via blade id.
  74  */
  75 static struct uv_rtc_timer_head         **blade_info __read_mostly;
  76
  77 static int                              uv_rtc_evt_enable;
  78
  79 /*
  80  * Hardware interface routines
  81  */
  82
  83 /* Send IPIs to another node */
  84 static void uv_rtc_send_IPI(int cpu)
  85 {
  86         unsigned long apicid, val;
  87         int pnode;
  88
  89         apicid = cpu_physical_id(cpu);
  90         pnode = uv_apicid_to_pnode(apicid);
  91         apicid |= uv_apicid_hibits;
  92         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  93               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  94               (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
  95
  96         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  97 }
  98
  99 /* Check for an RTC interrupt pending */
 100 static int uv_intr_pending(int pnode)
 101 {
 102         return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
 103                 UVH_EVENT_OCCURRED0_RTC1_MASK;
 104 }
 105
 106 /* Setup interrupt and return non-zero if early expiration occurred. */
 107 static int uv_setup_intr(int cpu, u64 expires)
 108 {
 109         u64 val;
 110         unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits;
 111         int pnode = uv_cpu_to_pnode(cpu);
 112
 113         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 114                 UVH_RTC1_INT_CONFIG_M_MASK);
 115         uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
 116
 117         uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
 118                 UVH_EVENT_OCCURRED0_RTC1_MASK);
 119
 120         val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
 121                 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
 122
 123         /* Set configuration */
 124         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
 125         /* Initialize comparator value */
 126         uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
 127
 128         if (uv_read_rtc(NULL) <= expires)
 129                 return 0;
 130
 131         return !uv_intr_pending(pnode);
 132 }
 133
 134 /*
 135  * Per-cpu timer tracking routines
 136  */
 137
 138 static __init void uv_rtc_deallocate_timers(void)
 139 {
 140         int bid;
 141
 142         for_each_possible_blade(bid) {
 143                 kfree(blade_info[bid]);
 144         }
 145         kfree(blade_info);
 146 }
 147
 148 /* Allocate per-node list of cpu timer expiration times. */
 149 static __init int uv_rtc_allocate_timers(void)
 150 {
 151         int cpu;
 152
 153         blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
 154         if (!blade_info)
 155                 return -ENOMEM;
 156         memset(blade_info, 0, uv_possible_blades * sizeof(void *));
 157
 158         for_each_present_cpu(cpu) {
 159                 int nid = cpu_to_node(cpu);
 160                 int bid = uv_cpu_to_blade_id(cpu);
 161                 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 162                 struct uv_rtc_timer_head *head = blade_info[bid];
 163
 164                 if (!head) {
 165                         head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
 166                                 (uv_blade_nr_possible_cpus(bid) *
 167                                         2 * sizeof(u64)),
 168                                 GFP_KERNEL, nid);
 169                         if (!head) {
 170                                 uv_rtc_deallocate_timers();
 171                                 return -ENOMEM;
 172                         }
 173                         spin_lock_init(&head->lock);
 174                         head->ncpus = uv_blade_nr_possible_cpus(bid);
 175                         head->next_cpu = -1;
 176                         blade_info[bid] = head;
 177                 }
 178
 179                 head->cpu[bcpu].lcpu = cpu;
 180                 head->cpu[bcpu].expires = ULLONG_MAX;
 181         }
 182
 183         return 0;
 184 }
 185
 186 /* Find and set the next expiring timer.  */
 187 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
 188 {
 189         u64 lowest = ULLONG_MAX;
 190         int c, bcpu = -1;
 191
 192         head->next_cpu = -1;
 193         for (c = 0; c < head->ncpus; c++) {
 194                 u64 exp = head->cpu[c].expires;
 195                 if (exp < lowest) {
 196                         bcpu = c;
 197                         lowest = exp;
 198                 }
 199         }
 200         if (bcpu >= 0) {
 201                 head->next_cpu = bcpu;
 202                 c = head->cpu[bcpu].lcpu;
 203                 if (uv_setup_intr(c, lowest))
 204                         /* If we didn't set it up in time, trigger */
 205                         uv_rtc_send_IPI(c);
 206         } else {
 207                 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 208                         UVH_RTC1_INT_CONFIG_M_MASK);
 209         }
 210 }
 211
 212 /*
 213  * Set expiration time for current cpu.
 214  *
 215  * Returns 1 if we missed the expiration time.
 216  */
 217 static int uv_rtc_set_timer(int cpu, u64 expires)
 218 {
 219         int pnode = uv_cpu_to_pnode(cpu);
 220         int bid = uv_cpu_to_blade_id(cpu);
 221         struct uv_rtc_timer_head *head = blade_info[bid];
 222         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 223         u64 *t = &head->cpu[bcpu].expires;
 224         unsigned long flags;
 225         int next_cpu;
 226
 227         spin_lock_irqsave(&head->lock, flags);
 228
 229         next_cpu = head->next_cpu;
 230         *t = expires;
 231
 232         /* Will this one be next to go off? */
 233         if (next_cpu < 0 || bcpu == next_cpu ||
 234                         expires < head->cpu[next_cpu].expires) {
 235                 head->next_cpu = bcpu;
 236                 if (uv_setup_intr(cpu, expires)) {
 237                         *t = ULLONG_MAX;
 238                         uv_rtc_find_next_timer(head, pnode);
 239                         spin_unlock_irqrestore(&head->lock, flags);
 240                         return -ETIME;
 241                 }
 242         }
 243
 244         spin_unlock_irqrestore(&head->lock, flags);
 245         return 0;
 246 }
 247
 248 /*
 249  * Unset expiration time for current cpu.
 250  *
 251  * Returns 1 if this timer was pending.
 252  */
 253 static int uv_rtc_unset_timer(int cpu, int force)
 254 {
 255         int pnode = uv_cpu_to_pnode(cpu);
 256         int bid = uv_cpu_to_blade_id(cpu);
 257         struct uv_rtc_timer_head *head = blade_info[bid];
 258         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 259         u64 *t = &head->cpu[bcpu].expires;
 260         unsigned long flags;
 261         int rc = 0;
 262
 263         spin_lock_irqsave(&head->lock, flags);
 264
 265         if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
 266                 rc = 1;
 267
 268         if (rc) {
 269                 *t = ULLONG_MAX;
 270                 /* Was the hardware setup for this timer? */
 271                 if (head->next_cpu == bcpu)
 272                         uv_rtc_find_next_timer(head, pnode);
 273         }
 274
 275         spin_unlock_irqrestore(&head->lock, flags);
 276
 277         return rc;
 278 }
 279
 280
 281 /*
 282  * Kernel interface routines.
 283  */
 284
 285 /*
 286  * Read the RTC.
 287  *
 288  * Starting with HUB rev 2.0, the UV RTC register is replicated across all
 289  * cachelines of it's own page.  This allows faster simultaneous reads
 290  * from a given socket.
 291  */
 292 static cycle_t uv_read_rtc(struct clocksource *cs)
 293 {
 294         unsigned long offset;
 295
 296         if (uv_get_min_hub_revision_id() == 1)
 297                 offset = 0;
 298         else
 299                 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
 300
 301         return (cycle_t)uv_read_local_mmr(UVH_RTC | offset);
 302 }
 303
 304 /*
 305  * Program the next event, relative to now
 306  */
 307 static int uv_rtc_next_event(unsigned long delta,
 308                              struct clock_event_device *ced)
 309 {
 310         int ced_cpu = cpumask_first(ced->cpumask);
 311
 312         return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
 313 }
 314
 315 /*
 316  * Setup the RTC timer in oneshot mode
 317  */
 318 static void uv_rtc_timer_setup(enum clock_event_mode mode,
 319                                struct clock_event_device *evt)
 320 {
 321         int ced_cpu = cpumask_first(evt->cpumask);
 322
 323         switch (mode) {
 324         case CLOCK_EVT_MODE_PERIODIC:
 325         case CLOCK_EVT_MODE_ONESHOT:
 326         case CLOCK_EVT_MODE_RESUME:
 327                 /* Nothing to do here yet */
 328                 break;
 329         case CLOCK_EVT_MODE_UNUSED:
 330         case CLOCK_EVT_MODE_SHUTDOWN:
 331                 uv_rtc_unset_timer(ced_cpu, 1);
 332                 break;
 333         }
 334 }
 335
 336 static void uv_rtc_interrupt(void)
 337 {
 338         int cpu = smp_processor_id();
 339         struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
 340
 341         if (!ced || !ced->event_handler)
 342                 return;
 343
 344         if (uv_rtc_unset_timer(cpu, 0) != 1)
 345                 return;
 346
 347         ced->event_handler(ced);
 348 }
 349
 350 static int __init uv_enable_evt_rtc(char *str)
 351 {
 352         uv_rtc_evt_enable = 1;
 353
 354         return 1;
 355 }
 356 __setup("uvrtcevt", uv_enable_evt_rtc);
 357
 358 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
 359 {
 360         struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
 361
 362         *ced = clock_event_device_uv;
 363         ced->cpumask = cpumask_of(smp_processor_id());
 364         clockevents_register_device(ced);
 365 }
 366
 367 static __init int uv_rtc_setup_clock(void)
 368 {
 369         int rc;
 370
 371         if (!is_uv_system())
 372                 return -ENODEV;
 373
 374         /* If single blade, prefer tsc */
 375         if (uv_num_possible_blades() == 1)
 376                 clocksource_uv.rating = 250;
 377
 378         rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
 379         if (rc)
 380                 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
 381         else
 382                 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
 383                         sn_rtc_cycles_per_second/(unsigned long)1E6);
 384
 385         if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
 386                 return rc;
 387
 388         /* Setup and register clockevents */
 389         rc = uv_rtc_allocate_timers();
 390         if (rc)
 391                 goto error;
 392
 393         x86_platform_ipi_callback = uv_rtc_interrupt;
 394
 395         clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
 396                                 NSEC_PER_SEC, clock_event_device_uv.shift);
 397
 398         clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
 399                                                 sn_rtc_cycles_per_second;
 400
 401         clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
 402                                 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
 403
 404         rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
 405         if (rc) {
 406                 x86_platform_ipi_callback = NULL;
 407                 uv_rtc_deallocate_timers();
 408                 goto error;
 409         }
 410
 411         printk(KERN_INFO "UV RTC clockevents registered\n");
 412
 413         return 0;
 414
 415 error:
 416         clocksource_unregister(&clocksource_uv);
 417         printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
 418
 419         return rc;
 420 }
 421 arch_initcall(uv_rtc_setup_clock);