x86/mpx: Restrict the mmap() size check to bounds tables
[deliverable/linux.git] / arch / x86 / power / cpu.c
1 /*
2 * Suspend support specific for i386/x86-64.
3 *
4 * Distribute under GPLv2
5 *
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9 */
10
11 #include <linux/suspend.h>
12 #include <linux/export.h>
13 #include <linux/smp.h>
14 #include <linux/perf_event.h>
15
16 #include <asm/pgtable.h>
17 #include <asm/proto.h>
18 #include <asm/mtrr.h>
19 #include <asm/page.h>
20 #include <asm/mce.h>
21 #include <asm/suspend.h>
22 #include <asm/fpu/internal.h>
23 #include <asm/debugreg.h>
24 #include <asm/cpu.h>
25
26 #ifdef CONFIG_X86_32
27 __visible unsigned long saved_context_ebx;
28 __visible unsigned long saved_context_esp, saved_context_ebp;
29 __visible unsigned long saved_context_esi, saved_context_edi;
30 __visible unsigned long saved_context_eflags;
31 #endif
32 struct saved_context saved_context;
33
34 /**
35 * __save_processor_state - save CPU registers before creating a
36 * hibernation image and before restoring the memory state from it
37 * @ctxt - structure to store the registers contents in
38 *
39 * NOTE: If there is a CPU register the modification of which by the
40 * boot kernel (ie. the kernel used for loading the hibernation image)
41 * might affect the operations of the restored target kernel (ie. the one
42 * saved in the hibernation image), then its contents must be saved by this
43 * function. In other words, if kernel A is hibernated and different
44 * kernel B is used for loading the hibernation image into memory, the
45 * kernel A's __save_processor_state() function must save all registers
46 * needed by kernel A, so that it can operate correctly after the resume
47 * regardless of what kernel B does in the meantime.
48 */
49 static void __save_processor_state(struct saved_context *ctxt)
50 {
51 #ifdef CONFIG_X86_32
52 mtrr_save_fixed_ranges(NULL);
53 #endif
54 kernel_fpu_begin();
55
56 /*
57 * descriptor tables
58 */
59 #ifdef CONFIG_X86_32
60 store_idt(&ctxt->idt);
61 #else
62 /* CONFIG_X86_64 */
63 store_idt((struct desc_ptr *)&ctxt->idt_limit);
64 #endif
65 /*
66 * We save it here, but restore it only in the hibernate case.
67 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
68 * mode in "secondary_startup_64". In 32-bit mode it is done via
69 * 'pmode_gdt' in wakeup_start.
70 */
71 ctxt->gdt_desc.size = GDT_SIZE - 1;
72 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
73
74 store_tr(ctxt->tr);
75
76 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
77 /*
78 * segment registers
79 */
80 #ifdef CONFIG_X86_32
81 savesegment(es, ctxt->es);
82 savesegment(fs, ctxt->fs);
83 savesegment(gs, ctxt->gs);
84 savesegment(ss, ctxt->ss);
85 #else
86 /* CONFIG_X86_64 */
87 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
88 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
89 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
90 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
91 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
92
93 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
94 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
95 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
96 mtrr_save_fixed_ranges(NULL);
97
98 rdmsrl(MSR_EFER, ctxt->efer);
99 #endif
100
101 /*
102 * control registers
103 */
104 ctxt->cr0 = read_cr0();
105 ctxt->cr2 = read_cr2();
106 ctxt->cr3 = read_cr3();
107 ctxt->cr4 = __read_cr4_safe();
108 #ifdef CONFIG_X86_64
109 ctxt->cr8 = read_cr8();
110 #endif
111 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
112 &ctxt->misc_enable);
113 }
114
115 /* Needed by apm.c */
116 void save_processor_state(void)
117 {
118 __save_processor_state(&saved_context);
119 x86_platform.save_sched_clock_state();
120 }
121 #ifdef CONFIG_X86_32
122 EXPORT_SYMBOL(save_processor_state);
123 #endif
124
125 static void do_fpu_end(void)
126 {
127 /*
128 * Restore FPU regs if necessary.
129 */
130 kernel_fpu_end();
131 }
132
133 static void fix_processor_context(void)
134 {
135 int cpu = smp_processor_id();
136 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
137 #ifdef CONFIG_X86_64
138 struct desc_struct *desc = get_cpu_gdt_table(cpu);
139 tss_desc tss;
140 #endif
141 set_tss_desc(cpu, t); /*
142 * This just modifies memory; should not be
143 * necessary. But... This is necessary, because
144 * 386 hardware has concept of busy TSS or some
145 * similar stupidity.
146 */
147
148 #ifdef CONFIG_X86_64
149 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
150 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
151 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
152
153 syscall_init(); /* This sets MSR_*STAR and related */
154 #endif
155 load_TR_desc(); /* This does ltr */
156 load_LDT(&current->active_mm->context); /* This does lldt */
157
158 fpu__resume_cpu();
159 }
160
161 /**
162 * __restore_processor_state - restore the contents of CPU registers saved
163 * by __save_processor_state()
164 * @ctxt - structure to load the registers contents from
165 */
166 static void notrace __restore_processor_state(struct saved_context *ctxt)
167 {
168 if (ctxt->misc_enable_saved)
169 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
170 /*
171 * control registers
172 */
173 /* cr4 was introduced in the Pentium CPU */
174 #ifdef CONFIG_X86_32
175 if (ctxt->cr4)
176 __write_cr4(ctxt->cr4);
177 #else
178 /* CONFIG X86_64 */
179 wrmsrl(MSR_EFER, ctxt->efer);
180 write_cr8(ctxt->cr8);
181 __write_cr4(ctxt->cr4);
182 #endif
183 write_cr3(ctxt->cr3);
184 write_cr2(ctxt->cr2);
185 write_cr0(ctxt->cr0);
186
187 /*
188 * now restore the descriptor tables to their proper values
189 * ltr is done i fix_processor_context().
190 */
191 #ifdef CONFIG_X86_32
192 load_idt(&ctxt->idt);
193 #else
194 /* CONFIG_X86_64 */
195 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
196 #endif
197
198 /*
199 * segment registers
200 */
201 #ifdef CONFIG_X86_32
202 loadsegment(es, ctxt->es);
203 loadsegment(fs, ctxt->fs);
204 loadsegment(gs, ctxt->gs);
205 loadsegment(ss, ctxt->ss);
206
207 /*
208 * sysenter MSRs
209 */
210 if (boot_cpu_has(X86_FEATURE_SEP))
211 enable_sep_cpu();
212 #else
213 /* CONFIG_X86_64 */
214 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
215 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
216 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
217 load_gs_index(ctxt->gs);
218 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
219
220 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
221 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
222 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
223 #endif
224
225 fix_processor_context();
226
227 do_fpu_end();
228 x86_platform.restore_sched_clock_state();
229 mtrr_bp_restore();
230 perf_restore_debug_store();
231 }
232
233 /* Needed by apm.c */
234 void notrace restore_processor_state(void)
235 {
236 __restore_processor_state(&saved_context);
237 }
238 #ifdef CONFIG_X86_32
239 EXPORT_SYMBOL(restore_processor_state);
240 #endif
241
242 /*
243 * When bsp_check() is called in hibernate and suspend, cpu hotplug
244 * is disabled already. So it's unnessary to handle race condition between
245 * cpumask query and cpu hotplug.
246 */
247 static int bsp_check(void)
248 {
249 if (cpumask_first(cpu_online_mask) != 0) {
250 pr_warn("CPU0 is offline.\n");
251 return -ENODEV;
252 }
253
254 return 0;
255 }
256
257 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
258 void *ptr)
259 {
260 int ret = 0;
261
262 switch (action) {
263 case PM_SUSPEND_PREPARE:
264 case PM_HIBERNATION_PREPARE:
265 ret = bsp_check();
266 break;
267 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
268 case PM_RESTORE_PREPARE:
269 /*
270 * When system resumes from hibernation, online CPU0 because
271 * 1. it's required for resume and
272 * 2. the CPU was online before hibernation
273 */
274 if (!cpu_online(0))
275 _debug_hotplug_cpu(0, 1);
276 break;
277 case PM_POST_RESTORE:
278 /*
279 * When a resume really happens, this code won't be called.
280 *
281 * This code is called only when user space hibernation software
282 * prepares for snapshot device during boot time. So we just
283 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
284 * preparing the snapshot device.
285 *
286 * This works for normal boot case in our CPU0 hotplug debug
287 * mode, i.e. CPU0 is offline and user mode hibernation
288 * software initializes during boot time.
289 *
290 * If CPU0 is online and user application accesses snapshot
291 * device after boot time, this will offline CPU0 and user may
292 * see different CPU0 state before and after accessing
293 * the snapshot device. But hopefully this is not a case when
294 * user debugging CPU0 hotplug. Even if users hit this case,
295 * they can easily online CPU0 back.
296 *
297 * To simplify this debug code, we only consider normal boot
298 * case. Otherwise we need to remember CPU0's state and restore
299 * to that state and resolve racy conditions etc.
300 */
301 _debug_hotplug_cpu(0, 0);
302 break;
303 #endif
304 default:
305 break;
306 }
307 return notifier_from_errno(ret);
308 }
309
310 static int __init bsp_pm_check_init(void)
311 {
312 /*
313 * Set this bsp_pm_callback as lower priority than
314 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
315 * earlier to disable cpu hotplug before bsp online check.
316 */
317 pm_notifier(bsp_pm_callback, -INT_MAX);
318 return 0;
319 }
320
321 core_initcall(bsp_pm_check_init);
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