arch/x86/xen/xen-asm.S

   1 /*
   2         Asm versions of Xen pv-ops, suitable for either direct use or inlining.
   3         The inline versions are the same as the direct-use versions, with the
   4         pre- and post-amble chopped off.
   5
   6         This code is encoded for size rather than absolute efficiency,
   7         with a view to being able to inline as much as possible.
   8
   9         We only bother with direct forms (ie, vcpu in pda) of the operations
  10         here; the indirect forms are better handled in C, since they're
  11         generally too large to inline anyway.
  12  */
  13
  14 #include <linux/linkage.h>
  15
  16 #include <asm/asm-offsets.h>
  17 #include <asm/thread_info.h>
  18 #include <asm/percpu.h>
  19 #include <asm/processor-flags.h>
  20 #include <asm/segment.h>
  21
  22 #include <xen/interface/xen.h>
  23
  24 #define RELOC(x, v)     .globl x##_reloc; x##_reloc=v
  25 #define ENDPATCH(x)     .globl x##_end; x##_end=.
  26
  27 /* Pseudo-flag used for virtual NMI, which we don't implement yet */
  28 #define XEN_EFLAGS_NMI  0x80000000
  29
  30 /*
  31         Enable events.  This clears the event mask and tests the pending
  32         event status with one and operation.  If there are pending
  33         events, then enter the hypervisor to get them handled.
  34  */
  35 ENTRY(xen_irq_enable_direct)
  36         /* Unmask events */
  37         movb $0, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
  38
  39         /* Preempt here doesn't matter because that will deal with
  40            any pending interrupts.  The pending check may end up being
  41            run on the wrong CPU, but that doesn't hurt. */
  42
  43         /* Test for pending */
  44         testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
  45         jz 1f
  46
  47 2:      call check_events
  48 1:
  49 ENDPATCH(xen_irq_enable_direct)
  50         ret
  51         ENDPROC(xen_irq_enable_direct)
  52         RELOC(xen_irq_enable_direct, 2b+1)
  53
  54
  55 /*
  56         Disabling events is simply a matter of making the event mask
  57         non-zero.
  58  */
  59 ENTRY(xen_irq_disable_direct)
  60         movb $1, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
  61 ENDPATCH(xen_irq_disable_direct)
  62         ret
  63         ENDPROC(xen_irq_disable_direct)
  64         RELOC(xen_irq_disable_direct, 0)
  65
  66 /*
  67         (xen_)save_fl is used to get the current interrupt enable status.
  68         Callers expect the status to be in X86_EFLAGS_IF, and other bits
  69         may be set in the return value.  We take advantage of this by
  70         making sure that X86_EFLAGS_IF has the right value (and other bits
  71         in that byte are 0), but other bits in the return value are
  72         undefined.  We need to toggle the state of the bit, because
  73         Xen and x86 use opposite senses (mask vs enable).
  74  */
  75 ENTRY(xen_save_fl_direct)
  76         testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
  77         setz %ah
  78         addb %ah,%ah
  79 ENDPATCH(xen_save_fl_direct)
  80         ret
  81         ENDPROC(xen_save_fl_direct)
  82         RELOC(xen_save_fl_direct, 0)
  83
  84
  85 /*
  86         In principle the caller should be passing us a value return
  87         from xen_save_fl_direct, but for robustness sake we test only
  88         the X86_EFLAGS_IF flag rather than the whole byte. After
  89         setting the interrupt mask state, it checks for unmasked
  90         pending events and enters the hypervisor to get them delivered
  91         if so.
  92  */
  93 ENTRY(xen_restore_fl_direct)
  94         testb $X86_EFLAGS_IF>>8, %ah
  95         setz PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
  96         /* Preempt here doesn't matter because that will deal with
  97            any pending interrupts.  The pending check may end up being
  98            run on the wrong CPU, but that doesn't hurt. */
  99
 100         /* check for unmasked and pending */
 101         cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
 102         jz 1f
 103 2:      call check_events
 104 1:
 105 ENDPATCH(xen_restore_fl_direct)
 106         ret
 107         ENDPROC(xen_restore_fl_direct)
 108         RELOC(xen_restore_fl_direct, 2b+1)
 109
 110 /*
 111         This is run where a normal iret would be run, with the same stack setup:
 112               8: eflags
 113               4: cs
 114         esp-> 0: eip
 115
 116         This attempts to make sure that any pending events are dealt
 117         with on return to usermode, but there is a small window in
 118         which an event can happen just before entering usermode.  If
 119         the nested interrupt ends up setting one of the TIF_WORK_MASK
 120         pending work flags, they will not be tested again before
 121         returning to usermode. This means that a process can end up
 122         with pending work, which will be unprocessed until the process
 123         enters and leaves the kernel again, which could be an
 124         unbounded amount of time.  This means that a pending signal or
 125         reschedule event could be indefinitely delayed.
 126
 127         The fix is to notice a nested interrupt in the critical
 128         window, and if one occurs, then fold the nested interrupt into
 129         the current interrupt stack frame, and re-process it
 130         iteratively rather than recursively.  This means that it will
 131         exit via the normal path, and all pending work will be dealt
 132         with appropriately.
 133
 134         Because the nested interrupt handler needs to deal with the
 135         current stack state in whatever form its in, we keep things
 136         simple by only using a single register which is pushed/popped
 137         on the stack.
 138  */
 139 ENTRY(xen_iret)
 140         /* test eflags for special cases */
 141         testl $(X86_EFLAGS_VM | XEN_EFLAGS_NMI), 8(%esp)
 142         jnz hyper_iret
 143
 144         push %eax
 145         ESP_OFFSET=4    # bytes pushed onto stack
 146
 147         /* Store vcpu_info pointer for easy access.  Do it this
 148            way to avoid having to reload %fs */
 149 #ifdef CONFIG_SMP
 150         GET_THREAD_INFO(%eax)
 151         movl TI_cpu(%eax),%eax
 152         movl __per_cpu_offset(,%eax,4),%eax
 153         mov per_cpu__xen_vcpu(%eax),%eax
 154 #else
 155         movl per_cpu__xen_vcpu, %eax
 156 #endif
 157
 158         /* check IF state we're restoring */
 159         testb $X86_EFLAGS_IF>>8, 8+1+ESP_OFFSET(%esp)
 160
 161         /* Maybe enable events.  Once this happens we could get a
 162            recursive event, so the critical region starts immediately
 163            afterwards.  However, if that happens we don't end up
 164            resuming the code, so we don't have to be worried about
 165            being preempted to another CPU. */
 166         setz XEN_vcpu_info_mask(%eax)
 167 xen_iret_start_crit:
 168
 169         /* check for unmasked and pending */
 170         cmpw $0x0001, XEN_vcpu_info_pending(%eax)
 171
 172         /* If there's something pending, mask events again so we
 173            can jump back into xen_hypervisor_callback */
 174         sete XEN_vcpu_info_mask(%eax)
 175
 176         popl %eax
 177
 178         /* From this point on the registers are restored and the stack
 179            updated, so we don't need to worry about it if we're preempted */
 180 iret_restore_end:
 181
 182         /* Jump to hypervisor_callback after fixing up the stack.
 183            Events are masked, so jumping out of the critical
 184            region is OK. */
 185         je xen_hypervisor_callback
 186
 187 1:      iret
 188 xen_iret_end_crit:
 189 .section __ex_table,"a"
 190         .align 4
 191         .long 1b,iret_exc
 192 .previous
 193
 194 hyper_iret:
 195         /* put this out of line since its very rarely used */
 196         jmp hypercall_page + __HYPERVISOR_iret * 32
 197
 198         .globl xen_iret_start_crit, xen_iret_end_crit
 199
 200 /*
 201    This is called by xen_hypervisor_callback in entry.S when it sees
 202    that the EIP at the time of interrupt was between xen_iret_start_crit
 203    and xen_iret_end_crit.  We're passed the EIP in %eax so we can do
 204    a more refined determination of what to do.
 205
 206    The stack format at this point is:
 207         ----------------
 208          ss             : (ss/esp may be present if we came from usermode)
 209          esp            :
 210          eflags         }  outer exception info
 211          cs             }
 212          eip            }
 213         ---------------- <- edi (copy dest)
 214          eax            :  outer eax if it hasn't been restored
 215         ----------------
 216          eflags         }  nested exception info
 217          cs             }   (no ss/esp because we're nested
 218          eip            }    from the same ring)
 219          orig_eax       }<- esi (copy src)
 220          - - - - - - - -
 221          fs             }
 222          es             }
 223          ds             }  SAVE_ALL state
 224          eax            }
 225           :             :
 226          ebx            }
 227         ----------------
 228          return addr     <- esp
 229         ----------------
 230
 231    In order to deliver the nested exception properly, we need to shift
 232    everything from the return addr up to the error code so it
 233    sits just under the outer exception info.  This means that when we
 234    handle the exception, we do it in the context of the outer exception
 235    rather than starting a new one.
 236
 237    The only caveat is that if the outer eax hasn't been
 238    restored yet (ie, it's still on stack), we need to insert
 239    its value into the SAVE_ALL state before going on, since
 240    it's usermode state which we eventually need to restore.
 241  */
 242 ENTRY(xen_iret_crit_fixup)
 243         /* offsets +4 for return address */
 244
 245         /*
 246            Paranoia: Make sure we're really coming from userspace.
 247            One could imagine a case where userspace jumps into the
 248            critical range address, but just before the CPU delivers a GP,
 249            it decides to deliver an interrupt instead.  Unlikely?
 250            Definitely.  Easy to avoid?  Yes.  The Intel documents
 251            explicitly say that the reported EIP for a bad jump is the
 252            jump instruction itself, not the destination, but some virtual
 253            environments get this wrong.
 254          */
 255         movl PT_CS+4(%esp), %ecx
 256         andl $SEGMENT_RPL_MASK, %ecx
 257         cmpl $USER_RPL, %ecx
 258         je 2f
 259
 260         lea PT_ORIG_EAX+4(%esp), %esi
 261         lea PT_EFLAGS+4(%esp), %edi
 262
 263         /* If eip is before iret_restore_end then stack
 264            hasn't been restored yet. */
 265         cmp $iret_restore_end, %eax
 266         jae 1f
 267
 268         movl 0+4(%edi),%eax             /* copy EAX */
 269         movl %eax, PT_EAX+4(%esp)
 270
 271         lea ESP_OFFSET(%edi),%edi       /* move dest up over saved regs */
 272
 273         /* set up the copy */
 274 1:      std
 275         mov $(PT_EIP+4) / 4, %ecx       /* copy ret+saved regs up to orig_eax */
 276         rep movsl
 277         cld
 278
 279         lea 4(%edi),%esp                /* point esp to new frame */
 280 2:      ret
 281
 282
 283 /*
 284         Force an event check by making a hypercall,
 285         but preserve regs before making the call.
 286  */
 287 check_events:
 288         push %eax
 289         push %ecx
 290         push %edx
 291         call force_evtchn_callback
 292         pop %edx
 293         pop %ecx
 294         pop %eax
 295         ret