2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/module.h>
29 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/pgalloc.h>
34 #include <asm/mach_apic.h>
37 #include <asm/proto.h>
38 #include <asm/timex.h>
43 int apic_runs_main_timer
;
44 int apic_calibrate_pmtmr __initdata
;
46 int disable_apic_timer __initdata
;
49 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
50 * IPIs in place of local APIC timers
52 static cpumask_t timer_interrupt_broadcast_ipi_mask
;
54 /* Using APIC to generate smp_local_timer_interrupt? */
55 int using_apic_timer __read_mostly
= 0;
57 static void apic_pm_activate(void);
59 void enable_NMI_through_LVT0 (void * dummy
)
63 v
= APIC_DM_NMI
; /* unmask and set to NMI */
64 apic_write(APIC_LVT0
, v
);
69 unsigned int v
, maxlvt
;
71 v
= apic_read(APIC_LVR
);
72 maxlvt
= GET_APIC_MAXLVT(v
);
77 * 'what should we do if we get a hw irq event on an illegal vector'.
78 * each architecture has to answer this themselves.
80 void ack_bad_irq(unsigned int irq
)
82 printk("unexpected IRQ trap at vector %02x\n", irq
);
84 * Currently unexpected vectors happen only on SMP and APIC.
85 * We _must_ ack these because every local APIC has only N
86 * irq slots per priority level, and a 'hanging, unacked' IRQ
87 * holds up an irq slot - in excessive cases (when multiple
88 * unexpected vectors occur) that might lock up the APIC
90 * But don't ack when the APIC is disabled. -AK
96 void clear_local_APIC(void)
101 maxlvt
= get_maxlvt();
104 * Masking an LVT entry can trigger a local APIC error
105 * if the vector is zero. Mask LVTERR first to prevent this.
108 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
109 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
112 * Careful: we have to set masks only first to deassert
113 * any level-triggered sources.
115 v
= apic_read(APIC_LVTT
);
116 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
117 v
= apic_read(APIC_LVT0
);
118 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
119 v
= apic_read(APIC_LVT1
);
120 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
122 v
= apic_read(APIC_LVTPC
);
123 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
127 * Clean APIC state for other OSs:
129 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
130 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
131 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
133 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
135 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
136 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
137 apic_write(APIC_ESR
, 0);
141 void disconnect_bsp_APIC(int virt_wire_setup
)
143 /* Go back to Virtual Wire compatibility mode */
146 /* For the spurious interrupt use vector F, and enable it */
147 value
= apic_read(APIC_SPIV
);
148 value
&= ~APIC_VECTOR_MASK
;
149 value
|= APIC_SPIV_APIC_ENABLED
;
151 apic_write(APIC_SPIV
, value
);
153 if (!virt_wire_setup
) {
154 /* For LVT0 make it edge triggered, active high, external and enabled */
155 value
= apic_read(APIC_LVT0
);
156 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
157 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
158 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
159 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
160 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
161 apic_write(APIC_LVT0
, value
);
164 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
167 /* For LVT1 make it edge triggered, active high, nmi and enabled */
168 value
= apic_read(APIC_LVT1
);
169 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
170 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
171 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
172 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
173 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
174 apic_write(APIC_LVT1
, value
);
177 void disable_local_APIC(void)
184 * Disable APIC (implies clearing of registers
187 value
= apic_read(APIC_SPIV
);
188 value
&= ~APIC_SPIV_APIC_ENABLED
;
189 apic_write(APIC_SPIV
, value
);
193 * This is to verify that we're looking at a real local APIC.
194 * Check these against your board if the CPUs aren't getting
195 * started for no apparent reason.
197 int __init
verify_local_APIC(void)
199 unsigned int reg0
, reg1
;
202 * The version register is read-only in a real APIC.
204 reg0
= apic_read(APIC_LVR
);
205 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
206 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
207 reg1
= apic_read(APIC_LVR
);
208 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
211 * The two version reads above should print the same
212 * numbers. If the second one is different, then we
213 * poke at a non-APIC.
219 * Check if the version looks reasonably.
221 reg1
= GET_APIC_VERSION(reg0
);
222 if (reg1
== 0x00 || reg1
== 0xff)
225 if (reg1
< 0x02 || reg1
== 0xff)
229 * The ID register is read/write in a real APIC.
231 reg0
= apic_read(APIC_ID
);
232 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
233 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
234 reg1
= apic_read(APIC_ID
);
235 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
236 apic_write(APIC_ID
, reg0
);
237 if (reg1
!= (reg0
^ APIC_ID_MASK
))
241 * The next two are just to see if we have sane values.
242 * They're only really relevant if we're in Virtual Wire
243 * compatibility mode, but most boxes are anymore.
245 reg0
= apic_read(APIC_LVT0
);
246 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
247 reg1
= apic_read(APIC_LVT1
);
248 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
253 void __init
sync_Arb_IDs(void)
255 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
256 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
257 if (ver
>= 0x14) /* P4 or higher */
263 apic_wait_icr_idle();
265 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
266 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
271 * An initial setup of the virtual wire mode.
273 void __init
init_bsp_APIC(void)
278 * Don't do the setup now if we have a SMP BIOS as the
279 * through-I/O-APIC virtual wire mode might be active.
281 if (smp_found_config
|| !cpu_has_apic
)
284 value
= apic_read(APIC_LVR
);
287 * Do not trust the local APIC being empty at bootup.
294 value
= apic_read(APIC_SPIV
);
295 value
&= ~APIC_VECTOR_MASK
;
296 value
|= APIC_SPIV_APIC_ENABLED
;
297 value
|= APIC_SPIV_FOCUS_DISABLED
;
298 value
|= SPURIOUS_APIC_VECTOR
;
299 apic_write(APIC_SPIV
, value
);
302 * Set up the virtual wire mode.
304 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
306 apic_write(APIC_LVT1
, value
);
309 void __cpuinit
setup_local_APIC (void)
311 unsigned int value
, maxlvt
;
314 value
= apic_read(APIC_LVR
);
316 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
319 * Double-check whether this APIC is really registered.
320 * This is meaningless in clustered apic mode, so we skip it.
322 if (!apic_id_registered())
326 * Intel recommends to set DFR, LDR and TPR before enabling
327 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
328 * document number 292116). So here it goes...
333 * Set Task Priority to 'accept all'. We never change this
336 value
= apic_read(APIC_TASKPRI
);
337 value
&= ~APIC_TPRI_MASK
;
338 apic_write(APIC_TASKPRI
, value
);
341 * After a crash, we no longer service the interrupts and a pending
342 * interrupt from previous kernel might still have ISR bit set.
344 * Most probably by now CPU has serviced that pending interrupt and
345 * it might not have done the ack_APIC_irq() because it thought,
346 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
347 * does not clear the ISR bit and cpu thinks it has already serivced
348 * the interrupt. Hence a vector might get locked. It was noticed
349 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
351 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
352 value
= apic_read(APIC_ISR
+ i
*0x10);
353 for (j
= 31; j
>= 0; j
--) {
360 * Now that we are all set up, enable the APIC
362 value
= apic_read(APIC_SPIV
);
363 value
&= ~APIC_VECTOR_MASK
;
367 value
|= APIC_SPIV_APIC_ENABLED
;
369 /* We always use processor focus */
372 * Set spurious IRQ vector
374 value
|= SPURIOUS_APIC_VECTOR
;
375 apic_write(APIC_SPIV
, value
);
380 * set up through-local-APIC on the BP's LINT0. This is not
381 * strictly necessary in pure symmetric-IO mode, but sometimes
382 * we delegate interrupts to the 8259A.
385 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
387 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
388 if (!smp_processor_id() && !value
) {
389 value
= APIC_DM_EXTINT
;
390 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
392 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
393 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
395 apic_write(APIC_LVT0
, value
);
398 * only the BP should see the LINT1 NMI signal, obviously.
400 if (!smp_processor_id())
403 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
404 apic_write(APIC_LVT1
, value
);
408 maxlvt
= get_maxlvt();
409 oldvalue
= apic_read(APIC_ESR
);
410 value
= ERROR_APIC_VECTOR
; // enables sending errors
411 apic_write(APIC_LVTERR
, value
);
413 * spec says clear errors after enabling vector.
416 apic_write(APIC_ESR
, 0);
417 value
= apic_read(APIC_ESR
);
418 if (value
!= oldvalue
)
419 apic_printk(APIC_VERBOSE
,
420 "ESR value after enabling vector: %08x, after %08x\n",
424 nmi_watchdog_default();
425 setup_apic_nmi_watchdog(NULL
);
432 /* 'active' is true if the local APIC was enabled by us and
433 not the BIOS; this signifies that we are also responsible
434 for disabling it before entering apm/acpi suspend */
436 /* r/w apic fields */
437 unsigned int apic_id
;
438 unsigned int apic_taskpri
;
439 unsigned int apic_ldr
;
440 unsigned int apic_dfr
;
441 unsigned int apic_spiv
;
442 unsigned int apic_lvtt
;
443 unsigned int apic_lvtpc
;
444 unsigned int apic_lvt0
;
445 unsigned int apic_lvt1
;
446 unsigned int apic_lvterr
;
447 unsigned int apic_tmict
;
448 unsigned int apic_tdcr
;
449 unsigned int apic_thmr
;
452 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
456 if (!apic_pm_state
.active
)
459 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
460 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
461 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
462 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
463 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
464 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
465 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
466 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
467 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
468 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
469 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
470 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
471 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
472 local_irq_save(flags
);
473 disable_local_APIC();
474 local_irq_restore(flags
);
478 static int lapic_resume(struct sys_device
*dev
)
483 if (!apic_pm_state
.active
)
486 local_irq_save(flags
);
487 rdmsr(MSR_IA32_APICBASE
, l
, h
);
488 l
&= ~MSR_IA32_APICBASE_BASE
;
489 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
490 wrmsr(MSR_IA32_APICBASE
, l
, h
);
491 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
492 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
493 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
494 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
495 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
496 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
497 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
498 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
499 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
500 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
501 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
502 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
503 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
504 apic_write(APIC_ESR
, 0);
506 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
507 apic_write(APIC_ESR
, 0);
509 local_irq_restore(flags
);
513 static struct sysdev_class lapic_sysclass
= {
514 set_kset_name("lapic"),
515 .resume
= lapic_resume
,
516 .suspend
= lapic_suspend
,
519 static struct sys_device device_lapic
= {
521 .cls
= &lapic_sysclass
,
524 static void __cpuinit
apic_pm_activate(void)
526 apic_pm_state
.active
= 1;
529 static int __init
init_lapic_sysfs(void)
534 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
535 error
= sysdev_class_register(&lapic_sysclass
);
537 error
= sysdev_register(&device_lapic
);
540 device_initcall(init_lapic_sysfs
);
542 #else /* CONFIG_PM */
544 static void apic_pm_activate(void) { }
546 #endif /* CONFIG_PM */
548 static int __init
apic_set_verbosity(char *str
)
551 skip_ioapic_setup
= 0;
555 if (strcmp("debug", str
) == 0)
556 apic_verbosity
= APIC_DEBUG
;
557 else if (strcmp("verbose", str
) == 0)
558 apic_verbosity
= APIC_VERBOSE
;
560 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
561 " use apic=verbose or apic=debug\n", str
);
567 early_param("apic", apic_set_verbosity
);
570 * Detect and enable local APICs on non-SMP boards.
571 * Original code written by Keir Fraser.
572 * On AMD64 we trust the BIOS - if it says no APIC it is likely
573 * not correctly set up (usually the APIC timer won't work etc.)
576 static int __init
detect_init_APIC (void)
579 printk(KERN_INFO
"No local APIC present\n");
583 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
588 void __init
init_apic_mappings(void)
590 unsigned long apic_phys
;
593 * If no local APIC can be found then set up a fake all
594 * zeroes page to simulate the local APIC and another
595 * one for the IO-APIC.
597 if (!smp_found_config
&& detect_init_APIC()) {
598 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
599 apic_phys
= __pa(apic_phys
);
601 apic_phys
= mp_lapic_addr
;
603 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
605 apic_printk(APIC_VERBOSE
,"mapped APIC to %16lx (%16lx)\n", APIC_BASE
, apic_phys
);
608 * Fetch the APIC ID of the BSP in case we have a
609 * default configuration (or the MP table is broken).
611 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
614 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
617 for (i
= 0; i
< nr_ioapics
; i
++) {
618 if (smp_found_config
) {
619 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
621 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
622 ioapic_phys
= __pa(ioapic_phys
);
624 set_fixmap_nocache(idx
, ioapic_phys
);
625 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
626 __fix_to_virt(idx
), ioapic_phys
);
633 * This function sets up the local APIC timer, with a timeout of
634 * 'clocks' APIC bus clock. During calibration we actually call
635 * this function twice on the boot CPU, once with a bogus timeout
636 * value, second time for real. The other (noncalibrating) CPUs
637 * call this function only once, with the real, calibrated value.
639 * We do reads before writes even if unnecessary, to get around the
640 * P5 APIC double write bug.
643 #define APIC_DIVISOR 16
645 static void __setup_APIC_LVTT(unsigned int clocks
)
647 unsigned int lvtt_value
, tmp_value
, ver
;
648 int cpu
= smp_processor_id();
650 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
651 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
653 if (cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
))
654 lvtt_value
|= APIC_LVT_MASKED
;
656 apic_write(APIC_LVTT
, lvtt_value
);
661 tmp_value
= apic_read(APIC_TDCR
);
662 apic_write(APIC_TDCR
, (tmp_value
663 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
666 apic_write(APIC_TMICT
, clocks
/APIC_DIVISOR
);
669 static void setup_APIC_timer(unsigned int clocks
)
673 local_irq_save(flags
);
675 /* wait for irq slice */
676 if (vxtime
.hpet_address
&& hpet_use_timer
) {
677 int trigger
= hpet_readl(HPET_T0_CMP
);
678 while (hpet_readl(HPET_COUNTER
) >= trigger
)
680 while (hpet_readl(HPET_COUNTER
) < trigger
)
686 c2
|= inb_p(0x40) << 8;
691 c2
|= inb_p(0x40) << 8;
692 } while (c2
- c1
< 300);
694 __setup_APIC_LVTT(clocks
);
695 /* Turn off PIT interrupt if we use APIC timer as main timer.
696 Only works with the PM timer right now
697 TBD fix it for HPET too. */
698 if (vxtime
.mode
== VXTIME_PMTMR
&&
699 smp_processor_id() == boot_cpu_id
&&
700 apic_runs_main_timer
== 1 &&
701 !cpu_isset(boot_cpu_id
, timer_interrupt_broadcast_ipi_mask
)) {
702 stop_timer_interrupt();
703 apic_runs_main_timer
++;
705 local_irq_restore(flags
);
709 * In this function we calibrate APIC bus clocks to the external
710 * timer. Unfortunately we cannot use jiffies and the timer irq
711 * to calibrate, since some later bootup code depends on getting
712 * the first irq? Ugh.
714 * We want to do the calibration only once since we
715 * want to have local timer irqs syncron. CPUs connected
716 * by the same APIC bus have the very same bus frequency.
717 * And we want to have irqs off anyways, no accidental
721 #define TICK_COUNT 100000000
723 static int __init
calibrate_APIC_clock(void)
725 int apic
, apic_start
, tsc
, tsc_start
;
728 * Put whatever arbitrary (but long enough) timeout
729 * value into the APIC clock, we just want to get the
730 * counter running for calibration.
732 __setup_APIC_LVTT(1000000000);
734 apic_start
= apic_read(APIC_TMCCT
);
735 #ifdef CONFIG_X86_PM_TIMER
736 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
737 pmtimer_wait(5000); /* 5ms wait */
738 apic
= apic_read(APIC_TMCCT
);
739 result
= (apic_start
- apic
) * 1000L / 5;
746 apic
= apic_read(APIC_TMCCT
);
748 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
749 (apic
- apic_start
) < TICK_COUNT
);
751 result
= (apic_start
- apic
) * 1000L * cpu_khz
/
754 printk("result %d\n", result
);
757 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
758 result
/ 1000 / 1000, result
/ 1000 % 1000);
760 return result
* APIC_DIVISOR
/ HZ
;
763 static unsigned int calibration_result
;
765 void __init
setup_boot_APIC_clock (void)
767 if (disable_apic_timer
) {
768 printk(KERN_INFO
"Disabling APIC timer\n");
772 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
773 using_apic_timer
= 1;
777 calibration_result
= calibrate_APIC_clock();
779 * Now set up the timer for real.
781 setup_APIC_timer(calibration_result
);
786 void __cpuinit
setup_secondary_APIC_clock(void)
788 local_irq_disable(); /* FIXME: Do we need this? --RR */
789 setup_APIC_timer(calibration_result
);
793 void disable_APIC_timer(void)
795 if (using_apic_timer
) {
798 v
= apic_read(APIC_LVTT
);
800 * When an illegal vector value (0-15) is written to an LVT
801 * entry and delivery mode is Fixed, the APIC may signal an
802 * illegal vector error, with out regard to whether the mask
803 * bit is set or whether an interrupt is actually seen on input.
805 * Boot sequence might call this function when the LVTT has
806 * '0' vector value. So make sure vector field is set to
809 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
810 apic_write(APIC_LVTT
, v
);
814 void enable_APIC_timer(void)
816 int cpu
= smp_processor_id();
818 if (using_apic_timer
&&
819 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
822 v
= apic_read(APIC_LVTT
);
823 apic_write(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
827 void switch_APIC_timer_to_ipi(void *cpumask
)
829 cpumask_t mask
= *(cpumask_t
*)cpumask
;
830 int cpu
= smp_processor_id();
832 if (cpu_isset(cpu
, mask
) &&
833 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
834 disable_APIC_timer();
835 cpu_set(cpu
, timer_interrupt_broadcast_ipi_mask
);
838 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
840 void smp_send_timer_broadcast_ipi(void)
844 cpus_and(mask
, cpu_online_map
, timer_interrupt_broadcast_ipi_mask
);
845 if (!cpus_empty(mask
)) {
846 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
850 void switch_ipi_to_APIC_timer(void *cpumask
)
852 cpumask_t mask
= *(cpumask_t
*)cpumask
;
853 int cpu
= smp_processor_id();
855 if (cpu_isset(cpu
, mask
) &&
856 cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
857 cpu_clear(cpu
, timer_interrupt_broadcast_ipi_mask
);
861 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
863 int setup_profiling_timer(unsigned int multiplier
)
868 void setup_APIC_extened_lvt(unsigned char lvt_off
, unsigned char vector
,
869 unsigned char msg_type
, unsigned char mask
)
871 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
872 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
879 * Local timer interrupt handler. It does both profiling and
880 * process statistics/rescheduling.
882 * We do profiling in every local tick, statistics/rescheduling
883 * happen only every 'profiling multiplier' ticks. The default
884 * multiplier is 1 and it can be changed by writing the new multiplier
885 * value into /proc/profile.
888 void smp_local_timer_interrupt(void)
890 profile_tick(CPU_PROFILING
);
892 update_process_times(user_mode(get_irq_regs()));
894 if (apic_runs_main_timer
> 1 && smp_processor_id() == boot_cpu_id
)
895 main_timer_handler();
897 * We take the 'long' return path, and there every subsystem
898 * grabs the appropriate locks (kernel lock/ irq lock).
900 * We might want to decouple profiling from the 'long path',
901 * and do the profiling totally in assembly.
903 * Currently this isn't too much of an issue (performance wise),
904 * we can take more than 100K local irqs per second on a 100 MHz P5.
909 * Local APIC timer interrupt. This is the most natural way for doing
910 * local interrupts, but local timer interrupts can be emulated by
911 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
913 * [ if a single-CPU system runs an SMP kernel then we call the local
914 * interrupt as well. Thus we cannot inline the local irq ... ]
916 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
918 struct pt_regs
*old_regs
= set_irq_regs(regs
);
921 * the NMI deadlock-detector uses this.
923 add_pda(apic_timer_irqs
, 1);
926 * NOTE! We'd better ACK the irq immediately,
927 * because timer handling can be slow.
931 * update_process_times() expects us to have done irq_enter().
932 * Besides, if we don't timer interrupts ignore the global
933 * interrupt lock, which is the WrongThing (tm) to do.
937 smp_local_timer_interrupt();
939 set_irq_regs(old_regs
);
943 * apic_is_clustered_box() -- Check if we can expect good TSC
945 * Thus far, the major user of this is IBM's Summit2 series:
947 * Clustered boxes may have unsynced TSC problems if they are
948 * multi-chassis. Use available data to take a good guess.
949 * If in doubt, go HPET.
951 __cpuinit
int apic_is_clustered_box(void)
953 int i
, clusters
, zeros
;
955 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
957 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
959 for (i
= 0; i
< NR_CPUS
; i
++) {
960 id
= bios_cpu_apicid
[i
];
961 if (id
!= BAD_APICID
)
962 __set_bit(APIC_CLUSTERID(id
), clustermap
);
965 /* Problem: Partially populated chassis may not have CPUs in some of
966 * the APIC clusters they have been allocated. Only present CPUs have
967 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
968 * clusters are allocated sequentially, count zeros only if they are
973 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
974 if (test_bit(i
, clustermap
)) {
975 clusters
+= 1 + zeros
;
982 * If clusters > 2, then should be multi-chassis.
983 * May have to revisit this when multi-core + hyperthreaded CPUs come
984 * out, but AFAIK this will work even for them.
986 return (clusters
> 2);
990 * This interrupt should _never_ happen with our APIC/SMP architecture
992 asmlinkage
void smp_spurious_interrupt(void)
998 * Check if this really is a spurious interrupt and ACK it
999 * if it is a vectored one. Just in case...
1000 * Spurious interrupts should not be ACKed.
1002 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1003 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1007 static unsigned long last_warning
;
1008 static unsigned long skipped
;
1010 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1011 if (time_before(last_warning
+30*HZ
,jiffies
)) {
1012 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1013 smp_processor_id(), skipped
);
1014 last_warning
= jiffies
;
1024 * This interrupt should never happen with our APIC/SMP architecture
1027 asmlinkage
void smp_error_interrupt(void)
1033 /* First tickle the hardware, only then report what went on. -- REW */
1034 v
= apic_read(APIC_ESR
);
1035 apic_write(APIC_ESR
, 0);
1036 v1
= apic_read(APIC_ESR
);
1038 atomic_inc(&irq_err_count
);
1040 /* Here is what the APIC error bits mean:
1043 2: Send accept error
1044 3: Receive accept error
1046 5: Send illegal vector
1047 6: Received illegal vector
1048 7: Illegal register address
1050 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1051 smp_processor_id(), v
, v1
);
1058 * This initializes the IO-APIC and APIC hardware if this is
1061 int __init
APIC_init_uniprocessor (void)
1064 printk(KERN_INFO
"Apic disabled\n");
1067 if (!cpu_has_apic
) {
1069 printk(KERN_INFO
"Apic disabled by BIOS\n");
1073 verify_local_APIC();
1075 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1076 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1080 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1084 setup_boot_APIC_clock();
1085 check_nmi_watchdog();
1089 static __init
int setup_disableapic(char *str
)
1092 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1095 early_param("disableapic", setup_disableapic
);
1097 /* same as disableapic, for compatibility */
1098 static __init
int setup_nolapic(char *str
)
1100 return setup_disableapic(str
);
1102 early_param("nolapic", setup_nolapic
);
1104 static __init
int setup_noapictimer(char *str
)
1106 if (str
[0] != ' ' && str
[0] != 0)
1108 disable_apic_timer
= 1;
1112 static __init
int setup_apicmaintimer(char *str
)
1114 apic_runs_main_timer
= 1;
1118 __setup("apicmaintimer", setup_apicmaintimer
);
1120 static __init
int setup_noapicmaintimer(char *str
)
1122 apic_runs_main_timer
= -1;
1125 __setup("noapicmaintimer", setup_noapicmaintimer
);
1127 static __init
int setup_apicpmtimer(char *s
)
1129 apic_calibrate_pmtmr
= 1;
1131 return setup_apicmaintimer(NULL
);
1133 __setup("apicpmtimer", setup_apicpmtimer
);
1135 __setup("noapictimer", setup_noapictimer
);