2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/module.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
41 int disable_apic_timer __initdata
;
44 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
45 * IPIs in place of local APIC timers
47 static cpumask_t timer_interrupt_broadcast_ipi_mask
;
49 /* Using APIC to generate smp_local_timer_interrupt? */
50 int using_apic_timer
= 0;
52 static void apic_pm_activate(void);
54 void enable_NMI_through_LVT0 (void * dummy
)
58 v
= APIC_DM_NMI
; /* unmask and set to NMI */
59 apic_write(APIC_LVT0
, v
);
64 unsigned int v
, maxlvt
;
66 v
= apic_read(APIC_LVR
);
67 maxlvt
= GET_APIC_MAXLVT(v
);
71 void clear_local_APIC(void)
76 maxlvt
= get_maxlvt();
79 * Masking an LVT entry on a P6 can trigger a local APIC error
80 * if the vector is zero. Mask LVTERR first to prevent this.
83 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
84 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
87 * Careful: we have to set masks only first to deassert
88 * any level-triggered sources.
90 v
= apic_read(APIC_LVTT
);
91 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
92 v
= apic_read(APIC_LVT0
);
93 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
94 v
= apic_read(APIC_LVT1
);
95 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
97 v
= apic_read(APIC_LVTPC
);
98 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
102 * Clean APIC state for other OSs:
104 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
105 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
106 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
108 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
110 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
111 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
112 apic_write(APIC_ESR
, 0);
116 void __init
connect_bsp_APIC(void)
120 * Do not trust the local APIC being empty at bootup.
124 * PIC mode, enable APIC mode in the IMCR, i.e.
125 * connect BSP's local APIC to INT and NMI lines.
127 apic_printk(APIC_VERBOSE
, "leaving PIC mode, enabling APIC mode.\n");
133 void disconnect_bsp_APIC(int virt_wire_setup
)
137 * Put the board back into PIC mode (has an effect
138 * only on certain older boards). Note that APIC
139 * interrupts, including IPIs, won't work beyond
140 * this point! The only exception are INIT IPIs.
142 apic_printk(APIC_QUIET
, "disabling APIC mode, entering PIC mode.\n");
147 /* Go back to Virtual Wire compatibility mode */
150 /* For the spurious interrupt use vector F, and enable it */
151 value
= apic_read(APIC_SPIV
);
152 value
&= ~APIC_VECTOR_MASK
;
153 value
|= APIC_SPIV_APIC_ENABLED
;
155 apic_write(APIC_SPIV
, value
);
157 if (!virt_wire_setup
) {
158 /* For LVT0 make it edge triggered, active high, external and enabled */
159 value
= apic_read(APIC_LVT0
);
160 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
161 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
162 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
163 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
164 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
165 apic_write(APIC_LVT0
, value
);
169 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
172 /* For LVT1 make it edge triggered, active high, nmi and enabled */
173 value
= apic_read(APIC_LVT1
);
175 APIC_MODE_MASK
| APIC_SEND_PENDING
|
176 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
177 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
178 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
179 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
180 apic_write(APIC_LVT1
, value
);
184 void disable_local_APIC(void)
191 * Disable APIC (implies clearing of registers
194 value
= apic_read(APIC_SPIV
);
195 value
&= ~APIC_SPIV_APIC_ENABLED
;
196 apic_write(APIC_SPIV
, value
);
200 * This is to verify that we're looking at a real local APIC.
201 * Check these against your board if the CPUs aren't getting
202 * started for no apparent reason.
204 int __init
verify_local_APIC(void)
206 unsigned int reg0
, reg1
;
209 * The version register is read-only in a real APIC.
211 reg0
= apic_read(APIC_LVR
);
212 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
213 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
214 reg1
= apic_read(APIC_LVR
);
215 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
218 * The two version reads above should print the same
219 * numbers. If the second one is different, then we
220 * poke at a non-APIC.
226 * Check if the version looks reasonably.
228 reg1
= GET_APIC_VERSION(reg0
);
229 if (reg1
== 0x00 || reg1
== 0xff)
232 if (reg1
< 0x02 || reg1
== 0xff)
236 * The ID register is read/write in a real APIC.
238 reg0
= apic_read(APIC_ID
);
239 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
240 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
241 reg1
= apic_read(APIC_ID
);
242 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
243 apic_write(APIC_ID
, reg0
);
244 if (reg1
!= (reg0
^ APIC_ID_MASK
))
248 * The next two are just to see if we have sane values.
249 * They're only really relevant if we're in Virtual Wire
250 * compatibility mode, but most boxes are anymore.
252 reg0
= apic_read(APIC_LVT0
);
253 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
254 reg1
= apic_read(APIC_LVT1
);
255 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
260 void __init
sync_Arb_IDs(void)
262 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
263 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
264 if (ver
>= 0x14) /* P4 or higher */
270 apic_wait_icr_idle();
272 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
273 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
277 extern void __error_in_apic_c (void);
280 * An initial setup of the virtual wire mode.
282 void __init
init_bsp_APIC(void)
287 * Don't do the setup now if we have a SMP BIOS as the
288 * through-I/O-APIC virtual wire mode might be active.
290 if (smp_found_config
|| !cpu_has_apic
)
293 value
= apic_read(APIC_LVR
);
296 * Do not trust the local APIC being empty at bootup.
303 value
= apic_read(APIC_SPIV
);
304 value
&= ~APIC_VECTOR_MASK
;
305 value
|= APIC_SPIV_APIC_ENABLED
;
306 value
|= APIC_SPIV_FOCUS_DISABLED
;
307 value
|= SPURIOUS_APIC_VECTOR
;
308 apic_write(APIC_SPIV
, value
);
311 * Set up the virtual wire mode.
313 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
315 apic_write(APIC_LVT1
, value
);
318 void __cpuinit
setup_local_APIC (void)
320 unsigned int value
, maxlvt
;
322 value
= apic_read(APIC_LVR
);
324 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
328 * Double-check whether this APIC is really registered.
329 * This is meaningless in clustered apic mode, so we skip it.
331 if (!apic_id_registered())
335 * Intel recommends to set DFR, LDR and TPR before enabling
336 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
337 * document number 292116). So here it goes...
342 * Set Task Priority to 'accept all'. We never change this
345 value
= apic_read(APIC_TASKPRI
);
346 value
&= ~APIC_TPRI_MASK
;
347 apic_write(APIC_TASKPRI
, value
);
350 * Now that we are all set up, enable the APIC
352 value
= apic_read(APIC_SPIV
);
353 value
&= ~APIC_VECTOR_MASK
;
357 value
|= APIC_SPIV_APIC_ENABLED
;
360 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
361 * certain networking cards. If high frequency interrupts are
362 * happening on a particular IOAPIC pin, plus the IOAPIC routing
363 * entry is masked/unmasked at a high rate as well then sooner or
364 * later IOAPIC line gets 'stuck', no more interrupts are received
365 * from the device. If focus CPU is disabled then the hang goes
368 * [ This bug can be reproduced easily with a level-triggered
369 * PCI Ne2000 networking cards and PII/PIII processors, dual
373 * Actually disabling the focus CPU check just makes the hang less
374 * frequent as it makes the interrupt distributon model be more
375 * like LRU than MRU (the short-term load is more even across CPUs).
376 * See also the comment in end_level_ioapic_irq(). --macro
379 /* Enable focus processor (bit==0) */
380 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
382 /* Disable focus processor (bit==1) */
383 value
|= APIC_SPIV_FOCUS_DISABLED
;
386 * Set spurious IRQ vector
388 value
|= SPURIOUS_APIC_VECTOR
;
389 apic_write(APIC_SPIV
, value
);
394 * set up through-local-APIC on the BP's LINT0. This is not
395 * strictly necessary in pure symmetric-IO mode, but sometimes
396 * we delegate interrupts to the 8259A.
399 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
401 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
402 if (!smp_processor_id() && (pic_mode
|| !value
)) {
403 value
= APIC_DM_EXTINT
;
404 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
406 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
407 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
409 apic_write(APIC_LVT0
, value
);
412 * only the BP should see the LINT1 NMI signal, obviously.
414 if (!smp_processor_id())
417 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
418 apic_write(APIC_LVT1
, value
);
422 maxlvt
= get_maxlvt();
423 oldvalue
= apic_read(APIC_ESR
);
424 value
= ERROR_APIC_VECTOR
; // enables sending errors
425 apic_write(APIC_LVTERR
, value
);
427 * spec says clear errors after enabling vector.
430 apic_write(APIC_ESR
, 0);
431 value
= apic_read(APIC_ESR
);
432 if (value
!= oldvalue
)
433 apic_printk(APIC_VERBOSE
,
434 "ESR value after enabling vector: %08x, after %08x\n",
438 nmi_watchdog_default();
439 if (nmi_watchdog
== NMI_LOCAL_APIC
)
440 setup_apic_nmi_watchdog();
447 /* 'active' is true if the local APIC was enabled by us and
448 not the BIOS; this signifies that we are also responsible
449 for disabling it before entering apm/acpi suspend */
451 /* r/w apic fields */
452 unsigned int apic_id
;
453 unsigned int apic_taskpri
;
454 unsigned int apic_ldr
;
455 unsigned int apic_dfr
;
456 unsigned int apic_spiv
;
457 unsigned int apic_lvtt
;
458 unsigned int apic_lvtpc
;
459 unsigned int apic_lvt0
;
460 unsigned int apic_lvt1
;
461 unsigned int apic_lvterr
;
462 unsigned int apic_tmict
;
463 unsigned int apic_tdcr
;
464 unsigned int apic_thmr
;
467 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
471 if (!apic_pm_state
.active
)
474 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
475 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
476 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
477 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
478 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
479 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
480 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
481 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
482 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
483 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
484 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
485 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
486 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
487 local_save_flags(flags
);
489 disable_local_APIC();
490 local_irq_restore(flags
);
494 static int lapic_resume(struct sys_device
*dev
)
499 if (!apic_pm_state
.active
)
502 /* XXX: Pavel needs this for S3 resume, but can't explain why */
503 set_fixmap_nocache(FIX_APIC_BASE
, APIC_DEFAULT_PHYS_BASE
);
505 local_irq_save(flags
);
506 rdmsr(MSR_IA32_APICBASE
, l
, h
);
507 l
&= ~MSR_IA32_APICBASE_BASE
;
508 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
509 wrmsr(MSR_IA32_APICBASE
, l
, h
);
510 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
511 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
512 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
513 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
514 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
515 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
516 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
517 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
518 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
519 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
520 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
521 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
522 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
523 apic_write(APIC_ESR
, 0);
525 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
526 apic_write(APIC_ESR
, 0);
528 local_irq_restore(flags
);
532 static struct sysdev_class lapic_sysclass
= {
533 set_kset_name("lapic"),
534 .resume
= lapic_resume
,
535 .suspend
= lapic_suspend
,
538 static struct sys_device device_lapic
= {
540 .cls
= &lapic_sysclass
,
543 static void __cpuinit
apic_pm_activate(void)
545 apic_pm_state
.active
= 1;
548 static int __init
init_lapic_sysfs(void)
553 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
554 error
= sysdev_class_register(&lapic_sysclass
);
556 error
= sysdev_register(&device_lapic
);
559 device_initcall(init_lapic_sysfs
);
561 #else /* CONFIG_PM */
563 static void apic_pm_activate(void) { }
565 #endif /* CONFIG_PM */
567 static int __init
apic_set_verbosity(char *str
)
569 if (strcmp("debug", str
) == 0)
570 apic_verbosity
= APIC_DEBUG
;
571 else if (strcmp("verbose", str
) == 0)
572 apic_verbosity
= APIC_VERBOSE
;
574 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
575 " use apic=verbose or apic=debug", str
);
580 __setup("apic=", apic_set_verbosity
);
583 * Detect and enable local APICs on non-SMP boards.
584 * Original code written by Keir Fraser.
585 * On AMD64 we trust the BIOS - if it says no APIC it is likely
586 * not correctly set up (usually the APIC timer won't work etc.)
589 static int __init
detect_init_APIC (void)
592 printk(KERN_INFO
"No local APIC present\n");
596 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
601 void __init
init_apic_mappings(void)
603 unsigned long apic_phys
;
606 * If no local APIC can be found then set up a fake all
607 * zeroes page to simulate the local APIC and another
608 * one for the IO-APIC.
610 if (!smp_found_config
&& detect_init_APIC()) {
611 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
612 apic_phys
= __pa(apic_phys
);
614 apic_phys
= mp_lapic_addr
;
616 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
617 apic_printk(APIC_VERBOSE
,"mapped APIC to %16lx (%16lx)\n", APIC_BASE
, apic_phys
);
620 * Fetch the APIC ID of the BSP in case we have a
621 * default configuration (or the MP table is broken).
623 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
625 #ifdef CONFIG_X86_IO_APIC
627 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
630 for (i
= 0; i
< nr_ioapics
; i
++) {
631 if (smp_found_config
) {
632 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
634 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
635 ioapic_phys
= __pa(ioapic_phys
);
637 set_fixmap_nocache(idx
, ioapic_phys
);
638 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
639 __fix_to_virt(idx
), ioapic_phys
);
647 * This function sets up the local APIC timer, with a timeout of
648 * 'clocks' APIC bus clock. During calibration we actually call
649 * this function twice on the boot CPU, once with a bogus timeout
650 * value, second time for real. The other (noncalibrating) CPUs
651 * call this function only once, with the real, calibrated value.
653 * We do reads before writes even if unnecessary, to get around the
654 * P5 APIC double write bug.
657 #define APIC_DIVISOR 16
659 static void __setup_APIC_LVTT(unsigned int clocks
)
661 unsigned int lvtt_value
, tmp_value
, ver
;
662 int cpu
= smp_processor_id();
664 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
665 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
667 if (cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
))
668 lvtt_value
|= APIC_LVT_MASKED
;
670 apic_write(APIC_LVTT
, lvtt_value
);
675 tmp_value
= apic_read(APIC_TDCR
);
676 apic_write(APIC_TDCR
, (tmp_value
677 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
680 apic_write(APIC_TMICT
, clocks
/APIC_DIVISOR
);
683 static void setup_APIC_timer(unsigned int clocks
)
687 local_irq_save(flags
);
689 /* wait for irq slice */
690 if (vxtime
.hpet_address
) {
691 int trigger
= hpet_readl(HPET_T0_CMP
);
692 while (hpet_readl(HPET_COUNTER
) >= trigger
)
694 while (hpet_readl(HPET_COUNTER
) < trigger
)
700 c2
|= inb_p(0x40) << 8;
705 c2
|= inb_p(0x40) << 8;
706 } while (c2
- c1
< 300);
709 __setup_APIC_LVTT(clocks
);
711 local_irq_restore(flags
);
715 * In this function we calibrate APIC bus clocks to the external
716 * timer. Unfortunately we cannot use jiffies and the timer irq
717 * to calibrate, since some later bootup code depends on getting
718 * the first irq? Ugh.
720 * We want to do the calibration only once since we
721 * want to have local timer irqs syncron. CPUs connected
722 * by the same APIC bus have the very same bus frequency.
723 * And we want to have irqs off anyways, no accidental
727 #define TICK_COUNT 100000000
729 static int __init
calibrate_APIC_clock(void)
731 int apic
, apic_start
, tsc
, tsc_start
;
734 * Put whatever arbitrary (but long enough) timeout
735 * value into the APIC clock, we just want to get the
736 * counter running for calibration.
738 __setup_APIC_LVTT(1000000000);
740 apic_start
= apic_read(APIC_TMCCT
);
744 apic
= apic_read(APIC_TMCCT
);
746 } while ((tsc
- tsc_start
) < TICK_COUNT
&& (apic
- apic_start
) < TICK_COUNT
);
748 result
= (apic_start
- apic
) * 1000L * cpu_khz
/ (tsc
- tsc_start
);
750 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
751 result
/ 1000 / 1000, result
/ 1000 % 1000);
753 return result
* APIC_DIVISOR
/ HZ
;
756 static unsigned int calibration_result
;
758 void __init
setup_boot_APIC_clock (void)
760 if (disable_apic_timer
) {
761 printk(KERN_INFO
"Disabling APIC timer\n");
765 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
766 using_apic_timer
= 1;
770 calibration_result
= calibrate_APIC_clock();
772 * Now set up the timer for real.
774 setup_APIC_timer(calibration_result
);
779 void __cpuinit
setup_secondary_APIC_clock(void)
781 local_irq_disable(); /* FIXME: Do we need this? --RR */
782 setup_APIC_timer(calibration_result
);
786 void disable_APIC_timer(void)
788 if (using_apic_timer
) {
791 v
= apic_read(APIC_LVTT
);
792 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
796 void enable_APIC_timer(void)
798 int cpu
= smp_processor_id();
800 if (using_apic_timer
&&
801 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
804 v
= apic_read(APIC_LVTT
);
805 apic_write(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
809 void switch_APIC_timer_to_ipi(void *cpumask
)
811 cpumask_t mask
= *(cpumask_t
*)cpumask
;
812 int cpu
= smp_processor_id();
814 if (cpu_isset(cpu
, mask
) &&
815 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
816 disable_APIC_timer();
817 cpu_set(cpu
, timer_interrupt_broadcast_ipi_mask
);
820 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
822 void smp_send_timer_broadcast_ipi(void)
826 cpus_and(mask
, cpu_online_map
, timer_interrupt_broadcast_ipi_mask
);
827 if (!cpus_empty(mask
)) {
828 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
832 void switch_ipi_to_APIC_timer(void *cpumask
)
834 cpumask_t mask
= *(cpumask_t
*)cpumask
;
835 int cpu
= smp_processor_id();
837 if (cpu_isset(cpu
, mask
) &&
838 cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
839 cpu_clear(cpu
, timer_interrupt_broadcast_ipi_mask
);
843 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
845 int setup_profiling_timer(unsigned int multiplier
)
850 #ifdef CONFIG_X86_MCE_AMD
851 void setup_threshold_lvt(unsigned long lvt_off
)
854 unsigned long reg
= (lvt_off
<< 4) + 0x500;
855 v
|= THRESHOLD_APIC_VECTOR
;
858 #endif /* CONFIG_X86_MCE_AMD */
863 * Local timer interrupt handler. It does both profiling and
864 * process statistics/rescheduling.
866 * We do profiling in every local tick, statistics/rescheduling
867 * happen only every 'profiling multiplier' ticks. The default
868 * multiplier is 1 and it can be changed by writing the new multiplier
869 * value into /proc/profile.
872 void smp_local_timer_interrupt(struct pt_regs
*regs
)
874 profile_tick(CPU_PROFILING
, regs
);
876 update_process_times(user_mode(regs
));
879 * We take the 'long' return path, and there every subsystem
880 * grabs the appropriate locks (kernel lock/ irq lock).
882 * we might want to decouple profiling from the 'long path',
883 * and do the profiling totally in assembly.
885 * Currently this isn't too much of an issue (performance wise),
886 * we can take more than 100K local irqs per second on a 100 MHz P5.
891 * Local APIC timer interrupt. This is the most natural way for doing
892 * local interrupts, but local timer interrupts can be emulated by
893 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
895 * [ if a single-CPU system runs an SMP kernel then we call the local
896 * interrupt as well. Thus we cannot inline the local irq ... ]
898 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
901 * the NMI deadlock-detector uses this.
903 add_pda(apic_timer_irqs
, 1);
906 * NOTE! We'd better ACK the irq immediately,
907 * because timer handling can be slow.
911 * update_process_times() expects us to have done irq_enter().
912 * Besides, if we don't timer interrupts ignore the global
913 * interrupt lock, which is the WrongThing (tm) to do.
917 smp_local_timer_interrupt(regs
);
922 * oem_force_hpet_timer -- force HPET mode for some boxes.
924 * Thus far, the major user of this is IBM's Summit2 series:
926 * Clustered boxes may have unsynced TSC problems if they are
927 * multi-chassis. Use available data to take a good guess.
928 * If in doubt, go HPET.
930 __init
int oem_force_hpet_timer(void)
932 int i
, clusters
, zeros
;
934 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
936 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
938 for (i
= 0; i
< NR_CPUS
; i
++) {
939 id
= bios_cpu_apicid
[i
];
940 if (id
!= BAD_APICID
)
941 __set_bit(APIC_CLUSTERID(id
), clustermap
);
944 /* Problem: Partially populated chassis may not have CPUs in some of
945 * the APIC clusters they have been allocated. Only present CPUs have
946 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
947 * clusters are allocated sequentially, count zeros only if they are
952 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
953 if (test_bit(i
, clustermap
)) {
954 clusters
+= 1 + zeros
;
961 * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
962 * Else return 0 to use TSC.
963 * May have to revisit this when multi-core + hyperthreaded CPUs come
964 * out, but AFAIK this will work even for them.
966 return (clusters
> 2);
970 * This interrupt should _never_ happen with our APIC/SMP architecture
972 asmlinkage
void smp_spurious_interrupt(void)
978 * Check if this really is a spurious interrupt and ACK it
979 * if it is a vectored one. Just in case...
980 * Spurious interrupts should not be ACKed.
982 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
983 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
987 static unsigned long last_warning
;
988 static unsigned long skipped
;
990 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
991 if (time_before(last_warning
+30*HZ
,jiffies
)) {
992 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, %ld skipped.\n",
993 smp_processor_id(), skipped
);
994 last_warning
= jiffies
;
1004 * This interrupt should never happen with our APIC/SMP architecture
1007 asmlinkage
void smp_error_interrupt(void)
1013 /* First tickle the hardware, only then report what went on. -- REW */
1014 v
= apic_read(APIC_ESR
);
1015 apic_write(APIC_ESR
, 0);
1016 v1
= apic_read(APIC_ESR
);
1018 atomic_inc(&irq_err_count
);
1020 /* Here is what the APIC error bits mean:
1023 2: Send accept error
1024 3: Receive accept error
1026 5: Send illegal vector
1027 6: Received illegal vector
1028 7: Illegal register address
1030 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1031 smp_processor_id(), v
, v1
);
1038 * This initializes the IO-APIC and APIC hardware if this is
1041 int __init
APIC_init_uniprocessor (void)
1044 printk(KERN_INFO
"Apic disabled\n");
1047 if (!cpu_has_apic
) {
1049 printk(KERN_INFO
"Apic disabled by BIOS\n");
1053 verify_local_APIC();
1057 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1058 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1062 #ifdef CONFIG_X86_IO_APIC
1063 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1068 setup_boot_APIC_clock();
1069 check_nmi_watchdog();
1073 static __init
int setup_disableapic(char *str
)
1079 static __init
int setup_nolapic(char *str
)
1085 static __init
int setup_noapictimer(char *str
)
1087 disable_apic_timer
= 1;
1091 /* dummy parsing: see setup.c */
1093 __setup("disableapic", setup_disableapic
);
1094 __setup("nolapic", setup_nolapic
); /* same as disableapic, for compatibility */
1096 __setup("noapictimer", setup_noapictimer
);
1098 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */