2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
34 #include <acpi/acpi_bus.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
46 #define __apicdebuginit __init
48 int sis_apic_bug
; /* not actually supported, dummy for compile */
50 static int no_timer_check
;
52 int disable_timer_pin_1 __initdata
;
54 int timer_over_8254 __initdata
= 0;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
59 static DEFINE_SPINLOCK(ioapic_lock
);
60 static DEFINE_SPINLOCK(vector_lock
);
63 * # of IRQ routing registers
65 int nr_ioapic_registers
[MAX_IO_APICS
];
68 * Rough estimation of how many shared IRQs there are, can
71 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
72 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75 * This is performance-critical, we want to do it O(1)
77 * the indexing order of this array favors 1:1 mappings
78 * between pins and IRQs.
81 static struct irq_pin_list
{
82 short apic
, pin
, next
;
83 } irq_2_pin
[PIN_MAP_SIZE
];
85 int vector_irq
[NR_VECTORS
] __read_mostly
= { [0 ... NR_VECTORS
- 1] = -1};
87 #define vector_to_irq(vector) \
88 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #define vector_to_irq(vector) (vector)
93 #define __DO_ACTION(R, ACTION, FINAL) \
97 struct irq_pin_list *entry = irq_2_pin + irq; \
99 BUG_ON(irq >= NR_IRQS); \
105 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
107 io_apic_modify(entry->apic, reg); \
110 entry = irq_2_pin + entry->next; \
116 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
122 cpus_and(tmp
, mask
, cpu_online_map
);
126 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
128 dest
= cpu_mask_to_apicid(mask
);
131 * Only the high 8 bits are valid.
133 dest
= SET_APIC_LOGICAL_ID(dest
);
135 spin_lock_irqsave(&ioapic_lock
, flags
);
136 __DO_ACTION(1, = dest
, )
137 set_irq_info(irq
, mask
);
138 spin_unlock_irqrestore(&ioapic_lock
, flags
);
142 static u8 gsi_2_irq
[NR_IRQ_VECTORS
] = { [0 ... NR_IRQ_VECTORS
-1] = 0xFF };
145 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
146 * shared ISA-space IRQs, so we have to support them. We are super
147 * fast in the common case, and fast for shared ISA-space IRQs.
149 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
151 static int first_free_entry
= NR_IRQS
;
152 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
154 BUG_ON(irq
>= NR_IRQS
);
156 entry
= irq_2_pin
+ entry
->next
;
158 if (entry
->pin
!= -1) {
159 entry
->next
= first_free_entry
;
160 entry
= irq_2_pin
+ entry
->next
;
161 if (++first_free_entry
>= PIN_MAP_SIZE
)
162 panic("io_apic.c: ran out of irq_2_pin entries!");
169 #define DO_ACTION(name,R,ACTION, FINAL) \
171 static void name##_IO_APIC_irq (unsigned int irq) \
172 __DO_ACTION(R, ACTION, FINAL)
174 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
176 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
179 static void mask_IO_APIC_irq (unsigned int irq
)
183 spin_lock_irqsave(&ioapic_lock
, flags
);
184 __mask_IO_APIC_irq(irq
);
185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
188 static void unmask_IO_APIC_irq (unsigned int irq
)
192 spin_lock_irqsave(&ioapic_lock
, flags
);
193 __unmask_IO_APIC_irq(irq
);
194 spin_unlock_irqrestore(&ioapic_lock
, flags
);
197 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
199 struct IO_APIC_route_entry entry
;
202 /* Check delivery_mode to be sure we're not clearing an SMI pin */
203 spin_lock_irqsave(&ioapic_lock
, flags
);
204 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
205 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
206 spin_unlock_irqrestore(&ioapic_lock
, flags
);
207 if (entry
.delivery_mode
== dest_SMI
)
210 * Disable it in the IO-APIC irq-routing table:
212 memset(&entry
, 0, sizeof(entry
));
214 spin_lock_irqsave(&ioapic_lock
, flags
);
215 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
216 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
217 spin_unlock_irqrestore(&ioapic_lock
, flags
);
220 static void clear_IO_APIC (void)
224 for (apic
= 0; apic
< nr_ioapics
; apic
++)
225 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
226 clear_IO_APIC_pin(apic
, pin
);
230 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
231 * specific CPU-side IRQs.
235 static int pirq_entries
[MAX_PIRQS
];
236 static int pirqs_enabled
;
237 int skip_ioapic_setup
;
240 /* dummy parsing: see setup.c */
242 static int __init
disable_ioapic_setup(char *str
)
244 skip_ioapic_setup
= 1;
248 static int __init
enable_ioapic_setup(char *str
)
251 skip_ioapic_setup
= 0;
255 __setup("noapic", disable_ioapic_setup
);
256 __setup("apic", enable_ioapic_setup
);
258 static int __init
setup_disable_8254_timer(char *s
)
260 timer_over_8254
= -1;
263 static int __init
setup_enable_8254_timer(char *s
)
269 __setup("disable_8254_timer", setup_disable_8254_timer
);
270 __setup("enable_8254_timer", setup_enable_8254_timer
);
272 #include <asm/pci-direct.h>
273 #include <linux/pci_ids.h>
274 #include <linux/pci.h>
279 static int nvidia_hpet_detected __initdata
;
281 static int __init
nvidia_hpet_check(unsigned long phys
, unsigned long size
)
283 nvidia_hpet_detected
= 1;
288 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
289 off. Check for an Nvidia or VIA PCI bridge and turn it off.
290 Use pci direct infrastructure because this runs before the PCI subsystem.
292 Can be overwritten with "apic"
294 And another hack to disable the IOMMU on VIA chipsets.
296 ... and others. Really should move this somewhere else.
299 void __init
check_ioapic(void)
302 /* Poor man's PCI discovery */
303 for (num
= 0; num
< 32; num
++) {
304 for (slot
= 0; slot
< 32; slot
++) {
305 for (func
= 0; func
< 8; func
++) {
309 class = read_pci_config(num
,slot
,func
,
311 if (class == 0xffffffff)
314 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI
)
317 vendor
= read_pci_config(num
, slot
, func
,
321 case PCI_VENDOR_ID_VIA
:
322 #ifdef CONFIG_GART_IOMMU
323 if ((end_pfn
> MAX_DMA32_PFN
||
325 !iommu_aperture_allowed
) {
327 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
328 iommu_aperture_disabled
= 1;
332 case PCI_VENDOR_ID_NVIDIA
:
335 * All timer overrides on Nvidia are
336 * wrong unless HPET is enabled.
338 nvidia_hpet_detected
= 0;
339 acpi_table_parse(ACPI_HPET
,
341 if (nvidia_hpet_detected
== 0) {
342 acpi_skip_timer_override
= 1;
343 printk(KERN_INFO
"Nvidia board "
344 "detected. Ignoring ACPI "
345 "timer override.\n");
348 /* RED-PEN skip them on mptables too? */
351 /* This should be actually default, but
352 for 2.6.16 let's do it for ATI only where
353 it's really needed. */
354 case PCI_VENDOR_ID_ATI
:
355 if (timer_over_8254
== 1) {
358 "ATI board detected. Disabling timer routing over 8254.\n");
364 /* No multi-function device? */
365 type
= read_pci_config_byte(num
,slot
,func
,
374 static int __init
ioapic_pirq_setup(char *str
)
377 int ints
[MAX_PIRQS
+1];
379 get_options(str
, ARRAY_SIZE(ints
), ints
);
381 for (i
= 0; i
< MAX_PIRQS
; i
++)
382 pirq_entries
[i
] = -1;
385 apic_printk(APIC_VERBOSE
, "PIRQ redirection, working around broken MP-BIOS.\n");
387 if (ints
[0] < MAX_PIRQS
)
390 for (i
= 0; i
< max
; i
++) {
391 apic_printk(APIC_VERBOSE
, "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
393 * PIRQs are mapped upside down, usually.
395 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
400 __setup("pirq=", ioapic_pirq_setup
);
403 * Find the IRQ entry number of a certain pin.
405 static int find_irq_entry(int apic
, int pin
, int type
)
409 for (i
= 0; i
< mp_irq_entries
; i
++)
410 if (mp_irqs
[i
].mpc_irqtype
== type
&&
411 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
412 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
413 mp_irqs
[i
].mpc_dstirq
== pin
)
420 * Find the pin to which IRQ[irq] (ISA) is connected
422 static int __init
find_isa_irq_pin(int irq
, int type
)
426 for (i
= 0; i
< mp_irq_entries
; i
++) {
427 int lbus
= mp_irqs
[i
].mpc_srcbus
;
429 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
430 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
431 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
432 (mp_irqs
[i
].mpc_irqtype
== type
) &&
433 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
435 return mp_irqs
[i
].mpc_dstirq
;
440 static int __init
find_isa_irq_apic(int irq
, int type
)
444 for (i
= 0; i
< mp_irq_entries
; i
++) {
445 int lbus
= mp_irqs
[i
].mpc_srcbus
;
447 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
448 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
449 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
450 (mp_irqs
[i
].mpc_irqtype
== type
) &&
451 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
454 if (i
< mp_irq_entries
) {
456 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
457 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
466 * Find a specific PCI IRQ entry.
467 * Not an __init, possibly needed by modules
469 static int pin_2_irq(int idx
, int apic
, int pin
);
471 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
473 int apic
, i
, best_guess
= -1;
475 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
477 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
478 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
481 for (i
= 0; i
< mp_irq_entries
; i
++) {
482 int lbus
= mp_irqs
[i
].mpc_srcbus
;
484 for (apic
= 0; apic
< nr_ioapics
; apic
++)
485 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
486 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
489 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
490 !mp_irqs
[i
].mpc_irqtype
&&
492 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
493 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
495 if (!(apic
|| IO_APIC_IRQ(irq
)))
498 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
501 * Use the first all-but-pin matching entry as a
502 * best-guess fuzzy result for broken mptables.
508 BUG_ON(best_guess
>= NR_IRQS
);
513 * EISA Edge/Level control register, ELCR
515 static int EISA_ELCR(unsigned int irq
)
518 unsigned int port
= 0x4d0 + (irq
>> 3);
519 return (inb(port
) >> (irq
& 7)) & 1;
521 apic_printk(APIC_VERBOSE
, "Broken MPtable reports ISA irq %d\n", irq
);
525 /* EISA interrupts are always polarity zero and can be edge or level
526 * trigger depending on the ELCR value. If an interrupt is listed as
527 * EISA conforming in the MP table, that means its trigger type must
528 * be read in from the ELCR */
530 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
531 #define default_EISA_polarity(idx) (0)
533 /* ISA interrupts are always polarity zero edge triggered,
534 * when listed as conforming in the MP table. */
536 #define default_ISA_trigger(idx) (0)
537 #define default_ISA_polarity(idx) (0)
539 /* PCI interrupts are always polarity one level triggered,
540 * when listed as conforming in the MP table. */
542 #define default_PCI_trigger(idx) (1)
543 #define default_PCI_polarity(idx) (1)
545 /* MCA interrupts are always polarity zero level triggered,
546 * when listed as conforming in the MP table. */
548 #define default_MCA_trigger(idx) (1)
549 #define default_MCA_polarity(idx) (0)
551 static int __init
MPBIOS_polarity(int idx
)
553 int bus
= mp_irqs
[idx
].mpc_srcbus
;
557 * Determine IRQ line polarity (high active or low active):
559 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
561 case 0: /* conforms, ie. bus-type dependent polarity */
563 switch (mp_bus_id_to_type
[bus
])
565 case MP_BUS_ISA
: /* ISA pin */
567 polarity
= default_ISA_polarity(idx
);
570 case MP_BUS_EISA
: /* EISA pin */
572 polarity
= default_EISA_polarity(idx
);
575 case MP_BUS_PCI
: /* PCI pin */
577 polarity
= default_PCI_polarity(idx
);
580 case MP_BUS_MCA
: /* MCA pin */
582 polarity
= default_MCA_polarity(idx
);
587 printk(KERN_WARNING
"broken BIOS!!\n");
594 case 1: /* high active */
599 case 2: /* reserved */
601 printk(KERN_WARNING
"broken BIOS!!\n");
605 case 3: /* low active */
610 default: /* invalid */
612 printk(KERN_WARNING
"broken BIOS!!\n");
620 static int MPBIOS_trigger(int idx
)
622 int bus
= mp_irqs
[idx
].mpc_srcbus
;
626 * Determine IRQ trigger mode (edge or level sensitive):
628 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
630 case 0: /* conforms, ie. bus-type dependent */
632 switch (mp_bus_id_to_type
[bus
])
634 case MP_BUS_ISA
: /* ISA pin */
636 trigger
= default_ISA_trigger(idx
);
639 case MP_BUS_EISA
: /* EISA pin */
641 trigger
= default_EISA_trigger(idx
);
644 case MP_BUS_PCI
: /* PCI pin */
646 trigger
= default_PCI_trigger(idx
);
649 case MP_BUS_MCA
: /* MCA pin */
651 trigger
= default_MCA_trigger(idx
);
656 printk(KERN_WARNING
"broken BIOS!!\n");
668 case 2: /* reserved */
670 printk(KERN_WARNING
"broken BIOS!!\n");
679 default: /* invalid */
681 printk(KERN_WARNING
"broken BIOS!!\n");
689 static inline int irq_polarity(int idx
)
691 return MPBIOS_polarity(idx
);
694 static inline int irq_trigger(int idx
)
696 return MPBIOS_trigger(idx
);
699 static int next_irq
= 16;
702 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
703 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
704 * from ACPI, which can reach 800 in large boxen.
706 * Compact the sparse GSI space into a sequential IRQ series and reuse
707 * vectors if possible.
709 int gsi_irq_sharing(int gsi
)
711 int i
, tries
, vector
;
713 BUG_ON(gsi
>= NR_IRQ_VECTORS
);
715 if (platform_legacy_irq(gsi
))
718 if (gsi_2_irq
[gsi
] != 0xFF)
719 return (int)gsi_2_irq
[gsi
];
723 vector
= assign_irq_vector(gsi
);
726 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
727 * use of vector and if found, return that IRQ. However, we never want
728 * to share legacy IRQs, which usually have a different trigger mode
731 for (i
= 0; i
< NR_IRQS
; i
++)
732 if (IO_APIC_VECTOR(i
) == vector
)
734 if (platform_legacy_irq(i
)) {
736 IO_APIC_VECTOR(i
) = 0;
739 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector
, gsi
);
743 printk(KERN_INFO
"GSI %d sharing vector 0x%02X and IRQ %d\n",
749 BUG_ON(i
>= NR_IRQS
);
751 IO_APIC_VECTOR(i
) = vector
;
752 printk(KERN_INFO
"GSI %d assigned vector 0x%02X and IRQ %d\n",
757 static int pin_2_irq(int idx
, int apic
, int pin
)
760 int bus
= mp_irqs
[idx
].mpc_srcbus
;
763 * Debugging check, we are in big trouble if this message pops up!
765 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
766 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
768 switch (mp_bus_id_to_type
[bus
])
770 case MP_BUS_ISA
: /* ISA pin */
774 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
777 case MP_BUS_PCI
: /* PCI pin */
780 * PCI IRQs are mapped in order
784 irq
+= nr_ioapic_registers
[i
++];
786 irq
= gsi_irq_sharing(irq
);
791 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
796 BUG_ON(irq
>= NR_IRQS
);
799 * PCI IRQ command line redirection. Yes, limits are hardcoded.
801 if ((pin
>= 16) && (pin
<= 23)) {
802 if (pirq_entries
[pin
-16] != -1) {
803 if (!pirq_entries
[pin
-16]) {
804 apic_printk(APIC_VERBOSE
, "disabling PIRQ%d\n", pin
-16);
806 irq
= pirq_entries
[pin
-16];
807 apic_printk(APIC_VERBOSE
, "using PIRQ%d -> IRQ %d\n",
812 BUG_ON(irq
>= NR_IRQS
);
816 static inline int IO_APIC_irq_trigger(int irq
)
820 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
821 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
822 idx
= find_irq_entry(apic
,pin
,mp_INT
);
823 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
824 return irq_trigger(idx
);
828 * nonexistent IRQs are edge default
833 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
834 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
836 int assign_irq_vector(int irq
)
838 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
841 BUG_ON(irq
!= AUTO_ASSIGN
&& (unsigned)irq
>= NR_IRQ_VECTORS
);
843 spin_lock(&vector_lock
);
845 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0) {
846 spin_unlock(&vector_lock
);
847 return IO_APIC_VECTOR(irq
);
851 if (current_vector
== IA32_SYSCALL_VECTOR
)
854 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
855 /* If we run out of vectors on large boxen, must share them. */
856 offset
= (offset
+ 1) % 8;
857 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
860 vector
= current_vector
;
861 vector_irq
[vector
] = irq
;
862 if (irq
!= AUTO_ASSIGN
)
863 IO_APIC_VECTOR(irq
) = vector
;
865 spin_unlock(&vector_lock
);
870 extern void (*interrupt
[NR_IRQS
])(void);
871 static struct hw_interrupt_type ioapic_level_type
;
872 static struct hw_interrupt_type ioapic_edge_type
;
874 #define IOAPIC_AUTO -1
875 #define IOAPIC_EDGE 0
876 #define IOAPIC_LEVEL 1
878 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
880 unsigned idx
= use_pci_vector() && !platform_legacy_irq(irq
) ? vector
: irq
;
882 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
883 trigger
== IOAPIC_LEVEL
)
884 irq_desc
[idx
].handler
= &ioapic_level_type
;
886 irq_desc
[idx
].handler
= &ioapic_edge_type
;
887 set_intr_gate(vector
, interrupt
[idx
]);
890 static void __init
setup_IO_APIC_irqs(void)
892 struct IO_APIC_route_entry entry
;
893 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
896 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
898 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
899 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
902 * add it to the IO-APIC irq-routing table:
904 memset(&entry
,0,sizeof(entry
));
906 entry
.delivery_mode
= INT_DELIVERY_MODE
;
907 entry
.dest_mode
= INT_DEST_MODE
;
908 entry
.mask
= 0; /* enable IRQ */
909 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
911 idx
= find_irq_entry(apic
,pin
,mp_INT
);
914 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
917 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
921 entry
.trigger
= irq_trigger(idx
);
922 entry
.polarity
= irq_polarity(idx
);
924 if (irq_trigger(idx
)) {
927 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
930 irq
= pin_2_irq(idx
, apic
, pin
);
931 add_pin_to_irq(irq
, apic
, pin
);
933 if (!apic
&& !IO_APIC_IRQ(irq
))
936 if (IO_APIC_IRQ(irq
)) {
937 vector
= assign_irq_vector(irq
);
938 entry
.vector
= vector
;
940 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
941 if (!apic
&& (irq
< 16))
942 disable_8259A_irq(irq
);
944 spin_lock_irqsave(&ioapic_lock
, flags
);
945 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
946 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
947 set_native_irq_info(irq
, TARGET_CPUS
);
948 spin_unlock_irqrestore(&ioapic_lock
, flags
);
953 apic_printk(APIC_VERBOSE
," not connected.\n");
957 * Set up the 8259A-master output pin as broadcast to all
960 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
962 struct IO_APIC_route_entry entry
;
965 memset(&entry
,0,sizeof(entry
));
967 disable_8259A_irq(0);
970 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
973 * We use logical delivery to get the timer IRQ
976 entry
.dest_mode
= INT_DEST_MODE
;
977 entry
.mask
= 0; /* unmask IRQ now */
978 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
979 entry
.delivery_mode
= INT_DELIVERY_MODE
;
982 entry
.vector
= vector
;
985 * The timer IRQ doesn't have to know that behind the
986 * scene we have a 8259A-master in AEOI mode ...
988 irq_desc
[0].handler
= &ioapic_edge_type
;
991 * Add it to the IO-APIC irq-routing table:
993 spin_lock_irqsave(&ioapic_lock
, flags
);
994 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
995 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
996 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1001 void __init
UNEXPECTED_IO_APIC(void)
1005 void __apicdebuginit
print_IO_APIC(void)
1008 union IO_APIC_reg_00 reg_00
;
1009 union IO_APIC_reg_01 reg_01
;
1010 union IO_APIC_reg_02 reg_02
;
1011 unsigned long flags
;
1013 if (apic_verbosity
== APIC_QUIET
)
1016 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1017 for (i
= 0; i
< nr_ioapics
; i
++)
1018 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1019 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1022 * We are a bit conservative about what we expect. We have to
1023 * know about every hardware change ASAP.
1025 printk(KERN_INFO
"testing the IO APIC.......................\n");
1027 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1029 spin_lock_irqsave(&ioapic_lock
, flags
);
1030 reg_00
.raw
= io_apic_read(apic
, 0);
1031 reg_01
.raw
= io_apic_read(apic
, 1);
1032 if (reg_01
.bits
.version
>= 0x10)
1033 reg_02
.raw
= io_apic_read(apic
, 2);
1034 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1037 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1038 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1039 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1040 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1041 UNEXPECTED_IO_APIC();
1043 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1044 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1045 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1046 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1047 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1048 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1049 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1050 (reg_01
.bits
.entries
!= 0x2E) &&
1051 (reg_01
.bits
.entries
!= 0x3F) &&
1052 (reg_01
.bits
.entries
!= 0x03)
1054 UNEXPECTED_IO_APIC();
1056 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1057 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1058 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1059 (reg_01
.bits
.version
!= 0x02) && /* 82801BA IO-APICs (ICH2) */
1060 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1061 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1062 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1063 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1065 UNEXPECTED_IO_APIC();
1066 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1067 UNEXPECTED_IO_APIC();
1069 if (reg_01
.bits
.version
>= 0x10) {
1070 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1071 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1072 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1073 UNEXPECTED_IO_APIC();
1076 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1078 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1079 " Stat Dest Deli Vect: \n");
1081 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1082 struct IO_APIC_route_entry entry
;
1084 spin_lock_irqsave(&ioapic_lock
, flags
);
1085 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1086 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1087 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1089 printk(KERN_DEBUG
" %02x %03X %02X ",
1091 entry
.dest
.logical
.logical_dest
,
1092 entry
.dest
.physical
.physical_dest
1095 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1100 entry
.delivery_status
,
1102 entry
.delivery_mode
,
1107 if (use_pci_vector())
1108 printk(KERN_INFO
"Using vector-based indexing\n");
1109 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1110 for (i
= 0; i
< NR_IRQS
; i
++) {
1111 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1114 if (use_pci_vector() && !platform_legacy_irq(i
))
1115 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1117 printk(KERN_DEBUG
"IRQ%d ", i
);
1119 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1122 entry
= irq_2_pin
+ entry
->next
;
1127 printk(KERN_INFO
".................................... done.\n");
1134 static __apicdebuginit
void print_APIC_bitfield (int base
)
1139 if (apic_verbosity
== APIC_QUIET
)
1142 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1143 for (i
= 0; i
< 8; i
++) {
1144 v
= apic_read(base
+ i
*0x10);
1145 for (j
= 0; j
< 32; j
++) {
1155 void __apicdebuginit
print_local_APIC(void * dummy
)
1157 unsigned int v
, ver
, maxlvt
;
1159 if (apic_verbosity
== APIC_QUIET
)
1162 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1163 smp_processor_id(), hard_smp_processor_id());
1164 v
= apic_read(APIC_ID
);
1165 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1166 v
= apic_read(APIC_LVR
);
1167 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1168 ver
= GET_APIC_VERSION(v
);
1169 maxlvt
= get_maxlvt();
1171 v
= apic_read(APIC_TASKPRI
);
1172 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1174 v
= apic_read(APIC_ARBPRI
);
1175 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1176 v
& APIC_ARBPRI_MASK
);
1177 v
= apic_read(APIC_PROCPRI
);
1178 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1180 v
= apic_read(APIC_EOI
);
1181 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1182 v
= apic_read(APIC_RRR
);
1183 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1184 v
= apic_read(APIC_LDR
);
1185 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1186 v
= apic_read(APIC_DFR
);
1187 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1188 v
= apic_read(APIC_SPIV
);
1189 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1191 printk(KERN_DEBUG
"... APIC ISR field:\n");
1192 print_APIC_bitfield(APIC_ISR
);
1193 printk(KERN_DEBUG
"... APIC TMR field:\n");
1194 print_APIC_bitfield(APIC_TMR
);
1195 printk(KERN_DEBUG
"... APIC IRR field:\n");
1196 print_APIC_bitfield(APIC_IRR
);
1198 v
= apic_read(APIC_ESR
);
1199 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1201 v
= apic_read(APIC_ICR
);
1202 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1203 v
= apic_read(APIC_ICR2
);
1204 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1206 v
= apic_read(APIC_LVTT
);
1207 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1209 if (maxlvt
> 3) { /* PC is LVT#4. */
1210 v
= apic_read(APIC_LVTPC
);
1211 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1213 v
= apic_read(APIC_LVT0
);
1214 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1215 v
= apic_read(APIC_LVT1
);
1216 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1218 if (maxlvt
> 2) { /* ERR is LVT#3. */
1219 v
= apic_read(APIC_LVTERR
);
1220 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1223 v
= apic_read(APIC_TMICT
);
1224 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1225 v
= apic_read(APIC_TMCCT
);
1226 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1227 v
= apic_read(APIC_TDCR
);
1228 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1232 void print_all_local_APICs (void)
1234 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1237 void __apicdebuginit
print_PIC(void)
1240 unsigned long flags
;
1242 if (apic_verbosity
== APIC_QUIET
)
1245 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1247 spin_lock_irqsave(&i8259A_lock
, flags
);
1249 v
= inb(0xa1) << 8 | inb(0x21);
1250 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1252 v
= inb(0xa0) << 8 | inb(0x20);
1253 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1257 v
= inb(0xa0) << 8 | inb(0x20);
1261 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1263 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1265 v
= inb(0x4d1) << 8 | inb(0x4d0);
1266 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1271 static void __init
enable_IO_APIC(void)
1273 union IO_APIC_reg_01 reg_01
;
1274 int i8259_apic
, i8259_pin
;
1276 unsigned long flags
;
1278 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1279 irq_2_pin
[i
].pin
= -1;
1280 irq_2_pin
[i
].next
= 0;
1283 for (i
= 0; i
< MAX_PIRQS
; i
++)
1284 pirq_entries
[i
] = -1;
1287 * The number of IO-APIC IRQ registers (== #pins):
1289 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1290 spin_lock_irqsave(&ioapic_lock
, flags
);
1291 reg_01
.raw
= io_apic_read(apic
, 1);
1292 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1293 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1295 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1297 /* See if any of the pins is in ExtINT mode */
1298 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1299 struct IO_APIC_route_entry entry
;
1300 spin_lock_irqsave(&ioapic_lock
, flags
);
1301 *(((int *)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1302 *(((int *)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1303 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1306 /* If the interrupt line is enabled and in ExtInt mode
1307 * I have found the pin where the i8259 is connected.
1309 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1310 ioapic_i8259
.apic
= apic
;
1311 ioapic_i8259
.pin
= pin
;
1317 /* Look to see what if the MP table has reported the ExtINT */
1318 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1319 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1320 /* Trust the MP table if nothing is setup in the hardware */
1321 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1322 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1323 ioapic_i8259
.pin
= i8259_pin
;
1324 ioapic_i8259
.apic
= i8259_apic
;
1326 /* Complain if the MP table and the hardware disagree */
1327 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1328 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1330 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1334 * Do not trust the IO-APIC being empty at bootup
1340 * Not an __init, needed by the reboot code
1342 void disable_IO_APIC(void)
1345 * Clear the IO-APIC before rebooting:
1350 * If the i8259 is routed through an IOAPIC
1351 * Put that IOAPIC in virtual wire mode
1352 * so legacy interrupts can be delivered.
1354 if (ioapic_i8259
.pin
!= -1) {
1355 struct IO_APIC_route_entry entry
;
1356 unsigned long flags
;
1358 memset(&entry
, 0, sizeof(entry
));
1359 entry
.mask
= 0; /* Enabled */
1360 entry
.trigger
= 0; /* Edge */
1362 entry
.polarity
= 0; /* High */
1363 entry
.delivery_status
= 0;
1364 entry
.dest_mode
= 0; /* Physical */
1365 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1367 entry
.dest
.physical
.physical_dest
=
1368 GET_APIC_ID(apic_read(APIC_ID
));
1371 * Add it to the IO-APIC irq-routing table:
1373 spin_lock_irqsave(&ioapic_lock
, flags
);
1374 io_apic_write(ioapic_i8259
.apic
, 0x11+2*ioapic_i8259
.pin
,
1375 *(((int *)&entry
)+1));
1376 io_apic_write(ioapic_i8259
.apic
, 0x10+2*ioapic_i8259
.pin
,
1377 *(((int *)&entry
)+0));
1378 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1381 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1385 * function to set the IO-APIC physical IDs based on the
1386 * values stored in the MPC table.
1388 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1391 static void __init
setup_ioapic_ids_from_mpc (void)
1393 union IO_APIC_reg_00 reg_00
;
1396 unsigned char old_id
;
1397 unsigned long flags
;
1400 * Set the IOAPIC ID to the value stored in the MPC table.
1402 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1404 /* Read the register 0 value */
1405 spin_lock_irqsave(&ioapic_lock
, flags
);
1406 reg_00
.raw
= io_apic_read(apic
, 0);
1407 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1409 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1412 printk(KERN_INFO
"Using IO-APIC %d\n", mp_ioapics
[apic
].mpc_apicid
);
1416 * We need to adjust the IRQ routing table
1417 * if the ID changed.
1419 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1420 for (i
= 0; i
< mp_irq_entries
; i
++)
1421 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1422 mp_irqs
[i
].mpc_dstapic
1423 = mp_ioapics
[apic
].mpc_apicid
;
1426 * Read the right value from the MPC table and
1427 * write it into the ID register.
1429 apic_printk(APIC_VERBOSE
,KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
1430 mp_ioapics
[apic
].mpc_apicid
);
1432 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1433 spin_lock_irqsave(&ioapic_lock
, flags
);
1434 io_apic_write(apic
, 0, reg_00
.raw
);
1435 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1440 spin_lock_irqsave(&ioapic_lock
, flags
);
1441 reg_00
.raw
= io_apic_read(apic
, 0);
1442 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1443 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1444 printk("could not set ID!\n");
1446 apic_printk(APIC_VERBOSE
," ok.\n");
1451 * There is a nasty bug in some older SMP boards, their mptable lies
1452 * about the timer IRQ. We do the following to work around the situation:
1454 * - timer IRQ defaults to IO-APIC IRQ
1455 * - if this function detects that timer IRQs are defunct, then we fall
1456 * back to ISA timer IRQs
1458 static int __init
timer_irq_works(void)
1460 unsigned long t1
= jiffies
;
1463 /* Let ten ticks pass... */
1464 mdelay((10 * 1000) / HZ
);
1467 * Expect a few ticks at least, to be sure some possible
1468 * glue logic does not lock up after one or two first
1469 * ticks in a non-ExtINT mode. Also the local APIC
1470 * might have cached one ExtINT interrupt. Finally, at
1471 * least one tick may be lost due to delays.
1475 if (jiffies
- t1
> 4)
1481 * In the SMP+IOAPIC case it might happen that there are an unspecified
1482 * number of pending IRQ events unhandled. These cases are very rare,
1483 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1484 * better to do it this way as thus we do not have to be aware of
1485 * 'pending' interrupts in the IRQ path, except at this point.
1488 * Edge triggered needs to resend any interrupt
1489 * that was delayed but this is now handled in the device
1494 * Starting up a edge-triggered IO-APIC interrupt is
1495 * nasty - we need to make sure that we get the edge.
1496 * If it is already asserted for some reason, we need
1497 * return 1 to indicate that is was pending.
1499 * This is not complete - we should be able to fake
1500 * an edge even if it isn't on the 8259A...
1503 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1505 int was_pending
= 0;
1506 unsigned long flags
;
1508 spin_lock_irqsave(&ioapic_lock
, flags
);
1510 disable_8259A_irq(irq
);
1511 if (i8259A_irq_pending(irq
))
1514 __unmask_IO_APIC_irq(irq
);
1515 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1521 * Once we have recorded IRQ_PENDING already, we can mask the
1522 * interrupt for real. This prevents IRQ storms from unhandled
1525 static void ack_edge_ioapic_irq(unsigned int irq
)
1528 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1529 == (IRQ_PENDING
| IRQ_DISABLED
))
1530 mask_IO_APIC_irq(irq
);
1535 * Level triggered interrupts can just be masked,
1536 * and shutting down and starting up the interrupt
1537 * is the same as enabling and disabling them -- except
1538 * with a startup need to return a "was pending" value.
1540 * Level triggered interrupts are special because we
1541 * do not touch any IO-APIC register while handling
1542 * them. We ack the APIC in the end-IRQ handler, not
1543 * in the start-IRQ-handler. Protection against reentrance
1544 * from the same interrupt is still provided, both by the
1545 * generic IRQ layer and by the fact that an unacked local
1546 * APIC does not accept IRQs.
1548 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1550 unmask_IO_APIC_irq(irq
);
1552 return 0; /* don't check for pending */
1555 static void end_level_ioapic_irq (unsigned int irq
)
1561 #ifdef CONFIG_PCI_MSI
1562 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
1564 int irq
= vector_to_irq(vector
);
1566 return startup_edge_ioapic_irq(irq
);
1569 static void ack_edge_ioapic_vector(unsigned int vector
)
1571 int irq
= vector_to_irq(vector
);
1573 move_native_irq(vector
);
1574 ack_edge_ioapic_irq(irq
);
1577 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
1579 int irq
= vector_to_irq(vector
);
1581 return startup_level_ioapic_irq (irq
);
1584 static void end_level_ioapic_vector (unsigned int vector
)
1586 int irq
= vector_to_irq(vector
);
1588 move_native_irq(vector
);
1589 end_level_ioapic_irq(irq
);
1592 static void mask_IO_APIC_vector (unsigned int vector
)
1594 int irq
= vector_to_irq(vector
);
1596 mask_IO_APIC_irq(irq
);
1599 static void unmask_IO_APIC_vector (unsigned int vector
)
1601 int irq
= vector_to_irq(vector
);
1603 unmask_IO_APIC_irq(irq
);
1607 static void set_ioapic_affinity_vector (unsigned int vector
,
1610 int irq
= vector_to_irq(vector
);
1612 set_native_irq_info(vector
, cpu_mask
);
1613 set_ioapic_affinity_irq(irq
, cpu_mask
);
1615 #endif // CONFIG_SMP
1616 #endif // CONFIG_PCI_MSI
1619 * Level and edge triggered IO-APIC interrupts need different handling,
1620 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1621 * handled with the level-triggered descriptor, but that one has slightly
1622 * more overhead. Level-triggered interrupts cannot be handled with the
1623 * edge-triggered handler, without risking IRQ storms and other ugly
1627 static struct hw_interrupt_type ioapic_edge_type __read_mostly
= {
1628 .typename
= "IO-APIC-edge",
1629 .startup
= startup_edge_ioapic
,
1630 .shutdown
= shutdown_edge_ioapic
,
1631 .enable
= enable_edge_ioapic
,
1632 .disable
= disable_edge_ioapic
,
1633 .ack
= ack_edge_ioapic
,
1634 .end
= end_edge_ioapic
,
1636 .set_affinity
= set_ioapic_affinity
,
1640 static struct hw_interrupt_type ioapic_level_type __read_mostly
= {
1641 .typename
= "IO-APIC-level",
1642 .startup
= startup_level_ioapic
,
1643 .shutdown
= shutdown_level_ioapic
,
1644 .enable
= enable_level_ioapic
,
1645 .disable
= disable_level_ioapic
,
1646 .ack
= mask_and_ack_level_ioapic
,
1647 .end
= end_level_ioapic
,
1649 .set_affinity
= set_ioapic_affinity
,
1653 static inline void init_IO_APIC_traps(void)
1658 * NOTE! The local APIC isn't very good at handling
1659 * multiple interrupts at the same interrupt level.
1660 * As the interrupt level is determined by taking the
1661 * vector number and shifting that right by 4, we
1662 * want to spread these out a bit so that they don't
1663 * all fall in the same interrupt level.
1665 * Also, we've got to be careful not to trash gate
1666 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1668 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1670 if (use_pci_vector()) {
1671 if (!platform_legacy_irq(tmp
))
1672 if ((tmp
= vector_to_irq(tmp
)) == -1)
1675 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
1677 * Hmm.. We don't have an entry for this,
1678 * so default to an old-fashioned 8259
1679 * interrupt if we can..
1682 make_8259A_irq(irq
);
1684 /* Strange. Oh, well.. */
1685 irq_desc
[irq
].handler
= &no_irq_type
;
1690 static void enable_lapic_irq (unsigned int irq
)
1694 v
= apic_read(APIC_LVT0
);
1695 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1698 static void disable_lapic_irq (unsigned int irq
)
1702 v
= apic_read(APIC_LVT0
);
1703 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1706 static void ack_lapic_irq (unsigned int irq
)
1711 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1713 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
1714 .typename
= "local-APIC-edge",
1715 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
1716 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
1717 .enable
= enable_lapic_irq
,
1718 .disable
= disable_lapic_irq
,
1719 .ack
= ack_lapic_irq
,
1720 .end
= end_lapic_irq
,
1723 static void setup_nmi (void)
1726 * Dirty trick to enable the NMI watchdog ...
1727 * We put the 8259A master into AEOI mode and
1728 * unmask on all local APICs LVT0 as NMI.
1730 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1731 * is from Maciej W. Rozycki - so we do not have to EOI from
1732 * the NMI handler or the timer interrupt.
1734 printk(KERN_INFO
"activating NMI Watchdog ...");
1736 enable_NMI_through_LVT0(NULL
);
1742 * This looks a bit hackish but it's about the only one way of sending
1743 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1744 * not support the ExtINT mode, unfortunately. We need to send these
1745 * cycles as some i82489DX-based boards have glue logic that keeps the
1746 * 8259A interrupt line asserted until INTA. --macro
1748 static inline void unlock_ExtINT_logic(void)
1751 struct IO_APIC_route_entry entry0
, entry1
;
1752 unsigned char save_control
, save_freq_select
;
1753 unsigned long flags
;
1755 pin
= find_isa_irq_pin(8, mp_INT
);
1756 apic
= find_isa_irq_apic(8, mp_INT
);
1760 spin_lock_irqsave(&ioapic_lock
, flags
);
1761 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1762 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1763 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1764 clear_IO_APIC_pin(apic
, pin
);
1766 memset(&entry1
, 0, sizeof(entry1
));
1768 entry1
.dest_mode
= 0; /* physical delivery */
1769 entry1
.mask
= 0; /* unmask IRQ now */
1770 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1771 entry1
.delivery_mode
= dest_ExtINT
;
1772 entry1
.polarity
= entry0
.polarity
;
1776 spin_lock_irqsave(&ioapic_lock
, flags
);
1777 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1778 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1779 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1781 save_control
= CMOS_READ(RTC_CONTROL
);
1782 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1783 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1785 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1790 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1794 CMOS_WRITE(save_control
, RTC_CONTROL
);
1795 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1796 clear_IO_APIC_pin(apic
, pin
);
1798 spin_lock_irqsave(&ioapic_lock
, flags
);
1799 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1800 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1801 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1804 int timer_uses_ioapic_pin_0
;
1807 * This code may look a bit paranoid, but it's supposed to cooperate with
1808 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1809 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1810 * fanatically on his truly buggy board.
1812 * FIXME: really need to revamp this for modern platforms only.
1814 static inline void check_timer(void)
1816 int apic1
, pin1
, apic2
, pin2
;
1820 * get/set the timer IRQ vector:
1822 disable_8259A_irq(0);
1823 vector
= assign_irq_vector(0);
1824 set_intr_gate(vector
, interrupt
[0]);
1827 * Subtle, code in do_timer_interrupt() expects an AEOI
1828 * mode for the 8259A whenever interrupts are routed
1829 * through I/O APICs. Also IRQ0 has to be enabled in
1830 * the 8259A which implies the virtual wire has to be
1831 * disabled in the local APIC.
1833 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1835 if (timer_over_8254
> 0)
1836 enable_8259A_irq(0);
1838 pin1
= find_isa_irq_pin(0, mp_INT
);
1839 apic1
= find_isa_irq_apic(0, mp_INT
);
1840 pin2
= ioapic_i8259
.pin
;
1841 apic2
= ioapic_i8259
.apic
;
1844 timer_uses_ioapic_pin_0
= 1;
1846 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1847 vector
, apic1
, pin1
, apic2
, pin2
);
1851 * Ok, does IRQ0 through the IOAPIC work?
1853 unmask_IO_APIC_irq(0);
1854 if (!no_timer_check
&& timer_irq_works()) {
1855 nmi_watchdog_default();
1856 if (nmi_watchdog
== NMI_IO_APIC
) {
1857 disable_8259A_irq(0);
1859 enable_8259A_irq(0);
1861 if (disable_timer_pin_1
> 0)
1862 clear_IO_APIC_pin(0, pin1
);
1865 clear_IO_APIC_pin(apic1
, pin1
);
1866 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: 8254 timer not "
1867 "connected to IO-APIC\n");
1870 apic_printk(APIC_VERBOSE
,KERN_INFO
"...trying to set up timer (IRQ0) "
1871 "through the 8259A ... ");
1873 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
1876 * legacy devices should be connected to IO APIC #0
1878 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
1879 if (timer_irq_works()) {
1880 apic_printk(APIC_VERBOSE
," works.\n");
1881 nmi_watchdog_default();
1882 if (nmi_watchdog
== NMI_IO_APIC
) {
1888 * Cleanup, just in case ...
1890 clear_IO_APIC_pin(apic2
, pin2
);
1892 apic_printk(APIC_VERBOSE
," failed.\n");
1894 if (nmi_watchdog
== NMI_IO_APIC
) {
1895 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1899 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1901 disable_8259A_irq(0);
1902 irq_desc
[0].handler
= &lapic_irq_type
;
1903 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1904 enable_8259A_irq(0);
1906 if (timer_irq_works()) {
1907 apic_printk(APIC_VERBOSE
," works.\n");
1910 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1911 apic_printk(APIC_VERBOSE
," failed.\n");
1913 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1917 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1919 unlock_ExtINT_logic();
1921 if (timer_irq_works()) {
1922 apic_printk(APIC_VERBOSE
," works.\n");
1925 apic_printk(APIC_VERBOSE
," failed :(.\n");
1926 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1929 static int __init
notimercheck(char *s
)
1934 __setup("no_timer_check", notimercheck
);
1938 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1939 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1940 * Linux doesn't really care, as it's not actually used
1941 * for any interrupt handling anyway.
1943 #define PIC_IRQS (1<<2)
1945 void __init
setup_IO_APIC(void)
1950 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
1952 io_apic_irqs
= ~PIC_IRQS
;
1954 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
1957 * Set up the IO-APIC IRQ routing table.
1960 setup_ioapic_ids_from_mpc();
1962 setup_IO_APIC_irqs();
1963 init_IO_APIC_traps();
1969 struct sysfs_ioapic_data
{
1970 struct sys_device dev
;
1971 struct IO_APIC_route_entry entry
[0];
1973 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
1975 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1977 struct IO_APIC_route_entry
*entry
;
1978 struct sysfs_ioapic_data
*data
;
1979 unsigned long flags
;
1982 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1983 entry
= data
->entry
;
1984 spin_lock_irqsave(&ioapic_lock
, flags
);
1985 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
1986 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
1987 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
1989 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1994 static int ioapic_resume(struct sys_device
*dev
)
1996 struct IO_APIC_route_entry
*entry
;
1997 struct sysfs_ioapic_data
*data
;
1998 unsigned long flags
;
1999 union IO_APIC_reg_00 reg_00
;
2002 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2003 entry
= data
->entry
;
2005 spin_lock_irqsave(&ioapic_lock
, flags
);
2006 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2007 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2008 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2009 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2011 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2012 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2013 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2015 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2020 static struct sysdev_class ioapic_sysdev_class
= {
2021 set_kset_name("ioapic"),
2022 .suspend
= ioapic_suspend
,
2023 .resume
= ioapic_resume
,
2026 static int __init
ioapic_init_sysfs(void)
2028 struct sys_device
* dev
;
2029 int i
, size
, error
= 0;
2031 error
= sysdev_class_register(&ioapic_sysdev_class
);
2035 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2036 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2037 * sizeof(struct IO_APIC_route_entry
);
2038 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2039 if (!mp_ioapic_data
[i
]) {
2040 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2043 memset(mp_ioapic_data
[i
], 0, size
);
2044 dev
= &mp_ioapic_data
[i
]->dev
;
2046 dev
->cls
= &ioapic_sysdev_class
;
2047 error
= sysdev_register(dev
);
2049 kfree(mp_ioapic_data
[i
]);
2050 mp_ioapic_data
[i
] = NULL
;
2051 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2059 device_initcall(ioapic_init_sysfs
);
2061 /* --------------------------------------------------------------------------
2062 ACPI-based IOAPIC Configuration
2063 -------------------------------------------------------------------------- */
2067 #define IO_APIC_MAX_ID 0xFE
2069 int __init
io_apic_get_version (int ioapic
)
2071 union IO_APIC_reg_01 reg_01
;
2072 unsigned long flags
;
2074 spin_lock_irqsave(&ioapic_lock
, flags
);
2075 reg_01
.raw
= io_apic_read(ioapic
, 1);
2076 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2078 return reg_01
.bits
.version
;
2082 int __init
io_apic_get_redir_entries (int ioapic
)
2084 union IO_APIC_reg_01 reg_01
;
2085 unsigned long flags
;
2087 spin_lock_irqsave(&ioapic_lock
, flags
);
2088 reg_01
.raw
= io_apic_read(ioapic
, 1);
2089 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2091 return reg_01
.bits
.entries
;
2095 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2097 struct IO_APIC_route_entry entry
;
2098 unsigned long flags
;
2100 if (!IO_APIC_IRQ(irq
)) {
2101 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2107 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2108 * Note that we mask (disable) IRQs now -- these get enabled when the
2109 * corresponding device driver registers for this IRQ.
2112 memset(&entry
,0,sizeof(entry
));
2114 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2115 entry
.dest_mode
= INT_DEST_MODE
;
2116 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2117 entry
.trigger
= triggering
;
2118 entry
.polarity
= polarity
;
2119 entry
.mask
= 1; /* Disabled (masked) */
2121 irq
= gsi_irq_sharing(irq
);
2123 * IRQs < 16 are already in the irq_2_pin[] map
2126 add_pin_to_irq(irq
, ioapic
, pin
);
2128 entry
.vector
= assign_irq_vector(irq
);
2130 apic_printk(APIC_VERBOSE
,KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2131 "IRQ %d Mode:%i Active:%i)\n", ioapic
,
2132 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2133 triggering
, polarity
);
2135 ioapic_register_intr(irq
, entry
.vector
, triggering
);
2137 if (!ioapic
&& (irq
< 16))
2138 disable_8259A_irq(irq
);
2140 spin_lock_irqsave(&ioapic_lock
, flags
);
2141 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2142 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2143 set_native_irq_info(use_pci_vector() ? entry
.vector
: irq
, TARGET_CPUS
);
2144 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2149 #endif /* CONFIG_ACPI */
2153 * This function currently is only a helper for the i386 smp boot process where
2154 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2155 * so mask in all cases should simply be TARGET_CPUS
2158 void __init
setup_ioapic_dest(void)
2160 int pin
, ioapic
, irq
, irq_entry
;
2162 if (skip_ioapic_setup
== 1)
2165 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2166 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2167 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2168 if (irq_entry
== -1)
2170 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2171 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);