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[PATCH] htirq: tidy up the htirq code
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
35 #ifdef CONFIG_ACPI
36 #include <acpi/acpi_bus.h>
37 #endif
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 static int assign_irq_vector(int irq, cpumask_t mask);
51
52 #define __apicdebuginit __init
53
54 int sis_apic_bug; /* not actually supported, dummy for compile */
55
56 static int no_timer_check;
57
58 static int disable_timer_pin_1 __initdata;
59
60 int timer_over_8254 __initdata = 0;
61
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
64
65 static DEFINE_SPINLOCK(ioapic_lock);
66 static DEFINE_SPINLOCK(vector_lock);
67
68 /*
69 * # of IRQ routing registers
70 */
71 int nr_ioapic_registers[MAX_IO_APICS];
72
73 /*
74 * Rough estimation of how many shared IRQs there are, can
75 * be changed anytime.
76 */
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79
80 /*
81 * This is performance-critical, we want to do it O(1)
82 *
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
85 */
86
87 static struct irq_pin_list {
88 short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
90
91 #define __DO_ACTION(R, ACTION, FINAL) \
92 \
93 { \
94 int pin; \
95 struct irq_pin_list *entry = irq_2_pin + irq; \
96 \
97 BUG_ON(irq >= NR_IRQS); \
98 for (;;) { \
99 unsigned int reg; \
100 pin = entry->pin; \
101 if (pin == -1) \
102 break; \
103 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
104 reg ACTION; \
105 io_apic_modify(entry->apic, reg); \
106 if (!entry->next) \
107 break; \
108 entry = irq_2_pin + entry->next; \
109 } \
110 FINAL; \
111 }
112
113 union entry_union {
114 struct { u32 w1, w2; };
115 struct IO_APIC_route_entry entry;
116 };
117
118 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
119 {
120 union entry_union eu;
121 unsigned long flags;
122 spin_lock_irqsave(&ioapic_lock, flags);
123 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
124 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
125 spin_unlock_irqrestore(&ioapic_lock, flags);
126 return eu.entry;
127 }
128
129 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
130 {
131 unsigned long flags;
132 union entry_union eu;
133 eu.entry = e;
134 spin_lock_irqsave(&ioapic_lock, flags);
135 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
136 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
137 spin_unlock_irqrestore(&ioapic_lock, flags);
138 }
139
140 #ifdef CONFIG_SMP
141 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
142 {
143 int apic, pin;
144 struct irq_pin_list *entry = irq_2_pin + irq;
145
146 BUG_ON(irq >= NR_IRQS);
147 for (;;) {
148 unsigned int reg;
149 apic = entry->apic;
150 pin = entry->pin;
151 if (pin == -1)
152 break;
153 io_apic_write(apic, 0x11 + pin*2, dest);
154 reg = io_apic_read(apic, 0x10 + pin*2);
155 reg &= ~0x000000ff;
156 reg |= vector;
157 io_apic_modify(apic, reg);
158 if (!entry->next)
159 break;
160 entry = irq_2_pin + entry->next;
161 }
162 }
163
164 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
165 {
166 unsigned long flags;
167 unsigned int dest;
168 cpumask_t tmp;
169 int vector;
170
171 cpus_and(tmp, mask, cpu_online_map);
172 if (cpus_empty(tmp))
173 tmp = TARGET_CPUS;
174
175 cpus_and(mask, tmp, CPU_MASK_ALL);
176
177 vector = assign_irq_vector(irq, mask);
178 if (vector < 0)
179 return;
180
181 cpus_clear(tmp);
182 cpu_set(vector >> 8, tmp);
183 dest = cpu_mask_to_apicid(tmp);
184
185 /*
186 * Only the high 8 bits are valid.
187 */
188 dest = SET_APIC_LOGICAL_ID(dest);
189
190 spin_lock_irqsave(&ioapic_lock, flags);
191 __target_IO_APIC_irq(irq, dest, vector & 0xff);
192 set_native_irq_info(irq, mask);
193 spin_unlock_irqrestore(&ioapic_lock, flags);
194 }
195 #endif
196
197 /*
198 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
199 * shared ISA-space IRQs, so we have to support them. We are super
200 * fast in the common case, and fast for shared ISA-space IRQs.
201 */
202 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
203 {
204 static int first_free_entry = NR_IRQS;
205 struct irq_pin_list *entry = irq_2_pin + irq;
206
207 BUG_ON(irq >= NR_IRQS);
208 while (entry->next)
209 entry = irq_2_pin + entry->next;
210
211 if (entry->pin != -1) {
212 entry->next = first_free_entry;
213 entry = irq_2_pin + entry->next;
214 if (++first_free_entry >= PIN_MAP_SIZE)
215 panic("io_apic.c: ran out of irq_2_pin entries!");
216 }
217 entry->apic = apic;
218 entry->pin = pin;
219 }
220
221
222 #define DO_ACTION(name,R,ACTION, FINAL) \
223 \
224 static void name##_IO_APIC_irq (unsigned int irq) \
225 __DO_ACTION(R, ACTION, FINAL)
226
227 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
228 /* mask = 1 */
229 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
230 /* mask = 0 */
231
232 static void mask_IO_APIC_irq (unsigned int irq)
233 {
234 unsigned long flags;
235
236 spin_lock_irqsave(&ioapic_lock, flags);
237 __mask_IO_APIC_irq(irq);
238 spin_unlock_irqrestore(&ioapic_lock, flags);
239 }
240
241 static void unmask_IO_APIC_irq (unsigned int irq)
242 {
243 unsigned long flags;
244
245 spin_lock_irqsave(&ioapic_lock, flags);
246 __unmask_IO_APIC_irq(irq);
247 spin_unlock_irqrestore(&ioapic_lock, flags);
248 }
249
250 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
251 {
252 struct IO_APIC_route_entry entry;
253
254 /* Check delivery_mode to be sure we're not clearing an SMI pin */
255 entry = ioapic_read_entry(apic, pin);
256 if (entry.delivery_mode == dest_SMI)
257 return;
258 /*
259 * Disable it in the IO-APIC irq-routing table:
260 */
261 memset(&entry, 0, sizeof(entry));
262 entry.mask = 1;
263 ioapic_write_entry(apic, pin, entry);
264 }
265
266 static void clear_IO_APIC (void)
267 {
268 int apic, pin;
269
270 for (apic = 0; apic < nr_ioapics; apic++)
271 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
272 clear_IO_APIC_pin(apic, pin);
273 }
274
275 int skip_ioapic_setup;
276 int ioapic_force;
277
278 /* dummy parsing: see setup.c */
279
280 static int __init disable_ioapic_setup(char *str)
281 {
282 skip_ioapic_setup = 1;
283 return 0;
284 }
285 early_param("noapic", disable_ioapic_setup);
286
287 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
288 static int __init disable_timer_pin_setup(char *arg)
289 {
290 disable_timer_pin_1 = 1;
291 return 1;
292 }
293 __setup("disable_timer_pin_1", disable_timer_pin_setup);
294
295 static int __init setup_disable_8254_timer(char *s)
296 {
297 timer_over_8254 = -1;
298 return 1;
299 }
300 static int __init setup_enable_8254_timer(char *s)
301 {
302 timer_over_8254 = 2;
303 return 1;
304 }
305
306 __setup("disable_8254_timer", setup_disable_8254_timer);
307 __setup("enable_8254_timer", setup_enable_8254_timer);
308
309
310 /*
311 * Find the IRQ entry number of a certain pin.
312 */
313 static int find_irq_entry(int apic, int pin, int type)
314 {
315 int i;
316
317 for (i = 0; i < mp_irq_entries; i++)
318 if (mp_irqs[i].mpc_irqtype == type &&
319 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
320 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
321 mp_irqs[i].mpc_dstirq == pin)
322 return i;
323
324 return -1;
325 }
326
327 /*
328 * Find the pin to which IRQ[irq] (ISA) is connected
329 */
330 static int __init find_isa_irq_pin(int irq, int type)
331 {
332 int i;
333
334 for (i = 0; i < mp_irq_entries; i++) {
335 int lbus = mp_irqs[i].mpc_srcbus;
336
337 if (test_bit(lbus, mp_bus_not_pci) &&
338 (mp_irqs[i].mpc_irqtype == type) &&
339 (mp_irqs[i].mpc_srcbusirq == irq))
340
341 return mp_irqs[i].mpc_dstirq;
342 }
343 return -1;
344 }
345
346 static int __init find_isa_irq_apic(int irq, int type)
347 {
348 int i;
349
350 for (i = 0; i < mp_irq_entries; i++) {
351 int lbus = mp_irqs[i].mpc_srcbus;
352
353 if (test_bit(lbus, mp_bus_not_pci) &&
354 (mp_irqs[i].mpc_irqtype == type) &&
355 (mp_irqs[i].mpc_srcbusirq == irq))
356 break;
357 }
358 if (i < mp_irq_entries) {
359 int apic;
360 for(apic = 0; apic < nr_ioapics; apic++) {
361 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
362 return apic;
363 }
364 }
365
366 return -1;
367 }
368
369 /*
370 * Find a specific PCI IRQ entry.
371 * Not an __init, possibly needed by modules
372 */
373 static int pin_2_irq(int idx, int apic, int pin);
374
375 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
376 {
377 int apic, i, best_guess = -1;
378
379 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
380 bus, slot, pin);
381 if (mp_bus_id_to_pci_bus[bus] == -1) {
382 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
383 return -1;
384 }
385 for (i = 0; i < mp_irq_entries; i++) {
386 int lbus = mp_irqs[i].mpc_srcbus;
387
388 for (apic = 0; apic < nr_ioapics; apic++)
389 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
390 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
391 break;
392
393 if (!test_bit(lbus, mp_bus_not_pci) &&
394 !mp_irqs[i].mpc_irqtype &&
395 (bus == lbus) &&
396 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
397 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
398
399 if (!(apic || IO_APIC_IRQ(irq)))
400 continue;
401
402 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
403 return irq;
404 /*
405 * Use the first all-but-pin matching entry as a
406 * best-guess fuzzy result for broken mptables.
407 */
408 if (best_guess < 0)
409 best_guess = irq;
410 }
411 }
412 BUG_ON(best_guess >= NR_IRQS);
413 return best_guess;
414 }
415
416 /* ISA interrupts are always polarity zero edge triggered,
417 * when listed as conforming in the MP table. */
418
419 #define default_ISA_trigger(idx) (0)
420 #define default_ISA_polarity(idx) (0)
421
422 /* PCI interrupts are always polarity one level triggered,
423 * when listed as conforming in the MP table. */
424
425 #define default_PCI_trigger(idx) (1)
426 #define default_PCI_polarity(idx) (1)
427
428 static int __init MPBIOS_polarity(int idx)
429 {
430 int bus = mp_irqs[idx].mpc_srcbus;
431 int polarity;
432
433 /*
434 * Determine IRQ line polarity (high active or low active):
435 */
436 switch (mp_irqs[idx].mpc_irqflag & 3)
437 {
438 case 0: /* conforms, ie. bus-type dependent polarity */
439 if (test_bit(bus, mp_bus_not_pci))
440 polarity = default_ISA_polarity(idx);
441 else
442 polarity = default_PCI_polarity(idx);
443 break;
444 case 1: /* high active */
445 {
446 polarity = 0;
447 break;
448 }
449 case 2: /* reserved */
450 {
451 printk(KERN_WARNING "broken BIOS!!\n");
452 polarity = 1;
453 break;
454 }
455 case 3: /* low active */
456 {
457 polarity = 1;
458 break;
459 }
460 default: /* invalid */
461 {
462 printk(KERN_WARNING "broken BIOS!!\n");
463 polarity = 1;
464 break;
465 }
466 }
467 return polarity;
468 }
469
470 static int MPBIOS_trigger(int idx)
471 {
472 int bus = mp_irqs[idx].mpc_srcbus;
473 int trigger;
474
475 /*
476 * Determine IRQ trigger mode (edge or level sensitive):
477 */
478 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
479 {
480 case 0: /* conforms, ie. bus-type dependent */
481 if (test_bit(bus, mp_bus_not_pci))
482 trigger = default_ISA_trigger(idx);
483 else
484 trigger = default_PCI_trigger(idx);
485 break;
486 case 1: /* edge */
487 {
488 trigger = 0;
489 break;
490 }
491 case 2: /* reserved */
492 {
493 printk(KERN_WARNING "broken BIOS!!\n");
494 trigger = 1;
495 break;
496 }
497 case 3: /* level */
498 {
499 trigger = 1;
500 break;
501 }
502 default: /* invalid */
503 {
504 printk(KERN_WARNING "broken BIOS!!\n");
505 trigger = 0;
506 break;
507 }
508 }
509 return trigger;
510 }
511
512 static inline int irq_polarity(int idx)
513 {
514 return MPBIOS_polarity(idx);
515 }
516
517 static inline int irq_trigger(int idx)
518 {
519 return MPBIOS_trigger(idx);
520 }
521
522 static int pin_2_irq(int idx, int apic, int pin)
523 {
524 int irq, i;
525 int bus = mp_irqs[idx].mpc_srcbus;
526
527 /*
528 * Debugging check, we are in big trouble if this message pops up!
529 */
530 if (mp_irqs[idx].mpc_dstirq != pin)
531 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
532
533 if (test_bit(bus, mp_bus_not_pci)) {
534 irq = mp_irqs[idx].mpc_srcbusirq;
535 } else {
536 /*
537 * PCI IRQs are mapped in order
538 */
539 i = irq = 0;
540 while (i < apic)
541 irq += nr_ioapic_registers[i++];
542 irq += pin;
543 }
544 BUG_ON(irq >= NR_IRQS);
545 return irq;
546 }
547
548 static inline int IO_APIC_irq_trigger(int irq)
549 {
550 int apic, idx, pin;
551
552 for (apic = 0; apic < nr_ioapics; apic++) {
553 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
554 idx = find_irq_entry(apic,pin,mp_INT);
555 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
556 return irq_trigger(idx);
557 }
558 }
559 /*
560 * nonexistent IRQs are edge default
561 */
562 return 0;
563 }
564
565 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
566 unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 };
567
568 static int __assign_irq_vector(int irq, cpumask_t mask)
569 {
570 /*
571 * NOTE! The local APIC isn't very good at handling
572 * multiple interrupts at the same interrupt level.
573 * As the interrupt level is determined by taking the
574 * vector number and shifting that right by 4, we
575 * want to spread these out a bit so that they don't
576 * all fall in the same interrupt level.
577 *
578 * Also, we've got to be careful not to trash gate
579 * 0x80, because int 0x80 is hm, kind of importantish. ;)
580 */
581 static struct {
582 int vector;
583 int offset;
584 } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
585 int old_vector = -1;
586 int cpu;
587
588 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
589
590 if (IO_APIC_VECTOR(irq) > 0)
591 old_vector = IO_APIC_VECTOR(irq);
592 if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) {
593 return old_vector;
594 }
595
596 for_each_cpu_mask(cpu, mask) {
597 int vector, offset;
598 vector = pos[cpu].vector;
599 offset = pos[cpu].offset;
600 next:
601 vector += 8;
602 if (vector >= FIRST_SYSTEM_VECTOR) {
603 /* If we run out of vectors on large boxen, must share them. */
604 offset = (offset + 1) % 8;
605 vector = FIRST_DEVICE_VECTOR + offset;
606 }
607 if (unlikely(pos[cpu].vector == vector))
608 continue;
609 if (vector == IA32_SYSCALL_VECTOR)
610 goto next;
611 if (per_cpu(vector_irq, cpu)[vector] != -1)
612 goto next;
613 /* Found one! */
614 pos[cpu].vector = vector;
615 pos[cpu].offset = offset;
616 if (old_vector >= 0) {
617 int old_cpu = old_vector >> 8;
618 old_vector &= 0xff;
619 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
620 }
621 per_cpu(vector_irq, cpu)[vector] = irq;
622 vector |= cpu << 8;
623 IO_APIC_VECTOR(irq) = vector;
624 return vector;
625 }
626 return -ENOSPC;
627 }
628
629 static int assign_irq_vector(int irq, cpumask_t mask)
630 {
631 int vector;
632 unsigned long flags;
633
634 spin_lock_irqsave(&vector_lock, flags);
635 vector = __assign_irq_vector(irq, mask);
636 spin_unlock_irqrestore(&vector_lock, flags);
637 return vector;
638 }
639
640 extern void (*interrupt[NR_IRQS])(void);
641
642 static struct irq_chip ioapic_chip;
643
644 #define IOAPIC_AUTO -1
645 #define IOAPIC_EDGE 0
646 #define IOAPIC_LEVEL 1
647
648 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
649 {
650 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
651 trigger == IOAPIC_LEVEL)
652 set_irq_chip_and_handler(irq, &ioapic_chip,
653 handle_fasteoi_irq);
654 else
655 set_irq_chip_and_handler(irq, &ioapic_chip,
656 handle_edge_irq);
657 }
658
659 static void __init setup_IO_APIC_irqs(void)
660 {
661 struct IO_APIC_route_entry entry;
662 int apic, pin, idx, irq, first_notcon = 1, vector;
663 unsigned long flags;
664
665 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
666
667 for (apic = 0; apic < nr_ioapics; apic++) {
668 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
669
670 /*
671 * add it to the IO-APIC irq-routing table:
672 */
673 memset(&entry,0,sizeof(entry));
674
675 entry.delivery_mode = INT_DELIVERY_MODE;
676 entry.dest_mode = INT_DEST_MODE;
677 entry.mask = 0; /* enable IRQ */
678 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
679
680 idx = find_irq_entry(apic,pin,mp_INT);
681 if (idx == -1) {
682 if (first_notcon) {
683 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
684 first_notcon = 0;
685 } else
686 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
687 continue;
688 }
689
690 entry.trigger = irq_trigger(idx);
691 entry.polarity = irq_polarity(idx);
692
693 if (irq_trigger(idx)) {
694 entry.trigger = 1;
695 entry.mask = 1;
696 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
697 }
698
699 irq = pin_2_irq(idx, apic, pin);
700 add_pin_to_irq(irq, apic, pin);
701
702 if (!apic && !IO_APIC_IRQ(irq))
703 continue;
704
705 if (IO_APIC_IRQ(irq)) {
706 cpumask_t mask;
707 vector = assign_irq_vector(irq, TARGET_CPUS);
708 if (vector < 0)
709 continue;
710
711 cpus_clear(mask);
712 cpu_set(vector >> 8, mask);
713 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
714 entry.vector = vector & 0xff;
715
716 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
717 if (!apic && (irq < 16))
718 disable_8259A_irq(irq);
719 }
720 ioapic_write_entry(apic, pin, entry);
721
722 spin_lock_irqsave(&ioapic_lock, flags);
723 set_native_irq_info(irq, TARGET_CPUS);
724 spin_unlock_irqrestore(&ioapic_lock, flags);
725 }
726 }
727
728 if (!first_notcon)
729 apic_printk(APIC_VERBOSE," not connected.\n");
730 }
731
732 /*
733 * Set up the 8259A-master output pin as broadcast to all
734 * CPUs.
735 */
736 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
737 {
738 struct IO_APIC_route_entry entry;
739 unsigned long flags;
740
741 memset(&entry,0,sizeof(entry));
742
743 disable_8259A_irq(0);
744
745 /* mask LVT0 */
746 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
747
748 /*
749 * We use logical delivery to get the timer IRQ
750 * to the first CPU.
751 */
752 entry.dest_mode = INT_DEST_MODE;
753 entry.mask = 0; /* unmask IRQ now */
754 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
755 entry.delivery_mode = INT_DELIVERY_MODE;
756 entry.polarity = 0;
757 entry.trigger = 0;
758 entry.vector = vector;
759
760 /*
761 * The timer IRQ doesn't have to know that behind the
762 * scene we have a 8259A-master in AEOI mode ...
763 */
764 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
765
766 /*
767 * Add it to the IO-APIC irq-routing table:
768 */
769 spin_lock_irqsave(&ioapic_lock, flags);
770 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
771 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
772 spin_unlock_irqrestore(&ioapic_lock, flags);
773
774 enable_8259A_irq(0);
775 }
776
777 void __init UNEXPECTED_IO_APIC(void)
778 {
779 }
780
781 void __apicdebuginit print_IO_APIC(void)
782 {
783 int apic, i;
784 union IO_APIC_reg_00 reg_00;
785 union IO_APIC_reg_01 reg_01;
786 union IO_APIC_reg_02 reg_02;
787 unsigned long flags;
788
789 if (apic_verbosity == APIC_QUIET)
790 return;
791
792 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
793 for (i = 0; i < nr_ioapics; i++)
794 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
795 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
796
797 /*
798 * We are a bit conservative about what we expect. We have to
799 * know about every hardware change ASAP.
800 */
801 printk(KERN_INFO "testing the IO APIC.......................\n");
802
803 for (apic = 0; apic < nr_ioapics; apic++) {
804
805 spin_lock_irqsave(&ioapic_lock, flags);
806 reg_00.raw = io_apic_read(apic, 0);
807 reg_01.raw = io_apic_read(apic, 1);
808 if (reg_01.bits.version >= 0x10)
809 reg_02.raw = io_apic_read(apic, 2);
810 spin_unlock_irqrestore(&ioapic_lock, flags);
811
812 printk("\n");
813 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
814 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
815 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
816 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
817 UNEXPECTED_IO_APIC();
818
819 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
820 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
821 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
822 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
823 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
824 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
825 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
826 (reg_01.bits.entries != 0x2E) &&
827 (reg_01.bits.entries != 0x3F) &&
828 (reg_01.bits.entries != 0x03)
829 )
830 UNEXPECTED_IO_APIC();
831
832 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
833 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
834 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
835 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
836 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
837 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
838 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
839 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
840 )
841 UNEXPECTED_IO_APIC();
842 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
843 UNEXPECTED_IO_APIC();
844
845 if (reg_01.bits.version >= 0x10) {
846 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
847 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
848 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
849 UNEXPECTED_IO_APIC();
850 }
851
852 printk(KERN_DEBUG ".... IRQ redirection table:\n");
853
854 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
855 " Stat Dest Deli Vect: \n");
856
857 for (i = 0; i <= reg_01.bits.entries; i++) {
858 struct IO_APIC_route_entry entry;
859
860 entry = ioapic_read_entry(apic, i);
861
862 printk(KERN_DEBUG " %02x %03X %02X ",
863 i,
864 entry.dest.logical.logical_dest,
865 entry.dest.physical.physical_dest
866 );
867
868 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
869 entry.mask,
870 entry.trigger,
871 entry.irr,
872 entry.polarity,
873 entry.delivery_status,
874 entry.dest_mode,
875 entry.delivery_mode,
876 entry.vector
877 );
878 }
879 }
880 printk(KERN_DEBUG "IRQ to pin mappings:\n");
881 for (i = 0; i < NR_IRQS; i++) {
882 struct irq_pin_list *entry = irq_2_pin + i;
883 if (entry->pin < 0)
884 continue;
885 printk(KERN_DEBUG "IRQ%d ", i);
886 for (;;) {
887 printk("-> %d:%d", entry->apic, entry->pin);
888 if (!entry->next)
889 break;
890 entry = irq_2_pin + entry->next;
891 }
892 printk("\n");
893 }
894
895 printk(KERN_INFO ".................................... done.\n");
896
897 return;
898 }
899
900 #if 0
901
902 static __apicdebuginit void print_APIC_bitfield (int base)
903 {
904 unsigned int v;
905 int i, j;
906
907 if (apic_verbosity == APIC_QUIET)
908 return;
909
910 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
911 for (i = 0; i < 8; i++) {
912 v = apic_read(base + i*0x10);
913 for (j = 0; j < 32; j++) {
914 if (v & (1<<j))
915 printk("1");
916 else
917 printk("0");
918 }
919 printk("\n");
920 }
921 }
922
923 void __apicdebuginit print_local_APIC(void * dummy)
924 {
925 unsigned int v, ver, maxlvt;
926
927 if (apic_verbosity == APIC_QUIET)
928 return;
929
930 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
931 smp_processor_id(), hard_smp_processor_id());
932 v = apic_read(APIC_ID);
933 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
934 v = apic_read(APIC_LVR);
935 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
936 ver = GET_APIC_VERSION(v);
937 maxlvt = get_maxlvt();
938
939 v = apic_read(APIC_TASKPRI);
940 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
941
942 v = apic_read(APIC_ARBPRI);
943 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
944 v & APIC_ARBPRI_MASK);
945 v = apic_read(APIC_PROCPRI);
946 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
947
948 v = apic_read(APIC_EOI);
949 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
950 v = apic_read(APIC_RRR);
951 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
952 v = apic_read(APIC_LDR);
953 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
954 v = apic_read(APIC_DFR);
955 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
956 v = apic_read(APIC_SPIV);
957 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
958
959 printk(KERN_DEBUG "... APIC ISR field:\n");
960 print_APIC_bitfield(APIC_ISR);
961 printk(KERN_DEBUG "... APIC TMR field:\n");
962 print_APIC_bitfield(APIC_TMR);
963 printk(KERN_DEBUG "... APIC IRR field:\n");
964 print_APIC_bitfield(APIC_IRR);
965
966 v = apic_read(APIC_ESR);
967 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
968
969 v = apic_read(APIC_ICR);
970 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
971 v = apic_read(APIC_ICR2);
972 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
973
974 v = apic_read(APIC_LVTT);
975 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
976
977 if (maxlvt > 3) { /* PC is LVT#4. */
978 v = apic_read(APIC_LVTPC);
979 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
980 }
981 v = apic_read(APIC_LVT0);
982 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
983 v = apic_read(APIC_LVT1);
984 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
985
986 if (maxlvt > 2) { /* ERR is LVT#3. */
987 v = apic_read(APIC_LVTERR);
988 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
989 }
990
991 v = apic_read(APIC_TMICT);
992 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
993 v = apic_read(APIC_TMCCT);
994 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
995 v = apic_read(APIC_TDCR);
996 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
997 printk("\n");
998 }
999
1000 void print_all_local_APICs (void)
1001 {
1002 on_each_cpu(print_local_APIC, NULL, 1, 1);
1003 }
1004
1005 void __apicdebuginit print_PIC(void)
1006 {
1007 unsigned int v;
1008 unsigned long flags;
1009
1010 if (apic_verbosity == APIC_QUIET)
1011 return;
1012
1013 printk(KERN_DEBUG "\nprinting PIC contents\n");
1014
1015 spin_lock_irqsave(&i8259A_lock, flags);
1016
1017 v = inb(0xa1) << 8 | inb(0x21);
1018 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1019
1020 v = inb(0xa0) << 8 | inb(0x20);
1021 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1022
1023 outb(0x0b,0xa0);
1024 outb(0x0b,0x20);
1025 v = inb(0xa0) << 8 | inb(0x20);
1026 outb(0x0a,0xa0);
1027 outb(0x0a,0x20);
1028
1029 spin_unlock_irqrestore(&i8259A_lock, flags);
1030
1031 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1032
1033 v = inb(0x4d1) << 8 | inb(0x4d0);
1034 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1035 }
1036
1037 #endif /* 0 */
1038
1039 static void __init enable_IO_APIC(void)
1040 {
1041 union IO_APIC_reg_01 reg_01;
1042 int i8259_apic, i8259_pin;
1043 int i, apic;
1044 unsigned long flags;
1045
1046 for (i = 0; i < PIN_MAP_SIZE; i++) {
1047 irq_2_pin[i].pin = -1;
1048 irq_2_pin[i].next = 0;
1049 }
1050
1051 /*
1052 * The number of IO-APIC IRQ registers (== #pins):
1053 */
1054 for (apic = 0; apic < nr_ioapics; apic++) {
1055 spin_lock_irqsave(&ioapic_lock, flags);
1056 reg_01.raw = io_apic_read(apic, 1);
1057 spin_unlock_irqrestore(&ioapic_lock, flags);
1058 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1059 }
1060 for(apic = 0; apic < nr_ioapics; apic++) {
1061 int pin;
1062 /* See if any of the pins is in ExtINT mode */
1063 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1064 struct IO_APIC_route_entry entry;
1065 entry = ioapic_read_entry(apic, pin);
1066
1067 /* If the interrupt line is enabled and in ExtInt mode
1068 * I have found the pin where the i8259 is connected.
1069 */
1070 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1071 ioapic_i8259.apic = apic;
1072 ioapic_i8259.pin = pin;
1073 goto found_i8259;
1074 }
1075 }
1076 }
1077 found_i8259:
1078 /* Look to see what if the MP table has reported the ExtINT */
1079 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1080 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1081 /* Trust the MP table if nothing is setup in the hardware */
1082 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1083 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1084 ioapic_i8259.pin = i8259_pin;
1085 ioapic_i8259.apic = i8259_apic;
1086 }
1087 /* Complain if the MP table and the hardware disagree */
1088 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1089 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1090 {
1091 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1092 }
1093
1094 /*
1095 * Do not trust the IO-APIC being empty at bootup
1096 */
1097 clear_IO_APIC();
1098 }
1099
1100 /*
1101 * Not an __init, needed by the reboot code
1102 */
1103 void disable_IO_APIC(void)
1104 {
1105 /*
1106 * Clear the IO-APIC before rebooting:
1107 */
1108 clear_IO_APIC();
1109
1110 /*
1111 * If the i8259 is routed through an IOAPIC
1112 * Put that IOAPIC in virtual wire mode
1113 * so legacy interrupts can be delivered.
1114 */
1115 if (ioapic_i8259.pin != -1) {
1116 struct IO_APIC_route_entry entry;
1117
1118 memset(&entry, 0, sizeof(entry));
1119 entry.mask = 0; /* Enabled */
1120 entry.trigger = 0; /* Edge */
1121 entry.irr = 0;
1122 entry.polarity = 0; /* High */
1123 entry.delivery_status = 0;
1124 entry.dest_mode = 0; /* Physical */
1125 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1126 entry.vector = 0;
1127 entry.dest.physical.physical_dest =
1128 GET_APIC_ID(apic_read(APIC_ID));
1129
1130 /*
1131 * Add it to the IO-APIC irq-routing table:
1132 */
1133 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1134 }
1135
1136 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1137 }
1138
1139 /*
1140 * There is a nasty bug in some older SMP boards, their mptable lies
1141 * about the timer IRQ. We do the following to work around the situation:
1142 *
1143 * - timer IRQ defaults to IO-APIC IRQ
1144 * - if this function detects that timer IRQs are defunct, then we fall
1145 * back to ISA timer IRQs
1146 */
1147 static int __init timer_irq_works(void)
1148 {
1149 unsigned long t1 = jiffies;
1150
1151 local_irq_enable();
1152 /* Let ten ticks pass... */
1153 mdelay((10 * 1000) / HZ);
1154
1155 /*
1156 * Expect a few ticks at least, to be sure some possible
1157 * glue logic does not lock up after one or two first
1158 * ticks in a non-ExtINT mode. Also the local APIC
1159 * might have cached one ExtINT interrupt. Finally, at
1160 * least one tick may be lost due to delays.
1161 */
1162
1163 /* jiffies wrap? */
1164 if (jiffies - t1 > 4)
1165 return 1;
1166 return 0;
1167 }
1168
1169 /*
1170 * In the SMP+IOAPIC case it might happen that there are an unspecified
1171 * number of pending IRQ events unhandled. These cases are very rare,
1172 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1173 * better to do it this way as thus we do not have to be aware of
1174 * 'pending' interrupts in the IRQ path, except at this point.
1175 */
1176 /*
1177 * Edge triggered needs to resend any interrupt
1178 * that was delayed but this is now handled in the device
1179 * independent code.
1180 */
1181
1182 /*
1183 * Starting up a edge-triggered IO-APIC interrupt is
1184 * nasty - we need to make sure that we get the edge.
1185 * If it is already asserted for some reason, we need
1186 * return 1 to indicate that is was pending.
1187 *
1188 * This is not complete - we should be able to fake
1189 * an edge even if it isn't on the 8259A...
1190 */
1191
1192 static unsigned int startup_ioapic_irq(unsigned int irq)
1193 {
1194 int was_pending = 0;
1195 unsigned long flags;
1196
1197 spin_lock_irqsave(&ioapic_lock, flags);
1198 if (irq < 16) {
1199 disable_8259A_irq(irq);
1200 if (i8259A_irq_pending(irq))
1201 was_pending = 1;
1202 }
1203 __unmask_IO_APIC_irq(irq);
1204 spin_unlock_irqrestore(&ioapic_lock, flags);
1205
1206 return was_pending;
1207 }
1208
1209 static int ioapic_retrigger_irq(unsigned int irq)
1210 {
1211 cpumask_t mask;
1212 unsigned vector;
1213
1214 vector = irq_vector[irq];
1215 cpus_clear(mask);
1216 cpu_set(vector >> 8, mask);
1217
1218 send_IPI_mask(mask, vector & 0xff);
1219
1220 return 1;
1221 }
1222
1223 /*
1224 * Level and edge triggered IO-APIC interrupts need different handling,
1225 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1226 * handled with the level-triggered descriptor, but that one has slightly
1227 * more overhead. Level-triggered interrupts cannot be handled with the
1228 * edge-triggered handler, without risking IRQ storms and other ugly
1229 * races.
1230 */
1231
1232 static void ack_apic_edge(unsigned int irq)
1233 {
1234 move_native_irq(irq);
1235 ack_APIC_irq();
1236 }
1237
1238 static void ack_apic_level(unsigned int irq)
1239 {
1240 int do_unmask_irq = 0;
1241
1242 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1243 /* If we are moving the irq we need to mask it */
1244 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1245 do_unmask_irq = 1;
1246 mask_IO_APIC_irq(irq);
1247 }
1248 #endif
1249
1250 /*
1251 * We must acknowledge the irq before we move it or the acknowledge will
1252 * not propogate properly.
1253 */
1254 ack_APIC_irq();
1255
1256 /* Now we can move and renable the irq */
1257 move_masked_irq(irq);
1258 if (unlikely(do_unmask_irq))
1259 unmask_IO_APIC_irq(irq);
1260 }
1261
1262 static struct irq_chip ioapic_chip __read_mostly = {
1263 .name = "IO-APIC",
1264 .startup = startup_ioapic_irq,
1265 .mask = mask_IO_APIC_irq,
1266 .unmask = unmask_IO_APIC_irq,
1267 .ack = ack_apic_edge,
1268 .eoi = ack_apic_level,
1269 #ifdef CONFIG_SMP
1270 .set_affinity = set_ioapic_affinity_irq,
1271 #endif
1272 .retrigger = ioapic_retrigger_irq,
1273 };
1274
1275 static inline void init_IO_APIC_traps(void)
1276 {
1277 int irq;
1278
1279 /*
1280 * NOTE! The local APIC isn't very good at handling
1281 * multiple interrupts at the same interrupt level.
1282 * As the interrupt level is determined by taking the
1283 * vector number and shifting that right by 4, we
1284 * want to spread these out a bit so that they don't
1285 * all fall in the same interrupt level.
1286 *
1287 * Also, we've got to be careful not to trash gate
1288 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1289 */
1290 for (irq = 0; irq < NR_IRQS ; irq++) {
1291 int tmp = irq;
1292 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1293 /*
1294 * Hmm.. We don't have an entry for this,
1295 * so default to an old-fashioned 8259
1296 * interrupt if we can..
1297 */
1298 if (irq < 16)
1299 make_8259A_irq(irq);
1300 else
1301 /* Strange. Oh, well.. */
1302 irq_desc[irq].chip = &no_irq_chip;
1303 }
1304 }
1305 }
1306
1307 static void enable_lapic_irq (unsigned int irq)
1308 {
1309 unsigned long v;
1310
1311 v = apic_read(APIC_LVT0);
1312 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1313 }
1314
1315 static void disable_lapic_irq (unsigned int irq)
1316 {
1317 unsigned long v;
1318
1319 v = apic_read(APIC_LVT0);
1320 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1321 }
1322
1323 static void ack_lapic_irq (unsigned int irq)
1324 {
1325 ack_APIC_irq();
1326 }
1327
1328 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1329
1330 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1331 .typename = "local-APIC-edge",
1332 .startup = NULL, /* startup_irq() not used for IRQ0 */
1333 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1334 .enable = enable_lapic_irq,
1335 .disable = disable_lapic_irq,
1336 .ack = ack_lapic_irq,
1337 .end = end_lapic_irq,
1338 };
1339
1340 static void setup_nmi (void)
1341 {
1342 /*
1343 * Dirty trick to enable the NMI watchdog ...
1344 * We put the 8259A master into AEOI mode and
1345 * unmask on all local APICs LVT0 as NMI.
1346 *
1347 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1348 * is from Maciej W. Rozycki - so we do not have to EOI from
1349 * the NMI handler or the timer interrupt.
1350 */
1351 printk(KERN_INFO "activating NMI Watchdog ...");
1352
1353 enable_NMI_through_LVT0(NULL);
1354
1355 printk(" done.\n");
1356 }
1357
1358 /*
1359 * This looks a bit hackish but it's about the only one way of sending
1360 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1361 * not support the ExtINT mode, unfortunately. We need to send these
1362 * cycles as some i82489DX-based boards have glue logic that keeps the
1363 * 8259A interrupt line asserted until INTA. --macro
1364 */
1365 static inline void unlock_ExtINT_logic(void)
1366 {
1367 int apic, pin, i;
1368 struct IO_APIC_route_entry entry0, entry1;
1369 unsigned char save_control, save_freq_select;
1370 unsigned long flags;
1371
1372 pin = find_isa_irq_pin(8, mp_INT);
1373 apic = find_isa_irq_apic(8, mp_INT);
1374 if (pin == -1)
1375 return;
1376
1377 spin_lock_irqsave(&ioapic_lock, flags);
1378 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1379 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1380 spin_unlock_irqrestore(&ioapic_lock, flags);
1381 clear_IO_APIC_pin(apic, pin);
1382
1383 memset(&entry1, 0, sizeof(entry1));
1384
1385 entry1.dest_mode = 0; /* physical delivery */
1386 entry1.mask = 0; /* unmask IRQ now */
1387 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1388 entry1.delivery_mode = dest_ExtINT;
1389 entry1.polarity = entry0.polarity;
1390 entry1.trigger = 0;
1391 entry1.vector = 0;
1392
1393 spin_lock_irqsave(&ioapic_lock, flags);
1394 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1395 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1396 spin_unlock_irqrestore(&ioapic_lock, flags);
1397
1398 save_control = CMOS_READ(RTC_CONTROL);
1399 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1400 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1401 RTC_FREQ_SELECT);
1402 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1403
1404 i = 100;
1405 while (i-- > 0) {
1406 mdelay(10);
1407 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1408 i -= 10;
1409 }
1410
1411 CMOS_WRITE(save_control, RTC_CONTROL);
1412 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1413 clear_IO_APIC_pin(apic, pin);
1414
1415 spin_lock_irqsave(&ioapic_lock, flags);
1416 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1417 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1418 spin_unlock_irqrestore(&ioapic_lock, flags);
1419 }
1420
1421 /*
1422 * This code may look a bit paranoid, but it's supposed to cooperate with
1423 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1424 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1425 * fanatically on his truly buggy board.
1426 *
1427 * FIXME: really need to revamp this for modern platforms only.
1428 */
1429 static inline void check_timer(void)
1430 {
1431 int apic1, pin1, apic2, pin2;
1432 int vector;
1433
1434 /*
1435 * get/set the timer IRQ vector:
1436 */
1437 disable_8259A_irq(0);
1438 vector = assign_irq_vector(0, TARGET_CPUS);
1439
1440 /*
1441 * Subtle, code in do_timer_interrupt() expects an AEOI
1442 * mode for the 8259A whenever interrupts are routed
1443 * through I/O APICs. Also IRQ0 has to be enabled in
1444 * the 8259A which implies the virtual wire has to be
1445 * disabled in the local APIC.
1446 */
1447 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1448 init_8259A(1);
1449 if (timer_over_8254 > 0)
1450 enable_8259A_irq(0);
1451
1452 pin1 = find_isa_irq_pin(0, mp_INT);
1453 apic1 = find_isa_irq_apic(0, mp_INT);
1454 pin2 = ioapic_i8259.pin;
1455 apic2 = ioapic_i8259.apic;
1456
1457 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1458 vector, apic1, pin1, apic2, pin2);
1459
1460 if (pin1 != -1) {
1461 /*
1462 * Ok, does IRQ0 through the IOAPIC work?
1463 */
1464 unmask_IO_APIC_irq(0);
1465 if (!no_timer_check && timer_irq_works()) {
1466 nmi_watchdog_default();
1467 if (nmi_watchdog == NMI_IO_APIC) {
1468 disable_8259A_irq(0);
1469 setup_nmi();
1470 enable_8259A_irq(0);
1471 }
1472 if (disable_timer_pin_1 > 0)
1473 clear_IO_APIC_pin(0, pin1);
1474 return;
1475 }
1476 clear_IO_APIC_pin(apic1, pin1);
1477 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1478 "connected to IO-APIC\n");
1479 }
1480
1481 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1482 "through the 8259A ... ");
1483 if (pin2 != -1) {
1484 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1485 apic2, pin2);
1486 /*
1487 * legacy devices should be connected to IO APIC #0
1488 */
1489 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1490 if (timer_irq_works()) {
1491 apic_printk(APIC_VERBOSE," works.\n");
1492 nmi_watchdog_default();
1493 if (nmi_watchdog == NMI_IO_APIC) {
1494 setup_nmi();
1495 }
1496 return;
1497 }
1498 /*
1499 * Cleanup, just in case ...
1500 */
1501 clear_IO_APIC_pin(apic2, pin2);
1502 }
1503 apic_printk(APIC_VERBOSE," failed.\n");
1504
1505 if (nmi_watchdog == NMI_IO_APIC) {
1506 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1507 nmi_watchdog = 0;
1508 }
1509
1510 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1511
1512 disable_8259A_irq(0);
1513 irq_desc[0].chip = &lapic_irq_type;
1514 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1515 enable_8259A_irq(0);
1516
1517 if (timer_irq_works()) {
1518 apic_printk(APIC_VERBOSE," works.\n");
1519 return;
1520 }
1521 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1522 apic_printk(APIC_VERBOSE," failed.\n");
1523
1524 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1525
1526 init_8259A(0);
1527 make_8259A_irq(0);
1528 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1529
1530 unlock_ExtINT_logic();
1531
1532 if (timer_irq_works()) {
1533 apic_printk(APIC_VERBOSE," works.\n");
1534 return;
1535 }
1536 apic_printk(APIC_VERBOSE," failed :(.\n");
1537 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1538 }
1539
1540 static int __init notimercheck(char *s)
1541 {
1542 no_timer_check = 1;
1543 return 1;
1544 }
1545 __setup("no_timer_check", notimercheck);
1546
1547 /*
1548 *
1549 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1550 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1551 * Linux doesn't really care, as it's not actually used
1552 * for any interrupt handling anyway.
1553 */
1554 #define PIC_IRQS (1<<2)
1555
1556 void __init setup_IO_APIC(void)
1557 {
1558 enable_IO_APIC();
1559
1560 if (acpi_ioapic)
1561 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1562 else
1563 io_apic_irqs = ~PIC_IRQS;
1564
1565 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1566
1567 sync_Arb_IDs();
1568 setup_IO_APIC_irqs();
1569 init_IO_APIC_traps();
1570 check_timer();
1571 if (!acpi_ioapic)
1572 print_IO_APIC();
1573 }
1574
1575 struct sysfs_ioapic_data {
1576 struct sys_device dev;
1577 struct IO_APIC_route_entry entry[0];
1578 };
1579 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1580
1581 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1582 {
1583 struct IO_APIC_route_entry *entry;
1584 struct sysfs_ioapic_data *data;
1585 int i;
1586
1587 data = container_of(dev, struct sysfs_ioapic_data, dev);
1588 entry = data->entry;
1589 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1590 *entry = ioapic_read_entry(dev->id, i);
1591
1592 return 0;
1593 }
1594
1595 static int ioapic_resume(struct sys_device *dev)
1596 {
1597 struct IO_APIC_route_entry *entry;
1598 struct sysfs_ioapic_data *data;
1599 unsigned long flags;
1600 union IO_APIC_reg_00 reg_00;
1601 int i;
1602
1603 data = container_of(dev, struct sysfs_ioapic_data, dev);
1604 entry = data->entry;
1605
1606 spin_lock_irqsave(&ioapic_lock, flags);
1607 reg_00.raw = io_apic_read(dev->id, 0);
1608 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1609 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1610 io_apic_write(dev->id, 0, reg_00.raw);
1611 }
1612 spin_unlock_irqrestore(&ioapic_lock, flags);
1613 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1614 ioapic_write_entry(dev->id, i, entry[i]);
1615
1616 return 0;
1617 }
1618
1619 static struct sysdev_class ioapic_sysdev_class = {
1620 set_kset_name("ioapic"),
1621 .suspend = ioapic_suspend,
1622 .resume = ioapic_resume,
1623 };
1624
1625 static int __init ioapic_init_sysfs(void)
1626 {
1627 struct sys_device * dev;
1628 int i, size, error = 0;
1629
1630 error = sysdev_class_register(&ioapic_sysdev_class);
1631 if (error)
1632 return error;
1633
1634 for (i = 0; i < nr_ioapics; i++ ) {
1635 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1636 * sizeof(struct IO_APIC_route_entry);
1637 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1638 if (!mp_ioapic_data[i]) {
1639 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1640 continue;
1641 }
1642 memset(mp_ioapic_data[i], 0, size);
1643 dev = &mp_ioapic_data[i]->dev;
1644 dev->id = i;
1645 dev->cls = &ioapic_sysdev_class;
1646 error = sysdev_register(dev);
1647 if (error) {
1648 kfree(mp_ioapic_data[i]);
1649 mp_ioapic_data[i] = NULL;
1650 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1651 continue;
1652 }
1653 }
1654
1655 return 0;
1656 }
1657
1658 device_initcall(ioapic_init_sysfs);
1659
1660 /*
1661 * Dynamic irq allocate and deallocation
1662 */
1663 int create_irq(void)
1664 {
1665 /* Allocate an unused irq */
1666 int irq;
1667 int new;
1668 int vector = 0;
1669 unsigned long flags;
1670
1671 irq = -ENOSPC;
1672 spin_lock_irqsave(&vector_lock, flags);
1673 for (new = (NR_IRQS - 1); new >= 0; new--) {
1674 if (platform_legacy_irq(new))
1675 continue;
1676 if (irq_vector[new] != 0)
1677 continue;
1678 vector = __assign_irq_vector(new, TARGET_CPUS);
1679 if (likely(vector > 0))
1680 irq = new;
1681 break;
1682 }
1683 spin_unlock_irqrestore(&vector_lock, flags);
1684
1685 if (irq >= 0) {
1686 dynamic_irq_init(irq);
1687 }
1688 return irq;
1689 }
1690
1691 void destroy_irq(unsigned int irq)
1692 {
1693 unsigned long flags;
1694
1695 dynamic_irq_cleanup(irq);
1696
1697 spin_lock_irqsave(&vector_lock, flags);
1698 irq_vector[irq] = 0;
1699 spin_unlock_irqrestore(&vector_lock, flags);
1700 }
1701
1702 /*
1703 * MSI mesage composition
1704 */
1705 #ifdef CONFIG_PCI_MSI
1706 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1707 {
1708 int vector;
1709 unsigned dest;
1710
1711 vector = assign_irq_vector(irq, TARGET_CPUS);
1712 if (vector >= 0) {
1713 cpumask_t tmp;
1714
1715 cpus_clear(tmp);
1716 cpu_set(vector >> 8, tmp);
1717 dest = cpu_mask_to_apicid(tmp);
1718
1719 msg->address_hi = MSI_ADDR_BASE_HI;
1720 msg->address_lo =
1721 MSI_ADDR_BASE_LO |
1722 ((INT_DEST_MODE == 0) ?
1723 MSI_ADDR_DEST_MODE_PHYSICAL:
1724 MSI_ADDR_DEST_MODE_LOGICAL) |
1725 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1726 MSI_ADDR_REDIRECTION_CPU:
1727 MSI_ADDR_REDIRECTION_LOWPRI) |
1728 MSI_ADDR_DEST_ID(dest);
1729
1730 msg->data =
1731 MSI_DATA_TRIGGER_EDGE |
1732 MSI_DATA_LEVEL_ASSERT |
1733 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1734 MSI_DATA_DELIVERY_FIXED:
1735 MSI_DATA_DELIVERY_LOWPRI) |
1736 MSI_DATA_VECTOR(vector);
1737 }
1738 return vector;
1739 }
1740
1741 #ifdef CONFIG_SMP
1742 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1743 {
1744 struct msi_msg msg;
1745 unsigned int dest;
1746 cpumask_t tmp;
1747 int vector;
1748
1749 cpus_and(tmp, mask, cpu_online_map);
1750 if (cpus_empty(tmp))
1751 tmp = TARGET_CPUS;
1752
1753 cpus_and(mask, tmp, CPU_MASK_ALL);
1754
1755 vector = assign_irq_vector(irq, mask);
1756 if (vector < 0)
1757 return;
1758
1759 cpus_clear(tmp);
1760 cpu_set(vector >> 8, tmp);
1761 dest = cpu_mask_to_apicid(tmp);
1762
1763 read_msi_msg(irq, &msg);
1764
1765 msg.data &= ~MSI_DATA_VECTOR_MASK;
1766 msg.data |= MSI_DATA_VECTOR(vector);
1767 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1768 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1769
1770 write_msi_msg(irq, &msg);
1771 set_native_irq_info(irq, mask);
1772 }
1773 #endif /* CONFIG_SMP */
1774
1775 /*
1776 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1777 * which implement the MSI or MSI-X Capability Structure.
1778 */
1779 static struct irq_chip msi_chip = {
1780 .name = "PCI-MSI",
1781 .unmask = unmask_msi_irq,
1782 .mask = mask_msi_irq,
1783 .ack = ack_apic_edge,
1784 #ifdef CONFIG_SMP
1785 .set_affinity = set_msi_irq_affinity,
1786 #endif
1787 .retrigger = ioapic_retrigger_irq,
1788 };
1789
1790 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1791 {
1792 struct msi_msg msg;
1793 int ret;
1794 ret = msi_compose_msg(dev, irq, &msg);
1795 if (ret < 0)
1796 return ret;
1797
1798 write_msi_msg(irq, &msg);
1799
1800 set_irq_chip_and_handler(irq, &msi_chip, handle_edge_irq);
1801
1802 return 0;
1803 }
1804
1805 void arch_teardown_msi_irq(unsigned int irq)
1806 {
1807 return;
1808 }
1809
1810 #endif /* CONFIG_PCI_MSI */
1811
1812 /*
1813 * Hypertransport interrupt support
1814 */
1815 #ifdef CONFIG_HT_IRQ
1816
1817 #ifdef CONFIG_SMP
1818
1819 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1820 {
1821 u32 low, high;
1822 low = read_ht_irq_low(irq);
1823 high = read_ht_irq_high(irq);
1824
1825 low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1826 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1827
1828 low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1829 high |= HT_IRQ_HIGH_DEST_ID(dest);
1830
1831 write_ht_irq_low(irq, low);
1832 write_ht_irq_high(irq, high);
1833 }
1834
1835 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1836 {
1837 unsigned int dest;
1838 cpumask_t tmp;
1839 int vector;
1840
1841 cpus_and(tmp, mask, cpu_online_map);
1842 if (cpus_empty(tmp))
1843 tmp = TARGET_CPUS;
1844
1845 cpus_and(mask, tmp, CPU_MASK_ALL);
1846
1847 vector = assign_irq_vector(irq, mask);
1848 if (vector < 0)
1849 return;
1850
1851 cpus_clear(tmp);
1852 cpu_set(vector >> 8, tmp);
1853 dest = cpu_mask_to_apicid(tmp);
1854
1855 target_ht_irq(irq, dest, vector & 0xff);
1856 set_native_irq_info(irq, mask);
1857 }
1858 #endif
1859
1860 static struct hw_interrupt_type ht_irq_chip = {
1861 .name = "PCI-HT",
1862 .mask = mask_ht_irq,
1863 .unmask = unmask_ht_irq,
1864 .ack = ack_apic_edge,
1865 #ifdef CONFIG_SMP
1866 .set_affinity = set_ht_irq_affinity,
1867 #endif
1868 .retrigger = ioapic_retrigger_irq,
1869 };
1870
1871 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1872 {
1873 int vector;
1874
1875 vector = assign_irq_vector(irq, TARGET_CPUS);
1876 if (vector >= 0) {
1877 u32 low, high;
1878 unsigned dest;
1879 cpumask_t tmp;
1880
1881 cpus_clear(tmp);
1882 cpu_set(vector >> 8, tmp);
1883 dest = cpu_mask_to_apicid(tmp);
1884
1885 high = HT_IRQ_HIGH_DEST_ID(dest);
1886
1887 low = HT_IRQ_LOW_BASE |
1888 HT_IRQ_LOW_DEST_ID(dest) |
1889 HT_IRQ_LOW_VECTOR(vector) |
1890 ((INT_DEST_MODE == 0) ?
1891 HT_IRQ_LOW_DM_PHYSICAL :
1892 HT_IRQ_LOW_DM_LOGICAL) |
1893 HT_IRQ_LOW_RQEOI_EDGE |
1894 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1895 HT_IRQ_LOW_MT_FIXED :
1896 HT_IRQ_LOW_MT_ARBITRATED);
1897
1898 write_ht_irq_low(irq, low);
1899 write_ht_irq_high(irq, high);
1900
1901 set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);
1902 }
1903 return vector;
1904 }
1905 #endif /* CONFIG_HT_IRQ */
1906
1907 /* --------------------------------------------------------------------------
1908 ACPI-based IOAPIC Configuration
1909 -------------------------------------------------------------------------- */
1910
1911 #ifdef CONFIG_ACPI
1912
1913 #define IO_APIC_MAX_ID 0xFE
1914
1915 int __init io_apic_get_redir_entries (int ioapic)
1916 {
1917 union IO_APIC_reg_01 reg_01;
1918 unsigned long flags;
1919
1920 spin_lock_irqsave(&ioapic_lock, flags);
1921 reg_01.raw = io_apic_read(ioapic, 1);
1922 spin_unlock_irqrestore(&ioapic_lock, flags);
1923
1924 return reg_01.bits.entries;
1925 }
1926
1927
1928 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1929 {
1930 struct IO_APIC_route_entry entry;
1931 unsigned long flags;
1932 int vector;
1933 cpumask_t mask;
1934
1935 if (!IO_APIC_IRQ(irq)) {
1936 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1937 ioapic);
1938 return -EINVAL;
1939 }
1940
1941 /*
1942 * IRQs < 16 are already in the irq_2_pin[] map
1943 */
1944 if (irq >= 16)
1945 add_pin_to_irq(irq, ioapic, pin);
1946
1947
1948 vector = assign_irq_vector(irq, TARGET_CPUS);
1949 if (vector < 0)
1950 return vector;
1951
1952 cpus_clear(mask);
1953 cpu_set(vector >> 8, mask);
1954
1955 /*
1956 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1957 * Note that we mask (disable) IRQs now -- these get enabled when the
1958 * corresponding device driver registers for this IRQ.
1959 */
1960
1961 memset(&entry,0,sizeof(entry));
1962
1963 entry.delivery_mode = INT_DELIVERY_MODE;
1964 entry.dest_mode = INT_DEST_MODE;
1965 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
1966 entry.trigger = triggering;
1967 entry.polarity = polarity;
1968 entry.mask = 1; /* Disabled (masked) */
1969 entry.vector = vector & 0xff;
1970
1971 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1972 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1973 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1974 triggering, polarity);
1975
1976 ioapic_register_intr(irq, entry.vector, triggering);
1977
1978 if (!ioapic && (irq < 16))
1979 disable_8259A_irq(irq);
1980
1981 ioapic_write_entry(ioapic, pin, entry);
1982
1983 spin_lock_irqsave(&ioapic_lock, flags);
1984 set_native_irq_info(irq, TARGET_CPUS);
1985 spin_unlock_irqrestore(&ioapic_lock, flags);
1986
1987 return 0;
1988 }
1989
1990 #endif /* CONFIG_ACPI */
1991
1992
1993 /*
1994 * This function currently is only a helper for the i386 smp boot process where
1995 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1996 * so mask in all cases should simply be TARGET_CPUS
1997 */
1998 #ifdef CONFIG_SMP
1999 void __init setup_ioapic_dest(void)
2000 {
2001 int pin, ioapic, irq, irq_entry;
2002
2003 if (skip_ioapic_setup == 1)
2004 return;
2005
2006 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2007 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2008 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2009 if (irq_entry == -1)
2010 continue;
2011 irq = pin_2_irq(irq_entry, ioapic, pin);
2012 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2013 }
2014
2015 }
2016 }
2017 #endif
Linux kernel - Deliverables
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