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[PATCH] msi: refactor and move the msi irq_chip into the arch code
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #ifdef CONFIG_ACPI
35 #include <acpi/acpi_bus.h>
36 #endif
37
38 #include <asm/io.h>
39 #include <asm/smp.h>
40 #include <asm/desc.h>
41 #include <asm/proto.h>
42 #include <asm/mach_apic.h>
43 #include <asm/acpi.h>
44 #include <asm/dma.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 static int assign_irq_vector(int irq, cpumask_t mask);
50
51 #define __apicdebuginit __init
52
53 int sis_apic_bug; /* not actually supported, dummy for compile */
54
55 static int no_timer_check;
56
57 static int disable_timer_pin_1 __initdata;
58
59 int timer_over_8254 __initdata = 0;
60
61 /* Where if anywhere is the i8259 connect in external int mode */
62 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
63
64 static DEFINE_SPINLOCK(ioapic_lock);
65 static DEFINE_SPINLOCK(vector_lock);
66
67 /*
68 * # of IRQ routing registers
69 */
70 int nr_ioapic_registers[MAX_IO_APICS];
71
72 /*
73 * Rough estimation of how many shared IRQs there are, can
74 * be changed anytime.
75 */
76 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
77 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
78
79 /*
80 * This is performance-critical, we want to do it O(1)
81 *
82 * the indexing order of this array favors 1:1 mappings
83 * between pins and IRQs.
84 */
85
86 static struct irq_pin_list {
87 short apic, pin, next;
88 } irq_2_pin[PIN_MAP_SIZE];
89
90 #define __DO_ACTION(R, ACTION, FINAL) \
91 \
92 { \
93 int pin; \
94 struct irq_pin_list *entry = irq_2_pin + irq; \
95 \
96 BUG_ON(irq >= NR_IRQS); \
97 for (;;) { \
98 unsigned int reg; \
99 pin = entry->pin; \
100 if (pin == -1) \
101 break; \
102 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
103 reg ACTION; \
104 io_apic_modify(entry->apic, reg); \
105 if (!entry->next) \
106 break; \
107 entry = irq_2_pin + entry->next; \
108 } \
109 FINAL; \
110 }
111
112 union entry_union {
113 struct { u32 w1, w2; };
114 struct IO_APIC_route_entry entry;
115 };
116
117 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
118 {
119 union entry_union eu;
120 unsigned long flags;
121 spin_lock_irqsave(&ioapic_lock, flags);
122 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
123 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
124 spin_unlock_irqrestore(&ioapic_lock, flags);
125 return eu.entry;
126 }
127
128 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
129 {
130 unsigned long flags;
131 union entry_union eu;
132 eu.entry = e;
133 spin_lock_irqsave(&ioapic_lock, flags);
134 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
135 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
136 spin_unlock_irqrestore(&ioapic_lock, flags);
137 }
138
139 #ifdef CONFIG_SMP
140 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
141 {
142 int apic, pin;
143 struct irq_pin_list *entry = irq_2_pin + irq;
144
145 BUG_ON(irq >= NR_IRQS);
146 for (;;) {
147 unsigned int reg;
148 apic = entry->apic;
149 pin = entry->pin;
150 if (pin == -1)
151 break;
152 io_apic_write(apic, 0x11 + pin*2, dest);
153 reg = io_apic_read(apic, 0x10 + pin*2);
154 reg &= ~0x000000ff;
155 reg |= vector;
156 io_apic_modify(apic, reg);
157 if (!entry->next)
158 break;
159 entry = irq_2_pin + entry->next;
160 }
161 }
162
163 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
164 {
165 unsigned long flags;
166 unsigned int dest;
167 cpumask_t tmp;
168 int vector;
169
170 cpus_and(tmp, mask, cpu_online_map);
171 if (cpus_empty(tmp))
172 tmp = TARGET_CPUS;
173
174 cpus_and(mask, tmp, CPU_MASK_ALL);
175
176 vector = assign_irq_vector(irq, mask);
177 if (vector < 0)
178 return;
179
180 cpus_clear(tmp);
181 cpu_set(vector >> 8, tmp);
182 dest = cpu_mask_to_apicid(tmp);
183
184 /*
185 * Only the high 8 bits are valid.
186 */
187 dest = SET_APIC_LOGICAL_ID(dest);
188
189 spin_lock_irqsave(&ioapic_lock, flags);
190 __target_IO_APIC_irq(irq, dest, vector & 0xff);
191 set_native_irq_info(irq, mask);
192 spin_unlock_irqrestore(&ioapic_lock, flags);
193 }
194 #endif
195
196 /*
197 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
198 * shared ISA-space IRQs, so we have to support them. We are super
199 * fast in the common case, and fast for shared ISA-space IRQs.
200 */
201 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
202 {
203 static int first_free_entry = NR_IRQS;
204 struct irq_pin_list *entry = irq_2_pin + irq;
205
206 BUG_ON(irq >= NR_IRQS);
207 while (entry->next)
208 entry = irq_2_pin + entry->next;
209
210 if (entry->pin != -1) {
211 entry->next = first_free_entry;
212 entry = irq_2_pin + entry->next;
213 if (++first_free_entry >= PIN_MAP_SIZE)
214 panic("io_apic.c: ran out of irq_2_pin entries!");
215 }
216 entry->apic = apic;
217 entry->pin = pin;
218 }
219
220
221 #define DO_ACTION(name,R,ACTION, FINAL) \
222 \
223 static void name##_IO_APIC_irq (unsigned int irq) \
224 __DO_ACTION(R, ACTION, FINAL)
225
226 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
227 /* mask = 1 */
228 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
229 /* mask = 0 */
230
231 static void mask_IO_APIC_irq (unsigned int irq)
232 {
233 unsigned long flags;
234
235 spin_lock_irqsave(&ioapic_lock, flags);
236 __mask_IO_APIC_irq(irq);
237 spin_unlock_irqrestore(&ioapic_lock, flags);
238 }
239
240 static void unmask_IO_APIC_irq (unsigned int irq)
241 {
242 unsigned long flags;
243
244 spin_lock_irqsave(&ioapic_lock, flags);
245 __unmask_IO_APIC_irq(irq);
246 spin_unlock_irqrestore(&ioapic_lock, flags);
247 }
248
249 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
250 {
251 struct IO_APIC_route_entry entry;
252
253 /* Check delivery_mode to be sure we're not clearing an SMI pin */
254 entry = ioapic_read_entry(apic, pin);
255 if (entry.delivery_mode == dest_SMI)
256 return;
257 /*
258 * Disable it in the IO-APIC irq-routing table:
259 */
260 memset(&entry, 0, sizeof(entry));
261 entry.mask = 1;
262 ioapic_write_entry(apic, pin, entry);
263 }
264
265 static void clear_IO_APIC (void)
266 {
267 int apic, pin;
268
269 for (apic = 0; apic < nr_ioapics; apic++)
270 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
271 clear_IO_APIC_pin(apic, pin);
272 }
273
274 int skip_ioapic_setup;
275 int ioapic_force;
276
277 /* dummy parsing: see setup.c */
278
279 static int __init disable_ioapic_setup(char *str)
280 {
281 skip_ioapic_setup = 1;
282 return 0;
283 }
284 early_param("noapic", disable_ioapic_setup);
285
286 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
287 static int __init disable_timer_pin_setup(char *arg)
288 {
289 disable_timer_pin_1 = 1;
290 return 1;
291 }
292 __setup("disable_timer_pin_1", disable_timer_pin_setup);
293
294 static int __init setup_disable_8254_timer(char *s)
295 {
296 timer_over_8254 = -1;
297 return 1;
298 }
299 static int __init setup_enable_8254_timer(char *s)
300 {
301 timer_over_8254 = 2;
302 return 1;
303 }
304
305 __setup("disable_8254_timer", setup_disable_8254_timer);
306 __setup("enable_8254_timer", setup_enable_8254_timer);
307
308
309 /*
310 * Find the IRQ entry number of a certain pin.
311 */
312 static int find_irq_entry(int apic, int pin, int type)
313 {
314 int i;
315
316 for (i = 0; i < mp_irq_entries; i++)
317 if (mp_irqs[i].mpc_irqtype == type &&
318 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
319 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
320 mp_irqs[i].mpc_dstirq == pin)
321 return i;
322
323 return -1;
324 }
325
326 /*
327 * Find the pin to which IRQ[irq] (ISA) is connected
328 */
329 static int __init find_isa_irq_pin(int irq, int type)
330 {
331 int i;
332
333 for (i = 0; i < mp_irq_entries; i++) {
334 int lbus = mp_irqs[i].mpc_srcbus;
335
336 if (test_bit(lbus, mp_bus_not_pci) &&
337 (mp_irqs[i].mpc_irqtype == type) &&
338 (mp_irqs[i].mpc_srcbusirq == irq))
339
340 return mp_irqs[i].mpc_dstirq;
341 }
342 return -1;
343 }
344
345 static int __init find_isa_irq_apic(int irq, int type)
346 {
347 int i;
348
349 for (i = 0; i < mp_irq_entries; i++) {
350 int lbus = mp_irqs[i].mpc_srcbus;
351
352 if (test_bit(lbus, mp_bus_not_pci) &&
353 (mp_irqs[i].mpc_irqtype == type) &&
354 (mp_irqs[i].mpc_srcbusirq == irq))
355 break;
356 }
357 if (i < mp_irq_entries) {
358 int apic;
359 for(apic = 0; apic < nr_ioapics; apic++) {
360 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
361 return apic;
362 }
363 }
364
365 return -1;
366 }
367
368 /*
369 * Find a specific PCI IRQ entry.
370 * Not an __init, possibly needed by modules
371 */
372 static int pin_2_irq(int idx, int apic, int pin);
373
374 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
375 {
376 int apic, i, best_guess = -1;
377
378 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
379 bus, slot, pin);
380 if (mp_bus_id_to_pci_bus[bus] == -1) {
381 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
382 return -1;
383 }
384 for (i = 0; i < mp_irq_entries; i++) {
385 int lbus = mp_irqs[i].mpc_srcbus;
386
387 for (apic = 0; apic < nr_ioapics; apic++)
388 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
389 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
390 break;
391
392 if (!test_bit(lbus, mp_bus_not_pci) &&
393 !mp_irqs[i].mpc_irqtype &&
394 (bus == lbus) &&
395 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
396 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
397
398 if (!(apic || IO_APIC_IRQ(irq)))
399 continue;
400
401 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
402 return irq;
403 /*
404 * Use the first all-but-pin matching entry as a
405 * best-guess fuzzy result for broken mptables.
406 */
407 if (best_guess < 0)
408 best_guess = irq;
409 }
410 }
411 BUG_ON(best_guess >= NR_IRQS);
412 return best_guess;
413 }
414
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
417
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
420
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
423
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
426
427 static int __init MPBIOS_polarity(int idx)
428 {
429 int bus = mp_irqs[idx].mpc_srcbus;
430 int polarity;
431
432 /*
433 * Determine IRQ line polarity (high active or low active):
434 */
435 switch (mp_irqs[idx].mpc_irqflag & 3)
436 {
437 case 0: /* conforms, ie. bus-type dependent polarity */
438 if (test_bit(bus, mp_bus_not_pci))
439 polarity = default_ISA_polarity(idx);
440 else
441 polarity = default_PCI_polarity(idx);
442 break;
443 case 1: /* high active */
444 {
445 polarity = 0;
446 break;
447 }
448 case 2: /* reserved */
449 {
450 printk(KERN_WARNING "broken BIOS!!\n");
451 polarity = 1;
452 break;
453 }
454 case 3: /* low active */
455 {
456 polarity = 1;
457 break;
458 }
459 default: /* invalid */
460 {
461 printk(KERN_WARNING "broken BIOS!!\n");
462 polarity = 1;
463 break;
464 }
465 }
466 return polarity;
467 }
468
469 static int MPBIOS_trigger(int idx)
470 {
471 int bus = mp_irqs[idx].mpc_srcbus;
472 int trigger;
473
474 /*
475 * Determine IRQ trigger mode (edge or level sensitive):
476 */
477 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
478 {
479 case 0: /* conforms, ie. bus-type dependent */
480 if (test_bit(bus, mp_bus_not_pci))
481 trigger = default_ISA_trigger(idx);
482 else
483 trigger = default_PCI_trigger(idx);
484 break;
485 case 1: /* edge */
486 {
487 trigger = 0;
488 break;
489 }
490 case 2: /* reserved */
491 {
492 printk(KERN_WARNING "broken BIOS!!\n");
493 trigger = 1;
494 break;
495 }
496 case 3: /* level */
497 {
498 trigger = 1;
499 break;
500 }
501 default: /* invalid */
502 {
503 printk(KERN_WARNING "broken BIOS!!\n");
504 trigger = 0;
505 break;
506 }
507 }
508 return trigger;
509 }
510
511 static inline int irq_polarity(int idx)
512 {
513 return MPBIOS_polarity(idx);
514 }
515
516 static inline int irq_trigger(int idx)
517 {
518 return MPBIOS_trigger(idx);
519 }
520
521 static int pin_2_irq(int idx, int apic, int pin)
522 {
523 int irq, i;
524 int bus = mp_irqs[idx].mpc_srcbus;
525
526 /*
527 * Debugging check, we are in big trouble if this message pops up!
528 */
529 if (mp_irqs[idx].mpc_dstirq != pin)
530 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
531
532 if (test_bit(bus, mp_bus_not_pci)) {
533 irq = mp_irqs[idx].mpc_srcbusirq;
534 } else {
535 /*
536 * PCI IRQs are mapped in order
537 */
538 i = irq = 0;
539 while (i < apic)
540 irq += nr_ioapic_registers[i++];
541 irq += pin;
542 }
543 BUG_ON(irq >= NR_IRQS);
544 return irq;
545 }
546
547 static inline int IO_APIC_irq_trigger(int irq)
548 {
549 int apic, idx, pin;
550
551 for (apic = 0; apic < nr_ioapics; apic++) {
552 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
553 idx = find_irq_entry(apic,pin,mp_INT);
554 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
555 return irq_trigger(idx);
556 }
557 }
558 /*
559 * nonexistent IRQs are edge default
560 */
561 return 0;
562 }
563
564 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
565 unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 };
566
567 static int __assign_irq_vector(int irq, cpumask_t mask)
568 {
569 /*
570 * NOTE! The local APIC isn't very good at handling
571 * multiple interrupts at the same interrupt level.
572 * As the interrupt level is determined by taking the
573 * vector number and shifting that right by 4, we
574 * want to spread these out a bit so that they don't
575 * all fall in the same interrupt level.
576 *
577 * Also, we've got to be careful not to trash gate
578 * 0x80, because int 0x80 is hm, kind of importantish. ;)
579 */
580 static struct {
581 int vector;
582 int offset;
583 } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
584 int old_vector = -1;
585 int cpu;
586
587 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
588
589 if (IO_APIC_VECTOR(irq) > 0)
590 old_vector = IO_APIC_VECTOR(irq);
591 if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) {
592 return old_vector;
593 }
594
595 for_each_cpu_mask(cpu, mask) {
596 int vector, offset;
597 vector = pos[cpu].vector;
598 offset = pos[cpu].offset;
599 next:
600 vector += 8;
601 if (vector >= FIRST_SYSTEM_VECTOR) {
602 /* If we run out of vectors on large boxen, must share them. */
603 offset = (offset + 1) % 8;
604 vector = FIRST_DEVICE_VECTOR + offset;
605 }
606 if (unlikely(pos[cpu].vector == vector))
607 continue;
608 if (vector == IA32_SYSCALL_VECTOR)
609 goto next;
610 if (per_cpu(vector_irq, cpu)[vector] != -1)
611 goto next;
612 /* Found one! */
613 pos[cpu].vector = vector;
614 pos[cpu].offset = offset;
615 if (old_vector >= 0) {
616 int old_cpu = old_vector >> 8;
617 old_vector &= 0xff;
618 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
619 }
620 per_cpu(vector_irq, cpu)[vector] = irq;
621 vector |= cpu << 8;
622 IO_APIC_VECTOR(irq) = vector;
623 return vector;
624 }
625 return -ENOSPC;
626 }
627
628 static int assign_irq_vector(int irq, cpumask_t mask)
629 {
630 int vector;
631 unsigned long flags;
632
633 spin_lock_irqsave(&vector_lock, flags);
634 vector = __assign_irq_vector(irq, mask);
635 spin_unlock_irqrestore(&vector_lock, flags);
636 return vector;
637 }
638
639 extern void (*interrupt[NR_IRQS])(void);
640
641 static struct irq_chip ioapic_chip;
642
643 #define IOAPIC_AUTO -1
644 #define IOAPIC_EDGE 0
645 #define IOAPIC_LEVEL 1
646
647 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
648 {
649 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
650 trigger == IOAPIC_LEVEL)
651 set_irq_chip_and_handler(irq, &ioapic_chip,
652 handle_fasteoi_irq);
653 else
654 set_irq_chip_and_handler(irq, &ioapic_chip,
655 handle_edge_irq);
656 }
657
658 static void __init setup_IO_APIC_irqs(void)
659 {
660 struct IO_APIC_route_entry entry;
661 int apic, pin, idx, irq, first_notcon = 1, vector;
662 unsigned long flags;
663
664 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
665
666 for (apic = 0; apic < nr_ioapics; apic++) {
667 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
668
669 /*
670 * add it to the IO-APIC irq-routing table:
671 */
672 memset(&entry,0,sizeof(entry));
673
674 entry.delivery_mode = INT_DELIVERY_MODE;
675 entry.dest_mode = INT_DEST_MODE;
676 entry.mask = 0; /* enable IRQ */
677 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
678
679 idx = find_irq_entry(apic,pin,mp_INT);
680 if (idx == -1) {
681 if (first_notcon) {
682 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
683 first_notcon = 0;
684 } else
685 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
686 continue;
687 }
688
689 entry.trigger = irq_trigger(idx);
690 entry.polarity = irq_polarity(idx);
691
692 if (irq_trigger(idx)) {
693 entry.trigger = 1;
694 entry.mask = 1;
695 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
696 }
697
698 irq = pin_2_irq(idx, apic, pin);
699 add_pin_to_irq(irq, apic, pin);
700
701 if (!apic && !IO_APIC_IRQ(irq))
702 continue;
703
704 if (IO_APIC_IRQ(irq)) {
705 cpumask_t mask;
706 vector = assign_irq_vector(irq, TARGET_CPUS);
707 if (vector < 0)
708 continue;
709
710 cpus_clear(mask);
711 cpu_set(vector >> 8, mask);
712 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
713 entry.vector = vector & 0xff;
714
715 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
716 if (!apic && (irq < 16))
717 disable_8259A_irq(irq);
718 }
719 ioapic_write_entry(apic, pin, entry);
720
721 spin_lock_irqsave(&ioapic_lock, flags);
722 set_native_irq_info(irq, TARGET_CPUS);
723 spin_unlock_irqrestore(&ioapic_lock, flags);
724 }
725 }
726
727 if (!first_notcon)
728 apic_printk(APIC_VERBOSE," not connected.\n");
729 }
730
731 /*
732 * Set up the 8259A-master output pin as broadcast to all
733 * CPUs.
734 */
735 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
736 {
737 struct IO_APIC_route_entry entry;
738 unsigned long flags;
739
740 memset(&entry,0,sizeof(entry));
741
742 disable_8259A_irq(0);
743
744 /* mask LVT0 */
745 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
746
747 /*
748 * We use logical delivery to get the timer IRQ
749 * to the first CPU.
750 */
751 entry.dest_mode = INT_DEST_MODE;
752 entry.mask = 0; /* unmask IRQ now */
753 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
754 entry.delivery_mode = INT_DELIVERY_MODE;
755 entry.polarity = 0;
756 entry.trigger = 0;
757 entry.vector = vector;
758
759 /*
760 * The timer IRQ doesn't have to know that behind the
761 * scene we have a 8259A-master in AEOI mode ...
762 */
763 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
764
765 /*
766 * Add it to the IO-APIC irq-routing table:
767 */
768 spin_lock_irqsave(&ioapic_lock, flags);
769 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
770 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
771 spin_unlock_irqrestore(&ioapic_lock, flags);
772
773 enable_8259A_irq(0);
774 }
775
776 void __init UNEXPECTED_IO_APIC(void)
777 {
778 }
779
780 void __apicdebuginit print_IO_APIC(void)
781 {
782 int apic, i;
783 union IO_APIC_reg_00 reg_00;
784 union IO_APIC_reg_01 reg_01;
785 union IO_APIC_reg_02 reg_02;
786 unsigned long flags;
787
788 if (apic_verbosity == APIC_QUIET)
789 return;
790
791 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
792 for (i = 0; i < nr_ioapics; i++)
793 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
794 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
795
796 /*
797 * We are a bit conservative about what we expect. We have to
798 * know about every hardware change ASAP.
799 */
800 printk(KERN_INFO "testing the IO APIC.......................\n");
801
802 for (apic = 0; apic < nr_ioapics; apic++) {
803
804 spin_lock_irqsave(&ioapic_lock, flags);
805 reg_00.raw = io_apic_read(apic, 0);
806 reg_01.raw = io_apic_read(apic, 1);
807 if (reg_01.bits.version >= 0x10)
808 reg_02.raw = io_apic_read(apic, 2);
809 spin_unlock_irqrestore(&ioapic_lock, flags);
810
811 printk("\n");
812 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
813 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
814 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
815 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
816 UNEXPECTED_IO_APIC();
817
818 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
819 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
820 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
821 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
822 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
823 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
824 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
825 (reg_01.bits.entries != 0x2E) &&
826 (reg_01.bits.entries != 0x3F) &&
827 (reg_01.bits.entries != 0x03)
828 )
829 UNEXPECTED_IO_APIC();
830
831 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
832 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
833 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
834 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
835 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
836 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
837 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
838 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
839 )
840 UNEXPECTED_IO_APIC();
841 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
842 UNEXPECTED_IO_APIC();
843
844 if (reg_01.bits.version >= 0x10) {
845 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
846 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
847 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
848 UNEXPECTED_IO_APIC();
849 }
850
851 printk(KERN_DEBUG ".... IRQ redirection table:\n");
852
853 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
854 " Stat Dest Deli Vect: \n");
855
856 for (i = 0; i <= reg_01.bits.entries; i++) {
857 struct IO_APIC_route_entry entry;
858
859 entry = ioapic_read_entry(apic, i);
860
861 printk(KERN_DEBUG " %02x %03X %02X ",
862 i,
863 entry.dest.logical.logical_dest,
864 entry.dest.physical.physical_dest
865 );
866
867 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
868 entry.mask,
869 entry.trigger,
870 entry.irr,
871 entry.polarity,
872 entry.delivery_status,
873 entry.dest_mode,
874 entry.delivery_mode,
875 entry.vector
876 );
877 }
878 }
879 printk(KERN_DEBUG "IRQ to pin mappings:\n");
880 for (i = 0; i < NR_IRQS; i++) {
881 struct irq_pin_list *entry = irq_2_pin + i;
882 if (entry->pin < 0)
883 continue;
884 printk(KERN_DEBUG "IRQ%d ", i);
885 for (;;) {
886 printk("-> %d:%d", entry->apic, entry->pin);
887 if (!entry->next)
888 break;
889 entry = irq_2_pin + entry->next;
890 }
891 printk("\n");
892 }
893
894 printk(KERN_INFO ".................................... done.\n");
895
896 return;
897 }
898
899 #if 0
900
901 static __apicdebuginit void print_APIC_bitfield (int base)
902 {
903 unsigned int v;
904 int i, j;
905
906 if (apic_verbosity == APIC_QUIET)
907 return;
908
909 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
910 for (i = 0; i < 8; i++) {
911 v = apic_read(base + i*0x10);
912 for (j = 0; j < 32; j++) {
913 if (v & (1<<j))
914 printk("1");
915 else
916 printk("0");
917 }
918 printk("\n");
919 }
920 }
921
922 void __apicdebuginit print_local_APIC(void * dummy)
923 {
924 unsigned int v, ver, maxlvt;
925
926 if (apic_verbosity == APIC_QUIET)
927 return;
928
929 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
930 smp_processor_id(), hard_smp_processor_id());
931 v = apic_read(APIC_ID);
932 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
933 v = apic_read(APIC_LVR);
934 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
935 ver = GET_APIC_VERSION(v);
936 maxlvt = get_maxlvt();
937
938 v = apic_read(APIC_TASKPRI);
939 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
940
941 v = apic_read(APIC_ARBPRI);
942 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
943 v & APIC_ARBPRI_MASK);
944 v = apic_read(APIC_PROCPRI);
945 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
946
947 v = apic_read(APIC_EOI);
948 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
949 v = apic_read(APIC_RRR);
950 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
951 v = apic_read(APIC_LDR);
952 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
953 v = apic_read(APIC_DFR);
954 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
955 v = apic_read(APIC_SPIV);
956 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
957
958 printk(KERN_DEBUG "... APIC ISR field:\n");
959 print_APIC_bitfield(APIC_ISR);
960 printk(KERN_DEBUG "... APIC TMR field:\n");
961 print_APIC_bitfield(APIC_TMR);
962 printk(KERN_DEBUG "... APIC IRR field:\n");
963 print_APIC_bitfield(APIC_IRR);
964
965 v = apic_read(APIC_ESR);
966 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
967
968 v = apic_read(APIC_ICR);
969 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
970 v = apic_read(APIC_ICR2);
971 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
972
973 v = apic_read(APIC_LVTT);
974 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
975
976 if (maxlvt > 3) { /* PC is LVT#4. */
977 v = apic_read(APIC_LVTPC);
978 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
979 }
980 v = apic_read(APIC_LVT0);
981 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
982 v = apic_read(APIC_LVT1);
983 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
984
985 if (maxlvt > 2) { /* ERR is LVT#3. */
986 v = apic_read(APIC_LVTERR);
987 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
988 }
989
990 v = apic_read(APIC_TMICT);
991 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
992 v = apic_read(APIC_TMCCT);
993 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
994 v = apic_read(APIC_TDCR);
995 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
996 printk("\n");
997 }
998
999 void print_all_local_APICs (void)
1000 {
1001 on_each_cpu(print_local_APIC, NULL, 1, 1);
1002 }
1003
1004 void __apicdebuginit print_PIC(void)
1005 {
1006 unsigned int v;
1007 unsigned long flags;
1008
1009 if (apic_verbosity == APIC_QUIET)
1010 return;
1011
1012 printk(KERN_DEBUG "\nprinting PIC contents\n");
1013
1014 spin_lock_irqsave(&i8259A_lock, flags);
1015
1016 v = inb(0xa1) << 8 | inb(0x21);
1017 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1018
1019 v = inb(0xa0) << 8 | inb(0x20);
1020 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1021
1022 outb(0x0b,0xa0);
1023 outb(0x0b,0x20);
1024 v = inb(0xa0) << 8 | inb(0x20);
1025 outb(0x0a,0xa0);
1026 outb(0x0a,0x20);
1027
1028 spin_unlock_irqrestore(&i8259A_lock, flags);
1029
1030 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1031
1032 v = inb(0x4d1) << 8 | inb(0x4d0);
1033 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1034 }
1035
1036 #endif /* 0 */
1037
1038 static void __init enable_IO_APIC(void)
1039 {
1040 union IO_APIC_reg_01 reg_01;
1041 int i8259_apic, i8259_pin;
1042 int i, apic;
1043 unsigned long flags;
1044
1045 for (i = 0; i < PIN_MAP_SIZE; i++) {
1046 irq_2_pin[i].pin = -1;
1047 irq_2_pin[i].next = 0;
1048 }
1049
1050 /*
1051 * The number of IO-APIC IRQ registers (== #pins):
1052 */
1053 for (apic = 0; apic < nr_ioapics; apic++) {
1054 spin_lock_irqsave(&ioapic_lock, flags);
1055 reg_01.raw = io_apic_read(apic, 1);
1056 spin_unlock_irqrestore(&ioapic_lock, flags);
1057 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1058 }
1059 for(apic = 0; apic < nr_ioapics; apic++) {
1060 int pin;
1061 /* See if any of the pins is in ExtINT mode */
1062 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1063 struct IO_APIC_route_entry entry;
1064 entry = ioapic_read_entry(apic, pin);
1065
1066 /* If the interrupt line is enabled and in ExtInt mode
1067 * I have found the pin where the i8259 is connected.
1068 */
1069 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1070 ioapic_i8259.apic = apic;
1071 ioapic_i8259.pin = pin;
1072 goto found_i8259;
1073 }
1074 }
1075 }
1076 found_i8259:
1077 /* Look to see what if the MP table has reported the ExtINT */
1078 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1079 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1080 /* Trust the MP table if nothing is setup in the hardware */
1081 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1082 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1083 ioapic_i8259.pin = i8259_pin;
1084 ioapic_i8259.apic = i8259_apic;
1085 }
1086 /* Complain if the MP table and the hardware disagree */
1087 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1088 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1089 {
1090 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1091 }
1092
1093 /*
1094 * Do not trust the IO-APIC being empty at bootup
1095 */
1096 clear_IO_APIC();
1097 }
1098
1099 /*
1100 * Not an __init, needed by the reboot code
1101 */
1102 void disable_IO_APIC(void)
1103 {
1104 /*
1105 * Clear the IO-APIC before rebooting:
1106 */
1107 clear_IO_APIC();
1108
1109 /*
1110 * If the i8259 is routed through an IOAPIC
1111 * Put that IOAPIC in virtual wire mode
1112 * so legacy interrupts can be delivered.
1113 */
1114 if (ioapic_i8259.pin != -1) {
1115 struct IO_APIC_route_entry entry;
1116
1117 memset(&entry, 0, sizeof(entry));
1118 entry.mask = 0; /* Enabled */
1119 entry.trigger = 0; /* Edge */
1120 entry.irr = 0;
1121 entry.polarity = 0; /* High */
1122 entry.delivery_status = 0;
1123 entry.dest_mode = 0; /* Physical */
1124 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1125 entry.vector = 0;
1126 entry.dest.physical.physical_dest =
1127 GET_APIC_ID(apic_read(APIC_ID));
1128
1129 /*
1130 * Add it to the IO-APIC irq-routing table:
1131 */
1132 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1133 }
1134
1135 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1136 }
1137
1138 /*
1139 * There is a nasty bug in some older SMP boards, their mptable lies
1140 * about the timer IRQ. We do the following to work around the situation:
1141 *
1142 * - timer IRQ defaults to IO-APIC IRQ
1143 * - if this function detects that timer IRQs are defunct, then we fall
1144 * back to ISA timer IRQs
1145 */
1146 static int __init timer_irq_works(void)
1147 {
1148 unsigned long t1 = jiffies;
1149
1150 local_irq_enable();
1151 /* Let ten ticks pass... */
1152 mdelay((10 * 1000) / HZ);
1153
1154 /*
1155 * Expect a few ticks at least, to be sure some possible
1156 * glue logic does not lock up after one or two first
1157 * ticks in a non-ExtINT mode. Also the local APIC
1158 * might have cached one ExtINT interrupt. Finally, at
1159 * least one tick may be lost due to delays.
1160 */
1161
1162 /* jiffies wrap? */
1163 if (jiffies - t1 > 4)
1164 return 1;
1165 return 0;
1166 }
1167
1168 /*
1169 * In the SMP+IOAPIC case it might happen that there are an unspecified
1170 * number of pending IRQ events unhandled. These cases are very rare,
1171 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1172 * better to do it this way as thus we do not have to be aware of
1173 * 'pending' interrupts in the IRQ path, except at this point.
1174 */
1175 /*
1176 * Edge triggered needs to resend any interrupt
1177 * that was delayed but this is now handled in the device
1178 * independent code.
1179 */
1180
1181 /*
1182 * Starting up a edge-triggered IO-APIC interrupt is
1183 * nasty - we need to make sure that we get the edge.
1184 * If it is already asserted for some reason, we need
1185 * return 1 to indicate that is was pending.
1186 *
1187 * This is not complete - we should be able to fake
1188 * an edge even if it isn't on the 8259A...
1189 */
1190
1191 static unsigned int startup_ioapic_irq(unsigned int irq)
1192 {
1193 int was_pending = 0;
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&ioapic_lock, flags);
1197 if (irq < 16) {
1198 disable_8259A_irq(irq);
1199 if (i8259A_irq_pending(irq))
1200 was_pending = 1;
1201 }
1202 __unmask_IO_APIC_irq(irq);
1203 spin_unlock_irqrestore(&ioapic_lock, flags);
1204
1205 return was_pending;
1206 }
1207
1208 static int ioapic_retrigger_irq(unsigned int irq)
1209 {
1210 cpumask_t mask;
1211 unsigned vector;
1212
1213 vector = irq_vector[irq];
1214 cpus_clear(mask);
1215 cpu_set(vector >> 8, mask);
1216
1217 send_IPI_mask(mask, vector & 0xff);
1218
1219 return 1;
1220 }
1221
1222 /*
1223 * Level and edge triggered IO-APIC interrupts need different handling,
1224 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1225 * handled with the level-triggered descriptor, but that one has slightly
1226 * more overhead. Level-triggered interrupts cannot be handled with the
1227 * edge-triggered handler, without risking IRQ storms and other ugly
1228 * races.
1229 */
1230
1231 static void ack_apic_edge(unsigned int irq)
1232 {
1233 move_native_irq(irq);
1234 ack_APIC_irq();
1235 }
1236
1237 static void ack_apic_level(unsigned int irq)
1238 {
1239 int do_unmask_irq = 0;
1240
1241 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1242 /* If we are moving the irq we need to mask it */
1243 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1244 do_unmask_irq = 1;
1245 mask_IO_APIC_irq(irq);
1246 }
1247 #endif
1248
1249 /*
1250 * We must acknowledge the irq before we move it or the acknowledge will
1251 * not propogate properly.
1252 */
1253 ack_APIC_irq();
1254
1255 /* Now we can move and renable the irq */
1256 move_masked_irq(irq);
1257 if (unlikely(do_unmask_irq))
1258 unmask_IO_APIC_irq(irq);
1259 }
1260
1261 static struct irq_chip ioapic_chip __read_mostly = {
1262 .name = "IO-APIC",
1263 .startup = startup_ioapic_irq,
1264 .mask = mask_IO_APIC_irq,
1265 .unmask = unmask_IO_APIC_irq,
1266 .ack = ack_apic_edge,
1267 .eoi = ack_apic_level,
1268 #ifdef CONFIG_SMP
1269 .set_affinity = set_ioapic_affinity_irq,
1270 #endif
1271 .retrigger = ioapic_retrigger_irq,
1272 };
1273
1274 static inline void init_IO_APIC_traps(void)
1275 {
1276 int irq;
1277
1278 /*
1279 * NOTE! The local APIC isn't very good at handling
1280 * multiple interrupts at the same interrupt level.
1281 * As the interrupt level is determined by taking the
1282 * vector number and shifting that right by 4, we
1283 * want to spread these out a bit so that they don't
1284 * all fall in the same interrupt level.
1285 *
1286 * Also, we've got to be careful not to trash gate
1287 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1288 */
1289 for (irq = 0; irq < NR_IRQS ; irq++) {
1290 int tmp = irq;
1291 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1292 /*
1293 * Hmm.. We don't have an entry for this,
1294 * so default to an old-fashioned 8259
1295 * interrupt if we can..
1296 */
1297 if (irq < 16)
1298 make_8259A_irq(irq);
1299 else
1300 /* Strange. Oh, well.. */
1301 irq_desc[irq].chip = &no_irq_chip;
1302 }
1303 }
1304 }
1305
1306 static void enable_lapic_irq (unsigned int irq)
1307 {
1308 unsigned long v;
1309
1310 v = apic_read(APIC_LVT0);
1311 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1312 }
1313
1314 static void disable_lapic_irq (unsigned int irq)
1315 {
1316 unsigned long v;
1317
1318 v = apic_read(APIC_LVT0);
1319 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1320 }
1321
1322 static void ack_lapic_irq (unsigned int irq)
1323 {
1324 ack_APIC_irq();
1325 }
1326
1327 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1328
1329 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1330 .typename = "local-APIC-edge",
1331 .startup = NULL, /* startup_irq() not used for IRQ0 */
1332 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1333 .enable = enable_lapic_irq,
1334 .disable = disable_lapic_irq,
1335 .ack = ack_lapic_irq,
1336 .end = end_lapic_irq,
1337 };
1338
1339 static void setup_nmi (void)
1340 {
1341 /*
1342 * Dirty trick to enable the NMI watchdog ...
1343 * We put the 8259A master into AEOI mode and
1344 * unmask on all local APICs LVT0 as NMI.
1345 *
1346 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1347 * is from Maciej W. Rozycki - so we do not have to EOI from
1348 * the NMI handler or the timer interrupt.
1349 */
1350 printk(KERN_INFO "activating NMI Watchdog ...");
1351
1352 enable_NMI_through_LVT0(NULL);
1353
1354 printk(" done.\n");
1355 }
1356
1357 /*
1358 * This looks a bit hackish but it's about the only one way of sending
1359 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1360 * not support the ExtINT mode, unfortunately. We need to send these
1361 * cycles as some i82489DX-based boards have glue logic that keeps the
1362 * 8259A interrupt line asserted until INTA. --macro
1363 */
1364 static inline void unlock_ExtINT_logic(void)
1365 {
1366 int apic, pin, i;
1367 struct IO_APIC_route_entry entry0, entry1;
1368 unsigned char save_control, save_freq_select;
1369 unsigned long flags;
1370
1371 pin = find_isa_irq_pin(8, mp_INT);
1372 apic = find_isa_irq_apic(8, mp_INT);
1373 if (pin == -1)
1374 return;
1375
1376 spin_lock_irqsave(&ioapic_lock, flags);
1377 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1378 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1379 spin_unlock_irqrestore(&ioapic_lock, flags);
1380 clear_IO_APIC_pin(apic, pin);
1381
1382 memset(&entry1, 0, sizeof(entry1));
1383
1384 entry1.dest_mode = 0; /* physical delivery */
1385 entry1.mask = 0; /* unmask IRQ now */
1386 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1387 entry1.delivery_mode = dest_ExtINT;
1388 entry1.polarity = entry0.polarity;
1389 entry1.trigger = 0;
1390 entry1.vector = 0;
1391
1392 spin_lock_irqsave(&ioapic_lock, flags);
1393 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1394 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1395 spin_unlock_irqrestore(&ioapic_lock, flags);
1396
1397 save_control = CMOS_READ(RTC_CONTROL);
1398 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1399 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1400 RTC_FREQ_SELECT);
1401 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1402
1403 i = 100;
1404 while (i-- > 0) {
1405 mdelay(10);
1406 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1407 i -= 10;
1408 }
1409
1410 CMOS_WRITE(save_control, RTC_CONTROL);
1411 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1412 clear_IO_APIC_pin(apic, pin);
1413
1414 spin_lock_irqsave(&ioapic_lock, flags);
1415 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1416 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1417 spin_unlock_irqrestore(&ioapic_lock, flags);
1418 }
1419
1420 /*
1421 * This code may look a bit paranoid, but it's supposed to cooperate with
1422 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1423 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1424 * fanatically on his truly buggy board.
1425 *
1426 * FIXME: really need to revamp this for modern platforms only.
1427 */
1428 static inline void check_timer(void)
1429 {
1430 int apic1, pin1, apic2, pin2;
1431 int vector;
1432
1433 /*
1434 * get/set the timer IRQ vector:
1435 */
1436 disable_8259A_irq(0);
1437 vector = assign_irq_vector(0, TARGET_CPUS);
1438
1439 /*
1440 * Subtle, code in do_timer_interrupt() expects an AEOI
1441 * mode for the 8259A whenever interrupts are routed
1442 * through I/O APICs. Also IRQ0 has to be enabled in
1443 * the 8259A which implies the virtual wire has to be
1444 * disabled in the local APIC.
1445 */
1446 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1447 init_8259A(1);
1448 if (timer_over_8254 > 0)
1449 enable_8259A_irq(0);
1450
1451 pin1 = find_isa_irq_pin(0, mp_INT);
1452 apic1 = find_isa_irq_apic(0, mp_INT);
1453 pin2 = ioapic_i8259.pin;
1454 apic2 = ioapic_i8259.apic;
1455
1456 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1457 vector, apic1, pin1, apic2, pin2);
1458
1459 if (pin1 != -1) {
1460 /*
1461 * Ok, does IRQ0 through the IOAPIC work?
1462 */
1463 unmask_IO_APIC_irq(0);
1464 if (!no_timer_check && timer_irq_works()) {
1465 nmi_watchdog_default();
1466 if (nmi_watchdog == NMI_IO_APIC) {
1467 disable_8259A_irq(0);
1468 setup_nmi();
1469 enable_8259A_irq(0);
1470 }
1471 if (disable_timer_pin_1 > 0)
1472 clear_IO_APIC_pin(0, pin1);
1473 return;
1474 }
1475 clear_IO_APIC_pin(apic1, pin1);
1476 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1477 "connected to IO-APIC\n");
1478 }
1479
1480 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1481 "through the 8259A ... ");
1482 if (pin2 != -1) {
1483 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1484 apic2, pin2);
1485 /*
1486 * legacy devices should be connected to IO APIC #0
1487 */
1488 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1489 if (timer_irq_works()) {
1490 apic_printk(APIC_VERBOSE," works.\n");
1491 nmi_watchdog_default();
1492 if (nmi_watchdog == NMI_IO_APIC) {
1493 setup_nmi();
1494 }
1495 return;
1496 }
1497 /*
1498 * Cleanup, just in case ...
1499 */
1500 clear_IO_APIC_pin(apic2, pin2);
1501 }
1502 apic_printk(APIC_VERBOSE," failed.\n");
1503
1504 if (nmi_watchdog == NMI_IO_APIC) {
1505 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1506 nmi_watchdog = 0;
1507 }
1508
1509 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1510
1511 disable_8259A_irq(0);
1512 irq_desc[0].chip = &lapic_irq_type;
1513 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1514 enable_8259A_irq(0);
1515
1516 if (timer_irq_works()) {
1517 apic_printk(APIC_VERBOSE," works.\n");
1518 return;
1519 }
1520 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1521 apic_printk(APIC_VERBOSE," failed.\n");
1522
1523 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1524
1525 init_8259A(0);
1526 make_8259A_irq(0);
1527 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1528
1529 unlock_ExtINT_logic();
1530
1531 if (timer_irq_works()) {
1532 apic_printk(APIC_VERBOSE," works.\n");
1533 return;
1534 }
1535 apic_printk(APIC_VERBOSE," failed :(.\n");
1536 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1537 }
1538
1539 static int __init notimercheck(char *s)
1540 {
1541 no_timer_check = 1;
1542 return 1;
1543 }
1544 __setup("no_timer_check", notimercheck);
1545
1546 /*
1547 *
1548 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1549 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1550 * Linux doesn't really care, as it's not actually used
1551 * for any interrupt handling anyway.
1552 */
1553 #define PIC_IRQS (1<<2)
1554
1555 void __init setup_IO_APIC(void)
1556 {
1557 enable_IO_APIC();
1558
1559 if (acpi_ioapic)
1560 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1561 else
1562 io_apic_irqs = ~PIC_IRQS;
1563
1564 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1565
1566 sync_Arb_IDs();
1567 setup_IO_APIC_irqs();
1568 init_IO_APIC_traps();
1569 check_timer();
1570 if (!acpi_ioapic)
1571 print_IO_APIC();
1572 }
1573
1574 struct sysfs_ioapic_data {
1575 struct sys_device dev;
1576 struct IO_APIC_route_entry entry[0];
1577 };
1578 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1579
1580 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1581 {
1582 struct IO_APIC_route_entry *entry;
1583 struct sysfs_ioapic_data *data;
1584 int i;
1585
1586 data = container_of(dev, struct sysfs_ioapic_data, dev);
1587 entry = data->entry;
1588 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1589 *entry = ioapic_read_entry(dev->id, i);
1590
1591 return 0;
1592 }
1593
1594 static int ioapic_resume(struct sys_device *dev)
1595 {
1596 struct IO_APIC_route_entry *entry;
1597 struct sysfs_ioapic_data *data;
1598 unsigned long flags;
1599 union IO_APIC_reg_00 reg_00;
1600 int i;
1601
1602 data = container_of(dev, struct sysfs_ioapic_data, dev);
1603 entry = data->entry;
1604
1605 spin_lock_irqsave(&ioapic_lock, flags);
1606 reg_00.raw = io_apic_read(dev->id, 0);
1607 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1608 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1609 io_apic_write(dev->id, 0, reg_00.raw);
1610 }
1611 spin_unlock_irqrestore(&ioapic_lock, flags);
1612 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1613 ioapic_write_entry(dev->id, i, entry[i]);
1614
1615 return 0;
1616 }
1617
1618 static struct sysdev_class ioapic_sysdev_class = {
1619 set_kset_name("ioapic"),
1620 .suspend = ioapic_suspend,
1621 .resume = ioapic_resume,
1622 };
1623
1624 static int __init ioapic_init_sysfs(void)
1625 {
1626 struct sys_device * dev;
1627 int i, size, error = 0;
1628
1629 error = sysdev_class_register(&ioapic_sysdev_class);
1630 if (error)
1631 return error;
1632
1633 for (i = 0; i < nr_ioapics; i++ ) {
1634 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1635 * sizeof(struct IO_APIC_route_entry);
1636 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1637 if (!mp_ioapic_data[i]) {
1638 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1639 continue;
1640 }
1641 memset(mp_ioapic_data[i], 0, size);
1642 dev = &mp_ioapic_data[i]->dev;
1643 dev->id = i;
1644 dev->cls = &ioapic_sysdev_class;
1645 error = sysdev_register(dev);
1646 if (error) {
1647 kfree(mp_ioapic_data[i]);
1648 mp_ioapic_data[i] = NULL;
1649 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1650 continue;
1651 }
1652 }
1653
1654 return 0;
1655 }
1656
1657 device_initcall(ioapic_init_sysfs);
1658
1659 /*
1660 * Dynamic irq allocate and deallocation
1661 */
1662 int create_irq(void)
1663 {
1664 /* Allocate an unused irq */
1665 int irq;
1666 int new;
1667 int vector = 0;
1668 unsigned long flags;
1669
1670 irq = -ENOSPC;
1671 spin_lock_irqsave(&vector_lock, flags);
1672 for (new = (NR_IRQS - 1); new >= 0; new--) {
1673 if (platform_legacy_irq(new))
1674 continue;
1675 if (irq_vector[new] != 0)
1676 continue;
1677 vector = __assign_irq_vector(new, TARGET_CPUS);
1678 if (likely(vector > 0))
1679 irq = new;
1680 break;
1681 }
1682 spin_unlock_irqrestore(&vector_lock, flags);
1683
1684 if (irq >= 0) {
1685 dynamic_irq_init(irq);
1686 }
1687 return irq;
1688 }
1689
1690 void destroy_irq(unsigned int irq)
1691 {
1692 unsigned long flags;
1693
1694 dynamic_irq_cleanup(irq);
1695
1696 spin_lock_irqsave(&vector_lock, flags);
1697 irq_vector[irq] = 0;
1698 spin_unlock_irqrestore(&vector_lock, flags);
1699 }
1700
1701 /*
1702 * MSI mesage composition
1703 */
1704 #ifdef CONFIG_PCI_MSI
1705 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1706 {
1707 int vector;
1708 unsigned dest;
1709
1710 vector = assign_irq_vector(irq, TARGET_CPUS);
1711 if (vector >= 0) {
1712 cpumask_t tmp;
1713
1714 cpus_clear(tmp);
1715 cpu_set(vector >> 8, tmp);
1716 dest = cpu_mask_to_apicid(tmp);
1717
1718 msg->address_hi = MSI_ADDR_BASE_HI;
1719 msg->address_lo =
1720 MSI_ADDR_BASE_LO |
1721 ((INT_DEST_MODE == 0) ?
1722 MSI_ADDR_DEST_MODE_PHYSICAL:
1723 MSI_ADDR_DEST_MODE_LOGICAL) |
1724 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1725 MSI_ADDR_REDIRECTION_CPU:
1726 MSI_ADDR_REDIRECTION_LOWPRI) |
1727 MSI_ADDR_DEST_ID(dest);
1728
1729 msg->data =
1730 MSI_DATA_TRIGGER_EDGE |
1731 MSI_DATA_LEVEL_ASSERT |
1732 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1733 MSI_DATA_DELIVERY_FIXED:
1734 MSI_DATA_DELIVERY_LOWPRI) |
1735 MSI_DATA_VECTOR(vector);
1736 }
1737 return vector;
1738 }
1739
1740 #ifdef CONFIG_SMP
1741 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1742 {
1743 struct msi_msg msg;
1744 unsigned int dest;
1745 cpumask_t tmp;
1746 int vector;
1747
1748 cpus_and(tmp, mask, cpu_online_map);
1749 if (cpus_empty(tmp))
1750 tmp = TARGET_CPUS;
1751
1752 cpus_and(mask, tmp, CPU_MASK_ALL);
1753
1754 vector = assign_irq_vector(irq, mask);
1755 if (vector < 0)
1756 return;
1757
1758 cpus_clear(tmp);
1759 cpu_set(vector >> 8, tmp);
1760 dest = cpu_mask_to_apicid(tmp);
1761
1762 read_msi_msg(irq, &msg);
1763
1764 msg.data &= ~MSI_DATA_VECTOR_MASK;
1765 msg.data |= MSI_DATA_VECTOR(vector);
1766 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1767 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1768
1769 write_msi_msg(irq, &msg);
1770 set_native_irq_info(irq, mask);
1771 }
1772 #endif /* CONFIG_SMP */
1773
1774 /*
1775 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1776 * which implement the MSI or MSI-X Capability Structure.
1777 */
1778 static struct irq_chip msi_chip = {
1779 .name = "PCI-MSI",
1780 .unmask = unmask_msi_irq,
1781 .mask = mask_msi_irq,
1782 .ack = ack_apic_edge,
1783 #ifdef CONFIG_SMP
1784 .set_affinity = set_msi_irq_affinity,
1785 #endif
1786 .retrigger = ioapic_retrigger_irq,
1787 };
1788
1789 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1790 {
1791 struct msi_msg msg;
1792 int ret;
1793 ret = msi_compose_msg(dev, irq, &msg);
1794 if (ret < 0)
1795 return ret;
1796
1797 write_msi_msg(irq, &msg);
1798
1799 set_irq_chip_and_handler(irq, &msi_chip, handle_edge_irq);
1800
1801 return 0;
1802 }
1803
1804 void arch_teardown_msi_irq(unsigned int irq)
1805 {
1806 return;
1807 }
1808
1809 #endif /* CONFIG_PCI_MSI */
1810
1811 /*
1812 * Hypertransport interrupt support
1813 */
1814 #ifdef CONFIG_HT_IRQ
1815
1816 #ifdef CONFIG_SMP
1817
1818 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1819 {
1820 u32 low, high;
1821 low = read_ht_irq_low(irq);
1822 high = read_ht_irq_high(irq);
1823
1824 low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1825 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1826
1827 low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1828 high |= HT_IRQ_HIGH_DEST_ID(dest);
1829
1830 write_ht_irq_low(irq, low);
1831 write_ht_irq_high(irq, high);
1832 }
1833
1834 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1835 {
1836 unsigned int dest;
1837 cpumask_t tmp;
1838 int vector;
1839
1840 cpus_and(tmp, mask, cpu_online_map);
1841 if (cpus_empty(tmp))
1842 tmp = TARGET_CPUS;
1843
1844 cpus_and(mask, tmp, CPU_MASK_ALL);
1845
1846 vector = assign_irq_vector(irq, mask);
1847 if (vector < 0)
1848 return;
1849
1850 cpus_clear(tmp);
1851 cpu_set(vector >> 8, tmp);
1852 dest = cpu_mask_to_apicid(tmp);
1853
1854 target_ht_irq(irq, dest, vector & 0xff);
1855 set_native_irq_info(irq, mask);
1856 }
1857 #endif
1858
1859 static struct hw_interrupt_type ht_irq_chip = {
1860 .name = "PCI-HT",
1861 .mask = mask_ht_irq,
1862 .unmask = unmask_ht_irq,
1863 .ack = ack_apic_edge,
1864 #ifdef CONFIG_SMP
1865 .set_affinity = set_ht_irq_affinity,
1866 #endif
1867 .retrigger = ioapic_retrigger_irq,
1868 };
1869
1870 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1871 {
1872 int vector;
1873
1874 vector = assign_irq_vector(irq, TARGET_CPUS);
1875 if (vector >= 0) {
1876 u32 low, high;
1877 unsigned dest;
1878 cpumask_t tmp;
1879
1880 cpus_clear(tmp);
1881 cpu_set(vector >> 8, tmp);
1882 dest = cpu_mask_to_apicid(tmp);
1883
1884 high = HT_IRQ_HIGH_DEST_ID(dest);
1885
1886 low = HT_IRQ_LOW_BASE |
1887 HT_IRQ_LOW_DEST_ID(dest) |
1888 HT_IRQ_LOW_VECTOR(vector) |
1889 ((INT_DEST_MODE == 0) ?
1890 HT_IRQ_LOW_DM_PHYSICAL :
1891 HT_IRQ_LOW_DM_LOGICAL) |
1892 HT_IRQ_LOW_RQEOI_EDGE |
1893 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1894 HT_IRQ_LOW_MT_FIXED :
1895 HT_IRQ_LOW_MT_ARBITRATED);
1896
1897 write_ht_irq_low(irq, low);
1898 write_ht_irq_high(irq, high);
1899
1900 set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);
1901 }
1902 return vector;
1903 }
1904 #endif /* CONFIG_HT_IRQ */
1905
1906 /* --------------------------------------------------------------------------
1907 ACPI-based IOAPIC Configuration
1908 -------------------------------------------------------------------------- */
1909
1910 #ifdef CONFIG_ACPI
1911
1912 #define IO_APIC_MAX_ID 0xFE
1913
1914 int __init io_apic_get_redir_entries (int ioapic)
1915 {
1916 union IO_APIC_reg_01 reg_01;
1917 unsigned long flags;
1918
1919 spin_lock_irqsave(&ioapic_lock, flags);
1920 reg_01.raw = io_apic_read(ioapic, 1);
1921 spin_unlock_irqrestore(&ioapic_lock, flags);
1922
1923 return reg_01.bits.entries;
1924 }
1925
1926
1927 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1928 {
1929 struct IO_APIC_route_entry entry;
1930 unsigned long flags;
1931 int vector;
1932 cpumask_t mask;
1933
1934 if (!IO_APIC_IRQ(irq)) {
1935 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1936 ioapic);
1937 return -EINVAL;
1938 }
1939
1940 /*
1941 * IRQs < 16 are already in the irq_2_pin[] map
1942 */
1943 if (irq >= 16)
1944 add_pin_to_irq(irq, ioapic, pin);
1945
1946
1947 vector = assign_irq_vector(irq, TARGET_CPUS);
1948 if (vector < 0)
1949 return vector;
1950
1951 cpus_clear(mask);
1952 cpu_set(vector >> 8, mask);
1953
1954 /*
1955 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1956 * Note that we mask (disable) IRQs now -- these get enabled when the
1957 * corresponding device driver registers for this IRQ.
1958 */
1959
1960 memset(&entry,0,sizeof(entry));
1961
1962 entry.delivery_mode = INT_DELIVERY_MODE;
1963 entry.dest_mode = INT_DEST_MODE;
1964 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
1965 entry.trigger = triggering;
1966 entry.polarity = polarity;
1967 entry.mask = 1; /* Disabled (masked) */
1968 entry.vector = vector & 0xff;
1969
1970 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1971 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1972 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1973 triggering, polarity);
1974
1975 ioapic_register_intr(irq, entry.vector, triggering);
1976
1977 if (!ioapic && (irq < 16))
1978 disable_8259A_irq(irq);
1979
1980 ioapic_write_entry(ioapic, pin, entry);
1981
1982 spin_lock_irqsave(&ioapic_lock, flags);
1983 set_native_irq_info(irq, TARGET_CPUS);
1984 spin_unlock_irqrestore(&ioapic_lock, flags);
1985
1986 return 0;
1987 }
1988
1989 #endif /* CONFIG_ACPI */
1990
1991
1992 /*
1993 * This function currently is only a helper for the i386 smp boot process where
1994 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1995 * so mask in all cases should simply be TARGET_CPUS
1996 */
1997 #ifdef CONFIG_SMP
1998 void __init setup_ioapic_dest(void)
1999 {
2000 int pin, ioapic, irq, irq_entry;
2001
2002 if (skip_ioapic_setup == 1)
2003 return;
2004
2005 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2006 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2007 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2008 if (irq_entry == -1)
2009 continue;
2010 irq = pin_2_irq(irq_entry, ioapic, pin);
2011 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2012 }
2013
2014 }
2015 }
2016 #endif
Linux kernel - Deliverables
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