arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/nmi.h>
  22 #include <linux/sysctl.h>
  23 #include <linux/kprobes.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30
  31 /*
  32  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  33  * - it may be reserved by some other driver, or not
  34  * - when not reserved by some other driver, it may be used for
  35  *   the NMI watchdog, or not
  36  *
  37  * This is maintained separately from nmi_active because the NMI
  38  * watchdog may also be driven from the I/O APIC timer.
  39  */
  40 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  41 static unsigned int lapic_nmi_owner;
  42 #define LAPIC_NMI_WATCHDOG      (1<<0)
  43 #define LAPIC_NMI_RESERVED      (1<<1)
  44
  45 /* nmi_active:
  46  * +1: the lapic NMI watchdog is active, but can be disabled
  47  *  0: the lapic NMI watchdog has not been set up, and cannot
  48  *     be enabled
  49  * -1: the lapic NMI watchdog is disabled, but can be enabled
  50  */
  51 int nmi_active;         /* oprofile uses this */
  52 int panic_on_timeout;
  53
  54 unsigned int nmi_watchdog = NMI_DEFAULT;
  55 static unsigned int nmi_hz = HZ;
  56 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  57 static unsigned int nmi_p4_cccr_val;
  58
  59 /* Note that these events don't tick when the CPU idles. This means
  60    the frequency varies with CPU load. */
  61
  62 #define K7_EVNTSEL_ENABLE       (1 << 22)
  63 #define K7_EVNTSEL_INT          (1 << 20)
  64 #define K7_EVNTSEL_OS           (1 << 17)
  65 #define K7_EVNTSEL_USR          (1 << 16)
  66 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  67 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  68
  69 #define MSR_P4_MISC_ENABLE      0x1A0
  70 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  71 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  72 #define MSR_P4_PERFCTR0         0x300
  73 #define MSR_P4_CCCR0            0x360
  74 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  75 #define P4_ESCR_OS              (1<<3)
  76 #define P4_ESCR_USR             (1<<2)
  77 #define P4_CCCR_OVF_PMI0        (1<<26)
  78 #define P4_CCCR_OVF_PMI1        (1<<27)
  79 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  80 #define P4_CCCR_COMPLEMENT      (1<<19)
  81 #define P4_CCCR_COMPARE         (1<<18)
  82 #define P4_CCCR_REQUIRED        (3<<16)
  83 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  84 #define P4_CCCR_ENABLE          (1<<12)
  85 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  86    CRU_ESCR0 (with any non-null event selector) through a complemented
  87    max threshold. [IA32-Vol3, Section 14.9.9] */
  88 #define MSR_P4_IQ_COUNTER0      0x30C
  89 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
  90 #define P4_NMI_IQ_CCCR0 \
  91         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
  92          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
  93
  94 static __cpuinit inline int nmi_known_cpu(void)
  95 {
  96         switch (boot_cpu_data.x86_vendor) {
  97         case X86_VENDOR_AMD:
  98                 return boot_cpu_data.x86 == 15;
  99         case X86_VENDOR_INTEL:
 100                 return boot_cpu_data.x86 == 15;
 101         }
 102         return 0;
 103 }
 104
 105 /* Run after command line and cpu_init init, but before all other checks */
 106 void __cpuinit nmi_watchdog_default(void)
 107 {
 108         if (nmi_watchdog != NMI_DEFAULT)
 109                 return;
 110         if (nmi_known_cpu())
 111                 nmi_watchdog = NMI_LOCAL_APIC;
 112         else
 113                 nmi_watchdog = NMI_IO_APIC;
 114 }
 115
 116 #ifdef CONFIG_SMP
 117 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 118  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 119  * CPUs during the test make them busy.
 120  */
 121 static __init void nmi_cpu_busy(void *data)
 122 {
 123         volatile int *endflag = data;
 124         local_irq_enable();
 125         /* Intentionally don't use cpu_relax here. This is
 126            to make sure that the performance counter really ticks,
 127            even if there is a simulator or similar that catches the
 128            pause instruction. On a real HT machine this is fine because
 129            all other CPUs are busy with "useless" delay loops and don't
 130            care if they get somewhat less cycles. */
 131         while (*endflag == 0)
 132                 barrier();
 133 }
 134 #endif
 135
 136 int __init check_nmi_watchdog (void)
 137 {
 138         volatile int endflag = 0;
 139         int *counts;
 140         int cpu;
 141
 142         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 143         if (!counts)
 144                 return -1;
 145
 146         printk(KERN_INFO "testing NMI watchdog ... ");
 147
 148 #ifdef CONFIG_SMP
 149         if (nmi_watchdog == NMI_LOCAL_APIC)
 150                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 151 #endif
 152
 153         for (cpu = 0; cpu < NR_CPUS; cpu++)
 154                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 155         local_irq_enable();
 156         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 157
 158         for_each_online_cpu(cpu) {
 159                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 160                         endflag = 1;
 161                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 162                                cpu,
 163                                counts[cpu],
 164                                cpu_pda(cpu)->__nmi_count);
 165                         nmi_active = 0;
 166                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 167                         nmi_perfctr_msr = 0;
 168                         kfree(counts);
 169                         return -1;
 170                 }
 171         }
 172         endflag = 1;
 173         printk("OK.\n");
 174
 175         /* now that we know it works we can reduce NMI frequency to
 176            something more reasonable; makes a difference in some configs */
 177         if (nmi_watchdog == NMI_LOCAL_APIC)
 178                 nmi_hz = 1;
 179
 180         kfree(counts);
 181         return 0;
 182 }
 183
 184 int __init setup_nmi_watchdog(char *str)
 185 {
 186         int nmi;
 187
 188         if (!strncmp(str,"panic",5)) {
 189                 panic_on_timeout = 1;
 190                 str = strchr(str, ',');
 191                 if (!str)
 192                         return 1;
 193                 ++str;
 194         }
 195
 196         get_option(&str, &nmi);
 197
 198         if (nmi >= NMI_INVALID)
 199                 return 0;
 200         nmi_watchdog = nmi;
 201         return 1;
 202 }
 203
 204 __setup("nmi_watchdog=", setup_nmi_watchdog);
 205
 206 static void disable_lapic_nmi_watchdog(void)
 207 {
 208         if (nmi_active <= 0)
 209                 return;
 210         switch (boot_cpu_data.x86_vendor) {
 211         case X86_VENDOR_AMD:
 212                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 213                 break;
 214         case X86_VENDOR_INTEL:
 215                 if (boot_cpu_data.x86 == 15) {
 216                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 217                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 218                 }
 219                 break;
 220         }
 221         nmi_active = -1;
 222         /* tell do_nmi() and others that we're not active any more */
 223         nmi_watchdog = 0;
 224 }
 225
 226 static void enable_lapic_nmi_watchdog(void)
 227 {
 228         if (nmi_active < 0) {
 229                 nmi_watchdog = NMI_LOCAL_APIC;
 230                 touch_nmi_watchdog();
 231                 setup_apic_nmi_watchdog();
 232         }
 233 }
 234
 235 int reserve_lapic_nmi(void)
 236 {
 237         unsigned int old_owner;
 238
 239         spin_lock(&lapic_nmi_owner_lock);
 240         old_owner = lapic_nmi_owner;
 241         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 242         spin_unlock(&lapic_nmi_owner_lock);
 243         if (old_owner & LAPIC_NMI_RESERVED)
 244                 return -EBUSY;
 245         if (old_owner & LAPIC_NMI_WATCHDOG)
 246                 disable_lapic_nmi_watchdog();
 247         return 0;
 248 }
 249
 250 void release_lapic_nmi(void)
 251 {
 252         unsigned int new_owner;
 253
 254         spin_lock(&lapic_nmi_owner_lock);
 255         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 256         lapic_nmi_owner = new_owner;
 257         spin_unlock(&lapic_nmi_owner_lock);
 258         if (new_owner & LAPIC_NMI_WATCHDOG)
 259                 enable_lapic_nmi_watchdog();
 260 }
 261
 262 void disable_timer_nmi_watchdog(void)
 263 {
 264         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 265                 return;
 266
 267         disable_irq(0);
 268         unset_nmi_callback();
 269         nmi_active = -1;
 270         nmi_watchdog = NMI_NONE;
 271 }
 272
 273 void enable_timer_nmi_watchdog(void)
 274 {
 275         if (nmi_active < 0) {
 276                 nmi_watchdog = NMI_IO_APIC;
 277                 touch_nmi_watchdog();
 278                 nmi_active = 1;
 279                 enable_irq(0);
 280         }
 281 }
 282
 283 #ifdef CONFIG_PM
 284
 285 static int nmi_pm_active; /* nmi_active before suspend */
 286
 287 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 288 {
 289         nmi_pm_active = nmi_active;
 290         disable_lapic_nmi_watchdog();
 291         return 0;
 292 }
 293
 294 static int lapic_nmi_resume(struct sys_device *dev)
 295 {
 296         if (nmi_pm_active > 0)
 297         enable_lapic_nmi_watchdog();
 298         return 0;
 299 }
 300
 301 static struct sysdev_class nmi_sysclass = {
 302         set_kset_name("lapic_nmi"),
 303         .resume         = lapic_nmi_resume,
 304         .suspend        = lapic_nmi_suspend,
 305 };
 306
 307 static struct sys_device device_lapic_nmi = {
 308         .id             = 0,
 309         .cls    = &nmi_sysclass,
 310 };
 311
 312 static int __init init_lapic_nmi_sysfs(void)
 313 {
 314         int error;
 315
 316         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 317                 return 0;
 318
 319         error = sysdev_class_register(&nmi_sysclass);
 320         if (!error)
 321                 error = sysdev_register(&device_lapic_nmi);
 322         return error;
 323 }
 324 /* must come after the local APIC's device_initcall() */
 325 late_initcall(init_lapic_nmi_sysfs);
 326
 327 #endif  /* CONFIG_PM */
 328
 329 /*
 330  * Activate the NMI watchdog via the local APIC.
 331  * Original code written by Keith Owens.
 332  */
 333
 334 static void clear_msr_range(unsigned int base, unsigned int n)
 335 {
 336         unsigned int i;
 337
 338         for(i = 0; i < n; ++i)
 339                 wrmsr(base+i, 0, 0);
 340 }
 341
 342 static void setup_k7_watchdog(void)
 343 {
 344         int i;
 345         unsigned int evntsel;
 346
 347         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 348
 349         for(i = 0; i < 4; ++i) {
 350                 /* Simulator may not support it */
 351                 if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
 352                         nmi_perfctr_msr = 0;
 353                         return;
 354                 }
 355                 wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
 356         }
 357
 358         evntsel = K7_EVNTSEL_INT
 359                 | K7_EVNTSEL_OS
 360                 | K7_EVNTSEL_USR
 361                 | K7_NMI_EVENT;
 362
 363         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 364         wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
 365         apic_write(APIC_LVTPC, APIC_DM_NMI);
 366         evntsel |= K7_EVNTSEL_ENABLE;
 367         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 368 }
 369
 370
 371 static int setup_p4_watchdog(void)
 372 {
 373         unsigned int misc_enable, dummy;
 374
 375         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 376         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 377                 return 0;
 378
 379         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 380         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 381 #ifdef CONFIG_SMP
 382         if (smp_num_siblings == 2)
 383                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 384 #endif
 385
 386         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 387                 clear_msr_range(0x3F1, 2);
 388         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 389            docs doesn't fully define it, so leave it alone for now. */
 390         if (boot_cpu_data.x86_model >= 0x3) {
 391                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 392                 clear_msr_range(0x3A0, 26);
 393                 clear_msr_range(0x3BC, 3);
 394         } else {
 395                 clear_msr_range(0x3A0, 31);
 396         }
 397         clear_msr_range(0x3C0, 6);
 398         clear_msr_range(0x3C8, 6);
 399         clear_msr_range(0x3E0, 2);
 400         clear_msr_range(MSR_P4_CCCR0, 18);
 401         clear_msr_range(MSR_P4_PERFCTR0, 18);
 402
 403         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 404         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 405         Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
 406         wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
 407         apic_write(APIC_LVTPC, APIC_DM_NMI);
 408         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 409         return 1;
 410 }
 411
 412 void setup_apic_nmi_watchdog(void)
 413 {
 414         switch (boot_cpu_data.x86_vendor) {
 415         case X86_VENDOR_AMD:
 416                 if (boot_cpu_data.x86 != 15)
 417                         return;
 418                 if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 419                         return;
 420                 setup_k7_watchdog();
 421                 break;
 422         case X86_VENDOR_INTEL:
 423                 if (boot_cpu_data.x86 != 15)
 424                         return;
 425                 if (!setup_p4_watchdog())
 426                         return;
 427                 break;
 428
 429         default:
 430                 return;
 431         }
 432         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 433         nmi_active = 1;
 434 }
 435
 436 /*
 437  * the best way to detect whether a CPU has a 'hard lockup' problem
 438  * is to check it's local APIC timer IRQ counts. If they are not
 439  * changing then that CPU has some problem.
 440  *
 441  * as these watchdog NMI IRQs are generated on every CPU, we only
 442  * have to check the current processor.
 443  */
 444
 445 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 446 static DEFINE_PER_CPU(local_t, alert_counter);
 447 static DEFINE_PER_CPU(int, nmi_touch);
 448
 449 void touch_nmi_watchdog (void)
 450 {
 451         if (nmi_watchdog > 0) {
 452                 unsigned cpu;
 453
 454                 /*
 455                  * Tell other CPUs to reset their alert counters. We cannot
 456                  * do it ourselves because the alert count increase is not
 457                  * atomic.
 458                  */
 459                 for_each_present_cpu (cpu)
 460                         per_cpu(nmi_touch, cpu) = 1;
 461         }
 462
 463         touch_softlockup_watchdog();
 464 }
 465
 466 void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 467 {
 468         int sum;
 469         int touched = 0;
 470
 471         sum = read_pda(apic_timer_irqs);
 472         if (__get_cpu_var(nmi_touch)) {
 473                 __get_cpu_var(nmi_touch) = 0;
 474                 touched = 1;
 475         }
 476 #ifdef CONFIG_X86_MCE
 477         /* Could check oops_in_progress here too, but it's safer
 478            not too */
 479         if (atomic_read(&mce_entry) > 0)
 480                 touched = 1;
 481 #endif
 482         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 483                 /*
 484                  * Ayiee, looks like this CPU is stuck ...
 485                  * wait a few IRQs (5 seconds) before doing the oops ...
 486                  */
 487                 local_inc(&__get_cpu_var(alert_counter));
 488                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
 489                         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 490                                                         == NOTIFY_STOP) {
 491                                 local_set(&__get_cpu_var(alert_counter), 0);
 492                                 return;
 493                         }
 494                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
 495                 }
 496         } else {
 497                 __get_cpu_var(last_irq_sum) = sum;
 498                 local_set(&__get_cpu_var(alert_counter), 0);
 499         }
 500         if (nmi_perfctr_msr) {
 501                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 502                         /*
 503                          * P4 quirks:
 504                          * - An overflown perfctr will assert its interrupt
 505                          *   until the OVF flag in its CCCR is cleared.
 506                          * - LVTPC is masked on interrupt and must be
 507                          *   unmasked by the LVTPC handler.
 508                          */
 509                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 510                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 511                 }
 512                 wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 513         }
 514 }
 515
 516 static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
 517 {
 518         return 0;
 519 }
 520
 521 static nmi_callback_t nmi_callback = dummy_nmi_callback;
 522
 523 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 524 {
 525         int cpu = safe_smp_processor_id();
 526
 527         nmi_enter();
 528         add_pda(__nmi_count,1);
 529         if (!rcu_dereference(nmi_callback)(regs, cpu))
 530                 default_do_nmi(regs);
 531         nmi_exit();
 532 }
 533
 534 void set_nmi_callback(nmi_callback_t callback)
 535 {
 536         vmalloc_sync_all();
 537         rcu_assign_pointer(nmi_callback, callback);
 538 }
 539
 540 void unset_nmi_callback(void)
 541 {
 542         nmi_callback = dummy_nmi_callback;
 543 }
 544
 545 #ifdef CONFIG_SYSCTL
 546
 547 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 548 {
 549         unsigned char reason = get_nmi_reason();
 550         char buf[64];
 551
 552         if (!(reason & 0xc0)) {
 553                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 554                 die_nmi(buf,regs);
 555         }
 556         return 0;
 557 }
 558
 559 /*
 560  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 561  */
 562 int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
 563                         void __user *buffer, size_t *length, loff_t *ppos)
 564 {
 565         int old_state;
 566
 567         old_state = unknown_nmi_panic;
 568         proc_dointvec(table, write, file, buffer, length, ppos);
 569         if (!!old_state == !!unknown_nmi_panic)
 570                 return 0;
 571
 572         if (unknown_nmi_panic) {
 573                 if (reserve_lapic_nmi() < 0) {
 574                         unknown_nmi_panic = 0;
 575                         return -EBUSY;
 576                 } else {
 577                         set_nmi_callback(unknown_nmi_panic_callback);
 578                 }
 579         } else {
 580                 release_lapic_nmi();
 581                 unset_nmi_callback();
 582         }
 583         return 0;
 584 }
 585
 586 #endif
 587
 588 EXPORT_SYMBOL(nmi_active);
 589 EXPORT_SYMBOL(nmi_watchdog);
 590 EXPORT_SYMBOL(reserve_lapic_nmi);
 591 EXPORT_SYMBOL(release_lapic_nmi);
 592 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 593 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
 594 EXPORT_SYMBOL(touch_nmi_watchdog);