arch/x86_64/pci/mmconfig.c

   1 /*
   2  * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
   3  *
   4  * This is an 64bit optimized version that always keeps the full mmconfig
   5  * space mapped. This allows lockless config space operation.
   6  */
   7
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/acpi.h>
  11 #include <linux/bitmap.h>
  12 #include <asm/e820.h>
  13
  14 #include "pci.h"
  15
  16 #define MMCONFIG_APER_SIZE (256*1024*1024)
  17 /* Verify the first 16 busses. We assume that systems with more busses
  18    get MCFG right. */
  19 #define MAX_CHECK_BUS 16
  20
  21 static DECLARE_BITMAP(fallback_slots, 32*MAX_CHECK_BUS);
  22
  23 /* Static virtual mapping of the MMCONFIG aperture */
  24 struct mmcfg_virt {
  25         struct acpi_table_mcfg_config *cfg;
  26         char __iomem *virt;
  27 };
  28 static struct mmcfg_virt *pci_mmcfg_virt;
  29
  30 static char __iomem *get_virt(unsigned int seg, unsigned bus)
  31 {
  32         int cfg_num = -1;
  33         struct acpi_table_mcfg_config *cfg;
  34
  35         while (1) {
  36                 ++cfg_num;
  37                 if (cfg_num >= pci_mmcfg_config_num)
  38                         break;
  39                 cfg = pci_mmcfg_virt[cfg_num].cfg;
  40                 if (cfg->pci_segment_group_number != seg)
  41                         continue;
  42                 if ((cfg->start_bus_number <= bus) &&
  43                     (cfg->end_bus_number >= bus))
  44                         return pci_mmcfg_virt[cfg_num].virt;
  45         }
  46
  47         /* Handle more broken MCFG tables on Asus etc.
  48            They only contain a single entry for bus 0-0. Assume
  49            this applies to all busses. */
  50         cfg = &pci_mmcfg_config[0];
  51         if (pci_mmcfg_config_num == 1 &&
  52                 cfg->pci_segment_group_number == 0 &&
  53                 (cfg->start_bus_number | cfg->end_bus_number) == 0)
  54                 return pci_mmcfg_virt[0].virt;
  55
  56         /* Fall back to type 0 */
  57         return NULL;
  58 }
  59
  60 static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
  61 {
  62         char __iomem *addr;
  63         if (seg == 0 && bus < MAX_CHECK_BUS &&
  64                 test_bit(32*bus + PCI_SLOT(devfn), fallback_slots))
  65                 return NULL;
  66         addr = get_virt(seg, bus);
  67         if (!addr)
  68                 return NULL;
  69         return addr + ((bus << 20) | (devfn << 12));
  70 }
  71
  72 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
  73                           unsigned int devfn, int reg, int len, u32 *value)
  74 {
  75         char __iomem *addr;
  76
  77         /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
  78         if (unlikely(!value || (bus > 255) || (devfn > 255) || (reg > 4095))) {
  79                 *value = -1;
  80                 return -EINVAL;
  81         }
  82
  83         addr = pci_dev_base(seg, bus, devfn);
  84         if (!addr)
  85                 return pci_conf1_read(seg,bus,devfn,reg,len,value);
  86
  87         switch (len) {
  88         case 1:
  89                 *value = readb(addr + reg);
  90                 break;
  91         case 2:
  92                 *value = readw(addr + reg);
  93                 break;
  94         case 4:
  95                 *value = readl(addr + reg);
  96                 break;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
 103                            unsigned int devfn, int reg, int len, u32 value)
 104 {
 105         char __iomem *addr;
 106
 107         /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
 108         if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
 109                 return -EINVAL;
 110
 111         addr = pci_dev_base(seg, bus, devfn);
 112         if (!addr)
 113                 return pci_conf1_write(seg,bus,devfn,reg,len,value);
 114
 115         switch (len) {
 116         case 1:
 117                 writeb(value, addr + reg);
 118                 break;
 119         case 2:
 120                 writew(value, addr + reg);
 121                 break;
 122         case 4:
 123                 writel(value, addr + reg);
 124                 break;
 125         }
 126
 127         return 0;
 128 }
 129
 130 static struct pci_raw_ops pci_mmcfg = {
 131         .read =         pci_mmcfg_read,
 132         .write =        pci_mmcfg_write,
 133 };
 134
 135 /* K8 systems have some devices (typically in the builtin northbridge)
 136    that are only accessible using type1
 137    Normally this can be expressed in the MCFG by not listing them
 138    and assigning suitable _SEGs, but this isn't implemented in some BIOS.
 139    Instead try to discover all devices on bus 0 that are unreachable using MM
 140    and fallback for them. */
 141 static __init void unreachable_devices(void)
 142 {
 143         int i, k;
 144         /* Use the max bus number from ACPI here? */
 145         for (k = 0; i < MAX_CHECK_BUS; k++) {
 146                 for (i = 0; i < 32; i++) {
 147                         u32 val1;
 148                         char __iomem *addr;
 149
 150                         pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
 151                         if (val1 == 0xffffffff)
 152                                 continue;
 153                         addr = pci_dev_base(0, k, PCI_DEVFN(i, 0));
 154                         if (addr == NULL|| readl(addr) != val1) {
 155                                 set_bit(i + 32*k, fallback_slots);
 156                                 printk(KERN_NOTICE
 157                                 "PCI: No mmconfig possible on device %x:%x\n",
 158                                         k, i);
 159                         }
 160                 }
 161         }
 162 }
 163
 164 void __init pci_mmcfg_init(void)
 165 {
 166         int i;
 167
 168         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 169                 return;
 170
 171         acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
 172         if ((pci_mmcfg_config_num == 0) ||
 173             (pci_mmcfg_config == NULL) ||
 174             (pci_mmcfg_config[0].base_address == 0))
 175                 return;
 176
 177         if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
 178                         pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
 179                         E820_RESERVED)) {
 180                 printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
 181                 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
 182                 return;
 183         }
 184
 185         /* RED-PEN i386 doesn't do _nocache right now */
 186         pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL);
 187         if (pci_mmcfg_virt == NULL) {
 188                 printk("PCI: Can not allocate memory for mmconfig structures\n");
 189                 return;
 190         }
 191         for (i = 0; i < pci_mmcfg_config_num; ++i) {
 192                 pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
 193                 pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
 194                 if (!pci_mmcfg_virt[i].virt) {
 195                         printk("PCI: Cannot map mmconfig aperture for segment %d\n",
 196                                pci_mmcfg_config[i].pci_segment_group_number);
 197                         return;
 198                 }
 199                 printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
 200         }
 201
 202         unreachable_devices();
 203
 204         raw_pci_ops = &pci_mmcfg;
 205         pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 206 }