1 /* BFD back-end for Renesas Super-H COFF binaries.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7 This file is part of BFD, the Binary File Descriptor library.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
30 #include "coff/internal.h"
32 #undef bfd_pe_print_pdata
37 #ifndef COFF_IMAGE_WITH_PE
38 static bfd_boolean sh_align_load_span
39 (bfd
*, asection
*, bfd_byte
*,
40 bfd_boolean (*) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
41 void *, bfd_vma
**, bfd_vma
*, bfd_vma
, bfd_vma
, bfd_boolean
*);
43 #define _bfd_sh_align_load_span sh_align_load_span
46 #define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
50 #define bfd_pe_print_pdata NULL
52 #endif /* COFF_WITH_PE. */
56 /* Internal functions. */
59 /* Can't build import tables with 2**4 alignment. */
60 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
62 /* Default section alignment to 2**4. */
63 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
66 #ifdef COFF_IMAGE_WITH_PE
67 /* Align PE executables. */
68 #define COFF_PAGE_SIZE 0x1000
71 /* Generate long file names. */
72 #define COFF_LONG_FILENAMES
75 /* Return TRUE if this relocation should
76 appear in the output .reloc section. */
79 in_reloc_p (bfd
* abfd ATTRIBUTE_UNUSED
,
80 reloc_howto_type
* howto
)
82 return ! howto
->pc_relative
&& howto
->type
!= R_SH_IMAGEBASE
;
86 static bfd_reloc_status_type
87 sh_reloc (bfd
*, arelent
*, asymbol
*, void *, asection
*, bfd
*, char **);
89 sh_relocate_section (bfd
*, struct bfd_link_info
*, bfd
*, asection
*,
90 bfd_byte
*, struct internal_reloc
*,
91 struct internal_syment
*, asection
**);
93 sh_align_loads (bfd
*, asection
*, struct internal_reloc
*,
94 bfd_byte
*, bfd_boolean
*);
96 /* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98 static reloc_howto_type sh_coff_howtos
[] =
104 HOWTO (R_SH_IMM32CE
, /* type */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
108 FALSE
, /* pc_relative */
110 complain_overflow_bitfield
, /* complain_on_overflow */
111 sh_reloc
, /* special_function */
112 "r_imm32ce", /* name */
113 TRUE
, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 FALSE
), /* pcrel_offset */
120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
128 HOWTO (R_SH_PCDISP8BY2
, /* type */
130 1, /* size (0 = byte, 1 = short, 2 = long) */
132 TRUE
, /* pc_relative */
134 complain_overflow_signed
, /* complain_on_overflow */
135 sh_reloc
, /* special_function */
136 "r_pcdisp8by2", /* name */
137 TRUE
, /* partial_inplace */
140 TRUE
), /* pcrel_offset */
142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
144 HOWTO (R_SH_PCDISP
, /* type */
146 1, /* size (0 = byte, 1 = short, 2 = long) */
148 TRUE
, /* pc_relative */
150 complain_overflow_signed
, /* complain_on_overflow */
151 sh_reloc
, /* special_function */
152 "r_pcdisp12by2", /* name */
153 TRUE
, /* partial_inplace */
154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
156 TRUE
), /* pcrel_offset */
160 HOWTO (R_SH_IMM32
, /* type */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
164 FALSE
, /* pc_relative */
166 complain_overflow_bitfield
, /* complain_on_overflow */
167 sh_reloc
, /* special_function */
168 "r_imm32", /* name */
169 TRUE
, /* partial_inplace */
170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
172 FALSE
), /* pcrel_offset */
176 HOWTO (R_SH_IMAGEBASE
, /* type */
178 2, /* size (0 = byte, 1 = short, 2 = long) */
180 FALSE
, /* pc_relative */
182 complain_overflow_bitfield
, /* complain_on_overflow */
183 sh_reloc
, /* special_function */
185 TRUE
, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 FALSE
), /* pcrel_offset */
190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
198 HOWTO (R_SH_PCRELIMM8BY2
, /* type */
200 1, /* size (0 = byte, 1 = short, 2 = long) */
202 TRUE
, /* pc_relative */
204 complain_overflow_unsigned
, /* complain_on_overflow */
205 sh_reloc
, /* special_function */
206 "r_pcrelimm8by2", /* name */
207 TRUE
, /* partial_inplace */
210 TRUE
), /* pcrel_offset */
212 HOWTO (R_SH_PCRELIMM8BY4
, /* type */
214 1, /* size (0 = byte, 1 = short, 2 = long) */
216 TRUE
, /* pc_relative */
218 complain_overflow_unsigned
, /* complain_on_overflow */
219 sh_reloc
, /* special_function */
220 "r_pcrelimm8by4", /* name */
221 TRUE
, /* partial_inplace */
224 TRUE
), /* pcrel_offset */
226 HOWTO (R_SH_IMM16
, /* type */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
230 FALSE
, /* pc_relative */
232 complain_overflow_bitfield
, /* complain_on_overflow */
233 sh_reloc
, /* special_function */
234 "r_imm16", /* name */
235 TRUE
, /* partial_inplace */
236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
238 FALSE
), /* pcrel_offset */
240 HOWTO (R_SH_SWITCH16
, /* type */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
244 FALSE
, /* pc_relative */
246 complain_overflow_bitfield
, /* complain_on_overflow */
247 sh_reloc
, /* special_function */
248 "r_switch16", /* name */
249 TRUE
, /* partial_inplace */
250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
252 FALSE
), /* pcrel_offset */
254 HOWTO (R_SH_SWITCH32
, /* type */
256 2, /* size (0 = byte, 1 = short, 2 = long) */
258 FALSE
, /* pc_relative */
260 complain_overflow_bitfield
, /* complain_on_overflow */
261 sh_reloc
, /* special_function */
262 "r_switch32", /* name */
263 TRUE
, /* partial_inplace */
264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE
), /* pcrel_offset */
268 HOWTO (R_SH_USES
, /* type */
270 1, /* size (0 = byte, 1 = short, 2 = long) */
272 FALSE
, /* pc_relative */
274 complain_overflow_bitfield
, /* complain_on_overflow */
275 sh_reloc
, /* special_function */
277 TRUE
, /* partial_inplace */
278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
280 FALSE
), /* pcrel_offset */
282 HOWTO (R_SH_COUNT
, /* type */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
286 FALSE
, /* pc_relative */
288 complain_overflow_bitfield
, /* complain_on_overflow */
289 sh_reloc
, /* special_function */
290 "r_count", /* name */
291 TRUE
, /* partial_inplace */
292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
294 FALSE
), /* pcrel_offset */
296 HOWTO (R_SH_ALIGN
, /* type */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
300 FALSE
, /* pc_relative */
302 complain_overflow_bitfield
, /* complain_on_overflow */
303 sh_reloc
, /* special_function */
304 "r_align", /* name */
305 TRUE
, /* partial_inplace */
306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
308 FALSE
), /* pcrel_offset */
310 HOWTO (R_SH_CODE
, /* type */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
314 FALSE
, /* pc_relative */
316 complain_overflow_bitfield
, /* complain_on_overflow */
317 sh_reloc
, /* special_function */
319 TRUE
, /* partial_inplace */
320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
322 FALSE
), /* pcrel_offset */
324 HOWTO (R_SH_DATA
, /* type */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
328 FALSE
, /* pc_relative */
330 complain_overflow_bitfield
, /* complain_on_overflow */
331 sh_reloc
, /* special_function */
333 TRUE
, /* partial_inplace */
334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
336 FALSE
), /* pcrel_offset */
338 HOWTO (R_SH_LABEL
, /* type */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
342 FALSE
, /* pc_relative */
344 complain_overflow_bitfield
, /* complain_on_overflow */
345 sh_reloc
, /* special_function */
346 "r_label", /* name */
347 TRUE
, /* partial_inplace */
348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
350 FALSE
), /* pcrel_offset */
352 HOWTO (R_SH_SWITCH8
, /* type */
354 0, /* size (0 = byte, 1 = short, 2 = long) */
356 FALSE
, /* pc_relative */
358 complain_overflow_bitfield
, /* complain_on_overflow */
359 sh_reloc
, /* special_function */
360 "r_switch8", /* name */
361 TRUE
, /* partial_inplace */
364 FALSE
) /* pcrel_offset */
367 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
369 /* Check for a bad magic number. */
370 #define BADMAG(x) SHBADMAG(x)
372 /* Customize coffcode.h (this is not currently used). */
375 /* FIXME: This should not be set here. */
376 #define __A_MAGIC_SET__
379 /* Swap the r_offset field in and out. */
380 #define SWAP_IN_RELOC_OFFSET H_GET_32
381 #define SWAP_OUT_RELOC_OFFSET H_PUT_32
383 /* Swap out extra information in the reloc structure. */
384 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
393 /* Get the value of a symbol, when performing a relocation. */
396 get_symbol_value (asymbol
*symbol
)
400 if (bfd_is_com_section (symbol
->section
))
403 relocation
= (symbol
->value
+
404 symbol
->section
->output_section
->vma
+
405 symbol
->section
->output_offset
);
411 /* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413 #define coff_rtype_to_howto coff_sh_rtype_to_howto
416 static reloc_howto_type
*
417 coff_sh_rtype_to_howto (bfd
* abfd ATTRIBUTE_UNUSED
,
419 struct internal_reloc
* rel
,
420 struct coff_link_hash_entry
* h
,
421 struct internal_syment
* sym
,
424 reloc_howto_type
* howto
;
426 howto
= sh_coff_howtos
+ rel
->r_type
;
430 if (howto
->pc_relative
)
431 *addendp
+= sec
->vma
;
433 if (sym
!= NULL
&& sym
->n_scnum
== 0 && sym
->n_value
!= 0)
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
440 BFD_ASSERT (h
!= NULL
);
443 if (howto
->pc_relative
)
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
454 *addendp
-= sym
->n_value
;
457 if (rel
->r_type
== R_SH_IMAGEBASE
)
458 *addendp
-= pe_data (sec
->output_section
->owner
)->pe_opthdr
.ImageBase
;
463 #endif /* COFF_WITH_PE */
465 /* This structure is used to map BFD reloc codes to SH PE relocs. */
466 struct shcoff_reloc_map
468 bfd_reloc_code_real_type bfd_reloc_val
;
469 unsigned char shcoff_reloc_val
;
473 /* An array mapping BFD reloc codes to SH PE relocs. */
474 static const struct shcoff_reloc_map sh_reloc_map
[] =
476 { BFD_RELOC_32
, R_SH_IMM32CE
},
477 { BFD_RELOC_RVA
, R_SH_IMAGEBASE
},
478 { BFD_RELOC_CTOR
, R_SH_IMM32CE
},
481 /* An array mapping BFD reloc codes to SH PE relocs. */
482 static const struct shcoff_reloc_map sh_reloc_map
[] =
484 { BFD_RELOC_32
, R_SH_IMM32
},
485 { BFD_RELOC_CTOR
, R_SH_IMM32
},
489 /* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
492 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
494 static reloc_howto_type
*
495 sh_coff_reloc_type_lookup (bfd
* abfd ATTRIBUTE_UNUSED
,
496 bfd_reloc_code_real_type code
)
500 for (i
= ARRAY_SIZE (sh_reloc_map
); i
--;)
501 if (sh_reloc_map
[i
].bfd_reloc_val
== code
)
502 return &sh_coff_howtos
[(int) sh_reloc_map
[i
].shcoff_reloc_val
];
504 _bfd_error_handler (_("SH Error: unknown reloc type %d"), code
);
508 static reloc_howto_type
*
509 sh_coff_reloc_name_lookup (bfd
*abfd ATTRIBUTE_UNUSED
,
514 for (i
= 0; i
< sizeof (sh_coff_howtos
) / sizeof (sh_coff_howtos
[0]); i
++)
515 if (sh_coff_howtos
[i
].name
!= NULL
516 && strcasecmp (sh_coff_howtos
[i
].name
, r_name
) == 0)
517 return &sh_coff_howtos
[i
];
522 /* This macro is used in coffcode.h to get the howto corresponding to
523 an internal reloc. */
525 #define RTYPE2HOWTO(relent, internal) \
527 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
528 ? &sh_coff_howtos[(internal)->r_type] \
529 : (reloc_howto_type *) NULL))
531 /* This is the same as the macro in coffcode.h, except that it copies
532 r_offset into reloc_entry->addend for some relocs. */
533 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
535 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
536 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
537 coffsym = (obj_symbols (abfd) \
538 + (cache_ptr->sym_ptr_ptr - symbols)); \
540 coffsym = coff_symbol_from (ptr); \
541 if (coffsym != (coff_symbol_type *) NULL \
542 && coffsym->native->u.syment.n_scnum == 0) \
543 cache_ptr->addend = 0; \
544 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
545 && ptr->section != (asection *) NULL) \
546 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
548 cache_ptr->addend = 0; \
549 if ((reloc).r_type == R_SH_SWITCH8 \
550 || (reloc).r_type == R_SH_SWITCH16 \
551 || (reloc).r_type == R_SH_SWITCH32 \
552 || (reloc).r_type == R_SH_USES \
553 || (reloc).r_type == R_SH_COUNT \
554 || (reloc).r_type == R_SH_ALIGN) \
555 cache_ptr->addend = (reloc).r_offset; \
558 /* This is the howto function for the SH relocations. */
560 static bfd_reloc_status_type
561 sh_reloc (bfd
* abfd
,
562 arelent
* reloc_entry
,
565 asection
* input_section
,
567 char ** error_message ATTRIBUTE_UNUSED
)
571 unsigned short r_type
;
572 bfd_vma addr
= reloc_entry
->address
;
573 bfd_byte
*hit_data
= addr
+ (bfd_byte
*) data
;
575 r_type
= reloc_entry
->howto
->type
;
577 if (output_bfd
!= NULL
)
579 /* Partial linking--do nothing. */
580 reloc_entry
->address
+= input_section
->output_offset
;
584 /* Almost all relocs have to do with relaxing. If any work must be
585 done for them, it has been done in sh_relax_section. */
586 if (r_type
!= R_SH_IMM32
588 && r_type
!= R_SH_IMM32CE
589 && r_type
!= R_SH_IMAGEBASE
591 && (r_type
!= R_SH_PCDISP
592 || (symbol_in
->flags
& BSF_LOCAL
) != 0))
595 if (symbol_in
!= NULL
596 && bfd_is_und_section (symbol_in
->section
))
597 return bfd_reloc_undefined
;
599 sym_value
= get_symbol_value (symbol_in
);
607 insn
= bfd_get_32 (abfd
, hit_data
);
608 insn
+= sym_value
+ reloc_entry
->addend
;
609 bfd_put_32 (abfd
, (bfd_vma
) insn
, hit_data
);
613 insn
= bfd_get_32 (abfd
, hit_data
);
614 insn
+= sym_value
+ reloc_entry
->addend
;
615 insn
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
616 bfd_put_32 (abfd
, (bfd_vma
) insn
, hit_data
);
620 insn
= bfd_get_16 (abfd
, hit_data
);
621 sym_value
+= reloc_entry
->addend
;
622 sym_value
-= (input_section
->output_section
->vma
623 + input_section
->output_offset
626 sym_value
+= (insn
& 0xfff) << 1;
629 insn
= (insn
& 0xf000) | (sym_value
& 0xfff);
630 bfd_put_16 (abfd
, (bfd_vma
) insn
, hit_data
);
631 if (sym_value
< (bfd_vma
) -0x1000 || sym_value
>= 0x1000)
632 return bfd_reloc_overflow
;
642 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
644 /* We can do relaxing. */
645 #define coff_bfd_relax_section sh_relax_section
647 /* We use the special COFF backend linker. */
648 #define coff_relocate_section sh_relocate_section
650 /* When relaxing, we need to use special code to get the relocated
652 #define coff_bfd_get_relocated_section_contents \
653 sh_coff_get_relocated_section_contents
655 #include "coffcode.h"
658 sh_relax_delete_bytes (bfd
*, asection
*, bfd_vma
, int);
660 /* This function handles relaxing on the SH.
662 Function calls on the SH look like this:
671 The compiler and assembler will cooperate to create R_SH_USES
672 relocs on the jsr instructions. The r_offset field of the
673 R_SH_USES reloc is the PC relative offset to the instruction which
674 loads the register (the r_offset field is computed as though it
675 were a jump instruction, so the offset value is actually from four
676 bytes past the instruction). The linker can use this reloc to
677 determine just which function is being called, and thus decide
678 whether it is possible to replace the jsr with a bsr.
680 If multiple function calls are all based on a single register load
681 (i.e., the same function is called multiple times), the compiler
682 guarantees that each function call will have an R_SH_USES reloc.
683 Therefore, if the linker is able to convert each R_SH_USES reloc
684 which refers to that address, it can safely eliminate the register
687 When the assembler creates an R_SH_USES reloc, it examines it to
688 determine which address is being loaded (L1 in the above example).
689 It then counts the number of references to that address, and
690 creates an R_SH_COUNT reloc at that address. The r_offset field of
691 the R_SH_COUNT reloc will be the number of references. If the
692 linker is able to eliminate a register load, it can use the
693 R_SH_COUNT reloc to see whether it can also eliminate the function
696 SH relaxing also handles another, unrelated, matter. On the SH, if
697 a load or store instruction is not aligned on a four byte boundary,
698 the memory cycle interferes with the 32 bit instruction fetch,
699 causing a one cycle bubble in the pipeline. Therefore, we try to
700 align load and store instructions on four byte boundaries if we
701 can, by swapping them with one of the adjacent instructions. */
704 sh_relax_section (bfd
*abfd
,
706 struct bfd_link_info
*link_info
,
709 struct internal_reloc
*internal_relocs
;
710 bfd_boolean have_code
;
711 struct internal_reloc
*irel
, *irelend
;
712 bfd_byte
*contents
= NULL
;
716 if (bfd_link_relocatable (link_info
)
717 || (sec
->flags
& SEC_RELOC
) == 0
718 || sec
->reloc_count
== 0)
721 if (coff_section_data (abfd
, sec
) == NULL
)
723 bfd_size_type amt
= sizeof (struct coff_section_tdata
);
724 sec
->used_by_bfd
= bfd_zalloc (abfd
, amt
);
725 if (sec
->used_by_bfd
== NULL
)
729 internal_relocs
= (_bfd_coff_read_internal_relocs
730 (abfd
, sec
, link_info
->keep_memory
,
731 (bfd_byte
*) NULL
, FALSE
,
732 (struct internal_reloc
*) NULL
));
733 if (internal_relocs
== NULL
)
738 irelend
= internal_relocs
+ sec
->reloc_count
;
739 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
741 bfd_vma laddr
, paddr
, symval
;
743 struct internal_reloc
*irelfn
, *irelscan
, *irelcount
;
744 struct internal_syment sym
;
747 if (irel
->r_type
== R_SH_CODE
)
750 if (irel
->r_type
!= R_SH_USES
)
753 /* Get the section contents. */
754 if (contents
== NULL
)
756 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
757 contents
= coff_section_data (abfd
, sec
)->contents
;
760 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
765 /* The r_offset field of the R_SH_USES reloc will point us to
766 the register load. The 4 is because the r_offset field is
767 computed as though it were a jump offset, which are based
768 from 4 bytes after the jump instruction. */
769 laddr
= irel
->r_vaddr
- sec
->vma
+ 4;
770 /* Careful to sign extend the 32-bit offset. */
771 laddr
+= ((irel
->r_offset
& 0xffffffff) ^ 0x80000000) - 0x80000000;
772 if (laddr
>= sec
->size
)
774 /* xgettext: c-format */
775 _bfd_error_handler (_("%B: 0x%lx: warning: bad R_SH_USES offset"),
776 abfd
, (unsigned long) irel
->r_vaddr
);
779 insn
= bfd_get_16 (abfd
, contents
+ laddr
);
781 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
782 if ((insn
& 0xf000) != 0xd000)
785 /* xgettext: c-format */
786 (_("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x"),
787 abfd
, (unsigned long) irel
->r_vaddr
, insn
);
791 /* Get the address from which the register is being loaded. The
792 displacement in the mov.l instruction is quadrupled. It is a
793 displacement from four bytes after the movl instruction, but,
794 before adding in the PC address, two least significant bits
795 of the PC are cleared. We assume that the section is aligned
796 on a four byte boundary. */
799 paddr
+= (laddr
+ 4) &~ (bfd_vma
) 3;
800 if (paddr
>= sec
->size
)
803 /* xgettext: c-format */
804 (_("%B: 0x%lx: warning: bad R_SH_USES load offset"),
805 abfd
, (unsigned long) irel
->r_vaddr
);
809 /* Get the reloc for the address from which the register is
810 being loaded. This reloc will tell us which function is
811 actually being called. */
813 for (irelfn
= internal_relocs
; irelfn
< irelend
; irelfn
++)
814 if (irelfn
->r_vaddr
== paddr
816 && (irelfn
->r_type
== R_SH_IMM32
817 || irelfn
->r_type
== R_SH_IMM32CE
818 || irelfn
->r_type
== R_SH_IMAGEBASE
)
821 && irelfn
->r_type
== R_SH_IMM32
825 if (irelfn
>= irelend
)
828 /* xgettext: c-format */
829 (_("%B: 0x%lx: warning: could not find expected reloc"),
830 abfd
, (unsigned long) paddr
);
834 /* Get the value of the symbol referred to by the reloc. */
835 if (! _bfd_coff_get_external_symbols (abfd
))
837 bfd_coff_swap_sym_in (abfd
,
838 ((bfd_byte
*) obj_coff_external_syms (abfd
)
840 * bfd_coff_symesz (abfd
))),
842 if (sym
.n_scnum
!= 0 && sym
.n_scnum
!= sec
->target_index
)
845 /* xgettext: c-format */
846 (_("%B: 0x%lx: warning: symbol in unexpected section"),
847 abfd
, (unsigned long) paddr
);
851 if (sym
.n_sclass
!= C_EXT
)
853 symval
= (sym
.n_value
855 + sec
->output_section
->vma
856 + sec
->output_offset
);
860 struct coff_link_hash_entry
*h
;
862 h
= obj_coff_sym_hashes (abfd
)[irelfn
->r_symndx
];
863 BFD_ASSERT (h
!= NULL
);
864 if (h
->root
.type
!= bfd_link_hash_defined
865 && h
->root
.type
!= bfd_link_hash_defweak
)
867 /* This appears to be a reference to an undefined
868 symbol. Just ignore it--it will be caught by the
869 regular reloc processing. */
873 symval
= (h
->root
.u
.def
.value
874 + h
->root
.u
.def
.section
->output_section
->vma
875 + h
->root
.u
.def
.section
->output_offset
);
878 symval
+= bfd_get_32 (abfd
, contents
+ paddr
- sec
->vma
);
880 /* See if this function call can be shortened. */
884 + sec
->output_section
->vma
887 if (foff
< -0x1000 || foff
>= 0x1000)
889 /* After all that work, we can't shorten this function call. */
893 /* Shorten the function call. */
895 /* For simplicity of coding, we are going to modify the section
896 contents, the section relocs, and the BFD symbol table. We
897 must tell the rest of the code not to free up this
898 information. It would be possible to instead create a table
899 of changes which have to be made, as is done in coff-mips.c;
900 that would be more work, but would require less memory when
901 the linker is run. */
903 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
904 coff_section_data (abfd
, sec
)->keep_relocs
= TRUE
;
906 coff_section_data (abfd
, sec
)->contents
= contents
;
907 coff_section_data (abfd
, sec
)->keep_contents
= TRUE
;
909 obj_coff_keep_syms (abfd
) = TRUE
;
911 /* Replace the jsr with a bsr. */
913 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
914 replace the jsr with a bsr. */
915 irel
->r_type
= R_SH_PCDISP
;
916 irel
->r_symndx
= irelfn
->r_symndx
;
917 if (sym
.n_sclass
!= C_EXT
)
919 /* If this needs to be changed because of future relaxing,
920 it will be handled here like other internal PCDISP
923 (bfd_vma
) 0xb000 | ((foff
>> 1) & 0xfff),
924 contents
+ irel
->r_vaddr
- sec
->vma
);
928 /* We can't fully resolve this yet, because the external
929 symbol value may be changed by future relaxing. We let
930 the final link phase handle it. */
931 bfd_put_16 (abfd
, (bfd_vma
) 0xb000,
932 contents
+ irel
->r_vaddr
- sec
->vma
);
935 /* See if there is another R_SH_USES reloc referring to the same
937 for (irelscan
= internal_relocs
; irelscan
< irelend
; irelscan
++)
938 if (irelscan
->r_type
== R_SH_USES
939 && laddr
== irelscan
->r_vaddr
- sec
->vma
+ 4 + irelscan
->r_offset
)
941 if (irelscan
< irelend
)
943 /* Some other function call depends upon this register load,
944 and we have not yet converted that function call.
945 Indeed, we may never be able to convert it. There is
946 nothing else we can do at this point. */
950 /* Look for a R_SH_COUNT reloc on the location where the
951 function address is stored. Do this before deleting any
952 bytes, to avoid confusion about the address. */
953 for (irelcount
= internal_relocs
; irelcount
< irelend
; irelcount
++)
954 if (irelcount
->r_vaddr
== paddr
955 && irelcount
->r_type
== R_SH_COUNT
)
958 /* Delete the register load. */
959 if (! sh_relax_delete_bytes (abfd
, sec
, laddr
, 2))
962 /* That will change things, so, just in case it permits some
963 other function call to come within range, we should relax
964 again. Note that this is not required, and it may be slow. */
967 /* Now check whether we got a COUNT reloc. */
968 if (irelcount
>= irelend
)
971 /* xgettext: c-format */
972 (_("%B: 0x%lx: warning: could not find expected COUNT reloc"),
973 abfd
, (unsigned long) paddr
);
977 /* The number of uses is stored in the r_offset field. We've
979 if (irelcount
->r_offset
== 0)
981 /* xgettext: c-format */
982 _bfd_error_handler (_("%B: 0x%lx: warning: bad count"),
983 abfd
, (unsigned long) paddr
);
987 --irelcount
->r_offset
;
989 /* If there are no more uses, we can delete the address. Reload
990 the address from irelfn, in case it was changed by the
991 previous call to sh_relax_delete_bytes. */
992 if (irelcount
->r_offset
== 0)
994 if (! sh_relax_delete_bytes (abfd
, sec
,
995 irelfn
->r_vaddr
- sec
->vma
, 4))
999 /* We've done all we can with that function call. */
1002 /* Look for load and store instructions that we can align on four
1006 bfd_boolean swapped
;
1008 /* Get the section contents. */
1009 if (contents
== NULL
)
1011 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
1012 contents
= coff_section_data (abfd
, sec
)->contents
;
1015 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
1020 if (! sh_align_loads (abfd
, sec
, internal_relocs
, contents
, &swapped
))
1025 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1026 coff_section_data (abfd
, sec
)->keep_relocs
= TRUE
;
1028 coff_section_data (abfd
, sec
)->contents
= contents
;
1029 coff_section_data (abfd
, sec
)->keep_contents
= TRUE
;
1031 obj_coff_keep_syms (abfd
) = TRUE
;
1035 if (internal_relocs
!= NULL
1036 && internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1038 if (! link_info
->keep_memory
)
1039 free (internal_relocs
);
1041 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1044 if (contents
!= NULL
&& contents
!= coff_section_data (abfd
, sec
)->contents
)
1046 if (! link_info
->keep_memory
)
1049 /* Cache the section contents for coff_link_input_bfd. */
1050 coff_section_data (abfd
, sec
)->contents
= contents
;
1056 if (internal_relocs
!= NULL
1057 && internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1058 free (internal_relocs
);
1059 if (contents
!= NULL
&& contents
!= coff_section_data (abfd
, sec
)->contents
)
1064 /* Delete some bytes from a section while relaxing. */
1067 sh_relax_delete_bytes (bfd
*abfd
,
1073 struct internal_reloc
*irel
, *irelend
;
1074 struct internal_reloc
*irelalign
;
1076 bfd_byte
*esym
, *esymend
;
1077 bfd_size_type symesz
;
1078 struct coff_link_hash_entry
**sym_hash
;
1081 contents
= coff_section_data (abfd
, sec
)->contents
;
1083 /* The deletion must stop at the next ALIGN reloc for an aligment
1084 power larger than the number of bytes we are deleting. */
1089 irel
= coff_section_data (abfd
, sec
)->relocs
;
1090 irelend
= irel
+ sec
->reloc_count
;
1091 for (; irel
< irelend
; irel
++)
1093 if (irel
->r_type
== R_SH_ALIGN
1094 && irel
->r_vaddr
- sec
->vma
> addr
1095 && count
< (1 << irel
->r_offset
))
1098 toaddr
= irel
->r_vaddr
- sec
->vma
;
1103 /* Actually delete the bytes. */
1104 memmove (contents
+ addr
, contents
+ addr
+ count
,
1105 (size_t) (toaddr
- addr
- count
));
1106 if (irelalign
== NULL
)
1112 #define NOP_OPCODE (0x0009)
1114 BFD_ASSERT ((count
& 1) == 0);
1115 for (i
= 0; i
< count
; i
+= 2)
1116 bfd_put_16 (abfd
, (bfd_vma
) NOP_OPCODE
, contents
+ toaddr
- count
+ i
);
1119 /* Adjust all the relocs. */
1120 for (irel
= coff_section_data (abfd
, sec
)->relocs
; irel
< irelend
; irel
++)
1122 bfd_vma nraddr
, stop
;
1125 struct internal_syment sym
;
1126 int off
, adjust
, oinsn
;
1127 bfd_signed_vma voff
= 0;
1128 bfd_boolean overflow
;
1130 /* Get the new reloc address. */
1131 nraddr
= irel
->r_vaddr
- sec
->vma
;
1132 if ((irel
->r_vaddr
- sec
->vma
> addr
1133 && irel
->r_vaddr
- sec
->vma
< toaddr
)
1134 || (irel
->r_type
== R_SH_ALIGN
1135 && irel
->r_vaddr
- sec
->vma
== toaddr
))
1138 /* See if this reloc was for the bytes we have deleted, in which
1139 case we no longer care about it. Don't delete relocs which
1140 represent addresses, though. */
1141 if (irel
->r_vaddr
- sec
->vma
>= addr
1142 && irel
->r_vaddr
- sec
->vma
< addr
+ count
1143 && irel
->r_type
!= R_SH_ALIGN
1144 && irel
->r_type
!= R_SH_CODE
1145 && irel
->r_type
!= R_SH_DATA
1146 && irel
->r_type
!= R_SH_LABEL
)
1147 irel
->r_type
= R_SH_UNUSED
;
1149 /* If this is a PC relative reloc, see if the range it covers
1150 includes the bytes we have deleted. */
1151 switch (irel
->r_type
)
1156 case R_SH_PCDISP8BY2
:
1158 case R_SH_PCRELIMM8BY2
:
1159 case R_SH_PCRELIMM8BY4
:
1160 start
= irel
->r_vaddr
- sec
->vma
;
1161 insn
= bfd_get_16 (abfd
, contents
+ nraddr
);
1165 switch (irel
->r_type
)
1168 start
= stop
= addr
;
1174 case R_SH_IMAGEBASE
:
1176 /* If this reloc is against a symbol defined in this
1177 section, and the symbol will not be adjusted below, we
1178 must check the addend to see it will put the value in
1179 range to be adjusted, and hence must be changed. */
1180 bfd_coff_swap_sym_in (abfd
,
1181 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1183 * bfd_coff_symesz (abfd
))),
1185 if (sym
.n_sclass
!= C_EXT
1186 && sym
.n_scnum
== sec
->target_index
1187 && ((bfd_vma
) sym
.n_value
<= addr
1188 || (bfd_vma
) sym
.n_value
>= toaddr
))
1192 val
= bfd_get_32 (abfd
, contents
+ nraddr
);
1194 if (val
> addr
&& val
< toaddr
)
1195 bfd_put_32 (abfd
, val
- count
, contents
+ nraddr
);
1197 start
= stop
= addr
;
1200 case R_SH_PCDISP8BY2
:
1204 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1208 bfd_coff_swap_sym_in (abfd
,
1209 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1211 * bfd_coff_symesz (abfd
))),
1213 if (sym
.n_sclass
== C_EXT
)
1214 start
= stop
= addr
;
1220 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1224 case R_SH_PCRELIMM8BY2
:
1226 stop
= start
+ 4 + off
* 2;
1229 case R_SH_PCRELIMM8BY4
:
1231 stop
= (start
&~ (bfd_vma
) 3) + 4 + off
* 4;
1237 /* These relocs types represent
1239 The r_offset field holds the difference between the reloc
1240 address and L1. That is the start of the reloc, and
1241 adding in the contents gives us the top. We must adjust
1242 both the r_offset field and the section contents. */
1244 start
= irel
->r_vaddr
- sec
->vma
;
1245 stop
= (bfd_vma
) ((bfd_signed_vma
) start
- (long) irel
->r_offset
);
1249 && (stop
<= addr
|| stop
>= toaddr
))
1250 irel
->r_offset
+= count
;
1251 else if (stop
> addr
1253 && (start
<= addr
|| start
>= toaddr
))
1254 irel
->r_offset
-= count
;
1258 if (irel
->r_type
== R_SH_SWITCH16
)
1259 voff
= bfd_get_signed_16 (abfd
, contents
+ nraddr
);
1260 else if (irel
->r_type
== R_SH_SWITCH8
)
1261 voff
= bfd_get_8 (abfd
, contents
+ nraddr
);
1263 voff
= bfd_get_signed_32 (abfd
, contents
+ nraddr
);
1264 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ voff
);
1269 start
= irel
->r_vaddr
- sec
->vma
;
1270 stop
= (bfd_vma
) ((bfd_signed_vma
) start
1271 + (long) irel
->r_offset
1278 && (stop
<= addr
|| stop
>= toaddr
))
1280 else if (stop
> addr
1282 && (start
<= addr
|| start
>= toaddr
))
1291 switch (irel
->r_type
)
1297 case R_SH_PCDISP8BY2
:
1298 case R_SH_PCRELIMM8BY2
:
1300 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1302 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1307 if ((oinsn
& 0xf000) != (insn
& 0xf000))
1309 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1312 case R_SH_PCRELIMM8BY4
:
1313 BFD_ASSERT (adjust
== count
|| count
>= 4);
1318 if ((irel
->r_vaddr
& 3) == 0)
1321 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1323 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1328 if (voff
< 0 || voff
>= 0xff)
1330 bfd_put_8 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1335 if (voff
< - 0x8000 || voff
>= 0x8000)
1337 bfd_put_signed_16 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1342 bfd_put_signed_32 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1346 irel
->r_offset
+= adjust
;
1353 /* xgettext: c-format */
1354 (_("%B: 0x%lx: fatal: reloc overflow while relaxing"),
1355 abfd
, (unsigned long) irel
->r_vaddr
);
1356 bfd_set_error (bfd_error_bad_value
);
1361 irel
->r_vaddr
= nraddr
+ sec
->vma
;
1364 /* Look through all the other sections. If there contain any IMM32
1365 relocs against internal symbols which we are not going to adjust
1366 below, we may need to adjust the addends. */
1367 for (o
= abfd
->sections
; o
!= NULL
; o
= o
->next
)
1369 struct internal_reloc
*internal_relocs
;
1370 struct internal_reloc
*irelscan
, *irelscanend
;
1371 bfd_byte
*ocontents
;
1374 || (o
->flags
& SEC_RELOC
) == 0
1375 || o
->reloc_count
== 0)
1378 /* We always cache the relocs. Perhaps, if info->keep_memory is
1379 FALSE, we should free them, if we are permitted to, when we
1380 leave sh_coff_relax_section. */
1381 internal_relocs
= (_bfd_coff_read_internal_relocs
1382 (abfd
, o
, TRUE
, (bfd_byte
*) NULL
, FALSE
,
1383 (struct internal_reloc
*) NULL
));
1384 if (internal_relocs
== NULL
)
1388 irelscanend
= internal_relocs
+ o
->reloc_count
;
1389 for (irelscan
= internal_relocs
; irelscan
< irelscanend
; irelscan
++)
1391 struct internal_syment sym
;
1394 if (irelscan
->r_type
!= R_SH_IMM32
1395 && irelscan
->r_type
!= R_SH_IMAGEBASE
1396 && irelscan
->r_type
!= R_SH_IMM32CE
)
1398 if (irelscan
->r_type
!= R_SH_IMM32
)
1402 bfd_coff_swap_sym_in (abfd
,
1403 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1404 + (irelscan
->r_symndx
1405 * bfd_coff_symesz (abfd
))),
1407 if (sym
.n_sclass
!= C_EXT
1408 && sym
.n_scnum
== sec
->target_index
1409 && ((bfd_vma
) sym
.n_value
<= addr
1410 || (bfd_vma
) sym
.n_value
>= toaddr
))
1414 if (ocontents
== NULL
)
1416 if (coff_section_data (abfd
, o
)->contents
!= NULL
)
1417 ocontents
= coff_section_data (abfd
, o
)->contents
;
1420 if (!bfd_malloc_and_get_section (abfd
, o
, &ocontents
))
1422 /* We always cache the section contents.
1423 Perhaps, if info->keep_memory is FALSE, we
1424 should free them, if we are permitted to,
1425 when we leave sh_coff_relax_section. */
1426 coff_section_data (abfd
, o
)->contents
= ocontents
;
1430 val
= bfd_get_32 (abfd
, ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1432 if (val
> addr
&& val
< toaddr
)
1433 bfd_put_32 (abfd
, val
- count
,
1434 ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1436 coff_section_data (abfd
, o
)->keep_contents
= TRUE
;
1441 /* Adjusting the internal symbols will not work if something has
1442 already retrieved the generic symbols. It would be possible to
1443 make this work by adjusting the generic symbols at the same time.
1444 However, this case should not arise in normal usage. */
1445 if (obj_symbols (abfd
) != NULL
1446 || obj_raw_syments (abfd
) != NULL
)
1449 (_("%B: fatal: generic symbols retrieved before relaxing"), abfd
);
1450 bfd_set_error (bfd_error_invalid_operation
);
1454 /* Adjust all the symbols. */
1455 sym_hash
= obj_coff_sym_hashes (abfd
);
1456 symesz
= bfd_coff_symesz (abfd
);
1457 esym
= (bfd_byte
*) obj_coff_external_syms (abfd
);
1458 esymend
= esym
+ obj_raw_syment_count (abfd
) * symesz
;
1459 while (esym
< esymend
)
1461 struct internal_syment isym
;
1463 bfd_coff_swap_sym_in (abfd
, esym
, &isym
);
1465 if (isym
.n_scnum
== sec
->target_index
1466 && (bfd_vma
) isym
.n_value
> addr
1467 && (bfd_vma
) isym
.n_value
< toaddr
)
1469 isym
.n_value
-= count
;
1471 bfd_coff_swap_sym_out (abfd
, &isym
, esym
);
1473 if (*sym_hash
!= NULL
)
1475 BFD_ASSERT ((*sym_hash
)->root
.type
== bfd_link_hash_defined
1476 || (*sym_hash
)->root
.type
== bfd_link_hash_defweak
);
1477 BFD_ASSERT ((*sym_hash
)->root
.u
.def
.value
>= addr
1478 && (*sym_hash
)->root
.u
.def
.value
< toaddr
);
1479 (*sym_hash
)->root
.u
.def
.value
-= count
;
1483 esym
+= (isym
.n_numaux
+ 1) * symesz
;
1484 sym_hash
+= isym
.n_numaux
+ 1;
1487 /* See if we can move the ALIGN reloc forward. We have adjusted
1488 r_vaddr for it already. */
1489 if (irelalign
!= NULL
)
1491 bfd_vma alignto
, alignaddr
;
1493 alignto
= BFD_ALIGN (toaddr
, 1 << irelalign
->r_offset
);
1494 alignaddr
= BFD_ALIGN (irelalign
->r_vaddr
- sec
->vma
,
1495 1 << irelalign
->r_offset
);
1496 if (alignto
!= alignaddr
)
1498 /* Tail recursion. */
1499 return sh_relax_delete_bytes (abfd
, sec
, alignaddr
,
1500 (int) (alignto
- alignaddr
));
1507 /* This is yet another version of the SH opcode table, used to rapidly
1508 get information about a particular instruction. */
1510 /* The opcode map is represented by an array of these structures. The
1511 array is indexed by the high order four bits in the instruction. */
1513 struct sh_major_opcode
1515 /* A pointer to the instruction list. This is an array which
1516 contains all the instructions with this major opcode. */
1517 const struct sh_minor_opcode
*minor_opcodes
;
1518 /* The number of elements in minor_opcodes. */
1519 unsigned short count
;
1522 /* This structure holds information for a set of SH opcodes. The
1523 instruction code is anded with the mask value, and the resulting
1524 value is used to search the order opcode list. */
1526 struct sh_minor_opcode
1528 /* The sorted opcode list. */
1529 const struct sh_opcode
*opcodes
;
1530 /* The number of elements in opcodes. */
1531 unsigned short count
;
1532 /* The mask value to use when searching the opcode list. */
1533 unsigned short mask
;
1536 /* This structure holds information for an SH instruction. An array
1537 of these structures is sorted in order by opcode. */
1541 /* The code for this instruction, after it has been anded with the
1542 mask value in the sh_major_opcode structure. */
1543 unsigned short opcode
;
1544 /* Flags for this instruction. */
1545 unsigned long flags
;
1548 /* Flag which appear in the sh_opcode structure. */
1550 /* This instruction loads a value from memory. */
1553 /* This instruction stores a value to memory. */
1556 /* This instruction is a branch. */
1557 #define BRANCH (0x4)
1559 /* This instruction has a delay slot. */
1562 /* This instruction uses the value in the register in the field at
1563 mask 0x0f00 of the instruction. */
1564 #define USES1 (0x10)
1565 #define USES1_REG(x) ((x & 0x0f00) >> 8)
1567 /* This instruction uses the value in the register in the field at
1568 mask 0x00f0 of the instruction. */
1569 #define USES2 (0x20)
1570 #define USES2_REG(x) ((x & 0x00f0) >> 4)
1572 /* This instruction uses the value in register 0. */
1573 #define USESR0 (0x40)
1575 /* This instruction sets the value in the register in the field at
1576 mask 0x0f00 of the instruction. */
1577 #define SETS1 (0x80)
1578 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
1580 /* This instruction sets the value in the register in the field at
1581 mask 0x00f0 of the instruction. */
1582 #define SETS2 (0x100)
1583 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
1585 /* This instruction sets register 0. */
1586 #define SETSR0 (0x200)
1588 /* This instruction sets a special register. */
1589 #define SETSSP (0x400)
1591 /* This instruction uses a special register. */
1592 #define USESSP (0x800)
1594 /* This instruction uses the floating point register in the field at
1595 mask 0x0f00 of the instruction. */
1596 #define USESF1 (0x1000)
1597 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
1599 /* This instruction uses the floating point register in the field at
1600 mask 0x00f0 of the instruction. */
1601 #define USESF2 (0x2000)
1602 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
1604 /* This instruction uses floating point register 0. */
1605 #define USESF0 (0x4000)
1607 /* This instruction sets the floating point register in the field at
1608 mask 0x0f00 of the instruction. */
1609 #define SETSF1 (0x8000)
1610 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1612 #define USESAS (0x10000)
1613 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1614 #define USESR8 (0x20000)
1615 #define SETSAS (0x40000)
1616 #define SETSAS_REG(x) USESAS_REG (x)
1618 #define MAP(a) a, sizeof a / sizeof a[0]
1620 #ifndef COFF_IMAGE_WITH_PE
1622 /* The opcode maps. */
1624 static const struct sh_opcode sh_opcode00
[] =
1626 { 0x0008, SETSSP
}, /* clrt */
1627 { 0x0009, 0 }, /* nop */
1628 { 0x000b, BRANCH
| DELAY
| USESSP
}, /* rts */
1629 { 0x0018, SETSSP
}, /* sett */
1630 { 0x0019, SETSSP
}, /* div0u */
1631 { 0x001b, 0 }, /* sleep */
1632 { 0x0028, SETSSP
}, /* clrmac */
1633 { 0x002b, BRANCH
| DELAY
| SETSSP
}, /* rte */
1634 { 0x0038, USESSP
| SETSSP
}, /* ldtlb */
1635 { 0x0048, SETSSP
}, /* clrs */
1636 { 0x0058, SETSSP
} /* sets */
1639 static const struct sh_opcode sh_opcode01
[] =
1641 { 0x0003, BRANCH
| DELAY
| USES1
| SETSSP
}, /* bsrf rn */
1642 { 0x000a, SETS1
| USESSP
}, /* sts mach,rn */
1643 { 0x001a, SETS1
| USESSP
}, /* sts macl,rn */
1644 { 0x0023, BRANCH
| DELAY
| USES1
}, /* braf rn */
1645 { 0x0029, SETS1
| USESSP
}, /* movt rn */
1646 { 0x002a, SETS1
| USESSP
}, /* sts pr,rn */
1647 { 0x005a, SETS1
| USESSP
}, /* sts fpul,rn */
1648 { 0x006a, SETS1
| USESSP
}, /* sts fpscr,rn / sts dsr,rn */
1649 { 0x0083, LOAD
| USES1
}, /* pref @rn */
1650 { 0x007a, SETS1
| USESSP
}, /* sts a0,rn */
1651 { 0x008a, SETS1
| USESSP
}, /* sts x0,rn */
1652 { 0x009a, SETS1
| USESSP
}, /* sts x1,rn */
1653 { 0x00aa, SETS1
| USESSP
}, /* sts y0,rn */
1654 { 0x00ba, SETS1
| USESSP
} /* sts y1,rn */
1657 static const struct sh_opcode sh_opcode02
[] =
1659 { 0x0002, SETS1
| USESSP
}, /* stc <special_reg>,rn */
1660 { 0x0004, STORE
| USES1
| USES2
| USESR0
}, /* mov.b rm,@(r0,rn) */
1661 { 0x0005, STORE
| USES1
| USES2
| USESR0
}, /* mov.w rm,@(r0,rn) */
1662 { 0x0006, STORE
| USES1
| USES2
| USESR0
}, /* mov.l rm,@(r0,rn) */
1663 { 0x0007, SETSSP
| USES1
| USES2
}, /* mul.l rm,rn */
1664 { 0x000c, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.b @(r0,rm),rn */
1665 { 0x000d, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.w @(r0,rm),rn */
1666 { 0x000e, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.l @(r0,rm),rn */
1667 { 0x000f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.l @rm+,@rn+ */
1670 static const struct sh_minor_opcode sh_opcode0
[] =
1672 { MAP (sh_opcode00
), 0xffff },
1673 { MAP (sh_opcode01
), 0xf0ff },
1674 { MAP (sh_opcode02
), 0xf00f }
1677 static const struct sh_opcode sh_opcode10
[] =
1679 { 0x1000, STORE
| USES1
| USES2
} /* mov.l rm,@(disp,rn) */
1682 static const struct sh_minor_opcode sh_opcode1
[] =
1684 { MAP (sh_opcode10
), 0xf000 }
1687 static const struct sh_opcode sh_opcode20
[] =
1689 { 0x2000, STORE
| USES1
| USES2
}, /* mov.b rm,@rn */
1690 { 0x2001, STORE
| USES1
| USES2
}, /* mov.w rm,@rn */
1691 { 0x2002, STORE
| USES1
| USES2
}, /* mov.l rm,@rn */
1692 { 0x2004, STORE
| SETS1
| USES1
| USES2
}, /* mov.b rm,@-rn */
1693 { 0x2005, STORE
| SETS1
| USES1
| USES2
}, /* mov.w rm,@-rn */
1694 { 0x2006, STORE
| SETS1
| USES1
| USES2
}, /* mov.l rm,@-rn */
1695 { 0x2007, SETSSP
| USES1
| USES2
| USESSP
}, /* div0s */
1696 { 0x2008, SETSSP
| USES1
| USES2
}, /* tst rm,rn */
1697 { 0x2009, SETS1
| USES1
| USES2
}, /* and rm,rn */
1698 { 0x200a, SETS1
| USES1
| USES2
}, /* xor rm,rn */
1699 { 0x200b, SETS1
| USES1
| USES2
}, /* or rm,rn */
1700 { 0x200c, SETSSP
| USES1
| USES2
}, /* cmp/str rm,rn */
1701 { 0x200d, SETS1
| USES1
| USES2
}, /* xtrct rm,rn */
1702 { 0x200e, SETSSP
| USES1
| USES2
}, /* mulu.w rm,rn */
1703 { 0x200f, SETSSP
| USES1
| USES2
} /* muls.w rm,rn */
1706 static const struct sh_minor_opcode sh_opcode2
[] =
1708 { MAP (sh_opcode20
), 0xf00f }
1711 static const struct sh_opcode sh_opcode30
[] =
1713 { 0x3000, SETSSP
| USES1
| USES2
}, /* cmp/eq rm,rn */
1714 { 0x3002, SETSSP
| USES1
| USES2
}, /* cmp/hs rm,rn */
1715 { 0x3003, SETSSP
| USES1
| USES2
}, /* cmp/ge rm,rn */
1716 { 0x3004, SETSSP
| USESSP
| USES1
| USES2
}, /* div1 rm,rn */
1717 { 0x3005, SETSSP
| USES1
| USES2
}, /* dmulu.l rm,rn */
1718 { 0x3006, SETSSP
| USES1
| USES2
}, /* cmp/hi rm,rn */
1719 { 0x3007, SETSSP
| USES1
| USES2
}, /* cmp/gt rm,rn */
1720 { 0x3008, SETS1
| USES1
| USES2
}, /* sub rm,rn */
1721 { 0x300a, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* subc rm,rn */
1722 { 0x300b, SETS1
| SETSSP
| USES1
| USES2
}, /* subv rm,rn */
1723 { 0x300c, SETS1
| USES1
| USES2
}, /* add rm,rn */
1724 { 0x300d, SETSSP
| USES1
| USES2
}, /* dmuls.l rm,rn */
1725 { 0x300e, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* addc rm,rn */
1726 { 0x300f, SETS1
| SETSSP
| USES1
| USES2
} /* addv rm,rn */
1729 static const struct sh_minor_opcode sh_opcode3
[] =
1731 { MAP (sh_opcode30
), 0xf00f }
1734 static const struct sh_opcode sh_opcode40
[] =
1736 { 0x4000, SETS1
| SETSSP
| USES1
}, /* shll rn */
1737 { 0x4001, SETS1
| SETSSP
| USES1
}, /* shlr rn */
1738 { 0x4002, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l mach,@-rn */
1739 { 0x4004, SETS1
| SETSSP
| USES1
}, /* rotl rn */
1740 { 0x4005, SETS1
| SETSSP
| USES1
}, /* rotr rn */
1741 { 0x4006, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,mach */
1742 { 0x4008, SETS1
| USES1
}, /* shll2 rn */
1743 { 0x4009, SETS1
| USES1
}, /* shlr2 rn */
1744 { 0x400a, SETSSP
| USES1
}, /* lds rm,mach */
1745 { 0x400b, BRANCH
| DELAY
| USES1
}, /* jsr @rn */
1746 { 0x4010, SETS1
| SETSSP
| USES1
}, /* dt rn */
1747 { 0x4011, SETSSP
| USES1
}, /* cmp/pz rn */
1748 { 0x4012, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l macl,@-rn */
1749 { 0x4014, SETSSP
| USES1
}, /* setrc rm */
1750 { 0x4015, SETSSP
| USES1
}, /* cmp/pl rn */
1751 { 0x4016, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,macl */
1752 { 0x4018, SETS1
| USES1
}, /* shll8 rn */
1753 { 0x4019, SETS1
| USES1
}, /* shlr8 rn */
1754 { 0x401a, SETSSP
| USES1
}, /* lds rm,macl */
1755 { 0x401b, LOAD
| SETSSP
| USES1
}, /* tas.b @rn */
1756 { 0x4020, SETS1
| SETSSP
| USES1
}, /* shal rn */
1757 { 0x4021, SETS1
| SETSSP
| USES1
}, /* shar rn */
1758 { 0x4022, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l pr,@-rn */
1759 { 0x4024, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcl rn */
1760 { 0x4025, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcr rn */
1761 { 0x4026, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,pr */
1762 { 0x4028, SETS1
| USES1
}, /* shll16 rn */
1763 { 0x4029, SETS1
| USES1
}, /* shlr16 rn */
1764 { 0x402a, SETSSP
| USES1
}, /* lds rm,pr */
1765 { 0x402b, BRANCH
| DELAY
| USES1
}, /* jmp @rn */
1766 { 0x4052, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpul,@-rn */
1767 { 0x4056, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpul */
1768 { 0x405a, SETSSP
| USES1
}, /* lds.l rm,fpul */
1769 { 0x4062, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpscr / dsr,@-rn */
1770 { 0x4066, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpscr / dsr */
1771 { 0x406a, SETSSP
| USES1
}, /* lds rm,fpscr / lds rm,dsr */
1772 { 0x4072, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l a0,@-rn */
1773 { 0x4076, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,a0 */
1774 { 0x407a, SETSSP
| USES1
}, /* lds.l rm,a0 */
1775 { 0x4082, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x0,@-rn */
1776 { 0x4086, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x0 */
1777 { 0x408a, SETSSP
| USES1
}, /* lds.l rm,x0 */
1778 { 0x4092, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x1,@-rn */
1779 { 0x4096, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x1 */
1780 { 0x409a, SETSSP
| USES1
}, /* lds.l rm,x1 */
1781 { 0x40a2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y0,@-rn */
1782 { 0x40a6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y0 */
1783 { 0x40aa, SETSSP
| USES1
}, /* lds.l rm,y0 */
1784 { 0x40b2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y1,@-rn */
1785 { 0x40b6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y1 */
1786 { 0x40ba, SETSSP
| USES1
} /* lds.l rm,y1 */
1789 static const struct sh_opcode sh_opcode41
[] =
1791 { 0x4003, STORE
| SETS1
| USES1
| USESSP
}, /* stc.l <special_reg>,@-rn */
1792 { 0x4007, LOAD
| SETS1
| SETSSP
| USES1
}, /* ldc.l @rm+,<special_reg> */
1793 { 0x400c, SETS1
| USES1
| USES2
}, /* shad rm,rn */
1794 { 0x400d, SETS1
| USES1
| USES2
}, /* shld rm,rn */
1795 { 0x400e, SETSSP
| USES1
}, /* ldc rm,<special_reg> */
1796 { 0x400f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.w @rm+,@rn+ */
1799 static const struct sh_minor_opcode sh_opcode4
[] =
1801 { MAP (sh_opcode40
), 0xf0ff },
1802 { MAP (sh_opcode41
), 0xf00f }
1805 static const struct sh_opcode sh_opcode50
[] =
1807 { 0x5000, LOAD
| SETS1
| USES2
} /* mov.l @(disp,rm),rn */
1810 static const struct sh_minor_opcode sh_opcode5
[] =
1812 { MAP (sh_opcode50
), 0xf000 }
1815 static const struct sh_opcode sh_opcode60
[] =
1817 { 0x6000, LOAD
| SETS1
| USES2
}, /* mov.b @rm,rn */
1818 { 0x6001, LOAD
| SETS1
| USES2
}, /* mov.w @rm,rn */
1819 { 0x6002, LOAD
| SETS1
| USES2
}, /* mov.l @rm,rn */
1820 { 0x6003, SETS1
| USES2
}, /* mov rm,rn */
1821 { 0x6004, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.b @rm+,rn */
1822 { 0x6005, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.w @rm+,rn */
1823 { 0x6006, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.l @rm+,rn */
1824 { 0x6007, SETS1
| USES2
}, /* not rm,rn */
1825 { 0x6008, SETS1
| USES2
}, /* swap.b rm,rn */
1826 { 0x6009, SETS1
| USES2
}, /* swap.w rm,rn */
1827 { 0x600a, SETS1
| SETSSP
| USES2
| USESSP
}, /* negc rm,rn */
1828 { 0x600b, SETS1
| USES2
}, /* neg rm,rn */
1829 { 0x600c, SETS1
| USES2
}, /* extu.b rm,rn */
1830 { 0x600d, SETS1
| USES2
}, /* extu.w rm,rn */
1831 { 0x600e, SETS1
| USES2
}, /* exts.b rm,rn */
1832 { 0x600f, SETS1
| USES2
} /* exts.w rm,rn */
1835 static const struct sh_minor_opcode sh_opcode6
[] =
1837 { MAP (sh_opcode60
), 0xf00f }
1840 static const struct sh_opcode sh_opcode70
[] =
1842 { 0x7000, SETS1
| USES1
} /* add #imm,rn */
1845 static const struct sh_minor_opcode sh_opcode7
[] =
1847 { MAP (sh_opcode70
), 0xf000 }
1850 static const struct sh_opcode sh_opcode80
[] =
1852 { 0x8000, STORE
| USES2
| USESR0
}, /* mov.b r0,@(disp,rn) */
1853 { 0x8100, STORE
| USES2
| USESR0
}, /* mov.w r0,@(disp,rn) */
1854 { 0x8200, SETSSP
}, /* setrc #imm */
1855 { 0x8400, LOAD
| SETSR0
| USES2
}, /* mov.b @(disp,rm),r0 */
1856 { 0x8500, LOAD
| SETSR0
| USES2
}, /* mov.w @(disp,rn),r0 */
1857 { 0x8800, SETSSP
| USESR0
}, /* cmp/eq #imm,r0 */
1858 { 0x8900, BRANCH
| USESSP
}, /* bt label */
1859 { 0x8b00, BRANCH
| USESSP
}, /* bf label */
1860 { 0x8c00, SETSSP
}, /* ldrs @(disp,pc) */
1861 { 0x8d00, BRANCH
| DELAY
| USESSP
}, /* bt/s label */
1862 { 0x8e00, SETSSP
}, /* ldre @(disp,pc) */
1863 { 0x8f00, BRANCH
| DELAY
| USESSP
} /* bf/s label */
1866 static const struct sh_minor_opcode sh_opcode8
[] =
1868 { MAP (sh_opcode80
), 0xff00 }
1871 static const struct sh_opcode sh_opcode90
[] =
1873 { 0x9000, LOAD
| SETS1
} /* mov.w @(disp,pc),rn */
1876 static const struct sh_minor_opcode sh_opcode9
[] =
1878 { MAP (sh_opcode90
), 0xf000 }
1881 static const struct sh_opcode sh_opcodea0
[] =
1883 { 0xa000, BRANCH
| DELAY
} /* bra label */
1886 static const struct sh_minor_opcode sh_opcodea
[] =
1888 { MAP (sh_opcodea0
), 0xf000 }
1891 static const struct sh_opcode sh_opcodeb0
[] =
1893 { 0xb000, BRANCH
| DELAY
} /* bsr label */
1896 static const struct sh_minor_opcode sh_opcodeb
[] =
1898 { MAP (sh_opcodeb0
), 0xf000 }
1901 static const struct sh_opcode sh_opcodec0
[] =
1903 { 0xc000, STORE
| USESR0
| USESSP
}, /* mov.b r0,@(disp,gbr) */
1904 { 0xc100, STORE
| USESR0
| USESSP
}, /* mov.w r0,@(disp,gbr) */
1905 { 0xc200, STORE
| USESR0
| USESSP
}, /* mov.l r0,@(disp,gbr) */
1906 { 0xc300, BRANCH
| USESSP
}, /* trapa #imm */
1907 { 0xc400, LOAD
| SETSR0
| USESSP
}, /* mov.b @(disp,gbr),r0 */
1908 { 0xc500, LOAD
| SETSR0
| USESSP
}, /* mov.w @(disp,gbr),r0 */
1909 { 0xc600, LOAD
| SETSR0
| USESSP
}, /* mov.l @(disp,gbr),r0 */
1910 { 0xc700, SETSR0
}, /* mova @(disp,pc),r0 */
1911 { 0xc800, SETSSP
| USESR0
}, /* tst #imm,r0 */
1912 { 0xc900, SETSR0
| USESR0
}, /* and #imm,r0 */
1913 { 0xca00, SETSR0
| USESR0
}, /* xor #imm,r0 */
1914 { 0xcb00, SETSR0
| USESR0
}, /* or #imm,r0 */
1915 { 0xcc00, LOAD
| SETSSP
| USESR0
| USESSP
}, /* tst.b #imm,@(r0,gbr) */
1916 { 0xcd00, LOAD
| STORE
| USESR0
| USESSP
}, /* and.b #imm,@(r0,gbr) */
1917 { 0xce00, LOAD
| STORE
| USESR0
| USESSP
}, /* xor.b #imm,@(r0,gbr) */
1918 { 0xcf00, LOAD
| STORE
| USESR0
| USESSP
} /* or.b #imm,@(r0,gbr) */
1921 static const struct sh_minor_opcode sh_opcodec
[] =
1923 { MAP (sh_opcodec0
), 0xff00 }
1926 static const struct sh_opcode sh_opcoded0
[] =
1928 { 0xd000, LOAD
| SETS1
} /* mov.l @(disp,pc),rn */
1931 static const struct sh_minor_opcode sh_opcoded
[] =
1933 { MAP (sh_opcoded0
), 0xf000 }
1936 static const struct sh_opcode sh_opcodee0
[] =
1938 { 0xe000, SETS1
} /* mov #imm,rn */
1941 static const struct sh_minor_opcode sh_opcodee
[] =
1943 { MAP (sh_opcodee0
), 0xf000 }
1946 static const struct sh_opcode sh_opcodef0
[] =
1948 { 0xf000, SETSF1
| USESF1
| USESF2
}, /* fadd fm,fn */
1949 { 0xf001, SETSF1
| USESF1
| USESF2
}, /* fsub fm,fn */
1950 { 0xf002, SETSF1
| USESF1
| USESF2
}, /* fmul fm,fn */
1951 { 0xf003, SETSF1
| USESF1
| USESF2
}, /* fdiv fm,fn */
1952 { 0xf004, SETSSP
| USESF1
| USESF2
}, /* fcmp/eq fm,fn */
1953 { 0xf005, SETSSP
| USESF1
| USESF2
}, /* fcmp/gt fm,fn */
1954 { 0xf006, LOAD
| SETSF1
| USES2
| USESR0
}, /* fmov.s @(r0,rm),fn */
1955 { 0xf007, STORE
| USES1
| USESF2
| USESR0
}, /* fmov.s fm,@(r0,rn) */
1956 { 0xf008, LOAD
| SETSF1
| USES2
}, /* fmov.s @rm,fn */
1957 { 0xf009, LOAD
| SETS2
| SETSF1
| USES2
}, /* fmov.s @rm+,fn */
1958 { 0xf00a, STORE
| USES1
| USESF2
}, /* fmov.s fm,@rn */
1959 { 0xf00b, STORE
| SETS1
| USES1
| USESF2
}, /* fmov.s fm,@-rn */
1960 { 0xf00c, SETSF1
| USESF2
}, /* fmov fm,fn */
1961 { 0xf00e, SETSF1
| USESF1
| USESF2
| USESF0
} /* fmac f0,fm,fn */
1964 static const struct sh_opcode sh_opcodef1
[] =
1966 { 0xf00d, SETSF1
| USESSP
}, /* fsts fpul,fn */
1967 { 0xf01d, SETSSP
| USESF1
}, /* flds fn,fpul */
1968 { 0xf02d, SETSF1
| USESSP
}, /* float fpul,fn */
1969 { 0xf03d, SETSSP
| USESF1
}, /* ftrc fn,fpul */
1970 { 0xf04d, SETSF1
| USESF1
}, /* fneg fn */
1971 { 0xf05d, SETSF1
| USESF1
}, /* fabs fn */
1972 { 0xf06d, SETSF1
| USESF1
}, /* fsqrt fn */
1973 { 0xf07d, SETSSP
| USESF1
}, /* ftst/nan fn */
1974 { 0xf08d, SETSF1
}, /* fldi0 fn */
1975 { 0xf09d, SETSF1
} /* fldi1 fn */
1978 static const struct sh_minor_opcode sh_opcodef
[] =
1980 { MAP (sh_opcodef0
), 0xf00f },
1981 { MAP (sh_opcodef1
), 0xf0ff }
1984 static struct sh_major_opcode sh_opcodes
[] =
1986 { MAP (sh_opcode0
) },
1987 { MAP (sh_opcode1
) },
1988 { MAP (sh_opcode2
) },
1989 { MAP (sh_opcode3
) },
1990 { MAP (sh_opcode4
) },
1991 { MAP (sh_opcode5
) },
1992 { MAP (sh_opcode6
) },
1993 { MAP (sh_opcode7
) },
1994 { MAP (sh_opcode8
) },
1995 { MAP (sh_opcode9
) },
1996 { MAP (sh_opcodea
) },
1997 { MAP (sh_opcodeb
) },
1998 { MAP (sh_opcodec
) },
1999 { MAP (sh_opcoded
) },
2000 { MAP (sh_opcodee
) },
2001 { MAP (sh_opcodef
) }
2004 /* The double data transfer / parallel processing insns are not
2005 described here. This will cause sh_align_load_span to leave them alone. */
2007 static const struct sh_opcode sh_dsp_opcodef0
[] =
2009 { 0xf400, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @-as,ds */
2010 { 0xf401, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@-as */
2011 { 0xf404, USESAS
| LOAD
| SETSSP
}, /* movs.x @as,ds */
2012 { 0xf405, USESAS
| STORE
| USESSP
}, /* movs.x ds,@as */
2013 { 0xf408, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @as+,ds */
2014 { 0xf409, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@as+ */
2015 { 0xf40c, USESAS
| SETSAS
| LOAD
| SETSSP
| USESR8
}, /* movs.x @as+r8,ds */
2016 { 0xf40d, USESAS
| SETSAS
| STORE
| USESSP
| USESR8
} /* movs.x ds,@as+r8 */
2019 static const struct sh_minor_opcode sh_dsp_opcodef
[] =
2021 { MAP (sh_dsp_opcodef0
), 0xfc0d }
2024 /* Given an instruction, return a pointer to the corresponding
2025 sh_opcode structure. Return NULL if the instruction is not
2028 static const struct sh_opcode
*
2029 sh_insn_info (unsigned int insn
)
2031 const struct sh_major_opcode
*maj
;
2032 const struct sh_minor_opcode
*min
, *minend
;
2034 maj
= &sh_opcodes
[(insn
& 0xf000) >> 12];
2035 min
= maj
->minor_opcodes
;
2036 minend
= min
+ maj
->count
;
2037 for (; min
< minend
; min
++)
2040 const struct sh_opcode
*op
, *opend
;
2042 l
= insn
& min
->mask
;
2044 opend
= op
+ min
->count
;
2046 /* Since the opcodes tables are sorted, we could use a binary
2047 search here if the count were above some cutoff value. */
2048 for (; op
< opend
; op
++)
2049 if (op
->opcode
== l
)
2056 /* See whether an instruction uses a general purpose register. */
2059 sh_insn_uses_reg (unsigned int insn
,
2060 const struct sh_opcode
*op
,
2067 if ((f
& USES1
) != 0
2068 && USES1_REG (insn
) == reg
)
2070 if ((f
& USES2
) != 0
2071 && USES2_REG (insn
) == reg
)
2073 if ((f
& USESR0
) != 0
2076 if ((f
& USESAS
) && reg
== USESAS_REG (insn
))
2078 if ((f
& USESR8
) && reg
== 8)
2084 /* See whether an instruction sets a general purpose register. */
2087 sh_insn_sets_reg (unsigned int insn
,
2088 const struct sh_opcode
*op
,
2095 if ((f
& SETS1
) != 0
2096 && SETS1_REG (insn
) == reg
)
2098 if ((f
& SETS2
) != 0
2099 && SETS2_REG (insn
) == reg
)
2101 if ((f
& SETSR0
) != 0
2104 if ((f
& SETSAS
) && reg
== SETSAS_REG (insn
))
2110 /* See whether an instruction uses or sets a general purpose register */
2113 sh_insn_uses_or_sets_reg (unsigned int insn
,
2114 const struct sh_opcode
*op
,
2117 if (sh_insn_uses_reg (insn
, op
, reg
))
2120 return sh_insn_sets_reg (insn
, op
, reg
);
2123 /* See whether an instruction uses a floating point register. */
2126 sh_insn_uses_freg (unsigned int insn
,
2127 const struct sh_opcode
*op
,
2134 /* We can't tell if this is a double-precision insn, so just play safe
2135 and assume that it might be. So not only have we test FREG against
2136 itself, but also even FREG against FREG+1 - if the using insn uses
2137 just the low part of a double precision value - but also an odd
2138 FREG against FREG-1 - if the setting insn sets just the low part
2139 of a double precision value.
2140 So what this all boils down to is that we have to ignore the lowest
2141 bit of the register number. */
2143 if ((f
& USESF1
) != 0
2144 && (USESF1_REG (insn
) & 0xe) == (freg
& 0xe))
2146 if ((f
& USESF2
) != 0
2147 && (USESF2_REG (insn
) & 0xe) == (freg
& 0xe))
2149 if ((f
& USESF0
) != 0
2156 /* See whether an instruction sets a floating point register. */
2159 sh_insn_sets_freg (unsigned int insn
,
2160 const struct sh_opcode
*op
,
2167 /* We can't tell if this is a double-precision insn, so just play safe
2168 and assume that it might be. So not only have we test FREG against
2169 itself, but also even FREG against FREG+1 - if the using insn uses
2170 just the low part of a double precision value - but also an odd
2171 FREG against FREG-1 - if the setting insn sets just the low part
2172 of a double precision value.
2173 So what this all boils down to is that we have to ignore the lowest
2174 bit of the register number. */
2176 if ((f
& SETSF1
) != 0
2177 && (SETSF1_REG (insn
) & 0xe) == (freg
& 0xe))
2183 /* See whether an instruction uses or sets a floating point register */
2186 sh_insn_uses_or_sets_freg (unsigned int insn
,
2187 const struct sh_opcode
*op
,
2190 if (sh_insn_uses_freg (insn
, op
, reg
))
2193 return sh_insn_sets_freg (insn
, op
, reg
);
2196 /* See whether instructions I1 and I2 conflict, assuming I1 comes
2197 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2198 This should return TRUE if there is a conflict, or FALSE if the
2199 instructions can be swapped safely. */
2202 sh_insns_conflict (unsigned int i1
,
2203 const struct sh_opcode
*op1
,
2205 const struct sh_opcode
*op2
)
2207 unsigned int f1
, f2
;
2212 /* Load of fpscr conflicts with floating point operations.
2213 FIXME: shouldn't test raw opcodes here. */
2214 if (((i1
& 0xf0ff) == 0x4066 && (i2
& 0xf000) == 0xf000)
2215 || ((i2
& 0xf0ff) == 0x4066 && (i1
& 0xf000) == 0xf000))
2218 if ((f1
& (BRANCH
| DELAY
)) != 0
2219 || (f2
& (BRANCH
| DELAY
)) != 0)
2222 if (((f1
| f2
) & SETSSP
)
2223 && (f1
& (SETSSP
| USESSP
))
2224 && (f2
& (SETSSP
| USESSP
)))
2227 if ((f1
& SETS1
) != 0
2228 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS1_REG (i1
)))
2230 if ((f1
& SETS2
) != 0
2231 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS2_REG (i1
)))
2233 if ((f1
& SETSR0
) != 0
2234 && sh_insn_uses_or_sets_reg (i2
, op2
, 0))
2237 && sh_insn_uses_or_sets_reg (i2
, op2
, SETSAS_REG (i1
)))
2239 if ((f1
& SETSF1
) != 0
2240 && sh_insn_uses_or_sets_freg (i2
, op2
, SETSF1_REG (i1
)))
2243 if ((f2
& SETS1
) != 0
2244 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS1_REG (i2
)))
2246 if ((f2
& SETS2
) != 0
2247 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS2_REG (i2
)))
2249 if ((f2
& SETSR0
) != 0
2250 && sh_insn_uses_or_sets_reg (i1
, op1
, 0))
2253 && sh_insn_uses_or_sets_reg (i1
, op1
, SETSAS_REG (i2
)))
2255 if ((f2
& SETSF1
) != 0
2256 && sh_insn_uses_or_sets_freg (i1
, op1
, SETSF1_REG (i2
)))
2259 /* The instructions do not conflict. */
2263 /* I1 is a load instruction, and I2 is some other instruction. Return
2264 TRUE if I1 loads a register which I2 uses. */
2267 sh_load_use (unsigned int i1
,
2268 const struct sh_opcode
*op1
,
2270 const struct sh_opcode
*op2
)
2276 if ((f1
& LOAD
) == 0)
2279 /* If both SETS1 and SETSSP are set, that means a load to a special
2280 register using postincrement addressing mode, which we don't care
2282 if ((f1
& SETS1
) != 0
2283 && (f1
& SETSSP
) == 0
2284 && sh_insn_uses_reg (i2
, op2
, (i1
& 0x0f00) >> 8))
2287 if ((f1
& SETSR0
) != 0
2288 && sh_insn_uses_reg (i2
, op2
, 0))
2291 if ((f1
& SETSF1
) != 0
2292 && sh_insn_uses_freg (i2
, op2
, (i1
& 0x0f00) >> 8))
2298 /* Try to align loads and stores within a span of memory. This is
2299 called by both the ELF and the COFF sh targets. ABFD and SEC are
2300 the BFD and section we are examining. CONTENTS is the contents of
2301 the section. SWAP is the routine to call to swap two instructions.
2302 RELOCS is a pointer to the internal relocation information, to be
2303 passed to SWAP. PLABEL is a pointer to the current label in a
2304 sorted list of labels; LABEL_END is the end of the list. START and
2305 STOP are the range of memory to examine. If a swap is made,
2306 *PSWAPPED is set to TRUE. */
2312 _bfd_sh_align_load_span (bfd
*abfd
,
2315 bfd_boolean (*swap
) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
2321 bfd_boolean
*pswapped
)
2323 int dsp
= (abfd
->arch_info
->mach
== bfd_mach_sh_dsp
2324 || abfd
->arch_info
->mach
== bfd_mach_sh3_dsp
);
2327 /* The SH4 has a Harvard architecture, hence aligning loads is not
2328 desirable. In fact, it is counter-productive, since it interferes
2329 with the schedules generated by the compiler. */
2330 if (abfd
->arch_info
->mach
== bfd_mach_sh4
)
2333 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2337 sh_opcodes
[0xf].minor_opcodes
= sh_dsp_opcodef
;
2338 sh_opcodes
[0xf].count
= sizeof sh_dsp_opcodef
/ sizeof sh_dsp_opcodef
[0];
2341 /* Instructions should be aligned on 2 byte boundaries. */
2342 if ((start
& 1) == 1)
2345 /* Now look through the unaligned addresses. */
2349 for (; i
< stop
; i
+= 4)
2352 const struct sh_opcode
*op
;
2353 unsigned int prev_insn
= 0;
2354 const struct sh_opcode
*prev_op
= NULL
;
2356 insn
= bfd_get_16 (abfd
, contents
+ i
);
2357 op
= sh_insn_info (insn
);
2359 || (op
->flags
& (LOAD
| STORE
)) == 0)
2362 /* This is a load or store which is not on a four byte boundary. */
2364 while (*plabel
< label_end
&& **plabel
< i
)
2369 prev_insn
= bfd_get_16 (abfd
, contents
+ i
- 2);
2370 /* If INSN is the field b of a parallel processing insn, it is not
2371 a load / store after all. Note that the test here might mistake
2372 the field_b of a pcopy insn for the starting code of a parallel
2373 processing insn; this might miss a swapping opportunity, but at
2374 least we're on the safe side. */
2375 if (dsp
&& (prev_insn
& 0xfc00) == 0xf800)
2378 /* Check if prev_insn is actually the field b of a parallel
2379 processing insn. Again, this can give a spurious match
2381 if (dsp
&& i
- 2 > start
)
2383 unsigned pprev_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2385 if ((pprev_insn
& 0xfc00) == 0xf800)
2388 prev_op
= sh_insn_info (prev_insn
);
2391 prev_op
= sh_insn_info (prev_insn
);
2393 /* If the load/store instruction is in a delay slot, we
2396 || (prev_op
->flags
& DELAY
) != 0)
2400 && (*plabel
>= label_end
|| **plabel
!= i
)
2402 && (prev_op
->flags
& (LOAD
| STORE
)) == 0
2403 && ! sh_insns_conflict (prev_insn
, prev_op
, insn
, op
))
2407 /* The load/store instruction does not have a label, and
2408 there is a previous instruction; PREV_INSN is not
2409 itself a load/store instruction, and PREV_INSN and
2410 INSN do not conflict. */
2416 unsigned int prev2_insn
;
2417 const struct sh_opcode
*prev2_op
;
2419 prev2_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2420 prev2_op
= sh_insn_info (prev2_insn
);
2422 /* If the instruction before PREV_INSN has a delay
2423 slot--that is, PREV_INSN is in a delay slot--we
2425 if (prev2_op
== NULL
2426 || (prev2_op
->flags
& DELAY
) != 0)
2429 /* If the instruction before PREV_INSN is a load,
2430 and it sets a register which INSN uses, then
2431 putting INSN immediately after PREV_INSN will
2432 cause a pipeline bubble, so there is no point to
2435 && (prev2_op
->flags
& LOAD
) != 0
2436 && sh_load_use (prev2_insn
, prev2_op
, insn
, op
))
2442 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
- 2))
2449 while (*plabel
< label_end
&& **plabel
< i
+ 2)
2453 && (*plabel
>= label_end
|| **plabel
!= i
+ 2))
2455 unsigned int next_insn
;
2456 const struct sh_opcode
*next_op
;
2458 /* There is an instruction after the load/store
2459 instruction, and it does not have a label. */
2460 next_insn
= bfd_get_16 (abfd
, contents
+ i
+ 2);
2461 next_op
= sh_insn_info (next_insn
);
2463 && (next_op
->flags
& (LOAD
| STORE
)) == 0
2464 && ! sh_insns_conflict (insn
, op
, next_insn
, next_op
))
2468 /* NEXT_INSN is not itself a load/store instruction,
2469 and it does not conflict with INSN. */
2473 /* If PREV_INSN is a load, and it sets a register
2474 which NEXT_INSN uses, then putting NEXT_INSN
2475 immediately after PREV_INSN will cause a pipeline
2476 bubble, so there is no reason to make this swap. */
2478 && (prev_op
->flags
& LOAD
) != 0
2479 && sh_load_use (prev_insn
, prev_op
, next_insn
, next_op
))
2482 /* If INSN is a load, and it sets a register which
2483 the insn after NEXT_INSN uses, then doing the
2484 swap will cause a pipeline bubble, so there is no
2485 reason to make the swap. However, if the insn
2486 after NEXT_INSN is itself a load or store
2487 instruction, then it is misaligned, so
2488 optimistically hope that it will be swapped
2489 itself, and just live with the pipeline bubble if
2493 && (op
->flags
& LOAD
) != 0)
2495 unsigned int next2_insn
;
2496 const struct sh_opcode
*next2_op
;
2498 next2_insn
= bfd_get_16 (abfd
, contents
+ i
+ 4);
2499 next2_op
= sh_insn_info (next2_insn
);
2500 if (next2_op
== NULL
2501 || ((next2_op
->flags
& (LOAD
| STORE
)) == 0
2502 && sh_load_use (insn
, op
, next2_insn
, next2_op
)))
2508 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
))
2519 #endif /* not COFF_IMAGE_WITH_PE */
2521 /* Swap two SH instructions. */
2524 sh_swap_insns (bfd
* abfd
,
2527 bfd_byte
* contents
,
2530 struct internal_reloc
*internal_relocs
= (struct internal_reloc
*) relocs
;
2531 unsigned short i1
, i2
;
2532 struct internal_reloc
*irel
, *irelend
;
2534 /* Swap the instructions themselves. */
2535 i1
= bfd_get_16 (abfd
, contents
+ addr
);
2536 i2
= bfd_get_16 (abfd
, contents
+ addr
+ 2);
2537 bfd_put_16 (abfd
, (bfd_vma
) i2
, contents
+ addr
);
2538 bfd_put_16 (abfd
, (bfd_vma
) i1
, contents
+ addr
+ 2);
2540 /* Adjust all reloc addresses. */
2541 irelend
= internal_relocs
+ sec
->reloc_count
;
2542 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2546 /* There are a few special types of relocs that we don't want to
2547 adjust. These relocs do not apply to the instruction itself,
2548 but are only associated with the address. */
2549 type
= irel
->r_type
;
2550 if (type
== R_SH_ALIGN
2551 || type
== R_SH_CODE
2552 || type
== R_SH_DATA
2553 || type
== R_SH_LABEL
)
2556 /* If an R_SH_USES reloc points to one of the addresses being
2557 swapped, we must adjust it. It would be incorrect to do this
2558 for a jump, though, since we want to execute both
2559 instructions after the jump. (We have avoided swapping
2560 around a label, so the jump will not wind up executing an
2561 instruction it shouldn't). */
2562 if (type
== R_SH_USES
)
2566 off
= irel
->r_vaddr
- sec
->vma
+ 4 + irel
->r_offset
;
2568 irel
->r_offset
+= 2;
2569 else if (off
== addr
+ 2)
2570 irel
->r_offset
-= 2;
2573 if (irel
->r_vaddr
- sec
->vma
== addr
)
2578 else if (irel
->r_vaddr
- sec
->vma
== addr
+ 2)
2589 unsigned short insn
, oinsn
;
2590 bfd_boolean overflow
;
2592 loc
= contents
+ irel
->r_vaddr
- sec
->vma
;
2599 case R_SH_PCDISP8BY2
:
2600 case R_SH_PCRELIMM8BY2
:
2601 insn
= bfd_get_16 (abfd
, loc
);
2604 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2606 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2610 insn
= bfd_get_16 (abfd
, loc
);
2613 if ((oinsn
& 0xf000) != (insn
& 0xf000))
2615 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2618 case R_SH_PCRELIMM8BY4
:
2619 /* This reloc ignores the least significant 3 bits of
2620 the program counter before adding in the offset.
2621 This means that if ADDR is at an even address, the
2622 swap will not affect the offset. If ADDR is an at an
2623 odd address, then the instruction will be crossing a
2624 four byte boundary, and must be adjusted. */
2625 if ((addr
& 3) != 0)
2627 insn
= bfd_get_16 (abfd
, loc
);
2630 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2632 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2641 /* xgettext: c-format */
2642 (_("%B: 0x%lx: fatal: reloc overflow while relaxing"),
2643 abfd
, (unsigned long) irel
->r_vaddr
);
2644 bfd_set_error (bfd_error_bad_value
);
2653 /* Look for loads and stores which we can align to four byte
2654 boundaries. See the longer comment above sh_relax_section for why
2655 this is desirable. This sets *PSWAPPED if some instruction was
2659 sh_align_loads (bfd
*abfd
,
2661 struct internal_reloc
*internal_relocs
,
2663 bfd_boolean
*pswapped
)
2665 struct internal_reloc
*irel
, *irelend
;
2666 bfd_vma
*labels
= NULL
;
2667 bfd_vma
*label
, *label_end
;
2672 irelend
= internal_relocs
+ sec
->reloc_count
;
2674 /* Get all the addresses with labels on them. */
2675 amt
= (bfd_size_type
) sec
->reloc_count
* sizeof (bfd_vma
);
2676 labels
= (bfd_vma
*) bfd_malloc (amt
);
2680 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2682 if (irel
->r_type
== R_SH_LABEL
)
2684 *label_end
= irel
->r_vaddr
- sec
->vma
;
2689 /* Note that the assembler currently always outputs relocs in
2690 address order. If that ever changes, this code will need to sort
2691 the label values and the relocs. */
2695 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2697 bfd_vma start
, stop
;
2699 if (irel
->r_type
!= R_SH_CODE
)
2702 start
= irel
->r_vaddr
- sec
->vma
;
2704 for (irel
++; irel
< irelend
; irel
++)
2705 if (irel
->r_type
== R_SH_DATA
)
2708 stop
= irel
->r_vaddr
- sec
->vma
;
2712 if (! _bfd_sh_align_load_span (abfd
, sec
, contents
, sh_swap_insns
,
2713 internal_relocs
, &label
,
2714 label_end
, start
, stop
, pswapped
))
2728 /* This is a modification of _bfd_coff_generic_relocate_section, which
2729 will handle SH relaxing. */
2732 sh_relocate_section (bfd
*output_bfd ATTRIBUTE_UNUSED
,
2733 struct bfd_link_info
*info
,
2735 asection
*input_section
,
2737 struct internal_reloc
*relocs
,
2738 struct internal_syment
*syms
,
2739 asection
**sections
)
2741 struct internal_reloc
*rel
;
2742 struct internal_reloc
*relend
;
2745 relend
= rel
+ input_section
->reloc_count
;
2746 for (; rel
< relend
; rel
++)
2749 struct coff_link_hash_entry
*h
;
2750 struct internal_syment
*sym
;
2753 reloc_howto_type
*howto
;
2754 bfd_reloc_status_type rstat
;
2756 /* Almost all relocs have to do with relaxing. If any work must
2757 be done for them, it has been done in sh_relax_section. */
2758 if (rel
->r_type
!= R_SH_IMM32
2760 && rel
->r_type
!= R_SH_IMM32CE
2761 && rel
->r_type
!= R_SH_IMAGEBASE
2763 && rel
->r_type
!= R_SH_PCDISP
)
2766 symndx
= rel
->r_symndx
;
2776 || (unsigned long) symndx
>= obj_raw_syment_count (input_bfd
))
2779 /* xgettext: c-format */
2780 (_("%B: illegal symbol index %ld in relocs"),
2782 bfd_set_error (bfd_error_bad_value
);
2785 h
= obj_coff_sym_hashes (input_bfd
)[symndx
];
2786 sym
= syms
+ symndx
;
2789 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
2790 addend
= - sym
->n_value
;
2794 if (rel
->r_type
== R_SH_PCDISP
)
2797 if (rel
->r_type
>= SH_COFF_HOWTO_COUNT
)
2800 howto
= &sh_coff_howtos
[rel
->r_type
];
2804 bfd_set_error (bfd_error_bad_value
);
2809 if (rel
->r_type
== R_SH_IMAGEBASE
)
2810 addend
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
2819 /* There is nothing to do for an internal PCDISP reloc. */
2820 if (rel
->r_type
== R_SH_PCDISP
)
2825 sec
= bfd_abs_section_ptr
;
2830 sec
= sections
[symndx
];
2831 val
= (sec
->output_section
->vma
2832 + sec
->output_offset
2839 if (h
->root
.type
== bfd_link_hash_defined
2840 || h
->root
.type
== bfd_link_hash_defweak
)
2844 sec
= h
->root
.u
.def
.section
;
2845 val
= (h
->root
.u
.def
.value
2846 + sec
->output_section
->vma
2847 + sec
->output_offset
);
2849 else if (! bfd_link_relocatable (info
))
2850 (*info
->callbacks
->undefined_symbol
)
2851 (info
, h
->root
.root
.string
, input_bfd
, input_section
,
2852 rel
->r_vaddr
- input_section
->vma
, TRUE
);
2855 rstat
= _bfd_final_link_relocate (howto
, input_bfd
, input_section
,
2857 rel
->r_vaddr
- input_section
->vma
,
2866 case bfd_reloc_overflow
:
2869 char buf
[SYMNMLEN
+ 1];
2875 else if (sym
->_n
._n_n
._n_zeroes
== 0
2876 && sym
->_n
._n_n
._n_offset
!= 0)
2877 name
= obj_coff_strings (input_bfd
) + sym
->_n
._n_n
._n_offset
;
2880 strncpy (buf
, sym
->_n
._n_name
, SYMNMLEN
);
2881 buf
[SYMNMLEN
] = '\0';
2885 (*info
->callbacks
->reloc_overflow
)
2886 (info
, (h
? &h
->root
: NULL
), name
, howto
->name
,
2887 (bfd_vma
) 0, input_bfd
, input_section
,
2888 rel
->r_vaddr
- input_section
->vma
);
2896 /* This is a version of bfd_generic_get_relocated_section_contents
2897 which uses sh_relocate_section. */
2900 sh_coff_get_relocated_section_contents (bfd
*output_bfd
,
2901 struct bfd_link_info
*link_info
,
2902 struct bfd_link_order
*link_order
,
2904 bfd_boolean relocatable
,
2907 asection
*input_section
= link_order
->u
.indirect
.section
;
2908 bfd
*input_bfd
= input_section
->owner
;
2909 asection
**sections
= NULL
;
2910 struct internal_reloc
*internal_relocs
= NULL
;
2911 struct internal_syment
*internal_syms
= NULL
;
2913 /* We only need to handle the case of relaxing, or of having a
2914 particular set of section contents, specially. */
2916 || coff_section_data (input_bfd
, input_section
) == NULL
2917 || coff_section_data (input_bfd
, input_section
)->contents
== NULL
)
2918 return bfd_generic_get_relocated_section_contents (output_bfd
, link_info
,
2923 memcpy (data
, coff_section_data (input_bfd
, input_section
)->contents
,
2924 (size_t) input_section
->size
);
2926 if ((input_section
->flags
& SEC_RELOC
) != 0
2927 && input_section
->reloc_count
> 0)
2929 bfd_size_type symesz
= bfd_coff_symesz (input_bfd
);
2930 bfd_byte
*esym
, *esymend
;
2931 struct internal_syment
*isymp
;
2935 if (! _bfd_coff_get_external_symbols (input_bfd
))
2938 internal_relocs
= (_bfd_coff_read_internal_relocs
2939 (input_bfd
, input_section
, FALSE
, (bfd_byte
*) NULL
,
2940 FALSE
, (struct internal_reloc
*) NULL
));
2941 if (internal_relocs
== NULL
)
2944 amt
= obj_raw_syment_count (input_bfd
);
2945 amt
*= sizeof (struct internal_syment
);
2946 internal_syms
= (struct internal_syment
*) bfd_malloc (amt
);
2947 if (internal_syms
== NULL
)
2950 amt
= obj_raw_syment_count (input_bfd
);
2951 amt
*= sizeof (asection
*);
2952 sections
= (asection
**) bfd_malloc (amt
);
2953 if (sections
== NULL
)
2956 isymp
= internal_syms
;
2958 esym
= (bfd_byte
*) obj_coff_external_syms (input_bfd
);
2959 esymend
= esym
+ obj_raw_syment_count (input_bfd
) * symesz
;
2960 while (esym
< esymend
)
2962 bfd_coff_swap_sym_in (input_bfd
, esym
, isymp
);
2964 if (isymp
->n_scnum
!= 0)
2965 *secpp
= coff_section_from_bfd_index (input_bfd
, isymp
->n_scnum
);
2968 if (isymp
->n_value
== 0)
2969 *secpp
= bfd_und_section_ptr
;
2971 *secpp
= bfd_com_section_ptr
;
2974 esym
+= (isymp
->n_numaux
+ 1) * symesz
;
2975 secpp
+= isymp
->n_numaux
+ 1;
2976 isymp
+= isymp
->n_numaux
+ 1;
2979 if (! sh_relocate_section (output_bfd
, link_info
, input_bfd
,
2980 input_section
, data
, internal_relocs
,
2981 internal_syms
, sections
))
2986 free (internal_syms
);
2987 internal_syms
= NULL
;
2988 free (internal_relocs
);
2989 internal_relocs
= NULL
;
2995 if (internal_relocs
!= NULL
)
2996 free (internal_relocs
);
2997 if (internal_syms
!= NULL
)
2998 free (internal_syms
);
2999 if (sections
!= NULL
)
3004 /* The target vectors. */
3006 #ifndef TARGET_SHL_SYM
3007 CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec
, "coff-sh", BFD_IS_RELAXABLE
, 0, '_', NULL
, COFF_SWAP_TABLE
)
3010 #ifdef TARGET_SHL_SYM
3011 #define TARGET_SYM TARGET_SHL_SYM
3013 #define TARGET_SYM sh_coff_le_vec
3016 #ifndef TARGET_SHL_NAME
3017 #define TARGET_SHL_NAME "coff-shl"
3021 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3022 SEC_CODE
| SEC_DATA
, '_', NULL
, COFF_SWAP_TABLE
);
3024 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3025 0, '_', NULL
, COFF_SWAP_TABLE
)
3028 #ifndef TARGET_SHL_SYM
3030 /* Some people want versions of the SH COFF target which do not align
3031 to 16 byte boundaries. We implement that by adding a couple of new
3032 target vectors. These are just like the ones above, but they
3033 change the default section alignment. To generate them in the
3034 assembler, use -small. To use them in the linker, use -b
3035 coff-sh{l}-small and -oformat coff-sh{l}-small.
3037 Yes, this is a horrible hack. A general solution for setting
3038 section alignment in COFF is rather complex. ELF handles this
3041 /* Only recognize the small versions if the target was not defaulted.
3042 Otherwise we won't recognize the non default endianness. */
3044 static const bfd_target
*
3045 coff_small_object_p (bfd
*abfd
)
3047 if (abfd
->target_defaulted
)
3049 bfd_set_error (bfd_error_wrong_format
);
3052 return coff_object_p (abfd
);
3055 /* Set the section alignment for the small versions. */
3058 coff_small_new_section_hook (bfd
*abfd
, asection
*section
)
3060 if (! coff_new_section_hook (abfd
, section
))
3063 /* We must align to at least a four byte boundary, because longword
3064 accesses must be on a four byte boundary. */
3065 if (section
->alignment_power
== COFF_DEFAULT_SECTION_ALIGNMENT_POWER
)
3066 section
->alignment_power
= 2;
3071 /* This is copied from bfd_coff_std_swap_table so that we can change
3072 the default section alignment power. */
3074 static bfd_coff_backend_data bfd_coff_small_swap_table
=
3076 coff_swap_aux_in
, coff_swap_sym_in
, coff_swap_lineno_in
,
3077 coff_swap_aux_out
, coff_swap_sym_out
,
3078 coff_swap_lineno_out
, coff_swap_reloc_out
,
3079 coff_swap_filehdr_out
, coff_swap_aouthdr_out
,
3080 coff_swap_scnhdr_out
,
3081 FILHSZ
, AOUTSZ
, SCNHSZ
, SYMESZ
, AUXESZ
, RELSZ
, LINESZ
, FILNMLEN
,
3082 #ifdef COFF_LONG_FILENAMES
3087 COFF_DEFAULT_LONG_SECTION_NAMES
,
3089 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3094 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3100 coff_swap_filehdr_in
, coff_swap_aouthdr_in
, coff_swap_scnhdr_in
,
3101 coff_swap_reloc_in
, coff_bad_format_hook
, coff_set_arch_mach_hook
,
3102 coff_mkobject_hook
, styp_to_sec_flags
, coff_set_alignment_hook
,
3103 coff_slurp_symbol_table
, symname_in_debug_hook
, coff_pointerize_aux_hook
,
3104 coff_print_aux
, coff_reloc16_extra_cases
, coff_reloc16_estimate
,
3105 coff_classify_symbol
, coff_compute_section_file_positions
,
3106 coff_start_final_link
, coff_relocate_section
, coff_rtype_to_howto
,
3107 coff_adjust_symndx
, coff_link_add_one_symbol
,
3108 coff_link_output_has_begun
, coff_final_link_postscript
,
3112 #define coff_small_close_and_cleanup \
3113 coff_close_and_cleanup
3114 #define coff_small_bfd_free_cached_info \
3115 coff_bfd_free_cached_info
3116 #define coff_small_get_section_contents \
3117 coff_get_section_contents
3118 #define coff_small_get_section_contents_in_window \
3119 coff_get_section_contents_in_window
3121 extern const bfd_target sh_coff_small_le_vec
;
3123 const bfd_target sh_coff_small_vec
=
3125 "coff-sh-small", /* name */
3126 bfd_target_coff_flavour
,
3127 BFD_ENDIAN_BIG
, /* data byte order is big */
3128 BFD_ENDIAN_BIG
, /* header byte order is big */
3130 (HAS_RELOC
| EXEC_P
| /* object flags */
3131 HAS_LINENO
| HAS_DEBUG
|
3132 HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3134 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3135 '_', /* leading symbol underscore */
3136 '/', /* ar_pad_char */
3137 15, /* ar_max_namelen */
3138 0, /* match priority. */
3139 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3140 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3141 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* data */
3142 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3143 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3144 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* hdrs */
3146 {_bfd_dummy_target
, coff_small_object_p
, /* bfd_check_format */
3147 bfd_generic_archive_p
, _bfd_dummy_target
},
3148 {bfd_false
, coff_mkobject
, _bfd_generic_mkarchive
, /* bfd_set_format */
3150 {bfd_false
, coff_write_object_contents
, /* bfd_write_contents */
3151 _bfd_write_archive_contents
, bfd_false
},
3153 BFD_JUMP_TABLE_GENERIC (coff_small
),
3154 BFD_JUMP_TABLE_COPY (coff
),
3155 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3156 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3157 BFD_JUMP_TABLE_SYMBOLS (coff
),
3158 BFD_JUMP_TABLE_RELOCS (coff
),
3159 BFD_JUMP_TABLE_WRITE (coff
),
3160 BFD_JUMP_TABLE_LINK (coff
),
3161 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3163 & sh_coff_small_le_vec
,
3165 & bfd_coff_small_swap_table
3168 const bfd_target sh_coff_small_le_vec
=
3170 "coff-shl-small", /* name */
3171 bfd_target_coff_flavour
,
3172 BFD_ENDIAN_LITTLE
, /* data byte order is little */
3173 BFD_ENDIAN_LITTLE
, /* header byte order is little endian too*/
3175 (HAS_RELOC
| EXEC_P
| /* object flags */
3176 HAS_LINENO
| HAS_DEBUG
|
3177 HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3179 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3180 '_', /* leading symbol underscore */
3181 '/', /* ar_pad_char */
3182 15, /* ar_max_namelen */
3183 0, /* match priority. */
3184 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3185 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3186 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* data */
3187 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3188 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3189 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* hdrs */
3191 {_bfd_dummy_target
, coff_small_object_p
, /* bfd_check_format */
3192 bfd_generic_archive_p
, _bfd_dummy_target
},
3193 {bfd_false
, coff_mkobject
, _bfd_generic_mkarchive
, /* bfd_set_format */
3195 {bfd_false
, coff_write_object_contents
, /* bfd_write_contents */
3196 _bfd_write_archive_contents
, bfd_false
},
3198 BFD_JUMP_TABLE_GENERIC (coff_small
),
3199 BFD_JUMP_TABLE_COPY (coff
),
3200 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3201 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3202 BFD_JUMP_TABLE_SYMBOLS (coff
),
3203 BFD_JUMP_TABLE_RELOCS (coff
),
3204 BFD_JUMP_TABLE_WRITE (coff
),
3205 BFD_JUMP_TABLE_LINK (coff
),
3206 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3208 & sh_coff_small_vec
,
3210 & bfd_coff_small_swap_table