1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2015 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how
,
489 unsigned int bitsize
,
490 unsigned int rightshift
,
491 unsigned int addrsize
,
494 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
495 bfd_reloc_status_type flag
= bfd_reloc_ok
;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask
= N_ONES (bitsize
);
502 signmask
= ~fieldmask
;
503 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
504 a
= (relocation
& addrmask
) >> rightshift
;
508 case complain_overflow_dont
:
511 case complain_overflow_signed
:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask
= ~ (fieldmask
>> 1);
517 case complain_overflow_bitfield
:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
525 flag
= bfd_reloc_overflow
;
528 case complain_overflow_unsigned
:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a
& signmask
) != 0)
531 flag
= bfd_reloc_overflow
;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd
*abfd
,
574 arelent
*reloc_entry
,
576 asection
*input_section
,
578 char **error_message
)
581 bfd_reloc_status_type flag
= bfd_reloc_ok
;
582 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
583 bfd_vma output_base
= 0;
584 reloc_howto_type
*howto
= reloc_entry
->howto
;
585 asection
*reloc_target_output_section
;
588 symbol
= *(reloc_entry
->sym_ptr_ptr
);
589 if (bfd_is_abs_section (symbol
->section
)
590 && output_bfd
!= NULL
)
592 reloc_entry
->address
+= input_section
->output_offset
;
596 /* PR 17512: file: 0f67f69d. */
598 return bfd_reloc_undefined
;
600 /* If we are not producing relocatable output, return an error if
601 the symbol is not defined. An undefined weak symbol is
602 considered to have a value of zero (SVR4 ABI, p. 4-27). */
603 if (bfd_is_und_section (symbol
->section
)
604 && (symbol
->flags
& BSF_WEAK
) == 0
605 && output_bfd
== NULL
)
606 flag
= bfd_reloc_undefined
;
608 /* If there is a function supplied to handle this relocation type,
609 call it. It'll return `bfd_reloc_continue' if further processing
611 if (howto
->special_function
)
613 bfd_reloc_status_type cont
;
614 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
615 input_section
, output_bfd
,
617 if (cont
!= bfd_reloc_continue
)
621 /* Is the address of the relocation really within the section? */
622 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
)
623 /* PR 17512: file: c146ab8b.
624 PR 17512: file: 46dff27f.
625 Include the size of the reloc in the test for out of range addresses. */
626 - bfd_get_reloc_size (howto
))
627 return bfd_reloc_outofrange
;
629 /* Work out which section the relocation is targeted at and the
630 initial relocation command value. */
632 /* Get symbol value. (Common symbols are special.) */
633 if (bfd_is_com_section (symbol
->section
))
636 relocation
= symbol
->value
;
638 reloc_target_output_section
= symbol
->section
->output_section
;
640 /* Convert input-section-relative symbol value to absolute. */
641 if ((output_bfd
&& ! howto
->partial_inplace
)
642 || reloc_target_output_section
== NULL
)
645 output_base
= reloc_target_output_section
->vma
;
647 relocation
+= output_base
+ symbol
->section
->output_offset
;
649 /* Add in supplied addend. */
650 relocation
+= reloc_entry
->addend
;
652 /* Here the variable relocation holds the final address of the
653 symbol we are relocating against, plus any addend. */
655 if (howto
->pc_relative
)
657 /* This is a PC relative relocation. We want to set RELOCATION
658 to the distance between the address of the symbol and the
659 location. RELOCATION is already the address of the symbol.
661 We start by subtracting the address of the section containing
664 If pcrel_offset is set, we must further subtract the position
665 of the location within the section. Some targets arrange for
666 the addend to be the negative of the position of the location
667 within the section; for example, i386-aout does this. For
668 i386-aout, pcrel_offset is FALSE. Some other targets do not
669 include the position of the location; for example, m88kbcs,
670 or ELF. For those targets, pcrel_offset is TRUE.
672 If we are producing relocatable output, then we must ensure
673 that this reloc will be correctly computed when the final
674 relocation is done. If pcrel_offset is FALSE we want to wind
675 up with the negative of the location within the section,
676 which means we must adjust the existing addend by the change
677 in the location within the section. If pcrel_offset is TRUE
678 we do not want to adjust the existing addend at all.
680 FIXME: This seems logical to me, but for the case of
681 producing relocatable output it is not what the code
682 actually does. I don't want to change it, because it seems
683 far too likely that something will break. */
686 input_section
->output_section
->vma
+ input_section
->output_offset
;
688 if (howto
->pcrel_offset
)
689 relocation
-= reloc_entry
->address
;
692 if (output_bfd
!= NULL
)
694 if (! howto
->partial_inplace
)
696 /* This is a partial relocation, and we want to apply the relocation
697 to the reloc entry rather than the raw data. Modify the reloc
698 inplace to reflect what we now know. */
699 reloc_entry
->addend
= relocation
;
700 reloc_entry
->address
+= input_section
->output_offset
;
705 /* This is a partial relocation, but inplace, so modify the
708 If we've relocated with a symbol with a section, change
709 into a ref to the section belonging to the symbol. */
711 reloc_entry
->address
+= input_section
->output_offset
;
714 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
715 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
716 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
718 /* For m68k-coff, the addend was being subtracted twice during
719 relocation with -r. Removing the line below this comment
720 fixes that problem; see PR 2953.
722 However, Ian wrote the following, regarding removing the line below,
723 which explains why it is still enabled: --djm
725 If you put a patch like that into BFD you need to check all the COFF
726 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
727 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
728 problem in a different way. There may very well be a reason that the
729 code works as it does.
731 Hmmm. The first obvious point is that bfd_perform_relocation should
732 not have any tests that depend upon the flavour. It's seem like
733 entirely the wrong place for such a thing. The second obvious point
734 is that the current code ignores the reloc addend when producing
735 relocatable output for COFF. That's peculiar. In fact, I really
736 have no idea what the point of the line you want to remove is.
738 A typical COFF reloc subtracts the old value of the symbol and adds in
739 the new value to the location in the object file (if it's a pc
740 relative reloc it adds the difference between the symbol value and the
741 location). When relocating we need to preserve that property.
743 BFD handles this by setting the addend to the negative of the old
744 value of the symbol. Unfortunately it handles common symbols in a
745 non-standard way (it doesn't subtract the old value) but that's a
746 different story (we can't change it without losing backward
747 compatibility with old object files) (coff-i386 does subtract the old
748 value, to be compatible with existing coff-i386 targets, like SCO).
750 So everything works fine when not producing relocatable output. When
751 we are producing relocatable output, logically we should do exactly
752 what we do when not producing relocatable output. Therefore, your
753 patch is correct. In fact, it should probably always just set
754 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
755 add the value into the object file. This won't hurt the COFF code,
756 which doesn't use the addend; I'm not sure what it will do to other
757 formats (the thing to check for would be whether any formats both use
758 the addend and set partial_inplace).
760 When I wanted to make coff-i386 produce relocatable output, I ran
761 into the problem that you are running into: I wanted to remove that
762 line. Rather than risk it, I made the coff-i386 relocs use a special
763 function; it's coff_i386_reloc in coff-i386.c. The function
764 specifically adds the addend field into the object file, knowing that
765 bfd_perform_relocation is not going to. If you remove that line, then
766 coff-i386.c will wind up adding the addend field in twice. It's
767 trivial to fix; it just needs to be done.
769 The problem with removing the line is just that it may break some
770 working code. With BFD it's hard to be sure of anything. The right
771 way to deal with this is simply to build and test at least all the
772 supported COFF targets. It should be straightforward if time and disk
773 space consuming. For each target:
775 2) generate some executable, and link it using -r (I would
776 probably use paranoia.o and link against newlib/libc.a, which
777 for all the supported targets would be available in
778 /usr/cygnus/progressive/H-host/target/lib/libc.a).
779 3) make the change to reloc.c
780 4) rebuild the linker
782 6) if the resulting object files are the same, you have at least
784 7) if they are different you have to figure out which version is
787 relocation
-= reloc_entry
->addend
;
788 reloc_entry
->addend
= 0;
792 reloc_entry
->addend
= relocation
;
797 /* FIXME: This overflow checking is incomplete, because the value
798 might have overflowed before we get here. For a correct check we
799 need to compute the value in a size larger than bitsize, but we
800 can't reasonably do that for a reloc the same size as a host
802 FIXME: We should also do overflow checking on the result after
803 adding in the value contained in the object file. */
804 if (howto
->complain_on_overflow
!= complain_overflow_dont
805 && flag
== bfd_reloc_ok
)
806 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
809 bfd_arch_bits_per_address (abfd
),
812 /* Either we are relocating all the way, or we don't want to apply
813 the relocation to the reloc entry (probably because there isn't
814 any room in the output format to describe addends to relocs). */
816 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
817 (OSF version 1.3, compiler version 3.11). It miscompiles the
831 x <<= (unsigned long) s.i0;
835 printf ("succeeded (%lx)\n", x);
839 relocation
>>= (bfd_vma
) howto
->rightshift
;
841 /* Shift everything up to where it's going to be used. */
842 relocation
<<= (bfd_vma
) howto
->bitpos
;
844 /* Wait for the day when all have the mask in them. */
847 i instruction to be left alone
848 o offset within instruction
849 r relocation offset to apply
858 (( i i i i i o o o o o from bfd_get<size>
859 and S S S S S) to get the size offset we want
860 + r r r r r r r r r r) to get the final value to place
861 and D D D D D to chop to right size
862 -----------------------
865 ( i i i i i o o o o o from bfd_get<size>
866 and N N N N N ) get instruction
867 -----------------------
873 -----------------------
874 = R R R R R R R R R R put into bfd_put<size>
878 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
884 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
886 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
892 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
894 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
899 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
901 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
906 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
907 relocation
= -relocation
;
909 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
915 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
916 relocation
= -relocation
;
918 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
929 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
931 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
938 return bfd_reloc_other
;
946 bfd_install_relocation
949 bfd_reloc_status_type bfd_install_relocation
951 arelent *reloc_entry,
952 void *data, bfd_vma data_start,
953 asection *input_section,
954 char **error_message);
957 This looks remarkably like <<bfd_perform_relocation>>, except it
958 does not expect that the section contents have been filled in.
959 I.e., it's suitable for use when creating, rather than applying
962 For now, this function should be considered reserved for the
966 bfd_reloc_status_type
967 bfd_install_relocation (bfd
*abfd
,
968 arelent
*reloc_entry
,
970 bfd_vma data_start_offset
,
971 asection
*input_section
,
972 char **error_message
)
975 bfd_reloc_status_type flag
= bfd_reloc_ok
;
976 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
977 bfd_vma output_base
= 0;
978 reloc_howto_type
*howto
= reloc_entry
->howto
;
979 asection
*reloc_target_output_section
;
983 symbol
= *(reloc_entry
->sym_ptr_ptr
);
984 if (bfd_is_abs_section (symbol
->section
))
986 reloc_entry
->address
+= input_section
->output_offset
;
990 /* If there is a function supplied to handle this relocation type,
991 call it. It'll return `bfd_reloc_continue' if further processing
993 if (howto
->special_function
)
995 bfd_reloc_status_type cont
;
997 /* XXX - The special_function calls haven't been fixed up to deal
998 with creating new relocations and section contents. */
999 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1000 /* XXX - Non-portable! */
1001 ((bfd_byte
*) data_start
1002 - data_start_offset
),
1003 input_section
, abfd
, error_message
);
1004 if (cont
!= bfd_reloc_continue
)
1008 /* Is the address of the relocation really within the section? */
1009 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
))
1010 return bfd_reloc_outofrange
;
1012 /* Work out which section the relocation is targeted at and the
1013 initial relocation command value. */
1015 /* Get symbol value. (Common symbols are special.) */
1016 if (bfd_is_com_section (symbol
->section
))
1019 relocation
= symbol
->value
;
1021 reloc_target_output_section
= symbol
->section
->output_section
;
1023 /* Convert input-section-relative symbol value to absolute. */
1024 if (! howto
->partial_inplace
)
1027 output_base
= reloc_target_output_section
->vma
;
1029 relocation
+= output_base
+ symbol
->section
->output_offset
;
1031 /* Add in supplied addend. */
1032 relocation
+= reloc_entry
->addend
;
1034 /* Here the variable relocation holds the final address of the
1035 symbol we are relocating against, plus any addend. */
1037 if (howto
->pc_relative
)
1039 /* This is a PC relative relocation. We want to set RELOCATION
1040 to the distance between the address of the symbol and the
1041 location. RELOCATION is already the address of the symbol.
1043 We start by subtracting the address of the section containing
1046 If pcrel_offset is set, we must further subtract the position
1047 of the location within the section. Some targets arrange for
1048 the addend to be the negative of the position of the location
1049 within the section; for example, i386-aout does this. For
1050 i386-aout, pcrel_offset is FALSE. Some other targets do not
1051 include the position of the location; for example, m88kbcs,
1052 or ELF. For those targets, pcrel_offset is TRUE.
1054 If we are producing relocatable output, then we must ensure
1055 that this reloc will be correctly computed when the final
1056 relocation is done. If pcrel_offset is FALSE we want to wind
1057 up with the negative of the location within the section,
1058 which means we must adjust the existing addend by the change
1059 in the location within the section. If pcrel_offset is TRUE
1060 we do not want to adjust the existing addend at all.
1062 FIXME: This seems logical to me, but for the case of
1063 producing relocatable output it is not what the code
1064 actually does. I don't want to change it, because it seems
1065 far too likely that something will break. */
1068 input_section
->output_section
->vma
+ input_section
->output_offset
;
1070 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1071 relocation
-= reloc_entry
->address
;
1074 if (! howto
->partial_inplace
)
1076 /* This is a partial relocation, and we want to apply the relocation
1077 to the reloc entry rather than the raw data. Modify the reloc
1078 inplace to reflect what we now know. */
1079 reloc_entry
->addend
= relocation
;
1080 reloc_entry
->address
+= input_section
->output_offset
;
1085 /* This is a partial relocation, but inplace, so modify the
1088 If we've relocated with a symbol with a section, change
1089 into a ref to the section belonging to the symbol. */
1090 reloc_entry
->address
+= input_section
->output_offset
;
1093 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1094 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1095 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1098 /* For m68k-coff, the addend was being subtracted twice during
1099 relocation with -r. Removing the line below this comment
1100 fixes that problem; see PR 2953.
1102 However, Ian wrote the following, regarding removing the line below,
1103 which explains why it is still enabled: --djm
1105 If you put a patch like that into BFD you need to check all the COFF
1106 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1107 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1108 problem in a different way. There may very well be a reason that the
1109 code works as it does.
1111 Hmmm. The first obvious point is that bfd_install_relocation should
1112 not have any tests that depend upon the flavour. It's seem like
1113 entirely the wrong place for such a thing. The second obvious point
1114 is that the current code ignores the reloc addend when producing
1115 relocatable output for COFF. That's peculiar. In fact, I really
1116 have no idea what the point of the line you want to remove is.
1118 A typical COFF reloc subtracts the old value of the symbol and adds in
1119 the new value to the location in the object file (if it's a pc
1120 relative reloc it adds the difference between the symbol value and the
1121 location). When relocating we need to preserve that property.
1123 BFD handles this by setting the addend to the negative of the old
1124 value of the symbol. Unfortunately it handles common symbols in a
1125 non-standard way (it doesn't subtract the old value) but that's a
1126 different story (we can't change it without losing backward
1127 compatibility with old object files) (coff-i386 does subtract the old
1128 value, to be compatible with existing coff-i386 targets, like SCO).
1130 So everything works fine when not producing relocatable output. When
1131 we are producing relocatable output, logically we should do exactly
1132 what we do when not producing relocatable output. Therefore, your
1133 patch is correct. In fact, it should probably always just set
1134 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1135 add the value into the object file. This won't hurt the COFF code,
1136 which doesn't use the addend; I'm not sure what it will do to other
1137 formats (the thing to check for would be whether any formats both use
1138 the addend and set partial_inplace).
1140 When I wanted to make coff-i386 produce relocatable output, I ran
1141 into the problem that you are running into: I wanted to remove that
1142 line. Rather than risk it, I made the coff-i386 relocs use a special
1143 function; it's coff_i386_reloc in coff-i386.c. The function
1144 specifically adds the addend field into the object file, knowing that
1145 bfd_install_relocation is not going to. If you remove that line, then
1146 coff-i386.c will wind up adding the addend field in twice. It's
1147 trivial to fix; it just needs to be done.
1149 The problem with removing the line is just that it may break some
1150 working code. With BFD it's hard to be sure of anything. The right
1151 way to deal with this is simply to build and test at least all the
1152 supported COFF targets. It should be straightforward if time and disk
1153 space consuming. For each target:
1155 2) generate some executable, and link it using -r (I would
1156 probably use paranoia.o and link against newlib/libc.a, which
1157 for all the supported targets would be available in
1158 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1159 3) make the change to reloc.c
1160 4) rebuild the linker
1162 6) if the resulting object files are the same, you have at least
1164 7) if they are different you have to figure out which version is
1166 relocation
-= reloc_entry
->addend
;
1167 /* FIXME: There should be no target specific code here... */
1168 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1169 reloc_entry
->addend
= 0;
1173 reloc_entry
->addend
= relocation
;
1177 /* FIXME: This overflow checking is incomplete, because the value
1178 might have overflowed before we get here. For a correct check we
1179 need to compute the value in a size larger than bitsize, but we
1180 can't reasonably do that for a reloc the same size as a host
1182 FIXME: We should also do overflow checking on the result after
1183 adding in the value contained in the object file. */
1184 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1185 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1188 bfd_arch_bits_per_address (abfd
),
1191 /* Either we are relocating all the way, or we don't want to apply
1192 the relocation to the reloc entry (probably because there isn't
1193 any room in the output format to describe addends to relocs). */
1195 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1196 (OSF version 1.3, compiler version 3.11). It miscompiles the
1210 x <<= (unsigned long) s.i0;
1212 printf ("failed\n");
1214 printf ("succeeded (%lx)\n", x);
1218 relocation
>>= (bfd_vma
) howto
->rightshift
;
1220 /* Shift everything up to where it's going to be used. */
1221 relocation
<<= (bfd_vma
) howto
->bitpos
;
1223 /* Wait for the day when all have the mask in them. */
1226 i instruction to be left alone
1227 o offset within instruction
1228 r relocation offset to apply
1237 (( i i i i i o o o o o from bfd_get<size>
1238 and S S S S S) to get the size offset we want
1239 + r r r r r r r r r r) to get the final value to place
1240 and D D D D D to chop to right size
1241 -----------------------
1244 ( i i i i i o o o o o from bfd_get<size>
1245 and N N N N N ) get instruction
1246 -----------------------
1252 -----------------------
1253 = R R R R R R R R R R put into bfd_put<size>
1257 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1259 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1261 switch (howto
->size
)
1265 char x
= bfd_get_8 (abfd
, data
);
1267 bfd_put_8 (abfd
, x
, data
);
1273 short x
= bfd_get_16 (abfd
, data
);
1275 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1280 long x
= bfd_get_32 (abfd
, data
);
1282 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1287 long x
= bfd_get_32 (abfd
, data
);
1288 relocation
= -relocation
;
1290 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1300 bfd_vma x
= bfd_get_64 (abfd
, data
);
1302 bfd_put_64 (abfd
, x
, data
);
1306 return bfd_reloc_other
;
1312 /* This relocation routine is used by some of the backend linkers.
1313 They do not construct asymbol or arelent structures, so there is no
1314 reason for them to use bfd_perform_relocation. Also,
1315 bfd_perform_relocation is so hacked up it is easier to write a new
1316 function than to try to deal with it.
1318 This routine does a final relocation. Whether it is useful for a
1319 relocatable link depends upon how the object format defines
1322 FIXME: This routine ignores any special_function in the HOWTO,
1323 since the existing special_function values have been written for
1324 bfd_perform_relocation.
1326 HOWTO is the reloc howto information.
1327 INPUT_BFD is the BFD which the reloc applies to.
1328 INPUT_SECTION is the section which the reloc applies to.
1329 CONTENTS is the contents of the section.
1330 ADDRESS is the address of the reloc within INPUT_SECTION.
1331 VALUE is the value of the symbol the reloc refers to.
1332 ADDEND is the addend of the reloc. */
1334 bfd_reloc_status_type
1335 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1337 asection
*input_section
,
1345 /* Sanity check the address. */
1346 if (address
> bfd_get_section_limit (input_bfd
, input_section
))
1347 return bfd_reloc_outofrange
;
1349 /* This function assumes that we are dealing with a basic relocation
1350 against a symbol. We want to compute the value of the symbol to
1351 relocate to. This is just VALUE, the value of the symbol, plus
1352 ADDEND, any addend associated with the reloc. */
1353 relocation
= value
+ addend
;
1355 /* If the relocation is PC relative, we want to set RELOCATION to
1356 the distance between the symbol (currently in RELOCATION) and the
1357 location we are relocating. Some targets (e.g., i386-aout)
1358 arrange for the contents of the section to be the negative of the
1359 offset of the location within the section; for such targets
1360 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1361 simply leave the contents of the section as zero; for such
1362 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1363 need to subtract out the offset of the location within the
1364 section (which is just ADDRESS). */
1365 if (howto
->pc_relative
)
1367 relocation
-= (input_section
->output_section
->vma
1368 + input_section
->output_offset
);
1369 if (howto
->pcrel_offset
)
1370 relocation
-= address
;
1373 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1374 contents
+ address
);
1377 /* Relocate a given location using a given value and howto. */
1379 bfd_reloc_status_type
1380 _bfd_relocate_contents (reloc_howto_type
*howto
,
1387 bfd_reloc_status_type flag
;
1388 unsigned int rightshift
= howto
->rightshift
;
1389 unsigned int bitpos
= howto
->bitpos
;
1391 /* If the size is negative, negate RELOCATION. This isn't very
1393 if (howto
->size
< 0)
1394 relocation
= -relocation
;
1396 /* Get the value we are going to relocate. */
1397 size
= bfd_get_reloc_size (howto
);
1404 x
= bfd_get_8 (input_bfd
, location
);
1407 x
= bfd_get_16 (input_bfd
, location
);
1410 x
= bfd_get_32 (input_bfd
, location
);
1414 x
= bfd_get_64 (input_bfd
, location
);
1421 /* Check for overflow. FIXME: We may drop bits during the addition
1422 which we don't check for. We must either check at every single
1423 operation, which would be tedious, or we must do the computations
1424 in a type larger than bfd_vma, which would be inefficient. */
1425 flag
= bfd_reloc_ok
;
1426 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1428 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1431 /* Get the values to be added together. For signed and unsigned
1432 relocations, we assume that all values should be truncated to
1433 the size of an address. For bitfields, all the bits matter.
1434 See also bfd_check_overflow. */
1435 fieldmask
= N_ONES (howto
->bitsize
);
1436 signmask
= ~fieldmask
;
1437 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1438 | (fieldmask
<< rightshift
));
1439 a
= (relocation
& addrmask
) >> rightshift
;
1440 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1441 addrmask
>>= rightshift
;
1443 switch (howto
->complain_on_overflow
)
1445 case complain_overflow_signed
:
1446 /* If any sign bits are set, all sign bits must be set.
1447 That is, A must be a valid negative address after
1449 signmask
= ~(fieldmask
>> 1);
1452 case complain_overflow_bitfield
:
1453 /* Much like the signed check, but for a field one bit
1454 wider. We allow a bitfield to represent numbers in the
1455 range -2**n to 2**n-1, where n is the number of bits in the
1456 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1457 can't overflow, which is exactly what we want. */
1459 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1460 flag
= bfd_reloc_overflow
;
1462 /* We only need this next bit of code if the sign bit of B
1463 is below the sign bit of A. This would only happen if
1464 SRC_MASK had fewer bits than BITSIZE. Note that if
1465 SRC_MASK has more bits than BITSIZE, we can get into
1466 trouble; we would need to verify that B is in range, as
1467 we do for A above. */
1468 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1471 /* Set all the bits above the sign bit. */
1474 /* Now we can do the addition. */
1477 /* See if the result has the correct sign. Bits above the
1478 sign bit are junk now; ignore them. If the sum is
1479 positive, make sure we did not have all negative inputs;
1480 if the sum is negative, make sure we did not have all
1481 positive inputs. The test below looks only at the sign
1482 bits, and it really just
1483 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1485 We mask with addrmask here to explicitly allow an address
1486 wrap-around. The Linux kernel relies on it, and it is
1487 the only way to write assembler code which can run when
1488 loaded at a location 0x80000000 away from the location at
1489 which it is linked. */
1490 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1491 flag
= bfd_reloc_overflow
;
1494 case complain_overflow_unsigned
:
1495 /* Checking for an unsigned overflow is relatively easy:
1496 trim the addresses and add, and trim the result as well.
1497 Overflow is normally indicated when the result does not
1498 fit in the field. However, we also need to consider the
1499 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1500 input is 0x80000000, and bfd_vma is only 32 bits; then we
1501 will get sum == 0, but there is an overflow, since the
1502 inputs did not fit in the field. Instead of doing a
1503 separate test, we can check for this by or-ing in the
1504 operands when testing for the sum overflowing its final
1506 sum
= (a
+ b
) & addrmask
;
1507 if ((a
| b
| sum
) & signmask
)
1508 flag
= bfd_reloc_overflow
;
1516 /* Put RELOCATION in the right bits. */
1517 relocation
>>= (bfd_vma
) rightshift
;
1518 relocation
<<= (bfd_vma
) bitpos
;
1520 /* Add RELOCATION to the right bits of X. */
1521 x
= ((x
& ~howto
->dst_mask
)
1522 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1524 /* Put the relocated value back in the object file. */
1530 bfd_put_8 (input_bfd
, x
, location
);
1533 bfd_put_16 (input_bfd
, x
, location
);
1536 bfd_put_32 (input_bfd
, x
, location
);
1540 bfd_put_64 (input_bfd
, x
, location
);
1550 /* Clear a given location using a given howto, by applying a fixed relocation
1551 value and discarding any in-place addend. This is used for fixed-up
1552 relocations against discarded symbols, to make ignorable debug or unwind
1553 information more obvious. */
1556 _bfd_clear_contents (reloc_howto_type
*howto
,
1558 asection
*input_section
,
1564 /* Get the value we are going to relocate. */
1565 size
= bfd_get_reloc_size (howto
);
1572 x
= bfd_get_8 (input_bfd
, location
);
1575 x
= bfd_get_16 (input_bfd
, location
);
1578 x
= bfd_get_32 (input_bfd
, location
);
1582 x
= bfd_get_64 (input_bfd
, location
);
1589 /* Zero out the unwanted bits of X. */
1590 x
&= ~howto
->dst_mask
;
1592 /* For a range list, use 1 instead of 0 as placeholder. 0
1593 would terminate the list, hiding any later entries. */
1594 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1595 ".debug_ranges") == 0
1596 && (howto
->dst_mask
& 1) != 0)
1599 /* Put the relocated value back in the object file. */
1606 bfd_put_8 (input_bfd
, x
, location
);
1609 bfd_put_16 (input_bfd
, x
, location
);
1612 bfd_put_32 (input_bfd
, x
, location
);
1616 bfd_put_64 (input_bfd
, x
, location
);
1627 howto manager, , typedef arelent, Relocations
1632 When an application wants to create a relocation, but doesn't
1633 know what the target machine might call it, it can find out by
1634 using this bit of code.
1643 The insides of a reloc code. The idea is that, eventually, there
1644 will be one enumerator for every type of relocation we ever do.
1645 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1646 return a howto pointer.
1648 This does mean that the application must determine the correct
1649 enumerator value; you can't get a howto pointer from a random set
1670 Basic absolute relocations of N bits.
1685 PC-relative relocations. Sometimes these are relative to the address
1686 of the relocation itself; sometimes they are relative to the start of
1687 the section containing the relocation. It depends on the specific target.
1689 The 24-bit relocation is used in some Intel 960 configurations.
1694 Section relative relocations. Some targets need this for DWARF2.
1697 BFD_RELOC_32_GOT_PCREL
1699 BFD_RELOC_16_GOT_PCREL
1701 BFD_RELOC_8_GOT_PCREL
1707 BFD_RELOC_LO16_GOTOFF
1709 BFD_RELOC_HI16_GOTOFF
1711 BFD_RELOC_HI16_S_GOTOFF
1715 BFD_RELOC_64_PLT_PCREL
1717 BFD_RELOC_32_PLT_PCREL
1719 BFD_RELOC_24_PLT_PCREL
1721 BFD_RELOC_16_PLT_PCREL
1723 BFD_RELOC_8_PLT_PCREL
1731 BFD_RELOC_LO16_PLTOFF
1733 BFD_RELOC_HI16_PLTOFF
1735 BFD_RELOC_HI16_S_PLTOFF
1749 BFD_RELOC_68K_GLOB_DAT
1751 BFD_RELOC_68K_JMP_SLOT
1753 BFD_RELOC_68K_RELATIVE
1755 BFD_RELOC_68K_TLS_GD32
1757 BFD_RELOC_68K_TLS_GD16
1759 BFD_RELOC_68K_TLS_GD8
1761 BFD_RELOC_68K_TLS_LDM32
1763 BFD_RELOC_68K_TLS_LDM16
1765 BFD_RELOC_68K_TLS_LDM8
1767 BFD_RELOC_68K_TLS_LDO32
1769 BFD_RELOC_68K_TLS_LDO16
1771 BFD_RELOC_68K_TLS_LDO8
1773 BFD_RELOC_68K_TLS_IE32
1775 BFD_RELOC_68K_TLS_IE16
1777 BFD_RELOC_68K_TLS_IE8
1779 BFD_RELOC_68K_TLS_LE32
1781 BFD_RELOC_68K_TLS_LE16
1783 BFD_RELOC_68K_TLS_LE8
1785 Relocations used by 68K ELF.
1788 BFD_RELOC_32_BASEREL
1790 BFD_RELOC_16_BASEREL
1792 BFD_RELOC_LO16_BASEREL
1794 BFD_RELOC_HI16_BASEREL
1796 BFD_RELOC_HI16_S_BASEREL
1802 Linkage-table relative.
1807 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1810 BFD_RELOC_32_PCREL_S2
1812 BFD_RELOC_16_PCREL_S2
1814 BFD_RELOC_23_PCREL_S2
1816 These PC-relative relocations are stored as word displacements --
1817 i.e., byte displacements shifted right two bits. The 30-bit word
1818 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1819 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1820 signed 16-bit displacement is used on the MIPS, and the 23-bit
1821 displacement is used on the Alpha.
1828 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1829 the target word. These are used on the SPARC.
1836 For systems that allocate a Global Pointer register, these are
1837 displacements off that register. These relocation types are
1838 handled specially, because the value the register will have is
1839 decided relatively late.
1842 BFD_RELOC_I960_CALLJ
1844 Reloc types used for i960/b.out.
1849 BFD_RELOC_SPARC_WDISP22
1855 BFD_RELOC_SPARC_GOT10
1857 BFD_RELOC_SPARC_GOT13
1859 BFD_RELOC_SPARC_GOT22
1861 BFD_RELOC_SPARC_PC10
1863 BFD_RELOC_SPARC_PC22
1865 BFD_RELOC_SPARC_WPLT30
1867 BFD_RELOC_SPARC_COPY
1869 BFD_RELOC_SPARC_GLOB_DAT
1871 BFD_RELOC_SPARC_JMP_SLOT
1873 BFD_RELOC_SPARC_RELATIVE
1875 BFD_RELOC_SPARC_UA16
1877 BFD_RELOC_SPARC_UA32
1879 BFD_RELOC_SPARC_UA64
1881 BFD_RELOC_SPARC_GOTDATA_HIX22
1883 BFD_RELOC_SPARC_GOTDATA_LOX10
1885 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1887 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1889 BFD_RELOC_SPARC_GOTDATA_OP
1891 BFD_RELOC_SPARC_JMP_IREL
1893 BFD_RELOC_SPARC_IRELATIVE
1895 SPARC ELF relocations. There is probably some overlap with other
1896 relocation types already defined.
1899 BFD_RELOC_SPARC_BASE13
1901 BFD_RELOC_SPARC_BASE22
1903 I think these are specific to SPARC a.out (e.g., Sun 4).
1913 BFD_RELOC_SPARC_OLO10
1915 BFD_RELOC_SPARC_HH22
1917 BFD_RELOC_SPARC_HM10
1919 BFD_RELOC_SPARC_LM22
1921 BFD_RELOC_SPARC_PC_HH22
1923 BFD_RELOC_SPARC_PC_HM10
1925 BFD_RELOC_SPARC_PC_LM22
1927 BFD_RELOC_SPARC_WDISP16
1929 BFD_RELOC_SPARC_WDISP19
1937 BFD_RELOC_SPARC_DISP64
1940 BFD_RELOC_SPARC_PLT32
1942 BFD_RELOC_SPARC_PLT64
1944 BFD_RELOC_SPARC_HIX22
1946 BFD_RELOC_SPARC_LOX10
1954 BFD_RELOC_SPARC_REGISTER
1958 BFD_RELOC_SPARC_SIZE32
1960 BFD_RELOC_SPARC_SIZE64
1962 BFD_RELOC_SPARC_WDISP10
1967 BFD_RELOC_SPARC_REV32
1969 SPARC little endian relocation
1971 BFD_RELOC_SPARC_TLS_GD_HI22
1973 BFD_RELOC_SPARC_TLS_GD_LO10
1975 BFD_RELOC_SPARC_TLS_GD_ADD
1977 BFD_RELOC_SPARC_TLS_GD_CALL
1979 BFD_RELOC_SPARC_TLS_LDM_HI22
1981 BFD_RELOC_SPARC_TLS_LDM_LO10
1983 BFD_RELOC_SPARC_TLS_LDM_ADD
1985 BFD_RELOC_SPARC_TLS_LDM_CALL
1987 BFD_RELOC_SPARC_TLS_LDO_HIX22
1989 BFD_RELOC_SPARC_TLS_LDO_LOX10
1991 BFD_RELOC_SPARC_TLS_LDO_ADD
1993 BFD_RELOC_SPARC_TLS_IE_HI22
1995 BFD_RELOC_SPARC_TLS_IE_LO10
1997 BFD_RELOC_SPARC_TLS_IE_LD
1999 BFD_RELOC_SPARC_TLS_IE_LDX
2001 BFD_RELOC_SPARC_TLS_IE_ADD
2003 BFD_RELOC_SPARC_TLS_LE_HIX22
2005 BFD_RELOC_SPARC_TLS_LE_LOX10
2007 BFD_RELOC_SPARC_TLS_DTPMOD32
2009 BFD_RELOC_SPARC_TLS_DTPMOD64
2011 BFD_RELOC_SPARC_TLS_DTPOFF32
2013 BFD_RELOC_SPARC_TLS_DTPOFF64
2015 BFD_RELOC_SPARC_TLS_TPOFF32
2017 BFD_RELOC_SPARC_TLS_TPOFF64
2019 SPARC TLS relocations
2028 BFD_RELOC_SPU_IMM10W
2032 BFD_RELOC_SPU_IMM16W
2036 BFD_RELOC_SPU_PCREL9a
2038 BFD_RELOC_SPU_PCREL9b
2040 BFD_RELOC_SPU_PCREL16
2050 BFD_RELOC_SPU_ADD_PIC
2055 BFD_RELOC_ALPHA_GPDISP_HI16
2057 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2058 "addend" in some special way.
2059 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2060 writing; when reading, it will be the absolute section symbol. The
2061 addend is the displacement in bytes of the "lda" instruction from
2062 the "ldah" instruction (which is at the address of this reloc).
2064 BFD_RELOC_ALPHA_GPDISP_LO16
2066 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2067 with GPDISP_HI16 relocs. The addend is ignored when writing the
2068 relocations out, and is filled in with the file's GP value on
2069 reading, for convenience.
2072 BFD_RELOC_ALPHA_GPDISP
2074 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2075 relocation except that there is no accompanying GPDISP_LO16
2079 BFD_RELOC_ALPHA_LITERAL
2081 BFD_RELOC_ALPHA_ELF_LITERAL
2083 BFD_RELOC_ALPHA_LITUSE
2085 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2086 the assembler turns it into a LDQ instruction to load the address of
2087 the symbol, and then fills in a register in the real instruction.
2089 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2090 section symbol. The addend is ignored when writing, but is filled
2091 in with the file's GP value on reading, for convenience, as with the
2094 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2095 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2096 but it generates output not based on the position within the .got
2097 section, but relative to the GP value chosen for the file during the
2100 The LITUSE reloc, on the instruction using the loaded address, gives
2101 information to the linker that it might be able to use to optimize
2102 away some literal section references. The symbol is ignored (read
2103 as the absolute section symbol), and the "addend" indicates the type
2104 of instruction using the register:
2105 1 - "memory" fmt insn
2106 2 - byte-manipulation (byte offset reg)
2107 3 - jsr (target of branch)
2110 BFD_RELOC_ALPHA_HINT
2112 The HINT relocation indicates a value that should be filled into the
2113 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2114 prediction logic which may be provided on some processors.
2117 BFD_RELOC_ALPHA_LINKAGE
2119 The LINKAGE relocation outputs a linkage pair in the object file,
2120 which is filled by the linker.
2123 BFD_RELOC_ALPHA_CODEADDR
2125 The CODEADDR relocation outputs a STO_CA in the object file,
2126 which is filled by the linker.
2129 BFD_RELOC_ALPHA_GPREL_HI16
2131 BFD_RELOC_ALPHA_GPREL_LO16
2133 The GPREL_HI/LO relocations together form a 32-bit offset from the
2137 BFD_RELOC_ALPHA_BRSGP
2139 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2140 share a common GP, and the target address is adjusted for
2141 STO_ALPHA_STD_GPLOAD.
2146 The NOP relocation outputs a NOP if the longword displacement
2147 between two procedure entry points is < 2^21.
2152 The BSR relocation outputs a BSR if the longword displacement
2153 between two procedure entry points is < 2^21.
2158 The LDA relocation outputs a LDA if the longword displacement
2159 between two procedure entry points is < 2^16.
2164 The BOH relocation outputs a BSR if the longword displacement
2165 between two procedure entry points is < 2^21, or else a hint.
2168 BFD_RELOC_ALPHA_TLSGD
2170 BFD_RELOC_ALPHA_TLSLDM
2172 BFD_RELOC_ALPHA_DTPMOD64
2174 BFD_RELOC_ALPHA_GOTDTPREL16
2176 BFD_RELOC_ALPHA_DTPREL64
2178 BFD_RELOC_ALPHA_DTPREL_HI16
2180 BFD_RELOC_ALPHA_DTPREL_LO16
2182 BFD_RELOC_ALPHA_DTPREL16
2184 BFD_RELOC_ALPHA_GOTTPREL16
2186 BFD_RELOC_ALPHA_TPREL64
2188 BFD_RELOC_ALPHA_TPREL_HI16
2190 BFD_RELOC_ALPHA_TPREL_LO16
2192 BFD_RELOC_ALPHA_TPREL16
2194 Alpha thread-local storage relocations.
2199 BFD_RELOC_MICROMIPS_JMP
2201 The MIPS jump instruction.
2204 BFD_RELOC_MIPS16_JMP
2206 The MIPS16 jump instruction.
2209 BFD_RELOC_MIPS16_GPREL
2211 MIPS16 GP relative reloc.
2216 High 16 bits of 32-bit value; simple reloc.
2221 High 16 bits of 32-bit value but the low 16 bits will be sign
2222 extended and added to form the final result. If the low 16
2223 bits form a negative number, we need to add one to the high value
2224 to compensate for the borrow when the low bits are added.
2232 BFD_RELOC_HI16_PCREL
2234 High 16 bits of 32-bit pc-relative value
2236 BFD_RELOC_HI16_S_PCREL
2238 High 16 bits of 32-bit pc-relative value, adjusted
2240 BFD_RELOC_LO16_PCREL
2242 Low 16 bits of pc-relative value
2245 BFD_RELOC_MIPS16_GOT16
2247 BFD_RELOC_MIPS16_CALL16
2249 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2250 16-bit immediate fields
2252 BFD_RELOC_MIPS16_HI16
2254 MIPS16 high 16 bits of 32-bit value.
2256 BFD_RELOC_MIPS16_HI16_S
2258 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2259 extended and added to form the final result. If the low 16
2260 bits form a negative number, we need to add one to the high value
2261 to compensate for the borrow when the low bits are added.
2263 BFD_RELOC_MIPS16_LO16
2268 BFD_RELOC_MIPS16_TLS_GD
2270 BFD_RELOC_MIPS16_TLS_LDM
2272 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2274 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2276 BFD_RELOC_MIPS16_TLS_GOTTPREL
2278 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2280 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2282 MIPS16 TLS relocations
2285 BFD_RELOC_MIPS_LITERAL
2287 BFD_RELOC_MICROMIPS_LITERAL
2289 Relocation against a MIPS literal section.
2292 BFD_RELOC_MICROMIPS_7_PCREL_S1
2294 BFD_RELOC_MICROMIPS_10_PCREL_S1
2296 BFD_RELOC_MICROMIPS_16_PCREL_S1
2298 microMIPS PC-relative relocations.
2301 BFD_RELOC_MIPS_21_PCREL_S2
2303 BFD_RELOC_MIPS_26_PCREL_S2
2305 BFD_RELOC_MIPS_18_PCREL_S3
2307 BFD_RELOC_MIPS_19_PCREL_S2
2309 MIPS PC-relative relocations.
2312 BFD_RELOC_MICROMIPS_GPREL16
2314 BFD_RELOC_MICROMIPS_HI16
2316 BFD_RELOC_MICROMIPS_HI16_S
2318 BFD_RELOC_MICROMIPS_LO16
2320 microMIPS versions of generic BFD relocs.
2323 BFD_RELOC_MIPS_GOT16
2325 BFD_RELOC_MICROMIPS_GOT16
2327 BFD_RELOC_MIPS_CALL16
2329 BFD_RELOC_MICROMIPS_CALL16
2331 BFD_RELOC_MIPS_GOT_HI16
2333 BFD_RELOC_MICROMIPS_GOT_HI16
2335 BFD_RELOC_MIPS_GOT_LO16
2337 BFD_RELOC_MICROMIPS_GOT_LO16
2339 BFD_RELOC_MIPS_CALL_HI16
2341 BFD_RELOC_MICROMIPS_CALL_HI16
2343 BFD_RELOC_MIPS_CALL_LO16
2345 BFD_RELOC_MICROMIPS_CALL_LO16
2349 BFD_RELOC_MICROMIPS_SUB
2351 BFD_RELOC_MIPS_GOT_PAGE
2353 BFD_RELOC_MICROMIPS_GOT_PAGE
2355 BFD_RELOC_MIPS_GOT_OFST
2357 BFD_RELOC_MICROMIPS_GOT_OFST
2359 BFD_RELOC_MIPS_GOT_DISP
2361 BFD_RELOC_MICROMIPS_GOT_DISP
2363 BFD_RELOC_MIPS_SHIFT5
2365 BFD_RELOC_MIPS_SHIFT6
2367 BFD_RELOC_MIPS_INSERT_A
2369 BFD_RELOC_MIPS_INSERT_B
2371 BFD_RELOC_MIPS_DELETE
2373 BFD_RELOC_MIPS_HIGHEST
2375 BFD_RELOC_MICROMIPS_HIGHEST
2377 BFD_RELOC_MIPS_HIGHER
2379 BFD_RELOC_MICROMIPS_HIGHER
2381 BFD_RELOC_MIPS_SCN_DISP
2383 BFD_RELOC_MICROMIPS_SCN_DISP
2385 BFD_RELOC_MIPS_REL16
2387 BFD_RELOC_MIPS_RELGOT
2391 BFD_RELOC_MICROMIPS_JALR
2393 BFD_RELOC_MIPS_TLS_DTPMOD32
2395 BFD_RELOC_MIPS_TLS_DTPREL32
2397 BFD_RELOC_MIPS_TLS_DTPMOD64
2399 BFD_RELOC_MIPS_TLS_DTPREL64
2401 BFD_RELOC_MIPS_TLS_GD
2403 BFD_RELOC_MICROMIPS_TLS_GD
2405 BFD_RELOC_MIPS_TLS_LDM
2407 BFD_RELOC_MICROMIPS_TLS_LDM
2409 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2411 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2413 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2415 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2417 BFD_RELOC_MIPS_TLS_GOTTPREL
2419 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2421 BFD_RELOC_MIPS_TLS_TPREL32
2423 BFD_RELOC_MIPS_TLS_TPREL64
2425 BFD_RELOC_MIPS_TLS_TPREL_HI16
2427 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2429 BFD_RELOC_MIPS_TLS_TPREL_LO16
2431 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2435 MIPS ELF relocations.
2441 BFD_RELOC_MIPS_JUMP_SLOT
2443 MIPS ELF relocations (VxWorks and PLT extensions).
2447 BFD_RELOC_MOXIE_10_PCREL
2449 Moxie ELF relocations.
2453 BFD_RELOC_FRV_LABEL16
2455 BFD_RELOC_FRV_LABEL24
2461 BFD_RELOC_FRV_GPREL12
2463 BFD_RELOC_FRV_GPRELU12
2465 BFD_RELOC_FRV_GPREL32
2467 BFD_RELOC_FRV_GPRELHI
2469 BFD_RELOC_FRV_GPRELLO
2477 BFD_RELOC_FRV_FUNCDESC
2479 BFD_RELOC_FRV_FUNCDESC_GOT12
2481 BFD_RELOC_FRV_FUNCDESC_GOTHI
2483 BFD_RELOC_FRV_FUNCDESC_GOTLO
2485 BFD_RELOC_FRV_FUNCDESC_VALUE
2487 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2489 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2491 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2493 BFD_RELOC_FRV_GOTOFF12
2495 BFD_RELOC_FRV_GOTOFFHI
2497 BFD_RELOC_FRV_GOTOFFLO
2499 BFD_RELOC_FRV_GETTLSOFF
2501 BFD_RELOC_FRV_TLSDESC_VALUE
2503 BFD_RELOC_FRV_GOTTLSDESC12
2505 BFD_RELOC_FRV_GOTTLSDESCHI
2507 BFD_RELOC_FRV_GOTTLSDESCLO
2509 BFD_RELOC_FRV_TLSMOFF12
2511 BFD_RELOC_FRV_TLSMOFFHI
2513 BFD_RELOC_FRV_TLSMOFFLO
2515 BFD_RELOC_FRV_GOTTLSOFF12
2517 BFD_RELOC_FRV_GOTTLSOFFHI
2519 BFD_RELOC_FRV_GOTTLSOFFLO
2521 BFD_RELOC_FRV_TLSOFF
2523 BFD_RELOC_FRV_TLSDESC_RELAX
2525 BFD_RELOC_FRV_GETTLSOFF_RELAX
2527 BFD_RELOC_FRV_TLSOFF_RELAX
2529 BFD_RELOC_FRV_TLSMOFF
2531 Fujitsu Frv Relocations.
2535 BFD_RELOC_MN10300_GOTOFF24
2537 This is a 24bit GOT-relative reloc for the mn10300.
2539 BFD_RELOC_MN10300_GOT32
2541 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2544 BFD_RELOC_MN10300_GOT24
2546 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2549 BFD_RELOC_MN10300_GOT16
2551 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2554 BFD_RELOC_MN10300_COPY
2556 Copy symbol at runtime.
2558 BFD_RELOC_MN10300_GLOB_DAT
2562 BFD_RELOC_MN10300_JMP_SLOT
2566 BFD_RELOC_MN10300_RELATIVE
2568 Adjust by program base.
2570 BFD_RELOC_MN10300_SYM_DIFF
2572 Together with another reloc targeted at the same location,
2573 allows for a value that is the difference of two symbols
2574 in the same section.
2576 BFD_RELOC_MN10300_ALIGN
2578 The addend of this reloc is an alignment power that must
2579 be honoured at the offset's location, regardless of linker
2582 BFD_RELOC_MN10300_TLS_GD
2584 BFD_RELOC_MN10300_TLS_LD
2586 BFD_RELOC_MN10300_TLS_LDO
2588 BFD_RELOC_MN10300_TLS_GOTIE
2590 BFD_RELOC_MN10300_TLS_IE
2592 BFD_RELOC_MN10300_TLS_LE
2594 BFD_RELOC_MN10300_TLS_DTPMOD
2596 BFD_RELOC_MN10300_TLS_DTPOFF
2598 BFD_RELOC_MN10300_TLS_TPOFF
2600 Various TLS-related relocations.
2602 BFD_RELOC_MN10300_32_PCREL
2604 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2607 BFD_RELOC_MN10300_16_PCREL
2609 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2620 BFD_RELOC_386_GLOB_DAT
2622 BFD_RELOC_386_JUMP_SLOT
2624 BFD_RELOC_386_RELATIVE
2626 BFD_RELOC_386_GOTOFF
2630 BFD_RELOC_386_TLS_TPOFF
2632 BFD_RELOC_386_TLS_IE
2634 BFD_RELOC_386_TLS_GOTIE
2636 BFD_RELOC_386_TLS_LE
2638 BFD_RELOC_386_TLS_GD
2640 BFD_RELOC_386_TLS_LDM
2642 BFD_RELOC_386_TLS_LDO_32
2644 BFD_RELOC_386_TLS_IE_32
2646 BFD_RELOC_386_TLS_LE_32
2648 BFD_RELOC_386_TLS_DTPMOD32
2650 BFD_RELOC_386_TLS_DTPOFF32
2652 BFD_RELOC_386_TLS_TPOFF32
2654 BFD_RELOC_386_TLS_GOTDESC
2656 BFD_RELOC_386_TLS_DESC_CALL
2658 BFD_RELOC_386_TLS_DESC
2660 BFD_RELOC_386_IRELATIVE
2662 i386/elf relocations
2665 BFD_RELOC_X86_64_GOT32
2667 BFD_RELOC_X86_64_PLT32
2669 BFD_RELOC_X86_64_COPY
2671 BFD_RELOC_X86_64_GLOB_DAT
2673 BFD_RELOC_X86_64_JUMP_SLOT
2675 BFD_RELOC_X86_64_RELATIVE
2677 BFD_RELOC_X86_64_GOTPCREL
2679 BFD_RELOC_X86_64_32S
2681 BFD_RELOC_X86_64_DTPMOD64
2683 BFD_RELOC_X86_64_DTPOFF64
2685 BFD_RELOC_X86_64_TPOFF64
2687 BFD_RELOC_X86_64_TLSGD
2689 BFD_RELOC_X86_64_TLSLD
2691 BFD_RELOC_X86_64_DTPOFF32
2693 BFD_RELOC_X86_64_GOTTPOFF
2695 BFD_RELOC_X86_64_TPOFF32
2697 BFD_RELOC_X86_64_GOTOFF64
2699 BFD_RELOC_X86_64_GOTPC32
2701 BFD_RELOC_X86_64_GOT64
2703 BFD_RELOC_X86_64_GOTPCREL64
2705 BFD_RELOC_X86_64_GOTPC64
2707 BFD_RELOC_X86_64_GOTPLT64
2709 BFD_RELOC_X86_64_PLTOFF64
2711 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2713 BFD_RELOC_X86_64_TLSDESC_CALL
2715 BFD_RELOC_X86_64_TLSDESC
2717 BFD_RELOC_X86_64_IRELATIVE
2719 BFD_RELOC_X86_64_PC32_BND
2721 BFD_RELOC_X86_64_PLT32_BND
2723 x86-64/elf relocations
2726 BFD_RELOC_NS32K_IMM_8
2728 BFD_RELOC_NS32K_IMM_16
2730 BFD_RELOC_NS32K_IMM_32
2732 BFD_RELOC_NS32K_IMM_8_PCREL
2734 BFD_RELOC_NS32K_IMM_16_PCREL
2736 BFD_RELOC_NS32K_IMM_32_PCREL
2738 BFD_RELOC_NS32K_DISP_8
2740 BFD_RELOC_NS32K_DISP_16
2742 BFD_RELOC_NS32K_DISP_32
2744 BFD_RELOC_NS32K_DISP_8_PCREL
2746 BFD_RELOC_NS32K_DISP_16_PCREL
2748 BFD_RELOC_NS32K_DISP_32_PCREL
2753 BFD_RELOC_PDP11_DISP_8_PCREL
2755 BFD_RELOC_PDP11_DISP_6_PCREL
2760 BFD_RELOC_PJ_CODE_HI16
2762 BFD_RELOC_PJ_CODE_LO16
2764 BFD_RELOC_PJ_CODE_DIR16
2766 BFD_RELOC_PJ_CODE_DIR32
2768 BFD_RELOC_PJ_CODE_REL16
2770 BFD_RELOC_PJ_CODE_REL32
2772 Picojava relocs. Not all of these appear in object files.
2783 BFD_RELOC_PPC_B16_BRTAKEN
2785 BFD_RELOC_PPC_B16_BRNTAKEN
2789 BFD_RELOC_PPC_BA16_BRTAKEN
2791 BFD_RELOC_PPC_BA16_BRNTAKEN
2795 BFD_RELOC_PPC_GLOB_DAT
2797 BFD_RELOC_PPC_JMP_SLOT
2799 BFD_RELOC_PPC_RELATIVE
2801 BFD_RELOC_PPC_LOCAL24PC
2803 BFD_RELOC_PPC_EMB_NADDR32
2805 BFD_RELOC_PPC_EMB_NADDR16
2807 BFD_RELOC_PPC_EMB_NADDR16_LO
2809 BFD_RELOC_PPC_EMB_NADDR16_HI
2811 BFD_RELOC_PPC_EMB_NADDR16_HA
2813 BFD_RELOC_PPC_EMB_SDAI16
2815 BFD_RELOC_PPC_EMB_SDA2I16
2817 BFD_RELOC_PPC_EMB_SDA2REL
2819 BFD_RELOC_PPC_EMB_SDA21
2821 BFD_RELOC_PPC_EMB_MRKREF
2823 BFD_RELOC_PPC_EMB_RELSEC16
2825 BFD_RELOC_PPC_EMB_RELST_LO
2827 BFD_RELOC_PPC_EMB_RELST_HI
2829 BFD_RELOC_PPC_EMB_RELST_HA
2831 BFD_RELOC_PPC_EMB_BIT_FLD
2833 BFD_RELOC_PPC_EMB_RELSDA
2835 BFD_RELOC_PPC_VLE_REL8
2837 BFD_RELOC_PPC_VLE_REL15
2839 BFD_RELOC_PPC_VLE_REL24
2841 BFD_RELOC_PPC_VLE_LO16A
2843 BFD_RELOC_PPC_VLE_LO16D
2845 BFD_RELOC_PPC_VLE_HI16A
2847 BFD_RELOC_PPC_VLE_HI16D
2849 BFD_RELOC_PPC_VLE_HA16A
2851 BFD_RELOC_PPC_VLE_HA16D
2853 BFD_RELOC_PPC_VLE_SDA21
2855 BFD_RELOC_PPC_VLE_SDA21_LO
2857 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2859 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2861 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2863 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2865 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2867 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2869 BFD_RELOC_PPC64_HIGHER
2871 BFD_RELOC_PPC64_HIGHER_S
2873 BFD_RELOC_PPC64_HIGHEST
2875 BFD_RELOC_PPC64_HIGHEST_S
2877 BFD_RELOC_PPC64_TOC16_LO
2879 BFD_RELOC_PPC64_TOC16_HI
2881 BFD_RELOC_PPC64_TOC16_HA
2885 BFD_RELOC_PPC64_PLTGOT16
2887 BFD_RELOC_PPC64_PLTGOT16_LO
2889 BFD_RELOC_PPC64_PLTGOT16_HI
2891 BFD_RELOC_PPC64_PLTGOT16_HA
2893 BFD_RELOC_PPC64_ADDR16_DS
2895 BFD_RELOC_PPC64_ADDR16_LO_DS
2897 BFD_RELOC_PPC64_GOT16_DS
2899 BFD_RELOC_PPC64_GOT16_LO_DS
2901 BFD_RELOC_PPC64_PLT16_LO_DS
2903 BFD_RELOC_PPC64_SECTOFF_DS
2905 BFD_RELOC_PPC64_SECTOFF_LO_DS
2907 BFD_RELOC_PPC64_TOC16_DS
2909 BFD_RELOC_PPC64_TOC16_LO_DS
2911 BFD_RELOC_PPC64_PLTGOT16_DS
2913 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2915 BFD_RELOC_PPC64_ADDR16_HIGH
2917 BFD_RELOC_PPC64_ADDR16_HIGHA
2919 BFD_RELOC_PPC64_ADDR64_LOCAL
2921 Power(rs6000) and PowerPC relocations.
2930 BFD_RELOC_PPC_DTPMOD
2932 BFD_RELOC_PPC_TPREL16
2934 BFD_RELOC_PPC_TPREL16_LO
2936 BFD_RELOC_PPC_TPREL16_HI
2938 BFD_RELOC_PPC_TPREL16_HA
2942 BFD_RELOC_PPC_DTPREL16
2944 BFD_RELOC_PPC_DTPREL16_LO
2946 BFD_RELOC_PPC_DTPREL16_HI
2948 BFD_RELOC_PPC_DTPREL16_HA
2950 BFD_RELOC_PPC_DTPREL
2952 BFD_RELOC_PPC_GOT_TLSGD16
2954 BFD_RELOC_PPC_GOT_TLSGD16_LO
2956 BFD_RELOC_PPC_GOT_TLSGD16_HI
2958 BFD_RELOC_PPC_GOT_TLSGD16_HA
2960 BFD_RELOC_PPC_GOT_TLSLD16
2962 BFD_RELOC_PPC_GOT_TLSLD16_LO
2964 BFD_RELOC_PPC_GOT_TLSLD16_HI
2966 BFD_RELOC_PPC_GOT_TLSLD16_HA
2968 BFD_RELOC_PPC_GOT_TPREL16
2970 BFD_RELOC_PPC_GOT_TPREL16_LO
2972 BFD_RELOC_PPC_GOT_TPREL16_HI
2974 BFD_RELOC_PPC_GOT_TPREL16_HA
2976 BFD_RELOC_PPC_GOT_DTPREL16
2978 BFD_RELOC_PPC_GOT_DTPREL16_LO
2980 BFD_RELOC_PPC_GOT_DTPREL16_HI
2982 BFD_RELOC_PPC_GOT_DTPREL16_HA
2984 BFD_RELOC_PPC64_TPREL16_DS
2986 BFD_RELOC_PPC64_TPREL16_LO_DS
2988 BFD_RELOC_PPC64_TPREL16_HIGHER
2990 BFD_RELOC_PPC64_TPREL16_HIGHERA
2992 BFD_RELOC_PPC64_TPREL16_HIGHEST
2994 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2996 BFD_RELOC_PPC64_DTPREL16_DS
2998 BFD_RELOC_PPC64_DTPREL16_LO_DS
3000 BFD_RELOC_PPC64_DTPREL16_HIGHER
3002 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3004 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3006 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3008 BFD_RELOC_PPC64_TPREL16_HIGH
3010 BFD_RELOC_PPC64_TPREL16_HIGHA
3012 BFD_RELOC_PPC64_DTPREL16_HIGH
3014 BFD_RELOC_PPC64_DTPREL16_HIGHA
3016 PowerPC and PowerPC64 thread-local storage relocations.
3021 IBM 370/390 relocations
3026 The type of reloc used to build a constructor table - at the moment
3027 probably a 32 bit wide absolute relocation, but the target can choose.
3028 It generally does map to one of the other relocation types.
3031 BFD_RELOC_ARM_PCREL_BRANCH
3033 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3034 not stored in the instruction.
3036 BFD_RELOC_ARM_PCREL_BLX
3038 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3039 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3040 field in the instruction.
3042 BFD_RELOC_THUMB_PCREL_BLX
3044 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3045 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3046 field in the instruction.
3048 BFD_RELOC_ARM_PCREL_CALL
3050 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3052 BFD_RELOC_ARM_PCREL_JUMP
3054 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3057 BFD_RELOC_THUMB_PCREL_BRANCH7
3059 BFD_RELOC_THUMB_PCREL_BRANCH9
3061 BFD_RELOC_THUMB_PCREL_BRANCH12
3063 BFD_RELOC_THUMB_PCREL_BRANCH20
3065 BFD_RELOC_THUMB_PCREL_BRANCH23
3067 BFD_RELOC_THUMB_PCREL_BRANCH25
3069 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3070 The lowest bit must be zero and is not stored in the instruction.
3071 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3072 "nn" one smaller in all cases. Note further that BRANCH23
3073 corresponds to R_ARM_THM_CALL.
3076 BFD_RELOC_ARM_OFFSET_IMM
3078 12-bit immediate offset, used in ARM-format ldr and str instructions.
3081 BFD_RELOC_ARM_THUMB_OFFSET
3083 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3086 BFD_RELOC_ARM_TARGET1
3088 Pc-relative or absolute relocation depending on target. Used for
3089 entries in .init_array sections.
3091 BFD_RELOC_ARM_ROSEGREL32
3093 Read-only segment base relative address.
3095 BFD_RELOC_ARM_SBREL32
3097 Data segment base relative address.
3099 BFD_RELOC_ARM_TARGET2
3101 This reloc is used for references to RTTI data from exception handling
3102 tables. The actual definition depends on the target. It may be a
3103 pc-relative or some form of GOT-indirect relocation.
3105 BFD_RELOC_ARM_PREL31
3107 31-bit PC relative address.
3113 BFD_RELOC_ARM_MOVW_PCREL
3115 BFD_RELOC_ARM_MOVT_PCREL
3117 BFD_RELOC_ARM_THUMB_MOVW
3119 BFD_RELOC_ARM_THUMB_MOVT
3121 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3123 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3125 Low and High halfword relocations for MOVW and MOVT instructions.
3128 BFD_RELOC_ARM_JUMP_SLOT
3130 BFD_RELOC_ARM_GLOB_DAT
3136 BFD_RELOC_ARM_RELATIVE
3138 BFD_RELOC_ARM_GOTOFF
3142 BFD_RELOC_ARM_GOT_PREL
3144 Relocations for setting up GOTs and PLTs for shared libraries.
3147 BFD_RELOC_ARM_TLS_GD32
3149 BFD_RELOC_ARM_TLS_LDO32
3151 BFD_RELOC_ARM_TLS_LDM32
3153 BFD_RELOC_ARM_TLS_DTPOFF32
3155 BFD_RELOC_ARM_TLS_DTPMOD32
3157 BFD_RELOC_ARM_TLS_TPOFF32
3159 BFD_RELOC_ARM_TLS_IE32
3161 BFD_RELOC_ARM_TLS_LE32
3163 BFD_RELOC_ARM_TLS_GOTDESC
3165 BFD_RELOC_ARM_TLS_CALL
3167 BFD_RELOC_ARM_THM_TLS_CALL
3169 BFD_RELOC_ARM_TLS_DESCSEQ
3171 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3173 BFD_RELOC_ARM_TLS_DESC
3175 ARM thread-local storage relocations.
3178 BFD_RELOC_ARM_ALU_PC_G0_NC
3180 BFD_RELOC_ARM_ALU_PC_G0
3182 BFD_RELOC_ARM_ALU_PC_G1_NC
3184 BFD_RELOC_ARM_ALU_PC_G1
3186 BFD_RELOC_ARM_ALU_PC_G2
3188 BFD_RELOC_ARM_LDR_PC_G0
3190 BFD_RELOC_ARM_LDR_PC_G1
3192 BFD_RELOC_ARM_LDR_PC_G2
3194 BFD_RELOC_ARM_LDRS_PC_G0
3196 BFD_RELOC_ARM_LDRS_PC_G1
3198 BFD_RELOC_ARM_LDRS_PC_G2
3200 BFD_RELOC_ARM_LDC_PC_G0
3202 BFD_RELOC_ARM_LDC_PC_G1
3204 BFD_RELOC_ARM_LDC_PC_G2
3206 BFD_RELOC_ARM_ALU_SB_G0_NC
3208 BFD_RELOC_ARM_ALU_SB_G0
3210 BFD_RELOC_ARM_ALU_SB_G1_NC
3212 BFD_RELOC_ARM_ALU_SB_G1
3214 BFD_RELOC_ARM_ALU_SB_G2
3216 BFD_RELOC_ARM_LDR_SB_G0
3218 BFD_RELOC_ARM_LDR_SB_G1
3220 BFD_RELOC_ARM_LDR_SB_G2
3222 BFD_RELOC_ARM_LDRS_SB_G0
3224 BFD_RELOC_ARM_LDRS_SB_G1
3226 BFD_RELOC_ARM_LDRS_SB_G2
3228 BFD_RELOC_ARM_LDC_SB_G0
3230 BFD_RELOC_ARM_LDC_SB_G1
3232 BFD_RELOC_ARM_LDC_SB_G2
3234 ARM group relocations.
3239 Annotation of BX instructions.
3242 BFD_RELOC_ARM_IRELATIVE
3244 ARM support for STT_GNU_IFUNC.
3247 BFD_RELOC_ARM_IMMEDIATE
3249 BFD_RELOC_ARM_ADRL_IMMEDIATE
3251 BFD_RELOC_ARM_T32_IMMEDIATE
3253 BFD_RELOC_ARM_T32_ADD_IMM
3255 BFD_RELOC_ARM_T32_IMM12
3257 BFD_RELOC_ARM_T32_ADD_PC12
3259 BFD_RELOC_ARM_SHIFT_IMM
3269 BFD_RELOC_ARM_CP_OFF_IMM
3271 BFD_RELOC_ARM_CP_OFF_IMM_S2
3273 BFD_RELOC_ARM_T32_CP_OFF_IMM
3275 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3277 BFD_RELOC_ARM_ADR_IMM
3279 BFD_RELOC_ARM_LDR_IMM
3281 BFD_RELOC_ARM_LITERAL
3283 BFD_RELOC_ARM_IN_POOL
3285 BFD_RELOC_ARM_OFFSET_IMM8
3287 BFD_RELOC_ARM_T32_OFFSET_U8
3289 BFD_RELOC_ARM_T32_OFFSET_IMM
3291 BFD_RELOC_ARM_HWLITERAL
3293 BFD_RELOC_ARM_THUMB_ADD
3295 BFD_RELOC_ARM_THUMB_IMM
3297 BFD_RELOC_ARM_THUMB_SHIFT
3299 These relocs are only used within the ARM assembler. They are not
3300 (at present) written to any object files.
3303 BFD_RELOC_SH_PCDISP8BY2
3305 BFD_RELOC_SH_PCDISP12BY2
3313 BFD_RELOC_SH_DISP12BY2
3315 BFD_RELOC_SH_DISP12BY4
3317 BFD_RELOC_SH_DISP12BY8
3321 BFD_RELOC_SH_DISP20BY8
3325 BFD_RELOC_SH_IMM4BY2
3327 BFD_RELOC_SH_IMM4BY4
3331 BFD_RELOC_SH_IMM8BY2
3333 BFD_RELOC_SH_IMM8BY4
3335 BFD_RELOC_SH_PCRELIMM8BY2
3337 BFD_RELOC_SH_PCRELIMM8BY4
3339 BFD_RELOC_SH_SWITCH16
3341 BFD_RELOC_SH_SWITCH32
3355 BFD_RELOC_SH_LOOP_START
3357 BFD_RELOC_SH_LOOP_END
3361 BFD_RELOC_SH_GLOB_DAT
3363 BFD_RELOC_SH_JMP_SLOT
3365 BFD_RELOC_SH_RELATIVE
3369 BFD_RELOC_SH_GOT_LOW16
3371 BFD_RELOC_SH_GOT_MEDLOW16
3373 BFD_RELOC_SH_GOT_MEDHI16
3375 BFD_RELOC_SH_GOT_HI16
3377 BFD_RELOC_SH_GOTPLT_LOW16
3379 BFD_RELOC_SH_GOTPLT_MEDLOW16
3381 BFD_RELOC_SH_GOTPLT_MEDHI16
3383 BFD_RELOC_SH_GOTPLT_HI16
3385 BFD_RELOC_SH_PLT_LOW16
3387 BFD_RELOC_SH_PLT_MEDLOW16
3389 BFD_RELOC_SH_PLT_MEDHI16
3391 BFD_RELOC_SH_PLT_HI16
3393 BFD_RELOC_SH_GOTOFF_LOW16
3395 BFD_RELOC_SH_GOTOFF_MEDLOW16
3397 BFD_RELOC_SH_GOTOFF_MEDHI16
3399 BFD_RELOC_SH_GOTOFF_HI16
3401 BFD_RELOC_SH_GOTPC_LOW16
3403 BFD_RELOC_SH_GOTPC_MEDLOW16
3405 BFD_RELOC_SH_GOTPC_MEDHI16
3407 BFD_RELOC_SH_GOTPC_HI16
3411 BFD_RELOC_SH_GLOB_DAT64
3413 BFD_RELOC_SH_JMP_SLOT64
3415 BFD_RELOC_SH_RELATIVE64
3417 BFD_RELOC_SH_GOT10BY4
3419 BFD_RELOC_SH_GOT10BY8
3421 BFD_RELOC_SH_GOTPLT10BY4
3423 BFD_RELOC_SH_GOTPLT10BY8
3425 BFD_RELOC_SH_GOTPLT32
3427 BFD_RELOC_SH_SHMEDIA_CODE
3433 BFD_RELOC_SH_IMMS6BY32
3439 BFD_RELOC_SH_IMMS10BY2
3441 BFD_RELOC_SH_IMMS10BY4
3443 BFD_RELOC_SH_IMMS10BY8
3449 BFD_RELOC_SH_IMM_LOW16
3451 BFD_RELOC_SH_IMM_LOW16_PCREL
3453 BFD_RELOC_SH_IMM_MEDLOW16
3455 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3457 BFD_RELOC_SH_IMM_MEDHI16
3459 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3461 BFD_RELOC_SH_IMM_HI16
3463 BFD_RELOC_SH_IMM_HI16_PCREL
3467 BFD_RELOC_SH_TLS_GD_32
3469 BFD_RELOC_SH_TLS_LD_32
3471 BFD_RELOC_SH_TLS_LDO_32
3473 BFD_RELOC_SH_TLS_IE_32
3475 BFD_RELOC_SH_TLS_LE_32
3477 BFD_RELOC_SH_TLS_DTPMOD32
3479 BFD_RELOC_SH_TLS_DTPOFF32
3481 BFD_RELOC_SH_TLS_TPOFF32
3485 BFD_RELOC_SH_GOTOFF20
3487 BFD_RELOC_SH_GOTFUNCDESC
3489 BFD_RELOC_SH_GOTFUNCDESC20
3491 BFD_RELOC_SH_GOTOFFFUNCDESC
3493 BFD_RELOC_SH_GOTOFFFUNCDESC20
3495 BFD_RELOC_SH_FUNCDESC
3497 Renesas / SuperH SH relocs. Not all of these appear in object files.
3500 BFD_RELOC_ARC_B22_PCREL
3503 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3504 not stored in the instruction. The high 20 bits are installed in bits 26
3505 through 7 of the instruction.
3509 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3510 stored in the instruction. The high 24 bits are installed in bits 23
3514 BFD_RELOC_BFIN_16_IMM
3516 ADI Blackfin 16 bit immediate absolute reloc.
3518 BFD_RELOC_BFIN_16_HIGH
3520 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3522 BFD_RELOC_BFIN_4_PCREL
3524 ADI Blackfin 'a' part of LSETUP.
3526 BFD_RELOC_BFIN_5_PCREL
3530 BFD_RELOC_BFIN_16_LOW
3532 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3534 BFD_RELOC_BFIN_10_PCREL
3538 BFD_RELOC_BFIN_11_PCREL
3540 ADI Blackfin 'b' part of LSETUP.
3542 BFD_RELOC_BFIN_12_PCREL_JUMP
3546 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3548 ADI Blackfin Short jump, pcrel.
3550 BFD_RELOC_BFIN_24_PCREL_CALL_X
3552 ADI Blackfin Call.x not implemented.
3554 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3556 ADI Blackfin Long Jump pcrel.
3558 BFD_RELOC_BFIN_GOT17M4
3560 BFD_RELOC_BFIN_GOTHI
3562 BFD_RELOC_BFIN_GOTLO
3564 BFD_RELOC_BFIN_FUNCDESC
3566 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3568 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3570 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3572 BFD_RELOC_BFIN_FUNCDESC_VALUE
3574 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3576 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3578 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3580 BFD_RELOC_BFIN_GOTOFF17M4
3582 BFD_RELOC_BFIN_GOTOFFHI
3584 BFD_RELOC_BFIN_GOTOFFLO
3586 ADI Blackfin FD-PIC relocations.
3590 ADI Blackfin GOT relocation.
3592 BFD_RELOC_BFIN_PLTPC
3594 ADI Blackfin PLTPC relocation.
3596 BFD_ARELOC_BFIN_PUSH
3598 ADI Blackfin arithmetic relocation.
3600 BFD_ARELOC_BFIN_CONST
3602 ADI Blackfin arithmetic relocation.
3606 ADI Blackfin arithmetic relocation.
3610 ADI Blackfin arithmetic relocation.
3612 BFD_ARELOC_BFIN_MULT
3614 ADI Blackfin arithmetic relocation.
3618 ADI Blackfin arithmetic relocation.
3622 ADI Blackfin arithmetic relocation.
3624 BFD_ARELOC_BFIN_LSHIFT
3626 ADI Blackfin arithmetic relocation.
3628 BFD_ARELOC_BFIN_RSHIFT
3630 ADI Blackfin arithmetic relocation.
3634 ADI Blackfin arithmetic relocation.
3638 ADI Blackfin arithmetic relocation.
3642 ADI Blackfin arithmetic relocation.
3644 BFD_ARELOC_BFIN_LAND
3646 ADI Blackfin arithmetic relocation.
3650 ADI Blackfin arithmetic relocation.
3654 ADI Blackfin arithmetic relocation.
3658 ADI Blackfin arithmetic relocation.
3660 BFD_ARELOC_BFIN_COMP
3662 ADI Blackfin arithmetic relocation.
3664 BFD_ARELOC_BFIN_PAGE
3666 ADI Blackfin arithmetic relocation.
3668 BFD_ARELOC_BFIN_HWPAGE
3670 ADI Blackfin arithmetic relocation.
3672 BFD_ARELOC_BFIN_ADDR
3674 ADI Blackfin arithmetic relocation.
3677 BFD_RELOC_D10V_10_PCREL_R
3679 Mitsubishi D10V relocs.
3680 This is a 10-bit reloc with the right 2 bits
3683 BFD_RELOC_D10V_10_PCREL_L
3685 Mitsubishi D10V relocs.
3686 This is a 10-bit reloc with the right 2 bits
3687 assumed to be 0. This is the same as the previous reloc
3688 except it is in the left container, i.e.,
3689 shifted left 15 bits.
3693 This is an 18-bit reloc with the right 2 bits
3696 BFD_RELOC_D10V_18_PCREL
3698 This is an 18-bit reloc with the right 2 bits
3704 Mitsubishi D30V relocs.
3705 This is a 6-bit absolute reloc.
3707 BFD_RELOC_D30V_9_PCREL
3709 This is a 6-bit pc-relative reloc with
3710 the right 3 bits assumed to be 0.
3712 BFD_RELOC_D30V_9_PCREL_R
3714 This is a 6-bit pc-relative reloc with
3715 the right 3 bits assumed to be 0. Same
3716 as the previous reloc but on the right side
3721 This is a 12-bit absolute reloc with the
3722 right 3 bitsassumed to be 0.
3724 BFD_RELOC_D30V_15_PCREL
3726 This is a 12-bit pc-relative reloc with
3727 the right 3 bits assumed to be 0.
3729 BFD_RELOC_D30V_15_PCREL_R
3731 This is a 12-bit pc-relative reloc with
3732 the right 3 bits assumed to be 0. Same
3733 as the previous reloc but on the right side
3738 This is an 18-bit absolute reloc with
3739 the right 3 bits assumed to be 0.
3741 BFD_RELOC_D30V_21_PCREL
3743 This is an 18-bit pc-relative reloc with
3744 the right 3 bits assumed to be 0.
3746 BFD_RELOC_D30V_21_PCREL_R
3748 This is an 18-bit pc-relative reloc with
3749 the right 3 bits assumed to be 0. Same
3750 as the previous reloc but on the right side
3755 This is a 32-bit absolute reloc.
3757 BFD_RELOC_D30V_32_PCREL
3759 This is a 32-bit pc-relative reloc.
3762 BFD_RELOC_DLX_HI16_S
3777 BFD_RELOC_M32C_RL_JUMP
3779 BFD_RELOC_M32C_RL_1ADDR
3781 BFD_RELOC_M32C_RL_2ADDR
3783 Renesas M16C/M32C Relocations.
3788 Renesas M32R (formerly Mitsubishi M32R) relocs.
3789 This is a 24 bit absolute address.
3791 BFD_RELOC_M32R_10_PCREL
3793 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3795 BFD_RELOC_M32R_18_PCREL
3797 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3799 BFD_RELOC_M32R_26_PCREL
3801 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3803 BFD_RELOC_M32R_HI16_ULO
3805 This is a 16-bit reloc containing the high 16 bits of an address
3806 used when the lower 16 bits are treated as unsigned.
3808 BFD_RELOC_M32R_HI16_SLO
3810 This is a 16-bit reloc containing the high 16 bits of an address
3811 used when the lower 16 bits are treated as signed.
3815 This is a 16-bit reloc containing the lower 16 bits of an address.
3817 BFD_RELOC_M32R_SDA16
3819 This is a 16-bit reloc containing the small data area offset for use in
3820 add3, load, and store instructions.
3822 BFD_RELOC_M32R_GOT24
3824 BFD_RELOC_M32R_26_PLTREL
3828 BFD_RELOC_M32R_GLOB_DAT
3830 BFD_RELOC_M32R_JMP_SLOT
3832 BFD_RELOC_M32R_RELATIVE
3834 BFD_RELOC_M32R_GOTOFF
3836 BFD_RELOC_M32R_GOTOFF_HI_ULO
3838 BFD_RELOC_M32R_GOTOFF_HI_SLO
3840 BFD_RELOC_M32R_GOTOFF_LO
3842 BFD_RELOC_M32R_GOTPC24
3844 BFD_RELOC_M32R_GOT16_HI_ULO
3846 BFD_RELOC_M32R_GOT16_HI_SLO
3848 BFD_RELOC_M32R_GOT16_LO
3850 BFD_RELOC_M32R_GOTPC_HI_ULO
3852 BFD_RELOC_M32R_GOTPC_HI_SLO
3854 BFD_RELOC_M32R_GOTPC_LO
3863 This is a 20 bit absolute address.
3865 BFD_RELOC_NDS32_9_PCREL
3867 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3869 BFD_RELOC_NDS32_WORD_9_PCREL
3871 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3873 BFD_RELOC_NDS32_15_PCREL
3875 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3877 BFD_RELOC_NDS32_17_PCREL
3879 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3881 BFD_RELOC_NDS32_25_PCREL
3883 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3885 BFD_RELOC_NDS32_HI20
3887 This is a 20-bit reloc containing the high 20 bits of an address
3888 used with the lower 12 bits
3890 BFD_RELOC_NDS32_LO12S3
3892 This is a 12-bit reloc containing the lower 12 bits of an address
3893 then shift right by 3. This is used with ldi,sdi...
3895 BFD_RELOC_NDS32_LO12S2
3897 This is a 12-bit reloc containing the lower 12 bits of an address
3898 then shift left by 2. This is used with lwi,swi...
3900 BFD_RELOC_NDS32_LO12S1
3902 This is a 12-bit reloc containing the lower 12 bits of an address
3903 then shift left by 1. This is used with lhi,shi...
3905 BFD_RELOC_NDS32_LO12S0
3907 This is a 12-bit reloc containing the lower 12 bits of an address
3908 then shift left by 0. This is used with lbisbi...
3910 BFD_RELOC_NDS32_LO12S0_ORI
3912 This is a 12-bit reloc containing the lower 12 bits of an address
3913 then shift left by 0. This is only used with branch relaxations
3915 BFD_RELOC_NDS32_SDA15S3
3917 This is a 15-bit reloc containing the small data area 18-bit signed offset
3918 and shift left by 3 for use in ldi, sdi...
3920 BFD_RELOC_NDS32_SDA15S2
3922 This is a 15-bit reloc containing the small data area 17-bit signed offset
3923 and shift left by 2 for use in lwi, swi...
3925 BFD_RELOC_NDS32_SDA15S1
3927 This is a 15-bit reloc containing the small data area 16-bit signed offset
3928 and shift left by 1 for use in lhi, shi...
3930 BFD_RELOC_NDS32_SDA15S0
3932 This is a 15-bit reloc containing the small data area 15-bit signed offset
3933 and shift left by 0 for use in lbi, sbi...
3935 BFD_RELOC_NDS32_SDA16S3
3937 This is a 16-bit reloc containing the small data area 16-bit signed offset
3940 BFD_RELOC_NDS32_SDA17S2
3942 This is a 17-bit reloc containing the small data area 17-bit signed offset
3943 and shift left by 2 for use in lwi.gp, swi.gp...
3945 BFD_RELOC_NDS32_SDA18S1
3947 This is a 18-bit reloc containing the small data area 18-bit signed offset
3948 and shift left by 1 for use in lhi.gp, shi.gp...
3950 BFD_RELOC_NDS32_SDA19S0
3952 This is a 19-bit reloc containing the small data area 19-bit signed offset
3953 and shift left by 0 for use in lbi.gp, sbi.gp...
3955 BFD_RELOC_NDS32_GOT20
3957 BFD_RELOC_NDS32_9_PLTREL
3959 BFD_RELOC_NDS32_25_PLTREL
3961 BFD_RELOC_NDS32_COPY
3963 BFD_RELOC_NDS32_GLOB_DAT
3965 BFD_RELOC_NDS32_JMP_SLOT
3967 BFD_RELOC_NDS32_RELATIVE
3969 BFD_RELOC_NDS32_GOTOFF
3971 BFD_RELOC_NDS32_GOTOFF_HI20
3973 BFD_RELOC_NDS32_GOTOFF_LO12
3975 BFD_RELOC_NDS32_GOTPC20
3977 BFD_RELOC_NDS32_GOT_HI20
3979 BFD_RELOC_NDS32_GOT_LO12
3981 BFD_RELOC_NDS32_GOTPC_HI20
3983 BFD_RELOC_NDS32_GOTPC_LO12
3987 BFD_RELOC_NDS32_INSN16
3989 BFD_RELOC_NDS32_LABEL
3991 BFD_RELOC_NDS32_LONGCALL1
3993 BFD_RELOC_NDS32_LONGCALL2
3995 BFD_RELOC_NDS32_LONGCALL3
3997 BFD_RELOC_NDS32_LONGJUMP1
3999 BFD_RELOC_NDS32_LONGJUMP2
4001 BFD_RELOC_NDS32_LONGJUMP3
4003 BFD_RELOC_NDS32_LOADSTORE
4005 BFD_RELOC_NDS32_9_FIXED
4007 BFD_RELOC_NDS32_15_FIXED
4009 BFD_RELOC_NDS32_17_FIXED
4011 BFD_RELOC_NDS32_25_FIXED
4013 BFD_RELOC_NDS32_LONGCALL4
4015 BFD_RELOC_NDS32_LONGCALL5
4017 BFD_RELOC_NDS32_LONGCALL6
4019 BFD_RELOC_NDS32_LONGJUMP4
4021 BFD_RELOC_NDS32_LONGJUMP5
4023 BFD_RELOC_NDS32_LONGJUMP6
4025 BFD_RELOC_NDS32_LONGJUMP7
4029 BFD_RELOC_NDS32_PLTREL_HI20
4031 BFD_RELOC_NDS32_PLTREL_LO12
4033 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4035 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4039 BFD_RELOC_NDS32_SDA12S2_DP
4041 BFD_RELOC_NDS32_SDA12S2_SP
4043 BFD_RELOC_NDS32_LO12S2_DP
4045 BFD_RELOC_NDS32_LO12S2_SP
4049 BFD_RELOC_NDS32_DWARF2_OP1
4051 BFD_RELOC_NDS32_DWARF2_OP2
4053 BFD_RELOC_NDS32_DWARF2_LEB
4055 for dwarf2 debug_line.
4057 BFD_RELOC_NDS32_UPDATE_TA
4059 for eliminate 16-bit instructions
4061 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4063 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4065 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4067 BFD_RELOC_NDS32_GOT_LO15
4069 BFD_RELOC_NDS32_GOT_LO19
4071 BFD_RELOC_NDS32_GOTOFF_LO15
4073 BFD_RELOC_NDS32_GOTOFF_LO19
4075 BFD_RELOC_NDS32_GOT15S2
4077 BFD_RELOC_NDS32_GOT17S2
4079 for PIC object relaxation
4084 This is a 5 bit absolute address.
4086 BFD_RELOC_NDS32_10_UPCREL
4088 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4090 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4092 If fp were omitted, fp can used as another gp.
4094 BFD_RELOC_NDS32_RELAX_ENTRY
4096 BFD_RELOC_NDS32_GOT_SUFF
4098 BFD_RELOC_NDS32_GOTOFF_SUFF
4100 BFD_RELOC_NDS32_PLT_GOT_SUFF
4102 BFD_RELOC_NDS32_MULCALL_SUFF
4106 BFD_RELOC_NDS32_PTR_COUNT
4108 BFD_RELOC_NDS32_PTR_RESOLVED
4110 BFD_RELOC_NDS32_PLTBLOCK
4112 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4114 BFD_RELOC_NDS32_RELAX_REGION_END
4116 BFD_RELOC_NDS32_MINUEND
4118 BFD_RELOC_NDS32_SUBTRAHEND
4120 BFD_RELOC_NDS32_DIFF8
4122 BFD_RELOC_NDS32_DIFF16
4124 BFD_RELOC_NDS32_DIFF32
4126 BFD_RELOC_NDS32_DIFF_ULEB128
4128 BFD_RELOC_NDS32_EMPTY
4130 relaxation relative relocation types
4132 BFD_RELOC_NDS32_25_ABS
4134 This is a 25 bit absolute address.
4136 BFD_RELOC_NDS32_DATA
4138 BFD_RELOC_NDS32_TRAN
4140 BFD_RELOC_NDS32_17IFC_PCREL
4142 BFD_RELOC_NDS32_10IFCU_PCREL
4144 For ex9 and ifc using.
4146 BFD_RELOC_NDS32_TPOFF
4148 BFD_RELOC_NDS32_TLS_LE_HI20
4150 BFD_RELOC_NDS32_TLS_LE_LO12
4152 BFD_RELOC_NDS32_TLS_LE_ADD
4154 BFD_RELOC_NDS32_TLS_LE_LS
4156 BFD_RELOC_NDS32_GOTTPOFF
4158 BFD_RELOC_NDS32_TLS_IE_HI20
4160 BFD_RELOC_NDS32_TLS_IE_LO12S2
4162 BFD_RELOC_NDS32_TLS_TPOFF
4164 BFD_RELOC_NDS32_TLS_LE_20
4166 BFD_RELOC_NDS32_TLS_LE_15S0
4168 BFD_RELOC_NDS32_TLS_LE_15S1
4170 BFD_RELOC_NDS32_TLS_LE_15S2
4176 BFD_RELOC_V850_9_PCREL
4178 This is a 9-bit reloc
4180 BFD_RELOC_V850_22_PCREL
4182 This is a 22-bit reloc
4185 BFD_RELOC_V850_SDA_16_16_OFFSET
4187 This is a 16 bit offset from the short data area pointer.
4189 BFD_RELOC_V850_SDA_15_16_OFFSET
4191 This is a 16 bit offset (of which only 15 bits are used) from the
4192 short data area pointer.
4194 BFD_RELOC_V850_ZDA_16_16_OFFSET
4196 This is a 16 bit offset from the zero data area pointer.
4198 BFD_RELOC_V850_ZDA_15_16_OFFSET
4200 This is a 16 bit offset (of which only 15 bits are used) from the
4201 zero data area pointer.
4203 BFD_RELOC_V850_TDA_6_8_OFFSET
4205 This is an 8 bit offset (of which only 6 bits are used) from the
4206 tiny data area pointer.
4208 BFD_RELOC_V850_TDA_7_8_OFFSET
4210 This is an 8bit offset (of which only 7 bits are used) from the tiny
4213 BFD_RELOC_V850_TDA_7_7_OFFSET
4215 This is a 7 bit offset from the tiny data area pointer.
4217 BFD_RELOC_V850_TDA_16_16_OFFSET
4219 This is a 16 bit offset from the tiny data area pointer.
4222 BFD_RELOC_V850_TDA_4_5_OFFSET
4224 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4227 BFD_RELOC_V850_TDA_4_4_OFFSET
4229 This is a 4 bit offset from the tiny data area pointer.
4231 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4233 This is a 16 bit offset from the short data area pointer, with the
4234 bits placed non-contiguously in the instruction.
4236 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4238 This is a 16 bit offset from the zero data area pointer, with the
4239 bits placed non-contiguously in the instruction.
4241 BFD_RELOC_V850_CALLT_6_7_OFFSET
4243 This is a 6 bit offset from the call table base pointer.
4245 BFD_RELOC_V850_CALLT_16_16_OFFSET
4247 This is a 16 bit offset from the call table base pointer.
4249 BFD_RELOC_V850_LONGCALL
4251 Used for relaxing indirect function calls.
4253 BFD_RELOC_V850_LONGJUMP
4255 Used for relaxing indirect jumps.
4257 BFD_RELOC_V850_ALIGN
4259 Used to maintain alignment whilst relaxing.
4261 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4263 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4266 BFD_RELOC_V850_16_PCREL
4268 This is a 16-bit reloc.
4270 BFD_RELOC_V850_17_PCREL
4272 This is a 17-bit reloc.
4276 This is a 23-bit reloc.
4278 BFD_RELOC_V850_32_PCREL
4280 This is a 32-bit reloc.
4282 BFD_RELOC_V850_32_ABS
4284 This is a 32-bit reloc.
4286 BFD_RELOC_V850_16_SPLIT_OFFSET
4288 This is a 16-bit reloc.
4290 BFD_RELOC_V850_16_S1
4292 This is a 16-bit reloc.
4294 BFD_RELOC_V850_LO16_S1
4296 Low 16 bits. 16 bit shifted by 1.
4298 BFD_RELOC_V850_CALLT_15_16_OFFSET
4300 This is a 16 bit offset from the call table base pointer.
4302 BFD_RELOC_V850_32_GOTPCREL
4306 BFD_RELOC_V850_16_GOT
4310 BFD_RELOC_V850_32_GOT
4314 BFD_RELOC_V850_22_PLT_PCREL
4318 BFD_RELOC_V850_32_PLT_PCREL
4326 BFD_RELOC_V850_GLOB_DAT
4330 BFD_RELOC_V850_JMP_SLOT
4334 BFD_RELOC_V850_RELATIVE
4338 BFD_RELOC_V850_16_GOTOFF
4342 BFD_RELOC_V850_32_GOTOFF
4357 This is a 8bit DP reloc for the tms320c30, where the most
4358 significant 8 bits of a 24 bit word are placed into the least
4359 significant 8 bits of the opcode.
4362 BFD_RELOC_TIC54X_PARTLS7
4364 This is a 7bit reloc for the tms320c54x, where the least
4365 significant 7 bits of a 16 bit word are placed into the least
4366 significant 7 bits of the opcode.
4369 BFD_RELOC_TIC54X_PARTMS9
4371 This is a 9bit DP reloc for the tms320c54x, where the most
4372 significant 9 bits of a 16 bit word are placed into the least
4373 significant 9 bits of the opcode.
4378 This is an extended address 23-bit reloc for the tms320c54x.
4381 BFD_RELOC_TIC54X_16_OF_23
4383 This is a 16-bit reloc for the tms320c54x, where the least
4384 significant 16 bits of a 23-bit extended address are placed into
4388 BFD_RELOC_TIC54X_MS7_OF_23
4390 This is a reloc for the tms320c54x, where the most
4391 significant 7 bits of a 23-bit extended address are placed into
4395 BFD_RELOC_C6000_PCR_S21
4397 BFD_RELOC_C6000_PCR_S12
4399 BFD_RELOC_C6000_PCR_S10
4401 BFD_RELOC_C6000_PCR_S7
4403 BFD_RELOC_C6000_ABS_S16
4405 BFD_RELOC_C6000_ABS_L16
4407 BFD_RELOC_C6000_ABS_H16
4409 BFD_RELOC_C6000_SBR_U15_B
4411 BFD_RELOC_C6000_SBR_U15_H
4413 BFD_RELOC_C6000_SBR_U15_W
4415 BFD_RELOC_C6000_SBR_S16
4417 BFD_RELOC_C6000_SBR_L16_B
4419 BFD_RELOC_C6000_SBR_L16_H
4421 BFD_RELOC_C6000_SBR_L16_W
4423 BFD_RELOC_C6000_SBR_H16_B
4425 BFD_RELOC_C6000_SBR_H16_H
4427 BFD_RELOC_C6000_SBR_H16_W
4429 BFD_RELOC_C6000_SBR_GOT_U15_W
4431 BFD_RELOC_C6000_SBR_GOT_L16_W
4433 BFD_RELOC_C6000_SBR_GOT_H16_W
4435 BFD_RELOC_C6000_DSBT_INDEX
4437 BFD_RELOC_C6000_PREL31
4439 BFD_RELOC_C6000_COPY
4441 BFD_RELOC_C6000_JUMP_SLOT
4443 BFD_RELOC_C6000_EHTYPE
4445 BFD_RELOC_C6000_PCR_H16
4447 BFD_RELOC_C6000_PCR_L16
4449 BFD_RELOC_C6000_ALIGN
4451 BFD_RELOC_C6000_FPHEAD
4453 BFD_RELOC_C6000_NOCMP
4455 TMS320C6000 relocations.
4460 This is a 48 bit reloc for the FR30 that stores 32 bits.
4464 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4467 BFD_RELOC_FR30_6_IN_4
4469 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4472 BFD_RELOC_FR30_8_IN_8
4474 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4477 BFD_RELOC_FR30_9_IN_8
4479 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4482 BFD_RELOC_FR30_10_IN_8
4484 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4487 BFD_RELOC_FR30_9_PCREL
4489 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4490 short offset into 8 bits.
4492 BFD_RELOC_FR30_12_PCREL
4494 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4495 short offset into 11 bits.
4498 BFD_RELOC_MCORE_PCREL_IMM8BY4
4500 BFD_RELOC_MCORE_PCREL_IMM11BY2
4502 BFD_RELOC_MCORE_PCREL_IMM4BY2
4504 BFD_RELOC_MCORE_PCREL_32
4506 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4510 Motorola Mcore relocations.
4519 BFD_RELOC_MEP_PCREL8A2
4521 BFD_RELOC_MEP_PCREL12A2
4523 BFD_RELOC_MEP_PCREL17A2
4525 BFD_RELOC_MEP_PCREL24A2
4527 BFD_RELOC_MEP_PCABS24A2
4539 BFD_RELOC_MEP_TPREL7
4541 BFD_RELOC_MEP_TPREL7A2
4543 BFD_RELOC_MEP_TPREL7A4
4545 BFD_RELOC_MEP_UIMM24
4547 BFD_RELOC_MEP_ADDR24A4
4549 BFD_RELOC_MEP_GNU_VTINHERIT
4551 BFD_RELOC_MEP_GNU_VTENTRY
4553 Toshiba Media Processor Relocations.
4557 BFD_RELOC_METAG_HIADDR16
4559 BFD_RELOC_METAG_LOADDR16
4561 BFD_RELOC_METAG_RELBRANCH
4563 BFD_RELOC_METAG_GETSETOFF
4565 BFD_RELOC_METAG_HIOG
4567 BFD_RELOC_METAG_LOOG
4569 BFD_RELOC_METAG_REL8
4571 BFD_RELOC_METAG_REL16
4573 BFD_RELOC_METAG_HI16_GOTOFF
4575 BFD_RELOC_METAG_LO16_GOTOFF
4577 BFD_RELOC_METAG_GETSET_GOTOFF
4579 BFD_RELOC_METAG_GETSET_GOT
4581 BFD_RELOC_METAG_HI16_GOTPC
4583 BFD_RELOC_METAG_LO16_GOTPC
4585 BFD_RELOC_METAG_HI16_PLT
4587 BFD_RELOC_METAG_LO16_PLT
4589 BFD_RELOC_METAG_RELBRANCH_PLT
4591 BFD_RELOC_METAG_GOTOFF
4595 BFD_RELOC_METAG_COPY
4597 BFD_RELOC_METAG_JMP_SLOT
4599 BFD_RELOC_METAG_RELATIVE
4601 BFD_RELOC_METAG_GLOB_DAT
4603 BFD_RELOC_METAG_TLS_GD
4605 BFD_RELOC_METAG_TLS_LDM
4607 BFD_RELOC_METAG_TLS_LDO_HI16
4609 BFD_RELOC_METAG_TLS_LDO_LO16
4611 BFD_RELOC_METAG_TLS_LDO
4613 BFD_RELOC_METAG_TLS_IE
4615 BFD_RELOC_METAG_TLS_IENONPIC
4617 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4619 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4621 BFD_RELOC_METAG_TLS_TPOFF
4623 BFD_RELOC_METAG_TLS_DTPMOD
4625 BFD_RELOC_METAG_TLS_DTPOFF
4627 BFD_RELOC_METAG_TLS_LE
4629 BFD_RELOC_METAG_TLS_LE_HI16
4631 BFD_RELOC_METAG_TLS_LE_LO16
4633 Imagination Technologies Meta relocations.
4638 BFD_RELOC_MMIX_GETA_1
4640 BFD_RELOC_MMIX_GETA_2
4642 BFD_RELOC_MMIX_GETA_3
4644 These are relocations for the GETA instruction.
4646 BFD_RELOC_MMIX_CBRANCH
4648 BFD_RELOC_MMIX_CBRANCH_J
4650 BFD_RELOC_MMIX_CBRANCH_1
4652 BFD_RELOC_MMIX_CBRANCH_2
4654 BFD_RELOC_MMIX_CBRANCH_3
4656 These are relocations for a conditional branch instruction.
4658 BFD_RELOC_MMIX_PUSHJ
4660 BFD_RELOC_MMIX_PUSHJ_1
4662 BFD_RELOC_MMIX_PUSHJ_2
4664 BFD_RELOC_MMIX_PUSHJ_3
4666 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4668 These are relocations for the PUSHJ instruction.
4672 BFD_RELOC_MMIX_JMP_1
4674 BFD_RELOC_MMIX_JMP_2
4676 BFD_RELOC_MMIX_JMP_3
4678 These are relocations for the JMP instruction.
4680 BFD_RELOC_MMIX_ADDR19
4682 This is a relocation for a relative address as in a GETA instruction or
4685 BFD_RELOC_MMIX_ADDR27
4687 This is a relocation for a relative address as in a JMP instruction.
4689 BFD_RELOC_MMIX_REG_OR_BYTE
4691 This is a relocation for an instruction field that may be a general
4692 register or a value 0..255.
4696 This is a relocation for an instruction field that may be a general
4699 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4701 This is a relocation for two instruction fields holding a register and
4702 an offset, the equivalent of the relocation.
4704 BFD_RELOC_MMIX_LOCAL
4706 This relocation is an assertion that the expression is not allocated as
4707 a global register. It does not modify contents.
4710 BFD_RELOC_AVR_7_PCREL
4712 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4713 short offset into 7 bits.
4715 BFD_RELOC_AVR_13_PCREL
4717 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4718 short offset into 12 bits.
4722 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4723 program memory address) into 16 bits.
4725 BFD_RELOC_AVR_LO8_LDI
4727 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4728 data memory address) into 8 bit immediate value of LDI insn.
4730 BFD_RELOC_AVR_HI8_LDI
4732 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4733 of data memory address) into 8 bit immediate value of LDI insn.
4735 BFD_RELOC_AVR_HH8_LDI
4737 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4738 of program memory address) into 8 bit immediate value of LDI insn.
4740 BFD_RELOC_AVR_MS8_LDI
4742 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4743 of 32 bit value) into 8 bit immediate value of LDI insn.
4745 BFD_RELOC_AVR_LO8_LDI_NEG
4747 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4748 (usually data memory address) into 8 bit immediate value of SUBI insn.
4750 BFD_RELOC_AVR_HI8_LDI_NEG
4752 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4753 (high 8 bit of data memory address) into 8 bit immediate value of
4756 BFD_RELOC_AVR_HH8_LDI_NEG
4758 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4759 (most high 8 bit of program memory address) into 8 bit immediate value
4760 of LDI or SUBI insn.
4762 BFD_RELOC_AVR_MS8_LDI_NEG
4764 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4765 of 32 bit value) into 8 bit immediate value of LDI insn.
4767 BFD_RELOC_AVR_LO8_LDI_PM
4769 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4770 command address) into 8 bit immediate value of LDI insn.
4772 BFD_RELOC_AVR_LO8_LDI_GS
4774 This is a 16 bit reloc for the AVR that stores 8 bit value
4775 (command address) into 8 bit immediate value of LDI insn. If the address
4776 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4779 BFD_RELOC_AVR_HI8_LDI_PM
4781 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4782 of command address) into 8 bit immediate value of LDI insn.
4784 BFD_RELOC_AVR_HI8_LDI_GS
4786 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4787 of command address) into 8 bit immediate value of LDI insn. If the address
4788 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4791 BFD_RELOC_AVR_HH8_LDI_PM
4793 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4794 of command address) into 8 bit immediate value of LDI insn.
4796 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4798 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4799 (usually command address) into 8 bit immediate value of SUBI insn.
4801 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4803 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4804 (high 8 bit of 16 bit command address) into 8 bit immediate value
4807 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4809 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4810 (high 6 bit of 22 bit command address) into 8 bit immediate
4815 This is a 32 bit reloc for the AVR that stores 23 bit value
4820 This is a 16 bit reloc for the AVR that stores all needed bits
4821 for absolute addressing with ldi with overflow check to linktime
4825 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4828 BFD_RELOC_AVR_6_ADIW
4830 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4835 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4836 in .byte lo8(symbol)
4840 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4841 in .byte hi8(symbol)
4845 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4846 in .byte hlo8(symbol)
4850 BFD_RELOC_AVR_DIFF16
4852 BFD_RELOC_AVR_DIFF32
4854 AVR relocations to mark the difference of two local symbols.
4855 These are only needed to support linker relaxation and can be ignored
4856 when not relaxing. The field is set to the value of the difference
4857 assuming no relaxation. The relocation encodes the position of the
4858 second symbol so the linker can determine whether to adjust the field
4861 BFD_RELOC_AVR_LDS_STS_16
4863 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4864 lds and sts instructions supported only tiny core.
4868 This is a 6 bit reloc for the AVR that stores an I/O register
4869 number for the IN and OUT instructions
4873 This is a 5 bit reloc for the AVR that stores an I/O register
4874 number for the SBIC, SBIS, SBI and CBI instructions
4878 BFD_RELOC_RL78_NEG16
4880 BFD_RELOC_RL78_NEG24
4882 BFD_RELOC_RL78_NEG32
4884 BFD_RELOC_RL78_16_OP
4886 BFD_RELOC_RL78_24_OP
4888 BFD_RELOC_RL78_32_OP
4896 BFD_RELOC_RL78_DIR3U_PCREL
4900 BFD_RELOC_RL78_GPRELB
4902 BFD_RELOC_RL78_GPRELW
4904 BFD_RELOC_RL78_GPRELL
4908 BFD_RELOC_RL78_OP_SUBTRACT
4910 BFD_RELOC_RL78_OP_NEG
4912 BFD_RELOC_RL78_OP_AND
4914 BFD_RELOC_RL78_OP_SHRA
4918 BFD_RELOC_RL78_ABS16
4920 BFD_RELOC_RL78_ABS16_REV
4922 BFD_RELOC_RL78_ABS32
4924 BFD_RELOC_RL78_ABS32_REV
4926 BFD_RELOC_RL78_ABS16U
4928 BFD_RELOC_RL78_ABS16UW
4930 BFD_RELOC_RL78_ABS16UL
4932 BFD_RELOC_RL78_RELAX
4942 Renesas RL78 Relocations.
4965 BFD_RELOC_RX_DIR3U_PCREL
4977 BFD_RELOC_RX_OP_SUBTRACT
4985 BFD_RELOC_RX_ABS16_REV
4989 BFD_RELOC_RX_ABS32_REV
4993 BFD_RELOC_RX_ABS16UW
4995 BFD_RELOC_RX_ABS16UL
4999 Renesas RX Relocations.
5012 32 bit PC relative PLT address.
5016 Copy symbol at runtime.
5018 BFD_RELOC_390_GLOB_DAT
5022 BFD_RELOC_390_JMP_SLOT
5026 BFD_RELOC_390_RELATIVE
5028 Adjust by program base.
5032 32 bit PC relative offset to GOT.
5038 BFD_RELOC_390_PC12DBL
5040 PC relative 12 bit shifted by 1.
5042 BFD_RELOC_390_PLT12DBL
5044 12 bit PC rel. PLT shifted by 1.
5046 BFD_RELOC_390_PC16DBL
5048 PC relative 16 bit shifted by 1.
5050 BFD_RELOC_390_PLT16DBL
5052 16 bit PC rel. PLT shifted by 1.
5054 BFD_RELOC_390_PC24DBL
5056 PC relative 24 bit shifted by 1.
5058 BFD_RELOC_390_PLT24DBL
5060 24 bit PC rel. PLT shifted by 1.
5062 BFD_RELOC_390_PC32DBL
5064 PC relative 32 bit shifted by 1.
5066 BFD_RELOC_390_PLT32DBL
5068 32 bit PC rel. PLT shifted by 1.
5070 BFD_RELOC_390_GOTPCDBL
5072 32 bit PC rel. GOT shifted by 1.
5080 64 bit PC relative PLT address.
5082 BFD_RELOC_390_GOTENT
5084 32 bit rel. offset to GOT entry.
5086 BFD_RELOC_390_GOTOFF64
5088 64 bit offset to GOT.
5090 BFD_RELOC_390_GOTPLT12
5092 12-bit offset to symbol-entry within GOT, with PLT handling.
5094 BFD_RELOC_390_GOTPLT16
5096 16-bit offset to symbol-entry within GOT, with PLT handling.
5098 BFD_RELOC_390_GOTPLT32
5100 32-bit offset to symbol-entry within GOT, with PLT handling.
5102 BFD_RELOC_390_GOTPLT64
5104 64-bit offset to symbol-entry within GOT, with PLT handling.
5106 BFD_RELOC_390_GOTPLTENT
5108 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5110 BFD_RELOC_390_PLTOFF16
5112 16-bit rel. offset from the GOT to a PLT entry.
5114 BFD_RELOC_390_PLTOFF32
5116 32-bit rel. offset from the GOT to a PLT entry.
5118 BFD_RELOC_390_PLTOFF64
5120 64-bit rel. offset from the GOT to a PLT entry.
5123 BFD_RELOC_390_TLS_LOAD
5125 BFD_RELOC_390_TLS_GDCALL
5127 BFD_RELOC_390_TLS_LDCALL
5129 BFD_RELOC_390_TLS_GD32
5131 BFD_RELOC_390_TLS_GD64
5133 BFD_RELOC_390_TLS_GOTIE12
5135 BFD_RELOC_390_TLS_GOTIE32
5137 BFD_RELOC_390_TLS_GOTIE64
5139 BFD_RELOC_390_TLS_LDM32
5141 BFD_RELOC_390_TLS_LDM64
5143 BFD_RELOC_390_TLS_IE32
5145 BFD_RELOC_390_TLS_IE64
5147 BFD_RELOC_390_TLS_IEENT
5149 BFD_RELOC_390_TLS_LE32
5151 BFD_RELOC_390_TLS_LE64
5153 BFD_RELOC_390_TLS_LDO32
5155 BFD_RELOC_390_TLS_LDO64
5157 BFD_RELOC_390_TLS_DTPMOD
5159 BFD_RELOC_390_TLS_DTPOFF
5161 BFD_RELOC_390_TLS_TPOFF
5163 s390 tls relocations.
5170 BFD_RELOC_390_GOTPLT20
5172 BFD_RELOC_390_TLS_GOTIE20
5174 Long displacement extension.
5177 BFD_RELOC_390_IRELATIVE
5179 STT_GNU_IFUNC relocation.
5182 BFD_RELOC_SCORE_GPREL15
5185 Low 16 bit for load/store
5187 BFD_RELOC_SCORE_DUMMY2
5191 This is a 24-bit reloc with the right 1 bit assumed to be 0
5193 BFD_RELOC_SCORE_BRANCH
5195 This is a 19-bit reloc with the right 1 bit assumed to be 0
5197 BFD_RELOC_SCORE_IMM30
5199 This is a 32-bit reloc for 48-bit instructions.
5201 BFD_RELOC_SCORE_IMM32
5203 This is a 32-bit reloc for 48-bit instructions.
5205 BFD_RELOC_SCORE16_JMP
5207 This is a 11-bit reloc with the right 1 bit assumed to be 0
5209 BFD_RELOC_SCORE16_BRANCH
5211 This is a 8-bit reloc with the right 1 bit assumed to be 0
5213 BFD_RELOC_SCORE_BCMP
5215 This is a 9-bit reloc with the right 1 bit assumed to be 0
5217 BFD_RELOC_SCORE_GOT15
5219 BFD_RELOC_SCORE_GOT_LO16
5221 BFD_RELOC_SCORE_CALL15
5223 BFD_RELOC_SCORE_DUMMY_HI16
5225 Undocumented Score relocs
5230 Scenix IP2K - 9-bit register number / data address
5234 Scenix IP2K - 4-bit register/data bank number
5236 BFD_RELOC_IP2K_ADDR16CJP
5238 Scenix IP2K - low 13 bits of instruction word address
5240 BFD_RELOC_IP2K_PAGE3
5242 Scenix IP2K - high 3 bits of instruction word address
5244 BFD_RELOC_IP2K_LO8DATA
5246 BFD_RELOC_IP2K_HI8DATA
5248 BFD_RELOC_IP2K_EX8DATA
5250 Scenix IP2K - ext/low/high 8 bits of data address
5252 BFD_RELOC_IP2K_LO8INSN
5254 BFD_RELOC_IP2K_HI8INSN
5256 Scenix IP2K - low/high 8 bits of instruction word address
5258 BFD_RELOC_IP2K_PC_SKIP
5260 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5264 Scenix IP2K - 16 bit word address in text section.
5266 BFD_RELOC_IP2K_FR_OFFSET
5268 Scenix IP2K - 7-bit sp or dp offset
5270 BFD_RELOC_VPE4KMATH_DATA
5272 BFD_RELOC_VPE4KMATH_INSN
5274 Scenix VPE4K coprocessor - data/insn-space addressing
5277 BFD_RELOC_VTABLE_INHERIT
5279 BFD_RELOC_VTABLE_ENTRY
5281 These two relocations are used by the linker to determine which of
5282 the entries in a C++ virtual function table are actually used. When
5283 the --gc-sections option is given, the linker will zero out the entries
5284 that are not used, so that the code for those functions need not be
5285 included in the output.
5287 VTABLE_INHERIT is a zero-space relocation used to describe to the
5288 linker the inheritance tree of a C++ virtual function table. The
5289 relocation's symbol should be the parent class' vtable, and the
5290 relocation should be located at the child vtable.
5292 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5293 virtual function table entry. The reloc's symbol should refer to the
5294 table of the class mentioned in the code. Off of that base, an offset
5295 describes the entry that is being used. For Rela hosts, this offset
5296 is stored in the reloc's addend. For Rel hosts, we are forced to put
5297 this offset in the reloc's section offset.
5300 BFD_RELOC_IA64_IMM14
5302 BFD_RELOC_IA64_IMM22
5304 BFD_RELOC_IA64_IMM64
5306 BFD_RELOC_IA64_DIR32MSB
5308 BFD_RELOC_IA64_DIR32LSB
5310 BFD_RELOC_IA64_DIR64MSB
5312 BFD_RELOC_IA64_DIR64LSB
5314 BFD_RELOC_IA64_GPREL22
5316 BFD_RELOC_IA64_GPREL64I
5318 BFD_RELOC_IA64_GPREL32MSB
5320 BFD_RELOC_IA64_GPREL32LSB
5322 BFD_RELOC_IA64_GPREL64MSB
5324 BFD_RELOC_IA64_GPREL64LSB
5326 BFD_RELOC_IA64_LTOFF22
5328 BFD_RELOC_IA64_LTOFF64I
5330 BFD_RELOC_IA64_PLTOFF22
5332 BFD_RELOC_IA64_PLTOFF64I
5334 BFD_RELOC_IA64_PLTOFF64MSB
5336 BFD_RELOC_IA64_PLTOFF64LSB
5338 BFD_RELOC_IA64_FPTR64I
5340 BFD_RELOC_IA64_FPTR32MSB
5342 BFD_RELOC_IA64_FPTR32LSB
5344 BFD_RELOC_IA64_FPTR64MSB
5346 BFD_RELOC_IA64_FPTR64LSB
5348 BFD_RELOC_IA64_PCREL21B
5350 BFD_RELOC_IA64_PCREL21BI
5352 BFD_RELOC_IA64_PCREL21M
5354 BFD_RELOC_IA64_PCREL21F
5356 BFD_RELOC_IA64_PCREL22
5358 BFD_RELOC_IA64_PCREL60B
5360 BFD_RELOC_IA64_PCREL64I
5362 BFD_RELOC_IA64_PCREL32MSB
5364 BFD_RELOC_IA64_PCREL32LSB
5366 BFD_RELOC_IA64_PCREL64MSB
5368 BFD_RELOC_IA64_PCREL64LSB
5370 BFD_RELOC_IA64_LTOFF_FPTR22
5372 BFD_RELOC_IA64_LTOFF_FPTR64I
5374 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5376 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5378 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5380 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5382 BFD_RELOC_IA64_SEGREL32MSB
5384 BFD_RELOC_IA64_SEGREL32LSB
5386 BFD_RELOC_IA64_SEGREL64MSB
5388 BFD_RELOC_IA64_SEGREL64LSB
5390 BFD_RELOC_IA64_SECREL32MSB
5392 BFD_RELOC_IA64_SECREL32LSB
5394 BFD_RELOC_IA64_SECREL64MSB
5396 BFD_RELOC_IA64_SECREL64LSB
5398 BFD_RELOC_IA64_REL32MSB
5400 BFD_RELOC_IA64_REL32LSB
5402 BFD_RELOC_IA64_REL64MSB
5404 BFD_RELOC_IA64_REL64LSB
5406 BFD_RELOC_IA64_LTV32MSB
5408 BFD_RELOC_IA64_LTV32LSB
5410 BFD_RELOC_IA64_LTV64MSB
5412 BFD_RELOC_IA64_LTV64LSB
5414 BFD_RELOC_IA64_IPLTMSB
5416 BFD_RELOC_IA64_IPLTLSB
5420 BFD_RELOC_IA64_LTOFF22X
5422 BFD_RELOC_IA64_LDXMOV
5424 BFD_RELOC_IA64_TPREL14
5426 BFD_RELOC_IA64_TPREL22
5428 BFD_RELOC_IA64_TPREL64I
5430 BFD_RELOC_IA64_TPREL64MSB
5432 BFD_RELOC_IA64_TPREL64LSB
5434 BFD_RELOC_IA64_LTOFF_TPREL22
5436 BFD_RELOC_IA64_DTPMOD64MSB
5438 BFD_RELOC_IA64_DTPMOD64LSB
5440 BFD_RELOC_IA64_LTOFF_DTPMOD22
5442 BFD_RELOC_IA64_DTPREL14
5444 BFD_RELOC_IA64_DTPREL22
5446 BFD_RELOC_IA64_DTPREL64I
5448 BFD_RELOC_IA64_DTPREL32MSB
5450 BFD_RELOC_IA64_DTPREL32LSB
5452 BFD_RELOC_IA64_DTPREL64MSB
5454 BFD_RELOC_IA64_DTPREL64LSB
5456 BFD_RELOC_IA64_LTOFF_DTPREL22
5458 Intel IA64 Relocations.
5461 BFD_RELOC_M68HC11_HI8
5463 Motorola 68HC11 reloc.
5464 This is the 8 bit high part of an absolute address.
5466 BFD_RELOC_M68HC11_LO8
5468 Motorola 68HC11 reloc.
5469 This is the 8 bit low part of an absolute address.
5471 BFD_RELOC_M68HC11_3B
5473 Motorola 68HC11 reloc.
5474 This is the 3 bit of a value.
5476 BFD_RELOC_M68HC11_RL_JUMP
5478 Motorola 68HC11 reloc.
5479 This reloc marks the beginning of a jump/call instruction.
5480 It is used for linker relaxation to correctly identify beginning
5481 of instruction and change some branches to use PC-relative
5484 BFD_RELOC_M68HC11_RL_GROUP
5486 Motorola 68HC11 reloc.
5487 This reloc marks a group of several instructions that gcc generates
5488 and for which the linker relaxation pass can modify and/or remove
5491 BFD_RELOC_M68HC11_LO16
5493 Motorola 68HC11 reloc.
5494 This is the 16-bit lower part of an address. It is used for 'call'
5495 instruction to specify the symbol address without any special
5496 transformation (due to memory bank window).
5498 BFD_RELOC_M68HC11_PAGE
5500 Motorola 68HC11 reloc.
5501 This is a 8-bit reloc that specifies the page number of an address.
5502 It is used by 'call' instruction to specify the page number of
5505 BFD_RELOC_M68HC11_24
5507 Motorola 68HC11 reloc.
5508 This is a 24-bit reloc that represents the address with a 16-bit
5509 value and a 8-bit page number. The symbol address is transformed
5510 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5512 BFD_RELOC_M68HC12_5B
5514 Motorola 68HC12 reloc.
5515 This is the 5 bits of a value.
5517 BFD_RELOC_XGATE_RL_JUMP
5519 Freescale XGATE reloc.
5520 This reloc marks the beginning of a bra/jal instruction.
5522 BFD_RELOC_XGATE_RL_GROUP
5524 Freescale XGATE reloc.
5525 This reloc marks a group of several instructions that gcc generates
5526 and for which the linker relaxation pass can modify and/or remove
5529 BFD_RELOC_XGATE_LO16
5531 Freescale XGATE reloc.
5532 This is the 16-bit lower part of an address. It is used for the '16-bit'
5535 BFD_RELOC_XGATE_GPAGE
5537 Freescale XGATE reloc.
5541 Freescale XGATE reloc.
5543 BFD_RELOC_XGATE_PCREL_9
5545 Freescale XGATE reloc.
5546 This is a 9-bit pc-relative reloc.
5548 BFD_RELOC_XGATE_PCREL_10
5550 Freescale XGATE reloc.
5551 This is a 10-bit pc-relative reloc.
5553 BFD_RELOC_XGATE_IMM8_LO
5555 Freescale XGATE reloc.
5556 This is the 16-bit lower part of an address. It is used for the '16-bit'
5559 BFD_RELOC_XGATE_IMM8_HI
5561 Freescale XGATE reloc.
5562 This is the 16-bit higher part of an address. It is used for the '16-bit'
5565 BFD_RELOC_XGATE_IMM3
5567 Freescale XGATE reloc.
5568 This is a 3-bit pc-relative reloc.
5570 BFD_RELOC_XGATE_IMM4
5572 Freescale XGATE reloc.
5573 This is a 4-bit pc-relative reloc.
5575 BFD_RELOC_XGATE_IMM5
5577 Freescale XGATE reloc.
5578 This is a 5-bit pc-relative reloc.
5580 BFD_RELOC_M68HC12_9B
5582 Motorola 68HC12 reloc.
5583 This is the 9 bits of a value.
5585 BFD_RELOC_M68HC12_16B
5587 Motorola 68HC12 reloc.
5588 This is the 16 bits of a value.
5590 BFD_RELOC_M68HC12_9_PCREL
5592 Motorola 68HC12/XGATE reloc.
5593 This is a PCREL9 branch.
5595 BFD_RELOC_M68HC12_10_PCREL
5597 Motorola 68HC12/XGATE reloc.
5598 This is a PCREL10 branch.
5600 BFD_RELOC_M68HC12_LO8XG
5602 Motorola 68HC12/XGATE reloc.
5603 This is the 8 bit low part of an absolute address and immediately precedes
5604 a matching HI8XG part.
5606 BFD_RELOC_M68HC12_HI8XG
5608 Motorola 68HC12/XGATE reloc.
5609 This is the 8 bit high part of an absolute address and immediately follows
5610 a matching LO8XG part.
5614 BFD_RELOC_16C_NUM08_C
5618 BFD_RELOC_16C_NUM16_C
5622 BFD_RELOC_16C_NUM32_C
5624 BFD_RELOC_16C_DISP04
5626 BFD_RELOC_16C_DISP04_C
5628 BFD_RELOC_16C_DISP08
5630 BFD_RELOC_16C_DISP08_C
5632 BFD_RELOC_16C_DISP16
5634 BFD_RELOC_16C_DISP16_C
5636 BFD_RELOC_16C_DISP24
5638 BFD_RELOC_16C_DISP24_C
5640 BFD_RELOC_16C_DISP24a
5642 BFD_RELOC_16C_DISP24a_C
5646 BFD_RELOC_16C_REG04_C
5648 BFD_RELOC_16C_REG04a
5650 BFD_RELOC_16C_REG04a_C
5654 BFD_RELOC_16C_REG14_C
5658 BFD_RELOC_16C_REG16_C
5662 BFD_RELOC_16C_REG20_C
5666 BFD_RELOC_16C_ABS20_C
5670 BFD_RELOC_16C_ABS24_C
5674 BFD_RELOC_16C_IMM04_C
5678 BFD_RELOC_16C_IMM16_C
5682 BFD_RELOC_16C_IMM20_C
5686 BFD_RELOC_16C_IMM24_C
5690 BFD_RELOC_16C_IMM32_C
5692 NS CR16C Relocations.
5697 BFD_RELOC_CR16_NUM16
5699 BFD_RELOC_CR16_NUM32
5701 BFD_RELOC_CR16_NUM32a
5703 BFD_RELOC_CR16_REGREL0
5705 BFD_RELOC_CR16_REGREL4
5707 BFD_RELOC_CR16_REGREL4a
5709 BFD_RELOC_CR16_REGREL14
5711 BFD_RELOC_CR16_REGREL14a
5713 BFD_RELOC_CR16_REGREL16
5715 BFD_RELOC_CR16_REGREL20
5717 BFD_RELOC_CR16_REGREL20a
5719 BFD_RELOC_CR16_ABS20
5721 BFD_RELOC_CR16_ABS24
5727 BFD_RELOC_CR16_IMM16
5729 BFD_RELOC_CR16_IMM20
5731 BFD_RELOC_CR16_IMM24
5733 BFD_RELOC_CR16_IMM32
5735 BFD_RELOC_CR16_IMM32a
5737 BFD_RELOC_CR16_DISP4
5739 BFD_RELOC_CR16_DISP8
5741 BFD_RELOC_CR16_DISP16
5743 BFD_RELOC_CR16_DISP20
5745 BFD_RELOC_CR16_DISP24
5747 BFD_RELOC_CR16_DISP24a
5749 BFD_RELOC_CR16_SWITCH8
5751 BFD_RELOC_CR16_SWITCH16
5753 BFD_RELOC_CR16_SWITCH32
5755 BFD_RELOC_CR16_GOT_REGREL20
5757 BFD_RELOC_CR16_GOTC_REGREL20
5759 BFD_RELOC_CR16_GLOB_DAT
5761 NS CR16 Relocations.
5768 BFD_RELOC_CRX_REL8_CMP
5776 BFD_RELOC_CRX_REGREL12
5778 BFD_RELOC_CRX_REGREL22
5780 BFD_RELOC_CRX_REGREL28
5782 BFD_RELOC_CRX_REGREL32
5798 BFD_RELOC_CRX_SWITCH8
5800 BFD_RELOC_CRX_SWITCH16
5802 BFD_RELOC_CRX_SWITCH32
5807 BFD_RELOC_CRIS_BDISP8
5809 BFD_RELOC_CRIS_UNSIGNED_5
5811 BFD_RELOC_CRIS_SIGNED_6
5813 BFD_RELOC_CRIS_UNSIGNED_6
5815 BFD_RELOC_CRIS_SIGNED_8
5817 BFD_RELOC_CRIS_UNSIGNED_8
5819 BFD_RELOC_CRIS_SIGNED_16
5821 BFD_RELOC_CRIS_UNSIGNED_16
5823 BFD_RELOC_CRIS_LAPCQ_OFFSET
5825 BFD_RELOC_CRIS_UNSIGNED_4
5827 These relocs are only used within the CRIS assembler. They are not
5828 (at present) written to any object files.
5832 BFD_RELOC_CRIS_GLOB_DAT
5834 BFD_RELOC_CRIS_JUMP_SLOT
5836 BFD_RELOC_CRIS_RELATIVE
5838 Relocs used in ELF shared libraries for CRIS.
5840 BFD_RELOC_CRIS_32_GOT
5842 32-bit offset to symbol-entry within GOT.
5844 BFD_RELOC_CRIS_16_GOT
5846 16-bit offset to symbol-entry within GOT.
5848 BFD_RELOC_CRIS_32_GOTPLT
5850 32-bit offset to symbol-entry within GOT, with PLT handling.
5852 BFD_RELOC_CRIS_16_GOTPLT
5854 16-bit offset to symbol-entry within GOT, with PLT handling.
5856 BFD_RELOC_CRIS_32_GOTREL
5858 32-bit offset to symbol, relative to GOT.
5860 BFD_RELOC_CRIS_32_PLT_GOTREL
5862 32-bit offset to symbol with PLT entry, relative to GOT.
5864 BFD_RELOC_CRIS_32_PLT_PCREL
5866 32-bit offset to symbol with PLT entry, relative to this relocation.
5869 BFD_RELOC_CRIS_32_GOT_GD
5871 BFD_RELOC_CRIS_16_GOT_GD
5873 BFD_RELOC_CRIS_32_GD
5877 BFD_RELOC_CRIS_32_DTPREL
5879 BFD_RELOC_CRIS_16_DTPREL
5881 BFD_RELOC_CRIS_32_GOT_TPREL
5883 BFD_RELOC_CRIS_16_GOT_TPREL
5885 BFD_RELOC_CRIS_32_TPREL
5887 BFD_RELOC_CRIS_16_TPREL
5889 BFD_RELOC_CRIS_DTPMOD
5891 BFD_RELOC_CRIS_32_IE
5893 Relocs used in TLS code for CRIS.
5898 BFD_RELOC_860_GLOB_DAT
5900 BFD_RELOC_860_JUMP_SLOT
5902 BFD_RELOC_860_RELATIVE
5912 BFD_RELOC_860_SPLIT0
5916 BFD_RELOC_860_SPLIT1
5920 BFD_RELOC_860_SPLIT2
5924 BFD_RELOC_860_LOGOT0
5926 BFD_RELOC_860_SPGOT0
5928 BFD_RELOC_860_LOGOT1
5930 BFD_RELOC_860_SPGOT1
5932 BFD_RELOC_860_LOGOTOFF0
5934 BFD_RELOC_860_SPGOTOFF0
5936 BFD_RELOC_860_LOGOTOFF1
5938 BFD_RELOC_860_SPGOTOFF1
5940 BFD_RELOC_860_LOGOTOFF2
5942 BFD_RELOC_860_LOGOTOFF3
5946 BFD_RELOC_860_HIGHADJ
5950 BFD_RELOC_860_HAGOTOFF
5958 BFD_RELOC_860_HIGOTOFF
5960 Intel i860 Relocations.
5963 BFD_RELOC_OR1K_REL_26
5965 BFD_RELOC_OR1K_GOTPC_HI16
5967 BFD_RELOC_OR1K_GOTPC_LO16
5969 BFD_RELOC_OR1K_GOT16
5971 BFD_RELOC_OR1K_PLT26
5973 BFD_RELOC_OR1K_GOTOFF_HI16
5975 BFD_RELOC_OR1K_GOTOFF_LO16
5979 BFD_RELOC_OR1K_GLOB_DAT
5981 BFD_RELOC_OR1K_JMP_SLOT
5983 BFD_RELOC_OR1K_RELATIVE
5985 BFD_RELOC_OR1K_TLS_GD_HI16
5987 BFD_RELOC_OR1K_TLS_GD_LO16
5989 BFD_RELOC_OR1K_TLS_LDM_HI16
5991 BFD_RELOC_OR1K_TLS_LDM_LO16
5993 BFD_RELOC_OR1K_TLS_LDO_HI16
5995 BFD_RELOC_OR1K_TLS_LDO_LO16
5997 BFD_RELOC_OR1K_TLS_IE_HI16
5999 BFD_RELOC_OR1K_TLS_IE_LO16
6001 BFD_RELOC_OR1K_TLS_LE_HI16
6003 BFD_RELOC_OR1K_TLS_LE_LO16
6005 BFD_RELOC_OR1K_TLS_TPOFF
6007 BFD_RELOC_OR1K_TLS_DTPOFF
6009 BFD_RELOC_OR1K_TLS_DTPMOD
6011 OpenRISC 1000 Relocations.
6014 BFD_RELOC_H8_DIR16A8
6016 BFD_RELOC_H8_DIR16R8
6018 BFD_RELOC_H8_DIR24A8
6020 BFD_RELOC_H8_DIR24R8
6022 BFD_RELOC_H8_DIR32A16
6024 BFD_RELOC_H8_DISP32A16
6029 BFD_RELOC_XSTORMY16_REL_12
6031 BFD_RELOC_XSTORMY16_12
6033 BFD_RELOC_XSTORMY16_24
6035 BFD_RELOC_XSTORMY16_FPTR16
6037 Sony Xstormy16 Relocations.
6042 Self-describing complex relocations.
6054 Infineon Relocations.
6057 BFD_RELOC_VAX_GLOB_DAT
6059 BFD_RELOC_VAX_JMP_SLOT
6061 BFD_RELOC_VAX_RELATIVE
6063 Relocations used by VAX ELF.
6068 Morpho MT - 16 bit immediate relocation.
6072 Morpho MT - Hi 16 bits of an address.
6076 Morpho MT - Low 16 bits of an address.
6078 BFD_RELOC_MT_GNU_VTINHERIT
6080 Morpho MT - Used to tell the linker which vtable entries are used.
6082 BFD_RELOC_MT_GNU_VTENTRY
6084 Morpho MT - Used to tell the linker which vtable entries are used.
6086 BFD_RELOC_MT_PCINSN8
6088 Morpho MT - 8 bit immediate relocation.
6091 BFD_RELOC_MSP430_10_PCREL
6093 BFD_RELOC_MSP430_16_PCREL
6097 BFD_RELOC_MSP430_16_PCREL_BYTE
6099 BFD_RELOC_MSP430_16_BYTE
6101 BFD_RELOC_MSP430_2X_PCREL
6103 BFD_RELOC_MSP430_RL_PCREL
6105 BFD_RELOC_MSP430_ABS8
6107 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6109 BFD_RELOC_MSP430X_PCR20_EXT_DST
6111 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6113 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6115 BFD_RELOC_MSP430X_ABS20_EXT_DST
6117 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6119 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6121 BFD_RELOC_MSP430X_ABS20_ADR_DST
6123 BFD_RELOC_MSP430X_PCR16
6125 BFD_RELOC_MSP430X_PCR20_CALL
6127 BFD_RELOC_MSP430X_ABS16
6129 BFD_RELOC_MSP430_ABS_HI16
6131 BFD_RELOC_MSP430_PREL31
6133 BFD_RELOC_MSP430_SYM_DIFF
6135 msp430 specific relocation codes
6142 BFD_RELOC_NIOS2_CALL26
6144 BFD_RELOC_NIOS2_IMM5
6146 BFD_RELOC_NIOS2_CACHE_OPX
6148 BFD_RELOC_NIOS2_IMM6
6150 BFD_RELOC_NIOS2_IMM8
6152 BFD_RELOC_NIOS2_HI16
6154 BFD_RELOC_NIOS2_LO16
6156 BFD_RELOC_NIOS2_HIADJ16
6158 BFD_RELOC_NIOS2_GPREL
6160 BFD_RELOC_NIOS2_UJMP
6162 BFD_RELOC_NIOS2_CJMP
6164 BFD_RELOC_NIOS2_CALLR
6166 BFD_RELOC_NIOS2_ALIGN
6168 BFD_RELOC_NIOS2_GOT16
6170 BFD_RELOC_NIOS2_CALL16
6172 BFD_RELOC_NIOS2_GOTOFF_LO
6174 BFD_RELOC_NIOS2_GOTOFF_HA
6176 BFD_RELOC_NIOS2_PCREL_LO
6178 BFD_RELOC_NIOS2_PCREL_HA
6180 BFD_RELOC_NIOS2_TLS_GD16
6182 BFD_RELOC_NIOS2_TLS_LDM16
6184 BFD_RELOC_NIOS2_TLS_LDO16
6186 BFD_RELOC_NIOS2_TLS_IE16
6188 BFD_RELOC_NIOS2_TLS_LE16
6190 BFD_RELOC_NIOS2_TLS_DTPMOD
6192 BFD_RELOC_NIOS2_TLS_DTPREL
6194 BFD_RELOC_NIOS2_TLS_TPREL
6196 BFD_RELOC_NIOS2_COPY
6198 BFD_RELOC_NIOS2_GLOB_DAT
6200 BFD_RELOC_NIOS2_JUMP_SLOT
6202 BFD_RELOC_NIOS2_RELATIVE
6204 BFD_RELOC_NIOS2_GOTOFF
6206 BFD_RELOC_NIOS2_CALL26_NOAT
6208 BFD_RELOC_NIOS2_GOT_LO
6210 BFD_RELOC_NIOS2_GOT_HA
6212 BFD_RELOC_NIOS2_CALL_LO
6214 BFD_RELOC_NIOS2_CALL_HA
6216 Relocations used by the Altera Nios II core.
6219 BFD_RELOC_IQ2000_OFFSET_16
6221 BFD_RELOC_IQ2000_OFFSET_21
6223 BFD_RELOC_IQ2000_UHI16
6228 BFD_RELOC_XTENSA_RTLD
6230 Special Xtensa relocation used only by PLT entries in ELF shared
6231 objects to indicate that the runtime linker should set the value
6232 to one of its own internal functions or data structures.
6234 BFD_RELOC_XTENSA_GLOB_DAT
6236 BFD_RELOC_XTENSA_JMP_SLOT
6238 BFD_RELOC_XTENSA_RELATIVE
6240 Xtensa relocations for ELF shared objects.
6242 BFD_RELOC_XTENSA_PLT
6244 Xtensa relocation used in ELF object files for symbols that may require
6245 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6247 BFD_RELOC_XTENSA_DIFF8
6249 BFD_RELOC_XTENSA_DIFF16
6251 BFD_RELOC_XTENSA_DIFF32
6253 Xtensa relocations to mark the difference of two local symbols.
6254 These are only needed to support linker relaxation and can be ignored
6255 when not relaxing. The field is set to the value of the difference
6256 assuming no relaxation. The relocation encodes the position of the
6257 first symbol so the linker can determine whether to adjust the field
6260 BFD_RELOC_XTENSA_SLOT0_OP
6262 BFD_RELOC_XTENSA_SLOT1_OP
6264 BFD_RELOC_XTENSA_SLOT2_OP
6266 BFD_RELOC_XTENSA_SLOT3_OP
6268 BFD_RELOC_XTENSA_SLOT4_OP
6270 BFD_RELOC_XTENSA_SLOT5_OP
6272 BFD_RELOC_XTENSA_SLOT6_OP
6274 BFD_RELOC_XTENSA_SLOT7_OP
6276 BFD_RELOC_XTENSA_SLOT8_OP
6278 BFD_RELOC_XTENSA_SLOT9_OP
6280 BFD_RELOC_XTENSA_SLOT10_OP
6282 BFD_RELOC_XTENSA_SLOT11_OP
6284 BFD_RELOC_XTENSA_SLOT12_OP
6286 BFD_RELOC_XTENSA_SLOT13_OP
6288 BFD_RELOC_XTENSA_SLOT14_OP
6290 Generic Xtensa relocations for instruction operands. Only the slot
6291 number is encoded in the relocation. The relocation applies to the
6292 last PC-relative immediate operand, or if there are no PC-relative
6293 immediates, to the last immediate operand.
6295 BFD_RELOC_XTENSA_SLOT0_ALT
6297 BFD_RELOC_XTENSA_SLOT1_ALT
6299 BFD_RELOC_XTENSA_SLOT2_ALT
6301 BFD_RELOC_XTENSA_SLOT3_ALT
6303 BFD_RELOC_XTENSA_SLOT4_ALT
6305 BFD_RELOC_XTENSA_SLOT5_ALT
6307 BFD_RELOC_XTENSA_SLOT6_ALT
6309 BFD_RELOC_XTENSA_SLOT7_ALT
6311 BFD_RELOC_XTENSA_SLOT8_ALT
6313 BFD_RELOC_XTENSA_SLOT9_ALT
6315 BFD_RELOC_XTENSA_SLOT10_ALT
6317 BFD_RELOC_XTENSA_SLOT11_ALT
6319 BFD_RELOC_XTENSA_SLOT12_ALT
6321 BFD_RELOC_XTENSA_SLOT13_ALT
6323 BFD_RELOC_XTENSA_SLOT14_ALT
6325 Alternate Xtensa relocations. Only the slot is encoded in the
6326 relocation. The meaning of these relocations is opcode-specific.
6328 BFD_RELOC_XTENSA_OP0
6330 BFD_RELOC_XTENSA_OP1
6332 BFD_RELOC_XTENSA_OP2
6334 Xtensa relocations for backward compatibility. These have all been
6335 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6337 BFD_RELOC_XTENSA_ASM_EXPAND
6339 Xtensa relocation to mark that the assembler expanded the
6340 instructions from an original target. The expansion size is
6341 encoded in the reloc size.
6343 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6345 Xtensa relocation to mark that the linker should simplify
6346 assembler-expanded instructions. This is commonly used
6347 internally by the linker after analysis of a
6348 BFD_RELOC_XTENSA_ASM_EXPAND.
6350 BFD_RELOC_XTENSA_TLSDESC_FN
6352 BFD_RELOC_XTENSA_TLSDESC_ARG
6354 BFD_RELOC_XTENSA_TLS_DTPOFF
6356 BFD_RELOC_XTENSA_TLS_TPOFF
6358 BFD_RELOC_XTENSA_TLS_FUNC
6360 BFD_RELOC_XTENSA_TLS_ARG
6362 BFD_RELOC_XTENSA_TLS_CALL
6364 Xtensa TLS relocations.
6369 8 bit signed offset in (ix+d) or (iy+d).
6387 BFD_RELOC_LM32_BRANCH
6389 BFD_RELOC_LM32_16_GOT
6391 BFD_RELOC_LM32_GOTOFF_HI16
6393 BFD_RELOC_LM32_GOTOFF_LO16
6397 BFD_RELOC_LM32_GLOB_DAT
6399 BFD_RELOC_LM32_JMP_SLOT
6401 BFD_RELOC_LM32_RELATIVE
6403 Lattice Mico32 relocations.
6406 BFD_RELOC_MACH_O_SECTDIFF
6408 Difference between two section addreses. Must be followed by a
6409 BFD_RELOC_MACH_O_PAIR.
6411 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6413 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6415 BFD_RELOC_MACH_O_PAIR
6417 Pair of relocation. Contains the first symbol.
6420 BFD_RELOC_MACH_O_X86_64_BRANCH32
6422 BFD_RELOC_MACH_O_X86_64_BRANCH8
6424 PCREL relocations. They are marked as branch to create PLT entry if
6427 BFD_RELOC_MACH_O_X86_64_GOT
6429 Used when referencing a GOT entry.
6431 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6433 Used when loading a GOT entry with movq. It is specially marked so that
6434 the linker could optimize the movq to a leaq if possible.
6436 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
6438 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6440 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
6442 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6444 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6446 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6448 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6450 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6452 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6454 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6457 BFD_RELOC_MICROBLAZE_32_LO
6459 This is a 32 bit reloc for the microblaze that stores the
6460 low 16 bits of a value
6462 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6464 This is a 32 bit pc-relative reloc for the microblaze that
6465 stores the low 16 bits of a value
6467 BFD_RELOC_MICROBLAZE_32_ROSDA
6469 This is a 32 bit reloc for the microblaze that stores a
6470 value relative to the read-only small data area anchor
6472 BFD_RELOC_MICROBLAZE_32_RWSDA
6474 This is a 32 bit reloc for the microblaze that stores a
6475 value relative to the read-write small data area anchor
6477 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6479 This is a 32 bit reloc for the microblaze to handle
6480 expressions of the form "Symbol Op Symbol"
6482 BFD_RELOC_MICROBLAZE_64_NONE
6484 This is a 64 bit reloc that stores the 32 bit pc relative
6485 value in two words (with an imm instruction). No relocation is
6486 done here - only used for relaxing
6488 BFD_RELOC_MICROBLAZE_64_GOTPC
6490 This is a 64 bit reloc that stores the 32 bit pc relative
6491 value in two words (with an imm instruction). The relocation is
6492 PC-relative GOT offset
6494 BFD_RELOC_MICROBLAZE_64_GOT
6496 This is a 64 bit reloc that stores the 32 bit pc relative
6497 value in two words (with an imm instruction). The relocation is
6500 BFD_RELOC_MICROBLAZE_64_PLT
6502 This is a 64 bit reloc that stores the 32 bit pc relative
6503 value in two words (with an imm instruction). The relocation is
6504 PC-relative offset into PLT
6506 BFD_RELOC_MICROBLAZE_64_GOTOFF
6508 This is a 64 bit reloc that stores the 32 bit GOT relative
6509 value in two words (with an imm instruction). The relocation is
6510 relative offset from _GLOBAL_OFFSET_TABLE_
6512 BFD_RELOC_MICROBLAZE_32_GOTOFF
6514 This is a 32 bit reloc that stores the 32 bit GOT relative
6515 value in a word. The relocation is relative offset from
6516 _GLOBAL_OFFSET_TABLE_
6518 BFD_RELOC_MICROBLAZE_COPY
6520 This is used to tell the dynamic linker to copy the value out of
6521 the dynamic object into the runtime process image.
6523 BFD_RELOC_MICROBLAZE_64_TLS
6527 BFD_RELOC_MICROBLAZE_64_TLSGD
6529 This is a 64 bit reloc that stores the 32 bit GOT relative value
6530 of the GOT TLS GD info entry in two words (with an imm instruction). The
6531 relocation is GOT offset.
6533 BFD_RELOC_MICROBLAZE_64_TLSLD
6535 This is a 64 bit reloc that stores the 32 bit GOT relative value
6536 of the GOT TLS LD info entry in two words (with an imm instruction). The
6537 relocation is GOT offset.
6539 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6541 This is a 32 bit reloc that stores the Module ID to GOT(n).
6543 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6545 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6547 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6549 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6552 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6554 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6555 to two words (uses imm instruction).
6557 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6559 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6560 to two words (uses imm instruction).
6563 BFD_RELOC_AARCH64_RELOC_START
6565 AArch64 pseudo relocation code to mark the start of the AArch64
6566 relocation enumerators. N.B. the order of the enumerators is
6567 important as several tables in the AArch64 bfd backend are indexed
6568 by these enumerators; make sure they are all synced.
6570 BFD_RELOC_AARCH64_NONE
6572 AArch64 null relocation code.
6574 BFD_RELOC_AARCH64_64
6576 BFD_RELOC_AARCH64_32
6578 BFD_RELOC_AARCH64_16
6580 Basic absolute relocations of N bits. These are equivalent to
6581 BFD_RELOC_N and they were added to assist the indexing of the howto
6584 BFD_RELOC_AARCH64_64_PCREL
6586 BFD_RELOC_AARCH64_32_PCREL
6588 BFD_RELOC_AARCH64_16_PCREL
6590 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6591 and they were added to assist the indexing of the howto table.
6593 BFD_RELOC_AARCH64_MOVW_G0
6595 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6596 of an unsigned address/value.
6598 BFD_RELOC_AARCH64_MOVW_G0_NC
6600 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6601 an address/value. No overflow checking.
6603 BFD_RELOC_AARCH64_MOVW_G1
6605 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6606 of an unsigned address/value.
6608 BFD_RELOC_AARCH64_MOVW_G1_NC
6610 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6611 of an address/value. No overflow checking.
6613 BFD_RELOC_AARCH64_MOVW_G2
6615 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6616 of an unsigned address/value.
6618 BFD_RELOC_AARCH64_MOVW_G2_NC
6620 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6621 of an address/value. No overflow checking.
6623 BFD_RELOC_AARCH64_MOVW_G3
6625 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6626 of a signed or unsigned address/value.
6628 BFD_RELOC_AARCH64_MOVW_G0_S
6630 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6631 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6634 BFD_RELOC_AARCH64_MOVW_G1_S
6636 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6637 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6640 BFD_RELOC_AARCH64_MOVW_G2_S
6642 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6643 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6646 BFD_RELOC_AARCH64_LD_LO19_PCREL
6648 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6649 offset. The lowest two bits must be zero and are not stored in the
6650 instruction, giving a 21 bit signed byte offset.
6652 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6654 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6656 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6658 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6659 offset, giving a 4KB aligned page base address.
6661 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6663 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6664 offset, giving a 4KB aligned page base address, but with no overflow
6667 BFD_RELOC_AARCH64_ADD_LO12
6669 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6670 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6672 BFD_RELOC_AARCH64_LDST8_LO12
6674 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6675 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6677 BFD_RELOC_AARCH64_TSTBR14
6679 AArch64 14 bit pc-relative test bit and branch.
6680 The lowest two bits must be zero and are not stored in the instruction,
6681 giving a 16 bit signed byte offset.
6683 BFD_RELOC_AARCH64_BRANCH19
6685 AArch64 19 bit pc-relative conditional branch and compare & branch.
6686 The lowest two bits must be zero and are not stored in the instruction,
6687 giving a 21 bit signed byte offset.
6689 BFD_RELOC_AARCH64_JUMP26
6691 AArch64 26 bit pc-relative unconditional branch.
6692 The lowest two bits must be zero and are not stored in the instruction,
6693 giving a 28 bit signed byte offset.
6695 BFD_RELOC_AARCH64_CALL26
6697 AArch64 26 bit pc-relative unconditional branch and link.
6698 The lowest two bits must be zero and are not stored in the instruction,
6699 giving a 28 bit signed byte offset.
6701 BFD_RELOC_AARCH64_LDST16_LO12
6703 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6704 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6706 BFD_RELOC_AARCH64_LDST32_LO12
6708 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6709 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6711 BFD_RELOC_AARCH64_LDST64_LO12
6713 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6714 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6716 BFD_RELOC_AARCH64_LDST128_LO12
6718 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6719 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6721 BFD_RELOC_AARCH64_GOT_LD_PREL19
6723 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6724 offset of the global offset table entry for a symbol. The lowest two
6725 bits must be zero and are not stored in the instruction, giving a 21
6726 bit signed byte offset. This relocation type requires signed overflow
6729 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6731 Get to the page base of the global offset table entry for a symbol as
6732 part of an ADRP instruction using a 21 bit PC relative value.Used in
6733 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6735 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6737 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6738 the GOT entry for this symbol. Used in conjunction with
6739 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6741 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6743 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6744 the GOT entry for this symbol. Used in conjunction with
6745 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6747 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6749 Get to the page base of the global offset table entry for a symbols
6750 tls_index structure as part of an adrp instruction using a 21 bit PC
6751 relative value. Used in conjunction with
6752 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6754 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6756 Unsigned 12 bit byte offset to global offset table entry for a symbols
6757 tls_index structure. Used in conjunction with
6758 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6760 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6762 AArch64 TLS INITIAL EXEC relocation.
6764 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6766 AArch64 TLS INITIAL EXEC relocation.
6768 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6770 AArch64 TLS INITIAL EXEC relocation.
6772 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6774 AArch64 TLS INITIAL EXEC relocation.
6776 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6778 AArch64 TLS INITIAL EXEC relocation.
6780 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6782 AArch64 TLS INITIAL EXEC relocation.
6784 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6786 AArch64 TLS LOCAL EXEC relocation.
6788 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6790 AArch64 TLS LOCAL EXEC relocation.
6792 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6794 AArch64 TLS LOCAL EXEC relocation.
6796 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6798 AArch64 TLS LOCAL EXEC relocation.
6800 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6802 AArch64 TLS LOCAL EXEC relocation.
6804 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6806 AArch64 TLS LOCAL EXEC relocation.
6808 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6810 AArch64 TLS LOCAL EXEC relocation.
6812 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6814 AArch64 TLS LOCAL EXEC relocation.
6816 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
6818 AArch64 TLS DESC relocation.
6820 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6822 AArch64 TLS DESC relocation.
6824 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
6826 AArch64 TLS DESC relocation.
6828 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6830 AArch64 TLS DESC relocation.
6832 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6834 AArch64 TLS DESC relocation.
6836 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6838 AArch64 TLS DESC relocation.
6840 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6842 AArch64 TLS DESC relocation.
6844 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6846 AArch64 TLS DESC relocation.
6848 BFD_RELOC_AARCH64_TLSDESC_LDR
6850 AArch64 TLS DESC relocation.
6852 BFD_RELOC_AARCH64_TLSDESC_ADD
6854 AArch64 TLS DESC relocation.
6856 BFD_RELOC_AARCH64_TLSDESC_CALL
6858 AArch64 TLS DESC relocation.
6860 BFD_RELOC_AARCH64_COPY
6862 AArch64 TLS relocation.
6864 BFD_RELOC_AARCH64_GLOB_DAT
6866 AArch64 TLS relocation.
6868 BFD_RELOC_AARCH64_JUMP_SLOT
6870 AArch64 TLS relocation.
6872 BFD_RELOC_AARCH64_RELATIVE
6874 AArch64 TLS relocation.
6876 BFD_RELOC_AARCH64_TLS_DTPMOD
6878 AArch64 TLS relocation.
6880 BFD_RELOC_AARCH64_TLS_DTPREL
6882 AArch64 TLS relocation.
6884 BFD_RELOC_AARCH64_TLS_TPREL
6886 AArch64 TLS relocation.
6888 BFD_RELOC_AARCH64_TLSDESC
6890 AArch64 TLS relocation.
6892 BFD_RELOC_AARCH64_IRELATIVE
6894 AArch64 support for STT_GNU_IFUNC.
6896 BFD_RELOC_AARCH64_RELOC_END
6898 AArch64 pseudo relocation code to mark the end of the AArch64
6899 relocation enumerators that have direct mapping to ELF reloc codes.
6900 There are a few more enumerators after this one; those are mainly
6901 used by the AArch64 assembler for the internal fixup or to select
6902 one of the above enumerators.
6904 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6906 AArch64 pseudo relocation code to be used internally by the AArch64
6907 assembler and not (currently) written to any object files.
6909 BFD_RELOC_AARCH64_LDST_LO12
6911 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6912 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6914 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
6916 AArch64 pseudo relocation code to be used internally by the AArch64
6917 assembler and not (currently) written to any object files.
6919 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
6921 AArch64 pseudo relocation code to be used internally by the AArch64
6922 assembler and not (currently) written to any object files.
6924 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
6926 AArch64 pseudo relocation code to be used internally by the AArch64
6927 assembler and not (currently) written to any object files.
6930 BFD_RELOC_TILEPRO_COPY
6932 BFD_RELOC_TILEPRO_GLOB_DAT
6934 BFD_RELOC_TILEPRO_JMP_SLOT
6936 BFD_RELOC_TILEPRO_RELATIVE
6938 BFD_RELOC_TILEPRO_BROFF_X1
6940 BFD_RELOC_TILEPRO_JOFFLONG_X1
6942 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6944 BFD_RELOC_TILEPRO_IMM8_X0
6946 BFD_RELOC_TILEPRO_IMM8_Y0
6948 BFD_RELOC_TILEPRO_IMM8_X1
6950 BFD_RELOC_TILEPRO_IMM8_Y1
6952 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6954 BFD_RELOC_TILEPRO_MT_IMM15_X1
6956 BFD_RELOC_TILEPRO_MF_IMM15_X1
6958 BFD_RELOC_TILEPRO_IMM16_X0
6960 BFD_RELOC_TILEPRO_IMM16_X1
6962 BFD_RELOC_TILEPRO_IMM16_X0_LO
6964 BFD_RELOC_TILEPRO_IMM16_X1_LO
6966 BFD_RELOC_TILEPRO_IMM16_X0_HI
6968 BFD_RELOC_TILEPRO_IMM16_X1_HI
6970 BFD_RELOC_TILEPRO_IMM16_X0_HA
6972 BFD_RELOC_TILEPRO_IMM16_X1_HA
6974 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6976 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6978 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6980 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6982 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6984 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6986 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6988 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6990 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6992 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6994 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6996 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6998 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7000 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7002 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7004 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7006 BFD_RELOC_TILEPRO_MMSTART_X0
7008 BFD_RELOC_TILEPRO_MMEND_X0
7010 BFD_RELOC_TILEPRO_MMSTART_X1
7012 BFD_RELOC_TILEPRO_MMEND_X1
7014 BFD_RELOC_TILEPRO_SHAMT_X0
7016 BFD_RELOC_TILEPRO_SHAMT_X1
7018 BFD_RELOC_TILEPRO_SHAMT_Y0
7020 BFD_RELOC_TILEPRO_SHAMT_Y1
7022 BFD_RELOC_TILEPRO_TLS_GD_CALL
7024 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7026 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7028 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7030 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7032 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7034 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7036 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7038 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7040 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7042 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7044 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7046 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7048 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7050 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7052 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7054 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7056 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7058 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7060 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7062 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7064 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7066 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7068 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7070 BFD_RELOC_TILEPRO_TLS_TPOFF32
7072 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7074 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7076 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7078 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7080 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7082 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7084 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7086 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7088 Tilera TILEPro Relocations.
7090 BFD_RELOC_TILEGX_HW0
7092 BFD_RELOC_TILEGX_HW1
7094 BFD_RELOC_TILEGX_HW2
7096 BFD_RELOC_TILEGX_HW3
7098 BFD_RELOC_TILEGX_HW0_LAST
7100 BFD_RELOC_TILEGX_HW1_LAST
7102 BFD_RELOC_TILEGX_HW2_LAST
7104 BFD_RELOC_TILEGX_COPY
7106 BFD_RELOC_TILEGX_GLOB_DAT
7108 BFD_RELOC_TILEGX_JMP_SLOT
7110 BFD_RELOC_TILEGX_RELATIVE
7112 BFD_RELOC_TILEGX_BROFF_X1
7114 BFD_RELOC_TILEGX_JUMPOFF_X1
7116 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7118 BFD_RELOC_TILEGX_IMM8_X0
7120 BFD_RELOC_TILEGX_IMM8_Y0
7122 BFD_RELOC_TILEGX_IMM8_X1
7124 BFD_RELOC_TILEGX_IMM8_Y1
7126 BFD_RELOC_TILEGX_DEST_IMM8_X1
7128 BFD_RELOC_TILEGX_MT_IMM14_X1
7130 BFD_RELOC_TILEGX_MF_IMM14_X1
7132 BFD_RELOC_TILEGX_MMSTART_X0
7134 BFD_RELOC_TILEGX_MMEND_X0
7136 BFD_RELOC_TILEGX_SHAMT_X0
7138 BFD_RELOC_TILEGX_SHAMT_X1
7140 BFD_RELOC_TILEGX_SHAMT_Y0
7142 BFD_RELOC_TILEGX_SHAMT_Y1
7144 BFD_RELOC_TILEGX_IMM16_X0_HW0
7146 BFD_RELOC_TILEGX_IMM16_X1_HW0
7148 BFD_RELOC_TILEGX_IMM16_X0_HW1
7150 BFD_RELOC_TILEGX_IMM16_X1_HW1
7152 BFD_RELOC_TILEGX_IMM16_X0_HW2
7154 BFD_RELOC_TILEGX_IMM16_X1_HW2
7156 BFD_RELOC_TILEGX_IMM16_X0_HW3
7158 BFD_RELOC_TILEGX_IMM16_X1_HW3
7160 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7162 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7164 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7166 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7168 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7170 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7172 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7174 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7176 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7178 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7180 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7182 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7184 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7186 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7188 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7190 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7192 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7194 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7196 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7198 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7200 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7202 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7204 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7206 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7208 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7210 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7212 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7214 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7216 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7218 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7220 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7222 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7224 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7226 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7228 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7230 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7232 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7234 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7236 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7238 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7240 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7242 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7244 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7246 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7248 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7250 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7252 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7254 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7256 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7258 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7260 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7262 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7264 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7266 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7268 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7270 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7272 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7274 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7276 BFD_RELOC_TILEGX_TLS_DTPMOD64
7278 BFD_RELOC_TILEGX_TLS_DTPOFF64
7280 BFD_RELOC_TILEGX_TLS_TPOFF64
7282 BFD_RELOC_TILEGX_TLS_DTPMOD32
7284 BFD_RELOC_TILEGX_TLS_DTPOFF32
7286 BFD_RELOC_TILEGX_TLS_TPOFF32
7288 BFD_RELOC_TILEGX_TLS_GD_CALL
7290 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7292 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7294 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7296 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7298 BFD_RELOC_TILEGX_TLS_IE_LOAD
7300 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7302 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7304 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7306 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7308 Tilera TILE-Gx Relocations.
7311 BFD_RELOC_EPIPHANY_SIMM8
7313 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7315 BFD_RELOC_EPIPHANY_SIMM24
7317 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7319 BFD_RELOC_EPIPHANY_HIGH
7321 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7323 BFD_RELOC_EPIPHANY_LOW
7325 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7327 BFD_RELOC_EPIPHANY_SIMM11
7329 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7331 BFD_RELOC_EPIPHANY_IMM11
7333 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7335 BFD_RELOC_EPIPHANY_IMM8
7337 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7340 BFD_RELOC_VISIUM_HI16
7342 BFD_RELOC_VISIUM_LO16
7344 BFD_RELOC_VISIUM_IM16
7346 BFD_RELOC_VISIUM_REL16
7348 BFD_RELOC_VISIUM_HI16_PCREL
7350 BFD_RELOC_VISIUM_LO16_PCREL
7352 BFD_RELOC_VISIUM_IM16_PCREL
7360 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7365 bfd_reloc_type_lookup
7366 bfd_reloc_name_lookup
7369 reloc_howto_type *bfd_reloc_type_lookup
7370 (bfd *abfd, bfd_reloc_code_real_type code);
7371 reloc_howto_type *bfd_reloc_name_lookup
7372 (bfd *abfd, const char *reloc_name);
7375 Return a pointer to a howto structure which, when
7376 invoked, will perform the relocation @var{code} on data from the
7382 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7384 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7388 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7390 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7393 static reloc_howto_type bfd_howto_32
=
7394 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7398 bfd_default_reloc_type_lookup
7401 reloc_howto_type *bfd_default_reloc_type_lookup
7402 (bfd *abfd, bfd_reloc_code_real_type code);
7405 Provides a default relocation lookup routine for any architecture.
7410 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7414 case BFD_RELOC_CTOR
:
7415 /* The type of reloc used in a ctor, which will be as wide as the
7416 address - so either a 64, 32, or 16 bitter. */
7417 switch (bfd_arch_bits_per_address (abfd
))
7422 return &bfd_howto_32
;
7436 bfd_get_reloc_code_name
7439 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7442 Provides a printable name for the supplied relocation code.
7443 Useful mainly for printing error messages.
7447 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7449 if (code
> BFD_RELOC_UNUSED
)
7451 return bfd_reloc_code_real_names
[code
];
7456 bfd_generic_relax_section
7459 bfd_boolean bfd_generic_relax_section
7462 struct bfd_link_info *,
7466 Provides default handling for relaxing for back ends which
7471 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
7472 asection
*section ATTRIBUTE_UNUSED
,
7473 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
7476 if (link_info
->relocatable
)
7477 (*link_info
->callbacks
->einfo
)
7478 (_("%P%F: --relax and -r may not be used together\n"));
7486 bfd_generic_gc_sections
7489 bfd_boolean bfd_generic_gc_sections
7490 (bfd *, struct bfd_link_info *);
7493 Provides default handling for relaxing for back ends which
7494 don't do section gc -- i.e., does nothing.
7498 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7499 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
7506 bfd_generic_lookup_section_flags
7509 bfd_boolean bfd_generic_lookup_section_flags
7510 (struct bfd_link_info *, struct flag_info *, asection *);
7513 Provides default handling for section flags lookup
7514 -- i.e., does nothing.
7515 Returns FALSE if the section should be omitted, otherwise TRUE.
7519 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
7520 struct flag_info
*flaginfo
,
7521 asection
*section ATTRIBUTE_UNUSED
)
7523 if (flaginfo
!= NULL
)
7525 (*_bfd_error_handler
) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7533 bfd_generic_merge_sections
7536 bfd_boolean bfd_generic_merge_sections
7537 (bfd *, struct bfd_link_info *);
7540 Provides default handling for SEC_MERGE section merging for back ends
7541 which don't have SEC_MERGE support -- i.e., does nothing.
7545 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7546 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
7553 bfd_generic_get_relocated_section_contents
7556 bfd_byte *bfd_generic_get_relocated_section_contents
7558 struct bfd_link_info *link_info,
7559 struct bfd_link_order *link_order,
7561 bfd_boolean relocatable,
7565 Provides default handling of relocation effort for back ends
7566 which can't be bothered to do it efficiently.
7571 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
7572 struct bfd_link_info
*link_info
,
7573 struct bfd_link_order
*link_order
,
7575 bfd_boolean relocatable
,
7578 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
7579 asection
*input_section
= link_order
->u
.indirect
.section
;
7581 arelent
**reloc_vector
;
7584 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
7588 /* Read in the section. */
7589 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
7592 if (reloc_size
== 0)
7595 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
7596 if (reloc_vector
== NULL
)
7599 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
7603 if (reloc_count
< 0)
7606 if (reloc_count
> 0)
7609 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
7611 char *error_message
= NULL
;
7613 bfd_reloc_status_type r
;
7615 symbol
= *(*parent
)->sym_ptr_ptr
;
7616 if (symbol
->section
&& discarded_section (symbol
->section
))
7619 static reloc_howto_type none_howto
7620 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
7621 "unused", FALSE
, 0, 0, FALSE
);
7623 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
7624 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
7626 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
7627 (*parent
)->addend
= 0;
7628 (*parent
)->howto
= &none_howto
;
7632 r
= bfd_perform_relocation (input_bfd
,
7636 relocatable
? abfd
: NULL
,
7641 asection
*os
= input_section
->output_section
;
7643 /* A partial link, so keep the relocs. */
7644 os
->orelocation
[os
->reloc_count
] = *parent
;
7648 if (r
!= bfd_reloc_ok
)
7652 case bfd_reloc_undefined
:
7653 if (!((*link_info
->callbacks
->undefined_symbol
)
7654 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7655 input_bfd
, input_section
, (*parent
)->address
,
7659 case bfd_reloc_dangerous
:
7660 BFD_ASSERT (error_message
!= NULL
);
7661 if (!((*link_info
->callbacks
->reloc_dangerous
)
7662 (link_info
, error_message
, input_bfd
, input_section
,
7663 (*parent
)->address
)))
7666 case bfd_reloc_overflow
:
7667 if (!((*link_info
->callbacks
->reloc_overflow
)
7669 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7670 (*parent
)->howto
->name
, (*parent
)->addend
,
7671 input_bfd
, input_section
, (*parent
)->address
)))
7674 case bfd_reloc_outofrange
:
7676 This error can result when processing some partially
7677 complete binaries. Do not abort, but issue an error
7679 link_info
->callbacks
->einfo
7680 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7681 abfd
, input_section
, * parent
);
7684 case bfd_reloc_notsupported
:
7686 This error can result when processing a corrupt binary.
7687 Do not abort. Issue an error message instead. */
7688 link_info
->callbacks
->einfo
7689 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
7690 abfd
, input_section
, * parent
);
7702 free (reloc_vector
);
7706 free (reloc_vector
);