1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2021 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
58 typedef arelent, howto manager, Relocations, Relocations
63 This is the structure of a relocation entry:
67 .typedef enum bfd_reloc_status
69 . {* No errors detected. Note - the value 2 is used so that it
70 . will not be mistaken for the boolean TRUE or FALSE values. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok. If this type is
92 . returned, the error_message argument to bfd_perform_relocation
96 . bfd_reloc_status_type;
98 .typedef const struct reloc_howto_struct reloc_howto_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's idea of
288 . an external reloc number is stored in this field. *}
291 . {* The encoded size of the item to be relocated. This is *not* a
292 . power-of-two measure. Use bfd_get_reloc_size to find the size
293 . of the item in bytes. *}
294 . unsigned int size:3;
296 . {* The number of bits in the field to be relocated. This is used
297 . when doing overflow checking. *}
298 . unsigned int bitsize:7;
300 . {* The value the final relocation is shifted right by. This drops
301 . unwanted data from the relocation. *}
302 . unsigned int rightshift:6;
304 . {* The bit position of the reloc value in the destination.
305 . The relocated value is left shifted by this amount. *}
306 . unsigned int bitpos:6;
308 . {* What type of overflow error should be checked for when
310 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
312 . {* The relocation value should be negated before applying. *}
313 . unsigned int negate:1;
315 . {* The relocation is relative to the item being relocated. *}
316 . unsigned int pc_relative:1;
318 . {* Some formats record a relocation addend in the section contents
319 . rather than with the relocation. For ELF formats this is the
320 . distinction between USE_REL and USE_RELA (though the code checks
321 . for USE_REL == 1/0). The value of this field is TRUE if the
322 . addend is recorded with the section contents; when performing a
323 . partial link (ld -r) the section contents (the data) will be
324 . modified. The value of this field is FALSE if addends are
325 . recorded with the relocation (in arelent.addend); when performing
326 . a partial link the relocation will be modified.
327 . All relocations for all ELF USE_RELA targets should set this field
328 . to FALSE (values of TRUE should be looked on with suspicion).
329 . However, the converse is not true: not all relocations of all ELF
330 . USE_REL targets set this field to TRUE. Why this is so is peculiar
331 . to each particular target. For relocs that aren't used in partial
332 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
333 . unsigned int partial_inplace:1;
335 . {* When some formats create PC relative instructions, they leave
336 . the value of the pc of the place being relocated in the offset
337 . slot of the instruction, so that a PC relative relocation can
338 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
339 . Some formats leave the displacement part of an instruction
340 . empty (e.g., ELF); this flag signals the fact. *}
341 . unsigned int pcrel_offset:1;
343 . {* src_mask selects the part of the instruction (or data) to be used
344 . in the relocation sum. If the target relocations don't have an
345 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
346 . dst_mask to extract the addend from the section contents. If
347 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
348 . field should normally be zero. Non-zero values for ELF USE_RELA
349 . targets should be viewed with suspicion as normally the value in
350 . the dst_mask part of the section contents should be ignored. *}
353 . {* dst_mask selects which parts of the instruction (or data) are
354 . replaced with a relocated value. *}
357 . {* If this field is non null, then the supplied function is
358 . called rather than the normal function. This allows really
359 . strange relocation methods to be accommodated. *}
360 . bfd_reloc_status_type (*special_function)
361 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
364 . {* The textual name of the relocation type. *}
375 The HOWTO macro fills in a reloc_howto_type (a typedef for
376 const struct reloc_howto_struct).
378 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
379 . inplace, src_mask, dst_mask, pcrel_off) \
380 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
381 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
384 This is used to fill in an empty howto entry in an array.
386 .#define EMPTY_HOWTO(C) \
387 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
388 . NULL, FALSE, 0, 0, FALSE)
397 unsigned int bfd_get_reloc_size (reloc_howto_type *);
400 For a reloc_howto_type that operates on a fixed number of bytes,
401 this returns the number of bytes operated on.
405 bfd_get_reloc_size (reloc_howto_type
*howto
)
425 How relocs are tied together in an <<asection>>:
427 .typedef struct relent_chain
430 . struct relent_chain *next;
436 /* N_ONES produces N one bits, without undefined behaviour for N
437 between zero and the number of bits in a bfd_vma. */
438 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
445 bfd_reloc_status_type bfd_check_overflow
446 (enum complain_overflow how,
447 unsigned int bitsize,
448 unsigned int rightshift,
449 unsigned int addrsize,
453 Perform overflow checking on @var{relocation} which has
454 @var{bitsize} significant bits and will be shifted right by
455 @var{rightshift} bits, on a machine with addresses containing
456 @var{addrsize} significant bits. The result is either of
457 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
461 bfd_reloc_status_type
462 bfd_check_overflow (enum complain_overflow how
,
463 unsigned int bitsize
,
464 unsigned int rightshift
,
465 unsigned int addrsize
,
468 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
469 bfd_reloc_status_type flag
= bfd_reloc_ok
;
474 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
475 we'll be permissive: extra bits in the field mask will
476 automatically extend the address mask for purposes of the
478 fieldmask
= N_ONES (bitsize
);
479 signmask
= ~fieldmask
;
480 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
481 a
= (relocation
& addrmask
) >> rightshift
;
485 case complain_overflow_dont
:
488 case complain_overflow_signed
:
489 /* If any sign bits are set, all sign bits must be set. That
490 is, A must be a valid negative address after shifting. */
491 signmask
= ~ (fieldmask
>> 1);
494 case complain_overflow_bitfield
:
495 /* Bitfields are sometimes signed, sometimes unsigned. We
496 explicitly allow an address wrap too, which means a bitfield
497 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
498 if the value has some, but not all, bits set outside the
501 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
502 flag
= bfd_reloc_overflow
;
505 case complain_overflow_unsigned
:
506 /* We have an overflow if the address does not fit in the field. */
507 if ((a
& signmask
) != 0)
508 flag
= bfd_reloc_overflow
;
520 bfd_reloc_offset_in_range
523 bfd_boolean bfd_reloc_offset_in_range
524 (reloc_howto_type *howto,
527 bfd_size_type offset);
530 Returns TRUE if the reloc described by @var{HOWTO} can be
531 applied at @var{OFFSET} octets in @var{SECTION}.
535 /* HOWTO describes a relocation, at offset OCTET. Return whether the
536 relocation field is within SECTION of ABFD. */
539 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
544 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
545 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
547 /* The reloc field must be contained entirely within the section.
548 Allow zero length fields (marker relocs or NONE relocs where no
549 relocation will be performed) at the end of the section. */
550 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
553 /* Read and return the section contents at DATA converted to a host
554 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
557 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
562 return bfd_get_8 (abfd
, data
);
565 return bfd_get_16 (abfd
, data
);
568 return bfd_get_32 (abfd
, data
);
575 return bfd_get_64 (abfd
, data
);
579 return bfd_get_24 (abfd
, data
);
587 /* Convert VAL to target format and write to DATA. The number of
588 bytes written is given by the HOWTO. */
591 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
596 bfd_put_8 (abfd
, val
, data
);
600 bfd_put_16 (abfd
, val
, data
);
604 bfd_put_32 (abfd
, val
, data
);
612 bfd_put_64 (abfd
, val
, data
);
617 bfd_put_24 (abfd
, val
, data
);
625 /* Apply RELOCATION value to target bytes at DATA, according to
629 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
632 bfd_vma val
= read_reloc (abfd
, data
, howto
);
635 relocation
= -relocation
;
637 val
= ((val
& ~howto
->dst_mask
)
638 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
640 write_reloc (abfd
, val
, data
, howto
);
645 bfd_perform_relocation
648 bfd_reloc_status_type bfd_perform_relocation
650 arelent *reloc_entry,
652 asection *input_section,
654 char **error_message);
657 If @var{output_bfd} is supplied to this function, the
658 generated image will be relocatable; the relocations are
659 copied to the output file after they have been changed to
660 reflect the new state of the world. There are two ways of
661 reflecting the results of partial linkage in an output file:
662 by modifying the output data in place, and by modifying the
663 relocation record. Some native formats (e.g., basic a.out and
664 basic coff) have no way of specifying an addend in the
665 relocation type, so the addend has to go in the output data.
666 This is no big deal since in these formats the output data
667 slot will always be big enough for the addend. Complex reloc
668 types with addends were invented to solve just this problem.
669 The @var{error_message} argument is set to an error message if
670 this return @code{bfd_reloc_dangerous}.
674 bfd_reloc_status_type
675 bfd_perform_relocation (bfd
*abfd
,
676 arelent
*reloc_entry
,
678 asection
*input_section
,
680 char **error_message
)
683 bfd_reloc_status_type flag
= bfd_reloc_ok
;
684 bfd_size_type octets
;
685 bfd_vma output_base
= 0;
686 reloc_howto_type
*howto
= reloc_entry
->howto
;
687 asection
*reloc_target_output_section
;
690 symbol
= *(reloc_entry
->sym_ptr_ptr
);
692 /* If we are not producing relocatable output, return an error if
693 the symbol is not defined. An undefined weak symbol is
694 considered to have a value of zero (SVR4 ABI, p. 4-27). */
695 if (bfd_is_und_section (symbol
->section
)
696 && (symbol
->flags
& BSF_WEAK
) == 0
697 && output_bfd
== NULL
)
698 flag
= bfd_reloc_undefined
;
700 /* If there is a function supplied to handle this relocation type,
701 call it. It'll return `bfd_reloc_continue' if further processing
703 if (howto
&& howto
->special_function
)
705 bfd_reloc_status_type cont
;
707 /* Note - we do not call bfd_reloc_offset_in_range here as the
708 reloc_entry->address field might actually be valid for the
709 backend concerned. It is up to the special_function itself
710 to call bfd_reloc_offset_in_range if needed. */
711 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
712 input_section
, output_bfd
,
714 if (cont
!= bfd_reloc_continue
)
718 if (bfd_is_abs_section (symbol
->section
)
719 && output_bfd
!= NULL
)
721 reloc_entry
->address
+= input_section
->output_offset
;
725 /* PR 17512: file: 0f67f69d. */
727 return bfd_reloc_undefined
;
729 /* Is the address of the relocation really within the section? */
730 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
731 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
732 return bfd_reloc_outofrange
;
734 /* Work out which section the relocation is targeted at and the
735 initial relocation command value. */
737 /* Get symbol value. (Common symbols are special.) */
738 if (bfd_is_com_section (symbol
->section
))
741 relocation
= symbol
->value
;
743 reloc_target_output_section
= symbol
->section
->output_section
;
745 /* Convert input-section-relative symbol value to absolute. */
746 if ((output_bfd
&& ! howto
->partial_inplace
)
747 || reloc_target_output_section
== NULL
)
750 output_base
= reloc_target_output_section
->vma
;
752 output_base
+= symbol
->section
->output_offset
;
754 /* If symbol addresses are in octets, convert to bytes. */
755 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
756 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
757 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
759 relocation
+= output_base
;
761 /* Add in supplied addend. */
762 relocation
+= reloc_entry
->addend
;
764 /* Here the variable relocation holds the final address of the
765 symbol we are relocating against, plus any addend. */
767 if (howto
->pc_relative
)
769 /* This is a PC relative relocation. We want to set RELOCATION
770 to the distance between the address of the symbol and the
771 location. RELOCATION is already the address of the symbol.
773 We start by subtracting the address of the section containing
776 If pcrel_offset is set, we must further subtract the position
777 of the location within the section. Some targets arrange for
778 the addend to be the negative of the position of the location
779 within the section; for example, i386-aout does this. For
780 i386-aout, pcrel_offset is FALSE. Some other targets do not
781 include the position of the location; for example, ELF.
782 For those targets, pcrel_offset is TRUE.
784 If we are producing relocatable output, then we must ensure
785 that this reloc will be correctly computed when the final
786 relocation is done. If pcrel_offset is FALSE we want to wind
787 up with the negative of the location within the section,
788 which means we must adjust the existing addend by the change
789 in the location within the section. If pcrel_offset is TRUE
790 we do not want to adjust the existing addend at all.
792 FIXME: This seems logical to me, but for the case of
793 producing relocatable output it is not what the code
794 actually does. I don't want to change it, because it seems
795 far too likely that something will break. */
798 input_section
->output_section
->vma
+ input_section
->output_offset
;
800 if (howto
->pcrel_offset
)
801 relocation
-= reloc_entry
->address
;
804 if (output_bfd
!= NULL
)
806 if (! howto
->partial_inplace
)
808 /* This is a partial relocation, and we want to apply the relocation
809 to the reloc entry rather than the raw data. Modify the reloc
810 inplace to reflect what we now know. */
811 reloc_entry
->addend
= relocation
;
812 reloc_entry
->address
+= input_section
->output_offset
;
817 /* This is a partial relocation, but inplace, so modify the
820 If we've relocated with a symbol with a section, change
821 into a ref to the section belonging to the symbol. */
823 reloc_entry
->address
+= input_section
->output_offset
;
826 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
827 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
828 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
830 /* For m68k-coff, the addend was being subtracted twice during
831 relocation with -r. Removing the line below this comment
832 fixes that problem; see PR 2953.
834 However, Ian wrote the following, regarding removing the line below,
835 which explains why it is still enabled: --djm
837 If you put a patch like that into BFD you need to check all the COFF
838 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
839 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
840 problem in a different way. There may very well be a reason that the
841 code works as it does.
843 Hmmm. The first obvious point is that bfd_perform_relocation should
844 not have any tests that depend upon the flavour. It's seem like
845 entirely the wrong place for such a thing. The second obvious point
846 is that the current code ignores the reloc addend when producing
847 relocatable output for COFF. That's peculiar. In fact, I really
848 have no idea what the point of the line you want to remove is.
850 A typical COFF reloc subtracts the old value of the symbol and adds in
851 the new value to the location in the object file (if it's a pc
852 relative reloc it adds the difference between the symbol value and the
853 location). When relocating we need to preserve that property.
855 BFD handles this by setting the addend to the negative of the old
856 value of the symbol. Unfortunately it handles common symbols in a
857 non-standard way (it doesn't subtract the old value) but that's a
858 different story (we can't change it without losing backward
859 compatibility with old object files) (coff-i386 does subtract the old
860 value, to be compatible with existing coff-i386 targets, like SCO).
862 So everything works fine when not producing relocatable output. When
863 we are producing relocatable output, logically we should do exactly
864 what we do when not producing relocatable output. Therefore, your
865 patch is correct. In fact, it should probably always just set
866 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
867 add the value into the object file. This won't hurt the COFF code,
868 which doesn't use the addend; I'm not sure what it will do to other
869 formats (the thing to check for would be whether any formats both use
870 the addend and set partial_inplace).
872 When I wanted to make coff-i386 produce relocatable output, I ran
873 into the problem that you are running into: I wanted to remove that
874 line. Rather than risk it, I made the coff-i386 relocs use a special
875 function; it's coff_i386_reloc in coff-i386.c. The function
876 specifically adds the addend field into the object file, knowing that
877 bfd_perform_relocation is not going to. If you remove that line, then
878 coff-i386.c will wind up adding the addend field in twice. It's
879 trivial to fix; it just needs to be done.
881 The problem with removing the line is just that it may break some
882 working code. With BFD it's hard to be sure of anything. The right
883 way to deal with this is simply to build and test at least all the
884 supported COFF targets. It should be straightforward if time and disk
885 space consuming. For each target:
887 2) generate some executable, and link it using -r (I would
888 probably use paranoia.o and link against newlib/libc.a, which
889 for all the supported targets would be available in
890 /usr/cygnus/progressive/H-host/target/lib/libc.a).
891 3) make the change to reloc.c
892 4) rebuild the linker
894 6) if the resulting object files are the same, you have at least
896 7) if they are different you have to figure out which version is
899 relocation
-= reloc_entry
->addend
;
900 reloc_entry
->addend
= 0;
904 reloc_entry
->addend
= relocation
;
909 /* FIXME: This overflow checking is incomplete, because the value
910 might have overflowed before we get here. For a correct check we
911 need to compute the value in a size larger than bitsize, but we
912 can't reasonably do that for a reloc the same size as a host
914 FIXME: We should also do overflow checking on the result after
915 adding in the value contained in the object file. */
916 if (howto
->complain_on_overflow
!= complain_overflow_dont
917 && flag
== bfd_reloc_ok
)
918 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
921 bfd_arch_bits_per_address (abfd
),
924 /* Either we are relocating all the way, or we don't want to apply
925 the relocation to the reloc entry (probably because there isn't
926 any room in the output format to describe addends to relocs). */
928 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
929 (OSF version 1.3, compiler version 3.11). It miscompiles the
943 x <<= (unsigned long) s.i0;
947 printf ("succeeded (%lx)\n", x);
951 relocation
>>= (bfd_vma
) howto
->rightshift
;
953 /* Shift everything up to where it's going to be used. */
954 relocation
<<= (bfd_vma
) howto
->bitpos
;
956 /* Wait for the day when all have the mask in them. */
959 i instruction to be left alone
960 o offset within instruction
961 r relocation offset to apply
970 (( i i i i i o o o o o from bfd_get<size>
971 and S S S S S) to get the size offset we want
972 + r r r r r r r r r r) to get the final value to place
973 and D D D D D to chop to right size
974 -----------------------
977 ( i i i i i o o o o o from bfd_get<size>
978 and N N N N N ) get instruction
979 -----------------------
985 -----------------------
986 = R R R R R R R R R R put into bfd_put<size>
989 data
= (bfd_byte
*) data
+ octets
;
990 apply_reloc (abfd
, data
, howto
, relocation
);
996 bfd_install_relocation
999 bfd_reloc_status_type bfd_install_relocation
1001 arelent *reloc_entry,
1002 void *data, bfd_vma data_start,
1003 asection *input_section,
1004 char **error_message);
1007 This looks remarkably like <<bfd_perform_relocation>>, except it
1008 does not expect that the section contents have been filled in.
1009 I.e., it's suitable for use when creating, rather than applying
1012 For now, this function should be considered reserved for the
1016 bfd_reloc_status_type
1017 bfd_install_relocation (bfd
*abfd
,
1018 arelent
*reloc_entry
,
1020 bfd_vma data_start_offset
,
1021 asection
*input_section
,
1022 char **error_message
)
1025 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1026 bfd_size_type octets
;
1027 bfd_vma output_base
= 0;
1028 reloc_howto_type
*howto
= reloc_entry
->howto
;
1029 asection
*reloc_target_output_section
;
1033 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1035 /* If there is a function supplied to handle this relocation type,
1036 call it. It'll return `bfd_reloc_continue' if further processing
1038 if (howto
&& howto
->special_function
)
1040 bfd_reloc_status_type cont
;
1042 /* Note - we do not call bfd_reloc_offset_in_range here as the
1043 reloc_entry->address field might actually be valid for the
1044 backend concerned. It is up to the special_function itself
1045 to call bfd_reloc_offset_in_range if needed. */
1046 /* XXX - The special_function calls haven't been fixed up to deal
1047 with creating new relocations and section contents. */
1048 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1049 /* XXX - Non-portable! */
1050 ((bfd_byte
*) data_start
1051 - data_start_offset
),
1052 input_section
, abfd
, error_message
);
1053 if (cont
!= bfd_reloc_continue
)
1057 if (bfd_is_abs_section (symbol
->section
))
1059 reloc_entry
->address
+= input_section
->output_offset
;
1060 return bfd_reloc_ok
;
1063 /* No need to check for howto != NULL if !bfd_is_abs_section as
1064 it will have been checked in `bfd_perform_relocation already'. */
1066 /* Is the address of the relocation really within the section? */
1067 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1068 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1069 return bfd_reloc_outofrange
;
1071 /* Work out which section the relocation is targeted at and the
1072 initial relocation command value. */
1074 /* Get symbol value. (Common symbols are special.) */
1075 if (bfd_is_com_section (symbol
->section
))
1078 relocation
= symbol
->value
;
1080 reloc_target_output_section
= symbol
->section
->output_section
;
1082 /* Convert input-section-relative symbol value to absolute. */
1083 if (! howto
->partial_inplace
)
1086 output_base
= reloc_target_output_section
->vma
;
1088 output_base
+= symbol
->section
->output_offset
;
1090 /* If symbol addresses are in octets, convert to bytes. */
1091 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1092 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1093 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1095 relocation
+= output_base
;
1097 /* Add in supplied addend. */
1098 relocation
+= reloc_entry
->addend
;
1100 /* Here the variable relocation holds the final address of the
1101 symbol we are relocating against, plus any addend. */
1103 if (howto
->pc_relative
)
1105 /* This is a PC relative relocation. We want to set RELOCATION
1106 to the distance between the address of the symbol and the
1107 location. RELOCATION is already the address of the symbol.
1109 We start by subtracting the address of the section containing
1112 If pcrel_offset is set, we must further subtract the position
1113 of the location within the section. Some targets arrange for
1114 the addend to be the negative of the position of the location
1115 within the section; for example, i386-aout does this. For
1116 i386-aout, pcrel_offset is FALSE. Some other targets do not
1117 include the position of the location; for example, ELF.
1118 For those targets, pcrel_offset is TRUE.
1120 If we are producing relocatable output, then we must ensure
1121 that this reloc will be correctly computed when the final
1122 relocation is done. If pcrel_offset is FALSE we want to wind
1123 up with the negative of the location within the section,
1124 which means we must adjust the existing addend by the change
1125 in the location within the section. If pcrel_offset is TRUE
1126 we do not want to adjust the existing addend at all.
1128 FIXME: This seems logical to me, but for the case of
1129 producing relocatable output it is not what the code
1130 actually does. I don't want to change it, because it seems
1131 far too likely that something will break. */
1134 input_section
->output_section
->vma
+ input_section
->output_offset
;
1136 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1137 relocation
-= reloc_entry
->address
;
1140 if (! howto
->partial_inplace
)
1142 /* This is a partial relocation, and we want to apply the relocation
1143 to the reloc entry rather than the raw data. Modify the reloc
1144 inplace to reflect what we now know. */
1145 reloc_entry
->addend
= relocation
;
1146 reloc_entry
->address
+= input_section
->output_offset
;
1151 /* This is a partial relocation, but inplace, so modify the
1154 If we've relocated with a symbol with a section, change
1155 into a ref to the section belonging to the symbol. */
1156 reloc_entry
->address
+= input_section
->output_offset
;
1159 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1160 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1161 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1164 /* For m68k-coff, the addend was being subtracted twice during
1165 relocation with -r. Removing the line below this comment
1166 fixes that problem; see PR 2953.
1168 However, Ian wrote the following, regarding removing the line below,
1169 which explains why it is still enabled: --djm
1171 If you put a patch like that into BFD you need to check all the COFF
1172 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1173 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1174 problem in a different way. There may very well be a reason that the
1175 code works as it does.
1177 Hmmm. The first obvious point is that bfd_install_relocation should
1178 not have any tests that depend upon the flavour. It's seem like
1179 entirely the wrong place for such a thing. The second obvious point
1180 is that the current code ignores the reloc addend when producing
1181 relocatable output for COFF. That's peculiar. In fact, I really
1182 have no idea what the point of the line you want to remove is.
1184 A typical COFF reloc subtracts the old value of the symbol and adds in
1185 the new value to the location in the object file (if it's a pc
1186 relative reloc it adds the difference between the symbol value and the
1187 location). When relocating we need to preserve that property.
1189 BFD handles this by setting the addend to the negative of the old
1190 value of the symbol. Unfortunately it handles common symbols in a
1191 non-standard way (it doesn't subtract the old value) but that's a
1192 different story (we can't change it without losing backward
1193 compatibility with old object files) (coff-i386 does subtract the old
1194 value, to be compatible with existing coff-i386 targets, like SCO).
1196 So everything works fine when not producing relocatable output. When
1197 we are producing relocatable output, logically we should do exactly
1198 what we do when not producing relocatable output. Therefore, your
1199 patch is correct. In fact, it should probably always just set
1200 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1201 add the value into the object file. This won't hurt the COFF code,
1202 which doesn't use the addend; I'm not sure what it will do to other
1203 formats (the thing to check for would be whether any formats both use
1204 the addend and set partial_inplace).
1206 When I wanted to make coff-i386 produce relocatable output, I ran
1207 into the problem that you are running into: I wanted to remove that
1208 line. Rather than risk it, I made the coff-i386 relocs use a special
1209 function; it's coff_i386_reloc in coff-i386.c. The function
1210 specifically adds the addend field into the object file, knowing that
1211 bfd_install_relocation is not going to. If you remove that line, then
1212 coff-i386.c will wind up adding the addend field in twice. It's
1213 trivial to fix; it just needs to be done.
1215 The problem with removing the line is just that it may break some
1216 working code. With BFD it's hard to be sure of anything. The right
1217 way to deal with this is simply to build and test at least all the
1218 supported COFF targets. It should be straightforward if time and disk
1219 space consuming. For each target:
1221 2) generate some executable, and link it using -r (I would
1222 probably use paranoia.o and link against newlib/libc.a, which
1223 for all the supported targets would be available in
1224 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1225 3) make the change to reloc.c
1226 4) rebuild the linker
1228 6) if the resulting object files are the same, you have at least
1230 7) if they are different you have to figure out which version is
1232 relocation
-= reloc_entry
->addend
;
1233 /* FIXME: There should be no target specific code here... */
1234 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1235 reloc_entry
->addend
= 0;
1239 reloc_entry
->addend
= relocation
;
1243 /* FIXME: This overflow checking is incomplete, because the value
1244 might have overflowed before we get here. For a correct check we
1245 need to compute the value in a size larger than bitsize, but we
1246 can't reasonably do that for a reloc the same size as a host
1248 FIXME: We should also do overflow checking on the result after
1249 adding in the value contained in the object file. */
1250 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1251 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1254 bfd_arch_bits_per_address (abfd
),
1257 /* Either we are relocating all the way, or we don't want to apply
1258 the relocation to the reloc entry (probably because there isn't
1259 any room in the output format to describe addends to relocs). */
1261 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1262 (OSF version 1.3, compiler version 3.11). It miscompiles the
1276 x <<= (unsigned long) s.i0;
1278 printf ("failed\n");
1280 printf ("succeeded (%lx)\n", x);
1284 relocation
>>= (bfd_vma
) howto
->rightshift
;
1286 /* Shift everything up to where it's going to be used. */
1287 relocation
<<= (bfd_vma
) howto
->bitpos
;
1289 /* Wait for the day when all have the mask in them. */
1292 i instruction to be left alone
1293 o offset within instruction
1294 r relocation offset to apply
1303 (( i i i i i o o o o o from bfd_get<size>
1304 and S S S S S) to get the size offset we want
1305 + r r r r r r r r r r) to get the final value to place
1306 and D D D D D to chop to right size
1307 -----------------------
1310 ( i i i i i o o o o o from bfd_get<size>
1311 and N N N N N ) get instruction
1312 -----------------------
1318 -----------------------
1319 = R R R R R R R R R R put into bfd_put<size>
1322 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1323 apply_reloc (abfd
, data
, howto
, relocation
);
1327 /* This relocation routine is used by some of the backend linkers.
1328 They do not construct asymbol or arelent structures, so there is no
1329 reason for them to use bfd_perform_relocation. Also,
1330 bfd_perform_relocation is so hacked up it is easier to write a new
1331 function than to try to deal with it.
1333 This routine does a final relocation. Whether it is useful for a
1334 relocatable link depends upon how the object format defines
1337 FIXME: This routine ignores any special_function in the HOWTO,
1338 since the existing special_function values have been written for
1339 bfd_perform_relocation.
1341 HOWTO is the reloc howto information.
1342 INPUT_BFD is the BFD which the reloc applies to.
1343 INPUT_SECTION is the section which the reloc applies to.
1344 CONTENTS is the contents of the section.
1345 ADDRESS is the address of the reloc within INPUT_SECTION.
1346 VALUE is the value of the symbol the reloc refers to.
1347 ADDEND is the addend of the reloc. */
1349 bfd_reloc_status_type
1350 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1352 asection
*input_section
,
1359 bfd_size_type octets
= (address
1360 * bfd_octets_per_byte (input_bfd
, input_section
));
1362 /* Sanity check the address. */
1363 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1364 return bfd_reloc_outofrange
;
1366 /* This function assumes that we are dealing with a basic relocation
1367 against a symbol. We want to compute the value of the symbol to
1368 relocate to. This is just VALUE, the value of the symbol, plus
1369 ADDEND, any addend associated with the reloc. */
1370 relocation
= value
+ addend
;
1372 /* If the relocation is PC relative, we want to set RELOCATION to
1373 the distance between the symbol (currently in RELOCATION) and the
1374 location we are relocating. Some targets (e.g., i386-aout)
1375 arrange for the contents of the section to be the negative of the
1376 offset of the location within the section; for such targets
1377 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1378 the contents of the section as zero; for such targets
1379 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1380 subtract out the offset of the location within the section (which
1381 is just ADDRESS). */
1382 if (howto
->pc_relative
)
1384 relocation
-= (input_section
->output_section
->vma
1385 + input_section
->output_offset
);
1386 if (howto
->pcrel_offset
)
1387 relocation
-= address
;
1390 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1394 /* Relocate a given location using a given value and howto. */
1396 bfd_reloc_status_type
1397 _bfd_relocate_contents (reloc_howto_type
*howto
,
1403 bfd_reloc_status_type flag
;
1404 unsigned int rightshift
= howto
->rightshift
;
1405 unsigned int bitpos
= howto
->bitpos
;
1408 relocation
= -relocation
;
1410 /* Get the value we are going to relocate. */
1411 x
= read_reloc (input_bfd
, location
, howto
);
1413 /* Check for overflow. FIXME: We may drop bits during the addition
1414 which we don't check for. We must either check at every single
1415 operation, which would be tedious, or we must do the computations
1416 in a type larger than bfd_vma, which would be inefficient. */
1417 flag
= bfd_reloc_ok
;
1418 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1420 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1423 /* Get the values to be added together. For signed and unsigned
1424 relocations, we assume that all values should be truncated to
1425 the size of an address. For bitfields, all the bits matter.
1426 See also bfd_check_overflow. */
1427 fieldmask
= N_ONES (howto
->bitsize
);
1428 signmask
= ~fieldmask
;
1429 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1430 | (fieldmask
<< rightshift
));
1431 a
= (relocation
& addrmask
) >> rightshift
;
1432 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1433 addrmask
>>= rightshift
;
1435 switch (howto
->complain_on_overflow
)
1437 case complain_overflow_signed
:
1438 /* If any sign bits are set, all sign bits must be set.
1439 That is, A must be a valid negative address after
1441 signmask
= ~(fieldmask
>> 1);
1444 case complain_overflow_bitfield
:
1445 /* Much like the signed check, but for a field one bit
1446 wider. We allow a bitfield to represent numbers in the
1447 range -2**n to 2**n-1, where n is the number of bits in the
1448 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1449 can't overflow, which is exactly what we want. */
1451 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1452 flag
= bfd_reloc_overflow
;
1454 /* We only need this next bit of code if the sign bit of B
1455 is below the sign bit of A. This would only happen if
1456 SRC_MASK had fewer bits than BITSIZE. Note that if
1457 SRC_MASK has more bits than BITSIZE, we can get into
1458 trouble; we would need to verify that B is in range, as
1459 we do for A above. */
1460 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1463 /* Set all the bits above the sign bit. */
1466 /* Now we can do the addition. */
1469 /* See if the result has the correct sign. Bits above the
1470 sign bit are junk now; ignore them. If the sum is
1471 positive, make sure we did not have all negative inputs;
1472 if the sum is negative, make sure we did not have all
1473 positive inputs. The test below looks only at the sign
1474 bits, and it really just
1475 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1477 We mask with addrmask here to explicitly allow an address
1478 wrap-around. The Linux kernel relies on it, and it is
1479 the only way to write assembler code which can run when
1480 loaded at a location 0x80000000 away from the location at
1481 which it is linked. */
1482 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1483 flag
= bfd_reloc_overflow
;
1486 case complain_overflow_unsigned
:
1487 /* Checking for an unsigned overflow is relatively easy:
1488 trim the addresses and add, and trim the result as well.
1489 Overflow is normally indicated when the result does not
1490 fit in the field. However, we also need to consider the
1491 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1492 input is 0x80000000, and bfd_vma is only 32 bits; then we
1493 will get sum == 0, but there is an overflow, since the
1494 inputs did not fit in the field. Instead of doing a
1495 separate test, we can check for this by or-ing in the
1496 operands when testing for the sum overflowing its final
1498 sum
= (a
+ b
) & addrmask
;
1499 if ((a
| b
| sum
) & signmask
)
1500 flag
= bfd_reloc_overflow
;
1508 /* Put RELOCATION in the right bits. */
1509 relocation
>>= (bfd_vma
) rightshift
;
1510 relocation
<<= (bfd_vma
) bitpos
;
1512 /* Add RELOCATION to the right bits of X. */
1513 x
= ((x
& ~howto
->dst_mask
)
1514 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1516 /* Put the relocated value back in the object file. */
1517 write_reloc (input_bfd
, x
, location
, howto
);
1521 /* Clear a given location using a given howto, by applying a fixed relocation
1522 value and discarding any in-place addend. This is used for fixed-up
1523 relocations against discarded symbols, to make ignorable debug or unwind
1524 information more obvious. */
1526 bfd_reloc_status_type
1527 _bfd_clear_contents (reloc_howto_type
*howto
,
1529 asection
*input_section
,
1536 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1537 return bfd_reloc_outofrange
;
1539 /* Get the value we are going to relocate. */
1540 location
= buf
+ off
;
1541 x
= read_reloc (input_bfd
, location
, howto
);
1543 /* Zero out the unwanted bits of X. */
1544 x
&= ~howto
->dst_mask
;
1546 /* For a range list, use 1 instead of 0 as placeholder. 0
1547 would terminate the list, hiding any later entries. */
1548 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1549 && (howto
->dst_mask
& 1) != 0)
1552 /* Put the relocated value back in the object file. */
1553 write_reloc (input_bfd
, x
, location
, howto
);
1554 return bfd_reloc_ok
;
1560 howto manager, , typedef arelent, Relocations
1565 When an application wants to create a relocation, but doesn't
1566 know what the target machine might call it, it can find out by
1567 using this bit of code.
1576 The insides of a reloc code. The idea is that, eventually, there
1577 will be one enumerator for every type of relocation we ever do.
1578 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1579 return a howto pointer.
1581 This does mean that the application must determine the correct
1582 enumerator value; you can't get a howto pointer from a random set
1603 Basic absolute relocations of N bits.
1618 PC-relative relocations. Sometimes these are relative to the address
1619 of the relocation itself; sometimes they are relative to the start of
1620 the section containing the relocation. It depends on the specific target.
1625 Section relative relocations. Some targets need this for DWARF2.
1628 BFD_RELOC_32_GOT_PCREL
1630 BFD_RELOC_16_GOT_PCREL
1632 BFD_RELOC_8_GOT_PCREL
1638 BFD_RELOC_LO16_GOTOFF
1640 BFD_RELOC_HI16_GOTOFF
1642 BFD_RELOC_HI16_S_GOTOFF
1646 BFD_RELOC_64_PLT_PCREL
1648 BFD_RELOC_32_PLT_PCREL
1650 BFD_RELOC_24_PLT_PCREL
1652 BFD_RELOC_16_PLT_PCREL
1654 BFD_RELOC_8_PLT_PCREL
1662 BFD_RELOC_LO16_PLTOFF
1664 BFD_RELOC_HI16_PLTOFF
1666 BFD_RELOC_HI16_S_PLTOFF
1680 BFD_RELOC_68K_GLOB_DAT
1682 BFD_RELOC_68K_JMP_SLOT
1684 BFD_RELOC_68K_RELATIVE
1686 BFD_RELOC_68K_TLS_GD32
1688 BFD_RELOC_68K_TLS_GD16
1690 BFD_RELOC_68K_TLS_GD8
1692 BFD_RELOC_68K_TLS_LDM32
1694 BFD_RELOC_68K_TLS_LDM16
1696 BFD_RELOC_68K_TLS_LDM8
1698 BFD_RELOC_68K_TLS_LDO32
1700 BFD_RELOC_68K_TLS_LDO16
1702 BFD_RELOC_68K_TLS_LDO8
1704 BFD_RELOC_68K_TLS_IE32
1706 BFD_RELOC_68K_TLS_IE16
1708 BFD_RELOC_68K_TLS_IE8
1710 BFD_RELOC_68K_TLS_LE32
1712 BFD_RELOC_68K_TLS_LE16
1714 BFD_RELOC_68K_TLS_LE8
1716 Relocations used by 68K ELF.
1719 BFD_RELOC_32_BASEREL
1721 BFD_RELOC_16_BASEREL
1723 BFD_RELOC_LO16_BASEREL
1725 BFD_RELOC_HI16_BASEREL
1727 BFD_RELOC_HI16_S_BASEREL
1733 Linkage-table relative.
1738 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1741 BFD_RELOC_32_PCREL_S2
1743 BFD_RELOC_16_PCREL_S2
1745 BFD_RELOC_23_PCREL_S2
1747 These PC-relative relocations are stored as word displacements --
1748 i.e., byte displacements shifted right two bits. The 30-bit word
1749 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1750 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1751 signed 16-bit displacement is used on the MIPS, and the 23-bit
1752 displacement is used on the Alpha.
1759 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1760 the target word. These are used on the SPARC.
1767 For systems that allocate a Global Pointer register, these are
1768 displacements off that register. These relocation types are
1769 handled specially, because the value the register will have is
1770 decided relatively late.
1775 BFD_RELOC_SPARC_WDISP22
1781 BFD_RELOC_SPARC_GOT10
1783 BFD_RELOC_SPARC_GOT13
1785 BFD_RELOC_SPARC_GOT22
1787 BFD_RELOC_SPARC_PC10
1789 BFD_RELOC_SPARC_PC22
1791 BFD_RELOC_SPARC_WPLT30
1793 BFD_RELOC_SPARC_COPY
1795 BFD_RELOC_SPARC_GLOB_DAT
1797 BFD_RELOC_SPARC_JMP_SLOT
1799 BFD_RELOC_SPARC_RELATIVE
1801 BFD_RELOC_SPARC_UA16
1803 BFD_RELOC_SPARC_UA32
1805 BFD_RELOC_SPARC_UA64
1807 BFD_RELOC_SPARC_GOTDATA_HIX22
1809 BFD_RELOC_SPARC_GOTDATA_LOX10
1811 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1813 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1815 BFD_RELOC_SPARC_GOTDATA_OP
1817 BFD_RELOC_SPARC_JMP_IREL
1819 BFD_RELOC_SPARC_IRELATIVE
1821 SPARC ELF relocations. There is probably some overlap with other
1822 relocation types already defined.
1825 BFD_RELOC_SPARC_BASE13
1827 BFD_RELOC_SPARC_BASE22
1829 I think these are specific to SPARC a.out (e.g., Sun 4).
1839 BFD_RELOC_SPARC_OLO10
1841 BFD_RELOC_SPARC_HH22
1843 BFD_RELOC_SPARC_HM10
1845 BFD_RELOC_SPARC_LM22
1847 BFD_RELOC_SPARC_PC_HH22
1849 BFD_RELOC_SPARC_PC_HM10
1851 BFD_RELOC_SPARC_PC_LM22
1853 BFD_RELOC_SPARC_WDISP16
1855 BFD_RELOC_SPARC_WDISP19
1863 BFD_RELOC_SPARC_DISP64
1866 BFD_RELOC_SPARC_PLT32
1868 BFD_RELOC_SPARC_PLT64
1870 BFD_RELOC_SPARC_HIX22
1872 BFD_RELOC_SPARC_LOX10
1880 BFD_RELOC_SPARC_REGISTER
1884 BFD_RELOC_SPARC_SIZE32
1886 BFD_RELOC_SPARC_SIZE64
1888 BFD_RELOC_SPARC_WDISP10
1893 BFD_RELOC_SPARC_REV32
1895 SPARC little endian relocation
1897 BFD_RELOC_SPARC_TLS_GD_HI22
1899 BFD_RELOC_SPARC_TLS_GD_LO10
1901 BFD_RELOC_SPARC_TLS_GD_ADD
1903 BFD_RELOC_SPARC_TLS_GD_CALL
1905 BFD_RELOC_SPARC_TLS_LDM_HI22
1907 BFD_RELOC_SPARC_TLS_LDM_LO10
1909 BFD_RELOC_SPARC_TLS_LDM_ADD
1911 BFD_RELOC_SPARC_TLS_LDM_CALL
1913 BFD_RELOC_SPARC_TLS_LDO_HIX22
1915 BFD_RELOC_SPARC_TLS_LDO_LOX10
1917 BFD_RELOC_SPARC_TLS_LDO_ADD
1919 BFD_RELOC_SPARC_TLS_IE_HI22
1921 BFD_RELOC_SPARC_TLS_IE_LO10
1923 BFD_RELOC_SPARC_TLS_IE_LD
1925 BFD_RELOC_SPARC_TLS_IE_LDX
1927 BFD_RELOC_SPARC_TLS_IE_ADD
1929 BFD_RELOC_SPARC_TLS_LE_HIX22
1931 BFD_RELOC_SPARC_TLS_LE_LOX10
1933 BFD_RELOC_SPARC_TLS_DTPMOD32
1935 BFD_RELOC_SPARC_TLS_DTPMOD64
1937 BFD_RELOC_SPARC_TLS_DTPOFF32
1939 BFD_RELOC_SPARC_TLS_DTPOFF64
1941 BFD_RELOC_SPARC_TLS_TPOFF32
1943 BFD_RELOC_SPARC_TLS_TPOFF64
1945 SPARC TLS relocations
1954 BFD_RELOC_SPU_IMM10W
1958 BFD_RELOC_SPU_IMM16W
1962 BFD_RELOC_SPU_PCREL9a
1964 BFD_RELOC_SPU_PCREL9b
1966 BFD_RELOC_SPU_PCREL16
1976 BFD_RELOC_SPU_ADD_PIC
1981 BFD_RELOC_ALPHA_GPDISP_HI16
1983 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1984 "addend" in some special way.
1985 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1986 writing; when reading, it will be the absolute section symbol. The
1987 addend is the displacement in bytes of the "lda" instruction from
1988 the "ldah" instruction (which is at the address of this reloc).
1990 BFD_RELOC_ALPHA_GPDISP_LO16
1992 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1993 with GPDISP_HI16 relocs. The addend is ignored when writing the
1994 relocations out, and is filled in with the file's GP value on
1995 reading, for convenience.
1998 BFD_RELOC_ALPHA_GPDISP
2000 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2001 relocation except that there is no accompanying GPDISP_LO16
2005 BFD_RELOC_ALPHA_LITERAL
2007 BFD_RELOC_ALPHA_ELF_LITERAL
2009 BFD_RELOC_ALPHA_LITUSE
2011 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2012 the assembler turns it into a LDQ instruction to load the address of
2013 the symbol, and then fills in a register in the real instruction.
2015 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2016 section symbol. The addend is ignored when writing, but is filled
2017 in with the file's GP value on reading, for convenience, as with the
2020 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2021 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2022 but it generates output not based on the position within the .got
2023 section, but relative to the GP value chosen for the file during the
2026 The LITUSE reloc, on the instruction using the loaded address, gives
2027 information to the linker that it might be able to use to optimize
2028 away some literal section references. The symbol is ignored (read
2029 as the absolute section symbol), and the "addend" indicates the type
2030 of instruction using the register:
2031 1 - "memory" fmt insn
2032 2 - byte-manipulation (byte offset reg)
2033 3 - jsr (target of branch)
2036 BFD_RELOC_ALPHA_HINT
2038 The HINT relocation indicates a value that should be filled into the
2039 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2040 prediction logic which may be provided on some processors.
2043 BFD_RELOC_ALPHA_LINKAGE
2045 The LINKAGE relocation outputs a linkage pair in the object file,
2046 which is filled by the linker.
2049 BFD_RELOC_ALPHA_CODEADDR
2051 The CODEADDR relocation outputs a STO_CA in the object file,
2052 which is filled by the linker.
2055 BFD_RELOC_ALPHA_GPREL_HI16
2057 BFD_RELOC_ALPHA_GPREL_LO16
2059 The GPREL_HI/LO relocations together form a 32-bit offset from the
2063 BFD_RELOC_ALPHA_BRSGP
2065 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2066 share a common GP, and the target address is adjusted for
2067 STO_ALPHA_STD_GPLOAD.
2072 The NOP relocation outputs a NOP if the longword displacement
2073 between two procedure entry points is < 2^21.
2078 The BSR relocation outputs a BSR if the longword displacement
2079 between two procedure entry points is < 2^21.
2084 The LDA relocation outputs a LDA if the longword displacement
2085 between two procedure entry points is < 2^16.
2090 The BOH relocation outputs a BSR if the longword displacement
2091 between two procedure entry points is < 2^21, or else a hint.
2094 BFD_RELOC_ALPHA_TLSGD
2096 BFD_RELOC_ALPHA_TLSLDM
2098 BFD_RELOC_ALPHA_DTPMOD64
2100 BFD_RELOC_ALPHA_GOTDTPREL16
2102 BFD_RELOC_ALPHA_DTPREL64
2104 BFD_RELOC_ALPHA_DTPREL_HI16
2106 BFD_RELOC_ALPHA_DTPREL_LO16
2108 BFD_RELOC_ALPHA_DTPREL16
2110 BFD_RELOC_ALPHA_GOTTPREL16
2112 BFD_RELOC_ALPHA_TPREL64
2114 BFD_RELOC_ALPHA_TPREL_HI16
2116 BFD_RELOC_ALPHA_TPREL_LO16
2118 BFD_RELOC_ALPHA_TPREL16
2120 Alpha thread-local storage relocations.
2125 BFD_RELOC_MICROMIPS_JMP
2127 The MIPS jump instruction.
2130 BFD_RELOC_MIPS16_JMP
2132 The MIPS16 jump instruction.
2135 BFD_RELOC_MIPS16_GPREL
2137 MIPS16 GP relative reloc.
2142 High 16 bits of 32-bit value; simple reloc.
2147 High 16 bits of 32-bit value but the low 16 bits will be sign
2148 extended and added to form the final result. If the low 16
2149 bits form a negative number, we need to add one to the high value
2150 to compensate for the borrow when the low bits are added.
2158 BFD_RELOC_HI16_PCREL
2160 High 16 bits of 32-bit pc-relative value
2162 BFD_RELOC_HI16_S_PCREL
2164 High 16 bits of 32-bit pc-relative value, adjusted
2166 BFD_RELOC_LO16_PCREL
2168 Low 16 bits of pc-relative value
2171 BFD_RELOC_MIPS16_GOT16
2173 BFD_RELOC_MIPS16_CALL16
2175 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2176 16-bit immediate fields
2178 BFD_RELOC_MIPS16_HI16
2180 MIPS16 high 16 bits of 32-bit value.
2182 BFD_RELOC_MIPS16_HI16_S
2184 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2185 extended and added to form the final result. If the low 16
2186 bits form a negative number, we need to add one to the high value
2187 to compensate for the borrow when the low bits are added.
2189 BFD_RELOC_MIPS16_LO16
2194 BFD_RELOC_MIPS16_TLS_GD
2196 BFD_RELOC_MIPS16_TLS_LDM
2198 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2200 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2202 BFD_RELOC_MIPS16_TLS_GOTTPREL
2204 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2206 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2208 MIPS16 TLS relocations
2211 BFD_RELOC_MIPS_LITERAL
2213 BFD_RELOC_MICROMIPS_LITERAL
2215 Relocation against a MIPS literal section.
2218 BFD_RELOC_MICROMIPS_7_PCREL_S1
2220 BFD_RELOC_MICROMIPS_10_PCREL_S1
2222 BFD_RELOC_MICROMIPS_16_PCREL_S1
2224 microMIPS PC-relative relocations.
2227 BFD_RELOC_MIPS16_16_PCREL_S1
2229 MIPS16 PC-relative relocation.
2232 BFD_RELOC_MIPS_21_PCREL_S2
2234 BFD_RELOC_MIPS_26_PCREL_S2
2236 BFD_RELOC_MIPS_18_PCREL_S3
2238 BFD_RELOC_MIPS_19_PCREL_S2
2240 MIPS PC-relative relocations.
2243 BFD_RELOC_MICROMIPS_GPREL16
2245 BFD_RELOC_MICROMIPS_HI16
2247 BFD_RELOC_MICROMIPS_HI16_S
2249 BFD_RELOC_MICROMIPS_LO16
2251 microMIPS versions of generic BFD relocs.
2254 BFD_RELOC_MIPS_GOT16
2256 BFD_RELOC_MICROMIPS_GOT16
2258 BFD_RELOC_MIPS_CALL16
2260 BFD_RELOC_MICROMIPS_CALL16
2262 BFD_RELOC_MIPS_GOT_HI16
2264 BFD_RELOC_MICROMIPS_GOT_HI16
2266 BFD_RELOC_MIPS_GOT_LO16
2268 BFD_RELOC_MICROMIPS_GOT_LO16
2270 BFD_RELOC_MIPS_CALL_HI16
2272 BFD_RELOC_MICROMIPS_CALL_HI16
2274 BFD_RELOC_MIPS_CALL_LO16
2276 BFD_RELOC_MICROMIPS_CALL_LO16
2280 BFD_RELOC_MICROMIPS_SUB
2282 BFD_RELOC_MIPS_GOT_PAGE
2284 BFD_RELOC_MICROMIPS_GOT_PAGE
2286 BFD_RELOC_MIPS_GOT_OFST
2288 BFD_RELOC_MICROMIPS_GOT_OFST
2290 BFD_RELOC_MIPS_GOT_DISP
2292 BFD_RELOC_MICROMIPS_GOT_DISP
2294 BFD_RELOC_MIPS_SHIFT5
2296 BFD_RELOC_MIPS_SHIFT6
2298 BFD_RELOC_MIPS_INSERT_A
2300 BFD_RELOC_MIPS_INSERT_B
2302 BFD_RELOC_MIPS_DELETE
2304 BFD_RELOC_MIPS_HIGHEST
2306 BFD_RELOC_MICROMIPS_HIGHEST
2308 BFD_RELOC_MIPS_HIGHER
2310 BFD_RELOC_MICROMIPS_HIGHER
2312 BFD_RELOC_MIPS_SCN_DISP
2314 BFD_RELOC_MICROMIPS_SCN_DISP
2316 BFD_RELOC_MIPS_REL16
2318 BFD_RELOC_MIPS_RELGOT
2322 BFD_RELOC_MICROMIPS_JALR
2324 BFD_RELOC_MIPS_TLS_DTPMOD32
2326 BFD_RELOC_MIPS_TLS_DTPREL32
2328 BFD_RELOC_MIPS_TLS_DTPMOD64
2330 BFD_RELOC_MIPS_TLS_DTPREL64
2332 BFD_RELOC_MIPS_TLS_GD
2334 BFD_RELOC_MICROMIPS_TLS_GD
2336 BFD_RELOC_MIPS_TLS_LDM
2338 BFD_RELOC_MICROMIPS_TLS_LDM
2340 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2342 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2344 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2346 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2348 BFD_RELOC_MIPS_TLS_GOTTPREL
2350 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2352 BFD_RELOC_MIPS_TLS_TPREL32
2354 BFD_RELOC_MIPS_TLS_TPREL64
2356 BFD_RELOC_MIPS_TLS_TPREL_HI16
2358 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2360 BFD_RELOC_MIPS_TLS_TPREL_LO16
2362 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2366 MIPS ELF relocations.
2372 BFD_RELOC_MIPS_JUMP_SLOT
2374 MIPS ELF relocations (VxWorks and PLT extensions).
2378 BFD_RELOC_MOXIE_10_PCREL
2380 Moxie ELF relocations.
2392 BFD_RELOC_FT32_RELAX
2400 BFD_RELOC_FT32_DIFF32
2402 FT32 ELF relocations.
2406 BFD_RELOC_FRV_LABEL16
2408 BFD_RELOC_FRV_LABEL24
2414 BFD_RELOC_FRV_GPREL12
2416 BFD_RELOC_FRV_GPRELU12
2418 BFD_RELOC_FRV_GPREL32
2420 BFD_RELOC_FRV_GPRELHI
2422 BFD_RELOC_FRV_GPRELLO
2430 BFD_RELOC_FRV_FUNCDESC
2432 BFD_RELOC_FRV_FUNCDESC_GOT12
2434 BFD_RELOC_FRV_FUNCDESC_GOTHI
2436 BFD_RELOC_FRV_FUNCDESC_GOTLO
2438 BFD_RELOC_FRV_FUNCDESC_VALUE
2440 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2442 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2444 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2446 BFD_RELOC_FRV_GOTOFF12
2448 BFD_RELOC_FRV_GOTOFFHI
2450 BFD_RELOC_FRV_GOTOFFLO
2452 BFD_RELOC_FRV_GETTLSOFF
2454 BFD_RELOC_FRV_TLSDESC_VALUE
2456 BFD_RELOC_FRV_GOTTLSDESC12
2458 BFD_RELOC_FRV_GOTTLSDESCHI
2460 BFD_RELOC_FRV_GOTTLSDESCLO
2462 BFD_RELOC_FRV_TLSMOFF12
2464 BFD_RELOC_FRV_TLSMOFFHI
2466 BFD_RELOC_FRV_TLSMOFFLO
2468 BFD_RELOC_FRV_GOTTLSOFF12
2470 BFD_RELOC_FRV_GOTTLSOFFHI
2472 BFD_RELOC_FRV_GOTTLSOFFLO
2474 BFD_RELOC_FRV_TLSOFF
2476 BFD_RELOC_FRV_TLSDESC_RELAX
2478 BFD_RELOC_FRV_GETTLSOFF_RELAX
2480 BFD_RELOC_FRV_TLSOFF_RELAX
2482 BFD_RELOC_FRV_TLSMOFF
2484 Fujitsu Frv Relocations.
2488 BFD_RELOC_MN10300_GOTOFF24
2490 This is a 24bit GOT-relative reloc for the mn10300.
2492 BFD_RELOC_MN10300_GOT32
2494 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2497 BFD_RELOC_MN10300_GOT24
2499 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2502 BFD_RELOC_MN10300_GOT16
2504 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2507 BFD_RELOC_MN10300_COPY
2509 Copy symbol at runtime.
2511 BFD_RELOC_MN10300_GLOB_DAT
2515 BFD_RELOC_MN10300_JMP_SLOT
2519 BFD_RELOC_MN10300_RELATIVE
2521 Adjust by program base.
2523 BFD_RELOC_MN10300_SYM_DIFF
2525 Together with another reloc targeted at the same location,
2526 allows for a value that is the difference of two symbols
2527 in the same section.
2529 BFD_RELOC_MN10300_ALIGN
2531 The addend of this reloc is an alignment power that must
2532 be honoured at the offset's location, regardless of linker
2535 BFD_RELOC_MN10300_TLS_GD
2537 BFD_RELOC_MN10300_TLS_LD
2539 BFD_RELOC_MN10300_TLS_LDO
2541 BFD_RELOC_MN10300_TLS_GOTIE
2543 BFD_RELOC_MN10300_TLS_IE
2545 BFD_RELOC_MN10300_TLS_LE
2547 BFD_RELOC_MN10300_TLS_DTPMOD
2549 BFD_RELOC_MN10300_TLS_DTPOFF
2551 BFD_RELOC_MN10300_TLS_TPOFF
2553 Various TLS-related relocations.
2555 BFD_RELOC_MN10300_32_PCREL
2557 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2560 BFD_RELOC_MN10300_16_PCREL
2562 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2573 BFD_RELOC_386_GLOB_DAT
2575 BFD_RELOC_386_JUMP_SLOT
2577 BFD_RELOC_386_RELATIVE
2579 BFD_RELOC_386_GOTOFF
2583 BFD_RELOC_386_TLS_TPOFF
2585 BFD_RELOC_386_TLS_IE
2587 BFD_RELOC_386_TLS_GOTIE
2589 BFD_RELOC_386_TLS_LE
2591 BFD_RELOC_386_TLS_GD
2593 BFD_RELOC_386_TLS_LDM
2595 BFD_RELOC_386_TLS_LDO_32
2597 BFD_RELOC_386_TLS_IE_32
2599 BFD_RELOC_386_TLS_LE_32
2601 BFD_RELOC_386_TLS_DTPMOD32
2603 BFD_RELOC_386_TLS_DTPOFF32
2605 BFD_RELOC_386_TLS_TPOFF32
2607 BFD_RELOC_386_TLS_GOTDESC
2609 BFD_RELOC_386_TLS_DESC_CALL
2611 BFD_RELOC_386_TLS_DESC
2613 BFD_RELOC_386_IRELATIVE
2615 BFD_RELOC_386_GOT32X
2617 i386/elf relocations
2620 BFD_RELOC_X86_64_GOT32
2622 BFD_RELOC_X86_64_PLT32
2624 BFD_RELOC_X86_64_COPY
2626 BFD_RELOC_X86_64_GLOB_DAT
2628 BFD_RELOC_X86_64_JUMP_SLOT
2630 BFD_RELOC_X86_64_RELATIVE
2632 BFD_RELOC_X86_64_GOTPCREL
2634 BFD_RELOC_X86_64_32S
2636 BFD_RELOC_X86_64_DTPMOD64
2638 BFD_RELOC_X86_64_DTPOFF64
2640 BFD_RELOC_X86_64_TPOFF64
2642 BFD_RELOC_X86_64_TLSGD
2644 BFD_RELOC_X86_64_TLSLD
2646 BFD_RELOC_X86_64_DTPOFF32
2648 BFD_RELOC_X86_64_GOTTPOFF
2650 BFD_RELOC_X86_64_TPOFF32
2652 BFD_RELOC_X86_64_GOTOFF64
2654 BFD_RELOC_X86_64_GOTPC32
2656 BFD_RELOC_X86_64_GOT64
2658 BFD_RELOC_X86_64_GOTPCREL64
2660 BFD_RELOC_X86_64_GOTPC64
2662 BFD_RELOC_X86_64_GOTPLT64
2664 BFD_RELOC_X86_64_PLTOFF64
2666 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2668 BFD_RELOC_X86_64_TLSDESC_CALL
2670 BFD_RELOC_X86_64_TLSDESC
2672 BFD_RELOC_X86_64_IRELATIVE
2674 BFD_RELOC_X86_64_PC32_BND
2676 BFD_RELOC_X86_64_PLT32_BND
2678 BFD_RELOC_X86_64_GOTPCRELX
2680 BFD_RELOC_X86_64_REX_GOTPCRELX
2682 x86-64/elf relocations
2685 BFD_RELOC_NS32K_IMM_8
2687 BFD_RELOC_NS32K_IMM_16
2689 BFD_RELOC_NS32K_IMM_32
2691 BFD_RELOC_NS32K_IMM_8_PCREL
2693 BFD_RELOC_NS32K_IMM_16_PCREL
2695 BFD_RELOC_NS32K_IMM_32_PCREL
2697 BFD_RELOC_NS32K_DISP_8
2699 BFD_RELOC_NS32K_DISP_16
2701 BFD_RELOC_NS32K_DISP_32
2703 BFD_RELOC_NS32K_DISP_8_PCREL
2705 BFD_RELOC_NS32K_DISP_16_PCREL
2707 BFD_RELOC_NS32K_DISP_32_PCREL
2712 BFD_RELOC_PDP11_DISP_8_PCREL
2714 BFD_RELOC_PDP11_DISP_6_PCREL
2719 BFD_RELOC_PJ_CODE_HI16
2721 BFD_RELOC_PJ_CODE_LO16
2723 BFD_RELOC_PJ_CODE_DIR16
2725 BFD_RELOC_PJ_CODE_DIR32
2727 BFD_RELOC_PJ_CODE_REL16
2729 BFD_RELOC_PJ_CODE_REL32
2731 Picojava relocs. Not all of these appear in object files.
2742 BFD_RELOC_PPC_B16_BRTAKEN
2744 BFD_RELOC_PPC_B16_BRNTAKEN
2748 BFD_RELOC_PPC_BA16_BRTAKEN
2750 BFD_RELOC_PPC_BA16_BRNTAKEN
2754 BFD_RELOC_PPC_GLOB_DAT
2756 BFD_RELOC_PPC_JMP_SLOT
2758 BFD_RELOC_PPC_RELATIVE
2760 BFD_RELOC_PPC_LOCAL24PC
2762 BFD_RELOC_PPC_EMB_NADDR32
2764 BFD_RELOC_PPC_EMB_NADDR16
2766 BFD_RELOC_PPC_EMB_NADDR16_LO
2768 BFD_RELOC_PPC_EMB_NADDR16_HI
2770 BFD_RELOC_PPC_EMB_NADDR16_HA
2772 BFD_RELOC_PPC_EMB_SDAI16
2774 BFD_RELOC_PPC_EMB_SDA2I16
2776 BFD_RELOC_PPC_EMB_SDA2REL
2778 BFD_RELOC_PPC_EMB_SDA21
2780 BFD_RELOC_PPC_EMB_MRKREF
2782 BFD_RELOC_PPC_EMB_RELSEC16
2784 BFD_RELOC_PPC_EMB_RELST_LO
2786 BFD_RELOC_PPC_EMB_RELST_HI
2788 BFD_RELOC_PPC_EMB_RELST_HA
2790 BFD_RELOC_PPC_EMB_BIT_FLD
2792 BFD_RELOC_PPC_EMB_RELSDA
2794 BFD_RELOC_PPC_VLE_REL8
2796 BFD_RELOC_PPC_VLE_REL15
2798 BFD_RELOC_PPC_VLE_REL24
2800 BFD_RELOC_PPC_VLE_LO16A
2802 BFD_RELOC_PPC_VLE_LO16D
2804 BFD_RELOC_PPC_VLE_HI16A
2806 BFD_RELOC_PPC_VLE_HI16D
2808 BFD_RELOC_PPC_VLE_HA16A
2810 BFD_RELOC_PPC_VLE_HA16D
2812 BFD_RELOC_PPC_VLE_SDA21
2814 BFD_RELOC_PPC_VLE_SDA21_LO
2816 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2818 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2820 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2822 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2824 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2826 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2828 BFD_RELOC_PPC_16DX_HA
2830 BFD_RELOC_PPC_REL16DX_HA
2832 BFD_RELOC_PPC64_HIGHER
2834 BFD_RELOC_PPC64_HIGHER_S
2836 BFD_RELOC_PPC64_HIGHEST
2838 BFD_RELOC_PPC64_HIGHEST_S
2840 BFD_RELOC_PPC64_TOC16_LO
2842 BFD_RELOC_PPC64_TOC16_HI
2844 BFD_RELOC_PPC64_TOC16_HA
2848 BFD_RELOC_PPC64_PLTGOT16
2850 BFD_RELOC_PPC64_PLTGOT16_LO
2852 BFD_RELOC_PPC64_PLTGOT16_HI
2854 BFD_RELOC_PPC64_PLTGOT16_HA
2856 BFD_RELOC_PPC64_ADDR16_DS
2858 BFD_RELOC_PPC64_ADDR16_LO_DS
2860 BFD_RELOC_PPC64_GOT16_DS
2862 BFD_RELOC_PPC64_GOT16_LO_DS
2864 BFD_RELOC_PPC64_PLT16_LO_DS
2866 BFD_RELOC_PPC64_SECTOFF_DS
2868 BFD_RELOC_PPC64_SECTOFF_LO_DS
2870 BFD_RELOC_PPC64_TOC16_DS
2872 BFD_RELOC_PPC64_TOC16_LO_DS
2874 BFD_RELOC_PPC64_PLTGOT16_DS
2876 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2878 BFD_RELOC_PPC64_ADDR16_HIGH
2880 BFD_RELOC_PPC64_ADDR16_HIGHA
2882 BFD_RELOC_PPC64_REL16_HIGH
2884 BFD_RELOC_PPC64_REL16_HIGHA
2886 BFD_RELOC_PPC64_REL16_HIGHER
2888 BFD_RELOC_PPC64_REL16_HIGHERA
2890 BFD_RELOC_PPC64_REL16_HIGHEST
2892 BFD_RELOC_PPC64_REL16_HIGHESTA
2894 BFD_RELOC_PPC64_ADDR64_LOCAL
2896 BFD_RELOC_PPC64_ENTRY
2898 BFD_RELOC_PPC64_REL24_NOTOC
2902 BFD_RELOC_PPC64_D34_LO
2904 BFD_RELOC_PPC64_D34_HI30
2906 BFD_RELOC_PPC64_D34_HA30
2908 BFD_RELOC_PPC64_PCREL34
2910 BFD_RELOC_PPC64_GOT_PCREL34
2912 BFD_RELOC_PPC64_PLT_PCREL34
2914 BFD_RELOC_PPC64_ADDR16_HIGHER34
2916 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2918 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2920 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2922 BFD_RELOC_PPC64_REL16_HIGHER34
2924 BFD_RELOC_PPC64_REL16_HIGHERA34
2926 BFD_RELOC_PPC64_REL16_HIGHEST34
2928 BFD_RELOC_PPC64_REL16_HIGHESTA34
2932 BFD_RELOC_PPC64_PCREL28
2934 Power(rs6000) and PowerPC relocations.
2943 BFD_RELOC_PPC_DTPMOD
2945 BFD_RELOC_PPC_TPREL16
2947 BFD_RELOC_PPC_TPREL16_LO
2949 BFD_RELOC_PPC_TPREL16_HI
2951 BFD_RELOC_PPC_TPREL16_HA
2955 BFD_RELOC_PPC_DTPREL16
2957 BFD_RELOC_PPC_DTPREL16_LO
2959 BFD_RELOC_PPC_DTPREL16_HI
2961 BFD_RELOC_PPC_DTPREL16_HA
2963 BFD_RELOC_PPC_DTPREL
2965 BFD_RELOC_PPC_GOT_TLSGD16
2967 BFD_RELOC_PPC_GOT_TLSGD16_LO
2969 BFD_RELOC_PPC_GOT_TLSGD16_HI
2971 BFD_RELOC_PPC_GOT_TLSGD16_HA
2973 BFD_RELOC_PPC_GOT_TLSLD16
2975 BFD_RELOC_PPC_GOT_TLSLD16_LO
2977 BFD_RELOC_PPC_GOT_TLSLD16_HI
2979 BFD_RELOC_PPC_GOT_TLSLD16_HA
2981 BFD_RELOC_PPC_GOT_TPREL16
2983 BFD_RELOC_PPC_GOT_TPREL16_LO
2985 BFD_RELOC_PPC_GOT_TPREL16_HI
2987 BFD_RELOC_PPC_GOT_TPREL16_HA
2989 BFD_RELOC_PPC_GOT_DTPREL16
2991 BFD_RELOC_PPC_GOT_DTPREL16_LO
2993 BFD_RELOC_PPC_GOT_DTPREL16_HI
2995 BFD_RELOC_PPC_GOT_DTPREL16_HA
2997 BFD_RELOC_PPC64_TPREL16_DS
2999 BFD_RELOC_PPC64_TPREL16_LO_DS
3001 BFD_RELOC_PPC64_TPREL16_HIGH
3003 BFD_RELOC_PPC64_TPREL16_HIGHA
3005 BFD_RELOC_PPC64_TPREL16_HIGHER
3007 BFD_RELOC_PPC64_TPREL16_HIGHERA
3009 BFD_RELOC_PPC64_TPREL16_HIGHEST
3011 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3013 BFD_RELOC_PPC64_DTPREL16_DS
3015 BFD_RELOC_PPC64_DTPREL16_LO_DS
3017 BFD_RELOC_PPC64_DTPREL16_HIGH
3019 BFD_RELOC_PPC64_DTPREL16_HIGHA
3021 BFD_RELOC_PPC64_DTPREL16_HIGHER
3023 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3025 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3027 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3029 BFD_RELOC_PPC64_TPREL34
3031 BFD_RELOC_PPC64_DTPREL34
3033 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
3035 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
3037 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
3039 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
3041 BFD_RELOC_PPC64_TLS_PCREL
3043 PowerPC and PowerPC64 thread-local storage relocations.
3048 IBM 370/390 relocations
3053 The type of reloc used to build a constructor table - at the moment
3054 probably a 32 bit wide absolute relocation, but the target can choose.
3055 It generally does map to one of the other relocation types.
3058 BFD_RELOC_ARM_PCREL_BRANCH
3060 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3061 not stored in the instruction.
3063 BFD_RELOC_ARM_PCREL_BLX
3065 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3066 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3067 field in the instruction.
3069 BFD_RELOC_THUMB_PCREL_BLX
3071 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3072 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3073 field in the instruction.
3075 BFD_RELOC_ARM_PCREL_CALL
3077 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3079 BFD_RELOC_ARM_PCREL_JUMP
3081 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3084 BFD_RELOC_THUMB_PCREL_BRANCH5
3086 ARM 5-bit pc-relative branch for Branch Future instructions.
3089 BFD_RELOC_THUMB_PCREL_BFCSEL
3091 ARM 6-bit pc-relative branch for BFCSEL instruction.
3094 BFD_RELOC_ARM_THUMB_BF17
3096 ARM 17-bit pc-relative branch for Branch Future instructions.
3099 BFD_RELOC_ARM_THUMB_BF13
3101 ARM 13-bit pc-relative branch for BFCSEL instruction.
3104 BFD_RELOC_ARM_THUMB_BF19
3106 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3109 BFD_RELOC_ARM_THUMB_LOOP12
3111 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3114 BFD_RELOC_THUMB_PCREL_BRANCH7
3116 BFD_RELOC_THUMB_PCREL_BRANCH9
3118 BFD_RELOC_THUMB_PCREL_BRANCH12
3120 BFD_RELOC_THUMB_PCREL_BRANCH20
3122 BFD_RELOC_THUMB_PCREL_BRANCH23
3124 BFD_RELOC_THUMB_PCREL_BRANCH25
3126 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3127 The lowest bit must be zero and is not stored in the instruction.
3128 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3129 "nn" one smaller in all cases. Note further that BRANCH23
3130 corresponds to R_ARM_THM_CALL.
3133 BFD_RELOC_ARM_OFFSET_IMM
3135 12-bit immediate offset, used in ARM-format ldr and str instructions.
3138 BFD_RELOC_ARM_THUMB_OFFSET
3140 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3143 BFD_RELOC_ARM_TARGET1
3145 Pc-relative or absolute relocation depending on target. Used for
3146 entries in .init_array sections.
3148 BFD_RELOC_ARM_ROSEGREL32
3150 Read-only segment base relative address.
3152 BFD_RELOC_ARM_SBREL32
3154 Data segment base relative address.
3156 BFD_RELOC_ARM_TARGET2
3158 This reloc is used for references to RTTI data from exception handling
3159 tables. The actual definition depends on the target. It may be a
3160 pc-relative or some form of GOT-indirect relocation.
3162 BFD_RELOC_ARM_PREL31
3164 31-bit PC relative address.
3170 BFD_RELOC_ARM_MOVW_PCREL
3172 BFD_RELOC_ARM_MOVT_PCREL
3174 BFD_RELOC_ARM_THUMB_MOVW
3176 BFD_RELOC_ARM_THUMB_MOVT
3178 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3180 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3182 Low and High halfword relocations for MOVW and MOVT instructions.
3185 BFD_RELOC_ARM_GOTFUNCDESC
3187 BFD_RELOC_ARM_GOTOFFFUNCDESC
3189 BFD_RELOC_ARM_FUNCDESC
3191 BFD_RELOC_ARM_FUNCDESC_VALUE
3193 BFD_RELOC_ARM_TLS_GD32_FDPIC
3195 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3197 BFD_RELOC_ARM_TLS_IE32_FDPIC
3199 ARM FDPIC specific relocations.
3202 BFD_RELOC_ARM_JUMP_SLOT
3204 BFD_RELOC_ARM_GLOB_DAT
3210 BFD_RELOC_ARM_RELATIVE
3212 BFD_RELOC_ARM_GOTOFF
3216 BFD_RELOC_ARM_GOT_PREL
3218 Relocations for setting up GOTs and PLTs for shared libraries.
3221 BFD_RELOC_ARM_TLS_GD32
3223 BFD_RELOC_ARM_TLS_LDO32
3225 BFD_RELOC_ARM_TLS_LDM32
3227 BFD_RELOC_ARM_TLS_DTPOFF32
3229 BFD_RELOC_ARM_TLS_DTPMOD32
3231 BFD_RELOC_ARM_TLS_TPOFF32
3233 BFD_RELOC_ARM_TLS_IE32
3235 BFD_RELOC_ARM_TLS_LE32
3237 BFD_RELOC_ARM_TLS_GOTDESC
3239 BFD_RELOC_ARM_TLS_CALL
3241 BFD_RELOC_ARM_THM_TLS_CALL
3243 BFD_RELOC_ARM_TLS_DESCSEQ
3245 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3247 BFD_RELOC_ARM_TLS_DESC
3249 ARM thread-local storage relocations.
3252 BFD_RELOC_ARM_ALU_PC_G0_NC
3254 BFD_RELOC_ARM_ALU_PC_G0
3256 BFD_RELOC_ARM_ALU_PC_G1_NC
3258 BFD_RELOC_ARM_ALU_PC_G1
3260 BFD_RELOC_ARM_ALU_PC_G2
3262 BFD_RELOC_ARM_LDR_PC_G0
3264 BFD_RELOC_ARM_LDR_PC_G1
3266 BFD_RELOC_ARM_LDR_PC_G2
3268 BFD_RELOC_ARM_LDRS_PC_G0
3270 BFD_RELOC_ARM_LDRS_PC_G1
3272 BFD_RELOC_ARM_LDRS_PC_G2
3274 BFD_RELOC_ARM_LDC_PC_G0
3276 BFD_RELOC_ARM_LDC_PC_G1
3278 BFD_RELOC_ARM_LDC_PC_G2
3280 BFD_RELOC_ARM_ALU_SB_G0_NC
3282 BFD_RELOC_ARM_ALU_SB_G0
3284 BFD_RELOC_ARM_ALU_SB_G1_NC
3286 BFD_RELOC_ARM_ALU_SB_G1
3288 BFD_RELOC_ARM_ALU_SB_G2
3290 BFD_RELOC_ARM_LDR_SB_G0
3292 BFD_RELOC_ARM_LDR_SB_G1
3294 BFD_RELOC_ARM_LDR_SB_G2
3296 BFD_RELOC_ARM_LDRS_SB_G0
3298 BFD_RELOC_ARM_LDRS_SB_G1
3300 BFD_RELOC_ARM_LDRS_SB_G2
3302 BFD_RELOC_ARM_LDC_SB_G0
3304 BFD_RELOC_ARM_LDC_SB_G1
3306 BFD_RELOC_ARM_LDC_SB_G2
3308 ARM group relocations.
3313 Annotation of BX instructions.
3316 BFD_RELOC_ARM_IRELATIVE
3318 ARM support for STT_GNU_IFUNC.
3321 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3323 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3325 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3327 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3329 Thumb1 relocations to support execute-only code.
3332 BFD_RELOC_ARM_IMMEDIATE
3334 BFD_RELOC_ARM_ADRL_IMMEDIATE
3336 BFD_RELOC_ARM_T32_IMMEDIATE
3338 BFD_RELOC_ARM_T32_ADD_IMM
3340 BFD_RELOC_ARM_T32_IMM12
3342 BFD_RELOC_ARM_T32_ADD_PC12
3344 BFD_RELOC_ARM_SHIFT_IMM
3354 BFD_RELOC_ARM_CP_OFF_IMM
3356 BFD_RELOC_ARM_CP_OFF_IMM_S2
3358 BFD_RELOC_ARM_T32_CP_OFF_IMM
3360 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3362 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3364 BFD_RELOC_ARM_ADR_IMM
3366 BFD_RELOC_ARM_LDR_IMM
3368 BFD_RELOC_ARM_LITERAL
3370 BFD_RELOC_ARM_IN_POOL
3372 BFD_RELOC_ARM_OFFSET_IMM8
3374 BFD_RELOC_ARM_T32_OFFSET_U8
3376 BFD_RELOC_ARM_T32_OFFSET_IMM
3378 BFD_RELOC_ARM_HWLITERAL
3380 BFD_RELOC_ARM_THUMB_ADD
3382 BFD_RELOC_ARM_THUMB_IMM
3384 BFD_RELOC_ARM_THUMB_SHIFT
3386 These relocs are only used within the ARM assembler. They are not
3387 (at present) written to any object files.
3390 BFD_RELOC_SH_PCDISP8BY2
3392 BFD_RELOC_SH_PCDISP12BY2
3400 BFD_RELOC_SH_DISP12BY2
3402 BFD_RELOC_SH_DISP12BY4
3404 BFD_RELOC_SH_DISP12BY8
3408 BFD_RELOC_SH_DISP20BY8
3412 BFD_RELOC_SH_IMM4BY2
3414 BFD_RELOC_SH_IMM4BY4
3418 BFD_RELOC_SH_IMM8BY2
3420 BFD_RELOC_SH_IMM8BY4
3422 BFD_RELOC_SH_PCRELIMM8BY2
3424 BFD_RELOC_SH_PCRELIMM8BY4
3426 BFD_RELOC_SH_SWITCH16
3428 BFD_RELOC_SH_SWITCH32
3442 BFD_RELOC_SH_LOOP_START
3444 BFD_RELOC_SH_LOOP_END
3448 BFD_RELOC_SH_GLOB_DAT
3450 BFD_RELOC_SH_JMP_SLOT
3452 BFD_RELOC_SH_RELATIVE
3456 BFD_RELOC_SH_GOT_LOW16
3458 BFD_RELOC_SH_GOT_MEDLOW16
3460 BFD_RELOC_SH_GOT_MEDHI16
3462 BFD_RELOC_SH_GOT_HI16
3464 BFD_RELOC_SH_GOTPLT_LOW16
3466 BFD_RELOC_SH_GOTPLT_MEDLOW16
3468 BFD_RELOC_SH_GOTPLT_MEDHI16
3470 BFD_RELOC_SH_GOTPLT_HI16
3472 BFD_RELOC_SH_PLT_LOW16
3474 BFD_RELOC_SH_PLT_MEDLOW16
3476 BFD_RELOC_SH_PLT_MEDHI16
3478 BFD_RELOC_SH_PLT_HI16
3480 BFD_RELOC_SH_GOTOFF_LOW16
3482 BFD_RELOC_SH_GOTOFF_MEDLOW16
3484 BFD_RELOC_SH_GOTOFF_MEDHI16
3486 BFD_RELOC_SH_GOTOFF_HI16
3488 BFD_RELOC_SH_GOTPC_LOW16
3490 BFD_RELOC_SH_GOTPC_MEDLOW16
3492 BFD_RELOC_SH_GOTPC_MEDHI16
3494 BFD_RELOC_SH_GOTPC_HI16
3498 BFD_RELOC_SH_GLOB_DAT64
3500 BFD_RELOC_SH_JMP_SLOT64
3502 BFD_RELOC_SH_RELATIVE64
3504 BFD_RELOC_SH_GOT10BY4
3506 BFD_RELOC_SH_GOT10BY8
3508 BFD_RELOC_SH_GOTPLT10BY4
3510 BFD_RELOC_SH_GOTPLT10BY8
3512 BFD_RELOC_SH_GOTPLT32
3514 BFD_RELOC_SH_SHMEDIA_CODE
3520 BFD_RELOC_SH_IMMS6BY32
3526 BFD_RELOC_SH_IMMS10BY2
3528 BFD_RELOC_SH_IMMS10BY4
3530 BFD_RELOC_SH_IMMS10BY8
3536 BFD_RELOC_SH_IMM_LOW16
3538 BFD_RELOC_SH_IMM_LOW16_PCREL
3540 BFD_RELOC_SH_IMM_MEDLOW16
3542 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3544 BFD_RELOC_SH_IMM_MEDHI16
3546 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3548 BFD_RELOC_SH_IMM_HI16
3550 BFD_RELOC_SH_IMM_HI16_PCREL
3554 BFD_RELOC_SH_TLS_GD_32
3556 BFD_RELOC_SH_TLS_LD_32
3558 BFD_RELOC_SH_TLS_LDO_32
3560 BFD_RELOC_SH_TLS_IE_32
3562 BFD_RELOC_SH_TLS_LE_32
3564 BFD_RELOC_SH_TLS_DTPMOD32
3566 BFD_RELOC_SH_TLS_DTPOFF32
3568 BFD_RELOC_SH_TLS_TPOFF32
3572 BFD_RELOC_SH_GOTOFF20
3574 BFD_RELOC_SH_GOTFUNCDESC
3576 BFD_RELOC_SH_GOTFUNCDESC20
3578 BFD_RELOC_SH_GOTOFFFUNCDESC
3580 BFD_RELOC_SH_GOTOFFFUNCDESC20
3582 BFD_RELOC_SH_FUNCDESC
3584 Renesas / SuperH SH relocs. Not all of these appear in object files.
3607 BFD_RELOC_ARC_SECTOFF
3609 BFD_RELOC_ARC_S21H_PCREL
3611 BFD_RELOC_ARC_S21W_PCREL
3613 BFD_RELOC_ARC_S25H_PCREL
3615 BFD_RELOC_ARC_S25W_PCREL
3619 BFD_RELOC_ARC_SDA_LDST
3621 BFD_RELOC_ARC_SDA_LDST1
3623 BFD_RELOC_ARC_SDA_LDST2
3625 BFD_RELOC_ARC_SDA16_LD
3627 BFD_RELOC_ARC_SDA16_LD1
3629 BFD_RELOC_ARC_SDA16_LD2
3631 BFD_RELOC_ARC_S13_PCREL
3637 BFD_RELOC_ARC_32_ME_S
3639 BFD_RELOC_ARC_N32_ME
3641 BFD_RELOC_ARC_SECTOFF_ME
3643 BFD_RELOC_ARC_SDA32_ME
3647 BFD_RELOC_AC_SECTOFF_U8
3649 BFD_RELOC_AC_SECTOFF_U8_1
3651 BFD_RELOC_AC_SECTOFF_U8_2
3653 BFD_RELOC_AC_SECTOFF_S9
3655 BFD_RELOC_AC_SECTOFF_S9_1
3657 BFD_RELOC_AC_SECTOFF_S9_2
3659 BFD_RELOC_ARC_SECTOFF_ME_1
3661 BFD_RELOC_ARC_SECTOFF_ME_2
3663 BFD_RELOC_ARC_SECTOFF_1
3665 BFD_RELOC_ARC_SECTOFF_2
3667 BFD_RELOC_ARC_SDA_12
3669 BFD_RELOC_ARC_SDA16_ST2
3671 BFD_RELOC_ARC_32_PCREL
3677 BFD_RELOC_ARC_GOTPC32
3683 BFD_RELOC_ARC_GLOB_DAT
3685 BFD_RELOC_ARC_JMP_SLOT
3687 BFD_RELOC_ARC_RELATIVE
3689 BFD_RELOC_ARC_GOTOFF
3693 BFD_RELOC_ARC_S21W_PCREL_PLT
3695 BFD_RELOC_ARC_S25H_PCREL_PLT
3697 BFD_RELOC_ARC_TLS_DTPMOD
3699 BFD_RELOC_ARC_TLS_TPOFF
3701 BFD_RELOC_ARC_TLS_GD_GOT
3703 BFD_RELOC_ARC_TLS_GD_LD
3705 BFD_RELOC_ARC_TLS_GD_CALL
3707 BFD_RELOC_ARC_TLS_IE_GOT
3709 BFD_RELOC_ARC_TLS_DTPOFF
3711 BFD_RELOC_ARC_TLS_DTPOFF_S9
3713 BFD_RELOC_ARC_TLS_LE_S9
3715 BFD_RELOC_ARC_TLS_LE_32
3717 BFD_RELOC_ARC_S25W_PCREL_PLT
3719 BFD_RELOC_ARC_S21H_PCREL_PLT
3721 BFD_RELOC_ARC_NPS_CMEM16
3723 BFD_RELOC_ARC_JLI_SECTOFF
3728 BFD_RELOC_BFIN_16_IMM
3730 ADI Blackfin 16 bit immediate absolute reloc.
3732 BFD_RELOC_BFIN_16_HIGH
3734 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3736 BFD_RELOC_BFIN_4_PCREL
3738 ADI Blackfin 'a' part of LSETUP.
3740 BFD_RELOC_BFIN_5_PCREL
3744 BFD_RELOC_BFIN_16_LOW
3746 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3748 BFD_RELOC_BFIN_10_PCREL
3752 BFD_RELOC_BFIN_11_PCREL
3754 ADI Blackfin 'b' part of LSETUP.
3756 BFD_RELOC_BFIN_12_PCREL_JUMP
3760 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3762 ADI Blackfin Short jump, pcrel.
3764 BFD_RELOC_BFIN_24_PCREL_CALL_X
3766 ADI Blackfin Call.x not implemented.
3768 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3770 ADI Blackfin Long Jump pcrel.
3772 BFD_RELOC_BFIN_GOT17M4
3774 BFD_RELOC_BFIN_GOTHI
3776 BFD_RELOC_BFIN_GOTLO
3778 BFD_RELOC_BFIN_FUNCDESC
3780 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3782 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3784 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3786 BFD_RELOC_BFIN_FUNCDESC_VALUE
3788 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3790 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3792 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3794 BFD_RELOC_BFIN_GOTOFF17M4
3796 BFD_RELOC_BFIN_GOTOFFHI
3798 BFD_RELOC_BFIN_GOTOFFLO
3800 ADI Blackfin FD-PIC relocations.
3804 ADI Blackfin GOT relocation.
3806 BFD_RELOC_BFIN_PLTPC
3808 ADI Blackfin PLTPC relocation.
3810 BFD_ARELOC_BFIN_PUSH
3812 ADI Blackfin arithmetic relocation.
3814 BFD_ARELOC_BFIN_CONST
3816 ADI Blackfin arithmetic relocation.
3820 ADI Blackfin arithmetic relocation.
3824 ADI Blackfin arithmetic relocation.
3826 BFD_ARELOC_BFIN_MULT
3828 ADI Blackfin arithmetic relocation.
3832 ADI Blackfin arithmetic relocation.
3836 ADI Blackfin arithmetic relocation.
3838 BFD_ARELOC_BFIN_LSHIFT
3840 ADI Blackfin arithmetic relocation.
3842 BFD_ARELOC_BFIN_RSHIFT
3844 ADI Blackfin arithmetic relocation.
3848 ADI Blackfin arithmetic relocation.
3852 ADI Blackfin arithmetic relocation.
3856 ADI Blackfin arithmetic relocation.
3858 BFD_ARELOC_BFIN_LAND
3860 ADI Blackfin arithmetic relocation.
3864 ADI Blackfin arithmetic relocation.
3868 ADI Blackfin arithmetic relocation.
3872 ADI Blackfin arithmetic relocation.
3874 BFD_ARELOC_BFIN_COMP
3876 ADI Blackfin arithmetic relocation.
3878 BFD_ARELOC_BFIN_PAGE
3880 ADI Blackfin arithmetic relocation.
3882 BFD_ARELOC_BFIN_HWPAGE
3884 ADI Blackfin arithmetic relocation.
3886 BFD_ARELOC_BFIN_ADDR
3888 ADI Blackfin arithmetic relocation.
3891 BFD_RELOC_D10V_10_PCREL_R
3893 Mitsubishi D10V relocs.
3894 This is a 10-bit reloc with the right 2 bits
3897 BFD_RELOC_D10V_10_PCREL_L
3899 Mitsubishi D10V relocs.
3900 This is a 10-bit reloc with the right 2 bits
3901 assumed to be 0. This is the same as the previous reloc
3902 except it is in the left container, i.e.,
3903 shifted left 15 bits.
3907 This is an 18-bit reloc with the right 2 bits
3910 BFD_RELOC_D10V_18_PCREL
3912 This is an 18-bit reloc with the right 2 bits
3918 Mitsubishi D30V relocs.
3919 This is a 6-bit absolute reloc.
3921 BFD_RELOC_D30V_9_PCREL
3923 This is a 6-bit pc-relative reloc with
3924 the right 3 bits assumed to be 0.
3926 BFD_RELOC_D30V_9_PCREL_R
3928 This is a 6-bit pc-relative reloc with
3929 the right 3 bits assumed to be 0. Same
3930 as the previous reloc but on the right side
3935 This is a 12-bit absolute reloc with the
3936 right 3 bitsassumed to be 0.
3938 BFD_RELOC_D30V_15_PCREL
3940 This is a 12-bit pc-relative reloc with
3941 the right 3 bits assumed to be 0.
3943 BFD_RELOC_D30V_15_PCREL_R
3945 This is a 12-bit pc-relative reloc with
3946 the right 3 bits assumed to be 0. Same
3947 as the previous reloc but on the right side
3952 This is an 18-bit absolute reloc with
3953 the right 3 bits assumed to be 0.
3955 BFD_RELOC_D30V_21_PCREL
3957 This is an 18-bit pc-relative reloc with
3958 the right 3 bits assumed to be 0.
3960 BFD_RELOC_D30V_21_PCREL_R
3962 This is an 18-bit pc-relative reloc with
3963 the right 3 bits assumed to be 0. Same
3964 as the previous reloc but on the right side
3969 This is a 32-bit absolute reloc.
3971 BFD_RELOC_D30V_32_PCREL
3973 This is a 32-bit pc-relative reloc.
3976 BFD_RELOC_DLX_HI16_S
3991 BFD_RELOC_M32C_RL_JUMP
3993 BFD_RELOC_M32C_RL_1ADDR
3995 BFD_RELOC_M32C_RL_2ADDR
3997 Renesas M16C/M32C Relocations.
4002 Renesas M32R (formerly Mitsubishi M32R) relocs.
4003 This is a 24 bit absolute address.
4005 BFD_RELOC_M32R_10_PCREL
4007 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4009 BFD_RELOC_M32R_18_PCREL
4011 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4013 BFD_RELOC_M32R_26_PCREL
4015 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4017 BFD_RELOC_M32R_HI16_ULO
4019 This is a 16-bit reloc containing the high 16 bits of an address
4020 used when the lower 16 bits are treated as unsigned.
4022 BFD_RELOC_M32R_HI16_SLO
4024 This is a 16-bit reloc containing the high 16 bits of an address
4025 used when the lower 16 bits are treated as signed.
4029 This is a 16-bit reloc containing the lower 16 bits of an address.
4031 BFD_RELOC_M32R_SDA16
4033 This is a 16-bit reloc containing the small data area offset for use in
4034 add3, load, and store instructions.
4036 BFD_RELOC_M32R_GOT24
4038 BFD_RELOC_M32R_26_PLTREL
4042 BFD_RELOC_M32R_GLOB_DAT
4044 BFD_RELOC_M32R_JMP_SLOT
4046 BFD_RELOC_M32R_RELATIVE
4048 BFD_RELOC_M32R_GOTOFF
4050 BFD_RELOC_M32R_GOTOFF_HI_ULO
4052 BFD_RELOC_M32R_GOTOFF_HI_SLO
4054 BFD_RELOC_M32R_GOTOFF_LO
4056 BFD_RELOC_M32R_GOTPC24
4058 BFD_RELOC_M32R_GOT16_HI_ULO
4060 BFD_RELOC_M32R_GOT16_HI_SLO
4062 BFD_RELOC_M32R_GOT16_LO
4064 BFD_RELOC_M32R_GOTPC_HI_ULO
4066 BFD_RELOC_M32R_GOTPC_HI_SLO
4068 BFD_RELOC_M32R_GOTPC_LO
4077 This is a 20 bit absolute address.
4079 BFD_RELOC_NDS32_9_PCREL
4081 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4083 BFD_RELOC_NDS32_WORD_9_PCREL
4085 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4087 BFD_RELOC_NDS32_15_PCREL
4089 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4091 BFD_RELOC_NDS32_17_PCREL
4093 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4095 BFD_RELOC_NDS32_25_PCREL
4097 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4099 BFD_RELOC_NDS32_HI20
4101 This is a 20-bit reloc containing the high 20 bits of an address
4102 used with the lower 12 bits
4104 BFD_RELOC_NDS32_LO12S3
4106 This is a 12-bit reloc containing the lower 12 bits of an address
4107 then shift right by 3. This is used with ldi,sdi...
4109 BFD_RELOC_NDS32_LO12S2
4111 This is a 12-bit reloc containing the lower 12 bits of an address
4112 then shift left by 2. This is used with lwi,swi...
4114 BFD_RELOC_NDS32_LO12S1
4116 This is a 12-bit reloc containing the lower 12 bits of an address
4117 then shift left by 1. This is used with lhi,shi...
4119 BFD_RELOC_NDS32_LO12S0
4121 This is a 12-bit reloc containing the lower 12 bits of an address
4122 then shift left by 0. This is used with lbisbi...
4124 BFD_RELOC_NDS32_LO12S0_ORI
4126 This is a 12-bit reloc containing the lower 12 bits of an address
4127 then shift left by 0. This is only used with branch relaxations
4129 BFD_RELOC_NDS32_SDA15S3
4131 This is a 15-bit reloc containing the small data area 18-bit signed offset
4132 and shift left by 3 for use in ldi, sdi...
4134 BFD_RELOC_NDS32_SDA15S2
4136 This is a 15-bit reloc containing the small data area 17-bit signed offset
4137 and shift left by 2 for use in lwi, swi...
4139 BFD_RELOC_NDS32_SDA15S1
4141 This is a 15-bit reloc containing the small data area 16-bit signed offset
4142 and shift left by 1 for use in lhi, shi...
4144 BFD_RELOC_NDS32_SDA15S0
4146 This is a 15-bit reloc containing the small data area 15-bit signed offset
4147 and shift left by 0 for use in lbi, sbi...
4149 BFD_RELOC_NDS32_SDA16S3
4151 This is a 16-bit reloc containing the small data area 16-bit signed offset
4154 BFD_RELOC_NDS32_SDA17S2
4156 This is a 17-bit reloc containing the small data area 17-bit signed offset
4157 and shift left by 2 for use in lwi.gp, swi.gp...
4159 BFD_RELOC_NDS32_SDA18S1
4161 This is a 18-bit reloc containing the small data area 18-bit signed offset
4162 and shift left by 1 for use in lhi.gp, shi.gp...
4164 BFD_RELOC_NDS32_SDA19S0
4166 This is a 19-bit reloc containing the small data area 19-bit signed offset
4167 and shift left by 0 for use in lbi.gp, sbi.gp...
4169 BFD_RELOC_NDS32_GOT20
4171 BFD_RELOC_NDS32_9_PLTREL
4173 BFD_RELOC_NDS32_25_PLTREL
4175 BFD_RELOC_NDS32_COPY
4177 BFD_RELOC_NDS32_GLOB_DAT
4179 BFD_RELOC_NDS32_JMP_SLOT
4181 BFD_RELOC_NDS32_RELATIVE
4183 BFD_RELOC_NDS32_GOTOFF
4185 BFD_RELOC_NDS32_GOTOFF_HI20
4187 BFD_RELOC_NDS32_GOTOFF_LO12
4189 BFD_RELOC_NDS32_GOTPC20
4191 BFD_RELOC_NDS32_GOT_HI20
4193 BFD_RELOC_NDS32_GOT_LO12
4195 BFD_RELOC_NDS32_GOTPC_HI20
4197 BFD_RELOC_NDS32_GOTPC_LO12
4201 BFD_RELOC_NDS32_INSN16
4203 BFD_RELOC_NDS32_LABEL
4205 BFD_RELOC_NDS32_LONGCALL1
4207 BFD_RELOC_NDS32_LONGCALL2
4209 BFD_RELOC_NDS32_LONGCALL3
4211 BFD_RELOC_NDS32_LONGJUMP1
4213 BFD_RELOC_NDS32_LONGJUMP2
4215 BFD_RELOC_NDS32_LONGJUMP3
4217 BFD_RELOC_NDS32_LOADSTORE
4219 BFD_RELOC_NDS32_9_FIXED
4221 BFD_RELOC_NDS32_15_FIXED
4223 BFD_RELOC_NDS32_17_FIXED
4225 BFD_RELOC_NDS32_25_FIXED
4227 BFD_RELOC_NDS32_LONGCALL4
4229 BFD_RELOC_NDS32_LONGCALL5
4231 BFD_RELOC_NDS32_LONGCALL6
4233 BFD_RELOC_NDS32_LONGJUMP4
4235 BFD_RELOC_NDS32_LONGJUMP5
4237 BFD_RELOC_NDS32_LONGJUMP6
4239 BFD_RELOC_NDS32_LONGJUMP7
4243 BFD_RELOC_NDS32_PLTREL_HI20
4245 BFD_RELOC_NDS32_PLTREL_LO12
4247 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4249 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4253 BFD_RELOC_NDS32_SDA12S2_DP
4255 BFD_RELOC_NDS32_SDA12S2_SP
4257 BFD_RELOC_NDS32_LO12S2_DP
4259 BFD_RELOC_NDS32_LO12S2_SP
4263 BFD_RELOC_NDS32_DWARF2_OP1
4265 BFD_RELOC_NDS32_DWARF2_OP2
4267 BFD_RELOC_NDS32_DWARF2_LEB
4269 for dwarf2 debug_line.
4271 BFD_RELOC_NDS32_UPDATE_TA
4273 for eliminate 16-bit instructions
4275 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4277 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4279 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4281 BFD_RELOC_NDS32_GOT_LO15
4283 BFD_RELOC_NDS32_GOT_LO19
4285 BFD_RELOC_NDS32_GOTOFF_LO15
4287 BFD_RELOC_NDS32_GOTOFF_LO19
4289 BFD_RELOC_NDS32_GOT15S2
4291 BFD_RELOC_NDS32_GOT17S2
4293 for PIC object relaxation
4298 This is a 5 bit absolute address.
4300 BFD_RELOC_NDS32_10_UPCREL
4302 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4304 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4306 If fp were omitted, fp can used as another gp.
4308 BFD_RELOC_NDS32_RELAX_ENTRY
4310 BFD_RELOC_NDS32_GOT_SUFF
4312 BFD_RELOC_NDS32_GOTOFF_SUFF
4314 BFD_RELOC_NDS32_PLT_GOT_SUFF
4316 BFD_RELOC_NDS32_MULCALL_SUFF
4320 BFD_RELOC_NDS32_PTR_COUNT
4322 BFD_RELOC_NDS32_PTR_RESOLVED
4324 BFD_RELOC_NDS32_PLTBLOCK
4326 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4328 BFD_RELOC_NDS32_RELAX_REGION_END
4330 BFD_RELOC_NDS32_MINUEND
4332 BFD_RELOC_NDS32_SUBTRAHEND
4334 BFD_RELOC_NDS32_DIFF8
4336 BFD_RELOC_NDS32_DIFF16
4338 BFD_RELOC_NDS32_DIFF32
4340 BFD_RELOC_NDS32_DIFF_ULEB128
4342 BFD_RELOC_NDS32_EMPTY
4344 relaxation relative relocation types
4346 BFD_RELOC_NDS32_25_ABS
4348 This is a 25 bit absolute address.
4350 BFD_RELOC_NDS32_DATA
4352 BFD_RELOC_NDS32_TRAN
4354 BFD_RELOC_NDS32_17IFC_PCREL
4356 BFD_RELOC_NDS32_10IFCU_PCREL
4358 For ex9 and ifc using.
4360 BFD_RELOC_NDS32_TPOFF
4362 BFD_RELOC_NDS32_GOTTPOFF
4364 BFD_RELOC_NDS32_TLS_LE_HI20
4366 BFD_RELOC_NDS32_TLS_LE_LO12
4368 BFD_RELOC_NDS32_TLS_LE_20
4370 BFD_RELOC_NDS32_TLS_LE_15S0
4372 BFD_RELOC_NDS32_TLS_LE_15S1
4374 BFD_RELOC_NDS32_TLS_LE_15S2
4376 BFD_RELOC_NDS32_TLS_LE_ADD
4378 BFD_RELOC_NDS32_TLS_LE_LS
4380 BFD_RELOC_NDS32_TLS_IE_HI20
4382 BFD_RELOC_NDS32_TLS_IE_LO12
4384 BFD_RELOC_NDS32_TLS_IE_LO12S2
4386 BFD_RELOC_NDS32_TLS_IEGP_HI20
4388 BFD_RELOC_NDS32_TLS_IEGP_LO12
4390 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4392 BFD_RELOC_NDS32_TLS_IEGP_LW
4394 BFD_RELOC_NDS32_TLS_DESC
4396 BFD_RELOC_NDS32_TLS_DESC_HI20
4398 BFD_RELOC_NDS32_TLS_DESC_LO12
4400 BFD_RELOC_NDS32_TLS_DESC_20
4402 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4404 BFD_RELOC_NDS32_TLS_DESC_ADD
4406 BFD_RELOC_NDS32_TLS_DESC_FUNC
4408 BFD_RELOC_NDS32_TLS_DESC_CALL
4410 BFD_RELOC_NDS32_TLS_DESC_MEM
4412 BFD_RELOC_NDS32_REMOVE
4414 BFD_RELOC_NDS32_GROUP
4420 For floating load store relaxation.
4424 BFD_RELOC_V850_9_PCREL
4426 This is a 9-bit reloc
4428 BFD_RELOC_V850_22_PCREL
4430 This is a 22-bit reloc
4433 BFD_RELOC_V850_SDA_16_16_OFFSET
4435 This is a 16 bit offset from the short data area pointer.
4437 BFD_RELOC_V850_SDA_15_16_OFFSET
4439 This is a 16 bit offset (of which only 15 bits are used) from the
4440 short data area pointer.
4442 BFD_RELOC_V850_ZDA_16_16_OFFSET
4444 This is a 16 bit offset from the zero data area pointer.
4446 BFD_RELOC_V850_ZDA_15_16_OFFSET
4448 This is a 16 bit offset (of which only 15 bits are used) from the
4449 zero data area pointer.
4451 BFD_RELOC_V850_TDA_6_8_OFFSET
4453 This is an 8 bit offset (of which only 6 bits are used) from the
4454 tiny data area pointer.
4456 BFD_RELOC_V850_TDA_7_8_OFFSET
4458 This is an 8bit offset (of which only 7 bits are used) from the tiny
4461 BFD_RELOC_V850_TDA_7_7_OFFSET
4463 This is a 7 bit offset from the tiny data area pointer.
4465 BFD_RELOC_V850_TDA_16_16_OFFSET
4467 This is a 16 bit offset from the tiny data area pointer.
4470 BFD_RELOC_V850_TDA_4_5_OFFSET
4472 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4475 BFD_RELOC_V850_TDA_4_4_OFFSET
4477 This is a 4 bit offset from the tiny data area pointer.
4479 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4481 This is a 16 bit offset from the short data area pointer, with the
4482 bits placed non-contiguously in the instruction.
4484 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4486 This is a 16 bit offset from the zero data area pointer, with the
4487 bits placed non-contiguously in the instruction.
4489 BFD_RELOC_V850_CALLT_6_7_OFFSET
4491 This is a 6 bit offset from the call table base pointer.
4493 BFD_RELOC_V850_CALLT_16_16_OFFSET
4495 This is a 16 bit offset from the call table base pointer.
4497 BFD_RELOC_V850_LONGCALL
4499 Used for relaxing indirect function calls.
4501 BFD_RELOC_V850_LONGJUMP
4503 Used for relaxing indirect jumps.
4505 BFD_RELOC_V850_ALIGN
4507 Used to maintain alignment whilst relaxing.
4509 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4511 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4514 BFD_RELOC_V850_16_PCREL
4516 This is a 16-bit reloc.
4518 BFD_RELOC_V850_17_PCREL
4520 This is a 17-bit reloc.
4524 This is a 23-bit reloc.
4526 BFD_RELOC_V850_32_PCREL
4528 This is a 32-bit reloc.
4530 BFD_RELOC_V850_32_ABS
4532 This is a 32-bit reloc.
4534 BFD_RELOC_V850_16_SPLIT_OFFSET
4536 This is a 16-bit reloc.
4538 BFD_RELOC_V850_16_S1
4540 This is a 16-bit reloc.
4542 BFD_RELOC_V850_LO16_S1
4544 Low 16 bits. 16 bit shifted by 1.
4546 BFD_RELOC_V850_CALLT_15_16_OFFSET
4548 This is a 16 bit offset from the call table base pointer.
4550 BFD_RELOC_V850_32_GOTPCREL
4554 BFD_RELOC_V850_16_GOT
4558 BFD_RELOC_V850_32_GOT
4562 BFD_RELOC_V850_22_PLT_PCREL
4566 BFD_RELOC_V850_32_PLT_PCREL
4574 BFD_RELOC_V850_GLOB_DAT
4578 BFD_RELOC_V850_JMP_SLOT
4582 BFD_RELOC_V850_RELATIVE
4586 BFD_RELOC_V850_16_GOTOFF
4590 BFD_RELOC_V850_32_GOTOFF
4605 This is a 8bit DP reloc for the tms320c30, where the most
4606 significant 8 bits of a 24 bit word are placed into the least
4607 significant 8 bits of the opcode.
4610 BFD_RELOC_TIC54X_PARTLS7
4612 This is a 7bit reloc for the tms320c54x, where the least
4613 significant 7 bits of a 16 bit word are placed into the least
4614 significant 7 bits of the opcode.
4617 BFD_RELOC_TIC54X_PARTMS9
4619 This is a 9bit DP reloc for the tms320c54x, where the most
4620 significant 9 bits of a 16 bit word are placed into the least
4621 significant 9 bits of the opcode.
4626 This is an extended address 23-bit reloc for the tms320c54x.
4629 BFD_RELOC_TIC54X_16_OF_23
4631 This is a 16-bit reloc for the tms320c54x, where the least
4632 significant 16 bits of a 23-bit extended address are placed into
4636 BFD_RELOC_TIC54X_MS7_OF_23
4638 This is a reloc for the tms320c54x, where the most
4639 significant 7 bits of a 23-bit extended address are placed into
4643 BFD_RELOC_C6000_PCR_S21
4645 BFD_RELOC_C6000_PCR_S12
4647 BFD_RELOC_C6000_PCR_S10
4649 BFD_RELOC_C6000_PCR_S7
4651 BFD_RELOC_C6000_ABS_S16
4653 BFD_RELOC_C6000_ABS_L16
4655 BFD_RELOC_C6000_ABS_H16
4657 BFD_RELOC_C6000_SBR_U15_B
4659 BFD_RELOC_C6000_SBR_U15_H
4661 BFD_RELOC_C6000_SBR_U15_W
4663 BFD_RELOC_C6000_SBR_S16
4665 BFD_RELOC_C6000_SBR_L16_B
4667 BFD_RELOC_C6000_SBR_L16_H
4669 BFD_RELOC_C6000_SBR_L16_W
4671 BFD_RELOC_C6000_SBR_H16_B
4673 BFD_RELOC_C6000_SBR_H16_H
4675 BFD_RELOC_C6000_SBR_H16_W
4677 BFD_RELOC_C6000_SBR_GOT_U15_W
4679 BFD_RELOC_C6000_SBR_GOT_L16_W
4681 BFD_RELOC_C6000_SBR_GOT_H16_W
4683 BFD_RELOC_C6000_DSBT_INDEX
4685 BFD_RELOC_C6000_PREL31
4687 BFD_RELOC_C6000_COPY
4689 BFD_RELOC_C6000_JUMP_SLOT
4691 BFD_RELOC_C6000_EHTYPE
4693 BFD_RELOC_C6000_PCR_H16
4695 BFD_RELOC_C6000_PCR_L16
4697 BFD_RELOC_C6000_ALIGN
4699 BFD_RELOC_C6000_FPHEAD
4701 BFD_RELOC_C6000_NOCMP
4703 TMS320C6000 relocations.
4708 This is a 48 bit reloc for the FR30 that stores 32 bits.
4712 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4715 BFD_RELOC_FR30_6_IN_4
4717 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4720 BFD_RELOC_FR30_8_IN_8
4722 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4725 BFD_RELOC_FR30_9_IN_8
4727 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4730 BFD_RELOC_FR30_10_IN_8
4732 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4735 BFD_RELOC_FR30_9_PCREL
4737 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4738 short offset into 8 bits.
4740 BFD_RELOC_FR30_12_PCREL
4742 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4743 short offset into 11 bits.
4746 BFD_RELOC_MCORE_PCREL_IMM8BY4
4748 BFD_RELOC_MCORE_PCREL_IMM11BY2
4750 BFD_RELOC_MCORE_PCREL_IMM4BY2
4752 BFD_RELOC_MCORE_PCREL_32
4754 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4758 Motorola Mcore relocations.
4767 BFD_RELOC_MEP_PCREL8A2
4769 BFD_RELOC_MEP_PCREL12A2
4771 BFD_RELOC_MEP_PCREL17A2
4773 BFD_RELOC_MEP_PCREL24A2
4775 BFD_RELOC_MEP_PCABS24A2
4787 BFD_RELOC_MEP_TPREL7
4789 BFD_RELOC_MEP_TPREL7A2
4791 BFD_RELOC_MEP_TPREL7A4
4793 BFD_RELOC_MEP_UIMM24
4795 BFD_RELOC_MEP_ADDR24A4
4797 BFD_RELOC_MEP_GNU_VTINHERIT
4799 BFD_RELOC_MEP_GNU_VTENTRY
4801 Toshiba Media Processor Relocations.
4805 BFD_RELOC_METAG_HIADDR16
4807 BFD_RELOC_METAG_LOADDR16
4809 BFD_RELOC_METAG_RELBRANCH
4811 BFD_RELOC_METAG_GETSETOFF
4813 BFD_RELOC_METAG_HIOG
4815 BFD_RELOC_METAG_LOOG
4817 BFD_RELOC_METAG_REL8
4819 BFD_RELOC_METAG_REL16
4821 BFD_RELOC_METAG_HI16_GOTOFF
4823 BFD_RELOC_METAG_LO16_GOTOFF
4825 BFD_RELOC_METAG_GETSET_GOTOFF
4827 BFD_RELOC_METAG_GETSET_GOT
4829 BFD_RELOC_METAG_HI16_GOTPC
4831 BFD_RELOC_METAG_LO16_GOTPC
4833 BFD_RELOC_METAG_HI16_PLT
4835 BFD_RELOC_METAG_LO16_PLT
4837 BFD_RELOC_METAG_RELBRANCH_PLT
4839 BFD_RELOC_METAG_GOTOFF
4843 BFD_RELOC_METAG_COPY
4845 BFD_RELOC_METAG_JMP_SLOT
4847 BFD_RELOC_METAG_RELATIVE
4849 BFD_RELOC_METAG_GLOB_DAT
4851 BFD_RELOC_METAG_TLS_GD
4853 BFD_RELOC_METAG_TLS_LDM
4855 BFD_RELOC_METAG_TLS_LDO_HI16
4857 BFD_RELOC_METAG_TLS_LDO_LO16
4859 BFD_RELOC_METAG_TLS_LDO
4861 BFD_RELOC_METAG_TLS_IE
4863 BFD_RELOC_METAG_TLS_IENONPIC
4865 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4867 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4869 BFD_RELOC_METAG_TLS_TPOFF
4871 BFD_RELOC_METAG_TLS_DTPMOD
4873 BFD_RELOC_METAG_TLS_DTPOFF
4875 BFD_RELOC_METAG_TLS_LE
4877 BFD_RELOC_METAG_TLS_LE_HI16
4879 BFD_RELOC_METAG_TLS_LE_LO16
4881 Imagination Technologies Meta relocations.
4886 BFD_RELOC_MMIX_GETA_1
4888 BFD_RELOC_MMIX_GETA_2
4890 BFD_RELOC_MMIX_GETA_3
4892 These are relocations for the GETA instruction.
4894 BFD_RELOC_MMIX_CBRANCH
4896 BFD_RELOC_MMIX_CBRANCH_J
4898 BFD_RELOC_MMIX_CBRANCH_1
4900 BFD_RELOC_MMIX_CBRANCH_2
4902 BFD_RELOC_MMIX_CBRANCH_3
4904 These are relocations for a conditional branch instruction.
4906 BFD_RELOC_MMIX_PUSHJ
4908 BFD_RELOC_MMIX_PUSHJ_1
4910 BFD_RELOC_MMIX_PUSHJ_2
4912 BFD_RELOC_MMIX_PUSHJ_3
4914 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4916 These are relocations for the PUSHJ instruction.
4920 BFD_RELOC_MMIX_JMP_1
4922 BFD_RELOC_MMIX_JMP_2
4924 BFD_RELOC_MMIX_JMP_3
4926 These are relocations for the JMP instruction.
4928 BFD_RELOC_MMIX_ADDR19
4930 This is a relocation for a relative address as in a GETA instruction or
4933 BFD_RELOC_MMIX_ADDR27
4935 This is a relocation for a relative address as in a JMP instruction.
4937 BFD_RELOC_MMIX_REG_OR_BYTE
4939 This is a relocation for an instruction field that may be a general
4940 register or a value 0..255.
4944 This is a relocation for an instruction field that may be a general
4947 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4949 This is a relocation for two instruction fields holding a register and
4950 an offset, the equivalent of the relocation.
4952 BFD_RELOC_MMIX_LOCAL
4954 This relocation is an assertion that the expression is not allocated as
4955 a global register. It does not modify contents.
4958 BFD_RELOC_AVR_7_PCREL
4960 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4961 short offset into 7 bits.
4963 BFD_RELOC_AVR_13_PCREL
4965 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4966 short offset into 12 bits.
4970 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4971 program memory address) into 16 bits.
4973 BFD_RELOC_AVR_LO8_LDI
4975 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4976 data memory address) into 8 bit immediate value of LDI insn.
4978 BFD_RELOC_AVR_HI8_LDI
4980 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4981 of data memory address) into 8 bit immediate value of LDI insn.
4983 BFD_RELOC_AVR_HH8_LDI
4985 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4986 of program memory address) into 8 bit immediate value of LDI insn.
4988 BFD_RELOC_AVR_MS8_LDI
4990 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4991 of 32 bit value) into 8 bit immediate value of LDI insn.
4993 BFD_RELOC_AVR_LO8_LDI_NEG
4995 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4996 (usually data memory address) into 8 bit immediate value of SUBI insn.
4998 BFD_RELOC_AVR_HI8_LDI_NEG
5000 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5001 (high 8 bit of data memory address) into 8 bit immediate value of
5004 BFD_RELOC_AVR_HH8_LDI_NEG
5006 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5007 (most high 8 bit of program memory address) into 8 bit immediate value
5008 of LDI or SUBI insn.
5010 BFD_RELOC_AVR_MS8_LDI_NEG
5012 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5013 of 32 bit value) into 8 bit immediate value of LDI insn.
5015 BFD_RELOC_AVR_LO8_LDI_PM
5017 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5018 command address) into 8 bit immediate value of LDI insn.
5020 BFD_RELOC_AVR_LO8_LDI_GS
5022 This is a 16 bit reloc for the AVR that stores 8 bit value
5023 (command address) into 8 bit immediate value of LDI insn. If the address
5024 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5027 BFD_RELOC_AVR_HI8_LDI_PM
5029 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5030 of command address) into 8 bit immediate value of LDI insn.
5032 BFD_RELOC_AVR_HI8_LDI_GS
5034 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5035 of command address) into 8 bit immediate value of LDI insn. If the address
5036 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5039 BFD_RELOC_AVR_HH8_LDI_PM
5041 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5042 of command address) into 8 bit immediate value of LDI insn.
5044 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5046 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5047 (usually command address) into 8 bit immediate value of SUBI insn.
5049 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5051 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5052 (high 8 bit of 16 bit command address) into 8 bit immediate value
5055 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5057 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5058 (high 6 bit of 22 bit command address) into 8 bit immediate
5063 This is a 32 bit reloc for the AVR that stores 23 bit value
5068 This is a 16 bit reloc for the AVR that stores all needed bits
5069 for absolute addressing with ldi with overflow check to linktime
5073 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5076 BFD_RELOC_AVR_6_ADIW
5078 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5083 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5084 in .byte lo8(symbol)
5088 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5089 in .byte hi8(symbol)
5093 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5094 in .byte hlo8(symbol)
5098 BFD_RELOC_AVR_DIFF16
5100 BFD_RELOC_AVR_DIFF32
5102 AVR relocations to mark the difference of two local symbols.
5103 These are only needed to support linker relaxation and can be ignored
5104 when not relaxing. The field is set to the value of the difference
5105 assuming no relaxation. The relocation encodes the position of the
5106 second symbol so the linker can determine whether to adjust the field
5109 BFD_RELOC_AVR_LDS_STS_16
5111 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5112 lds and sts instructions supported only tiny core.
5116 This is a 6 bit reloc for the AVR that stores an I/O register
5117 number for the IN and OUT instructions
5121 This is a 5 bit reloc for the AVR that stores an I/O register
5122 number for the SBIC, SBIS, SBI and CBI instructions
5125 BFD_RELOC_RISCV_HI20
5127 BFD_RELOC_RISCV_PCREL_HI20
5129 BFD_RELOC_RISCV_PCREL_LO12_I
5131 BFD_RELOC_RISCV_PCREL_LO12_S
5133 BFD_RELOC_RISCV_LO12_I
5135 BFD_RELOC_RISCV_LO12_S
5137 BFD_RELOC_RISCV_GPREL12_I
5139 BFD_RELOC_RISCV_GPREL12_S
5141 BFD_RELOC_RISCV_TPREL_HI20
5143 BFD_RELOC_RISCV_TPREL_LO12_I
5145 BFD_RELOC_RISCV_TPREL_LO12_S
5147 BFD_RELOC_RISCV_TPREL_ADD
5149 BFD_RELOC_RISCV_CALL
5151 BFD_RELOC_RISCV_CALL_PLT
5153 BFD_RELOC_RISCV_ADD8
5155 BFD_RELOC_RISCV_ADD16
5157 BFD_RELOC_RISCV_ADD32
5159 BFD_RELOC_RISCV_ADD64
5161 BFD_RELOC_RISCV_SUB8
5163 BFD_RELOC_RISCV_SUB16
5165 BFD_RELOC_RISCV_SUB32
5167 BFD_RELOC_RISCV_SUB64
5169 BFD_RELOC_RISCV_GOT_HI20
5171 BFD_RELOC_RISCV_TLS_GOT_HI20
5173 BFD_RELOC_RISCV_TLS_GD_HI20
5177 BFD_RELOC_RISCV_TLS_DTPMOD32
5179 BFD_RELOC_RISCV_TLS_DTPREL32
5181 BFD_RELOC_RISCV_TLS_DTPMOD64
5183 BFD_RELOC_RISCV_TLS_DTPREL64
5185 BFD_RELOC_RISCV_TLS_TPREL32
5187 BFD_RELOC_RISCV_TLS_TPREL64
5189 BFD_RELOC_RISCV_ALIGN
5191 BFD_RELOC_RISCV_RVC_BRANCH
5193 BFD_RELOC_RISCV_RVC_JUMP
5195 BFD_RELOC_RISCV_RVC_LUI
5197 BFD_RELOC_RISCV_GPREL_I
5199 BFD_RELOC_RISCV_GPREL_S
5201 BFD_RELOC_RISCV_TPREL_I
5203 BFD_RELOC_RISCV_TPREL_S
5205 BFD_RELOC_RISCV_RELAX
5209 BFD_RELOC_RISCV_SUB6
5211 BFD_RELOC_RISCV_SET6
5213 BFD_RELOC_RISCV_SET8
5215 BFD_RELOC_RISCV_SET16
5217 BFD_RELOC_RISCV_SET32
5219 BFD_RELOC_RISCV_32_PCREL
5226 BFD_RELOC_RL78_NEG16
5228 BFD_RELOC_RL78_NEG24
5230 BFD_RELOC_RL78_NEG32
5232 BFD_RELOC_RL78_16_OP
5234 BFD_RELOC_RL78_24_OP
5236 BFD_RELOC_RL78_32_OP
5244 BFD_RELOC_RL78_DIR3U_PCREL
5248 BFD_RELOC_RL78_GPRELB
5250 BFD_RELOC_RL78_GPRELW
5252 BFD_RELOC_RL78_GPRELL
5256 BFD_RELOC_RL78_OP_SUBTRACT
5258 BFD_RELOC_RL78_OP_NEG
5260 BFD_RELOC_RL78_OP_AND
5262 BFD_RELOC_RL78_OP_SHRA
5266 BFD_RELOC_RL78_ABS16
5268 BFD_RELOC_RL78_ABS16_REV
5270 BFD_RELOC_RL78_ABS32
5272 BFD_RELOC_RL78_ABS32_REV
5274 BFD_RELOC_RL78_ABS16U
5276 BFD_RELOC_RL78_ABS16UW
5278 BFD_RELOC_RL78_ABS16UL
5280 BFD_RELOC_RL78_RELAX
5290 BFD_RELOC_RL78_SADDR
5292 Renesas RL78 Relocations.
5315 BFD_RELOC_RX_DIR3U_PCREL
5327 BFD_RELOC_RX_OP_SUBTRACT
5335 BFD_RELOC_RX_ABS16_REV
5339 BFD_RELOC_RX_ABS32_REV
5343 BFD_RELOC_RX_ABS16UW
5345 BFD_RELOC_RX_ABS16UL
5349 Renesas RX Relocations.
5362 32 bit PC relative PLT address.
5366 Copy symbol at runtime.
5368 BFD_RELOC_390_GLOB_DAT
5372 BFD_RELOC_390_JMP_SLOT
5376 BFD_RELOC_390_RELATIVE
5378 Adjust by program base.
5382 32 bit PC relative offset to GOT.
5388 BFD_RELOC_390_PC12DBL
5390 PC relative 12 bit shifted by 1.
5392 BFD_RELOC_390_PLT12DBL
5394 12 bit PC rel. PLT shifted by 1.
5396 BFD_RELOC_390_PC16DBL
5398 PC relative 16 bit shifted by 1.
5400 BFD_RELOC_390_PLT16DBL
5402 16 bit PC rel. PLT shifted by 1.
5404 BFD_RELOC_390_PC24DBL
5406 PC relative 24 bit shifted by 1.
5408 BFD_RELOC_390_PLT24DBL
5410 24 bit PC rel. PLT shifted by 1.
5412 BFD_RELOC_390_PC32DBL
5414 PC relative 32 bit shifted by 1.
5416 BFD_RELOC_390_PLT32DBL
5418 32 bit PC rel. PLT shifted by 1.
5420 BFD_RELOC_390_GOTPCDBL
5422 32 bit PC rel. GOT shifted by 1.
5430 64 bit PC relative PLT address.
5432 BFD_RELOC_390_GOTENT
5434 32 bit rel. offset to GOT entry.
5436 BFD_RELOC_390_GOTOFF64
5438 64 bit offset to GOT.
5440 BFD_RELOC_390_GOTPLT12
5442 12-bit offset to symbol-entry within GOT, with PLT handling.
5444 BFD_RELOC_390_GOTPLT16
5446 16-bit offset to symbol-entry within GOT, with PLT handling.
5448 BFD_RELOC_390_GOTPLT32
5450 32-bit offset to symbol-entry within GOT, with PLT handling.
5452 BFD_RELOC_390_GOTPLT64
5454 64-bit offset to symbol-entry within GOT, with PLT handling.
5456 BFD_RELOC_390_GOTPLTENT
5458 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5460 BFD_RELOC_390_PLTOFF16
5462 16-bit rel. offset from the GOT to a PLT entry.
5464 BFD_RELOC_390_PLTOFF32
5466 32-bit rel. offset from the GOT to a PLT entry.
5468 BFD_RELOC_390_PLTOFF64
5470 64-bit rel. offset from the GOT to a PLT entry.
5473 BFD_RELOC_390_TLS_LOAD
5475 BFD_RELOC_390_TLS_GDCALL
5477 BFD_RELOC_390_TLS_LDCALL
5479 BFD_RELOC_390_TLS_GD32
5481 BFD_RELOC_390_TLS_GD64
5483 BFD_RELOC_390_TLS_GOTIE12
5485 BFD_RELOC_390_TLS_GOTIE32
5487 BFD_RELOC_390_TLS_GOTIE64
5489 BFD_RELOC_390_TLS_LDM32
5491 BFD_RELOC_390_TLS_LDM64
5493 BFD_RELOC_390_TLS_IE32
5495 BFD_RELOC_390_TLS_IE64
5497 BFD_RELOC_390_TLS_IEENT
5499 BFD_RELOC_390_TLS_LE32
5501 BFD_RELOC_390_TLS_LE64
5503 BFD_RELOC_390_TLS_LDO32
5505 BFD_RELOC_390_TLS_LDO64
5507 BFD_RELOC_390_TLS_DTPMOD
5509 BFD_RELOC_390_TLS_DTPOFF
5511 BFD_RELOC_390_TLS_TPOFF
5513 s390 tls relocations.
5520 BFD_RELOC_390_GOTPLT20
5522 BFD_RELOC_390_TLS_GOTIE20
5524 Long displacement extension.
5527 BFD_RELOC_390_IRELATIVE
5529 STT_GNU_IFUNC relocation.
5532 BFD_RELOC_SCORE_GPREL15
5535 Low 16 bit for load/store
5537 BFD_RELOC_SCORE_DUMMY2
5541 This is a 24-bit reloc with the right 1 bit assumed to be 0
5543 BFD_RELOC_SCORE_BRANCH
5545 This is a 19-bit reloc with the right 1 bit assumed to be 0
5547 BFD_RELOC_SCORE_IMM30
5549 This is a 32-bit reloc for 48-bit instructions.
5551 BFD_RELOC_SCORE_IMM32
5553 This is a 32-bit reloc for 48-bit instructions.
5555 BFD_RELOC_SCORE16_JMP
5557 This is a 11-bit reloc with the right 1 bit assumed to be 0
5559 BFD_RELOC_SCORE16_BRANCH
5561 This is a 8-bit reloc with the right 1 bit assumed to be 0
5563 BFD_RELOC_SCORE_BCMP
5565 This is a 9-bit reloc with the right 1 bit assumed to be 0
5567 BFD_RELOC_SCORE_GOT15
5569 BFD_RELOC_SCORE_GOT_LO16
5571 BFD_RELOC_SCORE_CALL15
5573 BFD_RELOC_SCORE_DUMMY_HI16
5575 Undocumented Score relocs
5580 Scenix IP2K - 9-bit register number / data address
5584 Scenix IP2K - 4-bit register/data bank number
5586 BFD_RELOC_IP2K_ADDR16CJP
5588 Scenix IP2K - low 13 bits of instruction word address
5590 BFD_RELOC_IP2K_PAGE3
5592 Scenix IP2K - high 3 bits of instruction word address
5594 BFD_RELOC_IP2K_LO8DATA
5596 BFD_RELOC_IP2K_HI8DATA
5598 BFD_RELOC_IP2K_EX8DATA
5600 Scenix IP2K - ext/low/high 8 bits of data address
5602 BFD_RELOC_IP2K_LO8INSN
5604 BFD_RELOC_IP2K_HI8INSN
5606 Scenix IP2K - low/high 8 bits of instruction word address
5608 BFD_RELOC_IP2K_PC_SKIP
5610 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5614 Scenix IP2K - 16 bit word address in text section.
5616 BFD_RELOC_IP2K_FR_OFFSET
5618 Scenix IP2K - 7-bit sp or dp offset
5620 BFD_RELOC_VPE4KMATH_DATA
5622 BFD_RELOC_VPE4KMATH_INSN
5624 Scenix VPE4K coprocessor - data/insn-space addressing
5627 BFD_RELOC_VTABLE_INHERIT
5629 BFD_RELOC_VTABLE_ENTRY
5631 These two relocations are used by the linker to determine which of
5632 the entries in a C++ virtual function table are actually used. When
5633 the --gc-sections option is given, the linker will zero out the entries
5634 that are not used, so that the code for those functions need not be
5635 included in the output.
5637 VTABLE_INHERIT is a zero-space relocation used to describe to the
5638 linker the inheritance tree of a C++ virtual function table. The
5639 relocation's symbol should be the parent class' vtable, and the
5640 relocation should be located at the child vtable.
5642 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5643 virtual function table entry. The reloc's symbol should refer to the
5644 table of the class mentioned in the code. Off of that base, an offset
5645 describes the entry that is being used. For Rela hosts, this offset
5646 is stored in the reloc's addend. For Rel hosts, we are forced to put
5647 this offset in the reloc's section offset.
5650 BFD_RELOC_IA64_IMM14
5652 BFD_RELOC_IA64_IMM22
5654 BFD_RELOC_IA64_IMM64
5656 BFD_RELOC_IA64_DIR32MSB
5658 BFD_RELOC_IA64_DIR32LSB
5660 BFD_RELOC_IA64_DIR64MSB
5662 BFD_RELOC_IA64_DIR64LSB
5664 BFD_RELOC_IA64_GPREL22
5666 BFD_RELOC_IA64_GPREL64I
5668 BFD_RELOC_IA64_GPREL32MSB
5670 BFD_RELOC_IA64_GPREL32LSB
5672 BFD_RELOC_IA64_GPREL64MSB
5674 BFD_RELOC_IA64_GPREL64LSB
5676 BFD_RELOC_IA64_LTOFF22
5678 BFD_RELOC_IA64_LTOFF64I
5680 BFD_RELOC_IA64_PLTOFF22
5682 BFD_RELOC_IA64_PLTOFF64I
5684 BFD_RELOC_IA64_PLTOFF64MSB
5686 BFD_RELOC_IA64_PLTOFF64LSB
5688 BFD_RELOC_IA64_FPTR64I
5690 BFD_RELOC_IA64_FPTR32MSB
5692 BFD_RELOC_IA64_FPTR32LSB
5694 BFD_RELOC_IA64_FPTR64MSB
5696 BFD_RELOC_IA64_FPTR64LSB
5698 BFD_RELOC_IA64_PCREL21B
5700 BFD_RELOC_IA64_PCREL21BI
5702 BFD_RELOC_IA64_PCREL21M
5704 BFD_RELOC_IA64_PCREL21F
5706 BFD_RELOC_IA64_PCREL22
5708 BFD_RELOC_IA64_PCREL60B
5710 BFD_RELOC_IA64_PCREL64I
5712 BFD_RELOC_IA64_PCREL32MSB
5714 BFD_RELOC_IA64_PCREL32LSB
5716 BFD_RELOC_IA64_PCREL64MSB
5718 BFD_RELOC_IA64_PCREL64LSB
5720 BFD_RELOC_IA64_LTOFF_FPTR22
5722 BFD_RELOC_IA64_LTOFF_FPTR64I
5724 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5726 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5728 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5730 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5732 BFD_RELOC_IA64_SEGREL32MSB
5734 BFD_RELOC_IA64_SEGREL32LSB
5736 BFD_RELOC_IA64_SEGREL64MSB
5738 BFD_RELOC_IA64_SEGREL64LSB
5740 BFD_RELOC_IA64_SECREL32MSB
5742 BFD_RELOC_IA64_SECREL32LSB
5744 BFD_RELOC_IA64_SECREL64MSB
5746 BFD_RELOC_IA64_SECREL64LSB
5748 BFD_RELOC_IA64_REL32MSB
5750 BFD_RELOC_IA64_REL32LSB
5752 BFD_RELOC_IA64_REL64MSB
5754 BFD_RELOC_IA64_REL64LSB
5756 BFD_RELOC_IA64_LTV32MSB
5758 BFD_RELOC_IA64_LTV32LSB
5760 BFD_RELOC_IA64_LTV64MSB
5762 BFD_RELOC_IA64_LTV64LSB
5764 BFD_RELOC_IA64_IPLTMSB
5766 BFD_RELOC_IA64_IPLTLSB
5770 BFD_RELOC_IA64_LTOFF22X
5772 BFD_RELOC_IA64_LDXMOV
5774 BFD_RELOC_IA64_TPREL14
5776 BFD_RELOC_IA64_TPREL22
5778 BFD_RELOC_IA64_TPREL64I
5780 BFD_RELOC_IA64_TPREL64MSB
5782 BFD_RELOC_IA64_TPREL64LSB
5784 BFD_RELOC_IA64_LTOFF_TPREL22
5786 BFD_RELOC_IA64_DTPMOD64MSB
5788 BFD_RELOC_IA64_DTPMOD64LSB
5790 BFD_RELOC_IA64_LTOFF_DTPMOD22
5792 BFD_RELOC_IA64_DTPREL14
5794 BFD_RELOC_IA64_DTPREL22
5796 BFD_RELOC_IA64_DTPREL64I
5798 BFD_RELOC_IA64_DTPREL32MSB
5800 BFD_RELOC_IA64_DTPREL32LSB
5802 BFD_RELOC_IA64_DTPREL64MSB
5804 BFD_RELOC_IA64_DTPREL64LSB
5806 BFD_RELOC_IA64_LTOFF_DTPREL22
5808 Intel IA64 Relocations.
5811 BFD_RELOC_M68HC11_HI8
5813 Motorola 68HC11 reloc.
5814 This is the 8 bit high part of an absolute address.
5816 BFD_RELOC_M68HC11_LO8
5818 Motorola 68HC11 reloc.
5819 This is the 8 bit low part of an absolute address.
5821 BFD_RELOC_M68HC11_3B
5823 Motorola 68HC11 reloc.
5824 This is the 3 bit of a value.
5826 BFD_RELOC_M68HC11_RL_JUMP
5828 Motorola 68HC11 reloc.
5829 This reloc marks the beginning of a jump/call instruction.
5830 It is used for linker relaxation to correctly identify beginning
5831 of instruction and change some branches to use PC-relative
5834 BFD_RELOC_M68HC11_RL_GROUP
5836 Motorola 68HC11 reloc.
5837 This reloc marks a group of several instructions that gcc generates
5838 and for which the linker relaxation pass can modify and/or remove
5841 BFD_RELOC_M68HC11_LO16
5843 Motorola 68HC11 reloc.
5844 This is the 16-bit lower part of an address. It is used for 'call'
5845 instruction to specify the symbol address without any special
5846 transformation (due to memory bank window).
5848 BFD_RELOC_M68HC11_PAGE
5850 Motorola 68HC11 reloc.
5851 This is a 8-bit reloc that specifies the page number of an address.
5852 It is used by 'call' instruction to specify the page number of
5855 BFD_RELOC_M68HC11_24
5857 Motorola 68HC11 reloc.
5858 This is a 24-bit reloc that represents the address with a 16-bit
5859 value and a 8-bit page number. The symbol address is transformed
5860 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5862 BFD_RELOC_M68HC12_5B
5864 Motorola 68HC12 reloc.
5865 This is the 5 bits of a value.
5867 BFD_RELOC_XGATE_RL_JUMP
5869 Freescale XGATE reloc.
5870 This reloc marks the beginning of a bra/jal instruction.
5872 BFD_RELOC_XGATE_RL_GROUP
5874 Freescale XGATE reloc.
5875 This reloc marks a group of several instructions that gcc generates
5876 and for which the linker relaxation pass can modify and/or remove
5879 BFD_RELOC_XGATE_LO16
5881 Freescale XGATE reloc.
5882 This is the 16-bit lower part of an address. It is used for the '16-bit'
5885 BFD_RELOC_XGATE_GPAGE
5887 Freescale XGATE reloc.
5891 Freescale XGATE reloc.
5893 BFD_RELOC_XGATE_PCREL_9
5895 Freescale XGATE reloc.
5896 This is a 9-bit pc-relative reloc.
5898 BFD_RELOC_XGATE_PCREL_10
5900 Freescale XGATE reloc.
5901 This is a 10-bit pc-relative reloc.
5903 BFD_RELOC_XGATE_IMM8_LO
5905 Freescale XGATE reloc.
5906 This is the 16-bit lower part of an address. It is used for the '16-bit'
5909 BFD_RELOC_XGATE_IMM8_HI
5911 Freescale XGATE reloc.
5912 This is the 16-bit higher part of an address. It is used for the '16-bit'
5915 BFD_RELOC_XGATE_IMM3
5917 Freescale XGATE reloc.
5918 This is a 3-bit pc-relative reloc.
5920 BFD_RELOC_XGATE_IMM4
5922 Freescale XGATE reloc.
5923 This is a 4-bit pc-relative reloc.
5925 BFD_RELOC_XGATE_IMM5
5927 Freescale XGATE reloc.
5928 This is a 5-bit pc-relative reloc.
5930 BFD_RELOC_M68HC12_9B
5932 Motorola 68HC12 reloc.
5933 This is the 9 bits of a value.
5935 BFD_RELOC_M68HC12_16B
5937 Motorola 68HC12 reloc.
5938 This is the 16 bits of a value.
5940 BFD_RELOC_M68HC12_9_PCREL
5942 Motorola 68HC12/XGATE reloc.
5943 This is a PCREL9 branch.
5945 BFD_RELOC_M68HC12_10_PCREL
5947 Motorola 68HC12/XGATE reloc.
5948 This is a PCREL10 branch.
5950 BFD_RELOC_M68HC12_LO8XG
5952 Motorola 68HC12/XGATE reloc.
5953 This is the 8 bit low part of an absolute address and immediately precedes
5954 a matching HI8XG part.
5956 BFD_RELOC_M68HC12_HI8XG
5958 Motorola 68HC12/XGATE reloc.
5959 This is the 8 bit high part of an absolute address and immediately follows
5960 a matching LO8XG part.
5962 BFD_RELOC_S12Z_15_PCREL
5964 Freescale S12Z reloc.
5965 This is a 15 bit relative address. If the most significant bits are all zero
5966 then it may be truncated to 8 bits.
5971 BFD_RELOC_CR16_NUM16
5973 BFD_RELOC_CR16_NUM32
5975 BFD_RELOC_CR16_NUM32a
5977 BFD_RELOC_CR16_REGREL0
5979 BFD_RELOC_CR16_REGREL4
5981 BFD_RELOC_CR16_REGREL4a
5983 BFD_RELOC_CR16_REGREL14
5985 BFD_RELOC_CR16_REGREL14a
5987 BFD_RELOC_CR16_REGREL16
5989 BFD_RELOC_CR16_REGREL20
5991 BFD_RELOC_CR16_REGREL20a
5993 BFD_RELOC_CR16_ABS20
5995 BFD_RELOC_CR16_ABS24
6001 BFD_RELOC_CR16_IMM16
6003 BFD_RELOC_CR16_IMM20
6005 BFD_RELOC_CR16_IMM24
6007 BFD_RELOC_CR16_IMM32
6009 BFD_RELOC_CR16_IMM32a
6011 BFD_RELOC_CR16_DISP4
6013 BFD_RELOC_CR16_DISP8
6015 BFD_RELOC_CR16_DISP16
6017 BFD_RELOC_CR16_DISP20
6019 BFD_RELOC_CR16_DISP24
6021 BFD_RELOC_CR16_DISP24a
6023 BFD_RELOC_CR16_SWITCH8
6025 BFD_RELOC_CR16_SWITCH16
6027 BFD_RELOC_CR16_SWITCH32
6029 BFD_RELOC_CR16_GOT_REGREL20
6031 BFD_RELOC_CR16_GOTC_REGREL20
6033 BFD_RELOC_CR16_GLOB_DAT
6035 NS CR16 Relocations.
6042 BFD_RELOC_CRX_REL8_CMP
6050 BFD_RELOC_CRX_REGREL12
6052 BFD_RELOC_CRX_REGREL22
6054 BFD_RELOC_CRX_REGREL28
6056 BFD_RELOC_CRX_REGREL32
6072 BFD_RELOC_CRX_SWITCH8
6074 BFD_RELOC_CRX_SWITCH16
6076 BFD_RELOC_CRX_SWITCH32
6081 BFD_RELOC_CRIS_BDISP8
6083 BFD_RELOC_CRIS_UNSIGNED_5
6085 BFD_RELOC_CRIS_SIGNED_6
6087 BFD_RELOC_CRIS_UNSIGNED_6
6089 BFD_RELOC_CRIS_SIGNED_8
6091 BFD_RELOC_CRIS_UNSIGNED_8
6093 BFD_RELOC_CRIS_SIGNED_16
6095 BFD_RELOC_CRIS_UNSIGNED_16
6097 BFD_RELOC_CRIS_LAPCQ_OFFSET
6099 BFD_RELOC_CRIS_UNSIGNED_4
6101 These relocs are only used within the CRIS assembler. They are not
6102 (at present) written to any object files.
6106 BFD_RELOC_CRIS_GLOB_DAT
6108 BFD_RELOC_CRIS_JUMP_SLOT
6110 BFD_RELOC_CRIS_RELATIVE
6112 Relocs used in ELF shared libraries for CRIS.
6114 BFD_RELOC_CRIS_32_GOT
6116 32-bit offset to symbol-entry within GOT.
6118 BFD_RELOC_CRIS_16_GOT
6120 16-bit offset to symbol-entry within GOT.
6122 BFD_RELOC_CRIS_32_GOTPLT
6124 32-bit offset to symbol-entry within GOT, with PLT handling.
6126 BFD_RELOC_CRIS_16_GOTPLT
6128 16-bit offset to symbol-entry within GOT, with PLT handling.
6130 BFD_RELOC_CRIS_32_GOTREL
6132 32-bit offset to symbol, relative to GOT.
6134 BFD_RELOC_CRIS_32_PLT_GOTREL
6136 32-bit offset to symbol with PLT entry, relative to GOT.
6138 BFD_RELOC_CRIS_32_PLT_PCREL
6140 32-bit offset to symbol with PLT entry, relative to this relocation.
6143 BFD_RELOC_CRIS_32_GOT_GD
6145 BFD_RELOC_CRIS_16_GOT_GD
6147 BFD_RELOC_CRIS_32_GD
6151 BFD_RELOC_CRIS_32_DTPREL
6153 BFD_RELOC_CRIS_16_DTPREL
6155 BFD_RELOC_CRIS_32_GOT_TPREL
6157 BFD_RELOC_CRIS_16_GOT_TPREL
6159 BFD_RELOC_CRIS_32_TPREL
6161 BFD_RELOC_CRIS_16_TPREL
6163 BFD_RELOC_CRIS_DTPMOD
6165 BFD_RELOC_CRIS_32_IE
6167 Relocs used in TLS code for CRIS.
6170 BFD_RELOC_OR1K_REL_26
6172 BFD_RELOC_OR1K_SLO16
6174 BFD_RELOC_OR1K_PCREL_PG21
6178 BFD_RELOC_OR1K_SLO13
6180 BFD_RELOC_OR1K_GOTPC_HI16
6182 BFD_RELOC_OR1K_GOTPC_LO16
6184 BFD_RELOC_OR1K_GOT16
6186 BFD_RELOC_OR1K_GOT_PG21
6188 BFD_RELOC_OR1K_GOT_LO13
6190 BFD_RELOC_OR1K_PLT26
6192 BFD_RELOC_OR1K_PLTA26
6194 BFD_RELOC_OR1K_GOTOFF_SLO16
6198 BFD_RELOC_OR1K_GLOB_DAT
6200 BFD_RELOC_OR1K_JMP_SLOT
6202 BFD_RELOC_OR1K_RELATIVE
6204 BFD_RELOC_OR1K_TLS_GD_HI16
6206 BFD_RELOC_OR1K_TLS_GD_LO16
6208 BFD_RELOC_OR1K_TLS_GD_PG21
6210 BFD_RELOC_OR1K_TLS_GD_LO13
6212 BFD_RELOC_OR1K_TLS_LDM_HI16
6214 BFD_RELOC_OR1K_TLS_LDM_LO16
6216 BFD_RELOC_OR1K_TLS_LDM_PG21
6218 BFD_RELOC_OR1K_TLS_LDM_LO13
6220 BFD_RELOC_OR1K_TLS_LDO_HI16
6222 BFD_RELOC_OR1K_TLS_LDO_LO16
6224 BFD_RELOC_OR1K_TLS_IE_HI16
6226 BFD_RELOC_OR1K_TLS_IE_AHI16
6228 BFD_RELOC_OR1K_TLS_IE_LO16
6230 BFD_RELOC_OR1K_TLS_IE_PG21
6232 BFD_RELOC_OR1K_TLS_IE_LO13
6234 BFD_RELOC_OR1K_TLS_LE_HI16
6236 BFD_RELOC_OR1K_TLS_LE_AHI16
6238 BFD_RELOC_OR1K_TLS_LE_LO16
6240 BFD_RELOC_OR1K_TLS_LE_SLO16
6242 BFD_RELOC_OR1K_TLS_TPOFF
6244 BFD_RELOC_OR1K_TLS_DTPOFF
6246 BFD_RELOC_OR1K_TLS_DTPMOD
6248 OpenRISC 1000 Relocations.
6251 BFD_RELOC_H8_DIR16A8
6253 BFD_RELOC_H8_DIR16R8
6255 BFD_RELOC_H8_DIR24A8
6257 BFD_RELOC_H8_DIR24R8
6259 BFD_RELOC_H8_DIR32A16
6261 BFD_RELOC_H8_DISP32A16
6266 BFD_RELOC_XSTORMY16_REL_12
6268 BFD_RELOC_XSTORMY16_12
6270 BFD_RELOC_XSTORMY16_24
6272 BFD_RELOC_XSTORMY16_FPTR16
6274 Sony Xstormy16 Relocations.
6279 Self-describing complex relocations.
6291 Infineon Relocations.
6294 BFD_RELOC_VAX_GLOB_DAT
6296 BFD_RELOC_VAX_JMP_SLOT
6298 BFD_RELOC_VAX_RELATIVE
6300 Relocations used by VAX ELF.
6305 Morpho MT - 16 bit immediate relocation.
6309 Morpho MT - Hi 16 bits of an address.
6313 Morpho MT - Low 16 bits of an address.
6315 BFD_RELOC_MT_GNU_VTINHERIT
6317 Morpho MT - Used to tell the linker which vtable entries are used.
6319 BFD_RELOC_MT_GNU_VTENTRY
6321 Morpho MT - Used to tell the linker which vtable entries are used.
6323 BFD_RELOC_MT_PCINSN8
6325 Morpho MT - 8 bit immediate relocation.
6328 BFD_RELOC_MSP430_10_PCREL
6330 BFD_RELOC_MSP430_16_PCREL
6334 BFD_RELOC_MSP430_16_PCREL_BYTE
6336 BFD_RELOC_MSP430_16_BYTE
6338 BFD_RELOC_MSP430_2X_PCREL
6340 BFD_RELOC_MSP430_RL_PCREL
6342 BFD_RELOC_MSP430_ABS8
6344 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6346 BFD_RELOC_MSP430X_PCR20_EXT_DST
6348 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6350 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6352 BFD_RELOC_MSP430X_ABS20_EXT_DST
6354 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6356 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6358 BFD_RELOC_MSP430X_ABS20_ADR_DST
6360 BFD_RELOC_MSP430X_PCR16
6362 BFD_RELOC_MSP430X_PCR20_CALL
6364 BFD_RELOC_MSP430X_ABS16
6366 BFD_RELOC_MSP430_ABS_HI16
6368 BFD_RELOC_MSP430_PREL31
6370 BFD_RELOC_MSP430_SYM_DIFF
6372 BFD_RELOC_MSP430_SET_ULEB128
6374 BFD_RELOC_MSP430_SUB_ULEB128
6377 msp430 specific relocation codes
6384 BFD_RELOC_NIOS2_CALL26
6386 BFD_RELOC_NIOS2_IMM5
6388 BFD_RELOC_NIOS2_CACHE_OPX
6390 BFD_RELOC_NIOS2_IMM6
6392 BFD_RELOC_NIOS2_IMM8
6394 BFD_RELOC_NIOS2_HI16
6396 BFD_RELOC_NIOS2_LO16
6398 BFD_RELOC_NIOS2_HIADJ16
6400 BFD_RELOC_NIOS2_GPREL
6402 BFD_RELOC_NIOS2_UJMP
6404 BFD_RELOC_NIOS2_CJMP
6406 BFD_RELOC_NIOS2_CALLR
6408 BFD_RELOC_NIOS2_ALIGN
6410 BFD_RELOC_NIOS2_GOT16
6412 BFD_RELOC_NIOS2_CALL16
6414 BFD_RELOC_NIOS2_GOTOFF_LO
6416 BFD_RELOC_NIOS2_GOTOFF_HA
6418 BFD_RELOC_NIOS2_PCREL_LO
6420 BFD_RELOC_NIOS2_PCREL_HA
6422 BFD_RELOC_NIOS2_TLS_GD16
6424 BFD_RELOC_NIOS2_TLS_LDM16
6426 BFD_RELOC_NIOS2_TLS_LDO16
6428 BFD_RELOC_NIOS2_TLS_IE16
6430 BFD_RELOC_NIOS2_TLS_LE16
6432 BFD_RELOC_NIOS2_TLS_DTPMOD
6434 BFD_RELOC_NIOS2_TLS_DTPREL
6436 BFD_RELOC_NIOS2_TLS_TPREL
6438 BFD_RELOC_NIOS2_COPY
6440 BFD_RELOC_NIOS2_GLOB_DAT
6442 BFD_RELOC_NIOS2_JUMP_SLOT
6444 BFD_RELOC_NIOS2_RELATIVE
6446 BFD_RELOC_NIOS2_GOTOFF
6448 BFD_RELOC_NIOS2_CALL26_NOAT
6450 BFD_RELOC_NIOS2_GOT_LO
6452 BFD_RELOC_NIOS2_GOT_HA
6454 BFD_RELOC_NIOS2_CALL_LO
6456 BFD_RELOC_NIOS2_CALL_HA
6458 BFD_RELOC_NIOS2_R2_S12
6460 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6462 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6464 BFD_RELOC_NIOS2_R2_T1I7_2
6466 BFD_RELOC_NIOS2_R2_T2I4
6468 BFD_RELOC_NIOS2_R2_T2I4_1
6470 BFD_RELOC_NIOS2_R2_T2I4_2
6472 BFD_RELOC_NIOS2_R2_X1I7_2
6474 BFD_RELOC_NIOS2_R2_X2L5
6476 BFD_RELOC_NIOS2_R2_F1I5_2
6478 BFD_RELOC_NIOS2_R2_L5I4X1
6480 BFD_RELOC_NIOS2_R2_T1X1I6
6482 BFD_RELOC_NIOS2_R2_T1X1I6_2
6484 Relocations used by the Altera Nios II core.
6489 PRU LDI 16-bit unsigned data-memory relocation.
6491 BFD_RELOC_PRU_U16_PMEMIMM
6493 PRU LDI 16-bit unsigned instruction-memory relocation.
6497 PRU relocation for two consecutive LDI load instructions that load a
6498 32 bit value into a register. If the higher bits are all zero, then
6499 the second instruction may be relaxed.
6501 BFD_RELOC_PRU_S10_PCREL
6503 PRU QBBx 10-bit signed PC-relative relocation.
6505 BFD_RELOC_PRU_U8_PCREL
6507 PRU 8-bit unsigned relocation used for the LOOP instruction.
6509 BFD_RELOC_PRU_32_PMEM
6511 BFD_RELOC_PRU_16_PMEM
6513 PRU Program Memory relocations. Used to convert from byte addressing to
6514 32-bit word addressing.
6516 BFD_RELOC_PRU_GNU_DIFF8
6518 BFD_RELOC_PRU_GNU_DIFF16
6520 BFD_RELOC_PRU_GNU_DIFF32
6522 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6524 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6526 PRU relocations to mark the difference of two local symbols.
6527 These are only needed to support linker relaxation and can be ignored
6528 when not relaxing. The field is set to the value of the difference
6529 assuming no relaxation. The relocation encodes the position of the
6530 second symbol so the linker can determine whether to adjust the field
6531 value. The PMEM variants encode the word difference, instead of byte
6532 difference between symbols.
6535 BFD_RELOC_IQ2000_OFFSET_16
6537 BFD_RELOC_IQ2000_OFFSET_21
6539 BFD_RELOC_IQ2000_UHI16
6544 BFD_RELOC_XTENSA_RTLD
6546 Special Xtensa relocation used only by PLT entries in ELF shared
6547 objects to indicate that the runtime linker should set the value
6548 to one of its own internal functions or data structures.
6550 BFD_RELOC_XTENSA_GLOB_DAT
6552 BFD_RELOC_XTENSA_JMP_SLOT
6554 BFD_RELOC_XTENSA_RELATIVE
6556 Xtensa relocations for ELF shared objects.
6558 BFD_RELOC_XTENSA_PLT
6560 Xtensa relocation used in ELF object files for symbols that may require
6561 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6563 BFD_RELOC_XTENSA_DIFF8
6565 BFD_RELOC_XTENSA_DIFF16
6567 BFD_RELOC_XTENSA_DIFF32
6569 Xtensa relocations for backward compatibility. These have been replaced
6570 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6571 Xtensa relocations to mark the difference of two local symbols.
6572 These are only needed to support linker relaxation and can be ignored
6573 when not relaxing. The field is set to the value of the difference
6574 assuming no relaxation. The relocation encodes the position of the
6575 first symbol so the linker can determine whether to adjust the field
6578 BFD_RELOC_XTENSA_SLOT0_OP
6580 BFD_RELOC_XTENSA_SLOT1_OP
6582 BFD_RELOC_XTENSA_SLOT2_OP
6584 BFD_RELOC_XTENSA_SLOT3_OP
6586 BFD_RELOC_XTENSA_SLOT4_OP
6588 BFD_RELOC_XTENSA_SLOT5_OP
6590 BFD_RELOC_XTENSA_SLOT6_OP
6592 BFD_RELOC_XTENSA_SLOT7_OP
6594 BFD_RELOC_XTENSA_SLOT8_OP
6596 BFD_RELOC_XTENSA_SLOT9_OP
6598 BFD_RELOC_XTENSA_SLOT10_OP
6600 BFD_RELOC_XTENSA_SLOT11_OP
6602 BFD_RELOC_XTENSA_SLOT12_OP
6604 BFD_RELOC_XTENSA_SLOT13_OP
6606 BFD_RELOC_XTENSA_SLOT14_OP
6608 Generic Xtensa relocations for instruction operands. Only the slot
6609 number is encoded in the relocation. The relocation applies to the
6610 last PC-relative immediate operand, or if there are no PC-relative
6611 immediates, to the last immediate operand.
6613 BFD_RELOC_XTENSA_SLOT0_ALT
6615 BFD_RELOC_XTENSA_SLOT1_ALT
6617 BFD_RELOC_XTENSA_SLOT2_ALT
6619 BFD_RELOC_XTENSA_SLOT3_ALT
6621 BFD_RELOC_XTENSA_SLOT4_ALT
6623 BFD_RELOC_XTENSA_SLOT5_ALT
6625 BFD_RELOC_XTENSA_SLOT6_ALT
6627 BFD_RELOC_XTENSA_SLOT7_ALT
6629 BFD_RELOC_XTENSA_SLOT8_ALT
6631 BFD_RELOC_XTENSA_SLOT9_ALT
6633 BFD_RELOC_XTENSA_SLOT10_ALT
6635 BFD_RELOC_XTENSA_SLOT11_ALT
6637 BFD_RELOC_XTENSA_SLOT12_ALT
6639 BFD_RELOC_XTENSA_SLOT13_ALT
6641 BFD_RELOC_XTENSA_SLOT14_ALT
6643 Alternate Xtensa relocations. Only the slot is encoded in the
6644 relocation. The meaning of these relocations is opcode-specific.
6646 BFD_RELOC_XTENSA_OP0
6648 BFD_RELOC_XTENSA_OP1
6650 BFD_RELOC_XTENSA_OP2
6652 Xtensa relocations for backward compatibility. These have all been
6653 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6655 BFD_RELOC_XTENSA_ASM_EXPAND
6657 Xtensa relocation to mark that the assembler expanded the
6658 instructions from an original target. The expansion size is
6659 encoded in the reloc size.
6661 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6663 Xtensa relocation to mark that the linker should simplify
6664 assembler-expanded instructions. This is commonly used
6665 internally by the linker after analysis of a
6666 BFD_RELOC_XTENSA_ASM_EXPAND.
6668 BFD_RELOC_XTENSA_TLSDESC_FN
6670 BFD_RELOC_XTENSA_TLSDESC_ARG
6672 BFD_RELOC_XTENSA_TLS_DTPOFF
6674 BFD_RELOC_XTENSA_TLS_TPOFF
6676 BFD_RELOC_XTENSA_TLS_FUNC
6678 BFD_RELOC_XTENSA_TLS_ARG
6680 BFD_RELOC_XTENSA_TLS_CALL
6682 Xtensa TLS relocations.
6684 BFD_RELOC_XTENSA_PDIFF8
6686 BFD_RELOC_XTENSA_PDIFF16
6688 BFD_RELOC_XTENSA_PDIFF32
6690 BFD_RELOC_XTENSA_NDIFF8
6692 BFD_RELOC_XTENSA_NDIFF16
6694 BFD_RELOC_XTENSA_NDIFF32
6696 Xtensa relocations to mark the difference of two local symbols.
6697 These are only needed to support linker relaxation and can be ignored
6698 when not relaxing. The field is set to the value of the difference
6699 assuming no relaxation. The relocation encodes the position of the
6700 subtracted symbol so the linker can determine whether to adjust the field
6701 value. PDIFF relocations are used for positive differences, NDIFF
6702 relocations are used for negative differences. The difference value
6703 is treated as unsigned with these relocation types, giving full
6709 8 bit signed offset in (ix+d) or (iy+d).
6713 First 8 bits of multibyte (32, 24 or 16 bit) value.
6717 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6721 Third 8 bits of multibyte (32 or 24 bit) value.
6725 Fourth 8 bits of multibyte (32 bit) value.
6729 Lowest 16 bits of multibyte (32 or 24 bit) value.
6733 Highest 16 bits of multibyte (32 or 24 bit) value.
6737 Like BFD_RELOC_16 but big-endian.
6755 BFD_RELOC_LM32_BRANCH
6757 BFD_RELOC_LM32_16_GOT
6759 BFD_RELOC_LM32_GOTOFF_HI16
6761 BFD_RELOC_LM32_GOTOFF_LO16
6765 BFD_RELOC_LM32_GLOB_DAT
6767 BFD_RELOC_LM32_JMP_SLOT
6769 BFD_RELOC_LM32_RELATIVE
6771 Lattice Mico32 relocations.
6774 BFD_RELOC_MACH_O_SECTDIFF
6776 Difference between two section addreses. Must be followed by a
6777 BFD_RELOC_MACH_O_PAIR.
6779 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6781 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6783 BFD_RELOC_MACH_O_PAIR
6785 Pair of relocation. Contains the first symbol.
6787 BFD_RELOC_MACH_O_SUBTRACTOR32
6789 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6791 BFD_RELOC_MACH_O_SUBTRACTOR64
6793 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6796 BFD_RELOC_MACH_O_X86_64_BRANCH32
6798 BFD_RELOC_MACH_O_X86_64_BRANCH8
6800 PCREL relocations. They are marked as branch to create PLT entry if
6803 BFD_RELOC_MACH_O_X86_64_GOT
6805 Used when referencing a GOT entry.
6807 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6809 Used when loading a GOT entry with movq. It is specially marked so that
6810 the linker could optimize the movq to a leaq if possible.
6812 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6814 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6816 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6818 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6820 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6822 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6824 BFD_RELOC_MACH_O_X86_64_TLV
6826 Used when referencing a TLV entry.
6830 BFD_RELOC_MACH_O_ARM64_ADDEND
6832 Addend for PAGE or PAGEOFF.
6834 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6836 Relative offset to page of GOT slot.
6838 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6840 Relative offset within page of GOT slot.
6842 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6844 Address of a GOT entry.
6847 BFD_RELOC_MICROBLAZE_32_LO
6849 This is a 32 bit reloc for the microblaze that stores the
6850 low 16 bits of a value
6852 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6854 This is a 32 bit pc-relative reloc for the microblaze that
6855 stores the low 16 bits of a value
6857 BFD_RELOC_MICROBLAZE_32_ROSDA
6859 This is a 32 bit reloc for the microblaze that stores a
6860 value relative to the read-only small data area anchor
6862 BFD_RELOC_MICROBLAZE_32_RWSDA
6864 This is a 32 bit reloc for the microblaze that stores a
6865 value relative to the read-write small data area anchor
6867 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6869 This is a 32 bit reloc for the microblaze to handle
6870 expressions of the form "Symbol Op Symbol"
6872 BFD_RELOC_MICROBLAZE_64_NONE
6874 This is a 64 bit reloc that stores the 32 bit pc relative
6875 value in two words (with an imm instruction). No relocation is
6876 done here - only used for relaxing
6878 BFD_RELOC_MICROBLAZE_64_GOTPC
6880 This is a 64 bit reloc that stores the 32 bit pc relative
6881 value in two words (with an imm instruction). The relocation is
6882 PC-relative GOT offset
6884 BFD_RELOC_MICROBLAZE_64_GOT
6886 This is a 64 bit reloc that stores the 32 bit pc relative
6887 value in two words (with an imm instruction). The relocation is
6890 BFD_RELOC_MICROBLAZE_64_PLT
6892 This is a 64 bit reloc that stores the 32 bit pc relative
6893 value in two words (with an imm instruction). The relocation is
6894 PC-relative offset into PLT
6896 BFD_RELOC_MICROBLAZE_64_GOTOFF
6898 This is a 64 bit reloc that stores the 32 bit GOT relative
6899 value in two words (with an imm instruction). The relocation is
6900 relative offset from _GLOBAL_OFFSET_TABLE_
6902 BFD_RELOC_MICROBLAZE_32_GOTOFF
6904 This is a 32 bit reloc that stores the 32 bit GOT relative
6905 value in a word. The relocation is relative offset from
6906 _GLOBAL_OFFSET_TABLE_
6908 BFD_RELOC_MICROBLAZE_COPY
6910 This is used to tell the dynamic linker to copy the value out of
6911 the dynamic object into the runtime process image.
6913 BFD_RELOC_MICROBLAZE_64_TLS
6917 BFD_RELOC_MICROBLAZE_64_TLSGD
6919 This is a 64 bit reloc that stores the 32 bit GOT relative value
6920 of the GOT TLS GD info entry in two words (with an imm instruction). The
6921 relocation is GOT offset.
6923 BFD_RELOC_MICROBLAZE_64_TLSLD
6925 This is a 64 bit reloc that stores the 32 bit GOT relative value
6926 of the GOT TLS LD info entry in two words (with an imm instruction). The
6927 relocation is GOT offset.
6929 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6931 This is a 32 bit reloc that stores the Module ID to GOT(n).
6933 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6935 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6937 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6939 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6942 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6944 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6945 to two words (uses imm instruction).
6947 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6949 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6950 to two words (uses imm instruction).
6952 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6954 This is a 64 bit reloc that stores the 32 bit pc relative
6955 value in two words (with an imm instruction). The relocation is
6956 PC-relative offset from start of TEXT.
6958 BFD_RELOC_MICROBLAZE_64_TEXTREL
6960 This is a 64 bit reloc that stores the 32 bit offset
6961 value in two words (with an imm instruction). The relocation is
6962 relative offset from start of TEXT.
6965 BFD_RELOC_AARCH64_RELOC_START
6967 AArch64 pseudo relocation code to mark the start of the AArch64
6968 relocation enumerators. N.B. the order of the enumerators is
6969 important as several tables in the AArch64 bfd backend are indexed
6970 by these enumerators; make sure they are all synced.
6972 BFD_RELOC_AARCH64_NULL
6974 Deprecated AArch64 null relocation code.
6976 BFD_RELOC_AARCH64_NONE
6978 AArch64 null relocation code.
6980 BFD_RELOC_AARCH64_64
6982 BFD_RELOC_AARCH64_32
6984 BFD_RELOC_AARCH64_16
6986 Basic absolute relocations of N bits. These are equivalent to
6987 BFD_RELOC_N and they were added to assist the indexing of the howto
6990 BFD_RELOC_AARCH64_64_PCREL
6992 BFD_RELOC_AARCH64_32_PCREL
6994 BFD_RELOC_AARCH64_16_PCREL
6996 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6997 and they were added to assist the indexing of the howto table.
6999 BFD_RELOC_AARCH64_MOVW_G0
7001 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7002 of an unsigned address/value.
7004 BFD_RELOC_AARCH64_MOVW_G0_NC
7006 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7007 an address/value. No overflow checking.
7009 BFD_RELOC_AARCH64_MOVW_G1
7011 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7012 of an unsigned address/value.
7014 BFD_RELOC_AARCH64_MOVW_G1_NC
7016 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7017 of an address/value. No overflow checking.
7019 BFD_RELOC_AARCH64_MOVW_G2
7021 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7022 of an unsigned address/value.
7024 BFD_RELOC_AARCH64_MOVW_G2_NC
7026 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7027 of an address/value. No overflow checking.
7029 BFD_RELOC_AARCH64_MOVW_G3
7031 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7032 of a signed or unsigned address/value.
7034 BFD_RELOC_AARCH64_MOVW_G0_S
7036 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7037 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7040 BFD_RELOC_AARCH64_MOVW_G1_S
7042 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7043 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7046 BFD_RELOC_AARCH64_MOVW_G2_S
7048 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7049 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7052 BFD_RELOC_AARCH64_MOVW_PREL_G0
7054 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7055 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7058 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7060 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7061 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7064 BFD_RELOC_AARCH64_MOVW_PREL_G1
7066 AArch64 MOVK instruction with most significant bits 16 to 31
7069 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7071 AArch64 MOVK instruction with most significant bits 16 to 31
7074 BFD_RELOC_AARCH64_MOVW_PREL_G2
7076 AArch64 MOVK instruction with most significant bits 32 to 47
7079 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7081 AArch64 MOVK instruction with most significant bits 32 to 47
7084 BFD_RELOC_AARCH64_MOVW_PREL_G3
7086 AArch64 MOVK instruction with most significant bits 47 to 63
7089 BFD_RELOC_AARCH64_LD_LO19_PCREL
7091 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7092 offset. The lowest two bits must be zero and are not stored in the
7093 instruction, giving a 21 bit signed byte offset.
7095 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7097 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7099 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7101 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7102 offset, giving a 4KB aligned page base address.
7104 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7106 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7107 offset, giving a 4KB aligned page base address, but with no overflow
7110 BFD_RELOC_AARCH64_ADD_LO12
7112 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7113 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7115 BFD_RELOC_AARCH64_LDST8_LO12
7117 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7118 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7120 BFD_RELOC_AARCH64_TSTBR14
7122 AArch64 14 bit pc-relative test bit and branch.
7123 The lowest two bits must be zero and are not stored in the instruction,
7124 giving a 16 bit signed byte offset.
7126 BFD_RELOC_AARCH64_BRANCH19
7128 AArch64 19 bit pc-relative conditional branch and compare & branch.
7129 The lowest two bits must be zero and are not stored in the instruction,
7130 giving a 21 bit signed byte offset.
7132 BFD_RELOC_AARCH64_JUMP26
7134 AArch64 26 bit pc-relative unconditional branch.
7135 The lowest two bits must be zero and are not stored in the instruction,
7136 giving a 28 bit signed byte offset.
7138 BFD_RELOC_AARCH64_CALL26
7140 AArch64 26 bit pc-relative unconditional branch and link.
7141 The lowest two bits must be zero and are not stored in the instruction,
7142 giving a 28 bit signed byte offset.
7144 BFD_RELOC_AARCH64_LDST16_LO12
7146 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7147 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7149 BFD_RELOC_AARCH64_LDST32_LO12
7151 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7152 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7154 BFD_RELOC_AARCH64_LDST64_LO12
7156 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7157 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7159 BFD_RELOC_AARCH64_LDST128_LO12
7161 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7162 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7164 BFD_RELOC_AARCH64_GOT_LD_PREL19
7166 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7167 offset of the global offset table entry for a symbol. The lowest two
7168 bits must be zero and are not stored in the instruction, giving a 21
7169 bit signed byte offset. This relocation type requires signed overflow
7172 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7174 Get to the page base of the global offset table entry for a symbol as
7175 part of an ADRP instruction using a 21 bit PC relative value.Used in
7176 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7178 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7180 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7181 the GOT entry for this symbol. Used in conjunction with
7182 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7184 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7186 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7187 the GOT entry for this symbol. Used in conjunction with
7188 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7190 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7192 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7193 for this symbol. Valid in LP64 ABI only.
7195 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7197 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7198 for this symbol. Valid in LP64 ABI only.
7200 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7202 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7203 the GOT entry for this symbol. Valid in LP64 ABI only.
7205 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7207 Scaled 14 bit byte offset to the page base of the global offset table.
7209 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7211 Scaled 15 bit byte offset to the page base of the global offset table.
7213 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7215 Get to the page base of the global offset table entry for a symbols
7216 tls_index structure as part of an adrp instruction using a 21 bit PC
7217 relative value. Used in conjunction with
7218 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7220 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7222 AArch64 TLS General Dynamic
7224 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7226 Unsigned 12 bit byte offset to global offset table entry for a symbols
7227 tls_index structure. Used in conjunction with
7228 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7230 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7232 AArch64 TLS General Dynamic relocation.
7234 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7236 AArch64 TLS General Dynamic relocation.
7238 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7240 AArch64 TLS INITIAL EXEC relocation.
7242 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7244 AArch64 TLS INITIAL EXEC relocation.
7246 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7248 AArch64 TLS INITIAL EXEC relocation.
7250 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7252 AArch64 TLS INITIAL EXEC relocation.
7254 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7256 AArch64 TLS INITIAL EXEC relocation.
7258 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7260 AArch64 TLS INITIAL EXEC relocation.
7262 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7264 bit[23:12] of byte offset to module TLS base address.
7266 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7268 Unsigned 12 bit byte offset to module TLS base address.
7270 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7272 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7274 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7276 Unsigned 12 bit byte offset to global offset table entry for a symbols
7277 tls_index structure. Used in conjunction with
7278 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7280 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7282 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7285 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7287 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7289 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7291 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7294 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7296 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7298 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7300 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7303 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7305 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7307 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7309 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7312 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7314 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7316 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7318 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7321 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7323 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7325 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7327 bit[15:0] of byte offset to module TLS base address.
7329 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7331 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7333 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7335 bit[31:16] of byte offset to module TLS base address.
7337 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7339 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7341 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7343 bit[47:32] of byte offset to module TLS base address.
7345 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7347 AArch64 TLS LOCAL EXEC relocation.
7349 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7351 AArch64 TLS LOCAL EXEC relocation.
7353 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7355 AArch64 TLS LOCAL EXEC relocation.
7357 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7359 AArch64 TLS LOCAL EXEC relocation.
7361 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7363 AArch64 TLS LOCAL EXEC relocation.
7365 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7367 AArch64 TLS LOCAL EXEC relocation.
7369 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7371 AArch64 TLS LOCAL EXEC relocation.
7373 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7375 AArch64 TLS LOCAL EXEC relocation.
7377 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7379 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7382 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7384 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7386 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7388 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7391 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7393 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7395 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7397 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7400 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7402 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7404 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7406 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7409 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7411 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7413 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7415 AArch64 TLS DESC relocation.
7417 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7419 AArch64 TLS DESC relocation.
7421 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7423 AArch64 TLS DESC relocation.
7425 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7427 AArch64 TLS DESC relocation.
7429 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7431 AArch64 TLS DESC relocation.
7433 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7435 AArch64 TLS DESC relocation.
7437 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7439 AArch64 TLS DESC relocation.
7441 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7443 AArch64 TLS DESC relocation.
7445 BFD_RELOC_AARCH64_TLSDESC_LDR
7447 AArch64 TLS DESC relocation.
7449 BFD_RELOC_AARCH64_TLSDESC_ADD
7451 AArch64 TLS DESC relocation.
7453 BFD_RELOC_AARCH64_TLSDESC_CALL
7455 AArch64 TLS DESC relocation.
7457 BFD_RELOC_AARCH64_COPY
7459 AArch64 TLS relocation.
7461 BFD_RELOC_AARCH64_GLOB_DAT
7463 AArch64 TLS relocation.
7465 BFD_RELOC_AARCH64_JUMP_SLOT
7467 AArch64 TLS relocation.
7469 BFD_RELOC_AARCH64_RELATIVE
7471 AArch64 TLS relocation.
7473 BFD_RELOC_AARCH64_TLS_DTPMOD
7475 AArch64 TLS relocation.
7477 BFD_RELOC_AARCH64_TLS_DTPREL
7479 AArch64 TLS relocation.
7481 BFD_RELOC_AARCH64_TLS_TPREL
7483 AArch64 TLS relocation.
7485 BFD_RELOC_AARCH64_TLSDESC
7487 AArch64 TLS relocation.
7489 BFD_RELOC_AARCH64_IRELATIVE
7491 AArch64 support for STT_GNU_IFUNC.
7493 BFD_RELOC_AARCH64_RELOC_END
7495 AArch64 pseudo relocation code to mark the end of the AArch64
7496 relocation enumerators that have direct mapping to ELF reloc codes.
7497 There are a few more enumerators after this one; those are mainly
7498 used by the AArch64 assembler for the internal fixup or to select
7499 one of the above enumerators.
7501 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7503 AArch64 pseudo relocation code to be used internally by the AArch64
7504 assembler and not (currently) written to any object files.
7506 BFD_RELOC_AARCH64_LDST_LO12
7508 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7509 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7511 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7513 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7514 used internally by the AArch64 assembler and not (currently) written to
7517 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7519 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7521 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7523 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7524 used internally by the AArch64 assembler and not (currently) written to
7527 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7529 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7531 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7533 AArch64 pseudo relocation code to be used internally by the AArch64
7534 assembler and not (currently) written to any object files.
7536 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7538 AArch64 pseudo relocation code to be used internally by the AArch64
7539 assembler and not (currently) written to any object files.
7541 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7543 AArch64 pseudo relocation code to be used internally by the AArch64
7544 assembler and not (currently) written to any object files.
7546 BFD_RELOC_TILEPRO_COPY
7548 BFD_RELOC_TILEPRO_GLOB_DAT
7550 BFD_RELOC_TILEPRO_JMP_SLOT
7552 BFD_RELOC_TILEPRO_RELATIVE
7554 BFD_RELOC_TILEPRO_BROFF_X1
7556 BFD_RELOC_TILEPRO_JOFFLONG_X1
7558 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7560 BFD_RELOC_TILEPRO_IMM8_X0
7562 BFD_RELOC_TILEPRO_IMM8_Y0
7564 BFD_RELOC_TILEPRO_IMM8_X1
7566 BFD_RELOC_TILEPRO_IMM8_Y1
7568 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7570 BFD_RELOC_TILEPRO_MT_IMM15_X1
7572 BFD_RELOC_TILEPRO_MF_IMM15_X1
7574 BFD_RELOC_TILEPRO_IMM16_X0
7576 BFD_RELOC_TILEPRO_IMM16_X1
7578 BFD_RELOC_TILEPRO_IMM16_X0_LO
7580 BFD_RELOC_TILEPRO_IMM16_X1_LO
7582 BFD_RELOC_TILEPRO_IMM16_X0_HI
7584 BFD_RELOC_TILEPRO_IMM16_X1_HI
7586 BFD_RELOC_TILEPRO_IMM16_X0_HA
7588 BFD_RELOC_TILEPRO_IMM16_X1_HA
7590 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7592 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7594 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7596 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7598 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7600 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7602 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7604 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7606 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7608 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7610 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7612 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7614 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7616 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7618 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7620 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7622 BFD_RELOC_TILEPRO_MMSTART_X0
7624 BFD_RELOC_TILEPRO_MMEND_X0
7626 BFD_RELOC_TILEPRO_MMSTART_X1
7628 BFD_RELOC_TILEPRO_MMEND_X1
7630 BFD_RELOC_TILEPRO_SHAMT_X0
7632 BFD_RELOC_TILEPRO_SHAMT_X1
7634 BFD_RELOC_TILEPRO_SHAMT_Y0
7636 BFD_RELOC_TILEPRO_SHAMT_Y1
7638 BFD_RELOC_TILEPRO_TLS_GD_CALL
7640 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7642 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7644 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7646 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7648 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7650 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7652 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7654 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7656 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7658 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7660 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7662 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7664 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7666 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7668 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7670 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7672 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7674 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7676 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7678 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7680 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7682 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7684 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7686 BFD_RELOC_TILEPRO_TLS_TPOFF32
7688 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7690 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7692 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7694 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7696 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7698 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7700 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7702 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7704 Tilera TILEPro Relocations.
7706 BFD_RELOC_TILEGX_HW0
7708 BFD_RELOC_TILEGX_HW1
7710 BFD_RELOC_TILEGX_HW2
7712 BFD_RELOC_TILEGX_HW3
7714 BFD_RELOC_TILEGX_HW0_LAST
7716 BFD_RELOC_TILEGX_HW1_LAST
7718 BFD_RELOC_TILEGX_HW2_LAST
7720 BFD_RELOC_TILEGX_COPY
7722 BFD_RELOC_TILEGX_GLOB_DAT
7724 BFD_RELOC_TILEGX_JMP_SLOT
7726 BFD_RELOC_TILEGX_RELATIVE
7728 BFD_RELOC_TILEGX_BROFF_X1
7730 BFD_RELOC_TILEGX_JUMPOFF_X1
7732 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7734 BFD_RELOC_TILEGX_IMM8_X0
7736 BFD_RELOC_TILEGX_IMM8_Y0
7738 BFD_RELOC_TILEGX_IMM8_X1
7740 BFD_RELOC_TILEGX_IMM8_Y1
7742 BFD_RELOC_TILEGX_DEST_IMM8_X1
7744 BFD_RELOC_TILEGX_MT_IMM14_X1
7746 BFD_RELOC_TILEGX_MF_IMM14_X1
7748 BFD_RELOC_TILEGX_MMSTART_X0
7750 BFD_RELOC_TILEGX_MMEND_X0
7752 BFD_RELOC_TILEGX_SHAMT_X0
7754 BFD_RELOC_TILEGX_SHAMT_X1
7756 BFD_RELOC_TILEGX_SHAMT_Y0
7758 BFD_RELOC_TILEGX_SHAMT_Y1
7760 BFD_RELOC_TILEGX_IMM16_X0_HW0
7762 BFD_RELOC_TILEGX_IMM16_X1_HW0
7764 BFD_RELOC_TILEGX_IMM16_X0_HW1
7766 BFD_RELOC_TILEGX_IMM16_X1_HW1
7768 BFD_RELOC_TILEGX_IMM16_X0_HW2
7770 BFD_RELOC_TILEGX_IMM16_X1_HW2
7772 BFD_RELOC_TILEGX_IMM16_X0_HW3
7774 BFD_RELOC_TILEGX_IMM16_X1_HW3
7776 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7778 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7780 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7782 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7784 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7786 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7788 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7790 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7792 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7794 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7796 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7798 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7800 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7802 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7804 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7810 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7812 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7814 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7816 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7818 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7820 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7822 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7824 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7826 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7828 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7830 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7832 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7834 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7836 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7838 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7840 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7842 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7844 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7846 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7848 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7850 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7852 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7854 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7856 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7858 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7860 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7862 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7864 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7866 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7868 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7870 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7872 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7874 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7876 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7878 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7880 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7882 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7884 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7886 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7888 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7890 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7892 BFD_RELOC_TILEGX_TLS_DTPMOD64
7894 BFD_RELOC_TILEGX_TLS_DTPOFF64
7896 BFD_RELOC_TILEGX_TLS_TPOFF64
7898 BFD_RELOC_TILEGX_TLS_DTPMOD32
7900 BFD_RELOC_TILEGX_TLS_DTPOFF32
7902 BFD_RELOC_TILEGX_TLS_TPOFF32
7904 BFD_RELOC_TILEGX_TLS_GD_CALL
7906 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7908 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7910 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7912 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7914 BFD_RELOC_TILEGX_TLS_IE_LOAD
7916 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7918 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7920 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7922 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7924 Tilera TILE-Gx Relocations.
7933 BFD_RELOC_BPF_DISP16
7935 BFD_RELOC_BPF_DISP32
7937 Linux eBPF relocations.
7940 BFD_RELOC_EPIPHANY_SIMM8
7942 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7944 BFD_RELOC_EPIPHANY_SIMM24
7946 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7948 BFD_RELOC_EPIPHANY_HIGH
7950 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7952 BFD_RELOC_EPIPHANY_LOW
7954 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7956 BFD_RELOC_EPIPHANY_SIMM11
7958 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7960 BFD_RELOC_EPIPHANY_IMM11
7962 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7964 BFD_RELOC_EPIPHANY_IMM8
7966 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7969 BFD_RELOC_VISIUM_HI16
7971 BFD_RELOC_VISIUM_LO16
7973 BFD_RELOC_VISIUM_IM16
7975 BFD_RELOC_VISIUM_REL16
7977 BFD_RELOC_VISIUM_HI16_PCREL
7979 BFD_RELOC_VISIUM_LO16_PCREL
7981 BFD_RELOC_VISIUM_IM16_PCREL
7986 BFD_RELOC_WASM32_LEB128
7988 BFD_RELOC_WASM32_LEB128_GOT
7990 BFD_RELOC_WASM32_LEB128_GOT_CODE
7992 BFD_RELOC_WASM32_LEB128_PLT
7994 BFD_RELOC_WASM32_PLT_INDEX
7996 BFD_RELOC_WASM32_ABS32_CODE
7998 BFD_RELOC_WASM32_COPY
8000 BFD_RELOC_WASM32_CODE_POINTER
8002 BFD_RELOC_WASM32_INDEX
8004 BFD_RELOC_WASM32_PLT_SIG
8006 WebAssembly relocations.
8009 BFD_RELOC_CKCORE_NONE
8011 BFD_RELOC_CKCORE_ADDR32
8013 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8015 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8017 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8019 BFD_RELOC_CKCORE_PCREL32
8021 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8023 BFD_RELOC_CKCORE_GNU_VTINHERIT
8025 BFD_RELOC_CKCORE_GNU_VTENTRY
8027 BFD_RELOC_CKCORE_RELATIVE
8029 BFD_RELOC_CKCORE_COPY
8031 BFD_RELOC_CKCORE_GLOB_DAT
8033 BFD_RELOC_CKCORE_JUMP_SLOT
8035 BFD_RELOC_CKCORE_GOTOFF
8037 BFD_RELOC_CKCORE_GOTPC
8039 BFD_RELOC_CKCORE_GOT32
8041 BFD_RELOC_CKCORE_PLT32
8043 BFD_RELOC_CKCORE_ADDRGOT
8045 BFD_RELOC_CKCORE_ADDRPLT
8047 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8049 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8051 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8053 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8055 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8057 BFD_RELOC_CKCORE_ADDR_HI16
8059 BFD_RELOC_CKCORE_ADDR_LO16
8061 BFD_RELOC_CKCORE_GOTPC_HI16
8063 BFD_RELOC_CKCORE_GOTPC_LO16
8065 BFD_RELOC_CKCORE_GOTOFF_HI16
8067 BFD_RELOC_CKCORE_GOTOFF_LO16
8069 BFD_RELOC_CKCORE_GOT12
8071 BFD_RELOC_CKCORE_GOT_HI16
8073 BFD_RELOC_CKCORE_GOT_LO16
8075 BFD_RELOC_CKCORE_PLT12
8077 BFD_RELOC_CKCORE_PLT_HI16
8079 BFD_RELOC_CKCORE_PLT_LO16
8081 BFD_RELOC_CKCORE_ADDRGOT_HI16
8083 BFD_RELOC_CKCORE_ADDRGOT_LO16
8085 BFD_RELOC_CKCORE_ADDRPLT_HI16
8087 BFD_RELOC_CKCORE_ADDRPLT_LO16
8089 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8091 BFD_RELOC_CKCORE_TOFFSET_LO16
8093 BFD_RELOC_CKCORE_DOFFSET_LO16
8095 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8097 BFD_RELOC_CKCORE_DOFFSET_IMM18
8099 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8101 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8103 BFD_RELOC_CKCORE_GOTOFF_IMM18
8105 BFD_RELOC_CKCORE_GOT_IMM18BY4
8107 BFD_RELOC_CKCORE_PLT_IMM18BY4
8109 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8111 BFD_RELOC_CKCORE_TLS_LE32
8113 BFD_RELOC_CKCORE_TLS_IE32
8115 BFD_RELOC_CKCORE_TLS_GD32
8117 BFD_RELOC_CKCORE_TLS_LDM32
8119 BFD_RELOC_CKCORE_TLS_LDO32
8121 BFD_RELOC_CKCORE_TLS_DTPMOD32
8123 BFD_RELOC_CKCORE_TLS_DTPOFF32
8125 BFD_RELOC_CKCORE_TLS_TPOFF32
8127 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8129 BFD_RELOC_CKCORE_NOJSRI
8131 BFD_RELOC_CKCORE_CALLGRAPH
8133 BFD_RELOC_CKCORE_IRELATIVE
8135 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8137 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8150 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8155 bfd_reloc_type_lookup
8156 bfd_reloc_name_lookup
8159 reloc_howto_type *bfd_reloc_type_lookup
8160 (bfd *abfd, bfd_reloc_code_real_type code);
8161 reloc_howto_type *bfd_reloc_name_lookup
8162 (bfd *abfd, const char *reloc_name);
8165 Return a pointer to a howto structure which, when
8166 invoked, will perform the relocation @var{code} on data from the
8172 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8174 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8178 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8180 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8183 static reloc_howto_type bfd_howto_32
=
8184 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8188 bfd_default_reloc_type_lookup
8191 reloc_howto_type *bfd_default_reloc_type_lookup
8192 (bfd *abfd, bfd_reloc_code_real_type code);
8195 Provides a default relocation lookup routine for any architecture.
8200 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8202 /* Very limited support is provided for relocs in generic targets
8203 such as elf32-little. FIXME: Should we always return NULL? */
8204 if (code
== BFD_RELOC_CTOR
8205 && bfd_arch_bits_per_address (abfd
) == 32)
8206 return &bfd_howto_32
;
8212 bfd_get_reloc_code_name
8215 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8218 Provides a printable name for the supplied relocation code.
8219 Useful mainly for printing error messages.
8223 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8225 if (code
> BFD_RELOC_UNUSED
)
8227 return bfd_reloc_code_real_names
[code
];
8232 bfd_generic_relax_section
8235 bfd_boolean bfd_generic_relax_section
8238 struct bfd_link_info *,
8242 Provides default handling for relaxing for back ends which
8247 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8248 asection
*section ATTRIBUTE_UNUSED
,
8249 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8252 if (bfd_link_relocatable (link_info
))
8253 (*link_info
->callbacks
->einfo
)
8254 (_("%P%F: --relax and -r may not be used together\n"));
8262 bfd_generic_gc_sections
8265 bfd_boolean bfd_generic_gc_sections
8266 (bfd *, struct bfd_link_info *);
8269 Provides default handling for relaxing for back ends which
8270 don't do section gc -- i.e., does nothing.
8274 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8275 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8282 bfd_generic_lookup_section_flags
8285 bfd_boolean bfd_generic_lookup_section_flags
8286 (struct bfd_link_info *, struct flag_info *, asection *);
8289 Provides default handling for section flags lookup
8290 -- i.e., does nothing.
8291 Returns FALSE if the section should be omitted, otherwise TRUE.
8295 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8296 struct flag_info
*flaginfo
,
8297 asection
*section ATTRIBUTE_UNUSED
)
8299 if (flaginfo
!= NULL
)
8301 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8309 bfd_generic_merge_sections
8312 bfd_boolean bfd_generic_merge_sections
8313 (bfd *, struct bfd_link_info *);
8316 Provides default handling for SEC_MERGE section merging for back ends
8317 which don't have SEC_MERGE support -- i.e., does nothing.
8321 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8322 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8329 bfd_generic_get_relocated_section_contents
8332 bfd_byte *bfd_generic_get_relocated_section_contents
8334 struct bfd_link_info *link_info,
8335 struct bfd_link_order *link_order,
8337 bfd_boolean relocatable,
8341 Provides default handling of relocation effort for back ends
8342 which can't be bothered to do it efficiently.
8347 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8348 struct bfd_link_info
*link_info
,
8349 struct bfd_link_order
*link_order
,
8351 bfd_boolean relocatable
,
8354 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8355 asection
*input_section
= link_order
->u
.indirect
.section
;
8357 arelent
**reloc_vector
;
8360 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8364 /* Read in the section. */
8365 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8371 if (reloc_size
== 0)
8374 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8375 if (reloc_vector
== NULL
)
8378 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8382 if (reloc_count
< 0)
8385 if (reloc_count
> 0)
8389 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8391 char *error_message
= NULL
;
8393 bfd_reloc_status_type r
;
8395 symbol
= *(*parent
)->sym_ptr_ptr
;
8396 /* PR ld/19628: A specially crafted input file
8397 can result in a NULL symbol pointer here. */
8400 link_info
->callbacks
->einfo
8401 /* xgettext:c-format */
8402 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8403 abfd
, input_section
, (* parent
)->address
);
8407 /* Zap reloc field when the symbol is from a discarded
8408 section, ignoring any addend. Do the same when called
8409 from bfd_simple_get_relocated_section_contents for
8410 undefined symbols in debug sections. This is to keep
8411 debug info reasonably sane, in particular so that
8412 DW_FORM_ref_addr to another file's .debug_info isn't
8413 confused with an offset into the current file's
8415 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8416 || (symbol
->section
== bfd_und_section_ptr
8417 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8418 && link_info
->input_bfds
== link_info
->output_bfd
))
8421 static reloc_howto_type none_howto
8422 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8423 "unused", FALSE
, 0, 0, FALSE
);
8425 off
= ((*parent
)->address
8426 * bfd_octets_per_byte (input_bfd
, input_section
));
8427 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8428 input_section
, data
, off
);
8429 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8430 (*parent
)->addend
= 0;
8431 (*parent
)->howto
= &none_howto
;
8435 r
= bfd_perform_relocation (input_bfd
,
8439 relocatable
? abfd
: NULL
,
8444 asection
*os
= input_section
->output_section
;
8446 /* A partial link, so keep the relocs. */
8447 os
->orelocation
[os
->reloc_count
] = *parent
;
8451 if (r
!= bfd_reloc_ok
)
8455 case bfd_reloc_undefined
:
8456 (*link_info
->callbacks
->undefined_symbol
)
8457 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8458 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8460 case bfd_reloc_dangerous
:
8461 BFD_ASSERT (error_message
!= NULL
);
8462 (*link_info
->callbacks
->reloc_dangerous
)
8463 (link_info
, error_message
,
8464 input_bfd
, input_section
, (*parent
)->address
);
8466 case bfd_reloc_overflow
:
8467 (*link_info
->callbacks
->reloc_overflow
)
8469 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8470 (*parent
)->howto
->name
, (*parent
)->addend
,
8471 input_bfd
, input_section
, (*parent
)->address
);
8473 case bfd_reloc_outofrange
:
8475 This error can result when processing some partially
8476 complete binaries. Do not abort, but issue an error
8478 link_info
->callbacks
->einfo
8479 /* xgettext:c-format */
8480 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8481 abfd
, input_section
, * parent
);
8484 case bfd_reloc_notsupported
:
8486 This error can result when processing a corrupt binary.
8487 Do not abort. Issue an error message instead. */
8488 link_info
->callbacks
->einfo
8489 /* xgettext:c-format */
8490 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8491 abfd
, input_section
, * parent
);
8495 /* PR 17512; file: 90c2a92e.
8496 Report unexpected results, without aborting. */
8497 link_info
->callbacks
->einfo
8498 /* xgettext:c-format */
8499 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8500 abfd
, input_section
, * parent
, r
);
8508 free (reloc_vector
);
8512 free (reloc_vector
);
8518 _bfd_generic_set_reloc
8521 void _bfd_generic_set_reloc
8525 unsigned int count);
8528 Installs a new set of internal relocations in SECTION.
8532 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8537 section
->orelocation
= relptr
;
8538 section
->reloc_count
= count
;
8543 _bfd_unrecognized_reloc
8546 bfd_boolean _bfd_unrecognized_reloc
8549 unsigned int r_type);
8552 Reports an unrecognized reloc.
8553 Written as a function in order to reduce code duplication.
8554 Returns FALSE so that it can be called from a return statement.
8558 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8560 /* xgettext:c-format */
8561 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8562 abfd
, r_type
, section
);
8564 /* PR 21803: Suggest the most likely cause of this error. */
8565 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8566 BFD_VERSION_STRING
);
8568 bfd_set_error (bfd_error_bad_value
);
8573 _bfd_norelocs_bfd_reloc_type_lookup
8575 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8577 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8581 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8582 const char *reloc_name ATTRIBUTE_UNUSED
)
8584 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8588 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8589 arelent
**relp ATTRIBUTE_UNUSED
,
8590 asymbol
**symp ATTRIBUTE_UNUSED
)
8592 return _bfd_long_bfd_n1_error (abfd
);