1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2017 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. *}
71 . {* The relocation was performed, but there was an overflow. *}
74 . {* The address to relocate was not within the section supplied. *}
75 . bfd_reloc_outofrange,
77 . {* Used by special functions. *}
80 . {* Unsupported relocation size requested. *}
81 . bfd_reloc_notsupported,
86 . {* The symbol to relocate against was undefined. *}
87 . bfd_reloc_undefined,
89 . {* The relocation was performed, but may not be ok - presently
90 . generated only when linking i960 coff files with i960 b.out
91 . symbols. If this type is returned, the error_message argument
92 . to bfd_perform_relocation will be set. *}
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated (e.g., i960 callj
322 . bfd_reloc_status_type (*special_function)
323 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
326 . {* The textual name of the relocation type. *}
329 . {* Some formats record a relocation addend in the section contents
330 . rather than with the relocation. For ELF formats this is the
331 . distinction between USE_REL and USE_RELA (though the code checks
332 . for USE_REL == 1/0). The value of this field is TRUE if the
333 . addend is recorded with the section contents; when performing a
334 . partial link (ld -r) the section contents (the data) will be
335 . modified. The value of this field is FALSE if addends are
336 . recorded with the relocation (in arelent.addend); when performing
337 . a partial link the relocation will be modified.
338 . All relocations for all ELF USE_RELA targets should set this field
339 . to FALSE (values of TRUE should be looked on with suspicion).
340 . However, the converse is not true: not all relocations of all ELF
341 . USE_REL targets set this field to TRUE. Why this is so is peculiar
342 . to each particular target. For relocs that aren't used in partial
343 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
344 . bfd_boolean partial_inplace;
346 . {* src_mask selects the part of the instruction (or data) to be used
347 . in the relocation sum. If the target relocations don't have an
348 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
349 . dst_mask to extract the addend from the section contents. If
350 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
351 . field should be zero. Non-zero values for ELF USE_RELA targets are
352 . bogus as in those cases the value in the dst_mask part of the
353 . section contents should be treated as garbage. *}
356 . {* dst_mask selects which parts of the instruction (or data) are
357 . replaced with a relocated value. *}
360 . {* When some formats create PC relative instructions, they leave
361 . the value of the pc of the place being relocated in the offset
362 . slot of the instruction, so that a PC relative relocation can
363 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
364 . Some formats leave the displacement part of an instruction
365 . empty (e.g., m88k bcs); this flag signals the fact. *}
366 . bfd_boolean pcrel_offset;
376 The HOWTO define is horrible and will go away.
378 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
379 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
382 And will be replaced with the totally magic way. But for the
383 moment, we are compatible, so do it this way.
385 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
386 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
387 . NAME, FALSE, 0, 0, IN)
391 This is used to fill in an empty howto entry in an array.
393 .#define EMPTY_HOWTO(C) \
394 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
395 . NULL, FALSE, 0, 0, FALSE)
399 Helper routine to turn a symbol into a relocation value.
401 .#define HOWTO_PREPARE(relocation, symbol) \
403 . if (symbol != NULL) \
405 . if (bfd_is_com_section (symbol->section)) \
411 . relocation = symbol->value; \
423 unsigned int bfd_get_reloc_size (reloc_howto_type *);
426 For a reloc_howto_type that operates on a fixed number of bytes,
427 this returns the number of bytes operated on.
431 bfd_get_reloc_size (reloc_howto_type
*howto
)
453 How relocs are tied together in an <<asection>>:
455 .typedef struct relent_chain
458 . struct relent_chain *next;
464 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
465 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
472 bfd_reloc_status_type bfd_check_overflow
473 (enum complain_overflow how,
474 unsigned int bitsize,
475 unsigned int rightshift,
476 unsigned int addrsize,
480 Perform overflow checking on @var{relocation} which has
481 @var{bitsize} significant bits and will be shifted right by
482 @var{rightshift} bits, on a machine with addresses containing
483 @var{addrsize} significant bits. The result is either of
484 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
488 bfd_reloc_status_type
489 bfd_check_overflow (enum complain_overflow how
,
490 unsigned int bitsize
,
491 unsigned int rightshift
,
492 unsigned int addrsize
,
495 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
496 bfd_reloc_status_type flag
= bfd_reloc_ok
;
498 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
499 we'll be permissive: extra bits in the field mask will
500 automatically extend the address mask for purposes of the
502 fieldmask
= N_ONES (bitsize
);
503 signmask
= ~fieldmask
;
504 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
505 a
= (relocation
& addrmask
) >> rightshift
;
509 case complain_overflow_dont
:
512 case complain_overflow_signed
:
513 /* If any sign bits are set, all sign bits must be set. That
514 is, A must be a valid negative address after shifting. */
515 signmask
= ~ (fieldmask
>> 1);
518 case complain_overflow_bitfield
:
519 /* Bitfields are sometimes signed, sometimes unsigned. We
520 explicitly allow an address wrap too, which means a bitfield
521 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
522 if the value has some, but not all, bits set outside the
525 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
526 flag
= bfd_reloc_overflow
;
529 case complain_overflow_unsigned
:
530 /* We have an overflow if the address does not fit in the field. */
531 if ((a
& signmask
) != 0)
532 flag
= bfd_reloc_overflow
;
542 /* HOWTO describes a relocation, at offset OCTET. Return whether the
543 relocation field is within SECTION of ABFD. */
546 reloc_offset_in_range (reloc_howto_type
*howto
, bfd
*abfd
,
547 asection
*section
, bfd_size_type octet
)
549 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
550 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
552 /* The reloc field must be contained entirely within the section.
553 Allow zero length fields (marker relocs or NONE relocs where no
554 relocation will be performed) at the end of the section. */
555 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
560 bfd_perform_relocation
563 bfd_reloc_status_type bfd_perform_relocation
565 arelent *reloc_entry,
567 asection *input_section,
569 char **error_message);
572 If @var{output_bfd} is supplied to this function, the
573 generated image will be relocatable; the relocations are
574 copied to the output file after they have been changed to
575 reflect the new state of the world. There are two ways of
576 reflecting the results of partial linkage in an output file:
577 by modifying the output data in place, and by modifying the
578 relocation record. Some native formats (e.g., basic a.out and
579 basic coff) have no way of specifying an addend in the
580 relocation type, so the addend has to go in the output data.
581 This is no big deal since in these formats the output data
582 slot will always be big enough for the addend. Complex reloc
583 types with addends were invented to solve just this problem.
584 The @var{error_message} argument is set to an error message if
585 this return @code{bfd_reloc_dangerous}.
589 bfd_reloc_status_type
590 bfd_perform_relocation (bfd
*abfd
,
591 arelent
*reloc_entry
,
593 asection
*input_section
,
595 char **error_message
)
598 bfd_reloc_status_type flag
= bfd_reloc_ok
;
599 bfd_size_type octets
;
600 bfd_vma output_base
= 0;
601 reloc_howto_type
*howto
= reloc_entry
->howto
;
602 asection
*reloc_target_output_section
;
605 symbol
= *(reloc_entry
->sym_ptr_ptr
);
607 /* If we are not producing relocatable output, return an error if
608 the symbol is not defined. An undefined weak symbol is
609 considered to have a value of zero (SVR4 ABI, p. 4-27). */
610 if (bfd_is_und_section (symbol
->section
)
611 && (symbol
->flags
& BSF_WEAK
) == 0
612 && output_bfd
== NULL
)
613 flag
= bfd_reloc_undefined
;
615 /* If there is a function supplied to handle this relocation type,
616 call it. It'll return `bfd_reloc_continue' if further processing
618 if (howto
&& howto
->special_function
)
620 bfd_reloc_status_type cont
;
621 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
622 input_section
, output_bfd
,
624 if (cont
!= bfd_reloc_continue
)
628 if (bfd_is_abs_section (symbol
->section
)
629 && output_bfd
!= NULL
)
631 reloc_entry
->address
+= input_section
->output_offset
;
635 /* PR 17512: file: 0f67f69d. */
637 return bfd_reloc_undefined
;
639 /* Is the address of the relocation really within the section? */
640 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
641 if (!reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
642 return bfd_reloc_outofrange
;
644 /* Work out which section the relocation is targeted at and the
645 initial relocation command value. */
647 /* Get symbol value. (Common symbols are special.) */
648 if (bfd_is_com_section (symbol
->section
))
651 relocation
= symbol
->value
;
653 reloc_target_output_section
= symbol
->section
->output_section
;
655 /* Convert input-section-relative symbol value to absolute. */
656 if ((output_bfd
&& ! howto
->partial_inplace
)
657 || reloc_target_output_section
== NULL
)
660 output_base
= reloc_target_output_section
->vma
;
662 relocation
+= output_base
+ symbol
->section
->output_offset
;
664 /* Add in supplied addend. */
665 relocation
+= reloc_entry
->addend
;
667 /* Here the variable relocation holds the final address of the
668 symbol we are relocating against, plus any addend. */
670 if (howto
->pc_relative
)
672 /* This is a PC relative relocation. We want to set RELOCATION
673 to the distance between the address of the symbol and the
674 location. RELOCATION is already the address of the symbol.
676 We start by subtracting the address of the section containing
679 If pcrel_offset is set, we must further subtract the position
680 of the location within the section. Some targets arrange for
681 the addend to be the negative of the position of the location
682 within the section; for example, i386-aout does this. For
683 i386-aout, pcrel_offset is FALSE. Some other targets do not
684 include the position of the location; for example, m88kbcs,
685 or ELF. For those targets, pcrel_offset is TRUE.
687 If we are producing relocatable output, then we must ensure
688 that this reloc will be correctly computed when the final
689 relocation is done. If pcrel_offset is FALSE we want to wind
690 up with the negative of the location within the section,
691 which means we must adjust the existing addend by the change
692 in the location within the section. If pcrel_offset is TRUE
693 we do not want to adjust the existing addend at all.
695 FIXME: This seems logical to me, but for the case of
696 producing relocatable output it is not what the code
697 actually does. I don't want to change it, because it seems
698 far too likely that something will break. */
701 input_section
->output_section
->vma
+ input_section
->output_offset
;
703 if (howto
->pcrel_offset
)
704 relocation
-= reloc_entry
->address
;
707 if (output_bfd
!= NULL
)
709 if (! howto
->partial_inplace
)
711 /* This is a partial relocation, and we want to apply the relocation
712 to the reloc entry rather than the raw data. Modify the reloc
713 inplace to reflect what we now know. */
714 reloc_entry
->addend
= relocation
;
715 reloc_entry
->address
+= input_section
->output_offset
;
720 /* This is a partial relocation, but inplace, so modify the
723 If we've relocated with a symbol with a section, change
724 into a ref to the section belonging to the symbol. */
726 reloc_entry
->address
+= input_section
->output_offset
;
729 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
730 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
731 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
733 /* For m68k-coff, the addend was being subtracted twice during
734 relocation with -r. Removing the line below this comment
735 fixes that problem; see PR 2953.
737 However, Ian wrote the following, regarding removing the line below,
738 which explains why it is still enabled: --djm
740 If you put a patch like that into BFD you need to check all the COFF
741 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
742 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
743 problem in a different way. There may very well be a reason that the
744 code works as it does.
746 Hmmm. The first obvious point is that bfd_perform_relocation should
747 not have any tests that depend upon the flavour. It's seem like
748 entirely the wrong place for such a thing. The second obvious point
749 is that the current code ignores the reloc addend when producing
750 relocatable output for COFF. That's peculiar. In fact, I really
751 have no idea what the point of the line you want to remove is.
753 A typical COFF reloc subtracts the old value of the symbol and adds in
754 the new value to the location in the object file (if it's a pc
755 relative reloc it adds the difference between the symbol value and the
756 location). When relocating we need to preserve that property.
758 BFD handles this by setting the addend to the negative of the old
759 value of the symbol. Unfortunately it handles common symbols in a
760 non-standard way (it doesn't subtract the old value) but that's a
761 different story (we can't change it without losing backward
762 compatibility with old object files) (coff-i386 does subtract the old
763 value, to be compatible with existing coff-i386 targets, like SCO).
765 So everything works fine when not producing relocatable output. When
766 we are producing relocatable output, logically we should do exactly
767 what we do when not producing relocatable output. Therefore, your
768 patch is correct. In fact, it should probably always just set
769 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
770 add the value into the object file. This won't hurt the COFF code,
771 which doesn't use the addend; I'm not sure what it will do to other
772 formats (the thing to check for would be whether any formats both use
773 the addend and set partial_inplace).
775 When I wanted to make coff-i386 produce relocatable output, I ran
776 into the problem that you are running into: I wanted to remove that
777 line. Rather than risk it, I made the coff-i386 relocs use a special
778 function; it's coff_i386_reloc in coff-i386.c. The function
779 specifically adds the addend field into the object file, knowing that
780 bfd_perform_relocation is not going to. If you remove that line, then
781 coff-i386.c will wind up adding the addend field in twice. It's
782 trivial to fix; it just needs to be done.
784 The problem with removing the line is just that it may break some
785 working code. With BFD it's hard to be sure of anything. The right
786 way to deal with this is simply to build and test at least all the
787 supported COFF targets. It should be straightforward if time and disk
788 space consuming. For each target:
790 2) generate some executable, and link it using -r (I would
791 probably use paranoia.o and link against newlib/libc.a, which
792 for all the supported targets would be available in
793 /usr/cygnus/progressive/H-host/target/lib/libc.a).
794 3) make the change to reloc.c
795 4) rebuild the linker
797 6) if the resulting object files are the same, you have at least
799 7) if they are different you have to figure out which version is
802 relocation
-= reloc_entry
->addend
;
803 reloc_entry
->addend
= 0;
807 reloc_entry
->addend
= relocation
;
812 /* FIXME: This overflow checking is incomplete, because the value
813 might have overflowed before we get here. For a correct check we
814 need to compute the value in a size larger than bitsize, but we
815 can't reasonably do that for a reloc the same size as a host
817 FIXME: We should also do overflow checking on the result after
818 adding in the value contained in the object file. */
819 if (howto
->complain_on_overflow
!= complain_overflow_dont
820 && flag
== bfd_reloc_ok
)
821 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
824 bfd_arch_bits_per_address (abfd
),
827 /* Either we are relocating all the way, or we don't want to apply
828 the relocation to the reloc entry (probably because there isn't
829 any room in the output format to describe addends to relocs). */
831 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
832 (OSF version 1.3, compiler version 3.11). It miscompiles the
846 x <<= (unsigned long) s.i0;
850 printf ("succeeded (%lx)\n", x);
854 relocation
>>= (bfd_vma
) howto
->rightshift
;
856 /* Shift everything up to where it's going to be used. */
857 relocation
<<= (bfd_vma
) howto
->bitpos
;
859 /* Wait for the day when all have the mask in them. */
862 i instruction to be left alone
863 o offset within instruction
864 r relocation offset to apply
873 (( i i i i i o o o o o from bfd_get<size>
874 and S S S S S) to get the size offset we want
875 + r r r r r r r r r r) to get the final value to place
876 and D D D D D to chop to right size
877 -----------------------
880 ( i i i i i o o o o o from bfd_get<size>
881 and N N N N N ) get instruction
882 -----------------------
888 -----------------------
889 = R R R R R R R R R R put into bfd_put<size>
893 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
899 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
901 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
907 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
909 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
914 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
916 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
921 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
922 relocation
= -relocation
;
924 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
930 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
931 relocation
= -relocation
;
933 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
944 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
946 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
953 return bfd_reloc_other
;
961 bfd_install_relocation
964 bfd_reloc_status_type bfd_install_relocation
966 arelent *reloc_entry,
967 void *data, bfd_vma data_start,
968 asection *input_section,
969 char **error_message);
972 This looks remarkably like <<bfd_perform_relocation>>, except it
973 does not expect that the section contents have been filled in.
974 I.e., it's suitable for use when creating, rather than applying
977 For now, this function should be considered reserved for the
981 bfd_reloc_status_type
982 bfd_install_relocation (bfd
*abfd
,
983 arelent
*reloc_entry
,
985 bfd_vma data_start_offset
,
986 asection
*input_section
,
987 char **error_message
)
990 bfd_reloc_status_type flag
= bfd_reloc_ok
;
991 bfd_size_type octets
;
992 bfd_vma output_base
= 0;
993 reloc_howto_type
*howto
= reloc_entry
->howto
;
994 asection
*reloc_target_output_section
;
998 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1000 /* If there is a function supplied to handle this relocation type,
1001 call it. It'll return `bfd_reloc_continue' if further processing
1003 if (howto
&& howto
->special_function
)
1005 bfd_reloc_status_type cont
;
1007 /* XXX - The special_function calls haven't been fixed up to deal
1008 with creating new relocations and section contents. */
1009 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1010 /* XXX - Non-portable! */
1011 ((bfd_byte
*) data_start
1012 - data_start_offset
),
1013 input_section
, abfd
, error_message
);
1014 if (cont
!= bfd_reloc_continue
)
1018 if (bfd_is_abs_section (symbol
->section
))
1020 reloc_entry
->address
+= input_section
->output_offset
;
1021 return bfd_reloc_ok
;
1024 /* No need to check for howto != NULL if !bfd_is_abs_section as
1025 it will have been checked in `bfd_perform_relocation already'. */
1027 /* Is the address of the relocation really within the section? */
1028 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1029 if (!reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1030 return bfd_reloc_outofrange
;
1032 /* Work out which section the relocation is targeted at and the
1033 initial relocation command value. */
1035 /* Get symbol value. (Common symbols are special.) */
1036 if (bfd_is_com_section (symbol
->section
))
1039 relocation
= symbol
->value
;
1041 reloc_target_output_section
= symbol
->section
->output_section
;
1043 /* Convert input-section-relative symbol value to absolute. */
1044 if (! howto
->partial_inplace
)
1047 output_base
= reloc_target_output_section
->vma
;
1049 relocation
+= output_base
+ symbol
->section
->output_offset
;
1051 /* Add in supplied addend. */
1052 relocation
+= reloc_entry
->addend
;
1054 /* Here the variable relocation holds the final address of the
1055 symbol we are relocating against, plus any addend. */
1057 if (howto
->pc_relative
)
1059 /* This is a PC relative relocation. We want to set RELOCATION
1060 to the distance between the address of the symbol and the
1061 location. RELOCATION is already the address of the symbol.
1063 We start by subtracting the address of the section containing
1066 If pcrel_offset is set, we must further subtract the position
1067 of the location within the section. Some targets arrange for
1068 the addend to be the negative of the position of the location
1069 within the section; for example, i386-aout does this. For
1070 i386-aout, pcrel_offset is FALSE. Some other targets do not
1071 include the position of the location; for example, m88kbcs,
1072 or ELF. For those targets, pcrel_offset is TRUE.
1074 If we are producing relocatable output, then we must ensure
1075 that this reloc will be correctly computed when the final
1076 relocation is done. If pcrel_offset is FALSE we want to wind
1077 up with the negative of the location within the section,
1078 which means we must adjust the existing addend by the change
1079 in the location within the section. If pcrel_offset is TRUE
1080 we do not want to adjust the existing addend at all.
1082 FIXME: This seems logical to me, but for the case of
1083 producing relocatable output it is not what the code
1084 actually does. I don't want to change it, because it seems
1085 far too likely that something will break. */
1088 input_section
->output_section
->vma
+ input_section
->output_offset
;
1090 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1091 relocation
-= reloc_entry
->address
;
1094 if (! howto
->partial_inplace
)
1096 /* This is a partial relocation, and we want to apply the relocation
1097 to the reloc entry rather than the raw data. Modify the reloc
1098 inplace to reflect what we now know. */
1099 reloc_entry
->addend
= relocation
;
1100 reloc_entry
->address
+= input_section
->output_offset
;
1105 /* This is a partial relocation, but inplace, so modify the
1108 If we've relocated with a symbol with a section, change
1109 into a ref to the section belonging to the symbol. */
1110 reloc_entry
->address
+= input_section
->output_offset
;
1113 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1114 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1115 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1118 /* For m68k-coff, the addend was being subtracted twice during
1119 relocation with -r. Removing the line below this comment
1120 fixes that problem; see PR 2953.
1122 However, Ian wrote the following, regarding removing the line below,
1123 which explains why it is still enabled: --djm
1125 If you put a patch like that into BFD you need to check all the COFF
1126 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1127 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1128 problem in a different way. There may very well be a reason that the
1129 code works as it does.
1131 Hmmm. The first obvious point is that bfd_install_relocation should
1132 not have any tests that depend upon the flavour. It's seem like
1133 entirely the wrong place for such a thing. The second obvious point
1134 is that the current code ignores the reloc addend when producing
1135 relocatable output for COFF. That's peculiar. In fact, I really
1136 have no idea what the point of the line you want to remove is.
1138 A typical COFF reloc subtracts the old value of the symbol and adds in
1139 the new value to the location in the object file (if it's a pc
1140 relative reloc it adds the difference between the symbol value and the
1141 location). When relocating we need to preserve that property.
1143 BFD handles this by setting the addend to the negative of the old
1144 value of the symbol. Unfortunately it handles common symbols in a
1145 non-standard way (it doesn't subtract the old value) but that's a
1146 different story (we can't change it without losing backward
1147 compatibility with old object files) (coff-i386 does subtract the old
1148 value, to be compatible with existing coff-i386 targets, like SCO).
1150 So everything works fine when not producing relocatable output. When
1151 we are producing relocatable output, logically we should do exactly
1152 what we do when not producing relocatable output. Therefore, your
1153 patch is correct. In fact, it should probably always just set
1154 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1155 add the value into the object file. This won't hurt the COFF code,
1156 which doesn't use the addend; I'm not sure what it will do to other
1157 formats (the thing to check for would be whether any formats both use
1158 the addend and set partial_inplace).
1160 When I wanted to make coff-i386 produce relocatable output, I ran
1161 into the problem that you are running into: I wanted to remove that
1162 line. Rather than risk it, I made the coff-i386 relocs use a special
1163 function; it's coff_i386_reloc in coff-i386.c. The function
1164 specifically adds the addend field into the object file, knowing that
1165 bfd_install_relocation is not going to. If you remove that line, then
1166 coff-i386.c will wind up adding the addend field in twice. It's
1167 trivial to fix; it just needs to be done.
1169 The problem with removing the line is just that it may break some
1170 working code. With BFD it's hard to be sure of anything. The right
1171 way to deal with this is simply to build and test at least all the
1172 supported COFF targets. It should be straightforward if time and disk
1173 space consuming. For each target:
1175 2) generate some executable, and link it using -r (I would
1176 probably use paranoia.o and link against newlib/libc.a, which
1177 for all the supported targets would be available in
1178 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1179 3) make the change to reloc.c
1180 4) rebuild the linker
1182 6) if the resulting object files are the same, you have at least
1184 7) if they are different you have to figure out which version is
1186 relocation
-= reloc_entry
->addend
;
1187 /* FIXME: There should be no target specific code here... */
1188 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1189 reloc_entry
->addend
= 0;
1193 reloc_entry
->addend
= relocation
;
1197 /* FIXME: This overflow checking is incomplete, because the value
1198 might have overflowed before we get here. For a correct check we
1199 need to compute the value in a size larger than bitsize, but we
1200 can't reasonably do that for a reloc the same size as a host
1202 FIXME: We should also do overflow checking on the result after
1203 adding in the value contained in the object file. */
1204 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1205 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1208 bfd_arch_bits_per_address (abfd
),
1211 /* Either we are relocating all the way, or we don't want to apply
1212 the relocation to the reloc entry (probably because there isn't
1213 any room in the output format to describe addends to relocs). */
1215 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1216 (OSF version 1.3, compiler version 3.11). It miscompiles the
1230 x <<= (unsigned long) s.i0;
1232 printf ("failed\n");
1234 printf ("succeeded (%lx)\n", x);
1238 relocation
>>= (bfd_vma
) howto
->rightshift
;
1240 /* Shift everything up to where it's going to be used. */
1241 relocation
<<= (bfd_vma
) howto
->bitpos
;
1243 /* Wait for the day when all have the mask in them. */
1246 i instruction to be left alone
1247 o offset within instruction
1248 r relocation offset to apply
1257 (( i i i i i o o o o o from bfd_get<size>
1258 and S S S S S) to get the size offset we want
1259 + r r r r r r r r r r) to get the final value to place
1260 and D D D D D to chop to right size
1261 -----------------------
1264 ( i i i i i o o o o o from bfd_get<size>
1265 and N N N N N ) get instruction
1266 -----------------------
1272 -----------------------
1273 = R R R R R R R R R R put into bfd_put<size>
1277 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1279 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1281 switch (howto
->size
)
1285 char x
= bfd_get_8 (abfd
, data
);
1287 bfd_put_8 (abfd
, x
, data
);
1293 short x
= bfd_get_16 (abfd
, data
);
1295 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1300 long x
= bfd_get_32 (abfd
, data
);
1302 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1307 long x
= bfd_get_32 (abfd
, data
);
1308 relocation
= -relocation
;
1310 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1320 bfd_vma x
= bfd_get_64 (abfd
, data
);
1322 bfd_put_64 (abfd
, x
, data
);
1326 return bfd_reloc_other
;
1332 /* This relocation routine is used by some of the backend linkers.
1333 They do not construct asymbol or arelent structures, so there is no
1334 reason for them to use bfd_perform_relocation. Also,
1335 bfd_perform_relocation is so hacked up it is easier to write a new
1336 function than to try to deal with it.
1338 This routine does a final relocation. Whether it is useful for a
1339 relocatable link depends upon how the object format defines
1342 FIXME: This routine ignores any special_function in the HOWTO,
1343 since the existing special_function values have been written for
1344 bfd_perform_relocation.
1346 HOWTO is the reloc howto information.
1347 INPUT_BFD is the BFD which the reloc applies to.
1348 INPUT_SECTION is the section which the reloc applies to.
1349 CONTENTS is the contents of the section.
1350 ADDRESS is the address of the reloc within INPUT_SECTION.
1351 VALUE is the value of the symbol the reloc refers to.
1352 ADDEND is the addend of the reloc. */
1354 bfd_reloc_status_type
1355 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1357 asection
*input_section
,
1364 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1366 /* Sanity check the address. */
1367 if (!reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1368 return bfd_reloc_outofrange
;
1370 /* This function assumes that we are dealing with a basic relocation
1371 against a symbol. We want to compute the value of the symbol to
1372 relocate to. This is just VALUE, the value of the symbol, plus
1373 ADDEND, any addend associated with the reloc. */
1374 relocation
= value
+ addend
;
1376 /* If the relocation is PC relative, we want to set RELOCATION to
1377 the distance between the symbol (currently in RELOCATION) and the
1378 location we are relocating. Some targets (e.g., i386-aout)
1379 arrange for the contents of the section to be the negative of the
1380 offset of the location within the section; for such targets
1381 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1382 simply leave the contents of the section as zero; for such
1383 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1384 need to subtract out the offset of the location within the
1385 section (which is just ADDRESS). */
1386 if (howto
->pc_relative
)
1388 relocation
-= (input_section
->output_section
->vma
1389 + input_section
->output_offset
);
1390 if (howto
->pcrel_offset
)
1391 relocation
-= address
;
1394 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1396 + address
* bfd_octets_per_byte (input_bfd
));
1399 /* Relocate a given location using a given value and howto. */
1401 bfd_reloc_status_type
1402 _bfd_relocate_contents (reloc_howto_type
*howto
,
1409 bfd_reloc_status_type flag
;
1410 unsigned int rightshift
= howto
->rightshift
;
1411 unsigned int bitpos
= howto
->bitpos
;
1413 /* If the size is negative, negate RELOCATION. This isn't very
1415 if (howto
->size
< 0)
1416 relocation
= -relocation
;
1418 /* Get the value we are going to relocate. */
1419 size
= bfd_get_reloc_size (howto
);
1425 return bfd_reloc_ok
;
1427 x
= bfd_get_8 (input_bfd
, location
);
1430 x
= bfd_get_16 (input_bfd
, location
);
1433 x
= bfd_get_32 (input_bfd
, location
);
1437 x
= bfd_get_64 (input_bfd
, location
);
1444 /* Check for overflow. FIXME: We may drop bits during the addition
1445 which we don't check for. We must either check at every single
1446 operation, which would be tedious, or we must do the computations
1447 in a type larger than bfd_vma, which would be inefficient. */
1448 flag
= bfd_reloc_ok
;
1449 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1451 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1454 /* Get the values to be added together. For signed and unsigned
1455 relocations, we assume that all values should be truncated to
1456 the size of an address. For bitfields, all the bits matter.
1457 See also bfd_check_overflow. */
1458 fieldmask
= N_ONES (howto
->bitsize
);
1459 signmask
= ~fieldmask
;
1460 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1461 | (fieldmask
<< rightshift
));
1462 a
= (relocation
& addrmask
) >> rightshift
;
1463 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1464 addrmask
>>= rightshift
;
1466 switch (howto
->complain_on_overflow
)
1468 case complain_overflow_signed
:
1469 /* If any sign bits are set, all sign bits must be set.
1470 That is, A must be a valid negative address after
1472 signmask
= ~(fieldmask
>> 1);
1475 case complain_overflow_bitfield
:
1476 /* Much like the signed check, but for a field one bit
1477 wider. We allow a bitfield to represent numbers in the
1478 range -2**n to 2**n-1, where n is the number of bits in the
1479 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1480 can't overflow, which is exactly what we want. */
1482 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1483 flag
= bfd_reloc_overflow
;
1485 /* We only need this next bit of code if the sign bit of B
1486 is below the sign bit of A. This would only happen if
1487 SRC_MASK had fewer bits than BITSIZE. Note that if
1488 SRC_MASK has more bits than BITSIZE, we can get into
1489 trouble; we would need to verify that B is in range, as
1490 we do for A above. */
1491 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1494 /* Set all the bits above the sign bit. */
1497 /* Now we can do the addition. */
1500 /* See if the result has the correct sign. Bits above the
1501 sign bit are junk now; ignore them. If the sum is
1502 positive, make sure we did not have all negative inputs;
1503 if the sum is negative, make sure we did not have all
1504 positive inputs. The test below looks only at the sign
1505 bits, and it really just
1506 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1508 We mask with addrmask here to explicitly allow an address
1509 wrap-around. The Linux kernel relies on it, and it is
1510 the only way to write assembler code which can run when
1511 loaded at a location 0x80000000 away from the location at
1512 which it is linked. */
1513 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1514 flag
= bfd_reloc_overflow
;
1517 case complain_overflow_unsigned
:
1518 /* Checking for an unsigned overflow is relatively easy:
1519 trim the addresses and add, and trim the result as well.
1520 Overflow is normally indicated when the result does not
1521 fit in the field. However, we also need to consider the
1522 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1523 input is 0x80000000, and bfd_vma is only 32 bits; then we
1524 will get sum == 0, but there is an overflow, since the
1525 inputs did not fit in the field. Instead of doing a
1526 separate test, we can check for this by or-ing in the
1527 operands when testing for the sum overflowing its final
1529 sum
= (a
+ b
) & addrmask
;
1530 if ((a
| b
| sum
) & signmask
)
1531 flag
= bfd_reloc_overflow
;
1539 /* Put RELOCATION in the right bits. */
1540 relocation
>>= (bfd_vma
) rightshift
;
1541 relocation
<<= (bfd_vma
) bitpos
;
1543 /* Add RELOCATION to the right bits of X. */
1544 x
= ((x
& ~howto
->dst_mask
)
1545 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1547 /* Put the relocated value back in the object file. */
1553 bfd_put_8 (input_bfd
, x
, location
);
1556 bfd_put_16 (input_bfd
, x
, location
);
1559 bfd_put_32 (input_bfd
, x
, location
);
1563 bfd_put_64 (input_bfd
, x
, location
);
1573 /* Clear a given location using a given howto, by applying a fixed relocation
1574 value and discarding any in-place addend. This is used for fixed-up
1575 relocations against discarded symbols, to make ignorable debug or unwind
1576 information more obvious. */
1579 _bfd_clear_contents (reloc_howto_type
*howto
,
1581 asection
*input_section
,
1587 /* Get the value we are going to relocate. */
1588 size
= bfd_get_reloc_size (howto
);
1596 x
= bfd_get_8 (input_bfd
, location
);
1599 x
= bfd_get_16 (input_bfd
, location
);
1602 x
= bfd_get_32 (input_bfd
, location
);
1606 x
= bfd_get_64 (input_bfd
, location
);
1613 /* Zero out the unwanted bits of X. */
1614 x
&= ~howto
->dst_mask
;
1616 /* For a range list, use 1 instead of 0 as placeholder. 0
1617 would terminate the list, hiding any later entries. */
1618 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1619 ".debug_ranges") == 0
1620 && (howto
->dst_mask
& 1) != 0)
1623 /* Put the relocated value back in the object file. */
1630 bfd_put_8 (input_bfd
, x
, location
);
1633 bfd_put_16 (input_bfd
, x
, location
);
1636 bfd_put_32 (input_bfd
, x
, location
);
1640 bfd_put_64 (input_bfd
, x
, location
);
1651 howto manager, , typedef arelent, Relocations
1656 When an application wants to create a relocation, but doesn't
1657 know what the target machine might call it, it can find out by
1658 using this bit of code.
1667 The insides of a reloc code. The idea is that, eventually, there
1668 will be one enumerator for every type of relocation we ever do.
1669 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1670 return a howto pointer.
1672 This does mean that the application must determine the correct
1673 enumerator value; you can't get a howto pointer from a random set
1694 Basic absolute relocations of N bits.
1709 PC-relative relocations. Sometimes these are relative to the address
1710 of the relocation itself; sometimes they are relative to the start of
1711 the section containing the relocation. It depends on the specific target.
1713 The 24-bit relocation is used in some Intel 960 configurations.
1718 Section relative relocations. Some targets need this for DWARF2.
1721 BFD_RELOC_32_GOT_PCREL
1723 BFD_RELOC_16_GOT_PCREL
1725 BFD_RELOC_8_GOT_PCREL
1731 BFD_RELOC_LO16_GOTOFF
1733 BFD_RELOC_HI16_GOTOFF
1735 BFD_RELOC_HI16_S_GOTOFF
1739 BFD_RELOC_64_PLT_PCREL
1741 BFD_RELOC_32_PLT_PCREL
1743 BFD_RELOC_24_PLT_PCREL
1745 BFD_RELOC_16_PLT_PCREL
1747 BFD_RELOC_8_PLT_PCREL
1755 BFD_RELOC_LO16_PLTOFF
1757 BFD_RELOC_HI16_PLTOFF
1759 BFD_RELOC_HI16_S_PLTOFF
1773 BFD_RELOC_68K_GLOB_DAT
1775 BFD_RELOC_68K_JMP_SLOT
1777 BFD_RELOC_68K_RELATIVE
1779 BFD_RELOC_68K_TLS_GD32
1781 BFD_RELOC_68K_TLS_GD16
1783 BFD_RELOC_68K_TLS_GD8
1785 BFD_RELOC_68K_TLS_LDM32
1787 BFD_RELOC_68K_TLS_LDM16
1789 BFD_RELOC_68K_TLS_LDM8
1791 BFD_RELOC_68K_TLS_LDO32
1793 BFD_RELOC_68K_TLS_LDO16
1795 BFD_RELOC_68K_TLS_LDO8
1797 BFD_RELOC_68K_TLS_IE32
1799 BFD_RELOC_68K_TLS_IE16
1801 BFD_RELOC_68K_TLS_IE8
1803 BFD_RELOC_68K_TLS_LE32
1805 BFD_RELOC_68K_TLS_LE16
1807 BFD_RELOC_68K_TLS_LE8
1809 Relocations used by 68K ELF.
1812 BFD_RELOC_32_BASEREL
1814 BFD_RELOC_16_BASEREL
1816 BFD_RELOC_LO16_BASEREL
1818 BFD_RELOC_HI16_BASEREL
1820 BFD_RELOC_HI16_S_BASEREL
1826 Linkage-table relative.
1831 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1834 BFD_RELOC_32_PCREL_S2
1836 BFD_RELOC_16_PCREL_S2
1838 BFD_RELOC_23_PCREL_S2
1840 These PC-relative relocations are stored as word displacements --
1841 i.e., byte displacements shifted right two bits. The 30-bit word
1842 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1843 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1844 signed 16-bit displacement is used on the MIPS, and the 23-bit
1845 displacement is used on the Alpha.
1852 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1853 the target word. These are used on the SPARC.
1860 For systems that allocate a Global Pointer register, these are
1861 displacements off that register. These relocation types are
1862 handled specially, because the value the register will have is
1863 decided relatively late.
1866 BFD_RELOC_I960_CALLJ
1868 Reloc types used for i960/b.out.
1873 BFD_RELOC_SPARC_WDISP22
1879 BFD_RELOC_SPARC_GOT10
1881 BFD_RELOC_SPARC_GOT13
1883 BFD_RELOC_SPARC_GOT22
1885 BFD_RELOC_SPARC_PC10
1887 BFD_RELOC_SPARC_PC22
1889 BFD_RELOC_SPARC_WPLT30
1891 BFD_RELOC_SPARC_COPY
1893 BFD_RELOC_SPARC_GLOB_DAT
1895 BFD_RELOC_SPARC_JMP_SLOT
1897 BFD_RELOC_SPARC_RELATIVE
1899 BFD_RELOC_SPARC_UA16
1901 BFD_RELOC_SPARC_UA32
1903 BFD_RELOC_SPARC_UA64
1905 BFD_RELOC_SPARC_GOTDATA_HIX22
1907 BFD_RELOC_SPARC_GOTDATA_LOX10
1909 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1911 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1913 BFD_RELOC_SPARC_GOTDATA_OP
1915 BFD_RELOC_SPARC_JMP_IREL
1917 BFD_RELOC_SPARC_IRELATIVE
1919 SPARC ELF relocations. There is probably some overlap with other
1920 relocation types already defined.
1923 BFD_RELOC_SPARC_BASE13
1925 BFD_RELOC_SPARC_BASE22
1927 I think these are specific to SPARC a.out (e.g., Sun 4).
1937 BFD_RELOC_SPARC_OLO10
1939 BFD_RELOC_SPARC_HH22
1941 BFD_RELOC_SPARC_HM10
1943 BFD_RELOC_SPARC_LM22
1945 BFD_RELOC_SPARC_PC_HH22
1947 BFD_RELOC_SPARC_PC_HM10
1949 BFD_RELOC_SPARC_PC_LM22
1951 BFD_RELOC_SPARC_WDISP16
1953 BFD_RELOC_SPARC_WDISP19
1961 BFD_RELOC_SPARC_DISP64
1964 BFD_RELOC_SPARC_PLT32
1966 BFD_RELOC_SPARC_PLT64
1968 BFD_RELOC_SPARC_HIX22
1970 BFD_RELOC_SPARC_LOX10
1978 BFD_RELOC_SPARC_REGISTER
1982 BFD_RELOC_SPARC_SIZE32
1984 BFD_RELOC_SPARC_SIZE64
1986 BFD_RELOC_SPARC_WDISP10
1991 BFD_RELOC_SPARC_REV32
1993 SPARC little endian relocation
1995 BFD_RELOC_SPARC_TLS_GD_HI22
1997 BFD_RELOC_SPARC_TLS_GD_LO10
1999 BFD_RELOC_SPARC_TLS_GD_ADD
2001 BFD_RELOC_SPARC_TLS_GD_CALL
2003 BFD_RELOC_SPARC_TLS_LDM_HI22
2005 BFD_RELOC_SPARC_TLS_LDM_LO10
2007 BFD_RELOC_SPARC_TLS_LDM_ADD
2009 BFD_RELOC_SPARC_TLS_LDM_CALL
2011 BFD_RELOC_SPARC_TLS_LDO_HIX22
2013 BFD_RELOC_SPARC_TLS_LDO_LOX10
2015 BFD_RELOC_SPARC_TLS_LDO_ADD
2017 BFD_RELOC_SPARC_TLS_IE_HI22
2019 BFD_RELOC_SPARC_TLS_IE_LO10
2021 BFD_RELOC_SPARC_TLS_IE_LD
2023 BFD_RELOC_SPARC_TLS_IE_LDX
2025 BFD_RELOC_SPARC_TLS_IE_ADD
2027 BFD_RELOC_SPARC_TLS_LE_HIX22
2029 BFD_RELOC_SPARC_TLS_LE_LOX10
2031 BFD_RELOC_SPARC_TLS_DTPMOD32
2033 BFD_RELOC_SPARC_TLS_DTPMOD64
2035 BFD_RELOC_SPARC_TLS_DTPOFF32
2037 BFD_RELOC_SPARC_TLS_DTPOFF64
2039 BFD_RELOC_SPARC_TLS_TPOFF32
2041 BFD_RELOC_SPARC_TLS_TPOFF64
2043 SPARC TLS relocations
2052 BFD_RELOC_SPU_IMM10W
2056 BFD_RELOC_SPU_IMM16W
2060 BFD_RELOC_SPU_PCREL9a
2062 BFD_RELOC_SPU_PCREL9b
2064 BFD_RELOC_SPU_PCREL16
2074 BFD_RELOC_SPU_ADD_PIC
2079 BFD_RELOC_ALPHA_GPDISP_HI16
2081 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2082 "addend" in some special way.
2083 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2084 writing; when reading, it will be the absolute section symbol. The
2085 addend is the displacement in bytes of the "lda" instruction from
2086 the "ldah" instruction (which is at the address of this reloc).
2088 BFD_RELOC_ALPHA_GPDISP_LO16
2090 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2091 with GPDISP_HI16 relocs. The addend is ignored when writing the
2092 relocations out, and is filled in with the file's GP value on
2093 reading, for convenience.
2096 BFD_RELOC_ALPHA_GPDISP
2098 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2099 relocation except that there is no accompanying GPDISP_LO16
2103 BFD_RELOC_ALPHA_LITERAL
2105 BFD_RELOC_ALPHA_ELF_LITERAL
2107 BFD_RELOC_ALPHA_LITUSE
2109 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2110 the assembler turns it into a LDQ instruction to load the address of
2111 the symbol, and then fills in a register in the real instruction.
2113 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2114 section symbol. The addend is ignored when writing, but is filled
2115 in with the file's GP value on reading, for convenience, as with the
2118 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2119 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2120 but it generates output not based on the position within the .got
2121 section, but relative to the GP value chosen for the file during the
2124 The LITUSE reloc, on the instruction using the loaded address, gives
2125 information to the linker that it might be able to use to optimize
2126 away some literal section references. The symbol is ignored (read
2127 as the absolute section symbol), and the "addend" indicates the type
2128 of instruction using the register:
2129 1 - "memory" fmt insn
2130 2 - byte-manipulation (byte offset reg)
2131 3 - jsr (target of branch)
2134 BFD_RELOC_ALPHA_HINT
2136 The HINT relocation indicates a value that should be filled into the
2137 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2138 prediction logic which may be provided on some processors.
2141 BFD_RELOC_ALPHA_LINKAGE
2143 The LINKAGE relocation outputs a linkage pair in the object file,
2144 which is filled by the linker.
2147 BFD_RELOC_ALPHA_CODEADDR
2149 The CODEADDR relocation outputs a STO_CA in the object file,
2150 which is filled by the linker.
2153 BFD_RELOC_ALPHA_GPREL_HI16
2155 BFD_RELOC_ALPHA_GPREL_LO16
2157 The GPREL_HI/LO relocations together form a 32-bit offset from the
2161 BFD_RELOC_ALPHA_BRSGP
2163 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2164 share a common GP, and the target address is adjusted for
2165 STO_ALPHA_STD_GPLOAD.
2170 The NOP relocation outputs a NOP if the longword displacement
2171 between two procedure entry points is < 2^21.
2176 The BSR relocation outputs a BSR if the longword displacement
2177 between two procedure entry points is < 2^21.
2182 The LDA relocation outputs a LDA if the longword displacement
2183 between two procedure entry points is < 2^16.
2188 The BOH relocation outputs a BSR if the longword displacement
2189 between two procedure entry points is < 2^21, or else a hint.
2192 BFD_RELOC_ALPHA_TLSGD
2194 BFD_RELOC_ALPHA_TLSLDM
2196 BFD_RELOC_ALPHA_DTPMOD64
2198 BFD_RELOC_ALPHA_GOTDTPREL16
2200 BFD_RELOC_ALPHA_DTPREL64
2202 BFD_RELOC_ALPHA_DTPREL_HI16
2204 BFD_RELOC_ALPHA_DTPREL_LO16
2206 BFD_RELOC_ALPHA_DTPREL16
2208 BFD_RELOC_ALPHA_GOTTPREL16
2210 BFD_RELOC_ALPHA_TPREL64
2212 BFD_RELOC_ALPHA_TPREL_HI16
2214 BFD_RELOC_ALPHA_TPREL_LO16
2216 BFD_RELOC_ALPHA_TPREL16
2218 Alpha thread-local storage relocations.
2223 BFD_RELOC_MICROMIPS_JMP
2225 The MIPS jump instruction.
2228 BFD_RELOC_MIPS16_JMP
2230 The MIPS16 jump instruction.
2233 BFD_RELOC_MIPS16_GPREL
2235 MIPS16 GP relative reloc.
2240 High 16 bits of 32-bit value; simple reloc.
2245 High 16 bits of 32-bit value but the low 16 bits will be sign
2246 extended and added to form the final result. If the low 16
2247 bits form a negative number, we need to add one to the high value
2248 to compensate for the borrow when the low bits are added.
2256 BFD_RELOC_HI16_PCREL
2258 High 16 bits of 32-bit pc-relative value
2260 BFD_RELOC_HI16_S_PCREL
2262 High 16 bits of 32-bit pc-relative value, adjusted
2264 BFD_RELOC_LO16_PCREL
2266 Low 16 bits of pc-relative value
2269 BFD_RELOC_MIPS16_GOT16
2271 BFD_RELOC_MIPS16_CALL16
2273 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2274 16-bit immediate fields
2276 BFD_RELOC_MIPS16_HI16
2278 MIPS16 high 16 bits of 32-bit value.
2280 BFD_RELOC_MIPS16_HI16_S
2282 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2283 extended and added to form the final result. If the low 16
2284 bits form a negative number, we need to add one to the high value
2285 to compensate for the borrow when the low bits are added.
2287 BFD_RELOC_MIPS16_LO16
2292 BFD_RELOC_MIPS16_TLS_GD
2294 BFD_RELOC_MIPS16_TLS_LDM
2296 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2298 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2300 BFD_RELOC_MIPS16_TLS_GOTTPREL
2302 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2304 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2306 MIPS16 TLS relocations
2309 BFD_RELOC_MIPS_LITERAL
2311 BFD_RELOC_MICROMIPS_LITERAL
2313 Relocation against a MIPS literal section.
2316 BFD_RELOC_MICROMIPS_7_PCREL_S1
2318 BFD_RELOC_MICROMIPS_10_PCREL_S1
2320 BFD_RELOC_MICROMIPS_16_PCREL_S1
2322 microMIPS PC-relative relocations.
2325 BFD_RELOC_MIPS16_16_PCREL_S1
2327 MIPS16 PC-relative relocation.
2330 BFD_RELOC_MIPS_21_PCREL_S2
2332 BFD_RELOC_MIPS_26_PCREL_S2
2334 BFD_RELOC_MIPS_18_PCREL_S3
2336 BFD_RELOC_MIPS_19_PCREL_S2
2338 MIPS PC-relative relocations.
2341 BFD_RELOC_MICROMIPS_GPREL16
2343 BFD_RELOC_MICROMIPS_HI16
2345 BFD_RELOC_MICROMIPS_HI16_S
2347 BFD_RELOC_MICROMIPS_LO16
2349 microMIPS versions of generic BFD relocs.
2352 BFD_RELOC_MIPS_GOT16
2354 BFD_RELOC_MICROMIPS_GOT16
2356 BFD_RELOC_MIPS_CALL16
2358 BFD_RELOC_MICROMIPS_CALL16
2360 BFD_RELOC_MIPS_GOT_HI16
2362 BFD_RELOC_MICROMIPS_GOT_HI16
2364 BFD_RELOC_MIPS_GOT_LO16
2366 BFD_RELOC_MICROMIPS_GOT_LO16
2368 BFD_RELOC_MIPS_CALL_HI16
2370 BFD_RELOC_MICROMIPS_CALL_HI16
2372 BFD_RELOC_MIPS_CALL_LO16
2374 BFD_RELOC_MICROMIPS_CALL_LO16
2378 BFD_RELOC_MICROMIPS_SUB
2380 BFD_RELOC_MIPS_GOT_PAGE
2382 BFD_RELOC_MICROMIPS_GOT_PAGE
2384 BFD_RELOC_MIPS_GOT_OFST
2386 BFD_RELOC_MICROMIPS_GOT_OFST
2388 BFD_RELOC_MIPS_GOT_DISP
2390 BFD_RELOC_MICROMIPS_GOT_DISP
2392 BFD_RELOC_MIPS_SHIFT5
2394 BFD_RELOC_MIPS_SHIFT6
2396 BFD_RELOC_MIPS_INSERT_A
2398 BFD_RELOC_MIPS_INSERT_B
2400 BFD_RELOC_MIPS_DELETE
2402 BFD_RELOC_MIPS_HIGHEST
2404 BFD_RELOC_MICROMIPS_HIGHEST
2406 BFD_RELOC_MIPS_HIGHER
2408 BFD_RELOC_MICROMIPS_HIGHER
2410 BFD_RELOC_MIPS_SCN_DISP
2412 BFD_RELOC_MICROMIPS_SCN_DISP
2414 BFD_RELOC_MIPS_REL16
2416 BFD_RELOC_MIPS_RELGOT
2420 BFD_RELOC_MICROMIPS_JALR
2422 BFD_RELOC_MIPS_TLS_DTPMOD32
2424 BFD_RELOC_MIPS_TLS_DTPREL32
2426 BFD_RELOC_MIPS_TLS_DTPMOD64
2428 BFD_RELOC_MIPS_TLS_DTPREL64
2430 BFD_RELOC_MIPS_TLS_GD
2432 BFD_RELOC_MICROMIPS_TLS_GD
2434 BFD_RELOC_MIPS_TLS_LDM
2436 BFD_RELOC_MICROMIPS_TLS_LDM
2438 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2440 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2442 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2444 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2446 BFD_RELOC_MIPS_TLS_GOTTPREL
2448 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2450 BFD_RELOC_MIPS_TLS_TPREL32
2452 BFD_RELOC_MIPS_TLS_TPREL64
2454 BFD_RELOC_MIPS_TLS_TPREL_HI16
2456 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2458 BFD_RELOC_MIPS_TLS_TPREL_LO16
2460 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2464 MIPS ELF relocations.
2470 BFD_RELOC_MIPS_JUMP_SLOT
2472 MIPS ELF relocations (VxWorks and PLT extensions).
2476 BFD_RELOC_MOXIE_10_PCREL
2478 Moxie ELF relocations.
2490 FT32 ELF relocations.
2494 BFD_RELOC_FRV_LABEL16
2496 BFD_RELOC_FRV_LABEL24
2502 BFD_RELOC_FRV_GPREL12
2504 BFD_RELOC_FRV_GPRELU12
2506 BFD_RELOC_FRV_GPREL32
2508 BFD_RELOC_FRV_GPRELHI
2510 BFD_RELOC_FRV_GPRELLO
2518 BFD_RELOC_FRV_FUNCDESC
2520 BFD_RELOC_FRV_FUNCDESC_GOT12
2522 BFD_RELOC_FRV_FUNCDESC_GOTHI
2524 BFD_RELOC_FRV_FUNCDESC_GOTLO
2526 BFD_RELOC_FRV_FUNCDESC_VALUE
2528 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2530 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2532 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2534 BFD_RELOC_FRV_GOTOFF12
2536 BFD_RELOC_FRV_GOTOFFHI
2538 BFD_RELOC_FRV_GOTOFFLO
2540 BFD_RELOC_FRV_GETTLSOFF
2542 BFD_RELOC_FRV_TLSDESC_VALUE
2544 BFD_RELOC_FRV_GOTTLSDESC12
2546 BFD_RELOC_FRV_GOTTLSDESCHI
2548 BFD_RELOC_FRV_GOTTLSDESCLO
2550 BFD_RELOC_FRV_TLSMOFF12
2552 BFD_RELOC_FRV_TLSMOFFHI
2554 BFD_RELOC_FRV_TLSMOFFLO
2556 BFD_RELOC_FRV_GOTTLSOFF12
2558 BFD_RELOC_FRV_GOTTLSOFFHI
2560 BFD_RELOC_FRV_GOTTLSOFFLO
2562 BFD_RELOC_FRV_TLSOFF
2564 BFD_RELOC_FRV_TLSDESC_RELAX
2566 BFD_RELOC_FRV_GETTLSOFF_RELAX
2568 BFD_RELOC_FRV_TLSOFF_RELAX
2570 BFD_RELOC_FRV_TLSMOFF
2572 Fujitsu Frv Relocations.
2576 BFD_RELOC_MN10300_GOTOFF24
2578 This is a 24bit GOT-relative reloc for the mn10300.
2580 BFD_RELOC_MN10300_GOT32
2582 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2585 BFD_RELOC_MN10300_GOT24
2587 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2590 BFD_RELOC_MN10300_GOT16
2592 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2595 BFD_RELOC_MN10300_COPY
2597 Copy symbol at runtime.
2599 BFD_RELOC_MN10300_GLOB_DAT
2603 BFD_RELOC_MN10300_JMP_SLOT
2607 BFD_RELOC_MN10300_RELATIVE
2609 Adjust by program base.
2611 BFD_RELOC_MN10300_SYM_DIFF
2613 Together with another reloc targeted at the same location,
2614 allows for a value that is the difference of two symbols
2615 in the same section.
2617 BFD_RELOC_MN10300_ALIGN
2619 The addend of this reloc is an alignment power that must
2620 be honoured at the offset's location, regardless of linker
2623 BFD_RELOC_MN10300_TLS_GD
2625 BFD_RELOC_MN10300_TLS_LD
2627 BFD_RELOC_MN10300_TLS_LDO
2629 BFD_RELOC_MN10300_TLS_GOTIE
2631 BFD_RELOC_MN10300_TLS_IE
2633 BFD_RELOC_MN10300_TLS_LE
2635 BFD_RELOC_MN10300_TLS_DTPMOD
2637 BFD_RELOC_MN10300_TLS_DTPOFF
2639 BFD_RELOC_MN10300_TLS_TPOFF
2641 Various TLS-related relocations.
2643 BFD_RELOC_MN10300_32_PCREL
2645 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2648 BFD_RELOC_MN10300_16_PCREL
2650 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2661 BFD_RELOC_386_GLOB_DAT
2663 BFD_RELOC_386_JUMP_SLOT
2665 BFD_RELOC_386_RELATIVE
2667 BFD_RELOC_386_GOTOFF
2671 BFD_RELOC_386_TLS_TPOFF
2673 BFD_RELOC_386_TLS_IE
2675 BFD_RELOC_386_TLS_GOTIE
2677 BFD_RELOC_386_TLS_LE
2679 BFD_RELOC_386_TLS_GD
2681 BFD_RELOC_386_TLS_LDM
2683 BFD_RELOC_386_TLS_LDO_32
2685 BFD_RELOC_386_TLS_IE_32
2687 BFD_RELOC_386_TLS_LE_32
2689 BFD_RELOC_386_TLS_DTPMOD32
2691 BFD_RELOC_386_TLS_DTPOFF32
2693 BFD_RELOC_386_TLS_TPOFF32
2695 BFD_RELOC_386_TLS_GOTDESC
2697 BFD_RELOC_386_TLS_DESC_CALL
2699 BFD_RELOC_386_TLS_DESC
2701 BFD_RELOC_386_IRELATIVE
2703 BFD_RELOC_386_GOT32X
2705 i386/elf relocations
2708 BFD_RELOC_X86_64_GOT32
2710 BFD_RELOC_X86_64_PLT32
2712 BFD_RELOC_X86_64_COPY
2714 BFD_RELOC_X86_64_GLOB_DAT
2716 BFD_RELOC_X86_64_JUMP_SLOT
2718 BFD_RELOC_X86_64_RELATIVE
2720 BFD_RELOC_X86_64_GOTPCREL
2722 BFD_RELOC_X86_64_32S
2724 BFD_RELOC_X86_64_DTPMOD64
2726 BFD_RELOC_X86_64_DTPOFF64
2728 BFD_RELOC_X86_64_TPOFF64
2730 BFD_RELOC_X86_64_TLSGD
2732 BFD_RELOC_X86_64_TLSLD
2734 BFD_RELOC_X86_64_DTPOFF32
2736 BFD_RELOC_X86_64_GOTTPOFF
2738 BFD_RELOC_X86_64_TPOFF32
2740 BFD_RELOC_X86_64_GOTOFF64
2742 BFD_RELOC_X86_64_GOTPC32
2744 BFD_RELOC_X86_64_GOT64
2746 BFD_RELOC_X86_64_GOTPCREL64
2748 BFD_RELOC_X86_64_GOTPC64
2750 BFD_RELOC_X86_64_GOTPLT64
2752 BFD_RELOC_X86_64_PLTOFF64
2754 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2756 BFD_RELOC_X86_64_TLSDESC_CALL
2758 BFD_RELOC_X86_64_TLSDESC
2760 BFD_RELOC_X86_64_IRELATIVE
2762 BFD_RELOC_X86_64_PC32_BND
2764 BFD_RELOC_X86_64_PLT32_BND
2766 BFD_RELOC_X86_64_GOTPCRELX
2768 BFD_RELOC_X86_64_REX_GOTPCRELX
2770 x86-64/elf relocations
2773 BFD_RELOC_NS32K_IMM_8
2775 BFD_RELOC_NS32K_IMM_16
2777 BFD_RELOC_NS32K_IMM_32
2779 BFD_RELOC_NS32K_IMM_8_PCREL
2781 BFD_RELOC_NS32K_IMM_16_PCREL
2783 BFD_RELOC_NS32K_IMM_32_PCREL
2785 BFD_RELOC_NS32K_DISP_8
2787 BFD_RELOC_NS32K_DISP_16
2789 BFD_RELOC_NS32K_DISP_32
2791 BFD_RELOC_NS32K_DISP_8_PCREL
2793 BFD_RELOC_NS32K_DISP_16_PCREL
2795 BFD_RELOC_NS32K_DISP_32_PCREL
2800 BFD_RELOC_PDP11_DISP_8_PCREL
2802 BFD_RELOC_PDP11_DISP_6_PCREL
2807 BFD_RELOC_PJ_CODE_HI16
2809 BFD_RELOC_PJ_CODE_LO16
2811 BFD_RELOC_PJ_CODE_DIR16
2813 BFD_RELOC_PJ_CODE_DIR32
2815 BFD_RELOC_PJ_CODE_REL16
2817 BFD_RELOC_PJ_CODE_REL32
2819 Picojava relocs. Not all of these appear in object files.
2830 BFD_RELOC_PPC_B16_BRTAKEN
2832 BFD_RELOC_PPC_B16_BRNTAKEN
2836 BFD_RELOC_PPC_BA16_BRTAKEN
2838 BFD_RELOC_PPC_BA16_BRNTAKEN
2842 BFD_RELOC_PPC_GLOB_DAT
2844 BFD_RELOC_PPC_JMP_SLOT
2846 BFD_RELOC_PPC_RELATIVE
2848 BFD_RELOC_PPC_LOCAL24PC
2850 BFD_RELOC_PPC_EMB_NADDR32
2852 BFD_RELOC_PPC_EMB_NADDR16
2854 BFD_RELOC_PPC_EMB_NADDR16_LO
2856 BFD_RELOC_PPC_EMB_NADDR16_HI
2858 BFD_RELOC_PPC_EMB_NADDR16_HA
2860 BFD_RELOC_PPC_EMB_SDAI16
2862 BFD_RELOC_PPC_EMB_SDA2I16
2864 BFD_RELOC_PPC_EMB_SDA2REL
2866 BFD_RELOC_PPC_EMB_SDA21
2868 BFD_RELOC_PPC_EMB_MRKREF
2870 BFD_RELOC_PPC_EMB_RELSEC16
2872 BFD_RELOC_PPC_EMB_RELST_LO
2874 BFD_RELOC_PPC_EMB_RELST_HI
2876 BFD_RELOC_PPC_EMB_RELST_HA
2878 BFD_RELOC_PPC_EMB_BIT_FLD
2880 BFD_RELOC_PPC_EMB_RELSDA
2882 BFD_RELOC_PPC_VLE_REL8
2884 BFD_RELOC_PPC_VLE_REL15
2886 BFD_RELOC_PPC_VLE_REL24
2888 BFD_RELOC_PPC_VLE_LO16A
2890 BFD_RELOC_PPC_VLE_LO16D
2892 BFD_RELOC_PPC_VLE_HI16A
2894 BFD_RELOC_PPC_VLE_HI16D
2896 BFD_RELOC_PPC_VLE_HA16A
2898 BFD_RELOC_PPC_VLE_HA16D
2900 BFD_RELOC_PPC_VLE_SDA21
2902 BFD_RELOC_PPC_VLE_SDA21_LO
2904 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2906 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2908 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2910 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2912 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2914 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2916 BFD_RELOC_PPC_16DX_HA
2918 BFD_RELOC_PPC_REL16DX_HA
2920 BFD_RELOC_PPC64_HIGHER
2922 BFD_RELOC_PPC64_HIGHER_S
2924 BFD_RELOC_PPC64_HIGHEST
2926 BFD_RELOC_PPC64_HIGHEST_S
2928 BFD_RELOC_PPC64_TOC16_LO
2930 BFD_RELOC_PPC64_TOC16_HI
2932 BFD_RELOC_PPC64_TOC16_HA
2936 BFD_RELOC_PPC64_PLTGOT16
2938 BFD_RELOC_PPC64_PLTGOT16_LO
2940 BFD_RELOC_PPC64_PLTGOT16_HI
2942 BFD_RELOC_PPC64_PLTGOT16_HA
2944 BFD_RELOC_PPC64_ADDR16_DS
2946 BFD_RELOC_PPC64_ADDR16_LO_DS
2948 BFD_RELOC_PPC64_GOT16_DS
2950 BFD_RELOC_PPC64_GOT16_LO_DS
2952 BFD_RELOC_PPC64_PLT16_LO_DS
2954 BFD_RELOC_PPC64_SECTOFF_DS
2956 BFD_RELOC_PPC64_SECTOFF_LO_DS
2958 BFD_RELOC_PPC64_TOC16_DS
2960 BFD_RELOC_PPC64_TOC16_LO_DS
2962 BFD_RELOC_PPC64_PLTGOT16_DS
2964 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2966 BFD_RELOC_PPC64_ADDR16_HIGH
2968 BFD_RELOC_PPC64_ADDR16_HIGHA
2970 BFD_RELOC_PPC64_ADDR64_LOCAL
2972 BFD_RELOC_PPC64_ENTRY
2974 Power(rs6000) and PowerPC relocations.
2983 BFD_RELOC_PPC_DTPMOD
2985 BFD_RELOC_PPC_TPREL16
2987 BFD_RELOC_PPC_TPREL16_LO
2989 BFD_RELOC_PPC_TPREL16_HI
2991 BFD_RELOC_PPC_TPREL16_HA
2995 BFD_RELOC_PPC_DTPREL16
2997 BFD_RELOC_PPC_DTPREL16_LO
2999 BFD_RELOC_PPC_DTPREL16_HI
3001 BFD_RELOC_PPC_DTPREL16_HA
3003 BFD_RELOC_PPC_DTPREL
3005 BFD_RELOC_PPC_GOT_TLSGD16
3007 BFD_RELOC_PPC_GOT_TLSGD16_LO
3009 BFD_RELOC_PPC_GOT_TLSGD16_HI
3011 BFD_RELOC_PPC_GOT_TLSGD16_HA
3013 BFD_RELOC_PPC_GOT_TLSLD16
3015 BFD_RELOC_PPC_GOT_TLSLD16_LO
3017 BFD_RELOC_PPC_GOT_TLSLD16_HI
3019 BFD_RELOC_PPC_GOT_TLSLD16_HA
3021 BFD_RELOC_PPC_GOT_TPREL16
3023 BFD_RELOC_PPC_GOT_TPREL16_LO
3025 BFD_RELOC_PPC_GOT_TPREL16_HI
3027 BFD_RELOC_PPC_GOT_TPREL16_HA
3029 BFD_RELOC_PPC_GOT_DTPREL16
3031 BFD_RELOC_PPC_GOT_DTPREL16_LO
3033 BFD_RELOC_PPC_GOT_DTPREL16_HI
3035 BFD_RELOC_PPC_GOT_DTPREL16_HA
3037 BFD_RELOC_PPC64_TPREL16_DS
3039 BFD_RELOC_PPC64_TPREL16_LO_DS
3041 BFD_RELOC_PPC64_TPREL16_HIGHER
3043 BFD_RELOC_PPC64_TPREL16_HIGHERA
3045 BFD_RELOC_PPC64_TPREL16_HIGHEST
3047 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3049 BFD_RELOC_PPC64_DTPREL16_DS
3051 BFD_RELOC_PPC64_DTPREL16_LO_DS
3053 BFD_RELOC_PPC64_DTPREL16_HIGHER
3055 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3057 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3059 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3061 BFD_RELOC_PPC64_TPREL16_HIGH
3063 BFD_RELOC_PPC64_TPREL16_HIGHA
3065 BFD_RELOC_PPC64_DTPREL16_HIGH
3067 BFD_RELOC_PPC64_DTPREL16_HIGHA
3069 PowerPC and PowerPC64 thread-local storage relocations.
3074 IBM 370/390 relocations
3079 The type of reloc used to build a constructor table - at the moment
3080 probably a 32 bit wide absolute relocation, but the target can choose.
3081 It generally does map to one of the other relocation types.
3084 BFD_RELOC_ARM_PCREL_BRANCH
3086 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3087 not stored in the instruction.
3089 BFD_RELOC_ARM_PCREL_BLX
3091 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3092 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3093 field in the instruction.
3095 BFD_RELOC_THUMB_PCREL_BLX
3097 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3098 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3099 field in the instruction.
3101 BFD_RELOC_ARM_PCREL_CALL
3103 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3105 BFD_RELOC_ARM_PCREL_JUMP
3107 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3110 BFD_RELOC_THUMB_PCREL_BRANCH7
3112 BFD_RELOC_THUMB_PCREL_BRANCH9
3114 BFD_RELOC_THUMB_PCREL_BRANCH12
3116 BFD_RELOC_THUMB_PCREL_BRANCH20
3118 BFD_RELOC_THUMB_PCREL_BRANCH23
3120 BFD_RELOC_THUMB_PCREL_BRANCH25
3122 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3123 The lowest bit must be zero and is not stored in the instruction.
3124 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3125 "nn" one smaller in all cases. Note further that BRANCH23
3126 corresponds to R_ARM_THM_CALL.
3129 BFD_RELOC_ARM_OFFSET_IMM
3131 12-bit immediate offset, used in ARM-format ldr and str instructions.
3134 BFD_RELOC_ARM_THUMB_OFFSET
3136 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3139 BFD_RELOC_ARM_TARGET1
3141 Pc-relative or absolute relocation depending on target. Used for
3142 entries in .init_array sections.
3144 BFD_RELOC_ARM_ROSEGREL32
3146 Read-only segment base relative address.
3148 BFD_RELOC_ARM_SBREL32
3150 Data segment base relative address.
3152 BFD_RELOC_ARM_TARGET2
3154 This reloc is used for references to RTTI data from exception handling
3155 tables. The actual definition depends on the target. It may be a
3156 pc-relative or some form of GOT-indirect relocation.
3158 BFD_RELOC_ARM_PREL31
3160 31-bit PC relative address.
3166 BFD_RELOC_ARM_MOVW_PCREL
3168 BFD_RELOC_ARM_MOVT_PCREL
3170 BFD_RELOC_ARM_THUMB_MOVW
3172 BFD_RELOC_ARM_THUMB_MOVT
3174 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3176 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3178 Low and High halfword relocations for MOVW and MOVT instructions.
3181 BFD_RELOC_ARM_JUMP_SLOT
3183 BFD_RELOC_ARM_GLOB_DAT
3189 BFD_RELOC_ARM_RELATIVE
3191 BFD_RELOC_ARM_GOTOFF
3195 BFD_RELOC_ARM_GOT_PREL
3197 Relocations for setting up GOTs and PLTs for shared libraries.
3200 BFD_RELOC_ARM_TLS_GD32
3202 BFD_RELOC_ARM_TLS_LDO32
3204 BFD_RELOC_ARM_TLS_LDM32
3206 BFD_RELOC_ARM_TLS_DTPOFF32
3208 BFD_RELOC_ARM_TLS_DTPMOD32
3210 BFD_RELOC_ARM_TLS_TPOFF32
3212 BFD_RELOC_ARM_TLS_IE32
3214 BFD_RELOC_ARM_TLS_LE32
3216 BFD_RELOC_ARM_TLS_GOTDESC
3218 BFD_RELOC_ARM_TLS_CALL
3220 BFD_RELOC_ARM_THM_TLS_CALL
3222 BFD_RELOC_ARM_TLS_DESCSEQ
3224 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3226 BFD_RELOC_ARM_TLS_DESC
3228 ARM thread-local storage relocations.
3231 BFD_RELOC_ARM_ALU_PC_G0_NC
3233 BFD_RELOC_ARM_ALU_PC_G0
3235 BFD_RELOC_ARM_ALU_PC_G1_NC
3237 BFD_RELOC_ARM_ALU_PC_G1
3239 BFD_RELOC_ARM_ALU_PC_G2
3241 BFD_RELOC_ARM_LDR_PC_G0
3243 BFD_RELOC_ARM_LDR_PC_G1
3245 BFD_RELOC_ARM_LDR_PC_G2
3247 BFD_RELOC_ARM_LDRS_PC_G0
3249 BFD_RELOC_ARM_LDRS_PC_G1
3251 BFD_RELOC_ARM_LDRS_PC_G2
3253 BFD_RELOC_ARM_LDC_PC_G0
3255 BFD_RELOC_ARM_LDC_PC_G1
3257 BFD_RELOC_ARM_LDC_PC_G2
3259 BFD_RELOC_ARM_ALU_SB_G0_NC
3261 BFD_RELOC_ARM_ALU_SB_G0
3263 BFD_RELOC_ARM_ALU_SB_G1_NC
3265 BFD_RELOC_ARM_ALU_SB_G1
3267 BFD_RELOC_ARM_ALU_SB_G2
3269 BFD_RELOC_ARM_LDR_SB_G0
3271 BFD_RELOC_ARM_LDR_SB_G1
3273 BFD_RELOC_ARM_LDR_SB_G2
3275 BFD_RELOC_ARM_LDRS_SB_G0
3277 BFD_RELOC_ARM_LDRS_SB_G1
3279 BFD_RELOC_ARM_LDRS_SB_G2
3281 BFD_RELOC_ARM_LDC_SB_G0
3283 BFD_RELOC_ARM_LDC_SB_G1
3285 BFD_RELOC_ARM_LDC_SB_G2
3287 ARM group relocations.
3292 Annotation of BX instructions.
3295 BFD_RELOC_ARM_IRELATIVE
3297 ARM support for STT_GNU_IFUNC.
3300 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3302 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3304 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3306 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3308 Thumb1 relocations to support execute-only code.
3311 BFD_RELOC_ARM_IMMEDIATE
3313 BFD_RELOC_ARM_ADRL_IMMEDIATE
3315 BFD_RELOC_ARM_T32_IMMEDIATE
3317 BFD_RELOC_ARM_T32_ADD_IMM
3319 BFD_RELOC_ARM_T32_IMM12
3321 BFD_RELOC_ARM_T32_ADD_PC12
3323 BFD_RELOC_ARM_SHIFT_IMM
3333 BFD_RELOC_ARM_CP_OFF_IMM
3335 BFD_RELOC_ARM_CP_OFF_IMM_S2
3337 BFD_RELOC_ARM_T32_CP_OFF_IMM
3339 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3341 BFD_RELOC_ARM_ADR_IMM
3343 BFD_RELOC_ARM_LDR_IMM
3345 BFD_RELOC_ARM_LITERAL
3347 BFD_RELOC_ARM_IN_POOL
3349 BFD_RELOC_ARM_OFFSET_IMM8
3351 BFD_RELOC_ARM_T32_OFFSET_U8
3353 BFD_RELOC_ARM_T32_OFFSET_IMM
3355 BFD_RELOC_ARM_HWLITERAL
3357 BFD_RELOC_ARM_THUMB_ADD
3359 BFD_RELOC_ARM_THUMB_IMM
3361 BFD_RELOC_ARM_THUMB_SHIFT
3363 These relocs are only used within the ARM assembler. They are not
3364 (at present) written to any object files.
3367 BFD_RELOC_SH_PCDISP8BY2
3369 BFD_RELOC_SH_PCDISP12BY2
3377 BFD_RELOC_SH_DISP12BY2
3379 BFD_RELOC_SH_DISP12BY4
3381 BFD_RELOC_SH_DISP12BY8
3385 BFD_RELOC_SH_DISP20BY8
3389 BFD_RELOC_SH_IMM4BY2
3391 BFD_RELOC_SH_IMM4BY4
3395 BFD_RELOC_SH_IMM8BY2
3397 BFD_RELOC_SH_IMM8BY4
3399 BFD_RELOC_SH_PCRELIMM8BY2
3401 BFD_RELOC_SH_PCRELIMM8BY4
3403 BFD_RELOC_SH_SWITCH16
3405 BFD_RELOC_SH_SWITCH32
3419 BFD_RELOC_SH_LOOP_START
3421 BFD_RELOC_SH_LOOP_END
3425 BFD_RELOC_SH_GLOB_DAT
3427 BFD_RELOC_SH_JMP_SLOT
3429 BFD_RELOC_SH_RELATIVE
3433 BFD_RELOC_SH_GOT_LOW16
3435 BFD_RELOC_SH_GOT_MEDLOW16
3437 BFD_RELOC_SH_GOT_MEDHI16
3439 BFD_RELOC_SH_GOT_HI16
3441 BFD_RELOC_SH_GOTPLT_LOW16
3443 BFD_RELOC_SH_GOTPLT_MEDLOW16
3445 BFD_RELOC_SH_GOTPLT_MEDHI16
3447 BFD_RELOC_SH_GOTPLT_HI16
3449 BFD_RELOC_SH_PLT_LOW16
3451 BFD_RELOC_SH_PLT_MEDLOW16
3453 BFD_RELOC_SH_PLT_MEDHI16
3455 BFD_RELOC_SH_PLT_HI16
3457 BFD_RELOC_SH_GOTOFF_LOW16
3459 BFD_RELOC_SH_GOTOFF_MEDLOW16
3461 BFD_RELOC_SH_GOTOFF_MEDHI16
3463 BFD_RELOC_SH_GOTOFF_HI16
3465 BFD_RELOC_SH_GOTPC_LOW16
3467 BFD_RELOC_SH_GOTPC_MEDLOW16
3469 BFD_RELOC_SH_GOTPC_MEDHI16
3471 BFD_RELOC_SH_GOTPC_HI16
3475 BFD_RELOC_SH_GLOB_DAT64
3477 BFD_RELOC_SH_JMP_SLOT64
3479 BFD_RELOC_SH_RELATIVE64
3481 BFD_RELOC_SH_GOT10BY4
3483 BFD_RELOC_SH_GOT10BY8
3485 BFD_RELOC_SH_GOTPLT10BY4
3487 BFD_RELOC_SH_GOTPLT10BY8
3489 BFD_RELOC_SH_GOTPLT32
3491 BFD_RELOC_SH_SHMEDIA_CODE
3497 BFD_RELOC_SH_IMMS6BY32
3503 BFD_RELOC_SH_IMMS10BY2
3505 BFD_RELOC_SH_IMMS10BY4
3507 BFD_RELOC_SH_IMMS10BY8
3513 BFD_RELOC_SH_IMM_LOW16
3515 BFD_RELOC_SH_IMM_LOW16_PCREL
3517 BFD_RELOC_SH_IMM_MEDLOW16
3519 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3521 BFD_RELOC_SH_IMM_MEDHI16
3523 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3525 BFD_RELOC_SH_IMM_HI16
3527 BFD_RELOC_SH_IMM_HI16_PCREL
3531 BFD_RELOC_SH_TLS_GD_32
3533 BFD_RELOC_SH_TLS_LD_32
3535 BFD_RELOC_SH_TLS_LDO_32
3537 BFD_RELOC_SH_TLS_IE_32
3539 BFD_RELOC_SH_TLS_LE_32
3541 BFD_RELOC_SH_TLS_DTPMOD32
3543 BFD_RELOC_SH_TLS_DTPOFF32
3545 BFD_RELOC_SH_TLS_TPOFF32
3549 BFD_RELOC_SH_GOTOFF20
3551 BFD_RELOC_SH_GOTFUNCDESC
3553 BFD_RELOC_SH_GOTFUNCDESC20
3555 BFD_RELOC_SH_GOTOFFFUNCDESC
3557 BFD_RELOC_SH_GOTOFFFUNCDESC20
3559 BFD_RELOC_SH_FUNCDESC
3561 Renesas / SuperH SH relocs. Not all of these appear in object files.
3584 BFD_RELOC_ARC_SECTOFF
3586 BFD_RELOC_ARC_S21H_PCREL
3588 BFD_RELOC_ARC_S21W_PCREL
3590 BFD_RELOC_ARC_S25H_PCREL
3592 BFD_RELOC_ARC_S25W_PCREL
3596 BFD_RELOC_ARC_SDA_LDST
3598 BFD_RELOC_ARC_SDA_LDST1
3600 BFD_RELOC_ARC_SDA_LDST2
3602 BFD_RELOC_ARC_SDA16_LD
3604 BFD_RELOC_ARC_SDA16_LD1
3606 BFD_RELOC_ARC_SDA16_LD2
3608 BFD_RELOC_ARC_S13_PCREL
3614 BFD_RELOC_ARC_32_ME_S
3616 BFD_RELOC_ARC_N32_ME
3618 BFD_RELOC_ARC_SECTOFF_ME
3620 BFD_RELOC_ARC_SDA32_ME
3624 BFD_RELOC_AC_SECTOFF_U8
3626 BFD_RELOC_AC_SECTOFF_U8_1
3628 BFD_RELOC_AC_SECTOFF_U8_2
3630 BFD_RELOC_AC_SECTOFF_S9
3632 BFD_RELOC_AC_SECTOFF_S9_1
3634 BFD_RELOC_AC_SECTOFF_S9_2
3636 BFD_RELOC_ARC_SECTOFF_ME_1
3638 BFD_RELOC_ARC_SECTOFF_ME_2
3640 BFD_RELOC_ARC_SECTOFF_1
3642 BFD_RELOC_ARC_SECTOFF_2
3644 BFD_RELOC_ARC_SDA_12
3646 BFD_RELOC_ARC_SDA16_ST2
3648 BFD_RELOC_ARC_32_PCREL
3654 BFD_RELOC_ARC_GOTPC32
3660 BFD_RELOC_ARC_GLOB_DAT
3662 BFD_RELOC_ARC_JMP_SLOT
3664 BFD_RELOC_ARC_RELATIVE
3666 BFD_RELOC_ARC_GOTOFF
3670 BFD_RELOC_ARC_S21W_PCREL_PLT
3672 BFD_RELOC_ARC_S25H_PCREL_PLT
3674 BFD_RELOC_ARC_TLS_DTPMOD
3676 BFD_RELOC_ARC_TLS_TPOFF
3678 BFD_RELOC_ARC_TLS_GD_GOT
3680 BFD_RELOC_ARC_TLS_GD_LD
3682 BFD_RELOC_ARC_TLS_GD_CALL
3684 BFD_RELOC_ARC_TLS_IE_GOT
3686 BFD_RELOC_ARC_TLS_DTPOFF
3688 BFD_RELOC_ARC_TLS_DTPOFF_S9
3690 BFD_RELOC_ARC_TLS_LE_S9
3692 BFD_RELOC_ARC_TLS_LE_32
3694 BFD_RELOC_ARC_S25W_PCREL_PLT
3696 BFD_RELOC_ARC_S21H_PCREL_PLT
3698 BFD_RELOC_ARC_NPS_CMEM16
3700 BFD_RELOC_ARC_JLI_SECTOFF
3705 BFD_RELOC_BFIN_16_IMM
3707 ADI Blackfin 16 bit immediate absolute reloc.
3709 BFD_RELOC_BFIN_16_HIGH
3711 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3713 BFD_RELOC_BFIN_4_PCREL
3715 ADI Blackfin 'a' part of LSETUP.
3717 BFD_RELOC_BFIN_5_PCREL
3721 BFD_RELOC_BFIN_16_LOW
3723 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3725 BFD_RELOC_BFIN_10_PCREL
3729 BFD_RELOC_BFIN_11_PCREL
3731 ADI Blackfin 'b' part of LSETUP.
3733 BFD_RELOC_BFIN_12_PCREL_JUMP
3737 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3739 ADI Blackfin Short jump, pcrel.
3741 BFD_RELOC_BFIN_24_PCREL_CALL_X
3743 ADI Blackfin Call.x not implemented.
3745 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3747 ADI Blackfin Long Jump pcrel.
3749 BFD_RELOC_BFIN_GOT17M4
3751 BFD_RELOC_BFIN_GOTHI
3753 BFD_RELOC_BFIN_GOTLO
3755 BFD_RELOC_BFIN_FUNCDESC
3757 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3759 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3761 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3763 BFD_RELOC_BFIN_FUNCDESC_VALUE
3765 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3767 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3769 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3771 BFD_RELOC_BFIN_GOTOFF17M4
3773 BFD_RELOC_BFIN_GOTOFFHI
3775 BFD_RELOC_BFIN_GOTOFFLO
3777 ADI Blackfin FD-PIC relocations.
3781 ADI Blackfin GOT relocation.
3783 BFD_RELOC_BFIN_PLTPC
3785 ADI Blackfin PLTPC relocation.
3787 BFD_ARELOC_BFIN_PUSH
3789 ADI Blackfin arithmetic relocation.
3791 BFD_ARELOC_BFIN_CONST
3793 ADI Blackfin arithmetic relocation.
3797 ADI Blackfin arithmetic relocation.
3801 ADI Blackfin arithmetic relocation.
3803 BFD_ARELOC_BFIN_MULT
3805 ADI Blackfin arithmetic relocation.
3809 ADI Blackfin arithmetic relocation.
3813 ADI Blackfin arithmetic relocation.
3815 BFD_ARELOC_BFIN_LSHIFT
3817 ADI Blackfin arithmetic relocation.
3819 BFD_ARELOC_BFIN_RSHIFT
3821 ADI Blackfin arithmetic relocation.
3825 ADI Blackfin arithmetic relocation.
3829 ADI Blackfin arithmetic relocation.
3833 ADI Blackfin arithmetic relocation.
3835 BFD_ARELOC_BFIN_LAND
3837 ADI Blackfin arithmetic relocation.
3841 ADI Blackfin arithmetic relocation.
3845 ADI Blackfin arithmetic relocation.
3849 ADI Blackfin arithmetic relocation.
3851 BFD_ARELOC_BFIN_COMP
3853 ADI Blackfin arithmetic relocation.
3855 BFD_ARELOC_BFIN_PAGE
3857 ADI Blackfin arithmetic relocation.
3859 BFD_ARELOC_BFIN_HWPAGE
3861 ADI Blackfin arithmetic relocation.
3863 BFD_ARELOC_BFIN_ADDR
3865 ADI Blackfin arithmetic relocation.
3868 BFD_RELOC_D10V_10_PCREL_R
3870 Mitsubishi D10V relocs.
3871 This is a 10-bit reloc with the right 2 bits
3874 BFD_RELOC_D10V_10_PCREL_L
3876 Mitsubishi D10V relocs.
3877 This is a 10-bit reloc with the right 2 bits
3878 assumed to be 0. This is the same as the previous reloc
3879 except it is in the left container, i.e.,
3880 shifted left 15 bits.
3884 This is an 18-bit reloc with the right 2 bits
3887 BFD_RELOC_D10V_18_PCREL
3889 This is an 18-bit reloc with the right 2 bits
3895 Mitsubishi D30V relocs.
3896 This is a 6-bit absolute reloc.
3898 BFD_RELOC_D30V_9_PCREL
3900 This is a 6-bit pc-relative reloc with
3901 the right 3 bits assumed to be 0.
3903 BFD_RELOC_D30V_9_PCREL_R
3905 This is a 6-bit pc-relative reloc with
3906 the right 3 bits assumed to be 0. Same
3907 as the previous reloc but on the right side
3912 This is a 12-bit absolute reloc with the
3913 right 3 bitsassumed to be 0.
3915 BFD_RELOC_D30V_15_PCREL
3917 This is a 12-bit pc-relative reloc with
3918 the right 3 bits assumed to be 0.
3920 BFD_RELOC_D30V_15_PCREL_R
3922 This is a 12-bit pc-relative reloc with
3923 the right 3 bits assumed to be 0. Same
3924 as the previous reloc but on the right side
3929 This is an 18-bit absolute reloc with
3930 the right 3 bits assumed to be 0.
3932 BFD_RELOC_D30V_21_PCREL
3934 This is an 18-bit pc-relative reloc with
3935 the right 3 bits assumed to be 0.
3937 BFD_RELOC_D30V_21_PCREL_R
3939 This is an 18-bit pc-relative reloc with
3940 the right 3 bits assumed to be 0. Same
3941 as the previous reloc but on the right side
3946 This is a 32-bit absolute reloc.
3948 BFD_RELOC_D30V_32_PCREL
3950 This is a 32-bit pc-relative reloc.
3953 BFD_RELOC_DLX_HI16_S
3968 BFD_RELOC_M32C_RL_JUMP
3970 BFD_RELOC_M32C_RL_1ADDR
3972 BFD_RELOC_M32C_RL_2ADDR
3974 Renesas M16C/M32C Relocations.
3979 Renesas M32R (formerly Mitsubishi M32R) relocs.
3980 This is a 24 bit absolute address.
3982 BFD_RELOC_M32R_10_PCREL
3984 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3986 BFD_RELOC_M32R_18_PCREL
3988 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3990 BFD_RELOC_M32R_26_PCREL
3992 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3994 BFD_RELOC_M32R_HI16_ULO
3996 This is a 16-bit reloc containing the high 16 bits of an address
3997 used when the lower 16 bits are treated as unsigned.
3999 BFD_RELOC_M32R_HI16_SLO
4001 This is a 16-bit reloc containing the high 16 bits of an address
4002 used when the lower 16 bits are treated as signed.
4006 This is a 16-bit reloc containing the lower 16 bits of an address.
4008 BFD_RELOC_M32R_SDA16
4010 This is a 16-bit reloc containing the small data area offset for use in
4011 add3, load, and store instructions.
4013 BFD_RELOC_M32R_GOT24
4015 BFD_RELOC_M32R_26_PLTREL
4019 BFD_RELOC_M32R_GLOB_DAT
4021 BFD_RELOC_M32R_JMP_SLOT
4023 BFD_RELOC_M32R_RELATIVE
4025 BFD_RELOC_M32R_GOTOFF
4027 BFD_RELOC_M32R_GOTOFF_HI_ULO
4029 BFD_RELOC_M32R_GOTOFF_HI_SLO
4031 BFD_RELOC_M32R_GOTOFF_LO
4033 BFD_RELOC_M32R_GOTPC24
4035 BFD_RELOC_M32R_GOT16_HI_ULO
4037 BFD_RELOC_M32R_GOT16_HI_SLO
4039 BFD_RELOC_M32R_GOT16_LO
4041 BFD_RELOC_M32R_GOTPC_HI_ULO
4043 BFD_RELOC_M32R_GOTPC_HI_SLO
4045 BFD_RELOC_M32R_GOTPC_LO
4054 This is a 20 bit absolute address.
4056 BFD_RELOC_NDS32_9_PCREL
4058 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4060 BFD_RELOC_NDS32_WORD_9_PCREL
4062 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4064 BFD_RELOC_NDS32_15_PCREL
4066 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4068 BFD_RELOC_NDS32_17_PCREL
4070 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4072 BFD_RELOC_NDS32_25_PCREL
4074 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4076 BFD_RELOC_NDS32_HI20
4078 This is a 20-bit reloc containing the high 20 bits of an address
4079 used with the lower 12 bits
4081 BFD_RELOC_NDS32_LO12S3
4083 This is a 12-bit reloc containing the lower 12 bits of an address
4084 then shift right by 3. This is used with ldi,sdi...
4086 BFD_RELOC_NDS32_LO12S2
4088 This is a 12-bit reloc containing the lower 12 bits of an address
4089 then shift left by 2. This is used with lwi,swi...
4091 BFD_RELOC_NDS32_LO12S1
4093 This is a 12-bit reloc containing the lower 12 bits of an address
4094 then shift left by 1. This is used with lhi,shi...
4096 BFD_RELOC_NDS32_LO12S0
4098 This is a 12-bit reloc containing the lower 12 bits of an address
4099 then shift left by 0. This is used with lbisbi...
4101 BFD_RELOC_NDS32_LO12S0_ORI
4103 This is a 12-bit reloc containing the lower 12 bits of an address
4104 then shift left by 0. This is only used with branch relaxations
4106 BFD_RELOC_NDS32_SDA15S3
4108 This is a 15-bit reloc containing the small data area 18-bit signed offset
4109 and shift left by 3 for use in ldi, sdi...
4111 BFD_RELOC_NDS32_SDA15S2
4113 This is a 15-bit reloc containing the small data area 17-bit signed offset
4114 and shift left by 2 for use in lwi, swi...
4116 BFD_RELOC_NDS32_SDA15S1
4118 This is a 15-bit reloc containing the small data area 16-bit signed offset
4119 and shift left by 1 for use in lhi, shi...
4121 BFD_RELOC_NDS32_SDA15S0
4123 This is a 15-bit reloc containing the small data area 15-bit signed offset
4124 and shift left by 0 for use in lbi, sbi...
4126 BFD_RELOC_NDS32_SDA16S3
4128 This is a 16-bit reloc containing the small data area 16-bit signed offset
4131 BFD_RELOC_NDS32_SDA17S2
4133 This is a 17-bit reloc containing the small data area 17-bit signed offset
4134 and shift left by 2 for use in lwi.gp, swi.gp...
4136 BFD_RELOC_NDS32_SDA18S1
4138 This is a 18-bit reloc containing the small data area 18-bit signed offset
4139 and shift left by 1 for use in lhi.gp, shi.gp...
4141 BFD_RELOC_NDS32_SDA19S0
4143 This is a 19-bit reloc containing the small data area 19-bit signed offset
4144 and shift left by 0 for use in lbi.gp, sbi.gp...
4146 BFD_RELOC_NDS32_GOT20
4148 BFD_RELOC_NDS32_9_PLTREL
4150 BFD_RELOC_NDS32_25_PLTREL
4152 BFD_RELOC_NDS32_COPY
4154 BFD_RELOC_NDS32_GLOB_DAT
4156 BFD_RELOC_NDS32_JMP_SLOT
4158 BFD_RELOC_NDS32_RELATIVE
4160 BFD_RELOC_NDS32_GOTOFF
4162 BFD_RELOC_NDS32_GOTOFF_HI20
4164 BFD_RELOC_NDS32_GOTOFF_LO12
4166 BFD_RELOC_NDS32_GOTPC20
4168 BFD_RELOC_NDS32_GOT_HI20
4170 BFD_RELOC_NDS32_GOT_LO12
4172 BFD_RELOC_NDS32_GOTPC_HI20
4174 BFD_RELOC_NDS32_GOTPC_LO12
4178 BFD_RELOC_NDS32_INSN16
4180 BFD_RELOC_NDS32_LABEL
4182 BFD_RELOC_NDS32_LONGCALL1
4184 BFD_RELOC_NDS32_LONGCALL2
4186 BFD_RELOC_NDS32_LONGCALL3
4188 BFD_RELOC_NDS32_LONGJUMP1
4190 BFD_RELOC_NDS32_LONGJUMP2
4192 BFD_RELOC_NDS32_LONGJUMP3
4194 BFD_RELOC_NDS32_LOADSTORE
4196 BFD_RELOC_NDS32_9_FIXED
4198 BFD_RELOC_NDS32_15_FIXED
4200 BFD_RELOC_NDS32_17_FIXED
4202 BFD_RELOC_NDS32_25_FIXED
4204 BFD_RELOC_NDS32_LONGCALL4
4206 BFD_RELOC_NDS32_LONGCALL5
4208 BFD_RELOC_NDS32_LONGCALL6
4210 BFD_RELOC_NDS32_LONGJUMP4
4212 BFD_RELOC_NDS32_LONGJUMP5
4214 BFD_RELOC_NDS32_LONGJUMP6
4216 BFD_RELOC_NDS32_LONGJUMP7
4220 BFD_RELOC_NDS32_PLTREL_HI20
4222 BFD_RELOC_NDS32_PLTREL_LO12
4224 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4226 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4230 BFD_RELOC_NDS32_SDA12S2_DP
4232 BFD_RELOC_NDS32_SDA12S2_SP
4234 BFD_RELOC_NDS32_LO12S2_DP
4236 BFD_RELOC_NDS32_LO12S2_SP
4240 BFD_RELOC_NDS32_DWARF2_OP1
4242 BFD_RELOC_NDS32_DWARF2_OP2
4244 BFD_RELOC_NDS32_DWARF2_LEB
4246 for dwarf2 debug_line.
4248 BFD_RELOC_NDS32_UPDATE_TA
4250 for eliminate 16-bit instructions
4252 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4254 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4256 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4258 BFD_RELOC_NDS32_GOT_LO15
4260 BFD_RELOC_NDS32_GOT_LO19
4262 BFD_RELOC_NDS32_GOTOFF_LO15
4264 BFD_RELOC_NDS32_GOTOFF_LO19
4266 BFD_RELOC_NDS32_GOT15S2
4268 BFD_RELOC_NDS32_GOT17S2
4270 for PIC object relaxation
4275 This is a 5 bit absolute address.
4277 BFD_RELOC_NDS32_10_UPCREL
4279 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4281 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4283 If fp were omitted, fp can used as another gp.
4285 BFD_RELOC_NDS32_RELAX_ENTRY
4287 BFD_RELOC_NDS32_GOT_SUFF
4289 BFD_RELOC_NDS32_GOTOFF_SUFF
4291 BFD_RELOC_NDS32_PLT_GOT_SUFF
4293 BFD_RELOC_NDS32_MULCALL_SUFF
4297 BFD_RELOC_NDS32_PTR_COUNT
4299 BFD_RELOC_NDS32_PTR_RESOLVED
4301 BFD_RELOC_NDS32_PLTBLOCK
4303 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4305 BFD_RELOC_NDS32_RELAX_REGION_END
4307 BFD_RELOC_NDS32_MINUEND
4309 BFD_RELOC_NDS32_SUBTRAHEND
4311 BFD_RELOC_NDS32_DIFF8
4313 BFD_RELOC_NDS32_DIFF16
4315 BFD_RELOC_NDS32_DIFF32
4317 BFD_RELOC_NDS32_DIFF_ULEB128
4319 BFD_RELOC_NDS32_EMPTY
4321 relaxation relative relocation types
4323 BFD_RELOC_NDS32_25_ABS
4325 This is a 25 bit absolute address.
4327 BFD_RELOC_NDS32_DATA
4329 BFD_RELOC_NDS32_TRAN
4331 BFD_RELOC_NDS32_17IFC_PCREL
4333 BFD_RELOC_NDS32_10IFCU_PCREL
4335 For ex9 and ifc using.
4337 BFD_RELOC_NDS32_TPOFF
4339 BFD_RELOC_NDS32_TLS_LE_HI20
4341 BFD_RELOC_NDS32_TLS_LE_LO12
4343 BFD_RELOC_NDS32_TLS_LE_ADD
4345 BFD_RELOC_NDS32_TLS_LE_LS
4347 BFD_RELOC_NDS32_GOTTPOFF
4349 BFD_RELOC_NDS32_TLS_IE_HI20
4351 BFD_RELOC_NDS32_TLS_IE_LO12S2
4353 BFD_RELOC_NDS32_TLS_TPOFF
4355 BFD_RELOC_NDS32_TLS_LE_20
4357 BFD_RELOC_NDS32_TLS_LE_15S0
4359 BFD_RELOC_NDS32_TLS_LE_15S1
4361 BFD_RELOC_NDS32_TLS_LE_15S2
4367 BFD_RELOC_V850_9_PCREL
4369 This is a 9-bit reloc
4371 BFD_RELOC_V850_22_PCREL
4373 This is a 22-bit reloc
4376 BFD_RELOC_V850_SDA_16_16_OFFSET
4378 This is a 16 bit offset from the short data area pointer.
4380 BFD_RELOC_V850_SDA_15_16_OFFSET
4382 This is a 16 bit offset (of which only 15 bits are used) from the
4383 short data area pointer.
4385 BFD_RELOC_V850_ZDA_16_16_OFFSET
4387 This is a 16 bit offset from the zero data area pointer.
4389 BFD_RELOC_V850_ZDA_15_16_OFFSET
4391 This is a 16 bit offset (of which only 15 bits are used) from the
4392 zero data area pointer.
4394 BFD_RELOC_V850_TDA_6_8_OFFSET
4396 This is an 8 bit offset (of which only 6 bits are used) from the
4397 tiny data area pointer.
4399 BFD_RELOC_V850_TDA_7_8_OFFSET
4401 This is an 8bit offset (of which only 7 bits are used) from the tiny
4404 BFD_RELOC_V850_TDA_7_7_OFFSET
4406 This is a 7 bit offset from the tiny data area pointer.
4408 BFD_RELOC_V850_TDA_16_16_OFFSET
4410 This is a 16 bit offset from the tiny data area pointer.
4413 BFD_RELOC_V850_TDA_4_5_OFFSET
4415 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4418 BFD_RELOC_V850_TDA_4_4_OFFSET
4420 This is a 4 bit offset from the tiny data area pointer.
4422 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4424 This is a 16 bit offset from the short data area pointer, with the
4425 bits placed non-contiguously in the instruction.
4427 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4429 This is a 16 bit offset from the zero data area pointer, with the
4430 bits placed non-contiguously in the instruction.
4432 BFD_RELOC_V850_CALLT_6_7_OFFSET
4434 This is a 6 bit offset from the call table base pointer.
4436 BFD_RELOC_V850_CALLT_16_16_OFFSET
4438 This is a 16 bit offset from the call table base pointer.
4440 BFD_RELOC_V850_LONGCALL
4442 Used for relaxing indirect function calls.
4444 BFD_RELOC_V850_LONGJUMP
4446 Used for relaxing indirect jumps.
4448 BFD_RELOC_V850_ALIGN
4450 Used to maintain alignment whilst relaxing.
4452 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4454 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4457 BFD_RELOC_V850_16_PCREL
4459 This is a 16-bit reloc.
4461 BFD_RELOC_V850_17_PCREL
4463 This is a 17-bit reloc.
4467 This is a 23-bit reloc.
4469 BFD_RELOC_V850_32_PCREL
4471 This is a 32-bit reloc.
4473 BFD_RELOC_V850_32_ABS
4475 This is a 32-bit reloc.
4477 BFD_RELOC_V850_16_SPLIT_OFFSET
4479 This is a 16-bit reloc.
4481 BFD_RELOC_V850_16_S1
4483 This is a 16-bit reloc.
4485 BFD_RELOC_V850_LO16_S1
4487 Low 16 bits. 16 bit shifted by 1.
4489 BFD_RELOC_V850_CALLT_15_16_OFFSET
4491 This is a 16 bit offset from the call table base pointer.
4493 BFD_RELOC_V850_32_GOTPCREL
4497 BFD_RELOC_V850_16_GOT
4501 BFD_RELOC_V850_32_GOT
4505 BFD_RELOC_V850_22_PLT_PCREL
4509 BFD_RELOC_V850_32_PLT_PCREL
4517 BFD_RELOC_V850_GLOB_DAT
4521 BFD_RELOC_V850_JMP_SLOT
4525 BFD_RELOC_V850_RELATIVE
4529 BFD_RELOC_V850_16_GOTOFF
4533 BFD_RELOC_V850_32_GOTOFF
4548 This is a 8bit DP reloc for the tms320c30, where the most
4549 significant 8 bits of a 24 bit word are placed into the least
4550 significant 8 bits of the opcode.
4553 BFD_RELOC_TIC54X_PARTLS7
4555 This is a 7bit reloc for the tms320c54x, where the least
4556 significant 7 bits of a 16 bit word are placed into the least
4557 significant 7 bits of the opcode.
4560 BFD_RELOC_TIC54X_PARTMS9
4562 This is a 9bit DP reloc for the tms320c54x, where the most
4563 significant 9 bits of a 16 bit word are placed into the least
4564 significant 9 bits of the opcode.
4569 This is an extended address 23-bit reloc for the tms320c54x.
4572 BFD_RELOC_TIC54X_16_OF_23
4574 This is a 16-bit reloc for the tms320c54x, where the least
4575 significant 16 bits of a 23-bit extended address are placed into
4579 BFD_RELOC_TIC54X_MS7_OF_23
4581 This is a reloc for the tms320c54x, where the most
4582 significant 7 bits of a 23-bit extended address are placed into
4586 BFD_RELOC_C6000_PCR_S21
4588 BFD_RELOC_C6000_PCR_S12
4590 BFD_RELOC_C6000_PCR_S10
4592 BFD_RELOC_C6000_PCR_S7
4594 BFD_RELOC_C6000_ABS_S16
4596 BFD_RELOC_C6000_ABS_L16
4598 BFD_RELOC_C6000_ABS_H16
4600 BFD_RELOC_C6000_SBR_U15_B
4602 BFD_RELOC_C6000_SBR_U15_H
4604 BFD_RELOC_C6000_SBR_U15_W
4606 BFD_RELOC_C6000_SBR_S16
4608 BFD_RELOC_C6000_SBR_L16_B
4610 BFD_RELOC_C6000_SBR_L16_H
4612 BFD_RELOC_C6000_SBR_L16_W
4614 BFD_RELOC_C6000_SBR_H16_B
4616 BFD_RELOC_C6000_SBR_H16_H
4618 BFD_RELOC_C6000_SBR_H16_W
4620 BFD_RELOC_C6000_SBR_GOT_U15_W
4622 BFD_RELOC_C6000_SBR_GOT_L16_W
4624 BFD_RELOC_C6000_SBR_GOT_H16_W
4626 BFD_RELOC_C6000_DSBT_INDEX
4628 BFD_RELOC_C6000_PREL31
4630 BFD_RELOC_C6000_COPY
4632 BFD_RELOC_C6000_JUMP_SLOT
4634 BFD_RELOC_C6000_EHTYPE
4636 BFD_RELOC_C6000_PCR_H16
4638 BFD_RELOC_C6000_PCR_L16
4640 BFD_RELOC_C6000_ALIGN
4642 BFD_RELOC_C6000_FPHEAD
4644 BFD_RELOC_C6000_NOCMP
4646 TMS320C6000 relocations.
4651 This is a 48 bit reloc for the FR30 that stores 32 bits.
4655 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4658 BFD_RELOC_FR30_6_IN_4
4660 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4663 BFD_RELOC_FR30_8_IN_8
4665 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4668 BFD_RELOC_FR30_9_IN_8
4670 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4673 BFD_RELOC_FR30_10_IN_8
4675 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4678 BFD_RELOC_FR30_9_PCREL
4680 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4681 short offset into 8 bits.
4683 BFD_RELOC_FR30_12_PCREL
4685 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4686 short offset into 11 bits.
4689 BFD_RELOC_MCORE_PCREL_IMM8BY4
4691 BFD_RELOC_MCORE_PCREL_IMM11BY2
4693 BFD_RELOC_MCORE_PCREL_IMM4BY2
4695 BFD_RELOC_MCORE_PCREL_32
4697 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4701 Motorola Mcore relocations.
4710 BFD_RELOC_MEP_PCREL8A2
4712 BFD_RELOC_MEP_PCREL12A2
4714 BFD_RELOC_MEP_PCREL17A2
4716 BFD_RELOC_MEP_PCREL24A2
4718 BFD_RELOC_MEP_PCABS24A2
4730 BFD_RELOC_MEP_TPREL7
4732 BFD_RELOC_MEP_TPREL7A2
4734 BFD_RELOC_MEP_TPREL7A4
4736 BFD_RELOC_MEP_UIMM24
4738 BFD_RELOC_MEP_ADDR24A4
4740 BFD_RELOC_MEP_GNU_VTINHERIT
4742 BFD_RELOC_MEP_GNU_VTENTRY
4744 Toshiba Media Processor Relocations.
4748 BFD_RELOC_METAG_HIADDR16
4750 BFD_RELOC_METAG_LOADDR16
4752 BFD_RELOC_METAG_RELBRANCH
4754 BFD_RELOC_METAG_GETSETOFF
4756 BFD_RELOC_METAG_HIOG
4758 BFD_RELOC_METAG_LOOG
4760 BFD_RELOC_METAG_REL8
4762 BFD_RELOC_METAG_REL16
4764 BFD_RELOC_METAG_HI16_GOTOFF
4766 BFD_RELOC_METAG_LO16_GOTOFF
4768 BFD_RELOC_METAG_GETSET_GOTOFF
4770 BFD_RELOC_METAG_GETSET_GOT
4772 BFD_RELOC_METAG_HI16_GOTPC
4774 BFD_RELOC_METAG_LO16_GOTPC
4776 BFD_RELOC_METAG_HI16_PLT
4778 BFD_RELOC_METAG_LO16_PLT
4780 BFD_RELOC_METAG_RELBRANCH_PLT
4782 BFD_RELOC_METAG_GOTOFF
4786 BFD_RELOC_METAG_COPY
4788 BFD_RELOC_METAG_JMP_SLOT
4790 BFD_RELOC_METAG_RELATIVE
4792 BFD_RELOC_METAG_GLOB_DAT
4794 BFD_RELOC_METAG_TLS_GD
4796 BFD_RELOC_METAG_TLS_LDM
4798 BFD_RELOC_METAG_TLS_LDO_HI16
4800 BFD_RELOC_METAG_TLS_LDO_LO16
4802 BFD_RELOC_METAG_TLS_LDO
4804 BFD_RELOC_METAG_TLS_IE
4806 BFD_RELOC_METAG_TLS_IENONPIC
4808 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4810 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4812 BFD_RELOC_METAG_TLS_TPOFF
4814 BFD_RELOC_METAG_TLS_DTPMOD
4816 BFD_RELOC_METAG_TLS_DTPOFF
4818 BFD_RELOC_METAG_TLS_LE
4820 BFD_RELOC_METAG_TLS_LE_HI16
4822 BFD_RELOC_METAG_TLS_LE_LO16
4824 Imagination Technologies Meta relocations.
4829 BFD_RELOC_MMIX_GETA_1
4831 BFD_RELOC_MMIX_GETA_2
4833 BFD_RELOC_MMIX_GETA_3
4835 These are relocations for the GETA instruction.
4837 BFD_RELOC_MMIX_CBRANCH
4839 BFD_RELOC_MMIX_CBRANCH_J
4841 BFD_RELOC_MMIX_CBRANCH_1
4843 BFD_RELOC_MMIX_CBRANCH_2
4845 BFD_RELOC_MMIX_CBRANCH_3
4847 These are relocations for a conditional branch instruction.
4849 BFD_RELOC_MMIX_PUSHJ
4851 BFD_RELOC_MMIX_PUSHJ_1
4853 BFD_RELOC_MMIX_PUSHJ_2
4855 BFD_RELOC_MMIX_PUSHJ_3
4857 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4859 These are relocations for the PUSHJ instruction.
4863 BFD_RELOC_MMIX_JMP_1
4865 BFD_RELOC_MMIX_JMP_2
4867 BFD_RELOC_MMIX_JMP_3
4869 These are relocations for the JMP instruction.
4871 BFD_RELOC_MMIX_ADDR19
4873 This is a relocation for a relative address as in a GETA instruction or
4876 BFD_RELOC_MMIX_ADDR27
4878 This is a relocation for a relative address as in a JMP instruction.
4880 BFD_RELOC_MMIX_REG_OR_BYTE
4882 This is a relocation for an instruction field that may be a general
4883 register or a value 0..255.
4887 This is a relocation for an instruction field that may be a general
4890 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4892 This is a relocation for two instruction fields holding a register and
4893 an offset, the equivalent of the relocation.
4895 BFD_RELOC_MMIX_LOCAL
4897 This relocation is an assertion that the expression is not allocated as
4898 a global register. It does not modify contents.
4901 BFD_RELOC_AVR_7_PCREL
4903 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4904 short offset into 7 bits.
4906 BFD_RELOC_AVR_13_PCREL
4908 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4909 short offset into 12 bits.
4913 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4914 program memory address) into 16 bits.
4916 BFD_RELOC_AVR_LO8_LDI
4918 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4919 data memory address) into 8 bit immediate value of LDI insn.
4921 BFD_RELOC_AVR_HI8_LDI
4923 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4924 of data memory address) into 8 bit immediate value of LDI insn.
4926 BFD_RELOC_AVR_HH8_LDI
4928 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4929 of program memory address) into 8 bit immediate value of LDI insn.
4931 BFD_RELOC_AVR_MS8_LDI
4933 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4934 of 32 bit value) into 8 bit immediate value of LDI insn.
4936 BFD_RELOC_AVR_LO8_LDI_NEG
4938 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4939 (usually data memory address) into 8 bit immediate value of SUBI insn.
4941 BFD_RELOC_AVR_HI8_LDI_NEG
4943 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4944 (high 8 bit of data memory address) into 8 bit immediate value of
4947 BFD_RELOC_AVR_HH8_LDI_NEG
4949 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4950 (most high 8 bit of program memory address) into 8 bit immediate value
4951 of LDI or SUBI insn.
4953 BFD_RELOC_AVR_MS8_LDI_NEG
4955 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4956 of 32 bit value) into 8 bit immediate value of LDI insn.
4958 BFD_RELOC_AVR_LO8_LDI_PM
4960 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4961 command address) into 8 bit immediate value of LDI insn.
4963 BFD_RELOC_AVR_LO8_LDI_GS
4965 This is a 16 bit reloc for the AVR that stores 8 bit value
4966 (command address) into 8 bit immediate value of LDI insn. If the address
4967 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4970 BFD_RELOC_AVR_HI8_LDI_PM
4972 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4973 of command address) into 8 bit immediate value of LDI insn.
4975 BFD_RELOC_AVR_HI8_LDI_GS
4977 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4978 of command address) into 8 bit immediate value of LDI insn. If the address
4979 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4982 BFD_RELOC_AVR_HH8_LDI_PM
4984 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4985 of command address) into 8 bit immediate value of LDI insn.
4987 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4989 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4990 (usually command address) into 8 bit immediate value of SUBI insn.
4992 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4994 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4995 (high 8 bit of 16 bit command address) into 8 bit immediate value
4998 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5000 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5001 (high 6 bit of 22 bit command address) into 8 bit immediate
5006 This is a 32 bit reloc for the AVR that stores 23 bit value
5011 This is a 16 bit reloc for the AVR that stores all needed bits
5012 for absolute addressing with ldi with overflow check to linktime
5016 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5019 BFD_RELOC_AVR_6_ADIW
5021 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5026 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5027 in .byte lo8(symbol)
5031 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5032 in .byte hi8(symbol)
5036 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5037 in .byte hlo8(symbol)
5041 BFD_RELOC_AVR_DIFF16
5043 BFD_RELOC_AVR_DIFF32
5045 AVR relocations to mark the difference of two local symbols.
5046 These are only needed to support linker relaxation and can be ignored
5047 when not relaxing. The field is set to the value of the difference
5048 assuming no relaxation. The relocation encodes the position of the
5049 second symbol so the linker can determine whether to adjust the field
5052 BFD_RELOC_AVR_LDS_STS_16
5054 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5055 lds and sts instructions supported only tiny core.
5059 This is a 6 bit reloc for the AVR that stores an I/O register
5060 number for the IN and OUT instructions
5064 This is a 5 bit reloc for the AVR that stores an I/O register
5065 number for the SBIC, SBIS, SBI and CBI instructions
5068 BFD_RELOC_RISCV_HI20
5070 BFD_RELOC_RISCV_PCREL_HI20
5072 BFD_RELOC_RISCV_PCREL_LO12_I
5074 BFD_RELOC_RISCV_PCREL_LO12_S
5076 BFD_RELOC_RISCV_LO12_I
5078 BFD_RELOC_RISCV_LO12_S
5080 BFD_RELOC_RISCV_GPREL12_I
5082 BFD_RELOC_RISCV_GPREL12_S
5084 BFD_RELOC_RISCV_TPREL_HI20
5086 BFD_RELOC_RISCV_TPREL_LO12_I
5088 BFD_RELOC_RISCV_TPREL_LO12_S
5090 BFD_RELOC_RISCV_TPREL_ADD
5092 BFD_RELOC_RISCV_CALL
5094 BFD_RELOC_RISCV_CALL_PLT
5096 BFD_RELOC_RISCV_ADD8
5098 BFD_RELOC_RISCV_ADD16
5100 BFD_RELOC_RISCV_ADD32
5102 BFD_RELOC_RISCV_ADD64
5104 BFD_RELOC_RISCV_SUB8
5106 BFD_RELOC_RISCV_SUB16
5108 BFD_RELOC_RISCV_SUB32
5110 BFD_RELOC_RISCV_SUB64
5112 BFD_RELOC_RISCV_GOT_HI20
5114 BFD_RELOC_RISCV_TLS_GOT_HI20
5116 BFD_RELOC_RISCV_TLS_GD_HI20
5120 BFD_RELOC_RISCV_TLS_DTPMOD32
5122 BFD_RELOC_RISCV_TLS_DTPREL32
5124 BFD_RELOC_RISCV_TLS_DTPMOD64
5126 BFD_RELOC_RISCV_TLS_DTPREL64
5128 BFD_RELOC_RISCV_TLS_TPREL32
5130 BFD_RELOC_RISCV_TLS_TPREL64
5132 BFD_RELOC_RISCV_ALIGN
5134 BFD_RELOC_RISCV_RVC_BRANCH
5136 BFD_RELOC_RISCV_RVC_JUMP
5138 BFD_RELOC_RISCV_RVC_LUI
5140 BFD_RELOC_RISCV_GPREL_I
5142 BFD_RELOC_RISCV_GPREL_S
5144 BFD_RELOC_RISCV_TPREL_I
5146 BFD_RELOC_RISCV_TPREL_S
5148 BFD_RELOC_RISCV_RELAX
5152 BFD_RELOC_RISCV_SUB6
5154 BFD_RELOC_RISCV_SET6
5156 BFD_RELOC_RISCV_SET8
5158 BFD_RELOC_RISCV_SET16
5160 BFD_RELOC_RISCV_SET32
5162 BFD_RELOC_RISCV_32_PCREL
5169 BFD_RELOC_RL78_NEG16
5171 BFD_RELOC_RL78_NEG24
5173 BFD_RELOC_RL78_NEG32
5175 BFD_RELOC_RL78_16_OP
5177 BFD_RELOC_RL78_24_OP
5179 BFD_RELOC_RL78_32_OP
5187 BFD_RELOC_RL78_DIR3U_PCREL
5191 BFD_RELOC_RL78_GPRELB
5193 BFD_RELOC_RL78_GPRELW
5195 BFD_RELOC_RL78_GPRELL
5199 BFD_RELOC_RL78_OP_SUBTRACT
5201 BFD_RELOC_RL78_OP_NEG
5203 BFD_RELOC_RL78_OP_AND
5205 BFD_RELOC_RL78_OP_SHRA
5209 BFD_RELOC_RL78_ABS16
5211 BFD_RELOC_RL78_ABS16_REV
5213 BFD_RELOC_RL78_ABS32
5215 BFD_RELOC_RL78_ABS32_REV
5217 BFD_RELOC_RL78_ABS16U
5219 BFD_RELOC_RL78_ABS16UW
5221 BFD_RELOC_RL78_ABS16UL
5223 BFD_RELOC_RL78_RELAX
5233 BFD_RELOC_RL78_SADDR
5235 Renesas RL78 Relocations.
5258 BFD_RELOC_RX_DIR3U_PCREL
5270 BFD_RELOC_RX_OP_SUBTRACT
5278 BFD_RELOC_RX_ABS16_REV
5282 BFD_RELOC_RX_ABS32_REV
5286 BFD_RELOC_RX_ABS16UW
5288 BFD_RELOC_RX_ABS16UL
5292 Renesas RX Relocations.
5305 32 bit PC relative PLT address.
5309 Copy symbol at runtime.
5311 BFD_RELOC_390_GLOB_DAT
5315 BFD_RELOC_390_JMP_SLOT
5319 BFD_RELOC_390_RELATIVE
5321 Adjust by program base.
5325 32 bit PC relative offset to GOT.
5331 BFD_RELOC_390_PC12DBL
5333 PC relative 12 bit shifted by 1.
5335 BFD_RELOC_390_PLT12DBL
5337 12 bit PC rel. PLT shifted by 1.
5339 BFD_RELOC_390_PC16DBL
5341 PC relative 16 bit shifted by 1.
5343 BFD_RELOC_390_PLT16DBL
5345 16 bit PC rel. PLT shifted by 1.
5347 BFD_RELOC_390_PC24DBL
5349 PC relative 24 bit shifted by 1.
5351 BFD_RELOC_390_PLT24DBL
5353 24 bit PC rel. PLT shifted by 1.
5355 BFD_RELOC_390_PC32DBL
5357 PC relative 32 bit shifted by 1.
5359 BFD_RELOC_390_PLT32DBL
5361 32 bit PC rel. PLT shifted by 1.
5363 BFD_RELOC_390_GOTPCDBL
5365 32 bit PC rel. GOT shifted by 1.
5373 64 bit PC relative PLT address.
5375 BFD_RELOC_390_GOTENT
5377 32 bit rel. offset to GOT entry.
5379 BFD_RELOC_390_GOTOFF64
5381 64 bit offset to GOT.
5383 BFD_RELOC_390_GOTPLT12
5385 12-bit offset to symbol-entry within GOT, with PLT handling.
5387 BFD_RELOC_390_GOTPLT16
5389 16-bit offset to symbol-entry within GOT, with PLT handling.
5391 BFD_RELOC_390_GOTPLT32
5393 32-bit offset to symbol-entry within GOT, with PLT handling.
5395 BFD_RELOC_390_GOTPLT64
5397 64-bit offset to symbol-entry within GOT, with PLT handling.
5399 BFD_RELOC_390_GOTPLTENT
5401 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5403 BFD_RELOC_390_PLTOFF16
5405 16-bit rel. offset from the GOT to a PLT entry.
5407 BFD_RELOC_390_PLTOFF32
5409 32-bit rel. offset from the GOT to a PLT entry.
5411 BFD_RELOC_390_PLTOFF64
5413 64-bit rel. offset from the GOT to a PLT entry.
5416 BFD_RELOC_390_TLS_LOAD
5418 BFD_RELOC_390_TLS_GDCALL
5420 BFD_RELOC_390_TLS_LDCALL
5422 BFD_RELOC_390_TLS_GD32
5424 BFD_RELOC_390_TLS_GD64
5426 BFD_RELOC_390_TLS_GOTIE12
5428 BFD_RELOC_390_TLS_GOTIE32
5430 BFD_RELOC_390_TLS_GOTIE64
5432 BFD_RELOC_390_TLS_LDM32
5434 BFD_RELOC_390_TLS_LDM64
5436 BFD_RELOC_390_TLS_IE32
5438 BFD_RELOC_390_TLS_IE64
5440 BFD_RELOC_390_TLS_IEENT
5442 BFD_RELOC_390_TLS_LE32
5444 BFD_RELOC_390_TLS_LE64
5446 BFD_RELOC_390_TLS_LDO32
5448 BFD_RELOC_390_TLS_LDO64
5450 BFD_RELOC_390_TLS_DTPMOD
5452 BFD_RELOC_390_TLS_DTPOFF
5454 BFD_RELOC_390_TLS_TPOFF
5456 s390 tls relocations.
5463 BFD_RELOC_390_GOTPLT20
5465 BFD_RELOC_390_TLS_GOTIE20
5467 Long displacement extension.
5470 BFD_RELOC_390_IRELATIVE
5472 STT_GNU_IFUNC relocation.
5475 BFD_RELOC_SCORE_GPREL15
5478 Low 16 bit for load/store
5480 BFD_RELOC_SCORE_DUMMY2
5484 This is a 24-bit reloc with the right 1 bit assumed to be 0
5486 BFD_RELOC_SCORE_BRANCH
5488 This is a 19-bit reloc with the right 1 bit assumed to be 0
5490 BFD_RELOC_SCORE_IMM30
5492 This is a 32-bit reloc for 48-bit instructions.
5494 BFD_RELOC_SCORE_IMM32
5496 This is a 32-bit reloc for 48-bit instructions.
5498 BFD_RELOC_SCORE16_JMP
5500 This is a 11-bit reloc with the right 1 bit assumed to be 0
5502 BFD_RELOC_SCORE16_BRANCH
5504 This is a 8-bit reloc with the right 1 bit assumed to be 0
5506 BFD_RELOC_SCORE_BCMP
5508 This is a 9-bit reloc with the right 1 bit assumed to be 0
5510 BFD_RELOC_SCORE_GOT15
5512 BFD_RELOC_SCORE_GOT_LO16
5514 BFD_RELOC_SCORE_CALL15
5516 BFD_RELOC_SCORE_DUMMY_HI16
5518 Undocumented Score relocs
5523 Scenix IP2K - 9-bit register number / data address
5527 Scenix IP2K - 4-bit register/data bank number
5529 BFD_RELOC_IP2K_ADDR16CJP
5531 Scenix IP2K - low 13 bits of instruction word address
5533 BFD_RELOC_IP2K_PAGE3
5535 Scenix IP2K - high 3 bits of instruction word address
5537 BFD_RELOC_IP2K_LO8DATA
5539 BFD_RELOC_IP2K_HI8DATA
5541 BFD_RELOC_IP2K_EX8DATA
5543 Scenix IP2K - ext/low/high 8 bits of data address
5545 BFD_RELOC_IP2K_LO8INSN
5547 BFD_RELOC_IP2K_HI8INSN
5549 Scenix IP2K - low/high 8 bits of instruction word address
5551 BFD_RELOC_IP2K_PC_SKIP
5553 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5557 Scenix IP2K - 16 bit word address in text section.
5559 BFD_RELOC_IP2K_FR_OFFSET
5561 Scenix IP2K - 7-bit sp or dp offset
5563 BFD_RELOC_VPE4KMATH_DATA
5565 BFD_RELOC_VPE4KMATH_INSN
5567 Scenix VPE4K coprocessor - data/insn-space addressing
5570 BFD_RELOC_VTABLE_INHERIT
5572 BFD_RELOC_VTABLE_ENTRY
5574 These two relocations are used by the linker to determine which of
5575 the entries in a C++ virtual function table are actually used. When
5576 the --gc-sections option is given, the linker will zero out the entries
5577 that are not used, so that the code for those functions need not be
5578 included in the output.
5580 VTABLE_INHERIT is a zero-space relocation used to describe to the
5581 linker the inheritance tree of a C++ virtual function table. The
5582 relocation's symbol should be the parent class' vtable, and the
5583 relocation should be located at the child vtable.
5585 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5586 virtual function table entry. The reloc's symbol should refer to the
5587 table of the class mentioned in the code. Off of that base, an offset
5588 describes the entry that is being used. For Rela hosts, this offset
5589 is stored in the reloc's addend. For Rel hosts, we are forced to put
5590 this offset in the reloc's section offset.
5593 BFD_RELOC_IA64_IMM14
5595 BFD_RELOC_IA64_IMM22
5597 BFD_RELOC_IA64_IMM64
5599 BFD_RELOC_IA64_DIR32MSB
5601 BFD_RELOC_IA64_DIR32LSB
5603 BFD_RELOC_IA64_DIR64MSB
5605 BFD_RELOC_IA64_DIR64LSB
5607 BFD_RELOC_IA64_GPREL22
5609 BFD_RELOC_IA64_GPREL64I
5611 BFD_RELOC_IA64_GPREL32MSB
5613 BFD_RELOC_IA64_GPREL32LSB
5615 BFD_RELOC_IA64_GPREL64MSB
5617 BFD_RELOC_IA64_GPREL64LSB
5619 BFD_RELOC_IA64_LTOFF22
5621 BFD_RELOC_IA64_LTOFF64I
5623 BFD_RELOC_IA64_PLTOFF22
5625 BFD_RELOC_IA64_PLTOFF64I
5627 BFD_RELOC_IA64_PLTOFF64MSB
5629 BFD_RELOC_IA64_PLTOFF64LSB
5631 BFD_RELOC_IA64_FPTR64I
5633 BFD_RELOC_IA64_FPTR32MSB
5635 BFD_RELOC_IA64_FPTR32LSB
5637 BFD_RELOC_IA64_FPTR64MSB
5639 BFD_RELOC_IA64_FPTR64LSB
5641 BFD_RELOC_IA64_PCREL21B
5643 BFD_RELOC_IA64_PCREL21BI
5645 BFD_RELOC_IA64_PCREL21M
5647 BFD_RELOC_IA64_PCREL21F
5649 BFD_RELOC_IA64_PCREL22
5651 BFD_RELOC_IA64_PCREL60B
5653 BFD_RELOC_IA64_PCREL64I
5655 BFD_RELOC_IA64_PCREL32MSB
5657 BFD_RELOC_IA64_PCREL32LSB
5659 BFD_RELOC_IA64_PCREL64MSB
5661 BFD_RELOC_IA64_PCREL64LSB
5663 BFD_RELOC_IA64_LTOFF_FPTR22
5665 BFD_RELOC_IA64_LTOFF_FPTR64I
5667 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5669 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5671 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5673 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5675 BFD_RELOC_IA64_SEGREL32MSB
5677 BFD_RELOC_IA64_SEGREL32LSB
5679 BFD_RELOC_IA64_SEGREL64MSB
5681 BFD_RELOC_IA64_SEGREL64LSB
5683 BFD_RELOC_IA64_SECREL32MSB
5685 BFD_RELOC_IA64_SECREL32LSB
5687 BFD_RELOC_IA64_SECREL64MSB
5689 BFD_RELOC_IA64_SECREL64LSB
5691 BFD_RELOC_IA64_REL32MSB
5693 BFD_RELOC_IA64_REL32LSB
5695 BFD_RELOC_IA64_REL64MSB
5697 BFD_RELOC_IA64_REL64LSB
5699 BFD_RELOC_IA64_LTV32MSB
5701 BFD_RELOC_IA64_LTV32LSB
5703 BFD_RELOC_IA64_LTV64MSB
5705 BFD_RELOC_IA64_LTV64LSB
5707 BFD_RELOC_IA64_IPLTMSB
5709 BFD_RELOC_IA64_IPLTLSB
5713 BFD_RELOC_IA64_LTOFF22X
5715 BFD_RELOC_IA64_LDXMOV
5717 BFD_RELOC_IA64_TPREL14
5719 BFD_RELOC_IA64_TPREL22
5721 BFD_RELOC_IA64_TPREL64I
5723 BFD_RELOC_IA64_TPREL64MSB
5725 BFD_RELOC_IA64_TPREL64LSB
5727 BFD_RELOC_IA64_LTOFF_TPREL22
5729 BFD_RELOC_IA64_DTPMOD64MSB
5731 BFD_RELOC_IA64_DTPMOD64LSB
5733 BFD_RELOC_IA64_LTOFF_DTPMOD22
5735 BFD_RELOC_IA64_DTPREL14
5737 BFD_RELOC_IA64_DTPREL22
5739 BFD_RELOC_IA64_DTPREL64I
5741 BFD_RELOC_IA64_DTPREL32MSB
5743 BFD_RELOC_IA64_DTPREL32LSB
5745 BFD_RELOC_IA64_DTPREL64MSB
5747 BFD_RELOC_IA64_DTPREL64LSB
5749 BFD_RELOC_IA64_LTOFF_DTPREL22
5751 Intel IA64 Relocations.
5754 BFD_RELOC_M68HC11_HI8
5756 Motorola 68HC11 reloc.
5757 This is the 8 bit high part of an absolute address.
5759 BFD_RELOC_M68HC11_LO8
5761 Motorola 68HC11 reloc.
5762 This is the 8 bit low part of an absolute address.
5764 BFD_RELOC_M68HC11_3B
5766 Motorola 68HC11 reloc.
5767 This is the 3 bit of a value.
5769 BFD_RELOC_M68HC11_RL_JUMP
5771 Motorola 68HC11 reloc.
5772 This reloc marks the beginning of a jump/call instruction.
5773 It is used for linker relaxation to correctly identify beginning
5774 of instruction and change some branches to use PC-relative
5777 BFD_RELOC_M68HC11_RL_GROUP
5779 Motorola 68HC11 reloc.
5780 This reloc marks a group of several instructions that gcc generates
5781 and for which the linker relaxation pass can modify and/or remove
5784 BFD_RELOC_M68HC11_LO16
5786 Motorola 68HC11 reloc.
5787 This is the 16-bit lower part of an address. It is used for 'call'
5788 instruction to specify the symbol address without any special
5789 transformation (due to memory bank window).
5791 BFD_RELOC_M68HC11_PAGE
5793 Motorola 68HC11 reloc.
5794 This is a 8-bit reloc that specifies the page number of an address.
5795 It is used by 'call' instruction to specify the page number of
5798 BFD_RELOC_M68HC11_24
5800 Motorola 68HC11 reloc.
5801 This is a 24-bit reloc that represents the address with a 16-bit
5802 value and a 8-bit page number. The symbol address is transformed
5803 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5805 BFD_RELOC_M68HC12_5B
5807 Motorola 68HC12 reloc.
5808 This is the 5 bits of a value.
5810 BFD_RELOC_XGATE_RL_JUMP
5812 Freescale XGATE reloc.
5813 This reloc marks the beginning of a bra/jal instruction.
5815 BFD_RELOC_XGATE_RL_GROUP
5817 Freescale XGATE reloc.
5818 This reloc marks a group of several instructions that gcc generates
5819 and for which the linker relaxation pass can modify and/or remove
5822 BFD_RELOC_XGATE_LO16
5824 Freescale XGATE reloc.
5825 This is the 16-bit lower part of an address. It is used for the '16-bit'
5828 BFD_RELOC_XGATE_GPAGE
5830 Freescale XGATE reloc.
5834 Freescale XGATE reloc.
5836 BFD_RELOC_XGATE_PCREL_9
5838 Freescale XGATE reloc.
5839 This is a 9-bit pc-relative reloc.
5841 BFD_RELOC_XGATE_PCREL_10
5843 Freescale XGATE reloc.
5844 This is a 10-bit pc-relative reloc.
5846 BFD_RELOC_XGATE_IMM8_LO
5848 Freescale XGATE reloc.
5849 This is the 16-bit lower part of an address. It is used for the '16-bit'
5852 BFD_RELOC_XGATE_IMM8_HI
5854 Freescale XGATE reloc.
5855 This is the 16-bit higher part of an address. It is used for the '16-bit'
5858 BFD_RELOC_XGATE_IMM3
5860 Freescale XGATE reloc.
5861 This is a 3-bit pc-relative reloc.
5863 BFD_RELOC_XGATE_IMM4
5865 Freescale XGATE reloc.
5866 This is a 4-bit pc-relative reloc.
5868 BFD_RELOC_XGATE_IMM5
5870 Freescale XGATE reloc.
5871 This is a 5-bit pc-relative reloc.
5873 BFD_RELOC_M68HC12_9B
5875 Motorola 68HC12 reloc.
5876 This is the 9 bits of a value.
5878 BFD_RELOC_M68HC12_16B
5880 Motorola 68HC12 reloc.
5881 This is the 16 bits of a value.
5883 BFD_RELOC_M68HC12_9_PCREL
5885 Motorola 68HC12/XGATE reloc.
5886 This is a PCREL9 branch.
5888 BFD_RELOC_M68HC12_10_PCREL
5890 Motorola 68HC12/XGATE reloc.
5891 This is a PCREL10 branch.
5893 BFD_RELOC_M68HC12_LO8XG
5895 Motorola 68HC12/XGATE reloc.
5896 This is the 8 bit low part of an absolute address and immediately precedes
5897 a matching HI8XG part.
5899 BFD_RELOC_M68HC12_HI8XG
5901 Motorola 68HC12/XGATE reloc.
5902 This is the 8 bit high part of an absolute address and immediately follows
5903 a matching LO8XG part.
5907 BFD_RELOC_16C_NUM08_C
5911 BFD_RELOC_16C_NUM16_C
5915 BFD_RELOC_16C_NUM32_C
5917 BFD_RELOC_16C_DISP04
5919 BFD_RELOC_16C_DISP04_C
5921 BFD_RELOC_16C_DISP08
5923 BFD_RELOC_16C_DISP08_C
5925 BFD_RELOC_16C_DISP16
5927 BFD_RELOC_16C_DISP16_C
5929 BFD_RELOC_16C_DISP24
5931 BFD_RELOC_16C_DISP24_C
5933 BFD_RELOC_16C_DISP24a
5935 BFD_RELOC_16C_DISP24a_C
5939 BFD_RELOC_16C_REG04_C
5941 BFD_RELOC_16C_REG04a
5943 BFD_RELOC_16C_REG04a_C
5947 BFD_RELOC_16C_REG14_C
5951 BFD_RELOC_16C_REG16_C
5955 BFD_RELOC_16C_REG20_C
5959 BFD_RELOC_16C_ABS20_C
5963 BFD_RELOC_16C_ABS24_C
5967 BFD_RELOC_16C_IMM04_C
5971 BFD_RELOC_16C_IMM16_C
5975 BFD_RELOC_16C_IMM20_C
5979 BFD_RELOC_16C_IMM24_C
5983 BFD_RELOC_16C_IMM32_C
5985 NS CR16C Relocations.
5990 BFD_RELOC_CR16_NUM16
5992 BFD_RELOC_CR16_NUM32
5994 BFD_RELOC_CR16_NUM32a
5996 BFD_RELOC_CR16_REGREL0
5998 BFD_RELOC_CR16_REGREL4
6000 BFD_RELOC_CR16_REGREL4a
6002 BFD_RELOC_CR16_REGREL14
6004 BFD_RELOC_CR16_REGREL14a
6006 BFD_RELOC_CR16_REGREL16
6008 BFD_RELOC_CR16_REGREL20
6010 BFD_RELOC_CR16_REGREL20a
6012 BFD_RELOC_CR16_ABS20
6014 BFD_RELOC_CR16_ABS24
6020 BFD_RELOC_CR16_IMM16
6022 BFD_RELOC_CR16_IMM20
6024 BFD_RELOC_CR16_IMM24
6026 BFD_RELOC_CR16_IMM32
6028 BFD_RELOC_CR16_IMM32a
6030 BFD_RELOC_CR16_DISP4
6032 BFD_RELOC_CR16_DISP8
6034 BFD_RELOC_CR16_DISP16
6036 BFD_RELOC_CR16_DISP20
6038 BFD_RELOC_CR16_DISP24
6040 BFD_RELOC_CR16_DISP24a
6042 BFD_RELOC_CR16_SWITCH8
6044 BFD_RELOC_CR16_SWITCH16
6046 BFD_RELOC_CR16_SWITCH32
6048 BFD_RELOC_CR16_GOT_REGREL20
6050 BFD_RELOC_CR16_GOTC_REGREL20
6052 BFD_RELOC_CR16_GLOB_DAT
6054 NS CR16 Relocations.
6061 BFD_RELOC_CRX_REL8_CMP
6069 BFD_RELOC_CRX_REGREL12
6071 BFD_RELOC_CRX_REGREL22
6073 BFD_RELOC_CRX_REGREL28
6075 BFD_RELOC_CRX_REGREL32
6091 BFD_RELOC_CRX_SWITCH8
6093 BFD_RELOC_CRX_SWITCH16
6095 BFD_RELOC_CRX_SWITCH32
6100 BFD_RELOC_CRIS_BDISP8
6102 BFD_RELOC_CRIS_UNSIGNED_5
6104 BFD_RELOC_CRIS_SIGNED_6
6106 BFD_RELOC_CRIS_UNSIGNED_6
6108 BFD_RELOC_CRIS_SIGNED_8
6110 BFD_RELOC_CRIS_UNSIGNED_8
6112 BFD_RELOC_CRIS_SIGNED_16
6114 BFD_RELOC_CRIS_UNSIGNED_16
6116 BFD_RELOC_CRIS_LAPCQ_OFFSET
6118 BFD_RELOC_CRIS_UNSIGNED_4
6120 These relocs are only used within the CRIS assembler. They are not
6121 (at present) written to any object files.
6125 BFD_RELOC_CRIS_GLOB_DAT
6127 BFD_RELOC_CRIS_JUMP_SLOT
6129 BFD_RELOC_CRIS_RELATIVE
6131 Relocs used in ELF shared libraries for CRIS.
6133 BFD_RELOC_CRIS_32_GOT
6135 32-bit offset to symbol-entry within GOT.
6137 BFD_RELOC_CRIS_16_GOT
6139 16-bit offset to symbol-entry within GOT.
6141 BFD_RELOC_CRIS_32_GOTPLT
6143 32-bit offset to symbol-entry within GOT, with PLT handling.
6145 BFD_RELOC_CRIS_16_GOTPLT
6147 16-bit offset to symbol-entry within GOT, with PLT handling.
6149 BFD_RELOC_CRIS_32_GOTREL
6151 32-bit offset to symbol, relative to GOT.
6153 BFD_RELOC_CRIS_32_PLT_GOTREL
6155 32-bit offset to symbol with PLT entry, relative to GOT.
6157 BFD_RELOC_CRIS_32_PLT_PCREL
6159 32-bit offset to symbol with PLT entry, relative to this relocation.
6162 BFD_RELOC_CRIS_32_GOT_GD
6164 BFD_RELOC_CRIS_16_GOT_GD
6166 BFD_RELOC_CRIS_32_GD
6170 BFD_RELOC_CRIS_32_DTPREL
6172 BFD_RELOC_CRIS_16_DTPREL
6174 BFD_RELOC_CRIS_32_GOT_TPREL
6176 BFD_RELOC_CRIS_16_GOT_TPREL
6178 BFD_RELOC_CRIS_32_TPREL
6180 BFD_RELOC_CRIS_16_TPREL
6182 BFD_RELOC_CRIS_DTPMOD
6184 BFD_RELOC_CRIS_32_IE
6186 Relocs used in TLS code for CRIS.
6191 BFD_RELOC_860_GLOB_DAT
6193 BFD_RELOC_860_JUMP_SLOT
6195 BFD_RELOC_860_RELATIVE
6205 BFD_RELOC_860_SPLIT0
6209 BFD_RELOC_860_SPLIT1
6213 BFD_RELOC_860_SPLIT2
6217 BFD_RELOC_860_LOGOT0
6219 BFD_RELOC_860_SPGOT0
6221 BFD_RELOC_860_LOGOT1
6223 BFD_RELOC_860_SPGOT1
6225 BFD_RELOC_860_LOGOTOFF0
6227 BFD_RELOC_860_SPGOTOFF0
6229 BFD_RELOC_860_LOGOTOFF1
6231 BFD_RELOC_860_SPGOTOFF1
6233 BFD_RELOC_860_LOGOTOFF2
6235 BFD_RELOC_860_LOGOTOFF3
6239 BFD_RELOC_860_HIGHADJ
6243 BFD_RELOC_860_HAGOTOFF
6251 BFD_RELOC_860_HIGOTOFF
6253 Intel i860 Relocations.
6256 BFD_RELOC_OR1K_REL_26
6258 BFD_RELOC_OR1K_GOTPC_HI16
6260 BFD_RELOC_OR1K_GOTPC_LO16
6262 BFD_RELOC_OR1K_GOT16
6264 BFD_RELOC_OR1K_PLT26
6266 BFD_RELOC_OR1K_GOTOFF_HI16
6268 BFD_RELOC_OR1K_GOTOFF_LO16
6272 BFD_RELOC_OR1K_GLOB_DAT
6274 BFD_RELOC_OR1K_JMP_SLOT
6276 BFD_RELOC_OR1K_RELATIVE
6278 BFD_RELOC_OR1K_TLS_GD_HI16
6280 BFD_RELOC_OR1K_TLS_GD_LO16
6282 BFD_RELOC_OR1K_TLS_LDM_HI16
6284 BFD_RELOC_OR1K_TLS_LDM_LO16
6286 BFD_RELOC_OR1K_TLS_LDO_HI16
6288 BFD_RELOC_OR1K_TLS_LDO_LO16
6290 BFD_RELOC_OR1K_TLS_IE_HI16
6292 BFD_RELOC_OR1K_TLS_IE_LO16
6294 BFD_RELOC_OR1K_TLS_LE_HI16
6296 BFD_RELOC_OR1K_TLS_LE_LO16
6298 BFD_RELOC_OR1K_TLS_TPOFF
6300 BFD_RELOC_OR1K_TLS_DTPOFF
6302 BFD_RELOC_OR1K_TLS_DTPMOD
6304 OpenRISC 1000 Relocations.
6307 BFD_RELOC_H8_DIR16A8
6309 BFD_RELOC_H8_DIR16R8
6311 BFD_RELOC_H8_DIR24A8
6313 BFD_RELOC_H8_DIR24R8
6315 BFD_RELOC_H8_DIR32A16
6317 BFD_RELOC_H8_DISP32A16
6322 BFD_RELOC_XSTORMY16_REL_12
6324 BFD_RELOC_XSTORMY16_12
6326 BFD_RELOC_XSTORMY16_24
6328 BFD_RELOC_XSTORMY16_FPTR16
6330 Sony Xstormy16 Relocations.
6335 Self-describing complex relocations.
6347 Infineon Relocations.
6350 BFD_RELOC_VAX_GLOB_DAT
6352 BFD_RELOC_VAX_JMP_SLOT
6354 BFD_RELOC_VAX_RELATIVE
6356 Relocations used by VAX ELF.
6361 Morpho MT - 16 bit immediate relocation.
6365 Morpho MT - Hi 16 bits of an address.
6369 Morpho MT - Low 16 bits of an address.
6371 BFD_RELOC_MT_GNU_VTINHERIT
6373 Morpho MT - Used to tell the linker which vtable entries are used.
6375 BFD_RELOC_MT_GNU_VTENTRY
6377 Morpho MT - Used to tell the linker which vtable entries are used.
6379 BFD_RELOC_MT_PCINSN8
6381 Morpho MT - 8 bit immediate relocation.
6384 BFD_RELOC_MSP430_10_PCREL
6386 BFD_RELOC_MSP430_16_PCREL
6390 BFD_RELOC_MSP430_16_PCREL_BYTE
6392 BFD_RELOC_MSP430_16_BYTE
6394 BFD_RELOC_MSP430_2X_PCREL
6396 BFD_RELOC_MSP430_RL_PCREL
6398 BFD_RELOC_MSP430_ABS8
6400 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6402 BFD_RELOC_MSP430X_PCR20_EXT_DST
6404 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6406 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6408 BFD_RELOC_MSP430X_ABS20_EXT_DST
6410 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6412 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6414 BFD_RELOC_MSP430X_ABS20_ADR_DST
6416 BFD_RELOC_MSP430X_PCR16
6418 BFD_RELOC_MSP430X_PCR20_CALL
6420 BFD_RELOC_MSP430X_ABS16
6422 BFD_RELOC_MSP430_ABS_HI16
6424 BFD_RELOC_MSP430_PREL31
6426 BFD_RELOC_MSP430_SYM_DIFF
6428 msp430 specific relocation codes
6435 BFD_RELOC_NIOS2_CALL26
6437 BFD_RELOC_NIOS2_IMM5
6439 BFD_RELOC_NIOS2_CACHE_OPX
6441 BFD_RELOC_NIOS2_IMM6
6443 BFD_RELOC_NIOS2_IMM8
6445 BFD_RELOC_NIOS2_HI16
6447 BFD_RELOC_NIOS2_LO16
6449 BFD_RELOC_NIOS2_HIADJ16
6451 BFD_RELOC_NIOS2_GPREL
6453 BFD_RELOC_NIOS2_UJMP
6455 BFD_RELOC_NIOS2_CJMP
6457 BFD_RELOC_NIOS2_CALLR
6459 BFD_RELOC_NIOS2_ALIGN
6461 BFD_RELOC_NIOS2_GOT16
6463 BFD_RELOC_NIOS2_CALL16
6465 BFD_RELOC_NIOS2_GOTOFF_LO
6467 BFD_RELOC_NIOS2_GOTOFF_HA
6469 BFD_RELOC_NIOS2_PCREL_LO
6471 BFD_RELOC_NIOS2_PCREL_HA
6473 BFD_RELOC_NIOS2_TLS_GD16
6475 BFD_RELOC_NIOS2_TLS_LDM16
6477 BFD_RELOC_NIOS2_TLS_LDO16
6479 BFD_RELOC_NIOS2_TLS_IE16
6481 BFD_RELOC_NIOS2_TLS_LE16
6483 BFD_RELOC_NIOS2_TLS_DTPMOD
6485 BFD_RELOC_NIOS2_TLS_DTPREL
6487 BFD_RELOC_NIOS2_TLS_TPREL
6489 BFD_RELOC_NIOS2_COPY
6491 BFD_RELOC_NIOS2_GLOB_DAT
6493 BFD_RELOC_NIOS2_JUMP_SLOT
6495 BFD_RELOC_NIOS2_RELATIVE
6497 BFD_RELOC_NIOS2_GOTOFF
6499 BFD_RELOC_NIOS2_CALL26_NOAT
6501 BFD_RELOC_NIOS2_GOT_LO
6503 BFD_RELOC_NIOS2_GOT_HA
6505 BFD_RELOC_NIOS2_CALL_LO
6507 BFD_RELOC_NIOS2_CALL_HA
6509 BFD_RELOC_NIOS2_R2_S12
6511 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6513 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6515 BFD_RELOC_NIOS2_R2_T1I7_2
6517 BFD_RELOC_NIOS2_R2_T2I4
6519 BFD_RELOC_NIOS2_R2_T2I4_1
6521 BFD_RELOC_NIOS2_R2_T2I4_2
6523 BFD_RELOC_NIOS2_R2_X1I7_2
6525 BFD_RELOC_NIOS2_R2_X2L5
6527 BFD_RELOC_NIOS2_R2_F1I5_2
6529 BFD_RELOC_NIOS2_R2_L5I4X1
6531 BFD_RELOC_NIOS2_R2_T1X1I6
6533 BFD_RELOC_NIOS2_R2_T1X1I6_2
6535 Relocations used by the Altera Nios II core.
6540 PRU LDI 16-bit unsigned data-memory relocation.
6542 BFD_RELOC_PRU_U16_PMEMIMM
6544 PRU LDI 16-bit unsigned instruction-memory relocation.
6548 PRU relocation for two consecutive LDI load instructions that load a
6549 32 bit value into a register. If the higher bits are all zero, then
6550 the second instruction may be relaxed.
6552 BFD_RELOC_PRU_S10_PCREL
6554 PRU QBBx 10-bit signed PC-relative relocation.
6556 BFD_RELOC_PRU_U8_PCREL
6558 PRU 8-bit unsigned relocation used for the LOOP instruction.
6560 BFD_RELOC_PRU_32_PMEM
6562 BFD_RELOC_PRU_16_PMEM
6564 PRU Program Memory relocations. Used to convert from byte addressing to
6565 32-bit word addressing.
6567 BFD_RELOC_PRU_GNU_DIFF8
6569 BFD_RELOC_PRU_GNU_DIFF16
6571 BFD_RELOC_PRU_GNU_DIFF32
6573 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6575 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6577 PRU relocations to mark the difference of two local symbols.
6578 These are only needed to support linker relaxation and can be ignored
6579 when not relaxing. The field is set to the value of the difference
6580 assuming no relaxation. The relocation encodes the position of the
6581 second symbol so the linker can determine whether to adjust the field
6582 value. The PMEM variants encode the word difference, instead of byte
6583 difference between symbols.
6586 BFD_RELOC_IQ2000_OFFSET_16
6588 BFD_RELOC_IQ2000_OFFSET_21
6590 BFD_RELOC_IQ2000_UHI16
6595 BFD_RELOC_XTENSA_RTLD
6597 Special Xtensa relocation used only by PLT entries in ELF shared
6598 objects to indicate that the runtime linker should set the value
6599 to one of its own internal functions or data structures.
6601 BFD_RELOC_XTENSA_GLOB_DAT
6603 BFD_RELOC_XTENSA_JMP_SLOT
6605 BFD_RELOC_XTENSA_RELATIVE
6607 Xtensa relocations for ELF shared objects.
6609 BFD_RELOC_XTENSA_PLT
6611 Xtensa relocation used in ELF object files for symbols that may require
6612 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6614 BFD_RELOC_XTENSA_DIFF8
6616 BFD_RELOC_XTENSA_DIFF16
6618 BFD_RELOC_XTENSA_DIFF32
6620 Xtensa relocations to mark the difference of two local symbols.
6621 These are only needed to support linker relaxation and can be ignored
6622 when not relaxing. The field is set to the value of the difference
6623 assuming no relaxation. The relocation encodes the position of the
6624 first symbol so the linker can determine whether to adjust the field
6627 BFD_RELOC_XTENSA_SLOT0_OP
6629 BFD_RELOC_XTENSA_SLOT1_OP
6631 BFD_RELOC_XTENSA_SLOT2_OP
6633 BFD_RELOC_XTENSA_SLOT3_OP
6635 BFD_RELOC_XTENSA_SLOT4_OP
6637 BFD_RELOC_XTENSA_SLOT5_OP
6639 BFD_RELOC_XTENSA_SLOT6_OP
6641 BFD_RELOC_XTENSA_SLOT7_OP
6643 BFD_RELOC_XTENSA_SLOT8_OP
6645 BFD_RELOC_XTENSA_SLOT9_OP
6647 BFD_RELOC_XTENSA_SLOT10_OP
6649 BFD_RELOC_XTENSA_SLOT11_OP
6651 BFD_RELOC_XTENSA_SLOT12_OP
6653 BFD_RELOC_XTENSA_SLOT13_OP
6655 BFD_RELOC_XTENSA_SLOT14_OP
6657 Generic Xtensa relocations for instruction operands. Only the slot
6658 number is encoded in the relocation. The relocation applies to the
6659 last PC-relative immediate operand, or if there are no PC-relative
6660 immediates, to the last immediate operand.
6662 BFD_RELOC_XTENSA_SLOT0_ALT
6664 BFD_RELOC_XTENSA_SLOT1_ALT
6666 BFD_RELOC_XTENSA_SLOT2_ALT
6668 BFD_RELOC_XTENSA_SLOT3_ALT
6670 BFD_RELOC_XTENSA_SLOT4_ALT
6672 BFD_RELOC_XTENSA_SLOT5_ALT
6674 BFD_RELOC_XTENSA_SLOT6_ALT
6676 BFD_RELOC_XTENSA_SLOT7_ALT
6678 BFD_RELOC_XTENSA_SLOT8_ALT
6680 BFD_RELOC_XTENSA_SLOT9_ALT
6682 BFD_RELOC_XTENSA_SLOT10_ALT
6684 BFD_RELOC_XTENSA_SLOT11_ALT
6686 BFD_RELOC_XTENSA_SLOT12_ALT
6688 BFD_RELOC_XTENSA_SLOT13_ALT
6690 BFD_RELOC_XTENSA_SLOT14_ALT
6692 Alternate Xtensa relocations. Only the slot is encoded in the
6693 relocation. The meaning of these relocations is opcode-specific.
6695 BFD_RELOC_XTENSA_OP0
6697 BFD_RELOC_XTENSA_OP1
6699 BFD_RELOC_XTENSA_OP2
6701 Xtensa relocations for backward compatibility. These have all been
6702 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6704 BFD_RELOC_XTENSA_ASM_EXPAND
6706 Xtensa relocation to mark that the assembler expanded the
6707 instructions from an original target. The expansion size is
6708 encoded in the reloc size.
6710 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6712 Xtensa relocation to mark that the linker should simplify
6713 assembler-expanded instructions. This is commonly used
6714 internally by the linker after analysis of a
6715 BFD_RELOC_XTENSA_ASM_EXPAND.
6717 BFD_RELOC_XTENSA_TLSDESC_FN
6719 BFD_RELOC_XTENSA_TLSDESC_ARG
6721 BFD_RELOC_XTENSA_TLS_DTPOFF
6723 BFD_RELOC_XTENSA_TLS_TPOFF
6725 BFD_RELOC_XTENSA_TLS_FUNC
6727 BFD_RELOC_XTENSA_TLS_ARG
6729 BFD_RELOC_XTENSA_TLS_CALL
6731 Xtensa TLS relocations.
6736 8 bit signed offset in (ix+d) or (iy+d).
6754 BFD_RELOC_LM32_BRANCH
6756 BFD_RELOC_LM32_16_GOT
6758 BFD_RELOC_LM32_GOTOFF_HI16
6760 BFD_RELOC_LM32_GOTOFF_LO16
6764 BFD_RELOC_LM32_GLOB_DAT
6766 BFD_RELOC_LM32_JMP_SLOT
6768 BFD_RELOC_LM32_RELATIVE
6770 Lattice Mico32 relocations.
6773 BFD_RELOC_MACH_O_SECTDIFF
6775 Difference between two section addreses. Must be followed by a
6776 BFD_RELOC_MACH_O_PAIR.
6778 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6780 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6782 BFD_RELOC_MACH_O_PAIR
6784 Pair of relocation. Contains the first symbol.
6786 BFD_RELOC_MACH_O_SUBTRACTOR32
6788 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6790 BFD_RELOC_MACH_O_SUBTRACTOR64
6792 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6795 BFD_RELOC_MACH_O_X86_64_BRANCH32
6797 BFD_RELOC_MACH_O_X86_64_BRANCH8
6799 PCREL relocations. They are marked as branch to create PLT entry if
6802 BFD_RELOC_MACH_O_X86_64_GOT
6804 Used when referencing a GOT entry.
6806 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6808 Used when loading a GOT entry with movq. It is specially marked so that
6809 the linker could optimize the movq to a leaq if possible.
6811 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6813 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6815 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6817 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6819 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6821 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6825 BFD_RELOC_MACH_O_ARM64_ADDEND
6827 Addend for PAGE or PAGEOFF.
6829 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6831 Relative offset to page of GOT slot.
6833 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6835 Relative offset within page of GOT slot.
6837 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6839 Address of a GOT entry.
6842 BFD_RELOC_MICROBLAZE_32_LO
6844 This is a 32 bit reloc for the microblaze that stores the
6845 low 16 bits of a value
6847 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6849 This is a 32 bit pc-relative reloc for the microblaze that
6850 stores the low 16 bits of a value
6852 BFD_RELOC_MICROBLAZE_32_ROSDA
6854 This is a 32 bit reloc for the microblaze that stores a
6855 value relative to the read-only small data area anchor
6857 BFD_RELOC_MICROBLAZE_32_RWSDA
6859 This is a 32 bit reloc for the microblaze that stores a
6860 value relative to the read-write small data area anchor
6862 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6864 This is a 32 bit reloc for the microblaze to handle
6865 expressions of the form "Symbol Op Symbol"
6867 BFD_RELOC_MICROBLAZE_64_NONE
6869 This is a 64 bit reloc that stores the 32 bit pc relative
6870 value in two words (with an imm instruction). No relocation is
6871 done here - only used for relaxing
6873 BFD_RELOC_MICROBLAZE_64_GOTPC
6875 This is a 64 bit reloc that stores the 32 bit pc relative
6876 value in two words (with an imm instruction). The relocation is
6877 PC-relative GOT offset
6879 BFD_RELOC_MICROBLAZE_64_GOT
6881 This is a 64 bit reloc that stores the 32 bit pc relative
6882 value in two words (with an imm instruction). The relocation is
6885 BFD_RELOC_MICROBLAZE_64_PLT
6887 This is a 64 bit reloc that stores the 32 bit pc relative
6888 value in two words (with an imm instruction). The relocation is
6889 PC-relative offset into PLT
6891 BFD_RELOC_MICROBLAZE_64_GOTOFF
6893 This is a 64 bit reloc that stores the 32 bit GOT relative
6894 value in two words (with an imm instruction). The relocation is
6895 relative offset from _GLOBAL_OFFSET_TABLE_
6897 BFD_RELOC_MICROBLAZE_32_GOTOFF
6899 This is a 32 bit reloc that stores the 32 bit GOT relative
6900 value in a word. The relocation is relative offset from
6901 _GLOBAL_OFFSET_TABLE_
6903 BFD_RELOC_MICROBLAZE_COPY
6905 This is used to tell the dynamic linker to copy the value out of
6906 the dynamic object into the runtime process image.
6908 BFD_RELOC_MICROBLAZE_64_TLS
6912 BFD_RELOC_MICROBLAZE_64_TLSGD
6914 This is a 64 bit reloc that stores the 32 bit GOT relative value
6915 of the GOT TLS GD info entry in two words (with an imm instruction). The
6916 relocation is GOT offset.
6918 BFD_RELOC_MICROBLAZE_64_TLSLD
6920 This is a 64 bit reloc that stores the 32 bit GOT relative value
6921 of the GOT TLS LD info entry in two words (with an imm instruction). The
6922 relocation is GOT offset.
6924 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6926 This is a 32 bit reloc that stores the Module ID to GOT(n).
6928 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6930 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6932 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6934 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6937 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6939 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6940 to two words (uses imm instruction).
6942 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6944 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6945 to two words (uses imm instruction).
6948 BFD_RELOC_AARCH64_RELOC_START
6950 AArch64 pseudo relocation code to mark the start of the AArch64
6951 relocation enumerators. N.B. the order of the enumerators is
6952 important as several tables in the AArch64 bfd backend are indexed
6953 by these enumerators; make sure they are all synced.
6955 BFD_RELOC_AARCH64_NULL
6957 Deprecated AArch64 null relocation code.
6959 BFD_RELOC_AARCH64_NONE
6961 AArch64 null relocation code.
6963 BFD_RELOC_AARCH64_64
6965 BFD_RELOC_AARCH64_32
6967 BFD_RELOC_AARCH64_16
6969 Basic absolute relocations of N bits. These are equivalent to
6970 BFD_RELOC_N and they were added to assist the indexing of the howto
6973 BFD_RELOC_AARCH64_64_PCREL
6975 BFD_RELOC_AARCH64_32_PCREL
6977 BFD_RELOC_AARCH64_16_PCREL
6979 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6980 and they were added to assist the indexing of the howto table.
6982 BFD_RELOC_AARCH64_MOVW_G0
6984 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6985 of an unsigned address/value.
6987 BFD_RELOC_AARCH64_MOVW_G0_NC
6989 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6990 an address/value. No overflow checking.
6992 BFD_RELOC_AARCH64_MOVW_G1
6994 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6995 of an unsigned address/value.
6997 BFD_RELOC_AARCH64_MOVW_G1_NC
6999 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7000 of an address/value. No overflow checking.
7002 BFD_RELOC_AARCH64_MOVW_G2
7004 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7005 of an unsigned address/value.
7007 BFD_RELOC_AARCH64_MOVW_G2_NC
7009 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7010 of an address/value. No overflow checking.
7012 BFD_RELOC_AARCH64_MOVW_G3
7014 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7015 of a signed or unsigned address/value.
7017 BFD_RELOC_AARCH64_MOVW_G0_S
7019 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7020 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7023 BFD_RELOC_AARCH64_MOVW_G1_S
7025 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7026 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7029 BFD_RELOC_AARCH64_MOVW_G2_S
7031 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7032 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7035 BFD_RELOC_AARCH64_LD_LO19_PCREL
7037 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7038 offset. The lowest two bits must be zero and are not stored in the
7039 instruction, giving a 21 bit signed byte offset.
7041 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7043 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7045 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7047 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7048 offset, giving a 4KB aligned page base address.
7050 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7052 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7053 offset, giving a 4KB aligned page base address, but with no overflow
7056 BFD_RELOC_AARCH64_ADD_LO12
7058 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7059 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7061 BFD_RELOC_AARCH64_LDST8_LO12
7063 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7064 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7066 BFD_RELOC_AARCH64_TSTBR14
7068 AArch64 14 bit pc-relative test bit and branch.
7069 The lowest two bits must be zero and are not stored in the instruction,
7070 giving a 16 bit signed byte offset.
7072 BFD_RELOC_AARCH64_BRANCH19
7074 AArch64 19 bit pc-relative conditional branch and compare & branch.
7075 The lowest two bits must be zero and are not stored in the instruction,
7076 giving a 21 bit signed byte offset.
7078 BFD_RELOC_AARCH64_JUMP26
7080 AArch64 26 bit pc-relative unconditional branch.
7081 The lowest two bits must be zero and are not stored in the instruction,
7082 giving a 28 bit signed byte offset.
7084 BFD_RELOC_AARCH64_CALL26
7086 AArch64 26 bit pc-relative unconditional branch and link.
7087 The lowest two bits must be zero and are not stored in the instruction,
7088 giving a 28 bit signed byte offset.
7090 BFD_RELOC_AARCH64_LDST16_LO12
7092 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7093 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7095 BFD_RELOC_AARCH64_LDST32_LO12
7097 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7098 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7100 BFD_RELOC_AARCH64_LDST64_LO12
7102 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7103 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7105 BFD_RELOC_AARCH64_LDST128_LO12
7107 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7108 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7110 BFD_RELOC_AARCH64_GOT_LD_PREL19
7112 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7113 offset of the global offset table entry for a symbol. The lowest two
7114 bits must be zero and are not stored in the instruction, giving a 21
7115 bit signed byte offset. This relocation type requires signed overflow
7118 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7120 Get to the page base of the global offset table entry for a symbol as
7121 part of an ADRP instruction using a 21 bit PC relative value.Used in
7122 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7124 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7126 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7127 the GOT entry for this symbol. Used in conjunction with
7128 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7130 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7132 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7133 the GOT entry for this symbol. Used in conjunction with
7134 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7136 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7138 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7139 for this symbol. Valid in LP64 ABI only.
7141 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7143 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7144 for this symbol. Valid in LP64 ABI only.
7146 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7148 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7149 the GOT entry for this symbol. Valid in LP64 ABI only.
7151 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7153 Scaled 14 bit byte offset to the page base of the global offset table.
7155 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7157 Scaled 15 bit byte offset to the page base of the global offset table.
7159 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7161 Get to the page base of the global offset table entry for a symbols
7162 tls_index structure as part of an adrp instruction using a 21 bit PC
7163 relative value. Used in conjunction with
7164 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7166 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7168 AArch64 TLS General Dynamic
7170 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7172 Unsigned 12 bit byte offset to global offset table entry for a symbols
7173 tls_index structure. Used in conjunction with
7174 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7176 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7178 AArch64 TLS General Dynamic relocation.
7180 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7182 AArch64 TLS General Dynamic relocation.
7184 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7186 AArch64 TLS INITIAL EXEC relocation.
7188 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7190 AArch64 TLS INITIAL EXEC relocation.
7192 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7194 AArch64 TLS INITIAL EXEC relocation.
7196 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7198 AArch64 TLS INITIAL EXEC relocation.
7200 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7202 AArch64 TLS INITIAL EXEC relocation.
7204 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7206 AArch64 TLS INITIAL EXEC relocation.
7208 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7210 bit[23:12] of byte offset to module TLS base address.
7212 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7214 Unsigned 12 bit byte offset to module TLS base address.
7216 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7218 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7220 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7222 Unsigned 12 bit byte offset to global offset table entry for a symbols
7223 tls_index structure. Used in conjunction with
7224 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7226 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7228 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7231 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7233 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7235 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7237 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7240 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7242 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7244 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7246 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7249 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7251 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7253 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7255 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7258 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7260 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7262 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7264 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7267 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7269 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7271 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7273 bit[15:0] of byte offset to module TLS base address.
7275 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7277 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7279 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7281 bit[31:16] of byte offset to module TLS base address.
7283 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7285 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7287 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7289 bit[47:32] of byte offset to module TLS base address.
7291 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7293 AArch64 TLS LOCAL EXEC relocation.
7295 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7297 AArch64 TLS LOCAL EXEC relocation.
7299 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7301 AArch64 TLS LOCAL EXEC relocation.
7303 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7305 AArch64 TLS LOCAL EXEC relocation.
7307 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7309 AArch64 TLS LOCAL EXEC relocation.
7311 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7313 AArch64 TLS LOCAL EXEC relocation.
7315 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7317 AArch64 TLS LOCAL EXEC relocation.
7319 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7321 AArch64 TLS LOCAL EXEC relocation.
7323 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7325 AArch64 TLS DESC relocation.
7327 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7329 AArch64 TLS DESC relocation.
7331 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7333 AArch64 TLS DESC relocation.
7335 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7337 AArch64 TLS DESC relocation.
7339 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7341 AArch64 TLS DESC relocation.
7343 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7345 AArch64 TLS DESC relocation.
7347 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7349 AArch64 TLS DESC relocation.
7351 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7353 AArch64 TLS DESC relocation.
7355 BFD_RELOC_AARCH64_TLSDESC_LDR
7357 AArch64 TLS DESC relocation.
7359 BFD_RELOC_AARCH64_TLSDESC_ADD
7361 AArch64 TLS DESC relocation.
7363 BFD_RELOC_AARCH64_TLSDESC_CALL
7365 AArch64 TLS DESC relocation.
7367 BFD_RELOC_AARCH64_COPY
7369 AArch64 TLS relocation.
7371 BFD_RELOC_AARCH64_GLOB_DAT
7373 AArch64 TLS relocation.
7375 BFD_RELOC_AARCH64_JUMP_SLOT
7377 AArch64 TLS relocation.
7379 BFD_RELOC_AARCH64_RELATIVE
7381 AArch64 TLS relocation.
7383 BFD_RELOC_AARCH64_TLS_DTPMOD
7385 AArch64 TLS relocation.
7387 BFD_RELOC_AARCH64_TLS_DTPREL
7389 AArch64 TLS relocation.
7391 BFD_RELOC_AARCH64_TLS_TPREL
7393 AArch64 TLS relocation.
7395 BFD_RELOC_AARCH64_TLSDESC
7397 AArch64 TLS relocation.
7399 BFD_RELOC_AARCH64_IRELATIVE
7401 AArch64 support for STT_GNU_IFUNC.
7403 BFD_RELOC_AARCH64_RELOC_END
7405 AArch64 pseudo relocation code to mark the end of the AArch64
7406 relocation enumerators that have direct mapping to ELF reloc codes.
7407 There are a few more enumerators after this one; those are mainly
7408 used by the AArch64 assembler for the internal fixup or to select
7409 one of the above enumerators.
7411 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7413 AArch64 pseudo relocation code to be used internally by the AArch64
7414 assembler and not (currently) written to any object files.
7416 BFD_RELOC_AARCH64_LDST_LO12
7418 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7419 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7421 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7423 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7424 used internally by the AArch64 assembler and not (currently) written to
7427 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7429 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7431 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7433 AArch64 pseudo relocation code to be used internally by the AArch64
7434 assembler and not (currently) written to any object files.
7436 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7438 AArch64 pseudo relocation code to be used internally by the AArch64
7439 assembler and not (currently) written to any object files.
7441 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7443 AArch64 pseudo relocation code to be used internally by the AArch64
7444 assembler and not (currently) written to any object files.
7446 BFD_RELOC_TILEPRO_COPY
7448 BFD_RELOC_TILEPRO_GLOB_DAT
7450 BFD_RELOC_TILEPRO_JMP_SLOT
7452 BFD_RELOC_TILEPRO_RELATIVE
7454 BFD_RELOC_TILEPRO_BROFF_X1
7456 BFD_RELOC_TILEPRO_JOFFLONG_X1
7458 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7460 BFD_RELOC_TILEPRO_IMM8_X0
7462 BFD_RELOC_TILEPRO_IMM8_Y0
7464 BFD_RELOC_TILEPRO_IMM8_X1
7466 BFD_RELOC_TILEPRO_IMM8_Y1
7468 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7470 BFD_RELOC_TILEPRO_MT_IMM15_X1
7472 BFD_RELOC_TILEPRO_MF_IMM15_X1
7474 BFD_RELOC_TILEPRO_IMM16_X0
7476 BFD_RELOC_TILEPRO_IMM16_X1
7478 BFD_RELOC_TILEPRO_IMM16_X0_LO
7480 BFD_RELOC_TILEPRO_IMM16_X1_LO
7482 BFD_RELOC_TILEPRO_IMM16_X0_HI
7484 BFD_RELOC_TILEPRO_IMM16_X1_HI
7486 BFD_RELOC_TILEPRO_IMM16_X0_HA
7488 BFD_RELOC_TILEPRO_IMM16_X1_HA
7490 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7492 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7494 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7496 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7498 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7500 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7502 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7504 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7506 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7508 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7510 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7512 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7514 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7516 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7518 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7520 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7522 BFD_RELOC_TILEPRO_MMSTART_X0
7524 BFD_RELOC_TILEPRO_MMEND_X0
7526 BFD_RELOC_TILEPRO_MMSTART_X1
7528 BFD_RELOC_TILEPRO_MMEND_X1
7530 BFD_RELOC_TILEPRO_SHAMT_X0
7532 BFD_RELOC_TILEPRO_SHAMT_X1
7534 BFD_RELOC_TILEPRO_SHAMT_Y0
7536 BFD_RELOC_TILEPRO_SHAMT_Y1
7538 BFD_RELOC_TILEPRO_TLS_GD_CALL
7540 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7542 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7544 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7546 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7548 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7550 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7552 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7554 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7556 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7558 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7560 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7562 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7564 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7566 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7568 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7570 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7572 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7574 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7576 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7578 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7580 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7582 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7584 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7586 BFD_RELOC_TILEPRO_TLS_TPOFF32
7588 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7590 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7592 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7594 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7596 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7598 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7600 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7602 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7604 Tilera TILEPro Relocations.
7606 BFD_RELOC_TILEGX_HW0
7608 BFD_RELOC_TILEGX_HW1
7610 BFD_RELOC_TILEGX_HW2
7612 BFD_RELOC_TILEGX_HW3
7614 BFD_RELOC_TILEGX_HW0_LAST
7616 BFD_RELOC_TILEGX_HW1_LAST
7618 BFD_RELOC_TILEGX_HW2_LAST
7620 BFD_RELOC_TILEGX_COPY
7622 BFD_RELOC_TILEGX_GLOB_DAT
7624 BFD_RELOC_TILEGX_JMP_SLOT
7626 BFD_RELOC_TILEGX_RELATIVE
7628 BFD_RELOC_TILEGX_BROFF_X1
7630 BFD_RELOC_TILEGX_JUMPOFF_X1
7632 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7634 BFD_RELOC_TILEGX_IMM8_X0
7636 BFD_RELOC_TILEGX_IMM8_Y0
7638 BFD_RELOC_TILEGX_IMM8_X1
7640 BFD_RELOC_TILEGX_IMM8_Y1
7642 BFD_RELOC_TILEGX_DEST_IMM8_X1
7644 BFD_RELOC_TILEGX_MT_IMM14_X1
7646 BFD_RELOC_TILEGX_MF_IMM14_X1
7648 BFD_RELOC_TILEGX_MMSTART_X0
7650 BFD_RELOC_TILEGX_MMEND_X0
7652 BFD_RELOC_TILEGX_SHAMT_X0
7654 BFD_RELOC_TILEGX_SHAMT_X1
7656 BFD_RELOC_TILEGX_SHAMT_Y0
7658 BFD_RELOC_TILEGX_SHAMT_Y1
7660 BFD_RELOC_TILEGX_IMM16_X0_HW0
7662 BFD_RELOC_TILEGX_IMM16_X1_HW0
7664 BFD_RELOC_TILEGX_IMM16_X0_HW1
7666 BFD_RELOC_TILEGX_IMM16_X1_HW1
7668 BFD_RELOC_TILEGX_IMM16_X0_HW2
7670 BFD_RELOC_TILEGX_IMM16_X1_HW2
7672 BFD_RELOC_TILEGX_IMM16_X0_HW3
7674 BFD_RELOC_TILEGX_IMM16_X1_HW3
7676 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7678 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7680 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7682 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7684 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7686 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7688 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7690 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7692 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7694 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7696 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7698 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7700 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7702 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7704 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7706 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7708 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7710 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7712 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7714 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7716 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7718 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7720 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7722 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7724 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7726 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7728 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7730 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7732 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7734 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7736 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7738 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7740 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7742 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7744 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7746 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7748 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7750 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7752 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7754 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7756 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7758 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7760 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7762 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7764 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7766 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7768 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7770 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7772 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7774 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7776 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7778 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7780 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7782 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7784 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7786 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7788 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7790 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7792 BFD_RELOC_TILEGX_TLS_DTPMOD64
7794 BFD_RELOC_TILEGX_TLS_DTPOFF64
7796 BFD_RELOC_TILEGX_TLS_TPOFF64
7798 BFD_RELOC_TILEGX_TLS_DTPMOD32
7800 BFD_RELOC_TILEGX_TLS_DTPOFF32
7802 BFD_RELOC_TILEGX_TLS_TPOFF32
7804 BFD_RELOC_TILEGX_TLS_GD_CALL
7806 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7808 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7810 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7812 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7814 BFD_RELOC_TILEGX_TLS_IE_LOAD
7816 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7818 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7820 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7822 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7824 Tilera TILE-Gx Relocations.
7827 BFD_RELOC_EPIPHANY_SIMM8
7829 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7831 BFD_RELOC_EPIPHANY_SIMM24
7833 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7835 BFD_RELOC_EPIPHANY_HIGH
7837 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7839 BFD_RELOC_EPIPHANY_LOW
7841 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7843 BFD_RELOC_EPIPHANY_SIMM11
7845 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7847 BFD_RELOC_EPIPHANY_IMM11
7849 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7851 BFD_RELOC_EPIPHANY_IMM8
7853 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7856 BFD_RELOC_VISIUM_HI16
7858 BFD_RELOC_VISIUM_LO16
7860 BFD_RELOC_VISIUM_IM16
7862 BFD_RELOC_VISIUM_REL16
7864 BFD_RELOC_VISIUM_HI16_PCREL
7866 BFD_RELOC_VISIUM_LO16_PCREL
7868 BFD_RELOC_VISIUM_IM16_PCREL
7873 BFD_RELOC_WASM32_LEB128
7875 BFD_RELOC_WASM32_LEB128_GOT
7877 BFD_RELOC_WASM32_LEB128_GOT_CODE
7879 BFD_RELOC_WASM32_LEB128_PLT
7881 BFD_RELOC_WASM32_PLT_INDEX
7883 BFD_RELOC_WASM32_ABS32_CODE
7885 BFD_RELOC_WASM32_COPY
7887 BFD_RELOC_WASM32_CODE_POINTER
7889 BFD_RELOC_WASM32_INDEX
7891 BFD_RELOC_WASM32_PLT_SIG
7893 WebAssembly relocations.
7899 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7904 bfd_reloc_type_lookup
7905 bfd_reloc_name_lookup
7908 reloc_howto_type *bfd_reloc_type_lookup
7909 (bfd *abfd, bfd_reloc_code_real_type code);
7910 reloc_howto_type *bfd_reloc_name_lookup
7911 (bfd *abfd, const char *reloc_name);
7914 Return a pointer to a howto structure which, when
7915 invoked, will perform the relocation @var{code} on data from the
7921 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7923 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7927 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7929 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7932 static reloc_howto_type bfd_howto_32
=
7933 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7937 bfd_default_reloc_type_lookup
7940 reloc_howto_type *bfd_default_reloc_type_lookup
7941 (bfd *abfd, bfd_reloc_code_real_type code);
7944 Provides a default relocation lookup routine for any architecture.
7949 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7953 case BFD_RELOC_CTOR
:
7954 /* The type of reloc used in a ctor, which will be as wide as the
7955 address - so either a 64, 32, or 16 bitter. */
7956 switch (bfd_arch_bits_per_address (abfd
))
7962 return &bfd_howto_32
;
7978 bfd_get_reloc_code_name
7981 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7984 Provides a printable name for the supplied relocation code.
7985 Useful mainly for printing error messages.
7989 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7991 if (code
> BFD_RELOC_UNUSED
)
7993 return bfd_reloc_code_real_names
[code
];
7998 bfd_generic_relax_section
8001 bfd_boolean bfd_generic_relax_section
8004 struct bfd_link_info *,
8008 Provides default handling for relaxing for back ends which
8013 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8014 asection
*section ATTRIBUTE_UNUSED
,
8015 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8018 if (bfd_link_relocatable (link_info
))
8019 (*link_info
->callbacks
->einfo
)
8020 (_("%P%F: --relax and -r may not be used together\n"));
8028 bfd_generic_gc_sections
8031 bfd_boolean bfd_generic_gc_sections
8032 (bfd *, struct bfd_link_info *);
8035 Provides default handling for relaxing for back ends which
8036 don't do section gc -- i.e., does nothing.
8040 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8041 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8048 bfd_generic_lookup_section_flags
8051 bfd_boolean bfd_generic_lookup_section_flags
8052 (struct bfd_link_info *, struct flag_info *, asection *);
8055 Provides default handling for section flags lookup
8056 -- i.e., does nothing.
8057 Returns FALSE if the section should be omitted, otherwise TRUE.
8061 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8062 struct flag_info
*flaginfo
,
8063 asection
*section ATTRIBUTE_UNUSED
)
8065 if (flaginfo
!= NULL
)
8067 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported.\n"));
8075 bfd_generic_merge_sections
8078 bfd_boolean bfd_generic_merge_sections
8079 (bfd *, struct bfd_link_info *);
8082 Provides default handling for SEC_MERGE section merging for back ends
8083 which don't have SEC_MERGE support -- i.e., does nothing.
8087 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8088 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8095 bfd_generic_get_relocated_section_contents
8098 bfd_byte *bfd_generic_get_relocated_section_contents
8100 struct bfd_link_info *link_info,
8101 struct bfd_link_order *link_order,
8103 bfd_boolean relocatable,
8107 Provides default handling of relocation effort for back ends
8108 which can't be bothered to do it efficiently.
8113 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8114 struct bfd_link_info
*link_info
,
8115 struct bfd_link_order
*link_order
,
8117 bfd_boolean relocatable
,
8120 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8121 asection
*input_section
= link_order
->u
.indirect
.section
;
8123 arelent
**reloc_vector
;
8126 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8130 /* Read in the section. */
8131 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8137 if (reloc_size
== 0)
8140 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8141 if (reloc_vector
== NULL
)
8144 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8148 if (reloc_count
< 0)
8151 if (reloc_count
> 0)
8155 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8157 char *error_message
= NULL
;
8159 bfd_reloc_status_type r
;
8161 symbol
= *(*parent
)->sym_ptr_ptr
;
8162 /* PR ld/19628: A specially crafted input file
8163 can result in a NULL symbol pointer here. */
8166 link_info
->callbacks
->einfo
8167 /* xgettext:c-format */
8168 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
8169 abfd
, input_section
, (* parent
)->address
);
8173 if (symbol
->section
&& discarded_section (symbol
->section
))
8176 static reloc_howto_type none_howto
8177 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8178 "unused", FALSE
, 0, 0, FALSE
);
8180 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
8181 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
8183 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8184 (*parent
)->addend
= 0;
8185 (*parent
)->howto
= &none_howto
;
8189 r
= bfd_perform_relocation (input_bfd
,
8193 relocatable
? abfd
: NULL
,
8198 asection
*os
= input_section
->output_section
;
8200 /* A partial link, so keep the relocs. */
8201 os
->orelocation
[os
->reloc_count
] = *parent
;
8205 if (r
!= bfd_reloc_ok
)
8209 case bfd_reloc_undefined
:
8210 (*link_info
->callbacks
->undefined_symbol
)
8211 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8212 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8214 case bfd_reloc_dangerous
:
8215 BFD_ASSERT (error_message
!= NULL
);
8216 (*link_info
->callbacks
->reloc_dangerous
)
8217 (link_info
, error_message
,
8218 input_bfd
, input_section
, (*parent
)->address
);
8220 case bfd_reloc_overflow
:
8221 (*link_info
->callbacks
->reloc_overflow
)
8223 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8224 (*parent
)->howto
->name
, (*parent
)->addend
,
8225 input_bfd
, input_section
, (*parent
)->address
);
8227 case bfd_reloc_outofrange
:
8229 This error can result when processing some partially
8230 complete binaries. Do not abort, but issue an error
8232 link_info
->callbacks
->einfo
8233 /* xgettext:c-format */
8234 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8235 abfd
, input_section
, * parent
);
8238 case bfd_reloc_notsupported
:
8240 This error can result when processing a corrupt binary.
8241 Do not abort. Issue an error message instead. */
8242 link_info
->callbacks
->einfo
8243 /* xgettext:c-format */
8244 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8245 abfd
, input_section
, * parent
);
8249 /* PR 17512; file: 90c2a92e.
8250 Report unexpected results, without aborting. */
8251 link_info
->callbacks
->einfo
8252 /* xgettext:c-format */
8253 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8254 abfd
, input_section
, * parent
, r
);
8262 free (reloc_vector
);
8266 free (reloc_vector
);
8272 _bfd_generic_set_reloc
8275 void _bfd_generic_set_reloc
8279 unsigned int count);
8282 Installs a new set of internal relocations in SECTION.
8286 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8291 section
->orelocation
= relptr
;
8292 section
->reloc_count
= count
;
8297 _bfd_unrecognized_reloc
8300 bfd_boolean _bfd_unrecognized_reloc
8303 unsigned int r_type);
8306 Reports an unrecognized reloc.
8307 Written as a function in order to reduce code duplication.
8308 Returns FALSE so that it can be called from a return statement.
8312 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8314 /* xgettext:c-format */
8315 _bfd_error_handler (_("%B: unrecognized relocation (%#x) in section `%A'"),
8316 abfd
, r_type
, section
);
8318 /* PR 21803: Suggest the most likely cause of this error. */
8319 _bfd_error_handler (_("Is this version of the linker - %s - out of date ?"),
8320 BFD_VERSION_STRING
);
8322 bfd_set_error (bfd_error_bad_value
);