1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2016 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how
,
489 unsigned int bitsize
,
490 unsigned int rightshift
,
491 unsigned int addrsize
,
494 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
495 bfd_reloc_status_type flag
= bfd_reloc_ok
;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask
= N_ONES (bitsize
);
502 signmask
= ~fieldmask
;
503 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
504 a
= (relocation
& addrmask
) >> rightshift
;
508 case complain_overflow_dont
:
511 case complain_overflow_signed
:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask
= ~ (fieldmask
>> 1);
517 case complain_overflow_bitfield
:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
525 flag
= bfd_reloc_overflow
;
528 case complain_overflow_unsigned
:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a
& signmask
) != 0)
531 flag
= bfd_reloc_overflow
;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd
*abfd
,
574 arelent
*reloc_entry
,
576 asection
*input_section
,
578 char **error_message
)
581 bfd_reloc_status_type flag
= bfd_reloc_ok
;
582 bfd_size_type octets
;
583 bfd_vma output_base
= 0;
584 reloc_howto_type
*howto
= reloc_entry
->howto
;
585 asection
*reloc_target_output_section
;
588 symbol
= *(reloc_entry
->sym_ptr_ptr
);
590 /* If we are not producing relocatable output, return an error if
591 the symbol is not defined. An undefined weak symbol is
592 considered to have a value of zero (SVR4 ABI, p. 4-27). */
593 if (bfd_is_und_section (symbol
->section
)
594 && (symbol
->flags
& BSF_WEAK
) == 0
595 && output_bfd
== NULL
)
596 flag
= bfd_reloc_undefined
;
598 /* If there is a function supplied to handle this relocation type,
599 call it. It'll return `bfd_reloc_continue' if further processing
601 if (howto
&& howto
->special_function
)
603 bfd_reloc_status_type cont
;
604 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
605 input_section
, output_bfd
,
607 if (cont
!= bfd_reloc_continue
)
611 if (bfd_is_abs_section (symbol
->section
)
612 && output_bfd
!= NULL
)
614 reloc_entry
->address
+= input_section
->output_offset
;
618 /* PR 17512: file: 0f67f69d. */
620 return bfd_reloc_undefined
;
622 /* Is the address of the relocation really within the section?
623 Include the size of the reloc in the test for out of range addresses.
624 PR 17512: file: c146ab8b, 46dff27f, 38e53ebf. */
625 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
626 if (octets
+ bfd_get_reloc_size (howto
)
627 > bfd_get_section_limit_octets (abfd
, input_section
))
628 return bfd_reloc_outofrange
;
630 /* Work out which section the relocation is targeted at and the
631 initial relocation command value. */
633 /* Get symbol value. (Common symbols are special.) */
634 if (bfd_is_com_section (symbol
->section
))
637 relocation
= symbol
->value
;
639 reloc_target_output_section
= symbol
->section
->output_section
;
641 /* Convert input-section-relative symbol value to absolute. */
642 if ((output_bfd
&& ! howto
->partial_inplace
)
643 || reloc_target_output_section
== NULL
)
646 output_base
= reloc_target_output_section
->vma
;
648 relocation
+= output_base
+ symbol
->section
->output_offset
;
650 /* Add in supplied addend. */
651 relocation
+= reloc_entry
->addend
;
653 /* Here the variable relocation holds the final address of the
654 symbol we are relocating against, plus any addend. */
656 if (howto
->pc_relative
)
658 /* This is a PC relative relocation. We want to set RELOCATION
659 to the distance between the address of the symbol and the
660 location. RELOCATION is already the address of the symbol.
662 We start by subtracting the address of the section containing
665 If pcrel_offset is set, we must further subtract the position
666 of the location within the section. Some targets arrange for
667 the addend to be the negative of the position of the location
668 within the section; for example, i386-aout does this. For
669 i386-aout, pcrel_offset is FALSE. Some other targets do not
670 include the position of the location; for example, m88kbcs,
671 or ELF. For those targets, pcrel_offset is TRUE.
673 If we are producing relocatable output, then we must ensure
674 that this reloc will be correctly computed when the final
675 relocation is done. If pcrel_offset is FALSE we want to wind
676 up with the negative of the location within the section,
677 which means we must adjust the existing addend by the change
678 in the location within the section. If pcrel_offset is TRUE
679 we do not want to adjust the existing addend at all.
681 FIXME: This seems logical to me, but for the case of
682 producing relocatable output it is not what the code
683 actually does. I don't want to change it, because it seems
684 far too likely that something will break. */
687 input_section
->output_section
->vma
+ input_section
->output_offset
;
689 if (howto
->pcrel_offset
)
690 relocation
-= reloc_entry
->address
;
693 if (output_bfd
!= NULL
)
695 if (! howto
->partial_inplace
)
697 /* This is a partial relocation, and we want to apply the relocation
698 to the reloc entry rather than the raw data. Modify the reloc
699 inplace to reflect what we now know. */
700 reloc_entry
->addend
= relocation
;
701 reloc_entry
->address
+= input_section
->output_offset
;
706 /* This is a partial relocation, but inplace, so modify the
709 If we've relocated with a symbol with a section, change
710 into a ref to the section belonging to the symbol. */
712 reloc_entry
->address
+= input_section
->output_offset
;
715 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
716 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
717 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
719 /* For m68k-coff, the addend was being subtracted twice during
720 relocation with -r. Removing the line below this comment
721 fixes that problem; see PR 2953.
723 However, Ian wrote the following, regarding removing the line below,
724 which explains why it is still enabled: --djm
726 If you put a patch like that into BFD you need to check all the COFF
727 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
728 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
729 problem in a different way. There may very well be a reason that the
730 code works as it does.
732 Hmmm. The first obvious point is that bfd_perform_relocation should
733 not have any tests that depend upon the flavour. It's seem like
734 entirely the wrong place for such a thing. The second obvious point
735 is that the current code ignores the reloc addend when producing
736 relocatable output for COFF. That's peculiar. In fact, I really
737 have no idea what the point of the line you want to remove is.
739 A typical COFF reloc subtracts the old value of the symbol and adds in
740 the new value to the location in the object file (if it's a pc
741 relative reloc it adds the difference between the symbol value and the
742 location). When relocating we need to preserve that property.
744 BFD handles this by setting the addend to the negative of the old
745 value of the symbol. Unfortunately it handles common symbols in a
746 non-standard way (it doesn't subtract the old value) but that's a
747 different story (we can't change it without losing backward
748 compatibility with old object files) (coff-i386 does subtract the old
749 value, to be compatible with existing coff-i386 targets, like SCO).
751 So everything works fine when not producing relocatable output. When
752 we are producing relocatable output, logically we should do exactly
753 what we do when not producing relocatable output. Therefore, your
754 patch is correct. In fact, it should probably always just set
755 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
756 add the value into the object file. This won't hurt the COFF code,
757 which doesn't use the addend; I'm not sure what it will do to other
758 formats (the thing to check for would be whether any formats both use
759 the addend and set partial_inplace).
761 When I wanted to make coff-i386 produce relocatable output, I ran
762 into the problem that you are running into: I wanted to remove that
763 line. Rather than risk it, I made the coff-i386 relocs use a special
764 function; it's coff_i386_reloc in coff-i386.c. The function
765 specifically adds the addend field into the object file, knowing that
766 bfd_perform_relocation is not going to. If you remove that line, then
767 coff-i386.c will wind up adding the addend field in twice. It's
768 trivial to fix; it just needs to be done.
770 The problem with removing the line is just that it may break some
771 working code. With BFD it's hard to be sure of anything. The right
772 way to deal with this is simply to build and test at least all the
773 supported COFF targets. It should be straightforward if time and disk
774 space consuming. For each target:
776 2) generate some executable, and link it using -r (I would
777 probably use paranoia.o and link against newlib/libc.a, which
778 for all the supported targets would be available in
779 /usr/cygnus/progressive/H-host/target/lib/libc.a).
780 3) make the change to reloc.c
781 4) rebuild the linker
783 6) if the resulting object files are the same, you have at least
785 7) if they are different you have to figure out which version is
788 relocation
-= reloc_entry
->addend
;
789 reloc_entry
->addend
= 0;
793 reloc_entry
->addend
= relocation
;
798 /* FIXME: This overflow checking is incomplete, because the value
799 might have overflowed before we get here. For a correct check we
800 need to compute the value in a size larger than bitsize, but we
801 can't reasonably do that for a reloc the same size as a host
803 FIXME: We should also do overflow checking on the result after
804 adding in the value contained in the object file. */
805 if (howto
->complain_on_overflow
!= complain_overflow_dont
806 && flag
== bfd_reloc_ok
)
807 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
810 bfd_arch_bits_per_address (abfd
),
813 /* Either we are relocating all the way, or we don't want to apply
814 the relocation to the reloc entry (probably because there isn't
815 any room in the output format to describe addends to relocs). */
817 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
818 (OSF version 1.3, compiler version 3.11). It miscompiles the
832 x <<= (unsigned long) s.i0;
836 printf ("succeeded (%lx)\n", x);
840 relocation
>>= (bfd_vma
) howto
->rightshift
;
842 /* Shift everything up to where it's going to be used. */
843 relocation
<<= (bfd_vma
) howto
->bitpos
;
845 /* Wait for the day when all have the mask in them. */
848 i instruction to be left alone
849 o offset within instruction
850 r relocation offset to apply
859 (( i i i i i o o o o o from bfd_get<size>
860 and S S S S S) to get the size offset we want
861 + r r r r r r r r r r) to get the final value to place
862 and D D D D D to chop to right size
863 -----------------------
866 ( i i i i i o o o o o from bfd_get<size>
867 and N N N N N ) get instruction
868 -----------------------
874 -----------------------
875 = R R R R R R R R R R put into bfd_put<size>
879 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
885 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
887 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
893 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
895 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
900 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
902 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
907 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
908 relocation
= -relocation
;
910 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
916 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
917 relocation
= -relocation
;
919 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
930 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
932 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
939 return bfd_reloc_other
;
947 bfd_install_relocation
950 bfd_reloc_status_type bfd_install_relocation
952 arelent *reloc_entry,
953 void *data, bfd_vma data_start,
954 asection *input_section,
955 char **error_message);
958 This looks remarkably like <<bfd_perform_relocation>>, except it
959 does not expect that the section contents have been filled in.
960 I.e., it's suitable for use when creating, rather than applying
963 For now, this function should be considered reserved for the
967 bfd_reloc_status_type
968 bfd_install_relocation (bfd
*abfd
,
969 arelent
*reloc_entry
,
971 bfd_vma data_start_offset
,
972 asection
*input_section
,
973 char **error_message
)
976 bfd_reloc_status_type flag
= bfd_reloc_ok
;
977 bfd_size_type octets
;
978 bfd_vma output_base
= 0;
979 reloc_howto_type
*howto
= reloc_entry
->howto
;
980 asection
*reloc_target_output_section
;
984 symbol
= *(reloc_entry
->sym_ptr_ptr
);
986 /* If there is a function supplied to handle this relocation type,
987 call it. It'll return `bfd_reloc_continue' if further processing
989 if (howto
&& howto
->special_function
)
991 bfd_reloc_status_type cont
;
993 /* XXX - The special_function calls haven't been fixed up to deal
994 with creating new relocations and section contents. */
995 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
996 /* XXX - Non-portable! */
997 ((bfd_byte
*) data_start
998 - data_start_offset
),
999 input_section
, abfd
, error_message
);
1000 if (cont
!= bfd_reloc_continue
)
1004 if (bfd_is_abs_section (symbol
->section
))
1006 reloc_entry
->address
+= input_section
->output_offset
;
1007 return bfd_reloc_ok
;
1010 /* No need to check for howto != NULL if !bfd_is_abs_section as
1011 it will have been checked in `bfd_perform_relocation already'. */
1013 /* Is the address of the relocation really within the section? */
1014 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1015 if (octets
+ bfd_get_reloc_size (howto
)
1016 > bfd_get_section_limit_octets (abfd
, input_section
))
1017 return bfd_reloc_outofrange
;
1019 /* Work out which section the relocation is targeted at and the
1020 initial relocation command value. */
1022 /* Get symbol value. (Common symbols are special.) */
1023 if (bfd_is_com_section (symbol
->section
))
1026 relocation
= symbol
->value
;
1028 reloc_target_output_section
= symbol
->section
->output_section
;
1030 /* Convert input-section-relative symbol value to absolute. */
1031 if (! howto
->partial_inplace
)
1034 output_base
= reloc_target_output_section
->vma
;
1036 relocation
+= output_base
+ symbol
->section
->output_offset
;
1038 /* Add in supplied addend. */
1039 relocation
+= reloc_entry
->addend
;
1041 /* Here the variable relocation holds the final address of the
1042 symbol we are relocating against, plus any addend. */
1044 if (howto
->pc_relative
)
1046 /* This is a PC relative relocation. We want to set RELOCATION
1047 to the distance between the address of the symbol and the
1048 location. RELOCATION is already the address of the symbol.
1050 We start by subtracting the address of the section containing
1053 If pcrel_offset is set, we must further subtract the position
1054 of the location within the section. Some targets arrange for
1055 the addend to be the negative of the position of the location
1056 within the section; for example, i386-aout does this. For
1057 i386-aout, pcrel_offset is FALSE. Some other targets do not
1058 include the position of the location; for example, m88kbcs,
1059 or ELF. For those targets, pcrel_offset is TRUE.
1061 If we are producing relocatable output, then we must ensure
1062 that this reloc will be correctly computed when the final
1063 relocation is done. If pcrel_offset is FALSE we want to wind
1064 up with the negative of the location within the section,
1065 which means we must adjust the existing addend by the change
1066 in the location within the section. If pcrel_offset is TRUE
1067 we do not want to adjust the existing addend at all.
1069 FIXME: This seems logical to me, but for the case of
1070 producing relocatable output it is not what the code
1071 actually does. I don't want to change it, because it seems
1072 far too likely that something will break. */
1075 input_section
->output_section
->vma
+ input_section
->output_offset
;
1077 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1078 relocation
-= reloc_entry
->address
;
1081 if (! howto
->partial_inplace
)
1083 /* This is a partial relocation, and we want to apply the relocation
1084 to the reloc entry rather than the raw data. Modify the reloc
1085 inplace to reflect what we now know. */
1086 reloc_entry
->addend
= relocation
;
1087 reloc_entry
->address
+= input_section
->output_offset
;
1092 /* This is a partial relocation, but inplace, so modify the
1095 If we've relocated with a symbol with a section, change
1096 into a ref to the section belonging to the symbol. */
1097 reloc_entry
->address
+= input_section
->output_offset
;
1100 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1101 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1102 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1105 /* For m68k-coff, the addend was being subtracted twice during
1106 relocation with -r. Removing the line below this comment
1107 fixes that problem; see PR 2953.
1109 However, Ian wrote the following, regarding removing the line below,
1110 which explains why it is still enabled: --djm
1112 If you put a patch like that into BFD you need to check all the COFF
1113 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1114 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1115 problem in a different way. There may very well be a reason that the
1116 code works as it does.
1118 Hmmm. The first obvious point is that bfd_install_relocation should
1119 not have any tests that depend upon the flavour. It's seem like
1120 entirely the wrong place for such a thing. The second obvious point
1121 is that the current code ignores the reloc addend when producing
1122 relocatable output for COFF. That's peculiar. In fact, I really
1123 have no idea what the point of the line you want to remove is.
1125 A typical COFF reloc subtracts the old value of the symbol and adds in
1126 the new value to the location in the object file (if it's a pc
1127 relative reloc it adds the difference between the symbol value and the
1128 location). When relocating we need to preserve that property.
1130 BFD handles this by setting the addend to the negative of the old
1131 value of the symbol. Unfortunately it handles common symbols in a
1132 non-standard way (it doesn't subtract the old value) but that's a
1133 different story (we can't change it without losing backward
1134 compatibility with old object files) (coff-i386 does subtract the old
1135 value, to be compatible with existing coff-i386 targets, like SCO).
1137 So everything works fine when not producing relocatable output. When
1138 we are producing relocatable output, logically we should do exactly
1139 what we do when not producing relocatable output. Therefore, your
1140 patch is correct. In fact, it should probably always just set
1141 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1142 add the value into the object file. This won't hurt the COFF code,
1143 which doesn't use the addend; I'm not sure what it will do to other
1144 formats (the thing to check for would be whether any formats both use
1145 the addend and set partial_inplace).
1147 When I wanted to make coff-i386 produce relocatable output, I ran
1148 into the problem that you are running into: I wanted to remove that
1149 line. Rather than risk it, I made the coff-i386 relocs use a special
1150 function; it's coff_i386_reloc in coff-i386.c. The function
1151 specifically adds the addend field into the object file, knowing that
1152 bfd_install_relocation is not going to. If you remove that line, then
1153 coff-i386.c will wind up adding the addend field in twice. It's
1154 trivial to fix; it just needs to be done.
1156 The problem with removing the line is just that it may break some
1157 working code. With BFD it's hard to be sure of anything. The right
1158 way to deal with this is simply to build and test at least all the
1159 supported COFF targets. It should be straightforward if time and disk
1160 space consuming. For each target:
1162 2) generate some executable, and link it using -r (I would
1163 probably use paranoia.o and link against newlib/libc.a, which
1164 for all the supported targets would be available in
1165 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1166 3) make the change to reloc.c
1167 4) rebuild the linker
1169 6) if the resulting object files are the same, you have at least
1171 7) if they are different you have to figure out which version is
1173 relocation
-= reloc_entry
->addend
;
1174 /* FIXME: There should be no target specific code here... */
1175 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1176 reloc_entry
->addend
= 0;
1180 reloc_entry
->addend
= relocation
;
1184 /* FIXME: This overflow checking is incomplete, because the value
1185 might have overflowed before we get here. For a correct check we
1186 need to compute the value in a size larger than bitsize, but we
1187 can't reasonably do that for a reloc the same size as a host
1189 FIXME: We should also do overflow checking on the result after
1190 adding in the value contained in the object file. */
1191 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1192 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1195 bfd_arch_bits_per_address (abfd
),
1198 /* Either we are relocating all the way, or we don't want to apply
1199 the relocation to the reloc entry (probably because there isn't
1200 any room in the output format to describe addends to relocs). */
1202 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1203 (OSF version 1.3, compiler version 3.11). It miscompiles the
1217 x <<= (unsigned long) s.i0;
1219 printf ("failed\n");
1221 printf ("succeeded (%lx)\n", x);
1225 relocation
>>= (bfd_vma
) howto
->rightshift
;
1227 /* Shift everything up to where it's going to be used. */
1228 relocation
<<= (bfd_vma
) howto
->bitpos
;
1230 /* Wait for the day when all have the mask in them. */
1233 i instruction to be left alone
1234 o offset within instruction
1235 r relocation offset to apply
1244 (( i i i i i o o o o o from bfd_get<size>
1245 and S S S S S) to get the size offset we want
1246 + r r r r r r r r r r) to get the final value to place
1247 and D D D D D to chop to right size
1248 -----------------------
1251 ( i i i i i o o o o o from bfd_get<size>
1252 and N N N N N ) get instruction
1253 -----------------------
1259 -----------------------
1260 = R R R R R R R R R R put into bfd_put<size>
1264 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1266 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1268 switch (howto
->size
)
1272 char x
= bfd_get_8 (abfd
, data
);
1274 bfd_put_8 (abfd
, x
, data
);
1280 short x
= bfd_get_16 (abfd
, data
);
1282 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1287 long x
= bfd_get_32 (abfd
, data
);
1289 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1294 long x
= bfd_get_32 (abfd
, data
);
1295 relocation
= -relocation
;
1297 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1307 bfd_vma x
= bfd_get_64 (abfd
, data
);
1309 bfd_put_64 (abfd
, x
, data
);
1313 return bfd_reloc_other
;
1319 /* This relocation routine is used by some of the backend linkers.
1320 They do not construct asymbol or arelent structures, so there is no
1321 reason for them to use bfd_perform_relocation. Also,
1322 bfd_perform_relocation is so hacked up it is easier to write a new
1323 function than to try to deal with it.
1325 This routine does a final relocation. Whether it is useful for a
1326 relocatable link depends upon how the object format defines
1329 FIXME: This routine ignores any special_function in the HOWTO,
1330 since the existing special_function values have been written for
1331 bfd_perform_relocation.
1333 HOWTO is the reloc howto information.
1334 INPUT_BFD is the BFD which the reloc applies to.
1335 INPUT_SECTION is the section which the reloc applies to.
1336 CONTENTS is the contents of the section.
1337 ADDRESS is the address of the reloc within INPUT_SECTION.
1338 VALUE is the value of the symbol the reloc refers to.
1339 ADDEND is the addend of the reloc. */
1341 bfd_reloc_status_type
1342 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1344 asection
*input_section
,
1351 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1353 /* Sanity check the address. */
1354 if (octets
+ bfd_get_reloc_size (howto
)
1355 > bfd_get_section_limit_octets (input_bfd
, input_section
))
1356 return bfd_reloc_outofrange
;
1358 /* This function assumes that we are dealing with a basic relocation
1359 against a symbol. We want to compute the value of the symbol to
1360 relocate to. This is just VALUE, the value of the symbol, plus
1361 ADDEND, any addend associated with the reloc. */
1362 relocation
= value
+ addend
;
1364 /* If the relocation is PC relative, we want to set RELOCATION to
1365 the distance between the symbol (currently in RELOCATION) and the
1366 location we are relocating. Some targets (e.g., i386-aout)
1367 arrange for the contents of the section to be the negative of the
1368 offset of the location within the section; for such targets
1369 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1370 simply leave the contents of the section as zero; for such
1371 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1372 need to subtract out the offset of the location within the
1373 section (which is just ADDRESS). */
1374 if (howto
->pc_relative
)
1376 relocation
-= (input_section
->output_section
->vma
1377 + input_section
->output_offset
);
1378 if (howto
->pcrel_offset
)
1379 relocation
-= address
;
1382 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1384 + address
* bfd_octets_per_byte (input_bfd
));
1387 /* Relocate a given location using a given value and howto. */
1389 bfd_reloc_status_type
1390 _bfd_relocate_contents (reloc_howto_type
*howto
,
1397 bfd_reloc_status_type flag
;
1398 unsigned int rightshift
= howto
->rightshift
;
1399 unsigned int bitpos
= howto
->bitpos
;
1401 /* If the size is negative, negate RELOCATION. This isn't very
1403 if (howto
->size
< 0)
1404 relocation
= -relocation
;
1406 /* Get the value we are going to relocate. */
1407 size
= bfd_get_reloc_size (howto
);
1413 return bfd_reloc_ok
;
1415 x
= bfd_get_8 (input_bfd
, location
);
1418 x
= bfd_get_16 (input_bfd
, location
);
1421 x
= bfd_get_32 (input_bfd
, location
);
1425 x
= bfd_get_64 (input_bfd
, location
);
1432 /* Check for overflow. FIXME: We may drop bits during the addition
1433 which we don't check for. We must either check at every single
1434 operation, which would be tedious, or we must do the computations
1435 in a type larger than bfd_vma, which would be inefficient. */
1436 flag
= bfd_reloc_ok
;
1437 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1439 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1442 /* Get the values to be added together. For signed and unsigned
1443 relocations, we assume that all values should be truncated to
1444 the size of an address. For bitfields, all the bits matter.
1445 See also bfd_check_overflow. */
1446 fieldmask
= N_ONES (howto
->bitsize
);
1447 signmask
= ~fieldmask
;
1448 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1449 | (fieldmask
<< rightshift
));
1450 a
= (relocation
& addrmask
) >> rightshift
;
1451 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1452 addrmask
>>= rightshift
;
1454 switch (howto
->complain_on_overflow
)
1456 case complain_overflow_signed
:
1457 /* If any sign bits are set, all sign bits must be set.
1458 That is, A must be a valid negative address after
1460 signmask
= ~(fieldmask
>> 1);
1463 case complain_overflow_bitfield
:
1464 /* Much like the signed check, but for a field one bit
1465 wider. We allow a bitfield to represent numbers in the
1466 range -2**n to 2**n-1, where n is the number of bits in the
1467 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1468 can't overflow, which is exactly what we want. */
1470 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1471 flag
= bfd_reloc_overflow
;
1473 /* We only need this next bit of code if the sign bit of B
1474 is below the sign bit of A. This would only happen if
1475 SRC_MASK had fewer bits than BITSIZE. Note that if
1476 SRC_MASK has more bits than BITSIZE, we can get into
1477 trouble; we would need to verify that B is in range, as
1478 we do for A above. */
1479 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1482 /* Set all the bits above the sign bit. */
1485 /* Now we can do the addition. */
1488 /* See if the result has the correct sign. Bits above the
1489 sign bit are junk now; ignore them. If the sum is
1490 positive, make sure we did not have all negative inputs;
1491 if the sum is negative, make sure we did not have all
1492 positive inputs. The test below looks only at the sign
1493 bits, and it really just
1494 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1496 We mask with addrmask here to explicitly allow an address
1497 wrap-around. The Linux kernel relies on it, and it is
1498 the only way to write assembler code which can run when
1499 loaded at a location 0x80000000 away from the location at
1500 which it is linked. */
1501 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1502 flag
= bfd_reloc_overflow
;
1505 case complain_overflow_unsigned
:
1506 /* Checking for an unsigned overflow is relatively easy:
1507 trim the addresses and add, and trim the result as well.
1508 Overflow is normally indicated when the result does not
1509 fit in the field. However, we also need to consider the
1510 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1511 input is 0x80000000, and bfd_vma is only 32 bits; then we
1512 will get sum == 0, but there is an overflow, since the
1513 inputs did not fit in the field. Instead of doing a
1514 separate test, we can check for this by or-ing in the
1515 operands when testing for the sum overflowing its final
1517 sum
= (a
+ b
) & addrmask
;
1518 if ((a
| b
| sum
) & signmask
)
1519 flag
= bfd_reloc_overflow
;
1527 /* Put RELOCATION in the right bits. */
1528 relocation
>>= (bfd_vma
) rightshift
;
1529 relocation
<<= (bfd_vma
) bitpos
;
1531 /* Add RELOCATION to the right bits of X. */
1532 x
= ((x
& ~howto
->dst_mask
)
1533 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1535 /* Put the relocated value back in the object file. */
1541 bfd_put_8 (input_bfd
, x
, location
);
1544 bfd_put_16 (input_bfd
, x
, location
);
1547 bfd_put_32 (input_bfd
, x
, location
);
1551 bfd_put_64 (input_bfd
, x
, location
);
1561 /* Clear a given location using a given howto, by applying a fixed relocation
1562 value and discarding any in-place addend. This is used for fixed-up
1563 relocations against discarded symbols, to make ignorable debug or unwind
1564 information more obvious. */
1567 _bfd_clear_contents (reloc_howto_type
*howto
,
1569 asection
*input_section
,
1575 /* Get the value we are going to relocate. */
1576 size
= bfd_get_reloc_size (howto
);
1584 x
= bfd_get_8 (input_bfd
, location
);
1587 x
= bfd_get_16 (input_bfd
, location
);
1590 x
= bfd_get_32 (input_bfd
, location
);
1594 x
= bfd_get_64 (input_bfd
, location
);
1601 /* Zero out the unwanted bits of X. */
1602 x
&= ~howto
->dst_mask
;
1604 /* For a range list, use 1 instead of 0 as placeholder. 0
1605 would terminate the list, hiding any later entries. */
1606 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1607 ".debug_ranges") == 0
1608 && (howto
->dst_mask
& 1) != 0)
1611 /* Put the relocated value back in the object file. */
1618 bfd_put_8 (input_bfd
, x
, location
);
1621 bfd_put_16 (input_bfd
, x
, location
);
1624 bfd_put_32 (input_bfd
, x
, location
);
1628 bfd_put_64 (input_bfd
, x
, location
);
1639 howto manager, , typedef arelent, Relocations
1644 When an application wants to create a relocation, but doesn't
1645 know what the target machine might call it, it can find out by
1646 using this bit of code.
1655 The insides of a reloc code. The idea is that, eventually, there
1656 will be one enumerator for every type of relocation we ever do.
1657 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1658 return a howto pointer.
1660 This does mean that the application must determine the correct
1661 enumerator value; you can't get a howto pointer from a random set
1682 Basic absolute relocations of N bits.
1697 PC-relative relocations. Sometimes these are relative to the address
1698 of the relocation itself; sometimes they are relative to the start of
1699 the section containing the relocation. It depends on the specific target.
1701 The 24-bit relocation is used in some Intel 960 configurations.
1706 Section relative relocations. Some targets need this for DWARF2.
1709 BFD_RELOC_32_GOT_PCREL
1711 BFD_RELOC_16_GOT_PCREL
1713 BFD_RELOC_8_GOT_PCREL
1719 BFD_RELOC_LO16_GOTOFF
1721 BFD_RELOC_HI16_GOTOFF
1723 BFD_RELOC_HI16_S_GOTOFF
1727 BFD_RELOC_64_PLT_PCREL
1729 BFD_RELOC_32_PLT_PCREL
1731 BFD_RELOC_24_PLT_PCREL
1733 BFD_RELOC_16_PLT_PCREL
1735 BFD_RELOC_8_PLT_PCREL
1743 BFD_RELOC_LO16_PLTOFF
1745 BFD_RELOC_HI16_PLTOFF
1747 BFD_RELOC_HI16_S_PLTOFF
1761 BFD_RELOC_68K_GLOB_DAT
1763 BFD_RELOC_68K_JMP_SLOT
1765 BFD_RELOC_68K_RELATIVE
1767 BFD_RELOC_68K_TLS_GD32
1769 BFD_RELOC_68K_TLS_GD16
1771 BFD_RELOC_68K_TLS_GD8
1773 BFD_RELOC_68K_TLS_LDM32
1775 BFD_RELOC_68K_TLS_LDM16
1777 BFD_RELOC_68K_TLS_LDM8
1779 BFD_RELOC_68K_TLS_LDO32
1781 BFD_RELOC_68K_TLS_LDO16
1783 BFD_RELOC_68K_TLS_LDO8
1785 BFD_RELOC_68K_TLS_IE32
1787 BFD_RELOC_68K_TLS_IE16
1789 BFD_RELOC_68K_TLS_IE8
1791 BFD_RELOC_68K_TLS_LE32
1793 BFD_RELOC_68K_TLS_LE16
1795 BFD_RELOC_68K_TLS_LE8
1797 Relocations used by 68K ELF.
1800 BFD_RELOC_32_BASEREL
1802 BFD_RELOC_16_BASEREL
1804 BFD_RELOC_LO16_BASEREL
1806 BFD_RELOC_HI16_BASEREL
1808 BFD_RELOC_HI16_S_BASEREL
1814 Linkage-table relative.
1819 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1822 BFD_RELOC_32_PCREL_S2
1824 BFD_RELOC_16_PCREL_S2
1826 BFD_RELOC_23_PCREL_S2
1828 These PC-relative relocations are stored as word displacements --
1829 i.e., byte displacements shifted right two bits. The 30-bit word
1830 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1831 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1832 signed 16-bit displacement is used on the MIPS, and the 23-bit
1833 displacement is used on the Alpha.
1840 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1841 the target word. These are used on the SPARC.
1848 For systems that allocate a Global Pointer register, these are
1849 displacements off that register. These relocation types are
1850 handled specially, because the value the register will have is
1851 decided relatively late.
1854 BFD_RELOC_I960_CALLJ
1856 Reloc types used for i960/b.out.
1861 BFD_RELOC_SPARC_WDISP22
1867 BFD_RELOC_SPARC_GOT10
1869 BFD_RELOC_SPARC_GOT13
1871 BFD_RELOC_SPARC_GOT22
1873 BFD_RELOC_SPARC_PC10
1875 BFD_RELOC_SPARC_PC22
1877 BFD_RELOC_SPARC_WPLT30
1879 BFD_RELOC_SPARC_COPY
1881 BFD_RELOC_SPARC_GLOB_DAT
1883 BFD_RELOC_SPARC_JMP_SLOT
1885 BFD_RELOC_SPARC_RELATIVE
1887 BFD_RELOC_SPARC_UA16
1889 BFD_RELOC_SPARC_UA32
1891 BFD_RELOC_SPARC_UA64
1893 BFD_RELOC_SPARC_GOTDATA_HIX22
1895 BFD_RELOC_SPARC_GOTDATA_LOX10
1897 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1899 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1901 BFD_RELOC_SPARC_GOTDATA_OP
1903 BFD_RELOC_SPARC_JMP_IREL
1905 BFD_RELOC_SPARC_IRELATIVE
1907 SPARC ELF relocations. There is probably some overlap with other
1908 relocation types already defined.
1911 BFD_RELOC_SPARC_BASE13
1913 BFD_RELOC_SPARC_BASE22
1915 I think these are specific to SPARC a.out (e.g., Sun 4).
1925 BFD_RELOC_SPARC_OLO10
1927 BFD_RELOC_SPARC_HH22
1929 BFD_RELOC_SPARC_HM10
1931 BFD_RELOC_SPARC_LM22
1933 BFD_RELOC_SPARC_PC_HH22
1935 BFD_RELOC_SPARC_PC_HM10
1937 BFD_RELOC_SPARC_PC_LM22
1939 BFD_RELOC_SPARC_WDISP16
1941 BFD_RELOC_SPARC_WDISP19
1949 BFD_RELOC_SPARC_DISP64
1952 BFD_RELOC_SPARC_PLT32
1954 BFD_RELOC_SPARC_PLT64
1956 BFD_RELOC_SPARC_HIX22
1958 BFD_RELOC_SPARC_LOX10
1966 BFD_RELOC_SPARC_REGISTER
1970 BFD_RELOC_SPARC_SIZE32
1972 BFD_RELOC_SPARC_SIZE64
1974 BFD_RELOC_SPARC_WDISP10
1979 BFD_RELOC_SPARC_REV32
1981 SPARC little endian relocation
1983 BFD_RELOC_SPARC_TLS_GD_HI22
1985 BFD_RELOC_SPARC_TLS_GD_LO10
1987 BFD_RELOC_SPARC_TLS_GD_ADD
1989 BFD_RELOC_SPARC_TLS_GD_CALL
1991 BFD_RELOC_SPARC_TLS_LDM_HI22
1993 BFD_RELOC_SPARC_TLS_LDM_LO10
1995 BFD_RELOC_SPARC_TLS_LDM_ADD
1997 BFD_RELOC_SPARC_TLS_LDM_CALL
1999 BFD_RELOC_SPARC_TLS_LDO_HIX22
2001 BFD_RELOC_SPARC_TLS_LDO_LOX10
2003 BFD_RELOC_SPARC_TLS_LDO_ADD
2005 BFD_RELOC_SPARC_TLS_IE_HI22
2007 BFD_RELOC_SPARC_TLS_IE_LO10
2009 BFD_RELOC_SPARC_TLS_IE_LD
2011 BFD_RELOC_SPARC_TLS_IE_LDX
2013 BFD_RELOC_SPARC_TLS_IE_ADD
2015 BFD_RELOC_SPARC_TLS_LE_HIX22
2017 BFD_RELOC_SPARC_TLS_LE_LOX10
2019 BFD_RELOC_SPARC_TLS_DTPMOD32
2021 BFD_RELOC_SPARC_TLS_DTPMOD64
2023 BFD_RELOC_SPARC_TLS_DTPOFF32
2025 BFD_RELOC_SPARC_TLS_DTPOFF64
2027 BFD_RELOC_SPARC_TLS_TPOFF32
2029 BFD_RELOC_SPARC_TLS_TPOFF64
2031 SPARC TLS relocations
2040 BFD_RELOC_SPU_IMM10W
2044 BFD_RELOC_SPU_IMM16W
2048 BFD_RELOC_SPU_PCREL9a
2050 BFD_RELOC_SPU_PCREL9b
2052 BFD_RELOC_SPU_PCREL16
2062 BFD_RELOC_SPU_ADD_PIC
2067 BFD_RELOC_ALPHA_GPDISP_HI16
2069 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2070 "addend" in some special way.
2071 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2072 writing; when reading, it will be the absolute section symbol. The
2073 addend is the displacement in bytes of the "lda" instruction from
2074 the "ldah" instruction (which is at the address of this reloc).
2076 BFD_RELOC_ALPHA_GPDISP_LO16
2078 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2079 with GPDISP_HI16 relocs. The addend is ignored when writing the
2080 relocations out, and is filled in with the file's GP value on
2081 reading, for convenience.
2084 BFD_RELOC_ALPHA_GPDISP
2086 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2087 relocation except that there is no accompanying GPDISP_LO16
2091 BFD_RELOC_ALPHA_LITERAL
2093 BFD_RELOC_ALPHA_ELF_LITERAL
2095 BFD_RELOC_ALPHA_LITUSE
2097 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2098 the assembler turns it into a LDQ instruction to load the address of
2099 the symbol, and then fills in a register in the real instruction.
2101 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2102 section symbol. The addend is ignored when writing, but is filled
2103 in with the file's GP value on reading, for convenience, as with the
2106 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2107 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2108 but it generates output not based on the position within the .got
2109 section, but relative to the GP value chosen for the file during the
2112 The LITUSE reloc, on the instruction using the loaded address, gives
2113 information to the linker that it might be able to use to optimize
2114 away some literal section references. The symbol is ignored (read
2115 as the absolute section symbol), and the "addend" indicates the type
2116 of instruction using the register:
2117 1 - "memory" fmt insn
2118 2 - byte-manipulation (byte offset reg)
2119 3 - jsr (target of branch)
2122 BFD_RELOC_ALPHA_HINT
2124 The HINT relocation indicates a value that should be filled into the
2125 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2126 prediction logic which may be provided on some processors.
2129 BFD_RELOC_ALPHA_LINKAGE
2131 The LINKAGE relocation outputs a linkage pair in the object file,
2132 which is filled by the linker.
2135 BFD_RELOC_ALPHA_CODEADDR
2137 The CODEADDR relocation outputs a STO_CA in the object file,
2138 which is filled by the linker.
2141 BFD_RELOC_ALPHA_GPREL_HI16
2143 BFD_RELOC_ALPHA_GPREL_LO16
2145 The GPREL_HI/LO relocations together form a 32-bit offset from the
2149 BFD_RELOC_ALPHA_BRSGP
2151 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2152 share a common GP, and the target address is adjusted for
2153 STO_ALPHA_STD_GPLOAD.
2158 The NOP relocation outputs a NOP if the longword displacement
2159 between two procedure entry points is < 2^21.
2164 The BSR relocation outputs a BSR if the longword displacement
2165 between two procedure entry points is < 2^21.
2170 The LDA relocation outputs a LDA if the longword displacement
2171 between two procedure entry points is < 2^16.
2176 The BOH relocation outputs a BSR if the longword displacement
2177 between two procedure entry points is < 2^21, or else a hint.
2180 BFD_RELOC_ALPHA_TLSGD
2182 BFD_RELOC_ALPHA_TLSLDM
2184 BFD_RELOC_ALPHA_DTPMOD64
2186 BFD_RELOC_ALPHA_GOTDTPREL16
2188 BFD_RELOC_ALPHA_DTPREL64
2190 BFD_RELOC_ALPHA_DTPREL_HI16
2192 BFD_RELOC_ALPHA_DTPREL_LO16
2194 BFD_RELOC_ALPHA_DTPREL16
2196 BFD_RELOC_ALPHA_GOTTPREL16
2198 BFD_RELOC_ALPHA_TPREL64
2200 BFD_RELOC_ALPHA_TPREL_HI16
2202 BFD_RELOC_ALPHA_TPREL_LO16
2204 BFD_RELOC_ALPHA_TPREL16
2206 Alpha thread-local storage relocations.
2211 BFD_RELOC_MICROMIPS_JMP
2213 The MIPS jump instruction.
2216 BFD_RELOC_MIPS16_JMP
2218 The MIPS16 jump instruction.
2221 BFD_RELOC_MIPS16_GPREL
2223 MIPS16 GP relative reloc.
2228 High 16 bits of 32-bit value; simple reloc.
2233 High 16 bits of 32-bit value but the low 16 bits will be sign
2234 extended and added to form the final result. If the low 16
2235 bits form a negative number, we need to add one to the high value
2236 to compensate for the borrow when the low bits are added.
2244 BFD_RELOC_HI16_PCREL
2246 High 16 bits of 32-bit pc-relative value
2248 BFD_RELOC_HI16_S_PCREL
2250 High 16 bits of 32-bit pc-relative value, adjusted
2252 BFD_RELOC_LO16_PCREL
2254 Low 16 bits of pc-relative value
2257 BFD_RELOC_MIPS16_GOT16
2259 BFD_RELOC_MIPS16_CALL16
2261 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2262 16-bit immediate fields
2264 BFD_RELOC_MIPS16_HI16
2266 MIPS16 high 16 bits of 32-bit value.
2268 BFD_RELOC_MIPS16_HI16_S
2270 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2271 extended and added to form the final result. If the low 16
2272 bits form a negative number, we need to add one to the high value
2273 to compensate for the borrow when the low bits are added.
2275 BFD_RELOC_MIPS16_LO16
2280 BFD_RELOC_MIPS16_TLS_GD
2282 BFD_RELOC_MIPS16_TLS_LDM
2284 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2286 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2288 BFD_RELOC_MIPS16_TLS_GOTTPREL
2290 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2292 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2294 MIPS16 TLS relocations
2297 BFD_RELOC_MIPS_LITERAL
2299 BFD_RELOC_MICROMIPS_LITERAL
2301 Relocation against a MIPS literal section.
2304 BFD_RELOC_MICROMIPS_7_PCREL_S1
2306 BFD_RELOC_MICROMIPS_10_PCREL_S1
2308 BFD_RELOC_MICROMIPS_16_PCREL_S1
2310 microMIPS PC-relative relocations.
2313 BFD_RELOC_MIPS16_16_PCREL_S1
2315 MIPS16 PC-relative relocation.
2318 BFD_RELOC_MIPS_21_PCREL_S2
2320 BFD_RELOC_MIPS_26_PCREL_S2
2322 BFD_RELOC_MIPS_18_PCREL_S3
2324 BFD_RELOC_MIPS_19_PCREL_S2
2326 MIPS PC-relative relocations.
2329 BFD_RELOC_MICROMIPS_GPREL16
2331 BFD_RELOC_MICROMIPS_HI16
2333 BFD_RELOC_MICROMIPS_HI16_S
2335 BFD_RELOC_MICROMIPS_LO16
2337 microMIPS versions of generic BFD relocs.
2340 BFD_RELOC_MIPS_GOT16
2342 BFD_RELOC_MICROMIPS_GOT16
2344 BFD_RELOC_MIPS_CALL16
2346 BFD_RELOC_MICROMIPS_CALL16
2348 BFD_RELOC_MIPS_GOT_HI16
2350 BFD_RELOC_MICROMIPS_GOT_HI16
2352 BFD_RELOC_MIPS_GOT_LO16
2354 BFD_RELOC_MICROMIPS_GOT_LO16
2356 BFD_RELOC_MIPS_CALL_HI16
2358 BFD_RELOC_MICROMIPS_CALL_HI16
2360 BFD_RELOC_MIPS_CALL_LO16
2362 BFD_RELOC_MICROMIPS_CALL_LO16
2366 BFD_RELOC_MICROMIPS_SUB
2368 BFD_RELOC_MIPS_GOT_PAGE
2370 BFD_RELOC_MICROMIPS_GOT_PAGE
2372 BFD_RELOC_MIPS_GOT_OFST
2374 BFD_RELOC_MICROMIPS_GOT_OFST
2376 BFD_RELOC_MIPS_GOT_DISP
2378 BFD_RELOC_MICROMIPS_GOT_DISP
2380 BFD_RELOC_MIPS_SHIFT5
2382 BFD_RELOC_MIPS_SHIFT6
2384 BFD_RELOC_MIPS_INSERT_A
2386 BFD_RELOC_MIPS_INSERT_B
2388 BFD_RELOC_MIPS_DELETE
2390 BFD_RELOC_MIPS_HIGHEST
2392 BFD_RELOC_MICROMIPS_HIGHEST
2394 BFD_RELOC_MIPS_HIGHER
2396 BFD_RELOC_MICROMIPS_HIGHER
2398 BFD_RELOC_MIPS_SCN_DISP
2400 BFD_RELOC_MICROMIPS_SCN_DISP
2402 BFD_RELOC_MIPS_REL16
2404 BFD_RELOC_MIPS_RELGOT
2408 BFD_RELOC_MICROMIPS_JALR
2410 BFD_RELOC_MIPS_TLS_DTPMOD32
2412 BFD_RELOC_MIPS_TLS_DTPREL32
2414 BFD_RELOC_MIPS_TLS_DTPMOD64
2416 BFD_RELOC_MIPS_TLS_DTPREL64
2418 BFD_RELOC_MIPS_TLS_GD
2420 BFD_RELOC_MICROMIPS_TLS_GD
2422 BFD_RELOC_MIPS_TLS_LDM
2424 BFD_RELOC_MICROMIPS_TLS_LDM
2426 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2428 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2430 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2432 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2434 BFD_RELOC_MIPS_TLS_GOTTPREL
2436 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2438 BFD_RELOC_MIPS_TLS_TPREL32
2440 BFD_RELOC_MIPS_TLS_TPREL64
2442 BFD_RELOC_MIPS_TLS_TPREL_HI16
2444 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2446 BFD_RELOC_MIPS_TLS_TPREL_LO16
2448 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2452 MIPS ELF relocations.
2458 BFD_RELOC_MIPS_JUMP_SLOT
2460 MIPS ELF relocations (VxWorks and PLT extensions).
2464 BFD_RELOC_MOXIE_10_PCREL
2466 Moxie ELF relocations.
2478 FT32 ELF relocations.
2482 BFD_RELOC_FRV_LABEL16
2484 BFD_RELOC_FRV_LABEL24
2490 BFD_RELOC_FRV_GPREL12
2492 BFD_RELOC_FRV_GPRELU12
2494 BFD_RELOC_FRV_GPREL32
2496 BFD_RELOC_FRV_GPRELHI
2498 BFD_RELOC_FRV_GPRELLO
2506 BFD_RELOC_FRV_FUNCDESC
2508 BFD_RELOC_FRV_FUNCDESC_GOT12
2510 BFD_RELOC_FRV_FUNCDESC_GOTHI
2512 BFD_RELOC_FRV_FUNCDESC_GOTLO
2514 BFD_RELOC_FRV_FUNCDESC_VALUE
2516 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2518 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2520 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2522 BFD_RELOC_FRV_GOTOFF12
2524 BFD_RELOC_FRV_GOTOFFHI
2526 BFD_RELOC_FRV_GOTOFFLO
2528 BFD_RELOC_FRV_GETTLSOFF
2530 BFD_RELOC_FRV_TLSDESC_VALUE
2532 BFD_RELOC_FRV_GOTTLSDESC12
2534 BFD_RELOC_FRV_GOTTLSDESCHI
2536 BFD_RELOC_FRV_GOTTLSDESCLO
2538 BFD_RELOC_FRV_TLSMOFF12
2540 BFD_RELOC_FRV_TLSMOFFHI
2542 BFD_RELOC_FRV_TLSMOFFLO
2544 BFD_RELOC_FRV_GOTTLSOFF12
2546 BFD_RELOC_FRV_GOTTLSOFFHI
2548 BFD_RELOC_FRV_GOTTLSOFFLO
2550 BFD_RELOC_FRV_TLSOFF
2552 BFD_RELOC_FRV_TLSDESC_RELAX
2554 BFD_RELOC_FRV_GETTLSOFF_RELAX
2556 BFD_RELOC_FRV_TLSOFF_RELAX
2558 BFD_RELOC_FRV_TLSMOFF
2560 Fujitsu Frv Relocations.
2564 BFD_RELOC_MN10300_GOTOFF24
2566 This is a 24bit GOT-relative reloc for the mn10300.
2568 BFD_RELOC_MN10300_GOT32
2570 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2573 BFD_RELOC_MN10300_GOT24
2575 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2578 BFD_RELOC_MN10300_GOT16
2580 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2583 BFD_RELOC_MN10300_COPY
2585 Copy symbol at runtime.
2587 BFD_RELOC_MN10300_GLOB_DAT
2591 BFD_RELOC_MN10300_JMP_SLOT
2595 BFD_RELOC_MN10300_RELATIVE
2597 Adjust by program base.
2599 BFD_RELOC_MN10300_SYM_DIFF
2601 Together with another reloc targeted at the same location,
2602 allows for a value that is the difference of two symbols
2603 in the same section.
2605 BFD_RELOC_MN10300_ALIGN
2607 The addend of this reloc is an alignment power that must
2608 be honoured at the offset's location, regardless of linker
2611 BFD_RELOC_MN10300_TLS_GD
2613 BFD_RELOC_MN10300_TLS_LD
2615 BFD_RELOC_MN10300_TLS_LDO
2617 BFD_RELOC_MN10300_TLS_GOTIE
2619 BFD_RELOC_MN10300_TLS_IE
2621 BFD_RELOC_MN10300_TLS_LE
2623 BFD_RELOC_MN10300_TLS_DTPMOD
2625 BFD_RELOC_MN10300_TLS_DTPOFF
2627 BFD_RELOC_MN10300_TLS_TPOFF
2629 Various TLS-related relocations.
2631 BFD_RELOC_MN10300_32_PCREL
2633 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2636 BFD_RELOC_MN10300_16_PCREL
2638 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2649 BFD_RELOC_386_GLOB_DAT
2651 BFD_RELOC_386_JUMP_SLOT
2653 BFD_RELOC_386_RELATIVE
2655 BFD_RELOC_386_GOTOFF
2659 BFD_RELOC_386_TLS_TPOFF
2661 BFD_RELOC_386_TLS_IE
2663 BFD_RELOC_386_TLS_GOTIE
2665 BFD_RELOC_386_TLS_LE
2667 BFD_RELOC_386_TLS_GD
2669 BFD_RELOC_386_TLS_LDM
2671 BFD_RELOC_386_TLS_LDO_32
2673 BFD_RELOC_386_TLS_IE_32
2675 BFD_RELOC_386_TLS_LE_32
2677 BFD_RELOC_386_TLS_DTPMOD32
2679 BFD_RELOC_386_TLS_DTPOFF32
2681 BFD_RELOC_386_TLS_TPOFF32
2683 BFD_RELOC_386_TLS_GOTDESC
2685 BFD_RELOC_386_TLS_DESC_CALL
2687 BFD_RELOC_386_TLS_DESC
2689 BFD_RELOC_386_IRELATIVE
2691 BFD_RELOC_386_GOT32X
2693 i386/elf relocations
2696 BFD_RELOC_X86_64_GOT32
2698 BFD_RELOC_X86_64_PLT32
2700 BFD_RELOC_X86_64_COPY
2702 BFD_RELOC_X86_64_GLOB_DAT
2704 BFD_RELOC_X86_64_JUMP_SLOT
2706 BFD_RELOC_X86_64_RELATIVE
2708 BFD_RELOC_X86_64_GOTPCREL
2710 BFD_RELOC_X86_64_32S
2712 BFD_RELOC_X86_64_DTPMOD64
2714 BFD_RELOC_X86_64_DTPOFF64
2716 BFD_RELOC_X86_64_TPOFF64
2718 BFD_RELOC_X86_64_TLSGD
2720 BFD_RELOC_X86_64_TLSLD
2722 BFD_RELOC_X86_64_DTPOFF32
2724 BFD_RELOC_X86_64_GOTTPOFF
2726 BFD_RELOC_X86_64_TPOFF32
2728 BFD_RELOC_X86_64_GOTOFF64
2730 BFD_RELOC_X86_64_GOTPC32
2732 BFD_RELOC_X86_64_GOT64
2734 BFD_RELOC_X86_64_GOTPCREL64
2736 BFD_RELOC_X86_64_GOTPC64
2738 BFD_RELOC_X86_64_GOTPLT64
2740 BFD_RELOC_X86_64_PLTOFF64
2742 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2744 BFD_RELOC_X86_64_TLSDESC_CALL
2746 BFD_RELOC_X86_64_TLSDESC
2748 BFD_RELOC_X86_64_IRELATIVE
2750 BFD_RELOC_X86_64_PC32_BND
2752 BFD_RELOC_X86_64_PLT32_BND
2754 BFD_RELOC_X86_64_GOTPCRELX
2756 BFD_RELOC_X86_64_REX_GOTPCRELX
2758 x86-64/elf relocations
2761 BFD_RELOC_NS32K_IMM_8
2763 BFD_RELOC_NS32K_IMM_16
2765 BFD_RELOC_NS32K_IMM_32
2767 BFD_RELOC_NS32K_IMM_8_PCREL
2769 BFD_RELOC_NS32K_IMM_16_PCREL
2771 BFD_RELOC_NS32K_IMM_32_PCREL
2773 BFD_RELOC_NS32K_DISP_8
2775 BFD_RELOC_NS32K_DISP_16
2777 BFD_RELOC_NS32K_DISP_32
2779 BFD_RELOC_NS32K_DISP_8_PCREL
2781 BFD_RELOC_NS32K_DISP_16_PCREL
2783 BFD_RELOC_NS32K_DISP_32_PCREL
2788 BFD_RELOC_PDP11_DISP_8_PCREL
2790 BFD_RELOC_PDP11_DISP_6_PCREL
2795 BFD_RELOC_PJ_CODE_HI16
2797 BFD_RELOC_PJ_CODE_LO16
2799 BFD_RELOC_PJ_CODE_DIR16
2801 BFD_RELOC_PJ_CODE_DIR32
2803 BFD_RELOC_PJ_CODE_REL16
2805 BFD_RELOC_PJ_CODE_REL32
2807 Picojava relocs. Not all of these appear in object files.
2818 BFD_RELOC_PPC_B16_BRTAKEN
2820 BFD_RELOC_PPC_B16_BRNTAKEN
2824 BFD_RELOC_PPC_BA16_BRTAKEN
2826 BFD_RELOC_PPC_BA16_BRNTAKEN
2830 BFD_RELOC_PPC_GLOB_DAT
2832 BFD_RELOC_PPC_JMP_SLOT
2834 BFD_RELOC_PPC_RELATIVE
2836 BFD_RELOC_PPC_LOCAL24PC
2838 BFD_RELOC_PPC_EMB_NADDR32
2840 BFD_RELOC_PPC_EMB_NADDR16
2842 BFD_RELOC_PPC_EMB_NADDR16_LO
2844 BFD_RELOC_PPC_EMB_NADDR16_HI
2846 BFD_RELOC_PPC_EMB_NADDR16_HA
2848 BFD_RELOC_PPC_EMB_SDAI16
2850 BFD_RELOC_PPC_EMB_SDA2I16
2852 BFD_RELOC_PPC_EMB_SDA2REL
2854 BFD_RELOC_PPC_EMB_SDA21
2856 BFD_RELOC_PPC_EMB_MRKREF
2858 BFD_RELOC_PPC_EMB_RELSEC16
2860 BFD_RELOC_PPC_EMB_RELST_LO
2862 BFD_RELOC_PPC_EMB_RELST_HI
2864 BFD_RELOC_PPC_EMB_RELST_HA
2866 BFD_RELOC_PPC_EMB_BIT_FLD
2868 BFD_RELOC_PPC_EMB_RELSDA
2870 BFD_RELOC_PPC_VLE_REL8
2872 BFD_RELOC_PPC_VLE_REL15
2874 BFD_RELOC_PPC_VLE_REL24
2876 BFD_RELOC_PPC_VLE_LO16A
2878 BFD_RELOC_PPC_VLE_LO16D
2880 BFD_RELOC_PPC_VLE_HI16A
2882 BFD_RELOC_PPC_VLE_HI16D
2884 BFD_RELOC_PPC_VLE_HA16A
2886 BFD_RELOC_PPC_VLE_HA16D
2888 BFD_RELOC_PPC_VLE_SDA21
2890 BFD_RELOC_PPC_VLE_SDA21_LO
2892 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2894 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2896 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2898 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2900 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2902 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2904 BFD_RELOC_PPC_REL16DX_HA
2906 BFD_RELOC_PPC64_HIGHER
2908 BFD_RELOC_PPC64_HIGHER_S
2910 BFD_RELOC_PPC64_HIGHEST
2912 BFD_RELOC_PPC64_HIGHEST_S
2914 BFD_RELOC_PPC64_TOC16_LO
2916 BFD_RELOC_PPC64_TOC16_HI
2918 BFD_RELOC_PPC64_TOC16_HA
2922 BFD_RELOC_PPC64_PLTGOT16
2924 BFD_RELOC_PPC64_PLTGOT16_LO
2926 BFD_RELOC_PPC64_PLTGOT16_HI
2928 BFD_RELOC_PPC64_PLTGOT16_HA
2930 BFD_RELOC_PPC64_ADDR16_DS
2932 BFD_RELOC_PPC64_ADDR16_LO_DS
2934 BFD_RELOC_PPC64_GOT16_DS
2936 BFD_RELOC_PPC64_GOT16_LO_DS
2938 BFD_RELOC_PPC64_PLT16_LO_DS
2940 BFD_RELOC_PPC64_SECTOFF_DS
2942 BFD_RELOC_PPC64_SECTOFF_LO_DS
2944 BFD_RELOC_PPC64_TOC16_DS
2946 BFD_RELOC_PPC64_TOC16_LO_DS
2948 BFD_RELOC_PPC64_PLTGOT16_DS
2950 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2952 BFD_RELOC_PPC64_ADDR16_HIGH
2954 BFD_RELOC_PPC64_ADDR16_HIGHA
2956 BFD_RELOC_PPC64_ADDR64_LOCAL
2958 BFD_RELOC_PPC64_ENTRY
2960 Power(rs6000) and PowerPC relocations.
2969 BFD_RELOC_PPC_DTPMOD
2971 BFD_RELOC_PPC_TPREL16
2973 BFD_RELOC_PPC_TPREL16_LO
2975 BFD_RELOC_PPC_TPREL16_HI
2977 BFD_RELOC_PPC_TPREL16_HA
2981 BFD_RELOC_PPC_DTPREL16
2983 BFD_RELOC_PPC_DTPREL16_LO
2985 BFD_RELOC_PPC_DTPREL16_HI
2987 BFD_RELOC_PPC_DTPREL16_HA
2989 BFD_RELOC_PPC_DTPREL
2991 BFD_RELOC_PPC_GOT_TLSGD16
2993 BFD_RELOC_PPC_GOT_TLSGD16_LO
2995 BFD_RELOC_PPC_GOT_TLSGD16_HI
2997 BFD_RELOC_PPC_GOT_TLSGD16_HA
2999 BFD_RELOC_PPC_GOT_TLSLD16
3001 BFD_RELOC_PPC_GOT_TLSLD16_LO
3003 BFD_RELOC_PPC_GOT_TLSLD16_HI
3005 BFD_RELOC_PPC_GOT_TLSLD16_HA
3007 BFD_RELOC_PPC_GOT_TPREL16
3009 BFD_RELOC_PPC_GOT_TPREL16_LO
3011 BFD_RELOC_PPC_GOT_TPREL16_HI
3013 BFD_RELOC_PPC_GOT_TPREL16_HA
3015 BFD_RELOC_PPC_GOT_DTPREL16
3017 BFD_RELOC_PPC_GOT_DTPREL16_LO
3019 BFD_RELOC_PPC_GOT_DTPREL16_HI
3021 BFD_RELOC_PPC_GOT_DTPREL16_HA
3023 BFD_RELOC_PPC64_TPREL16_DS
3025 BFD_RELOC_PPC64_TPREL16_LO_DS
3027 BFD_RELOC_PPC64_TPREL16_HIGHER
3029 BFD_RELOC_PPC64_TPREL16_HIGHERA
3031 BFD_RELOC_PPC64_TPREL16_HIGHEST
3033 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3035 BFD_RELOC_PPC64_DTPREL16_DS
3037 BFD_RELOC_PPC64_DTPREL16_LO_DS
3039 BFD_RELOC_PPC64_DTPREL16_HIGHER
3041 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3043 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3045 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3047 BFD_RELOC_PPC64_TPREL16_HIGH
3049 BFD_RELOC_PPC64_TPREL16_HIGHA
3051 BFD_RELOC_PPC64_DTPREL16_HIGH
3053 BFD_RELOC_PPC64_DTPREL16_HIGHA
3055 PowerPC and PowerPC64 thread-local storage relocations.
3060 IBM 370/390 relocations
3065 The type of reloc used to build a constructor table - at the moment
3066 probably a 32 bit wide absolute relocation, but the target can choose.
3067 It generally does map to one of the other relocation types.
3070 BFD_RELOC_ARM_PCREL_BRANCH
3072 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3073 not stored in the instruction.
3075 BFD_RELOC_ARM_PCREL_BLX
3077 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3078 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3079 field in the instruction.
3081 BFD_RELOC_THUMB_PCREL_BLX
3083 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3084 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3085 field in the instruction.
3087 BFD_RELOC_ARM_PCREL_CALL
3089 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3091 BFD_RELOC_ARM_PCREL_JUMP
3093 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3096 BFD_RELOC_THUMB_PCREL_BRANCH7
3098 BFD_RELOC_THUMB_PCREL_BRANCH9
3100 BFD_RELOC_THUMB_PCREL_BRANCH12
3102 BFD_RELOC_THUMB_PCREL_BRANCH20
3104 BFD_RELOC_THUMB_PCREL_BRANCH23
3106 BFD_RELOC_THUMB_PCREL_BRANCH25
3108 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3109 The lowest bit must be zero and is not stored in the instruction.
3110 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3111 "nn" one smaller in all cases. Note further that BRANCH23
3112 corresponds to R_ARM_THM_CALL.
3115 BFD_RELOC_ARM_OFFSET_IMM
3117 12-bit immediate offset, used in ARM-format ldr and str instructions.
3120 BFD_RELOC_ARM_THUMB_OFFSET
3122 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3125 BFD_RELOC_ARM_TARGET1
3127 Pc-relative or absolute relocation depending on target. Used for
3128 entries in .init_array sections.
3130 BFD_RELOC_ARM_ROSEGREL32
3132 Read-only segment base relative address.
3134 BFD_RELOC_ARM_SBREL32
3136 Data segment base relative address.
3138 BFD_RELOC_ARM_TARGET2
3140 This reloc is used for references to RTTI data from exception handling
3141 tables. The actual definition depends on the target. It may be a
3142 pc-relative or some form of GOT-indirect relocation.
3144 BFD_RELOC_ARM_PREL31
3146 31-bit PC relative address.
3152 BFD_RELOC_ARM_MOVW_PCREL
3154 BFD_RELOC_ARM_MOVT_PCREL
3156 BFD_RELOC_ARM_THUMB_MOVW
3158 BFD_RELOC_ARM_THUMB_MOVT
3160 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3162 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3164 Low and High halfword relocations for MOVW and MOVT instructions.
3167 BFD_RELOC_ARM_JUMP_SLOT
3169 BFD_RELOC_ARM_GLOB_DAT
3175 BFD_RELOC_ARM_RELATIVE
3177 BFD_RELOC_ARM_GOTOFF
3181 BFD_RELOC_ARM_GOT_PREL
3183 Relocations for setting up GOTs and PLTs for shared libraries.
3186 BFD_RELOC_ARM_TLS_GD32
3188 BFD_RELOC_ARM_TLS_LDO32
3190 BFD_RELOC_ARM_TLS_LDM32
3192 BFD_RELOC_ARM_TLS_DTPOFF32
3194 BFD_RELOC_ARM_TLS_DTPMOD32
3196 BFD_RELOC_ARM_TLS_TPOFF32
3198 BFD_RELOC_ARM_TLS_IE32
3200 BFD_RELOC_ARM_TLS_LE32
3202 BFD_RELOC_ARM_TLS_GOTDESC
3204 BFD_RELOC_ARM_TLS_CALL
3206 BFD_RELOC_ARM_THM_TLS_CALL
3208 BFD_RELOC_ARM_TLS_DESCSEQ
3210 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3212 BFD_RELOC_ARM_TLS_DESC
3214 ARM thread-local storage relocations.
3217 BFD_RELOC_ARM_ALU_PC_G0_NC
3219 BFD_RELOC_ARM_ALU_PC_G0
3221 BFD_RELOC_ARM_ALU_PC_G1_NC
3223 BFD_RELOC_ARM_ALU_PC_G1
3225 BFD_RELOC_ARM_ALU_PC_G2
3227 BFD_RELOC_ARM_LDR_PC_G0
3229 BFD_RELOC_ARM_LDR_PC_G1
3231 BFD_RELOC_ARM_LDR_PC_G2
3233 BFD_RELOC_ARM_LDRS_PC_G0
3235 BFD_RELOC_ARM_LDRS_PC_G1
3237 BFD_RELOC_ARM_LDRS_PC_G2
3239 BFD_RELOC_ARM_LDC_PC_G0
3241 BFD_RELOC_ARM_LDC_PC_G1
3243 BFD_RELOC_ARM_LDC_PC_G2
3245 BFD_RELOC_ARM_ALU_SB_G0_NC
3247 BFD_RELOC_ARM_ALU_SB_G0
3249 BFD_RELOC_ARM_ALU_SB_G1_NC
3251 BFD_RELOC_ARM_ALU_SB_G1
3253 BFD_RELOC_ARM_ALU_SB_G2
3255 BFD_RELOC_ARM_LDR_SB_G0
3257 BFD_RELOC_ARM_LDR_SB_G1
3259 BFD_RELOC_ARM_LDR_SB_G2
3261 BFD_RELOC_ARM_LDRS_SB_G0
3263 BFD_RELOC_ARM_LDRS_SB_G1
3265 BFD_RELOC_ARM_LDRS_SB_G2
3267 BFD_RELOC_ARM_LDC_SB_G0
3269 BFD_RELOC_ARM_LDC_SB_G1
3271 BFD_RELOC_ARM_LDC_SB_G2
3273 ARM group relocations.
3278 Annotation of BX instructions.
3281 BFD_RELOC_ARM_IRELATIVE
3283 ARM support for STT_GNU_IFUNC.
3286 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3288 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3290 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3292 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3294 Thumb1 relocations to support execute-only code.
3297 BFD_RELOC_ARM_IMMEDIATE
3299 BFD_RELOC_ARM_ADRL_IMMEDIATE
3301 BFD_RELOC_ARM_T32_IMMEDIATE
3303 BFD_RELOC_ARM_T32_ADD_IMM
3305 BFD_RELOC_ARM_T32_IMM12
3307 BFD_RELOC_ARM_T32_ADD_PC12
3309 BFD_RELOC_ARM_SHIFT_IMM
3319 BFD_RELOC_ARM_CP_OFF_IMM
3321 BFD_RELOC_ARM_CP_OFF_IMM_S2
3323 BFD_RELOC_ARM_T32_CP_OFF_IMM
3325 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3327 BFD_RELOC_ARM_ADR_IMM
3329 BFD_RELOC_ARM_LDR_IMM
3331 BFD_RELOC_ARM_LITERAL
3333 BFD_RELOC_ARM_IN_POOL
3335 BFD_RELOC_ARM_OFFSET_IMM8
3337 BFD_RELOC_ARM_T32_OFFSET_U8
3339 BFD_RELOC_ARM_T32_OFFSET_IMM
3341 BFD_RELOC_ARM_HWLITERAL
3343 BFD_RELOC_ARM_THUMB_ADD
3345 BFD_RELOC_ARM_THUMB_IMM
3347 BFD_RELOC_ARM_THUMB_SHIFT
3349 These relocs are only used within the ARM assembler. They are not
3350 (at present) written to any object files.
3353 BFD_RELOC_SH_PCDISP8BY2
3355 BFD_RELOC_SH_PCDISP12BY2
3363 BFD_RELOC_SH_DISP12BY2
3365 BFD_RELOC_SH_DISP12BY4
3367 BFD_RELOC_SH_DISP12BY8
3371 BFD_RELOC_SH_DISP20BY8
3375 BFD_RELOC_SH_IMM4BY2
3377 BFD_RELOC_SH_IMM4BY4
3381 BFD_RELOC_SH_IMM8BY2
3383 BFD_RELOC_SH_IMM8BY4
3385 BFD_RELOC_SH_PCRELIMM8BY2
3387 BFD_RELOC_SH_PCRELIMM8BY4
3389 BFD_RELOC_SH_SWITCH16
3391 BFD_RELOC_SH_SWITCH32
3405 BFD_RELOC_SH_LOOP_START
3407 BFD_RELOC_SH_LOOP_END
3411 BFD_RELOC_SH_GLOB_DAT
3413 BFD_RELOC_SH_JMP_SLOT
3415 BFD_RELOC_SH_RELATIVE
3419 BFD_RELOC_SH_GOT_LOW16
3421 BFD_RELOC_SH_GOT_MEDLOW16
3423 BFD_RELOC_SH_GOT_MEDHI16
3425 BFD_RELOC_SH_GOT_HI16
3427 BFD_RELOC_SH_GOTPLT_LOW16
3429 BFD_RELOC_SH_GOTPLT_MEDLOW16
3431 BFD_RELOC_SH_GOTPLT_MEDHI16
3433 BFD_RELOC_SH_GOTPLT_HI16
3435 BFD_RELOC_SH_PLT_LOW16
3437 BFD_RELOC_SH_PLT_MEDLOW16
3439 BFD_RELOC_SH_PLT_MEDHI16
3441 BFD_RELOC_SH_PLT_HI16
3443 BFD_RELOC_SH_GOTOFF_LOW16
3445 BFD_RELOC_SH_GOTOFF_MEDLOW16
3447 BFD_RELOC_SH_GOTOFF_MEDHI16
3449 BFD_RELOC_SH_GOTOFF_HI16
3451 BFD_RELOC_SH_GOTPC_LOW16
3453 BFD_RELOC_SH_GOTPC_MEDLOW16
3455 BFD_RELOC_SH_GOTPC_MEDHI16
3457 BFD_RELOC_SH_GOTPC_HI16
3461 BFD_RELOC_SH_GLOB_DAT64
3463 BFD_RELOC_SH_JMP_SLOT64
3465 BFD_RELOC_SH_RELATIVE64
3467 BFD_RELOC_SH_GOT10BY4
3469 BFD_RELOC_SH_GOT10BY8
3471 BFD_RELOC_SH_GOTPLT10BY4
3473 BFD_RELOC_SH_GOTPLT10BY8
3475 BFD_RELOC_SH_GOTPLT32
3477 BFD_RELOC_SH_SHMEDIA_CODE
3483 BFD_RELOC_SH_IMMS6BY32
3489 BFD_RELOC_SH_IMMS10BY2
3491 BFD_RELOC_SH_IMMS10BY4
3493 BFD_RELOC_SH_IMMS10BY8
3499 BFD_RELOC_SH_IMM_LOW16
3501 BFD_RELOC_SH_IMM_LOW16_PCREL
3503 BFD_RELOC_SH_IMM_MEDLOW16
3505 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3507 BFD_RELOC_SH_IMM_MEDHI16
3509 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3511 BFD_RELOC_SH_IMM_HI16
3513 BFD_RELOC_SH_IMM_HI16_PCREL
3517 BFD_RELOC_SH_TLS_GD_32
3519 BFD_RELOC_SH_TLS_LD_32
3521 BFD_RELOC_SH_TLS_LDO_32
3523 BFD_RELOC_SH_TLS_IE_32
3525 BFD_RELOC_SH_TLS_LE_32
3527 BFD_RELOC_SH_TLS_DTPMOD32
3529 BFD_RELOC_SH_TLS_DTPOFF32
3531 BFD_RELOC_SH_TLS_TPOFF32
3535 BFD_RELOC_SH_GOTOFF20
3537 BFD_RELOC_SH_GOTFUNCDESC
3539 BFD_RELOC_SH_GOTFUNCDESC20
3541 BFD_RELOC_SH_GOTOFFFUNCDESC
3543 BFD_RELOC_SH_GOTOFFFUNCDESC20
3545 BFD_RELOC_SH_FUNCDESC
3547 Renesas / SuperH SH relocs. Not all of these appear in object files.
3570 BFD_RELOC_ARC_SECTOFF
3572 BFD_RELOC_ARC_S21H_PCREL
3574 BFD_RELOC_ARC_S21W_PCREL
3576 BFD_RELOC_ARC_S25H_PCREL
3578 BFD_RELOC_ARC_S25W_PCREL
3582 BFD_RELOC_ARC_SDA_LDST
3584 BFD_RELOC_ARC_SDA_LDST1
3586 BFD_RELOC_ARC_SDA_LDST2
3588 BFD_RELOC_ARC_SDA16_LD
3590 BFD_RELOC_ARC_SDA16_LD1
3592 BFD_RELOC_ARC_SDA16_LD2
3594 BFD_RELOC_ARC_S13_PCREL
3600 BFD_RELOC_ARC_32_ME_S
3602 BFD_RELOC_ARC_N32_ME
3604 BFD_RELOC_ARC_SECTOFF_ME
3606 BFD_RELOC_ARC_SDA32_ME
3610 BFD_RELOC_AC_SECTOFF_U8
3612 BFD_RELOC_AC_SECTOFF_U8_1
3614 BFD_RELOC_AC_SECTOFF_U8_2
3616 BFD_RELOC_AC_SECTOFF_S9
3618 BFD_RELOC_AC_SECTOFF_S9_1
3620 BFD_RELOC_AC_SECTOFF_S9_2
3622 BFD_RELOC_ARC_SECTOFF_ME_1
3624 BFD_RELOC_ARC_SECTOFF_ME_2
3626 BFD_RELOC_ARC_SECTOFF_1
3628 BFD_RELOC_ARC_SECTOFF_2
3630 BFD_RELOC_ARC_SDA_12
3632 BFD_RELOC_ARC_SDA16_ST2
3634 BFD_RELOC_ARC_32_PCREL
3640 BFD_RELOC_ARC_GOTPC32
3646 BFD_RELOC_ARC_GLOB_DAT
3648 BFD_RELOC_ARC_JMP_SLOT
3650 BFD_RELOC_ARC_RELATIVE
3652 BFD_RELOC_ARC_GOTOFF
3656 BFD_RELOC_ARC_S21W_PCREL_PLT
3658 BFD_RELOC_ARC_S25H_PCREL_PLT
3660 BFD_RELOC_ARC_TLS_DTPMOD
3662 BFD_RELOC_ARC_TLS_TPOFF
3664 BFD_RELOC_ARC_TLS_GD_GOT
3666 BFD_RELOC_ARC_TLS_GD_LD
3668 BFD_RELOC_ARC_TLS_GD_CALL
3670 BFD_RELOC_ARC_TLS_IE_GOT
3672 BFD_RELOC_ARC_TLS_DTPOFF
3674 BFD_RELOC_ARC_TLS_DTPOFF_S9
3676 BFD_RELOC_ARC_TLS_LE_S9
3678 BFD_RELOC_ARC_TLS_LE_32
3680 BFD_RELOC_ARC_S25W_PCREL_PLT
3682 BFD_RELOC_ARC_S21H_PCREL_PLT
3684 BFD_RELOC_ARC_NPS_CMEM16
3689 BFD_RELOC_BFIN_16_IMM
3691 ADI Blackfin 16 bit immediate absolute reloc.
3693 BFD_RELOC_BFIN_16_HIGH
3695 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3697 BFD_RELOC_BFIN_4_PCREL
3699 ADI Blackfin 'a' part of LSETUP.
3701 BFD_RELOC_BFIN_5_PCREL
3705 BFD_RELOC_BFIN_16_LOW
3707 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3709 BFD_RELOC_BFIN_10_PCREL
3713 BFD_RELOC_BFIN_11_PCREL
3715 ADI Blackfin 'b' part of LSETUP.
3717 BFD_RELOC_BFIN_12_PCREL_JUMP
3721 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3723 ADI Blackfin Short jump, pcrel.
3725 BFD_RELOC_BFIN_24_PCREL_CALL_X
3727 ADI Blackfin Call.x not implemented.
3729 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3731 ADI Blackfin Long Jump pcrel.
3733 BFD_RELOC_BFIN_GOT17M4
3735 BFD_RELOC_BFIN_GOTHI
3737 BFD_RELOC_BFIN_GOTLO
3739 BFD_RELOC_BFIN_FUNCDESC
3741 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3743 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3745 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3747 BFD_RELOC_BFIN_FUNCDESC_VALUE
3749 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3751 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3753 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3755 BFD_RELOC_BFIN_GOTOFF17M4
3757 BFD_RELOC_BFIN_GOTOFFHI
3759 BFD_RELOC_BFIN_GOTOFFLO
3761 ADI Blackfin FD-PIC relocations.
3765 ADI Blackfin GOT relocation.
3767 BFD_RELOC_BFIN_PLTPC
3769 ADI Blackfin PLTPC relocation.
3771 BFD_ARELOC_BFIN_PUSH
3773 ADI Blackfin arithmetic relocation.
3775 BFD_ARELOC_BFIN_CONST
3777 ADI Blackfin arithmetic relocation.
3781 ADI Blackfin arithmetic relocation.
3785 ADI Blackfin arithmetic relocation.
3787 BFD_ARELOC_BFIN_MULT
3789 ADI Blackfin arithmetic relocation.
3793 ADI Blackfin arithmetic relocation.
3797 ADI Blackfin arithmetic relocation.
3799 BFD_ARELOC_BFIN_LSHIFT
3801 ADI Blackfin arithmetic relocation.
3803 BFD_ARELOC_BFIN_RSHIFT
3805 ADI Blackfin arithmetic relocation.
3809 ADI Blackfin arithmetic relocation.
3813 ADI Blackfin arithmetic relocation.
3817 ADI Blackfin arithmetic relocation.
3819 BFD_ARELOC_BFIN_LAND
3821 ADI Blackfin arithmetic relocation.
3825 ADI Blackfin arithmetic relocation.
3829 ADI Blackfin arithmetic relocation.
3833 ADI Blackfin arithmetic relocation.
3835 BFD_ARELOC_BFIN_COMP
3837 ADI Blackfin arithmetic relocation.
3839 BFD_ARELOC_BFIN_PAGE
3841 ADI Blackfin arithmetic relocation.
3843 BFD_ARELOC_BFIN_HWPAGE
3845 ADI Blackfin arithmetic relocation.
3847 BFD_ARELOC_BFIN_ADDR
3849 ADI Blackfin arithmetic relocation.
3852 BFD_RELOC_D10V_10_PCREL_R
3854 Mitsubishi D10V relocs.
3855 This is a 10-bit reloc with the right 2 bits
3858 BFD_RELOC_D10V_10_PCREL_L
3860 Mitsubishi D10V relocs.
3861 This is a 10-bit reloc with the right 2 bits
3862 assumed to be 0. This is the same as the previous reloc
3863 except it is in the left container, i.e.,
3864 shifted left 15 bits.
3868 This is an 18-bit reloc with the right 2 bits
3871 BFD_RELOC_D10V_18_PCREL
3873 This is an 18-bit reloc with the right 2 bits
3879 Mitsubishi D30V relocs.
3880 This is a 6-bit absolute reloc.
3882 BFD_RELOC_D30V_9_PCREL
3884 This is a 6-bit pc-relative reloc with
3885 the right 3 bits assumed to be 0.
3887 BFD_RELOC_D30V_9_PCREL_R
3889 This is a 6-bit pc-relative reloc with
3890 the right 3 bits assumed to be 0. Same
3891 as the previous reloc but on the right side
3896 This is a 12-bit absolute reloc with the
3897 right 3 bitsassumed to be 0.
3899 BFD_RELOC_D30V_15_PCREL
3901 This is a 12-bit pc-relative reloc with
3902 the right 3 bits assumed to be 0.
3904 BFD_RELOC_D30V_15_PCREL_R
3906 This is a 12-bit pc-relative reloc with
3907 the right 3 bits assumed to be 0. Same
3908 as the previous reloc but on the right side
3913 This is an 18-bit absolute reloc with
3914 the right 3 bits assumed to be 0.
3916 BFD_RELOC_D30V_21_PCREL
3918 This is an 18-bit pc-relative reloc with
3919 the right 3 bits assumed to be 0.
3921 BFD_RELOC_D30V_21_PCREL_R
3923 This is an 18-bit pc-relative reloc with
3924 the right 3 bits assumed to be 0. Same
3925 as the previous reloc but on the right side
3930 This is a 32-bit absolute reloc.
3932 BFD_RELOC_D30V_32_PCREL
3934 This is a 32-bit pc-relative reloc.
3937 BFD_RELOC_DLX_HI16_S
3952 BFD_RELOC_M32C_RL_JUMP
3954 BFD_RELOC_M32C_RL_1ADDR
3956 BFD_RELOC_M32C_RL_2ADDR
3958 Renesas M16C/M32C Relocations.
3963 Renesas M32R (formerly Mitsubishi M32R) relocs.
3964 This is a 24 bit absolute address.
3966 BFD_RELOC_M32R_10_PCREL
3968 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3970 BFD_RELOC_M32R_18_PCREL
3972 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3974 BFD_RELOC_M32R_26_PCREL
3976 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3978 BFD_RELOC_M32R_HI16_ULO
3980 This is a 16-bit reloc containing the high 16 bits of an address
3981 used when the lower 16 bits are treated as unsigned.
3983 BFD_RELOC_M32R_HI16_SLO
3985 This is a 16-bit reloc containing the high 16 bits of an address
3986 used when the lower 16 bits are treated as signed.
3990 This is a 16-bit reloc containing the lower 16 bits of an address.
3992 BFD_RELOC_M32R_SDA16
3994 This is a 16-bit reloc containing the small data area offset for use in
3995 add3, load, and store instructions.
3997 BFD_RELOC_M32R_GOT24
3999 BFD_RELOC_M32R_26_PLTREL
4003 BFD_RELOC_M32R_GLOB_DAT
4005 BFD_RELOC_M32R_JMP_SLOT
4007 BFD_RELOC_M32R_RELATIVE
4009 BFD_RELOC_M32R_GOTOFF
4011 BFD_RELOC_M32R_GOTOFF_HI_ULO
4013 BFD_RELOC_M32R_GOTOFF_HI_SLO
4015 BFD_RELOC_M32R_GOTOFF_LO
4017 BFD_RELOC_M32R_GOTPC24
4019 BFD_RELOC_M32R_GOT16_HI_ULO
4021 BFD_RELOC_M32R_GOT16_HI_SLO
4023 BFD_RELOC_M32R_GOT16_LO
4025 BFD_RELOC_M32R_GOTPC_HI_ULO
4027 BFD_RELOC_M32R_GOTPC_HI_SLO
4029 BFD_RELOC_M32R_GOTPC_LO
4038 This is a 20 bit absolute address.
4040 BFD_RELOC_NDS32_9_PCREL
4042 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4044 BFD_RELOC_NDS32_WORD_9_PCREL
4046 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4048 BFD_RELOC_NDS32_15_PCREL
4050 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4052 BFD_RELOC_NDS32_17_PCREL
4054 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4056 BFD_RELOC_NDS32_25_PCREL
4058 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4060 BFD_RELOC_NDS32_HI20
4062 This is a 20-bit reloc containing the high 20 bits of an address
4063 used with the lower 12 bits
4065 BFD_RELOC_NDS32_LO12S3
4067 This is a 12-bit reloc containing the lower 12 bits of an address
4068 then shift right by 3. This is used with ldi,sdi...
4070 BFD_RELOC_NDS32_LO12S2
4072 This is a 12-bit reloc containing the lower 12 bits of an address
4073 then shift left by 2. This is used with lwi,swi...
4075 BFD_RELOC_NDS32_LO12S1
4077 This is a 12-bit reloc containing the lower 12 bits of an address
4078 then shift left by 1. This is used with lhi,shi...
4080 BFD_RELOC_NDS32_LO12S0
4082 This is a 12-bit reloc containing the lower 12 bits of an address
4083 then shift left by 0. This is used with lbisbi...
4085 BFD_RELOC_NDS32_LO12S0_ORI
4087 This is a 12-bit reloc containing the lower 12 bits of an address
4088 then shift left by 0. This is only used with branch relaxations
4090 BFD_RELOC_NDS32_SDA15S3
4092 This is a 15-bit reloc containing the small data area 18-bit signed offset
4093 and shift left by 3 for use in ldi, sdi...
4095 BFD_RELOC_NDS32_SDA15S2
4097 This is a 15-bit reloc containing the small data area 17-bit signed offset
4098 and shift left by 2 for use in lwi, swi...
4100 BFD_RELOC_NDS32_SDA15S1
4102 This is a 15-bit reloc containing the small data area 16-bit signed offset
4103 and shift left by 1 for use in lhi, shi...
4105 BFD_RELOC_NDS32_SDA15S0
4107 This is a 15-bit reloc containing the small data area 15-bit signed offset
4108 and shift left by 0 for use in lbi, sbi...
4110 BFD_RELOC_NDS32_SDA16S3
4112 This is a 16-bit reloc containing the small data area 16-bit signed offset
4115 BFD_RELOC_NDS32_SDA17S2
4117 This is a 17-bit reloc containing the small data area 17-bit signed offset
4118 and shift left by 2 for use in lwi.gp, swi.gp...
4120 BFD_RELOC_NDS32_SDA18S1
4122 This is a 18-bit reloc containing the small data area 18-bit signed offset
4123 and shift left by 1 for use in lhi.gp, shi.gp...
4125 BFD_RELOC_NDS32_SDA19S0
4127 This is a 19-bit reloc containing the small data area 19-bit signed offset
4128 and shift left by 0 for use in lbi.gp, sbi.gp...
4130 BFD_RELOC_NDS32_GOT20
4132 BFD_RELOC_NDS32_9_PLTREL
4134 BFD_RELOC_NDS32_25_PLTREL
4136 BFD_RELOC_NDS32_COPY
4138 BFD_RELOC_NDS32_GLOB_DAT
4140 BFD_RELOC_NDS32_JMP_SLOT
4142 BFD_RELOC_NDS32_RELATIVE
4144 BFD_RELOC_NDS32_GOTOFF
4146 BFD_RELOC_NDS32_GOTOFF_HI20
4148 BFD_RELOC_NDS32_GOTOFF_LO12
4150 BFD_RELOC_NDS32_GOTPC20
4152 BFD_RELOC_NDS32_GOT_HI20
4154 BFD_RELOC_NDS32_GOT_LO12
4156 BFD_RELOC_NDS32_GOTPC_HI20
4158 BFD_RELOC_NDS32_GOTPC_LO12
4162 BFD_RELOC_NDS32_INSN16
4164 BFD_RELOC_NDS32_LABEL
4166 BFD_RELOC_NDS32_LONGCALL1
4168 BFD_RELOC_NDS32_LONGCALL2
4170 BFD_RELOC_NDS32_LONGCALL3
4172 BFD_RELOC_NDS32_LONGJUMP1
4174 BFD_RELOC_NDS32_LONGJUMP2
4176 BFD_RELOC_NDS32_LONGJUMP3
4178 BFD_RELOC_NDS32_LOADSTORE
4180 BFD_RELOC_NDS32_9_FIXED
4182 BFD_RELOC_NDS32_15_FIXED
4184 BFD_RELOC_NDS32_17_FIXED
4186 BFD_RELOC_NDS32_25_FIXED
4188 BFD_RELOC_NDS32_LONGCALL4
4190 BFD_RELOC_NDS32_LONGCALL5
4192 BFD_RELOC_NDS32_LONGCALL6
4194 BFD_RELOC_NDS32_LONGJUMP4
4196 BFD_RELOC_NDS32_LONGJUMP5
4198 BFD_RELOC_NDS32_LONGJUMP6
4200 BFD_RELOC_NDS32_LONGJUMP7
4204 BFD_RELOC_NDS32_PLTREL_HI20
4206 BFD_RELOC_NDS32_PLTREL_LO12
4208 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4210 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4214 BFD_RELOC_NDS32_SDA12S2_DP
4216 BFD_RELOC_NDS32_SDA12S2_SP
4218 BFD_RELOC_NDS32_LO12S2_DP
4220 BFD_RELOC_NDS32_LO12S2_SP
4224 BFD_RELOC_NDS32_DWARF2_OP1
4226 BFD_RELOC_NDS32_DWARF2_OP2
4228 BFD_RELOC_NDS32_DWARF2_LEB
4230 for dwarf2 debug_line.
4232 BFD_RELOC_NDS32_UPDATE_TA
4234 for eliminate 16-bit instructions
4236 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4238 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4240 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4242 BFD_RELOC_NDS32_GOT_LO15
4244 BFD_RELOC_NDS32_GOT_LO19
4246 BFD_RELOC_NDS32_GOTOFF_LO15
4248 BFD_RELOC_NDS32_GOTOFF_LO19
4250 BFD_RELOC_NDS32_GOT15S2
4252 BFD_RELOC_NDS32_GOT17S2
4254 for PIC object relaxation
4259 This is a 5 bit absolute address.
4261 BFD_RELOC_NDS32_10_UPCREL
4263 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4265 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4267 If fp were omitted, fp can used as another gp.
4269 BFD_RELOC_NDS32_RELAX_ENTRY
4271 BFD_RELOC_NDS32_GOT_SUFF
4273 BFD_RELOC_NDS32_GOTOFF_SUFF
4275 BFD_RELOC_NDS32_PLT_GOT_SUFF
4277 BFD_RELOC_NDS32_MULCALL_SUFF
4281 BFD_RELOC_NDS32_PTR_COUNT
4283 BFD_RELOC_NDS32_PTR_RESOLVED
4285 BFD_RELOC_NDS32_PLTBLOCK
4287 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4289 BFD_RELOC_NDS32_RELAX_REGION_END
4291 BFD_RELOC_NDS32_MINUEND
4293 BFD_RELOC_NDS32_SUBTRAHEND
4295 BFD_RELOC_NDS32_DIFF8
4297 BFD_RELOC_NDS32_DIFF16
4299 BFD_RELOC_NDS32_DIFF32
4301 BFD_RELOC_NDS32_DIFF_ULEB128
4303 BFD_RELOC_NDS32_EMPTY
4305 relaxation relative relocation types
4307 BFD_RELOC_NDS32_25_ABS
4309 This is a 25 bit absolute address.
4311 BFD_RELOC_NDS32_DATA
4313 BFD_RELOC_NDS32_TRAN
4315 BFD_RELOC_NDS32_17IFC_PCREL
4317 BFD_RELOC_NDS32_10IFCU_PCREL
4319 For ex9 and ifc using.
4321 BFD_RELOC_NDS32_TPOFF
4323 BFD_RELOC_NDS32_TLS_LE_HI20
4325 BFD_RELOC_NDS32_TLS_LE_LO12
4327 BFD_RELOC_NDS32_TLS_LE_ADD
4329 BFD_RELOC_NDS32_TLS_LE_LS
4331 BFD_RELOC_NDS32_GOTTPOFF
4333 BFD_RELOC_NDS32_TLS_IE_HI20
4335 BFD_RELOC_NDS32_TLS_IE_LO12S2
4337 BFD_RELOC_NDS32_TLS_TPOFF
4339 BFD_RELOC_NDS32_TLS_LE_20
4341 BFD_RELOC_NDS32_TLS_LE_15S0
4343 BFD_RELOC_NDS32_TLS_LE_15S1
4345 BFD_RELOC_NDS32_TLS_LE_15S2
4351 BFD_RELOC_V850_9_PCREL
4353 This is a 9-bit reloc
4355 BFD_RELOC_V850_22_PCREL
4357 This is a 22-bit reloc
4360 BFD_RELOC_V850_SDA_16_16_OFFSET
4362 This is a 16 bit offset from the short data area pointer.
4364 BFD_RELOC_V850_SDA_15_16_OFFSET
4366 This is a 16 bit offset (of which only 15 bits are used) from the
4367 short data area pointer.
4369 BFD_RELOC_V850_ZDA_16_16_OFFSET
4371 This is a 16 bit offset from the zero data area pointer.
4373 BFD_RELOC_V850_ZDA_15_16_OFFSET
4375 This is a 16 bit offset (of which only 15 bits are used) from the
4376 zero data area pointer.
4378 BFD_RELOC_V850_TDA_6_8_OFFSET
4380 This is an 8 bit offset (of which only 6 bits are used) from the
4381 tiny data area pointer.
4383 BFD_RELOC_V850_TDA_7_8_OFFSET
4385 This is an 8bit offset (of which only 7 bits are used) from the tiny
4388 BFD_RELOC_V850_TDA_7_7_OFFSET
4390 This is a 7 bit offset from the tiny data area pointer.
4392 BFD_RELOC_V850_TDA_16_16_OFFSET
4394 This is a 16 bit offset from the tiny data area pointer.
4397 BFD_RELOC_V850_TDA_4_5_OFFSET
4399 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4402 BFD_RELOC_V850_TDA_4_4_OFFSET
4404 This is a 4 bit offset from the tiny data area pointer.
4406 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4408 This is a 16 bit offset from the short data area pointer, with the
4409 bits placed non-contiguously in the instruction.
4411 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4413 This is a 16 bit offset from the zero data area pointer, with the
4414 bits placed non-contiguously in the instruction.
4416 BFD_RELOC_V850_CALLT_6_7_OFFSET
4418 This is a 6 bit offset from the call table base pointer.
4420 BFD_RELOC_V850_CALLT_16_16_OFFSET
4422 This is a 16 bit offset from the call table base pointer.
4424 BFD_RELOC_V850_LONGCALL
4426 Used for relaxing indirect function calls.
4428 BFD_RELOC_V850_LONGJUMP
4430 Used for relaxing indirect jumps.
4432 BFD_RELOC_V850_ALIGN
4434 Used to maintain alignment whilst relaxing.
4436 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4438 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4441 BFD_RELOC_V850_16_PCREL
4443 This is a 16-bit reloc.
4445 BFD_RELOC_V850_17_PCREL
4447 This is a 17-bit reloc.
4451 This is a 23-bit reloc.
4453 BFD_RELOC_V850_32_PCREL
4455 This is a 32-bit reloc.
4457 BFD_RELOC_V850_32_ABS
4459 This is a 32-bit reloc.
4461 BFD_RELOC_V850_16_SPLIT_OFFSET
4463 This is a 16-bit reloc.
4465 BFD_RELOC_V850_16_S1
4467 This is a 16-bit reloc.
4469 BFD_RELOC_V850_LO16_S1
4471 Low 16 bits. 16 bit shifted by 1.
4473 BFD_RELOC_V850_CALLT_15_16_OFFSET
4475 This is a 16 bit offset from the call table base pointer.
4477 BFD_RELOC_V850_32_GOTPCREL
4481 BFD_RELOC_V850_16_GOT
4485 BFD_RELOC_V850_32_GOT
4489 BFD_RELOC_V850_22_PLT_PCREL
4493 BFD_RELOC_V850_32_PLT_PCREL
4501 BFD_RELOC_V850_GLOB_DAT
4505 BFD_RELOC_V850_JMP_SLOT
4509 BFD_RELOC_V850_RELATIVE
4513 BFD_RELOC_V850_16_GOTOFF
4517 BFD_RELOC_V850_32_GOTOFF
4532 This is a 8bit DP reloc for the tms320c30, where the most
4533 significant 8 bits of a 24 bit word are placed into the least
4534 significant 8 bits of the opcode.
4537 BFD_RELOC_TIC54X_PARTLS7
4539 This is a 7bit reloc for the tms320c54x, where the least
4540 significant 7 bits of a 16 bit word are placed into the least
4541 significant 7 bits of the opcode.
4544 BFD_RELOC_TIC54X_PARTMS9
4546 This is a 9bit DP reloc for the tms320c54x, where the most
4547 significant 9 bits of a 16 bit word are placed into the least
4548 significant 9 bits of the opcode.
4553 This is an extended address 23-bit reloc for the tms320c54x.
4556 BFD_RELOC_TIC54X_16_OF_23
4558 This is a 16-bit reloc for the tms320c54x, where the least
4559 significant 16 bits of a 23-bit extended address are placed into
4563 BFD_RELOC_TIC54X_MS7_OF_23
4565 This is a reloc for the tms320c54x, where the most
4566 significant 7 bits of a 23-bit extended address are placed into
4570 BFD_RELOC_C6000_PCR_S21
4572 BFD_RELOC_C6000_PCR_S12
4574 BFD_RELOC_C6000_PCR_S10
4576 BFD_RELOC_C6000_PCR_S7
4578 BFD_RELOC_C6000_ABS_S16
4580 BFD_RELOC_C6000_ABS_L16
4582 BFD_RELOC_C6000_ABS_H16
4584 BFD_RELOC_C6000_SBR_U15_B
4586 BFD_RELOC_C6000_SBR_U15_H
4588 BFD_RELOC_C6000_SBR_U15_W
4590 BFD_RELOC_C6000_SBR_S16
4592 BFD_RELOC_C6000_SBR_L16_B
4594 BFD_RELOC_C6000_SBR_L16_H
4596 BFD_RELOC_C6000_SBR_L16_W
4598 BFD_RELOC_C6000_SBR_H16_B
4600 BFD_RELOC_C6000_SBR_H16_H
4602 BFD_RELOC_C6000_SBR_H16_W
4604 BFD_RELOC_C6000_SBR_GOT_U15_W
4606 BFD_RELOC_C6000_SBR_GOT_L16_W
4608 BFD_RELOC_C6000_SBR_GOT_H16_W
4610 BFD_RELOC_C6000_DSBT_INDEX
4612 BFD_RELOC_C6000_PREL31
4614 BFD_RELOC_C6000_COPY
4616 BFD_RELOC_C6000_JUMP_SLOT
4618 BFD_RELOC_C6000_EHTYPE
4620 BFD_RELOC_C6000_PCR_H16
4622 BFD_RELOC_C6000_PCR_L16
4624 BFD_RELOC_C6000_ALIGN
4626 BFD_RELOC_C6000_FPHEAD
4628 BFD_RELOC_C6000_NOCMP
4630 TMS320C6000 relocations.
4635 This is a 48 bit reloc for the FR30 that stores 32 bits.
4639 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4642 BFD_RELOC_FR30_6_IN_4
4644 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4647 BFD_RELOC_FR30_8_IN_8
4649 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4652 BFD_RELOC_FR30_9_IN_8
4654 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4657 BFD_RELOC_FR30_10_IN_8
4659 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4662 BFD_RELOC_FR30_9_PCREL
4664 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4665 short offset into 8 bits.
4667 BFD_RELOC_FR30_12_PCREL
4669 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4670 short offset into 11 bits.
4673 BFD_RELOC_MCORE_PCREL_IMM8BY4
4675 BFD_RELOC_MCORE_PCREL_IMM11BY2
4677 BFD_RELOC_MCORE_PCREL_IMM4BY2
4679 BFD_RELOC_MCORE_PCREL_32
4681 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4685 Motorola Mcore relocations.
4694 BFD_RELOC_MEP_PCREL8A2
4696 BFD_RELOC_MEP_PCREL12A2
4698 BFD_RELOC_MEP_PCREL17A2
4700 BFD_RELOC_MEP_PCREL24A2
4702 BFD_RELOC_MEP_PCABS24A2
4714 BFD_RELOC_MEP_TPREL7
4716 BFD_RELOC_MEP_TPREL7A2
4718 BFD_RELOC_MEP_TPREL7A4
4720 BFD_RELOC_MEP_UIMM24
4722 BFD_RELOC_MEP_ADDR24A4
4724 BFD_RELOC_MEP_GNU_VTINHERIT
4726 BFD_RELOC_MEP_GNU_VTENTRY
4728 Toshiba Media Processor Relocations.
4732 BFD_RELOC_METAG_HIADDR16
4734 BFD_RELOC_METAG_LOADDR16
4736 BFD_RELOC_METAG_RELBRANCH
4738 BFD_RELOC_METAG_GETSETOFF
4740 BFD_RELOC_METAG_HIOG
4742 BFD_RELOC_METAG_LOOG
4744 BFD_RELOC_METAG_REL8
4746 BFD_RELOC_METAG_REL16
4748 BFD_RELOC_METAG_HI16_GOTOFF
4750 BFD_RELOC_METAG_LO16_GOTOFF
4752 BFD_RELOC_METAG_GETSET_GOTOFF
4754 BFD_RELOC_METAG_GETSET_GOT
4756 BFD_RELOC_METAG_HI16_GOTPC
4758 BFD_RELOC_METAG_LO16_GOTPC
4760 BFD_RELOC_METAG_HI16_PLT
4762 BFD_RELOC_METAG_LO16_PLT
4764 BFD_RELOC_METAG_RELBRANCH_PLT
4766 BFD_RELOC_METAG_GOTOFF
4770 BFD_RELOC_METAG_COPY
4772 BFD_RELOC_METAG_JMP_SLOT
4774 BFD_RELOC_METAG_RELATIVE
4776 BFD_RELOC_METAG_GLOB_DAT
4778 BFD_RELOC_METAG_TLS_GD
4780 BFD_RELOC_METAG_TLS_LDM
4782 BFD_RELOC_METAG_TLS_LDO_HI16
4784 BFD_RELOC_METAG_TLS_LDO_LO16
4786 BFD_RELOC_METAG_TLS_LDO
4788 BFD_RELOC_METAG_TLS_IE
4790 BFD_RELOC_METAG_TLS_IENONPIC
4792 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4794 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4796 BFD_RELOC_METAG_TLS_TPOFF
4798 BFD_RELOC_METAG_TLS_DTPMOD
4800 BFD_RELOC_METAG_TLS_DTPOFF
4802 BFD_RELOC_METAG_TLS_LE
4804 BFD_RELOC_METAG_TLS_LE_HI16
4806 BFD_RELOC_METAG_TLS_LE_LO16
4808 Imagination Technologies Meta relocations.
4813 BFD_RELOC_MMIX_GETA_1
4815 BFD_RELOC_MMIX_GETA_2
4817 BFD_RELOC_MMIX_GETA_3
4819 These are relocations for the GETA instruction.
4821 BFD_RELOC_MMIX_CBRANCH
4823 BFD_RELOC_MMIX_CBRANCH_J
4825 BFD_RELOC_MMIX_CBRANCH_1
4827 BFD_RELOC_MMIX_CBRANCH_2
4829 BFD_RELOC_MMIX_CBRANCH_3
4831 These are relocations for a conditional branch instruction.
4833 BFD_RELOC_MMIX_PUSHJ
4835 BFD_RELOC_MMIX_PUSHJ_1
4837 BFD_RELOC_MMIX_PUSHJ_2
4839 BFD_RELOC_MMIX_PUSHJ_3
4841 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4843 These are relocations for the PUSHJ instruction.
4847 BFD_RELOC_MMIX_JMP_1
4849 BFD_RELOC_MMIX_JMP_2
4851 BFD_RELOC_MMIX_JMP_3
4853 These are relocations for the JMP instruction.
4855 BFD_RELOC_MMIX_ADDR19
4857 This is a relocation for a relative address as in a GETA instruction or
4860 BFD_RELOC_MMIX_ADDR27
4862 This is a relocation for a relative address as in a JMP instruction.
4864 BFD_RELOC_MMIX_REG_OR_BYTE
4866 This is a relocation for an instruction field that may be a general
4867 register or a value 0..255.
4871 This is a relocation for an instruction field that may be a general
4874 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4876 This is a relocation for two instruction fields holding a register and
4877 an offset, the equivalent of the relocation.
4879 BFD_RELOC_MMIX_LOCAL
4881 This relocation is an assertion that the expression is not allocated as
4882 a global register. It does not modify contents.
4885 BFD_RELOC_AVR_7_PCREL
4887 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4888 short offset into 7 bits.
4890 BFD_RELOC_AVR_13_PCREL
4892 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4893 short offset into 12 bits.
4897 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4898 program memory address) into 16 bits.
4900 BFD_RELOC_AVR_LO8_LDI
4902 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4903 data memory address) into 8 bit immediate value of LDI insn.
4905 BFD_RELOC_AVR_HI8_LDI
4907 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4908 of data memory address) into 8 bit immediate value of LDI insn.
4910 BFD_RELOC_AVR_HH8_LDI
4912 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4913 of program memory address) into 8 bit immediate value of LDI insn.
4915 BFD_RELOC_AVR_MS8_LDI
4917 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4918 of 32 bit value) into 8 bit immediate value of LDI insn.
4920 BFD_RELOC_AVR_LO8_LDI_NEG
4922 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4923 (usually data memory address) into 8 bit immediate value of SUBI insn.
4925 BFD_RELOC_AVR_HI8_LDI_NEG
4927 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4928 (high 8 bit of data memory address) into 8 bit immediate value of
4931 BFD_RELOC_AVR_HH8_LDI_NEG
4933 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4934 (most high 8 bit of program memory address) into 8 bit immediate value
4935 of LDI or SUBI insn.
4937 BFD_RELOC_AVR_MS8_LDI_NEG
4939 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4940 of 32 bit value) into 8 bit immediate value of LDI insn.
4942 BFD_RELOC_AVR_LO8_LDI_PM
4944 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4945 command address) into 8 bit immediate value of LDI insn.
4947 BFD_RELOC_AVR_LO8_LDI_GS
4949 This is a 16 bit reloc for the AVR that stores 8 bit value
4950 (command address) into 8 bit immediate value of LDI insn. If the address
4951 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4954 BFD_RELOC_AVR_HI8_LDI_PM
4956 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4957 of command address) into 8 bit immediate value of LDI insn.
4959 BFD_RELOC_AVR_HI8_LDI_GS
4961 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4962 of command address) into 8 bit immediate value of LDI insn. If the address
4963 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4966 BFD_RELOC_AVR_HH8_LDI_PM
4968 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4969 of command address) into 8 bit immediate value of LDI insn.
4971 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4973 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4974 (usually command address) into 8 bit immediate value of SUBI insn.
4976 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4978 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4979 (high 8 bit of 16 bit command address) into 8 bit immediate value
4982 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4984 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4985 (high 6 bit of 22 bit command address) into 8 bit immediate
4990 This is a 32 bit reloc for the AVR that stores 23 bit value
4995 This is a 16 bit reloc for the AVR that stores all needed bits
4996 for absolute addressing with ldi with overflow check to linktime
5000 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5003 BFD_RELOC_AVR_6_ADIW
5005 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5010 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5011 in .byte lo8(symbol)
5015 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5016 in .byte hi8(symbol)
5020 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5021 in .byte hlo8(symbol)
5025 BFD_RELOC_AVR_DIFF16
5027 BFD_RELOC_AVR_DIFF32
5029 AVR relocations to mark the difference of two local symbols.
5030 These are only needed to support linker relaxation and can be ignored
5031 when not relaxing. The field is set to the value of the difference
5032 assuming no relaxation. The relocation encodes the position of the
5033 second symbol so the linker can determine whether to adjust the field
5036 BFD_RELOC_AVR_LDS_STS_16
5038 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5039 lds and sts instructions supported only tiny core.
5043 This is a 6 bit reloc for the AVR that stores an I/O register
5044 number for the IN and OUT instructions
5048 This is a 5 bit reloc for the AVR that stores an I/O register
5049 number for the SBIC, SBIS, SBI and CBI instructions
5053 BFD_RELOC_RL78_NEG16
5055 BFD_RELOC_RL78_NEG24
5057 BFD_RELOC_RL78_NEG32
5059 BFD_RELOC_RL78_16_OP
5061 BFD_RELOC_RL78_24_OP
5063 BFD_RELOC_RL78_32_OP
5071 BFD_RELOC_RL78_DIR3U_PCREL
5075 BFD_RELOC_RL78_GPRELB
5077 BFD_RELOC_RL78_GPRELW
5079 BFD_RELOC_RL78_GPRELL
5083 BFD_RELOC_RL78_OP_SUBTRACT
5085 BFD_RELOC_RL78_OP_NEG
5087 BFD_RELOC_RL78_OP_AND
5089 BFD_RELOC_RL78_OP_SHRA
5093 BFD_RELOC_RL78_ABS16
5095 BFD_RELOC_RL78_ABS16_REV
5097 BFD_RELOC_RL78_ABS32
5099 BFD_RELOC_RL78_ABS32_REV
5101 BFD_RELOC_RL78_ABS16U
5103 BFD_RELOC_RL78_ABS16UW
5105 BFD_RELOC_RL78_ABS16UL
5107 BFD_RELOC_RL78_RELAX
5117 BFD_RELOC_RL78_SADDR
5119 Renesas RL78 Relocations.
5142 BFD_RELOC_RX_DIR3U_PCREL
5154 BFD_RELOC_RX_OP_SUBTRACT
5162 BFD_RELOC_RX_ABS16_REV
5166 BFD_RELOC_RX_ABS32_REV
5170 BFD_RELOC_RX_ABS16UW
5172 BFD_RELOC_RX_ABS16UL
5176 Renesas RX Relocations.
5189 32 bit PC relative PLT address.
5193 Copy symbol at runtime.
5195 BFD_RELOC_390_GLOB_DAT
5199 BFD_RELOC_390_JMP_SLOT
5203 BFD_RELOC_390_RELATIVE
5205 Adjust by program base.
5209 32 bit PC relative offset to GOT.
5215 BFD_RELOC_390_PC12DBL
5217 PC relative 12 bit shifted by 1.
5219 BFD_RELOC_390_PLT12DBL
5221 12 bit PC rel. PLT shifted by 1.
5223 BFD_RELOC_390_PC16DBL
5225 PC relative 16 bit shifted by 1.
5227 BFD_RELOC_390_PLT16DBL
5229 16 bit PC rel. PLT shifted by 1.
5231 BFD_RELOC_390_PC24DBL
5233 PC relative 24 bit shifted by 1.
5235 BFD_RELOC_390_PLT24DBL
5237 24 bit PC rel. PLT shifted by 1.
5239 BFD_RELOC_390_PC32DBL
5241 PC relative 32 bit shifted by 1.
5243 BFD_RELOC_390_PLT32DBL
5245 32 bit PC rel. PLT shifted by 1.
5247 BFD_RELOC_390_GOTPCDBL
5249 32 bit PC rel. GOT shifted by 1.
5257 64 bit PC relative PLT address.
5259 BFD_RELOC_390_GOTENT
5261 32 bit rel. offset to GOT entry.
5263 BFD_RELOC_390_GOTOFF64
5265 64 bit offset to GOT.
5267 BFD_RELOC_390_GOTPLT12
5269 12-bit offset to symbol-entry within GOT, with PLT handling.
5271 BFD_RELOC_390_GOTPLT16
5273 16-bit offset to symbol-entry within GOT, with PLT handling.
5275 BFD_RELOC_390_GOTPLT32
5277 32-bit offset to symbol-entry within GOT, with PLT handling.
5279 BFD_RELOC_390_GOTPLT64
5281 64-bit offset to symbol-entry within GOT, with PLT handling.
5283 BFD_RELOC_390_GOTPLTENT
5285 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5287 BFD_RELOC_390_PLTOFF16
5289 16-bit rel. offset from the GOT to a PLT entry.
5291 BFD_RELOC_390_PLTOFF32
5293 32-bit rel. offset from the GOT to a PLT entry.
5295 BFD_RELOC_390_PLTOFF64
5297 64-bit rel. offset from the GOT to a PLT entry.
5300 BFD_RELOC_390_TLS_LOAD
5302 BFD_RELOC_390_TLS_GDCALL
5304 BFD_RELOC_390_TLS_LDCALL
5306 BFD_RELOC_390_TLS_GD32
5308 BFD_RELOC_390_TLS_GD64
5310 BFD_RELOC_390_TLS_GOTIE12
5312 BFD_RELOC_390_TLS_GOTIE32
5314 BFD_RELOC_390_TLS_GOTIE64
5316 BFD_RELOC_390_TLS_LDM32
5318 BFD_RELOC_390_TLS_LDM64
5320 BFD_RELOC_390_TLS_IE32
5322 BFD_RELOC_390_TLS_IE64
5324 BFD_RELOC_390_TLS_IEENT
5326 BFD_RELOC_390_TLS_LE32
5328 BFD_RELOC_390_TLS_LE64
5330 BFD_RELOC_390_TLS_LDO32
5332 BFD_RELOC_390_TLS_LDO64
5334 BFD_RELOC_390_TLS_DTPMOD
5336 BFD_RELOC_390_TLS_DTPOFF
5338 BFD_RELOC_390_TLS_TPOFF
5340 s390 tls relocations.
5347 BFD_RELOC_390_GOTPLT20
5349 BFD_RELOC_390_TLS_GOTIE20
5351 Long displacement extension.
5354 BFD_RELOC_390_IRELATIVE
5356 STT_GNU_IFUNC relocation.
5359 BFD_RELOC_SCORE_GPREL15
5362 Low 16 bit for load/store
5364 BFD_RELOC_SCORE_DUMMY2
5368 This is a 24-bit reloc with the right 1 bit assumed to be 0
5370 BFD_RELOC_SCORE_BRANCH
5372 This is a 19-bit reloc with the right 1 bit assumed to be 0
5374 BFD_RELOC_SCORE_IMM30
5376 This is a 32-bit reloc for 48-bit instructions.
5378 BFD_RELOC_SCORE_IMM32
5380 This is a 32-bit reloc for 48-bit instructions.
5382 BFD_RELOC_SCORE16_JMP
5384 This is a 11-bit reloc with the right 1 bit assumed to be 0
5386 BFD_RELOC_SCORE16_BRANCH
5388 This is a 8-bit reloc with the right 1 bit assumed to be 0
5390 BFD_RELOC_SCORE_BCMP
5392 This is a 9-bit reloc with the right 1 bit assumed to be 0
5394 BFD_RELOC_SCORE_GOT15
5396 BFD_RELOC_SCORE_GOT_LO16
5398 BFD_RELOC_SCORE_CALL15
5400 BFD_RELOC_SCORE_DUMMY_HI16
5402 Undocumented Score relocs
5407 Scenix IP2K - 9-bit register number / data address
5411 Scenix IP2K - 4-bit register/data bank number
5413 BFD_RELOC_IP2K_ADDR16CJP
5415 Scenix IP2K - low 13 bits of instruction word address
5417 BFD_RELOC_IP2K_PAGE3
5419 Scenix IP2K - high 3 bits of instruction word address
5421 BFD_RELOC_IP2K_LO8DATA
5423 BFD_RELOC_IP2K_HI8DATA
5425 BFD_RELOC_IP2K_EX8DATA
5427 Scenix IP2K - ext/low/high 8 bits of data address
5429 BFD_RELOC_IP2K_LO8INSN
5431 BFD_RELOC_IP2K_HI8INSN
5433 Scenix IP2K - low/high 8 bits of instruction word address
5435 BFD_RELOC_IP2K_PC_SKIP
5437 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5441 Scenix IP2K - 16 bit word address in text section.
5443 BFD_RELOC_IP2K_FR_OFFSET
5445 Scenix IP2K - 7-bit sp or dp offset
5447 BFD_RELOC_VPE4KMATH_DATA
5449 BFD_RELOC_VPE4KMATH_INSN
5451 Scenix VPE4K coprocessor - data/insn-space addressing
5454 BFD_RELOC_VTABLE_INHERIT
5456 BFD_RELOC_VTABLE_ENTRY
5458 These two relocations are used by the linker to determine which of
5459 the entries in a C++ virtual function table are actually used. When
5460 the --gc-sections option is given, the linker will zero out the entries
5461 that are not used, so that the code for those functions need not be
5462 included in the output.
5464 VTABLE_INHERIT is a zero-space relocation used to describe to the
5465 linker the inheritance tree of a C++ virtual function table. The
5466 relocation's symbol should be the parent class' vtable, and the
5467 relocation should be located at the child vtable.
5469 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5470 virtual function table entry. The reloc's symbol should refer to the
5471 table of the class mentioned in the code. Off of that base, an offset
5472 describes the entry that is being used. For Rela hosts, this offset
5473 is stored in the reloc's addend. For Rel hosts, we are forced to put
5474 this offset in the reloc's section offset.
5477 BFD_RELOC_IA64_IMM14
5479 BFD_RELOC_IA64_IMM22
5481 BFD_RELOC_IA64_IMM64
5483 BFD_RELOC_IA64_DIR32MSB
5485 BFD_RELOC_IA64_DIR32LSB
5487 BFD_RELOC_IA64_DIR64MSB
5489 BFD_RELOC_IA64_DIR64LSB
5491 BFD_RELOC_IA64_GPREL22
5493 BFD_RELOC_IA64_GPREL64I
5495 BFD_RELOC_IA64_GPREL32MSB
5497 BFD_RELOC_IA64_GPREL32LSB
5499 BFD_RELOC_IA64_GPREL64MSB
5501 BFD_RELOC_IA64_GPREL64LSB
5503 BFD_RELOC_IA64_LTOFF22
5505 BFD_RELOC_IA64_LTOFF64I
5507 BFD_RELOC_IA64_PLTOFF22
5509 BFD_RELOC_IA64_PLTOFF64I
5511 BFD_RELOC_IA64_PLTOFF64MSB
5513 BFD_RELOC_IA64_PLTOFF64LSB
5515 BFD_RELOC_IA64_FPTR64I
5517 BFD_RELOC_IA64_FPTR32MSB
5519 BFD_RELOC_IA64_FPTR32LSB
5521 BFD_RELOC_IA64_FPTR64MSB
5523 BFD_RELOC_IA64_FPTR64LSB
5525 BFD_RELOC_IA64_PCREL21B
5527 BFD_RELOC_IA64_PCREL21BI
5529 BFD_RELOC_IA64_PCREL21M
5531 BFD_RELOC_IA64_PCREL21F
5533 BFD_RELOC_IA64_PCREL22
5535 BFD_RELOC_IA64_PCREL60B
5537 BFD_RELOC_IA64_PCREL64I
5539 BFD_RELOC_IA64_PCREL32MSB
5541 BFD_RELOC_IA64_PCREL32LSB
5543 BFD_RELOC_IA64_PCREL64MSB
5545 BFD_RELOC_IA64_PCREL64LSB
5547 BFD_RELOC_IA64_LTOFF_FPTR22
5549 BFD_RELOC_IA64_LTOFF_FPTR64I
5551 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5553 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5555 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5557 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5559 BFD_RELOC_IA64_SEGREL32MSB
5561 BFD_RELOC_IA64_SEGREL32LSB
5563 BFD_RELOC_IA64_SEGREL64MSB
5565 BFD_RELOC_IA64_SEGREL64LSB
5567 BFD_RELOC_IA64_SECREL32MSB
5569 BFD_RELOC_IA64_SECREL32LSB
5571 BFD_RELOC_IA64_SECREL64MSB
5573 BFD_RELOC_IA64_SECREL64LSB
5575 BFD_RELOC_IA64_REL32MSB
5577 BFD_RELOC_IA64_REL32LSB
5579 BFD_RELOC_IA64_REL64MSB
5581 BFD_RELOC_IA64_REL64LSB
5583 BFD_RELOC_IA64_LTV32MSB
5585 BFD_RELOC_IA64_LTV32LSB
5587 BFD_RELOC_IA64_LTV64MSB
5589 BFD_RELOC_IA64_LTV64LSB
5591 BFD_RELOC_IA64_IPLTMSB
5593 BFD_RELOC_IA64_IPLTLSB
5597 BFD_RELOC_IA64_LTOFF22X
5599 BFD_RELOC_IA64_LDXMOV
5601 BFD_RELOC_IA64_TPREL14
5603 BFD_RELOC_IA64_TPREL22
5605 BFD_RELOC_IA64_TPREL64I
5607 BFD_RELOC_IA64_TPREL64MSB
5609 BFD_RELOC_IA64_TPREL64LSB
5611 BFD_RELOC_IA64_LTOFF_TPREL22
5613 BFD_RELOC_IA64_DTPMOD64MSB
5615 BFD_RELOC_IA64_DTPMOD64LSB
5617 BFD_RELOC_IA64_LTOFF_DTPMOD22
5619 BFD_RELOC_IA64_DTPREL14
5621 BFD_RELOC_IA64_DTPREL22
5623 BFD_RELOC_IA64_DTPREL64I
5625 BFD_RELOC_IA64_DTPREL32MSB
5627 BFD_RELOC_IA64_DTPREL32LSB
5629 BFD_RELOC_IA64_DTPREL64MSB
5631 BFD_RELOC_IA64_DTPREL64LSB
5633 BFD_RELOC_IA64_LTOFF_DTPREL22
5635 Intel IA64 Relocations.
5638 BFD_RELOC_M68HC11_HI8
5640 Motorola 68HC11 reloc.
5641 This is the 8 bit high part of an absolute address.
5643 BFD_RELOC_M68HC11_LO8
5645 Motorola 68HC11 reloc.
5646 This is the 8 bit low part of an absolute address.
5648 BFD_RELOC_M68HC11_3B
5650 Motorola 68HC11 reloc.
5651 This is the 3 bit of a value.
5653 BFD_RELOC_M68HC11_RL_JUMP
5655 Motorola 68HC11 reloc.
5656 This reloc marks the beginning of a jump/call instruction.
5657 It is used for linker relaxation to correctly identify beginning
5658 of instruction and change some branches to use PC-relative
5661 BFD_RELOC_M68HC11_RL_GROUP
5663 Motorola 68HC11 reloc.
5664 This reloc marks a group of several instructions that gcc generates
5665 and for which the linker relaxation pass can modify and/or remove
5668 BFD_RELOC_M68HC11_LO16
5670 Motorola 68HC11 reloc.
5671 This is the 16-bit lower part of an address. It is used for 'call'
5672 instruction to specify the symbol address without any special
5673 transformation (due to memory bank window).
5675 BFD_RELOC_M68HC11_PAGE
5677 Motorola 68HC11 reloc.
5678 This is a 8-bit reloc that specifies the page number of an address.
5679 It is used by 'call' instruction to specify the page number of
5682 BFD_RELOC_M68HC11_24
5684 Motorola 68HC11 reloc.
5685 This is a 24-bit reloc that represents the address with a 16-bit
5686 value and a 8-bit page number. The symbol address is transformed
5687 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5689 BFD_RELOC_M68HC12_5B
5691 Motorola 68HC12 reloc.
5692 This is the 5 bits of a value.
5694 BFD_RELOC_XGATE_RL_JUMP
5696 Freescale XGATE reloc.
5697 This reloc marks the beginning of a bra/jal instruction.
5699 BFD_RELOC_XGATE_RL_GROUP
5701 Freescale XGATE reloc.
5702 This reloc marks a group of several instructions that gcc generates
5703 and for which the linker relaxation pass can modify and/or remove
5706 BFD_RELOC_XGATE_LO16
5708 Freescale XGATE reloc.
5709 This is the 16-bit lower part of an address. It is used for the '16-bit'
5712 BFD_RELOC_XGATE_GPAGE
5714 Freescale XGATE reloc.
5718 Freescale XGATE reloc.
5720 BFD_RELOC_XGATE_PCREL_9
5722 Freescale XGATE reloc.
5723 This is a 9-bit pc-relative reloc.
5725 BFD_RELOC_XGATE_PCREL_10
5727 Freescale XGATE reloc.
5728 This is a 10-bit pc-relative reloc.
5730 BFD_RELOC_XGATE_IMM8_LO
5732 Freescale XGATE reloc.
5733 This is the 16-bit lower part of an address. It is used for the '16-bit'
5736 BFD_RELOC_XGATE_IMM8_HI
5738 Freescale XGATE reloc.
5739 This is the 16-bit higher part of an address. It is used for the '16-bit'
5742 BFD_RELOC_XGATE_IMM3
5744 Freescale XGATE reloc.
5745 This is a 3-bit pc-relative reloc.
5747 BFD_RELOC_XGATE_IMM4
5749 Freescale XGATE reloc.
5750 This is a 4-bit pc-relative reloc.
5752 BFD_RELOC_XGATE_IMM5
5754 Freescale XGATE reloc.
5755 This is a 5-bit pc-relative reloc.
5757 BFD_RELOC_M68HC12_9B
5759 Motorola 68HC12 reloc.
5760 This is the 9 bits of a value.
5762 BFD_RELOC_M68HC12_16B
5764 Motorola 68HC12 reloc.
5765 This is the 16 bits of a value.
5767 BFD_RELOC_M68HC12_9_PCREL
5769 Motorola 68HC12/XGATE reloc.
5770 This is a PCREL9 branch.
5772 BFD_RELOC_M68HC12_10_PCREL
5774 Motorola 68HC12/XGATE reloc.
5775 This is a PCREL10 branch.
5777 BFD_RELOC_M68HC12_LO8XG
5779 Motorola 68HC12/XGATE reloc.
5780 This is the 8 bit low part of an absolute address and immediately precedes
5781 a matching HI8XG part.
5783 BFD_RELOC_M68HC12_HI8XG
5785 Motorola 68HC12/XGATE reloc.
5786 This is the 8 bit high part of an absolute address and immediately follows
5787 a matching LO8XG part.
5791 BFD_RELOC_16C_NUM08_C
5795 BFD_RELOC_16C_NUM16_C
5799 BFD_RELOC_16C_NUM32_C
5801 BFD_RELOC_16C_DISP04
5803 BFD_RELOC_16C_DISP04_C
5805 BFD_RELOC_16C_DISP08
5807 BFD_RELOC_16C_DISP08_C
5809 BFD_RELOC_16C_DISP16
5811 BFD_RELOC_16C_DISP16_C
5813 BFD_RELOC_16C_DISP24
5815 BFD_RELOC_16C_DISP24_C
5817 BFD_RELOC_16C_DISP24a
5819 BFD_RELOC_16C_DISP24a_C
5823 BFD_RELOC_16C_REG04_C
5825 BFD_RELOC_16C_REG04a
5827 BFD_RELOC_16C_REG04a_C
5831 BFD_RELOC_16C_REG14_C
5835 BFD_RELOC_16C_REG16_C
5839 BFD_RELOC_16C_REG20_C
5843 BFD_RELOC_16C_ABS20_C
5847 BFD_RELOC_16C_ABS24_C
5851 BFD_RELOC_16C_IMM04_C
5855 BFD_RELOC_16C_IMM16_C
5859 BFD_RELOC_16C_IMM20_C
5863 BFD_RELOC_16C_IMM24_C
5867 BFD_RELOC_16C_IMM32_C
5869 NS CR16C Relocations.
5874 BFD_RELOC_CR16_NUM16
5876 BFD_RELOC_CR16_NUM32
5878 BFD_RELOC_CR16_NUM32a
5880 BFD_RELOC_CR16_REGREL0
5882 BFD_RELOC_CR16_REGREL4
5884 BFD_RELOC_CR16_REGREL4a
5886 BFD_RELOC_CR16_REGREL14
5888 BFD_RELOC_CR16_REGREL14a
5890 BFD_RELOC_CR16_REGREL16
5892 BFD_RELOC_CR16_REGREL20
5894 BFD_RELOC_CR16_REGREL20a
5896 BFD_RELOC_CR16_ABS20
5898 BFD_RELOC_CR16_ABS24
5904 BFD_RELOC_CR16_IMM16
5906 BFD_RELOC_CR16_IMM20
5908 BFD_RELOC_CR16_IMM24
5910 BFD_RELOC_CR16_IMM32
5912 BFD_RELOC_CR16_IMM32a
5914 BFD_RELOC_CR16_DISP4
5916 BFD_RELOC_CR16_DISP8
5918 BFD_RELOC_CR16_DISP16
5920 BFD_RELOC_CR16_DISP20
5922 BFD_RELOC_CR16_DISP24
5924 BFD_RELOC_CR16_DISP24a
5926 BFD_RELOC_CR16_SWITCH8
5928 BFD_RELOC_CR16_SWITCH16
5930 BFD_RELOC_CR16_SWITCH32
5932 BFD_RELOC_CR16_GOT_REGREL20
5934 BFD_RELOC_CR16_GOTC_REGREL20
5936 BFD_RELOC_CR16_GLOB_DAT
5938 NS CR16 Relocations.
5945 BFD_RELOC_CRX_REL8_CMP
5953 BFD_RELOC_CRX_REGREL12
5955 BFD_RELOC_CRX_REGREL22
5957 BFD_RELOC_CRX_REGREL28
5959 BFD_RELOC_CRX_REGREL32
5975 BFD_RELOC_CRX_SWITCH8
5977 BFD_RELOC_CRX_SWITCH16
5979 BFD_RELOC_CRX_SWITCH32
5984 BFD_RELOC_CRIS_BDISP8
5986 BFD_RELOC_CRIS_UNSIGNED_5
5988 BFD_RELOC_CRIS_SIGNED_6
5990 BFD_RELOC_CRIS_UNSIGNED_6
5992 BFD_RELOC_CRIS_SIGNED_8
5994 BFD_RELOC_CRIS_UNSIGNED_8
5996 BFD_RELOC_CRIS_SIGNED_16
5998 BFD_RELOC_CRIS_UNSIGNED_16
6000 BFD_RELOC_CRIS_LAPCQ_OFFSET
6002 BFD_RELOC_CRIS_UNSIGNED_4
6004 These relocs are only used within the CRIS assembler. They are not
6005 (at present) written to any object files.
6009 BFD_RELOC_CRIS_GLOB_DAT
6011 BFD_RELOC_CRIS_JUMP_SLOT
6013 BFD_RELOC_CRIS_RELATIVE
6015 Relocs used in ELF shared libraries for CRIS.
6017 BFD_RELOC_CRIS_32_GOT
6019 32-bit offset to symbol-entry within GOT.
6021 BFD_RELOC_CRIS_16_GOT
6023 16-bit offset to symbol-entry within GOT.
6025 BFD_RELOC_CRIS_32_GOTPLT
6027 32-bit offset to symbol-entry within GOT, with PLT handling.
6029 BFD_RELOC_CRIS_16_GOTPLT
6031 16-bit offset to symbol-entry within GOT, with PLT handling.
6033 BFD_RELOC_CRIS_32_GOTREL
6035 32-bit offset to symbol, relative to GOT.
6037 BFD_RELOC_CRIS_32_PLT_GOTREL
6039 32-bit offset to symbol with PLT entry, relative to GOT.
6041 BFD_RELOC_CRIS_32_PLT_PCREL
6043 32-bit offset to symbol with PLT entry, relative to this relocation.
6046 BFD_RELOC_CRIS_32_GOT_GD
6048 BFD_RELOC_CRIS_16_GOT_GD
6050 BFD_RELOC_CRIS_32_GD
6054 BFD_RELOC_CRIS_32_DTPREL
6056 BFD_RELOC_CRIS_16_DTPREL
6058 BFD_RELOC_CRIS_32_GOT_TPREL
6060 BFD_RELOC_CRIS_16_GOT_TPREL
6062 BFD_RELOC_CRIS_32_TPREL
6064 BFD_RELOC_CRIS_16_TPREL
6066 BFD_RELOC_CRIS_DTPMOD
6068 BFD_RELOC_CRIS_32_IE
6070 Relocs used in TLS code for CRIS.
6075 BFD_RELOC_860_GLOB_DAT
6077 BFD_RELOC_860_JUMP_SLOT
6079 BFD_RELOC_860_RELATIVE
6089 BFD_RELOC_860_SPLIT0
6093 BFD_RELOC_860_SPLIT1
6097 BFD_RELOC_860_SPLIT2
6101 BFD_RELOC_860_LOGOT0
6103 BFD_RELOC_860_SPGOT0
6105 BFD_RELOC_860_LOGOT1
6107 BFD_RELOC_860_SPGOT1
6109 BFD_RELOC_860_LOGOTOFF0
6111 BFD_RELOC_860_SPGOTOFF0
6113 BFD_RELOC_860_LOGOTOFF1
6115 BFD_RELOC_860_SPGOTOFF1
6117 BFD_RELOC_860_LOGOTOFF2
6119 BFD_RELOC_860_LOGOTOFF3
6123 BFD_RELOC_860_HIGHADJ
6127 BFD_RELOC_860_HAGOTOFF
6135 BFD_RELOC_860_HIGOTOFF
6137 Intel i860 Relocations.
6140 BFD_RELOC_OR1K_REL_26
6142 BFD_RELOC_OR1K_GOTPC_HI16
6144 BFD_RELOC_OR1K_GOTPC_LO16
6146 BFD_RELOC_OR1K_GOT16
6148 BFD_RELOC_OR1K_PLT26
6150 BFD_RELOC_OR1K_GOTOFF_HI16
6152 BFD_RELOC_OR1K_GOTOFF_LO16
6156 BFD_RELOC_OR1K_GLOB_DAT
6158 BFD_RELOC_OR1K_JMP_SLOT
6160 BFD_RELOC_OR1K_RELATIVE
6162 BFD_RELOC_OR1K_TLS_GD_HI16
6164 BFD_RELOC_OR1K_TLS_GD_LO16
6166 BFD_RELOC_OR1K_TLS_LDM_HI16
6168 BFD_RELOC_OR1K_TLS_LDM_LO16
6170 BFD_RELOC_OR1K_TLS_LDO_HI16
6172 BFD_RELOC_OR1K_TLS_LDO_LO16
6174 BFD_RELOC_OR1K_TLS_IE_HI16
6176 BFD_RELOC_OR1K_TLS_IE_LO16
6178 BFD_RELOC_OR1K_TLS_LE_HI16
6180 BFD_RELOC_OR1K_TLS_LE_LO16
6182 BFD_RELOC_OR1K_TLS_TPOFF
6184 BFD_RELOC_OR1K_TLS_DTPOFF
6186 BFD_RELOC_OR1K_TLS_DTPMOD
6188 OpenRISC 1000 Relocations.
6191 BFD_RELOC_H8_DIR16A8
6193 BFD_RELOC_H8_DIR16R8
6195 BFD_RELOC_H8_DIR24A8
6197 BFD_RELOC_H8_DIR24R8
6199 BFD_RELOC_H8_DIR32A16
6201 BFD_RELOC_H8_DISP32A16
6206 BFD_RELOC_XSTORMY16_REL_12
6208 BFD_RELOC_XSTORMY16_12
6210 BFD_RELOC_XSTORMY16_24
6212 BFD_RELOC_XSTORMY16_FPTR16
6214 Sony Xstormy16 Relocations.
6219 Self-describing complex relocations.
6231 Infineon Relocations.
6234 BFD_RELOC_VAX_GLOB_DAT
6236 BFD_RELOC_VAX_JMP_SLOT
6238 BFD_RELOC_VAX_RELATIVE
6240 Relocations used by VAX ELF.
6245 Morpho MT - 16 bit immediate relocation.
6249 Morpho MT - Hi 16 bits of an address.
6253 Morpho MT - Low 16 bits of an address.
6255 BFD_RELOC_MT_GNU_VTINHERIT
6257 Morpho MT - Used to tell the linker which vtable entries are used.
6259 BFD_RELOC_MT_GNU_VTENTRY
6261 Morpho MT - Used to tell the linker which vtable entries are used.
6263 BFD_RELOC_MT_PCINSN8
6265 Morpho MT - 8 bit immediate relocation.
6268 BFD_RELOC_MSP430_10_PCREL
6270 BFD_RELOC_MSP430_16_PCREL
6274 BFD_RELOC_MSP430_16_PCREL_BYTE
6276 BFD_RELOC_MSP430_16_BYTE
6278 BFD_RELOC_MSP430_2X_PCREL
6280 BFD_RELOC_MSP430_RL_PCREL
6282 BFD_RELOC_MSP430_ABS8
6284 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6286 BFD_RELOC_MSP430X_PCR20_EXT_DST
6288 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6290 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6292 BFD_RELOC_MSP430X_ABS20_EXT_DST
6294 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6296 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6298 BFD_RELOC_MSP430X_ABS20_ADR_DST
6300 BFD_RELOC_MSP430X_PCR16
6302 BFD_RELOC_MSP430X_PCR20_CALL
6304 BFD_RELOC_MSP430X_ABS16
6306 BFD_RELOC_MSP430_ABS_HI16
6308 BFD_RELOC_MSP430_PREL31
6310 BFD_RELOC_MSP430_SYM_DIFF
6312 msp430 specific relocation codes
6319 BFD_RELOC_NIOS2_CALL26
6321 BFD_RELOC_NIOS2_IMM5
6323 BFD_RELOC_NIOS2_CACHE_OPX
6325 BFD_RELOC_NIOS2_IMM6
6327 BFD_RELOC_NIOS2_IMM8
6329 BFD_RELOC_NIOS2_HI16
6331 BFD_RELOC_NIOS2_LO16
6333 BFD_RELOC_NIOS2_HIADJ16
6335 BFD_RELOC_NIOS2_GPREL
6337 BFD_RELOC_NIOS2_UJMP
6339 BFD_RELOC_NIOS2_CJMP
6341 BFD_RELOC_NIOS2_CALLR
6343 BFD_RELOC_NIOS2_ALIGN
6345 BFD_RELOC_NIOS2_GOT16
6347 BFD_RELOC_NIOS2_CALL16
6349 BFD_RELOC_NIOS2_GOTOFF_LO
6351 BFD_RELOC_NIOS2_GOTOFF_HA
6353 BFD_RELOC_NIOS2_PCREL_LO
6355 BFD_RELOC_NIOS2_PCREL_HA
6357 BFD_RELOC_NIOS2_TLS_GD16
6359 BFD_RELOC_NIOS2_TLS_LDM16
6361 BFD_RELOC_NIOS2_TLS_LDO16
6363 BFD_RELOC_NIOS2_TLS_IE16
6365 BFD_RELOC_NIOS2_TLS_LE16
6367 BFD_RELOC_NIOS2_TLS_DTPMOD
6369 BFD_RELOC_NIOS2_TLS_DTPREL
6371 BFD_RELOC_NIOS2_TLS_TPREL
6373 BFD_RELOC_NIOS2_COPY
6375 BFD_RELOC_NIOS2_GLOB_DAT
6377 BFD_RELOC_NIOS2_JUMP_SLOT
6379 BFD_RELOC_NIOS2_RELATIVE
6381 BFD_RELOC_NIOS2_GOTOFF
6383 BFD_RELOC_NIOS2_CALL26_NOAT
6385 BFD_RELOC_NIOS2_GOT_LO
6387 BFD_RELOC_NIOS2_GOT_HA
6389 BFD_RELOC_NIOS2_CALL_LO
6391 BFD_RELOC_NIOS2_CALL_HA
6393 BFD_RELOC_NIOS2_R2_S12
6395 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6397 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6399 BFD_RELOC_NIOS2_R2_T1I7_2
6401 BFD_RELOC_NIOS2_R2_T2I4
6403 BFD_RELOC_NIOS2_R2_T2I4_1
6405 BFD_RELOC_NIOS2_R2_T2I4_2
6407 BFD_RELOC_NIOS2_R2_X1I7_2
6409 BFD_RELOC_NIOS2_R2_X2L5
6411 BFD_RELOC_NIOS2_R2_F1I5_2
6413 BFD_RELOC_NIOS2_R2_L5I4X1
6415 BFD_RELOC_NIOS2_R2_T1X1I6
6417 BFD_RELOC_NIOS2_R2_T1X1I6_2
6419 Relocations used by the Altera Nios II core.
6422 BFD_RELOC_IQ2000_OFFSET_16
6424 BFD_RELOC_IQ2000_OFFSET_21
6426 BFD_RELOC_IQ2000_UHI16
6431 BFD_RELOC_XTENSA_RTLD
6433 Special Xtensa relocation used only by PLT entries in ELF shared
6434 objects to indicate that the runtime linker should set the value
6435 to one of its own internal functions or data structures.
6437 BFD_RELOC_XTENSA_GLOB_DAT
6439 BFD_RELOC_XTENSA_JMP_SLOT
6441 BFD_RELOC_XTENSA_RELATIVE
6443 Xtensa relocations for ELF shared objects.
6445 BFD_RELOC_XTENSA_PLT
6447 Xtensa relocation used in ELF object files for symbols that may require
6448 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6450 BFD_RELOC_XTENSA_DIFF8
6452 BFD_RELOC_XTENSA_DIFF16
6454 BFD_RELOC_XTENSA_DIFF32
6456 Xtensa relocations to mark the difference of two local symbols.
6457 These are only needed to support linker relaxation and can be ignored
6458 when not relaxing. The field is set to the value of the difference
6459 assuming no relaxation. The relocation encodes the position of the
6460 first symbol so the linker can determine whether to adjust the field
6463 BFD_RELOC_XTENSA_SLOT0_OP
6465 BFD_RELOC_XTENSA_SLOT1_OP
6467 BFD_RELOC_XTENSA_SLOT2_OP
6469 BFD_RELOC_XTENSA_SLOT3_OP
6471 BFD_RELOC_XTENSA_SLOT4_OP
6473 BFD_RELOC_XTENSA_SLOT5_OP
6475 BFD_RELOC_XTENSA_SLOT6_OP
6477 BFD_RELOC_XTENSA_SLOT7_OP
6479 BFD_RELOC_XTENSA_SLOT8_OP
6481 BFD_RELOC_XTENSA_SLOT9_OP
6483 BFD_RELOC_XTENSA_SLOT10_OP
6485 BFD_RELOC_XTENSA_SLOT11_OP
6487 BFD_RELOC_XTENSA_SLOT12_OP
6489 BFD_RELOC_XTENSA_SLOT13_OP
6491 BFD_RELOC_XTENSA_SLOT14_OP
6493 Generic Xtensa relocations for instruction operands. Only the slot
6494 number is encoded in the relocation. The relocation applies to the
6495 last PC-relative immediate operand, or if there are no PC-relative
6496 immediates, to the last immediate operand.
6498 BFD_RELOC_XTENSA_SLOT0_ALT
6500 BFD_RELOC_XTENSA_SLOT1_ALT
6502 BFD_RELOC_XTENSA_SLOT2_ALT
6504 BFD_RELOC_XTENSA_SLOT3_ALT
6506 BFD_RELOC_XTENSA_SLOT4_ALT
6508 BFD_RELOC_XTENSA_SLOT5_ALT
6510 BFD_RELOC_XTENSA_SLOT6_ALT
6512 BFD_RELOC_XTENSA_SLOT7_ALT
6514 BFD_RELOC_XTENSA_SLOT8_ALT
6516 BFD_RELOC_XTENSA_SLOT9_ALT
6518 BFD_RELOC_XTENSA_SLOT10_ALT
6520 BFD_RELOC_XTENSA_SLOT11_ALT
6522 BFD_RELOC_XTENSA_SLOT12_ALT
6524 BFD_RELOC_XTENSA_SLOT13_ALT
6526 BFD_RELOC_XTENSA_SLOT14_ALT
6528 Alternate Xtensa relocations. Only the slot is encoded in the
6529 relocation. The meaning of these relocations is opcode-specific.
6531 BFD_RELOC_XTENSA_OP0
6533 BFD_RELOC_XTENSA_OP1
6535 BFD_RELOC_XTENSA_OP2
6537 Xtensa relocations for backward compatibility. These have all been
6538 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6540 BFD_RELOC_XTENSA_ASM_EXPAND
6542 Xtensa relocation to mark that the assembler expanded the
6543 instructions from an original target. The expansion size is
6544 encoded in the reloc size.
6546 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6548 Xtensa relocation to mark that the linker should simplify
6549 assembler-expanded instructions. This is commonly used
6550 internally by the linker after analysis of a
6551 BFD_RELOC_XTENSA_ASM_EXPAND.
6553 BFD_RELOC_XTENSA_TLSDESC_FN
6555 BFD_RELOC_XTENSA_TLSDESC_ARG
6557 BFD_RELOC_XTENSA_TLS_DTPOFF
6559 BFD_RELOC_XTENSA_TLS_TPOFF
6561 BFD_RELOC_XTENSA_TLS_FUNC
6563 BFD_RELOC_XTENSA_TLS_ARG
6565 BFD_RELOC_XTENSA_TLS_CALL
6567 Xtensa TLS relocations.
6572 8 bit signed offset in (ix+d) or (iy+d).
6590 BFD_RELOC_LM32_BRANCH
6592 BFD_RELOC_LM32_16_GOT
6594 BFD_RELOC_LM32_GOTOFF_HI16
6596 BFD_RELOC_LM32_GOTOFF_LO16
6600 BFD_RELOC_LM32_GLOB_DAT
6602 BFD_RELOC_LM32_JMP_SLOT
6604 BFD_RELOC_LM32_RELATIVE
6606 Lattice Mico32 relocations.
6609 BFD_RELOC_MACH_O_SECTDIFF
6611 Difference between two section addreses. Must be followed by a
6612 BFD_RELOC_MACH_O_PAIR.
6614 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6616 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6618 BFD_RELOC_MACH_O_PAIR
6620 Pair of relocation. Contains the first symbol.
6622 BFD_RELOC_MACH_O_SUBTRACTOR32
6624 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6626 BFD_RELOC_MACH_O_SUBTRACTOR64
6628 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6631 BFD_RELOC_MACH_O_X86_64_BRANCH32
6633 BFD_RELOC_MACH_O_X86_64_BRANCH8
6635 PCREL relocations. They are marked as branch to create PLT entry if
6638 BFD_RELOC_MACH_O_X86_64_GOT
6640 Used when referencing a GOT entry.
6642 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6644 Used when loading a GOT entry with movq. It is specially marked so that
6645 the linker could optimize the movq to a leaq if possible.
6647 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6649 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6651 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6653 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6655 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6657 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6661 BFD_RELOC_MACH_O_ARM64_ADDEND
6663 Addend for PAGE or PAGEOFF.
6665 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6667 Relative offset to page of GOT slot.
6669 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6671 Relative offset within page of GOT slot.
6673 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6675 Address of a GOT entry.
6678 BFD_RELOC_MICROBLAZE_32_LO
6680 This is a 32 bit reloc for the microblaze that stores the
6681 low 16 bits of a value
6683 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6685 This is a 32 bit pc-relative reloc for the microblaze that
6686 stores the low 16 bits of a value
6688 BFD_RELOC_MICROBLAZE_32_ROSDA
6690 This is a 32 bit reloc for the microblaze that stores a
6691 value relative to the read-only small data area anchor
6693 BFD_RELOC_MICROBLAZE_32_RWSDA
6695 This is a 32 bit reloc for the microblaze that stores a
6696 value relative to the read-write small data area anchor
6698 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6700 This is a 32 bit reloc for the microblaze to handle
6701 expressions of the form "Symbol Op Symbol"
6703 BFD_RELOC_MICROBLAZE_64_NONE
6705 This is a 64 bit reloc that stores the 32 bit pc relative
6706 value in two words (with an imm instruction). No relocation is
6707 done here - only used for relaxing
6709 BFD_RELOC_MICROBLAZE_64_GOTPC
6711 This is a 64 bit reloc that stores the 32 bit pc relative
6712 value in two words (with an imm instruction). The relocation is
6713 PC-relative GOT offset
6715 BFD_RELOC_MICROBLAZE_64_GOT
6717 This is a 64 bit reloc that stores the 32 bit pc relative
6718 value in two words (with an imm instruction). The relocation is
6721 BFD_RELOC_MICROBLAZE_64_PLT
6723 This is a 64 bit reloc that stores the 32 bit pc relative
6724 value in two words (with an imm instruction). The relocation is
6725 PC-relative offset into PLT
6727 BFD_RELOC_MICROBLAZE_64_GOTOFF
6729 This is a 64 bit reloc that stores the 32 bit GOT relative
6730 value in two words (with an imm instruction). The relocation is
6731 relative offset from _GLOBAL_OFFSET_TABLE_
6733 BFD_RELOC_MICROBLAZE_32_GOTOFF
6735 This is a 32 bit reloc that stores the 32 bit GOT relative
6736 value in a word. The relocation is relative offset from
6737 _GLOBAL_OFFSET_TABLE_
6739 BFD_RELOC_MICROBLAZE_COPY
6741 This is used to tell the dynamic linker to copy the value out of
6742 the dynamic object into the runtime process image.
6744 BFD_RELOC_MICROBLAZE_64_TLS
6748 BFD_RELOC_MICROBLAZE_64_TLSGD
6750 This is a 64 bit reloc that stores the 32 bit GOT relative value
6751 of the GOT TLS GD info entry in two words (with an imm instruction). The
6752 relocation is GOT offset.
6754 BFD_RELOC_MICROBLAZE_64_TLSLD
6756 This is a 64 bit reloc that stores the 32 bit GOT relative value
6757 of the GOT TLS LD info entry in two words (with an imm instruction). The
6758 relocation is GOT offset.
6760 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6762 This is a 32 bit reloc that stores the Module ID to GOT(n).
6764 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6766 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6768 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6770 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6773 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6775 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6776 to two words (uses imm instruction).
6778 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6780 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6781 to two words (uses imm instruction).
6784 BFD_RELOC_AARCH64_RELOC_START
6786 AArch64 pseudo relocation code to mark the start of the AArch64
6787 relocation enumerators. N.B. the order of the enumerators is
6788 important as several tables in the AArch64 bfd backend are indexed
6789 by these enumerators; make sure they are all synced.
6791 BFD_RELOC_AARCH64_NULL
6793 Deprecated AArch64 null relocation code.
6795 BFD_RELOC_AARCH64_NONE
6797 AArch64 null relocation code.
6799 BFD_RELOC_AARCH64_64
6801 BFD_RELOC_AARCH64_32
6803 BFD_RELOC_AARCH64_16
6805 Basic absolute relocations of N bits. These are equivalent to
6806 BFD_RELOC_N and they were added to assist the indexing of the howto
6809 BFD_RELOC_AARCH64_64_PCREL
6811 BFD_RELOC_AARCH64_32_PCREL
6813 BFD_RELOC_AARCH64_16_PCREL
6815 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6816 and they were added to assist the indexing of the howto table.
6818 BFD_RELOC_AARCH64_MOVW_G0
6820 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6821 of an unsigned address/value.
6823 BFD_RELOC_AARCH64_MOVW_G0_NC
6825 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6826 an address/value. No overflow checking.
6828 BFD_RELOC_AARCH64_MOVW_G1
6830 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6831 of an unsigned address/value.
6833 BFD_RELOC_AARCH64_MOVW_G1_NC
6835 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6836 of an address/value. No overflow checking.
6838 BFD_RELOC_AARCH64_MOVW_G2
6840 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6841 of an unsigned address/value.
6843 BFD_RELOC_AARCH64_MOVW_G2_NC
6845 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6846 of an address/value. No overflow checking.
6848 BFD_RELOC_AARCH64_MOVW_G3
6850 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6851 of a signed or unsigned address/value.
6853 BFD_RELOC_AARCH64_MOVW_G0_S
6855 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6856 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6859 BFD_RELOC_AARCH64_MOVW_G1_S
6861 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6862 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6865 BFD_RELOC_AARCH64_MOVW_G2_S
6867 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6868 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6871 BFD_RELOC_AARCH64_LD_LO19_PCREL
6873 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6874 offset. The lowest two bits must be zero and are not stored in the
6875 instruction, giving a 21 bit signed byte offset.
6877 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6879 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6881 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6883 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6884 offset, giving a 4KB aligned page base address.
6886 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6888 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6889 offset, giving a 4KB aligned page base address, but with no overflow
6892 BFD_RELOC_AARCH64_ADD_LO12
6894 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6895 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6897 BFD_RELOC_AARCH64_LDST8_LO12
6899 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6900 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6902 BFD_RELOC_AARCH64_TSTBR14
6904 AArch64 14 bit pc-relative test bit and branch.
6905 The lowest two bits must be zero and are not stored in the instruction,
6906 giving a 16 bit signed byte offset.
6908 BFD_RELOC_AARCH64_BRANCH19
6910 AArch64 19 bit pc-relative conditional branch and compare & branch.
6911 The lowest two bits must be zero and are not stored in the instruction,
6912 giving a 21 bit signed byte offset.
6914 BFD_RELOC_AARCH64_JUMP26
6916 AArch64 26 bit pc-relative unconditional branch.
6917 The lowest two bits must be zero and are not stored in the instruction,
6918 giving a 28 bit signed byte offset.
6920 BFD_RELOC_AARCH64_CALL26
6922 AArch64 26 bit pc-relative unconditional branch and link.
6923 The lowest two bits must be zero and are not stored in the instruction,
6924 giving a 28 bit signed byte offset.
6926 BFD_RELOC_AARCH64_LDST16_LO12
6928 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6929 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6931 BFD_RELOC_AARCH64_LDST32_LO12
6933 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6934 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6936 BFD_RELOC_AARCH64_LDST64_LO12
6938 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6939 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6941 BFD_RELOC_AARCH64_LDST128_LO12
6943 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6944 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6946 BFD_RELOC_AARCH64_GOT_LD_PREL19
6948 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6949 offset of the global offset table entry for a symbol. The lowest two
6950 bits must be zero and are not stored in the instruction, giving a 21
6951 bit signed byte offset. This relocation type requires signed overflow
6954 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6956 Get to the page base of the global offset table entry for a symbol as
6957 part of an ADRP instruction using a 21 bit PC relative value.Used in
6958 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6960 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6962 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6963 the GOT entry for this symbol. Used in conjunction with
6964 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6966 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6968 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6969 the GOT entry for this symbol. Used in conjunction with
6970 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6972 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
6974 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
6975 for this symbol. Valid in LP64 ABI only.
6977 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
6979 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
6980 for this symbol. Valid in LP64 ABI only.
6982 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
6984 Unsigned 15 bit byte offset for 64 bit load/store from the page of
6985 the GOT entry for this symbol. Valid in LP64 ABI only.
6987 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
6989 Scaled 14 bit byte offset to the page base of the global offset table.
6991 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
6993 Scaled 15 bit byte offset to the page base of the global offset table.
6995 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6997 Get to the page base of the global offset table entry for a symbols
6998 tls_index structure as part of an adrp instruction using a 21 bit PC
6999 relative value. Used in conjunction with
7000 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7002 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7004 AArch64 TLS General Dynamic
7006 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7008 Unsigned 12 bit byte offset to global offset table entry for a symbols
7009 tls_index structure. Used in conjunction with
7010 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7012 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7014 AArch64 TLS General Dynamic relocation.
7016 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7018 AArch64 TLS General Dynamic relocation.
7020 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7022 AArch64 TLS INITIAL EXEC relocation.
7024 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7026 AArch64 TLS INITIAL EXEC relocation.
7028 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7030 AArch64 TLS INITIAL EXEC relocation.
7032 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7034 AArch64 TLS INITIAL EXEC relocation.
7036 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7038 AArch64 TLS INITIAL EXEC relocation.
7040 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7042 AArch64 TLS INITIAL EXEC relocation.
7044 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7046 bit[23:12] of byte offset to module TLS base address.
7048 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7050 Unsigned 12 bit byte offset to module TLS base address.
7052 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7054 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7056 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7058 Unsigned 12 bit byte offset to global offset table entry for a symbols
7059 tls_index structure. Used in conjunction with
7060 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7062 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7064 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7067 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7069 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7071 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7073 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7076 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7078 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7080 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7082 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7085 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7087 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7089 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7091 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7094 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7096 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7098 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7100 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7103 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7105 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7107 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7109 bit[15:0] of byte offset to module TLS base address.
7111 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7113 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7115 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7117 bit[31:16] of byte offset to module TLS base address.
7119 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7121 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7123 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7125 bit[47:32] of byte offset to module TLS base address.
7127 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7129 AArch64 TLS LOCAL EXEC relocation.
7131 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7133 AArch64 TLS LOCAL EXEC relocation.
7135 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7137 AArch64 TLS LOCAL EXEC relocation.
7139 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7141 AArch64 TLS LOCAL EXEC relocation.
7143 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7145 AArch64 TLS LOCAL EXEC relocation.
7147 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7149 AArch64 TLS LOCAL EXEC relocation.
7151 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7153 AArch64 TLS LOCAL EXEC relocation.
7155 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7157 AArch64 TLS LOCAL EXEC relocation.
7159 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7161 AArch64 TLS DESC relocation.
7163 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7165 AArch64 TLS DESC relocation.
7167 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7169 AArch64 TLS DESC relocation.
7171 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
7173 AArch64 TLS DESC relocation.
7175 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7177 AArch64 TLS DESC relocation.
7179 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
7181 AArch64 TLS DESC relocation.
7183 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7185 AArch64 TLS DESC relocation.
7187 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7189 AArch64 TLS DESC relocation.
7191 BFD_RELOC_AARCH64_TLSDESC_LDR
7193 AArch64 TLS DESC relocation.
7195 BFD_RELOC_AARCH64_TLSDESC_ADD
7197 AArch64 TLS DESC relocation.
7199 BFD_RELOC_AARCH64_TLSDESC_CALL
7201 AArch64 TLS DESC relocation.
7203 BFD_RELOC_AARCH64_COPY
7205 AArch64 TLS relocation.
7207 BFD_RELOC_AARCH64_GLOB_DAT
7209 AArch64 TLS relocation.
7211 BFD_RELOC_AARCH64_JUMP_SLOT
7213 AArch64 TLS relocation.
7215 BFD_RELOC_AARCH64_RELATIVE
7217 AArch64 TLS relocation.
7219 BFD_RELOC_AARCH64_TLS_DTPMOD
7221 AArch64 TLS relocation.
7223 BFD_RELOC_AARCH64_TLS_DTPREL
7225 AArch64 TLS relocation.
7227 BFD_RELOC_AARCH64_TLS_TPREL
7229 AArch64 TLS relocation.
7231 BFD_RELOC_AARCH64_TLSDESC
7233 AArch64 TLS relocation.
7235 BFD_RELOC_AARCH64_IRELATIVE
7237 AArch64 support for STT_GNU_IFUNC.
7239 BFD_RELOC_AARCH64_RELOC_END
7241 AArch64 pseudo relocation code to mark the end of the AArch64
7242 relocation enumerators that have direct mapping to ELF reloc codes.
7243 There are a few more enumerators after this one; those are mainly
7244 used by the AArch64 assembler for the internal fixup or to select
7245 one of the above enumerators.
7247 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7249 AArch64 pseudo relocation code to be used internally by the AArch64
7250 assembler and not (currently) written to any object files.
7252 BFD_RELOC_AARCH64_LDST_LO12
7254 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7255 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7257 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7259 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7260 used internally by the AArch64 assembler and not (currently) written to
7263 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7265 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7267 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7269 AArch64 pseudo relocation code to be used internally by the AArch64
7270 assembler and not (currently) written to any object files.
7272 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7274 AArch64 pseudo relocation code to be used internally by the AArch64
7275 assembler and not (currently) written to any object files.
7277 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7279 AArch64 pseudo relocation code to be used internally by the AArch64
7280 assembler and not (currently) written to any object files.
7282 BFD_RELOC_TILEPRO_COPY
7284 BFD_RELOC_TILEPRO_GLOB_DAT
7286 BFD_RELOC_TILEPRO_JMP_SLOT
7288 BFD_RELOC_TILEPRO_RELATIVE
7290 BFD_RELOC_TILEPRO_BROFF_X1
7292 BFD_RELOC_TILEPRO_JOFFLONG_X1
7294 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7296 BFD_RELOC_TILEPRO_IMM8_X0
7298 BFD_RELOC_TILEPRO_IMM8_Y0
7300 BFD_RELOC_TILEPRO_IMM8_X1
7302 BFD_RELOC_TILEPRO_IMM8_Y1
7304 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7306 BFD_RELOC_TILEPRO_MT_IMM15_X1
7308 BFD_RELOC_TILEPRO_MF_IMM15_X1
7310 BFD_RELOC_TILEPRO_IMM16_X0
7312 BFD_RELOC_TILEPRO_IMM16_X1
7314 BFD_RELOC_TILEPRO_IMM16_X0_LO
7316 BFD_RELOC_TILEPRO_IMM16_X1_LO
7318 BFD_RELOC_TILEPRO_IMM16_X0_HI
7320 BFD_RELOC_TILEPRO_IMM16_X1_HI
7322 BFD_RELOC_TILEPRO_IMM16_X0_HA
7324 BFD_RELOC_TILEPRO_IMM16_X1_HA
7326 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7328 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7330 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7332 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7334 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7336 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7338 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7340 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7342 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7344 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7346 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7348 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7350 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7352 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7354 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7356 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7358 BFD_RELOC_TILEPRO_MMSTART_X0
7360 BFD_RELOC_TILEPRO_MMEND_X0
7362 BFD_RELOC_TILEPRO_MMSTART_X1
7364 BFD_RELOC_TILEPRO_MMEND_X1
7366 BFD_RELOC_TILEPRO_SHAMT_X0
7368 BFD_RELOC_TILEPRO_SHAMT_X1
7370 BFD_RELOC_TILEPRO_SHAMT_Y0
7372 BFD_RELOC_TILEPRO_SHAMT_Y1
7374 BFD_RELOC_TILEPRO_TLS_GD_CALL
7376 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7378 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7380 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7382 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7384 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7386 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7388 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7390 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7392 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7394 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7396 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7398 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7400 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7402 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7404 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7406 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7408 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7410 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7412 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7414 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7416 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7418 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7420 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7422 BFD_RELOC_TILEPRO_TLS_TPOFF32
7424 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7426 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7428 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7430 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7432 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7434 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7436 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7438 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7440 Tilera TILEPro Relocations.
7442 BFD_RELOC_TILEGX_HW0
7444 BFD_RELOC_TILEGX_HW1
7446 BFD_RELOC_TILEGX_HW2
7448 BFD_RELOC_TILEGX_HW3
7450 BFD_RELOC_TILEGX_HW0_LAST
7452 BFD_RELOC_TILEGX_HW1_LAST
7454 BFD_RELOC_TILEGX_HW2_LAST
7456 BFD_RELOC_TILEGX_COPY
7458 BFD_RELOC_TILEGX_GLOB_DAT
7460 BFD_RELOC_TILEGX_JMP_SLOT
7462 BFD_RELOC_TILEGX_RELATIVE
7464 BFD_RELOC_TILEGX_BROFF_X1
7466 BFD_RELOC_TILEGX_JUMPOFF_X1
7468 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7470 BFD_RELOC_TILEGX_IMM8_X0
7472 BFD_RELOC_TILEGX_IMM8_Y0
7474 BFD_RELOC_TILEGX_IMM8_X1
7476 BFD_RELOC_TILEGX_IMM8_Y1
7478 BFD_RELOC_TILEGX_DEST_IMM8_X1
7480 BFD_RELOC_TILEGX_MT_IMM14_X1
7482 BFD_RELOC_TILEGX_MF_IMM14_X1
7484 BFD_RELOC_TILEGX_MMSTART_X0
7486 BFD_RELOC_TILEGX_MMEND_X0
7488 BFD_RELOC_TILEGX_SHAMT_X0
7490 BFD_RELOC_TILEGX_SHAMT_X1
7492 BFD_RELOC_TILEGX_SHAMT_Y0
7494 BFD_RELOC_TILEGX_SHAMT_Y1
7496 BFD_RELOC_TILEGX_IMM16_X0_HW0
7498 BFD_RELOC_TILEGX_IMM16_X1_HW0
7500 BFD_RELOC_TILEGX_IMM16_X0_HW1
7502 BFD_RELOC_TILEGX_IMM16_X1_HW1
7504 BFD_RELOC_TILEGX_IMM16_X0_HW2
7506 BFD_RELOC_TILEGX_IMM16_X1_HW2
7508 BFD_RELOC_TILEGX_IMM16_X0_HW3
7510 BFD_RELOC_TILEGX_IMM16_X1_HW3
7512 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7514 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7516 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7518 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7520 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7522 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7524 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7526 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7528 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7530 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7532 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7534 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7536 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7538 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7540 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7542 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7544 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7546 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7548 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7550 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7552 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7554 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7556 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7558 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7560 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7562 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7564 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7566 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7568 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7570 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7572 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7574 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7576 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7578 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7580 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7582 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7584 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7586 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7588 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7590 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7592 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7594 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7596 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7598 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7600 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7602 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7604 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7606 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7608 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7610 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7612 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7614 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7616 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7618 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7620 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7622 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7624 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7626 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7628 BFD_RELOC_TILEGX_TLS_DTPMOD64
7630 BFD_RELOC_TILEGX_TLS_DTPOFF64
7632 BFD_RELOC_TILEGX_TLS_TPOFF64
7634 BFD_RELOC_TILEGX_TLS_DTPMOD32
7636 BFD_RELOC_TILEGX_TLS_DTPOFF32
7638 BFD_RELOC_TILEGX_TLS_TPOFF32
7640 BFD_RELOC_TILEGX_TLS_GD_CALL
7642 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7644 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7646 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7648 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7650 BFD_RELOC_TILEGX_TLS_IE_LOAD
7652 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7654 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7656 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7658 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7660 Tilera TILE-Gx Relocations.
7663 BFD_RELOC_EPIPHANY_SIMM8
7665 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7667 BFD_RELOC_EPIPHANY_SIMM24
7669 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7671 BFD_RELOC_EPIPHANY_HIGH
7673 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7675 BFD_RELOC_EPIPHANY_LOW
7677 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7679 BFD_RELOC_EPIPHANY_SIMM11
7681 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7683 BFD_RELOC_EPIPHANY_IMM11
7685 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7687 BFD_RELOC_EPIPHANY_IMM8
7689 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7692 BFD_RELOC_VISIUM_HI16
7694 BFD_RELOC_VISIUM_LO16
7696 BFD_RELOC_VISIUM_IM16
7698 BFD_RELOC_VISIUM_REL16
7700 BFD_RELOC_VISIUM_HI16_PCREL
7702 BFD_RELOC_VISIUM_LO16_PCREL
7704 BFD_RELOC_VISIUM_IM16_PCREL
7712 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7717 bfd_reloc_type_lookup
7718 bfd_reloc_name_lookup
7721 reloc_howto_type *bfd_reloc_type_lookup
7722 (bfd *abfd, bfd_reloc_code_real_type code);
7723 reloc_howto_type *bfd_reloc_name_lookup
7724 (bfd *abfd, const char *reloc_name);
7727 Return a pointer to a howto structure which, when
7728 invoked, will perform the relocation @var{code} on data from the
7734 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7736 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7740 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7742 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7745 static reloc_howto_type bfd_howto_32
=
7746 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7750 bfd_default_reloc_type_lookup
7753 reloc_howto_type *bfd_default_reloc_type_lookup
7754 (bfd *abfd, bfd_reloc_code_real_type code);
7757 Provides a default relocation lookup routine for any architecture.
7762 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7766 case BFD_RELOC_CTOR
:
7767 /* The type of reloc used in a ctor, which will be as wide as the
7768 address - so either a 64, 32, or 16 bitter. */
7769 switch (bfd_arch_bits_per_address (abfd
))
7774 return &bfd_howto_32
;
7788 bfd_get_reloc_code_name
7791 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7794 Provides a printable name for the supplied relocation code.
7795 Useful mainly for printing error messages.
7799 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7801 if (code
> BFD_RELOC_UNUSED
)
7803 return bfd_reloc_code_real_names
[code
];
7808 bfd_generic_relax_section
7811 bfd_boolean bfd_generic_relax_section
7814 struct bfd_link_info *,
7818 Provides default handling for relaxing for back ends which
7823 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
7824 asection
*section ATTRIBUTE_UNUSED
,
7825 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
7828 if (bfd_link_relocatable (link_info
))
7829 (*link_info
->callbacks
->einfo
)
7830 (_("%P%F: --relax and -r may not be used together\n"));
7838 bfd_generic_gc_sections
7841 bfd_boolean bfd_generic_gc_sections
7842 (bfd *, struct bfd_link_info *);
7845 Provides default handling for relaxing for back ends which
7846 don't do section gc -- i.e., does nothing.
7850 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7851 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
7858 bfd_generic_lookup_section_flags
7861 bfd_boolean bfd_generic_lookup_section_flags
7862 (struct bfd_link_info *, struct flag_info *, asection *);
7865 Provides default handling for section flags lookup
7866 -- i.e., does nothing.
7867 Returns FALSE if the section should be omitted, otherwise TRUE.
7871 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
7872 struct flag_info
*flaginfo
,
7873 asection
*section ATTRIBUTE_UNUSED
)
7875 if (flaginfo
!= NULL
)
7877 (*_bfd_error_handler
) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7885 bfd_generic_merge_sections
7888 bfd_boolean bfd_generic_merge_sections
7889 (bfd *, struct bfd_link_info *);
7892 Provides default handling for SEC_MERGE section merging for back ends
7893 which don't have SEC_MERGE support -- i.e., does nothing.
7897 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7898 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
7905 bfd_generic_get_relocated_section_contents
7908 bfd_byte *bfd_generic_get_relocated_section_contents
7910 struct bfd_link_info *link_info,
7911 struct bfd_link_order *link_order,
7913 bfd_boolean relocatable,
7917 Provides default handling of relocation effort for back ends
7918 which can't be bothered to do it efficiently.
7923 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
7924 struct bfd_link_info
*link_info
,
7925 struct bfd_link_order
*link_order
,
7927 bfd_boolean relocatable
,
7930 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
7931 asection
*input_section
= link_order
->u
.indirect
.section
;
7933 arelent
**reloc_vector
;
7936 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
7940 /* Read in the section. */
7941 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
7944 if (reloc_size
== 0)
7947 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
7948 if (reloc_vector
== NULL
)
7951 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
7955 if (reloc_count
< 0)
7958 if (reloc_count
> 0)
7962 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
7964 char *error_message
= NULL
;
7966 bfd_reloc_status_type r
;
7968 symbol
= *(*parent
)->sym_ptr_ptr
;
7969 /* PR ld/19628: A specially crafted input file
7970 can result in a NULL symbol pointer here. */
7973 link_info
->callbacks
->einfo
7974 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
7975 abfd
, input_section
, (* parent
)->address
);
7979 if (symbol
->section
&& discarded_section (symbol
->section
))
7982 static reloc_howto_type none_howto
7983 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
7984 "unused", FALSE
, 0, 0, FALSE
);
7986 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
7987 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
7989 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
7990 (*parent
)->addend
= 0;
7991 (*parent
)->howto
= &none_howto
;
7995 r
= bfd_perform_relocation (input_bfd
,
7999 relocatable
? abfd
: NULL
,
8004 asection
*os
= input_section
->output_section
;
8006 /* A partial link, so keep the relocs. */
8007 os
->orelocation
[os
->reloc_count
] = *parent
;
8011 if (r
!= bfd_reloc_ok
)
8015 case bfd_reloc_undefined
:
8016 (*link_info
->callbacks
->undefined_symbol
)
8017 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8018 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8020 case bfd_reloc_dangerous
:
8021 BFD_ASSERT (error_message
!= NULL
);
8022 (*link_info
->callbacks
->reloc_dangerous
)
8023 (link_info
, error_message
,
8024 input_bfd
, input_section
, (*parent
)->address
);
8026 case bfd_reloc_overflow
:
8027 (*link_info
->callbacks
->reloc_overflow
)
8029 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8030 (*parent
)->howto
->name
, (*parent
)->addend
,
8031 input_bfd
, input_section
, (*parent
)->address
);
8033 case bfd_reloc_outofrange
:
8035 This error can result when processing some partially
8036 complete binaries. Do not abort, but issue an error
8038 link_info
->callbacks
->einfo
8039 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8040 abfd
, input_section
, * parent
);
8043 case bfd_reloc_notsupported
:
8045 This error can result when processing a corrupt binary.
8046 Do not abort. Issue an error message instead. */
8047 link_info
->callbacks
->einfo
8048 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8049 abfd
, input_section
, * parent
);
8053 /* PR 17512; file: 90c2a92e.
8054 Report unexpected results, without aborting. */
8055 link_info
->callbacks
->einfo
8056 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8057 abfd
, input_section
, * parent
, r
);
8065 free (reloc_vector
);
8069 free (reloc_vector
);