1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2020 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The encoded size of the item to be relocated. This is *not* a
291 . power-of-two measure. Use bfd_get_reloc_size to find the size
292 . of the item in bytes. *}
293 . unsigned int size:3;
295 . {* The number of bits in the field to be relocated. This is used
296 . when doing overflow checking. *}
297 . unsigned int bitsize:7;
299 . {* The value the final relocation is shifted right by. This drops
300 . unwanted data from the relocation. *}
301 . unsigned int rightshift:6;
303 . {* The bit position of the reloc value in the destination.
304 . The relocated value is left shifted by this amount. *}
305 . unsigned int bitpos:6;
307 . {* What type of overflow error should be checked for when
309 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
311 . {* The relocation value should be negated before applying. *}
312 . unsigned int negate:1;
314 . {* The relocation is relative to the item being relocated. *}
315 . unsigned int pc_relative:1;
317 . {* Some formats record a relocation addend in the section contents
318 . rather than with the relocation. For ELF formats this is the
319 . distinction between USE_REL and USE_RELA (though the code checks
320 . for USE_REL == 1/0). The value of this field is TRUE if the
321 . addend is recorded with the section contents; when performing a
322 . partial link (ld -r) the section contents (the data) will be
323 . modified. The value of this field is FALSE if addends are
324 . recorded with the relocation (in arelent.addend); when performing
325 . a partial link the relocation will be modified.
326 . All relocations for all ELF USE_RELA targets should set this field
327 . to FALSE (values of TRUE should be looked on with suspicion).
328 . However, the converse is not true: not all relocations of all ELF
329 . USE_REL targets set this field to TRUE. Why this is so is peculiar
330 . to each particular target. For relocs that aren't used in partial
331 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
332 . unsigned int partial_inplace:1;
334 . {* When some formats create PC relative instructions, they leave
335 . the value of the pc of the place being relocated in the offset
336 . slot of the instruction, so that a PC relative relocation can
337 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
338 . Some formats leave the displacement part of an instruction
339 . empty (e.g., ELF); this flag signals the fact. *}
340 . unsigned int pcrel_offset:1;
342 . {* src_mask selects the part of the instruction (or data) to be used
343 . in the relocation sum. If the target relocations don't have an
344 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
345 . dst_mask to extract the addend from the section contents. If
346 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
347 . field should normally be zero. Non-zero values for ELF USE_RELA
348 . targets should be viewed with suspicion as normally the value in
349 . the dst_mask part of the section contents should be ignored. *}
352 . {* dst_mask selects which parts of the instruction (or data) are
353 . replaced with a relocated value. *}
356 . {* If this field is non null, then the supplied function is
357 . called rather than the normal function. This allows really
358 . strange relocation methods to be accommodated. *}
359 . bfd_reloc_status_type (*special_function)
360 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
363 . {* The textual name of the relocation type. *}
374 The HOWTO macro fills in a reloc_howto_type (a typedef for
375 const struct reloc_howto_struct).
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
387 . NULL, FALSE, 0, 0, FALSE)
396 unsigned int bfd_get_reloc_size (reloc_howto_type *);
399 For a reloc_howto_type that operates on a fixed number of bytes,
400 this returns the number of bytes operated on.
404 bfd_get_reloc_size (reloc_howto_type
*howto
)
424 How relocs are tied together in an <<asection>>:
426 .typedef struct relent_chain
429 . struct relent_chain *next;
435 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
436 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
443 bfd_reloc_status_type bfd_check_overflow
444 (enum complain_overflow how,
445 unsigned int bitsize,
446 unsigned int rightshift,
447 unsigned int addrsize,
451 Perform overflow checking on @var{relocation} which has
452 @var{bitsize} significant bits and will be shifted right by
453 @var{rightshift} bits, on a machine with addresses containing
454 @var{addrsize} significant bits. The result is either of
455 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
459 bfd_reloc_status_type
460 bfd_check_overflow (enum complain_overflow how
,
461 unsigned int bitsize
,
462 unsigned int rightshift
,
463 unsigned int addrsize
,
466 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
467 bfd_reloc_status_type flag
= bfd_reloc_ok
;
469 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
470 we'll be permissive: extra bits in the field mask will
471 automatically extend the address mask for purposes of the
473 fieldmask
= N_ONES (bitsize
);
474 signmask
= ~fieldmask
;
475 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
476 a
= (relocation
& addrmask
) >> rightshift
;
480 case complain_overflow_dont
:
483 case complain_overflow_signed
:
484 /* If any sign bits are set, all sign bits must be set. That
485 is, A must be a valid negative address after shifting. */
486 signmask
= ~ (fieldmask
>> 1);
489 case complain_overflow_bitfield
:
490 /* Bitfields are sometimes signed, sometimes unsigned. We
491 explicitly allow an address wrap too, which means a bitfield
492 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
493 if the value has some, but not all, bits set outside the
496 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
497 flag
= bfd_reloc_overflow
;
500 case complain_overflow_unsigned
:
501 /* We have an overflow if the address does not fit in the field. */
502 if ((a
& signmask
) != 0)
503 flag
= bfd_reloc_overflow
;
515 bfd_reloc_offset_in_range
518 bfd_boolean bfd_reloc_offset_in_range
519 (reloc_howto_type *howto,
522 bfd_size_type offset);
525 Returns TRUE if the reloc described by @var{HOWTO} can be
526 applied at @var{OFFSET} octets in @var{SECTION}.
530 /* HOWTO describes a relocation, at offset OCTET. Return whether the
531 relocation field is within SECTION of ABFD. */
534 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
539 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
540 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
542 /* The reloc field must be contained entirely within the section.
543 Allow zero length fields (marker relocs or NONE relocs where no
544 relocation will be performed) at the end of the section. */
545 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
548 /* Read and return the section contents at DATA converted to a host
549 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
552 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
557 return bfd_get_8 (abfd
, data
);
560 return bfd_get_16 (abfd
, data
);
563 return bfd_get_32 (abfd
, data
);
570 return bfd_get_64 (abfd
, data
);
574 return bfd_get_24 (abfd
, data
);
582 /* Convert VAL to target format and write to DATA. The number of
583 bytes written is given by the HOWTO. */
586 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
591 bfd_put_8 (abfd
, val
, data
);
595 bfd_put_16 (abfd
, val
, data
);
599 bfd_put_32 (abfd
, val
, data
);
607 bfd_put_64 (abfd
, val
, data
);
612 bfd_put_24 (abfd
, val
, data
);
620 /* Apply RELOCATION value to target bytes at DATA, according to
624 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
627 bfd_vma val
= read_reloc (abfd
, data
, howto
);
630 relocation
= -relocation
;
632 val
= ((val
& ~howto
->dst_mask
)
633 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
635 write_reloc (abfd
, val
, data
, howto
);
640 bfd_perform_relocation
643 bfd_reloc_status_type bfd_perform_relocation
645 arelent *reloc_entry,
647 asection *input_section,
649 char **error_message);
652 If @var{output_bfd} is supplied to this function, the
653 generated image will be relocatable; the relocations are
654 copied to the output file after they have been changed to
655 reflect the new state of the world. There are two ways of
656 reflecting the results of partial linkage in an output file:
657 by modifying the output data in place, and by modifying the
658 relocation record. Some native formats (e.g., basic a.out and
659 basic coff) have no way of specifying an addend in the
660 relocation type, so the addend has to go in the output data.
661 This is no big deal since in these formats the output data
662 slot will always be big enough for the addend. Complex reloc
663 types with addends were invented to solve just this problem.
664 The @var{error_message} argument is set to an error message if
665 this return @code{bfd_reloc_dangerous}.
669 bfd_reloc_status_type
670 bfd_perform_relocation (bfd
*abfd
,
671 arelent
*reloc_entry
,
673 asection
*input_section
,
675 char **error_message
)
678 bfd_reloc_status_type flag
= bfd_reloc_ok
;
679 bfd_size_type octets
;
680 bfd_vma output_base
= 0;
681 reloc_howto_type
*howto
= reloc_entry
->howto
;
682 asection
*reloc_target_output_section
;
685 symbol
= *(reloc_entry
->sym_ptr_ptr
);
687 /* If we are not producing relocatable output, return an error if
688 the symbol is not defined. An undefined weak symbol is
689 considered to have a value of zero (SVR4 ABI, p. 4-27). */
690 if (bfd_is_und_section (symbol
->section
)
691 && (symbol
->flags
& BSF_WEAK
) == 0
692 && output_bfd
== NULL
)
693 flag
= bfd_reloc_undefined
;
695 /* If there is a function supplied to handle this relocation type,
696 call it. It'll return `bfd_reloc_continue' if further processing
698 if (howto
&& howto
->special_function
)
700 bfd_reloc_status_type cont
;
702 /* Note - we do not call bfd_reloc_offset_in_range here as the
703 reloc_entry->address field might actually be valid for the
704 backend concerned. It is up to the special_function itself
705 to call bfd_reloc_offset_in_range if needed. */
706 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
707 input_section
, output_bfd
,
709 if (cont
!= bfd_reloc_continue
)
713 if (bfd_is_abs_section (symbol
->section
)
714 && output_bfd
!= NULL
)
716 reloc_entry
->address
+= input_section
->output_offset
;
720 /* PR 17512: file: 0f67f69d. */
722 return bfd_reloc_undefined
;
724 /* Is the address of the relocation really within the section? */
725 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
726 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
727 return bfd_reloc_outofrange
;
729 /* Work out which section the relocation is targeted at and the
730 initial relocation command value. */
732 /* Get symbol value. (Common symbols are special.) */
733 if (bfd_is_com_section (symbol
->section
))
736 relocation
= symbol
->value
;
738 reloc_target_output_section
= symbol
->section
->output_section
;
740 /* Convert input-section-relative symbol value to absolute. */
741 if ((output_bfd
&& ! howto
->partial_inplace
)
742 || reloc_target_output_section
== NULL
)
745 output_base
= reloc_target_output_section
->vma
;
747 output_base
+= symbol
->section
->output_offset
;
749 /* If symbol addresses are in octets, convert to bytes. */
750 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
751 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
752 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
754 relocation
+= output_base
;
756 /* Add in supplied addend. */
757 relocation
+= reloc_entry
->addend
;
759 /* Here the variable relocation holds the final address of the
760 symbol we are relocating against, plus any addend. */
762 if (howto
->pc_relative
)
764 /* This is a PC relative relocation. We want to set RELOCATION
765 to the distance between the address of the symbol and the
766 location. RELOCATION is already the address of the symbol.
768 We start by subtracting the address of the section containing
771 If pcrel_offset is set, we must further subtract the position
772 of the location within the section. Some targets arrange for
773 the addend to be the negative of the position of the location
774 within the section; for example, i386-aout does this. For
775 i386-aout, pcrel_offset is FALSE. Some other targets do not
776 include the position of the location; for example, ELF.
777 For those targets, pcrel_offset is TRUE.
779 If we are producing relocatable output, then we must ensure
780 that this reloc will be correctly computed when the final
781 relocation is done. If pcrel_offset is FALSE we want to wind
782 up with the negative of the location within the section,
783 which means we must adjust the existing addend by the change
784 in the location within the section. If pcrel_offset is TRUE
785 we do not want to adjust the existing addend at all.
787 FIXME: This seems logical to me, but for the case of
788 producing relocatable output it is not what the code
789 actually does. I don't want to change it, because it seems
790 far too likely that something will break. */
793 input_section
->output_section
->vma
+ input_section
->output_offset
;
795 if (howto
->pcrel_offset
)
796 relocation
-= reloc_entry
->address
;
799 if (output_bfd
!= NULL
)
801 if (! howto
->partial_inplace
)
803 /* This is a partial relocation, and we want to apply the relocation
804 to the reloc entry rather than the raw data. Modify the reloc
805 inplace to reflect what we now know. */
806 reloc_entry
->addend
= relocation
;
807 reloc_entry
->address
+= input_section
->output_offset
;
812 /* This is a partial relocation, but inplace, so modify the
815 If we've relocated with a symbol with a section, change
816 into a ref to the section belonging to the symbol. */
818 reloc_entry
->address
+= input_section
->output_offset
;
821 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
822 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
823 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
825 /* For m68k-coff, the addend was being subtracted twice during
826 relocation with -r. Removing the line below this comment
827 fixes that problem; see PR 2953.
829 However, Ian wrote the following, regarding removing the line below,
830 which explains why it is still enabled: --djm
832 If you put a patch like that into BFD you need to check all the COFF
833 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
834 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
835 problem in a different way. There may very well be a reason that the
836 code works as it does.
838 Hmmm. The first obvious point is that bfd_perform_relocation should
839 not have any tests that depend upon the flavour. It's seem like
840 entirely the wrong place for such a thing. The second obvious point
841 is that the current code ignores the reloc addend when producing
842 relocatable output for COFF. That's peculiar. In fact, I really
843 have no idea what the point of the line you want to remove is.
845 A typical COFF reloc subtracts the old value of the symbol and adds in
846 the new value to the location in the object file (if it's a pc
847 relative reloc it adds the difference between the symbol value and the
848 location). When relocating we need to preserve that property.
850 BFD handles this by setting the addend to the negative of the old
851 value of the symbol. Unfortunately it handles common symbols in a
852 non-standard way (it doesn't subtract the old value) but that's a
853 different story (we can't change it without losing backward
854 compatibility with old object files) (coff-i386 does subtract the old
855 value, to be compatible with existing coff-i386 targets, like SCO).
857 So everything works fine when not producing relocatable output. When
858 we are producing relocatable output, logically we should do exactly
859 what we do when not producing relocatable output. Therefore, your
860 patch is correct. In fact, it should probably always just set
861 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
862 add the value into the object file. This won't hurt the COFF code,
863 which doesn't use the addend; I'm not sure what it will do to other
864 formats (the thing to check for would be whether any formats both use
865 the addend and set partial_inplace).
867 When I wanted to make coff-i386 produce relocatable output, I ran
868 into the problem that you are running into: I wanted to remove that
869 line. Rather than risk it, I made the coff-i386 relocs use a special
870 function; it's coff_i386_reloc in coff-i386.c. The function
871 specifically adds the addend field into the object file, knowing that
872 bfd_perform_relocation is not going to. If you remove that line, then
873 coff-i386.c will wind up adding the addend field in twice. It's
874 trivial to fix; it just needs to be done.
876 The problem with removing the line is just that it may break some
877 working code. With BFD it's hard to be sure of anything. The right
878 way to deal with this is simply to build and test at least all the
879 supported COFF targets. It should be straightforward if time and disk
880 space consuming. For each target:
882 2) generate some executable, and link it using -r (I would
883 probably use paranoia.o and link against newlib/libc.a, which
884 for all the supported targets would be available in
885 /usr/cygnus/progressive/H-host/target/lib/libc.a).
886 3) make the change to reloc.c
887 4) rebuild the linker
889 6) if the resulting object files are the same, you have at least
891 7) if they are different you have to figure out which version is
894 relocation
-= reloc_entry
->addend
;
895 reloc_entry
->addend
= 0;
899 reloc_entry
->addend
= relocation
;
904 /* FIXME: This overflow checking is incomplete, because the value
905 might have overflowed before we get here. For a correct check we
906 need to compute the value in a size larger than bitsize, but we
907 can't reasonably do that for a reloc the same size as a host
909 FIXME: We should also do overflow checking on the result after
910 adding in the value contained in the object file. */
911 if (howto
->complain_on_overflow
!= complain_overflow_dont
912 && flag
== bfd_reloc_ok
)
913 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
916 bfd_arch_bits_per_address (abfd
),
919 /* Either we are relocating all the way, or we don't want to apply
920 the relocation to the reloc entry (probably because there isn't
921 any room in the output format to describe addends to relocs). */
923 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
924 (OSF version 1.3, compiler version 3.11). It miscompiles the
938 x <<= (unsigned long) s.i0;
942 printf ("succeeded (%lx)\n", x);
946 relocation
>>= (bfd_vma
) howto
->rightshift
;
948 /* Shift everything up to where it's going to be used. */
949 relocation
<<= (bfd_vma
) howto
->bitpos
;
951 /* Wait for the day when all have the mask in them. */
954 i instruction to be left alone
955 o offset within instruction
956 r relocation offset to apply
965 (( i i i i i o o o o o from bfd_get<size>
966 and S S S S S) to get the size offset we want
967 + r r r r r r r r r r) to get the final value to place
968 and D D D D D to chop to right size
969 -----------------------
972 ( i i i i i o o o o o from bfd_get<size>
973 and N N N N N ) get instruction
974 -----------------------
980 -----------------------
981 = R R R R R R R R R R put into bfd_put<size>
984 data
= (bfd_byte
*) data
+ octets
;
985 apply_reloc (abfd
, data
, howto
, relocation
);
991 bfd_install_relocation
994 bfd_reloc_status_type bfd_install_relocation
996 arelent *reloc_entry,
997 void *data, bfd_vma data_start,
998 asection *input_section,
999 char **error_message);
1002 This looks remarkably like <<bfd_perform_relocation>>, except it
1003 does not expect that the section contents have been filled in.
1004 I.e., it's suitable for use when creating, rather than applying
1007 For now, this function should be considered reserved for the
1011 bfd_reloc_status_type
1012 bfd_install_relocation (bfd
*abfd
,
1013 arelent
*reloc_entry
,
1015 bfd_vma data_start_offset
,
1016 asection
*input_section
,
1017 char **error_message
)
1020 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1021 bfd_size_type octets
;
1022 bfd_vma output_base
= 0;
1023 reloc_howto_type
*howto
= reloc_entry
->howto
;
1024 asection
*reloc_target_output_section
;
1028 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1030 /* If there is a function supplied to handle this relocation type,
1031 call it. It'll return `bfd_reloc_continue' if further processing
1033 if (howto
&& howto
->special_function
)
1035 bfd_reloc_status_type cont
;
1037 /* Note - we do not call bfd_reloc_offset_in_range here as the
1038 reloc_entry->address field might actually be valid for the
1039 backend concerned. It is up to the special_function itself
1040 to call bfd_reloc_offset_in_range if needed. */
1041 /* XXX - The special_function calls haven't been fixed up to deal
1042 with creating new relocations and section contents. */
1043 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1044 /* XXX - Non-portable! */
1045 ((bfd_byte
*) data_start
1046 - data_start_offset
),
1047 input_section
, abfd
, error_message
);
1048 if (cont
!= bfd_reloc_continue
)
1052 if (bfd_is_abs_section (symbol
->section
))
1054 reloc_entry
->address
+= input_section
->output_offset
;
1055 return bfd_reloc_ok
;
1058 /* No need to check for howto != NULL if !bfd_is_abs_section as
1059 it will have been checked in `bfd_perform_relocation already'. */
1061 /* Is the address of the relocation really within the section? */
1062 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1063 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1064 return bfd_reloc_outofrange
;
1066 /* Work out which section the relocation is targeted at and the
1067 initial relocation command value. */
1069 /* Get symbol value. (Common symbols are special.) */
1070 if (bfd_is_com_section (symbol
->section
))
1073 relocation
= symbol
->value
;
1075 reloc_target_output_section
= symbol
->section
->output_section
;
1077 /* Convert input-section-relative symbol value to absolute. */
1078 if (! howto
->partial_inplace
)
1081 output_base
= reloc_target_output_section
->vma
;
1083 output_base
+= symbol
->section
->output_offset
;
1085 /* If symbol addresses are in octets, convert to bytes. */
1086 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1087 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1088 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1090 relocation
+= output_base
;
1092 /* Add in supplied addend. */
1093 relocation
+= reloc_entry
->addend
;
1095 /* Here the variable relocation holds the final address of the
1096 symbol we are relocating against, plus any addend. */
1098 if (howto
->pc_relative
)
1100 /* This is a PC relative relocation. We want to set RELOCATION
1101 to the distance between the address of the symbol and the
1102 location. RELOCATION is already the address of the symbol.
1104 We start by subtracting the address of the section containing
1107 If pcrel_offset is set, we must further subtract the position
1108 of the location within the section. Some targets arrange for
1109 the addend to be the negative of the position of the location
1110 within the section; for example, i386-aout does this. For
1111 i386-aout, pcrel_offset is FALSE. Some other targets do not
1112 include the position of the location; for example, ELF.
1113 For those targets, pcrel_offset is TRUE.
1115 If we are producing relocatable output, then we must ensure
1116 that this reloc will be correctly computed when the final
1117 relocation is done. If pcrel_offset is FALSE we want to wind
1118 up with the negative of the location within the section,
1119 which means we must adjust the existing addend by the change
1120 in the location within the section. If pcrel_offset is TRUE
1121 we do not want to adjust the existing addend at all.
1123 FIXME: This seems logical to me, but for the case of
1124 producing relocatable output it is not what the code
1125 actually does. I don't want to change it, because it seems
1126 far too likely that something will break. */
1129 input_section
->output_section
->vma
+ input_section
->output_offset
;
1131 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1132 relocation
-= reloc_entry
->address
;
1135 if (! howto
->partial_inplace
)
1137 /* This is a partial relocation, and we want to apply the relocation
1138 to the reloc entry rather than the raw data. Modify the reloc
1139 inplace to reflect what we now know. */
1140 reloc_entry
->addend
= relocation
;
1141 reloc_entry
->address
+= input_section
->output_offset
;
1146 /* This is a partial relocation, but inplace, so modify the
1149 If we've relocated with a symbol with a section, change
1150 into a ref to the section belonging to the symbol. */
1151 reloc_entry
->address
+= input_section
->output_offset
;
1154 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1155 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1156 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1159 /* For m68k-coff, the addend was being subtracted twice during
1160 relocation with -r. Removing the line below this comment
1161 fixes that problem; see PR 2953.
1163 However, Ian wrote the following, regarding removing the line below,
1164 which explains why it is still enabled: --djm
1166 If you put a patch like that into BFD you need to check all the COFF
1167 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1168 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1169 problem in a different way. There may very well be a reason that the
1170 code works as it does.
1172 Hmmm. The first obvious point is that bfd_install_relocation should
1173 not have any tests that depend upon the flavour. It's seem like
1174 entirely the wrong place for such a thing. The second obvious point
1175 is that the current code ignores the reloc addend when producing
1176 relocatable output for COFF. That's peculiar. In fact, I really
1177 have no idea what the point of the line you want to remove is.
1179 A typical COFF reloc subtracts the old value of the symbol and adds in
1180 the new value to the location in the object file (if it's a pc
1181 relative reloc it adds the difference between the symbol value and the
1182 location). When relocating we need to preserve that property.
1184 BFD handles this by setting the addend to the negative of the old
1185 value of the symbol. Unfortunately it handles common symbols in a
1186 non-standard way (it doesn't subtract the old value) but that's a
1187 different story (we can't change it without losing backward
1188 compatibility with old object files) (coff-i386 does subtract the old
1189 value, to be compatible with existing coff-i386 targets, like SCO).
1191 So everything works fine when not producing relocatable output. When
1192 we are producing relocatable output, logically we should do exactly
1193 what we do when not producing relocatable output. Therefore, your
1194 patch is correct. In fact, it should probably always just set
1195 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1196 add the value into the object file. This won't hurt the COFF code,
1197 which doesn't use the addend; I'm not sure what it will do to other
1198 formats (the thing to check for would be whether any formats both use
1199 the addend and set partial_inplace).
1201 When I wanted to make coff-i386 produce relocatable output, I ran
1202 into the problem that you are running into: I wanted to remove that
1203 line. Rather than risk it, I made the coff-i386 relocs use a special
1204 function; it's coff_i386_reloc in coff-i386.c. The function
1205 specifically adds the addend field into the object file, knowing that
1206 bfd_install_relocation is not going to. If you remove that line, then
1207 coff-i386.c will wind up adding the addend field in twice. It's
1208 trivial to fix; it just needs to be done.
1210 The problem with removing the line is just that it may break some
1211 working code. With BFD it's hard to be sure of anything. The right
1212 way to deal with this is simply to build and test at least all the
1213 supported COFF targets. It should be straightforward if time and disk
1214 space consuming. For each target:
1216 2) generate some executable, and link it using -r (I would
1217 probably use paranoia.o and link against newlib/libc.a, which
1218 for all the supported targets would be available in
1219 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1220 3) make the change to reloc.c
1221 4) rebuild the linker
1223 6) if the resulting object files are the same, you have at least
1225 7) if they are different you have to figure out which version is
1227 relocation
-= reloc_entry
->addend
;
1228 /* FIXME: There should be no target specific code here... */
1229 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1230 reloc_entry
->addend
= 0;
1234 reloc_entry
->addend
= relocation
;
1238 /* FIXME: This overflow checking is incomplete, because the value
1239 might have overflowed before we get here. For a correct check we
1240 need to compute the value in a size larger than bitsize, but we
1241 can't reasonably do that for a reloc the same size as a host
1243 FIXME: We should also do overflow checking on the result after
1244 adding in the value contained in the object file. */
1245 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1246 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1249 bfd_arch_bits_per_address (abfd
),
1252 /* Either we are relocating all the way, or we don't want to apply
1253 the relocation to the reloc entry (probably because there isn't
1254 any room in the output format to describe addends to relocs). */
1256 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1257 (OSF version 1.3, compiler version 3.11). It miscompiles the
1271 x <<= (unsigned long) s.i0;
1273 printf ("failed\n");
1275 printf ("succeeded (%lx)\n", x);
1279 relocation
>>= (bfd_vma
) howto
->rightshift
;
1281 /* Shift everything up to where it's going to be used. */
1282 relocation
<<= (bfd_vma
) howto
->bitpos
;
1284 /* Wait for the day when all have the mask in them. */
1287 i instruction to be left alone
1288 o offset within instruction
1289 r relocation offset to apply
1298 (( i i i i i o o o o o from bfd_get<size>
1299 and S S S S S) to get the size offset we want
1300 + r r r r r r r r r r) to get the final value to place
1301 and D D D D D to chop to right size
1302 -----------------------
1305 ( i i i i i o o o o o from bfd_get<size>
1306 and N N N N N ) get instruction
1307 -----------------------
1313 -----------------------
1314 = R R R R R R R R R R put into bfd_put<size>
1317 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1318 apply_reloc (abfd
, data
, howto
, relocation
);
1322 /* This relocation routine is used by some of the backend linkers.
1323 They do not construct asymbol or arelent structures, so there is no
1324 reason for them to use bfd_perform_relocation. Also,
1325 bfd_perform_relocation is so hacked up it is easier to write a new
1326 function than to try to deal with it.
1328 This routine does a final relocation. Whether it is useful for a
1329 relocatable link depends upon how the object format defines
1332 FIXME: This routine ignores any special_function in the HOWTO,
1333 since the existing special_function values have been written for
1334 bfd_perform_relocation.
1336 HOWTO is the reloc howto information.
1337 INPUT_BFD is the BFD which the reloc applies to.
1338 INPUT_SECTION is the section which the reloc applies to.
1339 CONTENTS is the contents of the section.
1340 ADDRESS is the address of the reloc within INPUT_SECTION.
1341 VALUE is the value of the symbol the reloc refers to.
1342 ADDEND is the addend of the reloc. */
1344 bfd_reloc_status_type
1345 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1347 asection
*input_section
,
1354 bfd_size_type octets
= (address
1355 * bfd_octets_per_byte (input_bfd
, input_section
));
1357 /* Sanity check the address. */
1358 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1359 return bfd_reloc_outofrange
;
1361 /* This function assumes that we are dealing with a basic relocation
1362 against a symbol. We want to compute the value of the symbol to
1363 relocate to. This is just VALUE, the value of the symbol, plus
1364 ADDEND, any addend associated with the reloc. */
1365 relocation
= value
+ addend
;
1367 /* If the relocation is PC relative, we want to set RELOCATION to
1368 the distance between the symbol (currently in RELOCATION) and the
1369 location we are relocating. Some targets (e.g., i386-aout)
1370 arrange for the contents of the section to be the negative of the
1371 offset of the location within the section; for such targets
1372 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1373 the contents of the section as zero; for such targets
1374 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1375 subtract out the offset of the location within the section (which
1376 is just ADDRESS). */
1377 if (howto
->pc_relative
)
1379 relocation
-= (input_section
->output_section
->vma
1380 + input_section
->output_offset
);
1381 if (howto
->pcrel_offset
)
1382 relocation
-= address
;
1385 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1389 /* Relocate a given location using a given value and howto. */
1391 bfd_reloc_status_type
1392 _bfd_relocate_contents (reloc_howto_type
*howto
,
1398 bfd_reloc_status_type flag
;
1399 unsigned int rightshift
= howto
->rightshift
;
1400 unsigned int bitpos
= howto
->bitpos
;
1403 relocation
= -relocation
;
1405 /* Get the value we are going to relocate. */
1406 x
= read_reloc (input_bfd
, location
, howto
);
1408 /* Check for overflow. FIXME: We may drop bits during the addition
1409 which we don't check for. We must either check at every single
1410 operation, which would be tedious, or we must do the computations
1411 in a type larger than bfd_vma, which would be inefficient. */
1412 flag
= bfd_reloc_ok
;
1413 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1415 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1418 /* Get the values to be added together. For signed and unsigned
1419 relocations, we assume that all values should be truncated to
1420 the size of an address. For bitfields, all the bits matter.
1421 See also bfd_check_overflow. */
1422 fieldmask
= N_ONES (howto
->bitsize
);
1423 signmask
= ~fieldmask
;
1424 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1425 | (fieldmask
<< rightshift
));
1426 a
= (relocation
& addrmask
) >> rightshift
;
1427 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1428 addrmask
>>= rightshift
;
1430 switch (howto
->complain_on_overflow
)
1432 case complain_overflow_signed
:
1433 /* If any sign bits are set, all sign bits must be set.
1434 That is, A must be a valid negative address after
1436 signmask
= ~(fieldmask
>> 1);
1439 case complain_overflow_bitfield
:
1440 /* Much like the signed check, but for a field one bit
1441 wider. We allow a bitfield to represent numbers in the
1442 range -2**n to 2**n-1, where n is the number of bits in the
1443 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1444 can't overflow, which is exactly what we want. */
1446 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1447 flag
= bfd_reloc_overflow
;
1449 /* We only need this next bit of code if the sign bit of B
1450 is below the sign bit of A. This would only happen if
1451 SRC_MASK had fewer bits than BITSIZE. Note that if
1452 SRC_MASK has more bits than BITSIZE, we can get into
1453 trouble; we would need to verify that B is in range, as
1454 we do for A above. */
1455 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1458 /* Set all the bits above the sign bit. */
1461 /* Now we can do the addition. */
1464 /* See if the result has the correct sign. Bits above the
1465 sign bit are junk now; ignore them. If the sum is
1466 positive, make sure we did not have all negative inputs;
1467 if the sum is negative, make sure we did not have all
1468 positive inputs. The test below looks only at the sign
1469 bits, and it really just
1470 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1472 We mask with addrmask here to explicitly allow an address
1473 wrap-around. The Linux kernel relies on it, and it is
1474 the only way to write assembler code which can run when
1475 loaded at a location 0x80000000 away from the location at
1476 which it is linked. */
1477 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1478 flag
= bfd_reloc_overflow
;
1481 case complain_overflow_unsigned
:
1482 /* Checking for an unsigned overflow is relatively easy:
1483 trim the addresses and add, and trim the result as well.
1484 Overflow is normally indicated when the result does not
1485 fit in the field. However, we also need to consider the
1486 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1487 input is 0x80000000, and bfd_vma is only 32 bits; then we
1488 will get sum == 0, but there is an overflow, since the
1489 inputs did not fit in the field. Instead of doing a
1490 separate test, we can check for this by or-ing in the
1491 operands when testing for the sum overflowing its final
1493 sum
= (a
+ b
) & addrmask
;
1494 if ((a
| b
| sum
) & signmask
)
1495 flag
= bfd_reloc_overflow
;
1503 /* Put RELOCATION in the right bits. */
1504 relocation
>>= (bfd_vma
) rightshift
;
1505 relocation
<<= (bfd_vma
) bitpos
;
1507 /* Add RELOCATION to the right bits of X. */
1508 x
= ((x
& ~howto
->dst_mask
)
1509 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1511 /* Put the relocated value back in the object file. */
1512 write_reloc (input_bfd
, x
, location
, howto
);
1516 /* Clear a given location using a given howto, by applying a fixed relocation
1517 value and discarding any in-place addend. This is used for fixed-up
1518 relocations against discarded symbols, to make ignorable debug or unwind
1519 information more obvious. */
1521 bfd_reloc_status_type
1522 _bfd_clear_contents (reloc_howto_type
*howto
,
1524 asection
*input_section
,
1531 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1532 return bfd_reloc_outofrange
;
1534 /* Get the value we are going to relocate. */
1535 location
= buf
+ off
;
1536 x
= read_reloc (input_bfd
, location
, howto
);
1538 /* Zero out the unwanted bits of X. */
1539 x
&= ~howto
->dst_mask
;
1541 /* For a range list, use 1 instead of 0 as placeholder. 0
1542 would terminate the list, hiding any later entries. */
1543 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1544 && (howto
->dst_mask
& 1) != 0)
1547 /* Put the relocated value back in the object file. */
1548 write_reloc (input_bfd
, x
, location
, howto
);
1549 return bfd_reloc_ok
;
1555 howto manager, , typedef arelent, Relocations
1560 When an application wants to create a relocation, but doesn't
1561 know what the target machine might call it, it can find out by
1562 using this bit of code.
1571 The insides of a reloc code. The idea is that, eventually, there
1572 will be one enumerator for every type of relocation we ever do.
1573 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1574 return a howto pointer.
1576 This does mean that the application must determine the correct
1577 enumerator value; you can't get a howto pointer from a random set
1598 Basic absolute relocations of N bits.
1613 PC-relative relocations. Sometimes these are relative to the address
1614 of the relocation itself; sometimes they are relative to the start of
1615 the section containing the relocation. It depends on the specific target.
1620 Section relative relocations. Some targets need this for DWARF2.
1623 BFD_RELOC_32_GOT_PCREL
1625 BFD_RELOC_16_GOT_PCREL
1627 BFD_RELOC_8_GOT_PCREL
1633 BFD_RELOC_LO16_GOTOFF
1635 BFD_RELOC_HI16_GOTOFF
1637 BFD_RELOC_HI16_S_GOTOFF
1641 BFD_RELOC_64_PLT_PCREL
1643 BFD_RELOC_32_PLT_PCREL
1645 BFD_RELOC_24_PLT_PCREL
1647 BFD_RELOC_16_PLT_PCREL
1649 BFD_RELOC_8_PLT_PCREL
1657 BFD_RELOC_LO16_PLTOFF
1659 BFD_RELOC_HI16_PLTOFF
1661 BFD_RELOC_HI16_S_PLTOFF
1675 BFD_RELOC_68K_GLOB_DAT
1677 BFD_RELOC_68K_JMP_SLOT
1679 BFD_RELOC_68K_RELATIVE
1681 BFD_RELOC_68K_TLS_GD32
1683 BFD_RELOC_68K_TLS_GD16
1685 BFD_RELOC_68K_TLS_GD8
1687 BFD_RELOC_68K_TLS_LDM32
1689 BFD_RELOC_68K_TLS_LDM16
1691 BFD_RELOC_68K_TLS_LDM8
1693 BFD_RELOC_68K_TLS_LDO32
1695 BFD_RELOC_68K_TLS_LDO16
1697 BFD_RELOC_68K_TLS_LDO8
1699 BFD_RELOC_68K_TLS_IE32
1701 BFD_RELOC_68K_TLS_IE16
1703 BFD_RELOC_68K_TLS_IE8
1705 BFD_RELOC_68K_TLS_LE32
1707 BFD_RELOC_68K_TLS_LE16
1709 BFD_RELOC_68K_TLS_LE8
1711 Relocations used by 68K ELF.
1714 BFD_RELOC_32_BASEREL
1716 BFD_RELOC_16_BASEREL
1718 BFD_RELOC_LO16_BASEREL
1720 BFD_RELOC_HI16_BASEREL
1722 BFD_RELOC_HI16_S_BASEREL
1728 Linkage-table relative.
1733 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1736 BFD_RELOC_32_PCREL_S2
1738 BFD_RELOC_16_PCREL_S2
1740 BFD_RELOC_23_PCREL_S2
1742 These PC-relative relocations are stored as word displacements --
1743 i.e., byte displacements shifted right two bits. The 30-bit word
1744 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1745 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1746 signed 16-bit displacement is used on the MIPS, and the 23-bit
1747 displacement is used on the Alpha.
1754 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1755 the target word. These are used on the SPARC.
1762 For systems that allocate a Global Pointer register, these are
1763 displacements off that register. These relocation types are
1764 handled specially, because the value the register will have is
1765 decided relatively late.
1770 BFD_RELOC_SPARC_WDISP22
1776 BFD_RELOC_SPARC_GOT10
1778 BFD_RELOC_SPARC_GOT13
1780 BFD_RELOC_SPARC_GOT22
1782 BFD_RELOC_SPARC_PC10
1784 BFD_RELOC_SPARC_PC22
1786 BFD_RELOC_SPARC_WPLT30
1788 BFD_RELOC_SPARC_COPY
1790 BFD_RELOC_SPARC_GLOB_DAT
1792 BFD_RELOC_SPARC_JMP_SLOT
1794 BFD_RELOC_SPARC_RELATIVE
1796 BFD_RELOC_SPARC_UA16
1798 BFD_RELOC_SPARC_UA32
1800 BFD_RELOC_SPARC_UA64
1802 BFD_RELOC_SPARC_GOTDATA_HIX22
1804 BFD_RELOC_SPARC_GOTDATA_LOX10
1806 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1808 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1810 BFD_RELOC_SPARC_GOTDATA_OP
1812 BFD_RELOC_SPARC_JMP_IREL
1814 BFD_RELOC_SPARC_IRELATIVE
1816 SPARC ELF relocations. There is probably some overlap with other
1817 relocation types already defined.
1820 BFD_RELOC_SPARC_BASE13
1822 BFD_RELOC_SPARC_BASE22
1824 I think these are specific to SPARC a.out (e.g., Sun 4).
1834 BFD_RELOC_SPARC_OLO10
1836 BFD_RELOC_SPARC_HH22
1838 BFD_RELOC_SPARC_HM10
1840 BFD_RELOC_SPARC_LM22
1842 BFD_RELOC_SPARC_PC_HH22
1844 BFD_RELOC_SPARC_PC_HM10
1846 BFD_RELOC_SPARC_PC_LM22
1848 BFD_RELOC_SPARC_WDISP16
1850 BFD_RELOC_SPARC_WDISP19
1858 BFD_RELOC_SPARC_DISP64
1861 BFD_RELOC_SPARC_PLT32
1863 BFD_RELOC_SPARC_PLT64
1865 BFD_RELOC_SPARC_HIX22
1867 BFD_RELOC_SPARC_LOX10
1875 BFD_RELOC_SPARC_REGISTER
1879 BFD_RELOC_SPARC_SIZE32
1881 BFD_RELOC_SPARC_SIZE64
1883 BFD_RELOC_SPARC_WDISP10
1888 BFD_RELOC_SPARC_REV32
1890 SPARC little endian relocation
1892 BFD_RELOC_SPARC_TLS_GD_HI22
1894 BFD_RELOC_SPARC_TLS_GD_LO10
1896 BFD_RELOC_SPARC_TLS_GD_ADD
1898 BFD_RELOC_SPARC_TLS_GD_CALL
1900 BFD_RELOC_SPARC_TLS_LDM_HI22
1902 BFD_RELOC_SPARC_TLS_LDM_LO10
1904 BFD_RELOC_SPARC_TLS_LDM_ADD
1906 BFD_RELOC_SPARC_TLS_LDM_CALL
1908 BFD_RELOC_SPARC_TLS_LDO_HIX22
1910 BFD_RELOC_SPARC_TLS_LDO_LOX10
1912 BFD_RELOC_SPARC_TLS_LDO_ADD
1914 BFD_RELOC_SPARC_TLS_IE_HI22
1916 BFD_RELOC_SPARC_TLS_IE_LO10
1918 BFD_RELOC_SPARC_TLS_IE_LD
1920 BFD_RELOC_SPARC_TLS_IE_LDX
1922 BFD_RELOC_SPARC_TLS_IE_ADD
1924 BFD_RELOC_SPARC_TLS_LE_HIX22
1926 BFD_RELOC_SPARC_TLS_LE_LOX10
1928 BFD_RELOC_SPARC_TLS_DTPMOD32
1930 BFD_RELOC_SPARC_TLS_DTPMOD64
1932 BFD_RELOC_SPARC_TLS_DTPOFF32
1934 BFD_RELOC_SPARC_TLS_DTPOFF64
1936 BFD_RELOC_SPARC_TLS_TPOFF32
1938 BFD_RELOC_SPARC_TLS_TPOFF64
1940 SPARC TLS relocations
1949 BFD_RELOC_SPU_IMM10W
1953 BFD_RELOC_SPU_IMM16W
1957 BFD_RELOC_SPU_PCREL9a
1959 BFD_RELOC_SPU_PCREL9b
1961 BFD_RELOC_SPU_PCREL16
1971 BFD_RELOC_SPU_ADD_PIC
1976 BFD_RELOC_ALPHA_GPDISP_HI16
1978 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1979 "addend" in some special way.
1980 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1981 writing; when reading, it will be the absolute section symbol. The
1982 addend is the displacement in bytes of the "lda" instruction from
1983 the "ldah" instruction (which is at the address of this reloc).
1985 BFD_RELOC_ALPHA_GPDISP_LO16
1987 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1988 with GPDISP_HI16 relocs. The addend is ignored when writing the
1989 relocations out, and is filled in with the file's GP value on
1990 reading, for convenience.
1993 BFD_RELOC_ALPHA_GPDISP
1995 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1996 relocation except that there is no accompanying GPDISP_LO16
2000 BFD_RELOC_ALPHA_LITERAL
2002 BFD_RELOC_ALPHA_ELF_LITERAL
2004 BFD_RELOC_ALPHA_LITUSE
2006 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2007 the assembler turns it into a LDQ instruction to load the address of
2008 the symbol, and then fills in a register in the real instruction.
2010 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2011 section symbol. The addend is ignored when writing, but is filled
2012 in with the file's GP value on reading, for convenience, as with the
2015 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2016 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2017 but it generates output not based on the position within the .got
2018 section, but relative to the GP value chosen for the file during the
2021 The LITUSE reloc, on the instruction using the loaded address, gives
2022 information to the linker that it might be able to use to optimize
2023 away some literal section references. The symbol is ignored (read
2024 as the absolute section symbol), and the "addend" indicates the type
2025 of instruction using the register:
2026 1 - "memory" fmt insn
2027 2 - byte-manipulation (byte offset reg)
2028 3 - jsr (target of branch)
2031 BFD_RELOC_ALPHA_HINT
2033 The HINT relocation indicates a value that should be filled into the
2034 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2035 prediction logic which may be provided on some processors.
2038 BFD_RELOC_ALPHA_LINKAGE
2040 The LINKAGE relocation outputs a linkage pair in the object file,
2041 which is filled by the linker.
2044 BFD_RELOC_ALPHA_CODEADDR
2046 The CODEADDR relocation outputs a STO_CA in the object file,
2047 which is filled by the linker.
2050 BFD_RELOC_ALPHA_GPREL_HI16
2052 BFD_RELOC_ALPHA_GPREL_LO16
2054 The GPREL_HI/LO relocations together form a 32-bit offset from the
2058 BFD_RELOC_ALPHA_BRSGP
2060 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2061 share a common GP, and the target address is adjusted for
2062 STO_ALPHA_STD_GPLOAD.
2067 The NOP relocation outputs a NOP if the longword displacement
2068 between two procedure entry points is < 2^21.
2073 The BSR relocation outputs a BSR if the longword displacement
2074 between two procedure entry points is < 2^21.
2079 The LDA relocation outputs a LDA if the longword displacement
2080 between two procedure entry points is < 2^16.
2085 The BOH relocation outputs a BSR if the longword displacement
2086 between two procedure entry points is < 2^21, or else a hint.
2089 BFD_RELOC_ALPHA_TLSGD
2091 BFD_RELOC_ALPHA_TLSLDM
2093 BFD_RELOC_ALPHA_DTPMOD64
2095 BFD_RELOC_ALPHA_GOTDTPREL16
2097 BFD_RELOC_ALPHA_DTPREL64
2099 BFD_RELOC_ALPHA_DTPREL_HI16
2101 BFD_RELOC_ALPHA_DTPREL_LO16
2103 BFD_RELOC_ALPHA_DTPREL16
2105 BFD_RELOC_ALPHA_GOTTPREL16
2107 BFD_RELOC_ALPHA_TPREL64
2109 BFD_RELOC_ALPHA_TPREL_HI16
2111 BFD_RELOC_ALPHA_TPREL_LO16
2113 BFD_RELOC_ALPHA_TPREL16
2115 Alpha thread-local storage relocations.
2120 BFD_RELOC_MICROMIPS_JMP
2122 The MIPS jump instruction.
2125 BFD_RELOC_MIPS16_JMP
2127 The MIPS16 jump instruction.
2130 BFD_RELOC_MIPS16_GPREL
2132 MIPS16 GP relative reloc.
2137 High 16 bits of 32-bit value; simple reloc.
2142 High 16 bits of 32-bit value but the low 16 bits will be sign
2143 extended and added to form the final result. If the low 16
2144 bits form a negative number, we need to add one to the high value
2145 to compensate for the borrow when the low bits are added.
2153 BFD_RELOC_HI16_PCREL
2155 High 16 bits of 32-bit pc-relative value
2157 BFD_RELOC_HI16_S_PCREL
2159 High 16 bits of 32-bit pc-relative value, adjusted
2161 BFD_RELOC_LO16_PCREL
2163 Low 16 bits of pc-relative value
2166 BFD_RELOC_MIPS16_GOT16
2168 BFD_RELOC_MIPS16_CALL16
2170 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2171 16-bit immediate fields
2173 BFD_RELOC_MIPS16_HI16
2175 MIPS16 high 16 bits of 32-bit value.
2177 BFD_RELOC_MIPS16_HI16_S
2179 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2180 extended and added to form the final result. If the low 16
2181 bits form a negative number, we need to add one to the high value
2182 to compensate for the borrow when the low bits are added.
2184 BFD_RELOC_MIPS16_LO16
2189 BFD_RELOC_MIPS16_TLS_GD
2191 BFD_RELOC_MIPS16_TLS_LDM
2193 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2195 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2197 BFD_RELOC_MIPS16_TLS_GOTTPREL
2199 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2201 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2203 MIPS16 TLS relocations
2206 BFD_RELOC_MIPS_LITERAL
2208 BFD_RELOC_MICROMIPS_LITERAL
2210 Relocation against a MIPS literal section.
2213 BFD_RELOC_MICROMIPS_7_PCREL_S1
2215 BFD_RELOC_MICROMIPS_10_PCREL_S1
2217 BFD_RELOC_MICROMIPS_16_PCREL_S1
2219 microMIPS PC-relative relocations.
2222 BFD_RELOC_MIPS16_16_PCREL_S1
2224 MIPS16 PC-relative relocation.
2227 BFD_RELOC_MIPS_21_PCREL_S2
2229 BFD_RELOC_MIPS_26_PCREL_S2
2231 BFD_RELOC_MIPS_18_PCREL_S3
2233 BFD_RELOC_MIPS_19_PCREL_S2
2235 MIPS PC-relative relocations.
2238 BFD_RELOC_MICROMIPS_GPREL16
2240 BFD_RELOC_MICROMIPS_HI16
2242 BFD_RELOC_MICROMIPS_HI16_S
2244 BFD_RELOC_MICROMIPS_LO16
2246 microMIPS versions of generic BFD relocs.
2249 BFD_RELOC_MIPS_GOT16
2251 BFD_RELOC_MICROMIPS_GOT16
2253 BFD_RELOC_MIPS_CALL16
2255 BFD_RELOC_MICROMIPS_CALL16
2257 BFD_RELOC_MIPS_GOT_HI16
2259 BFD_RELOC_MICROMIPS_GOT_HI16
2261 BFD_RELOC_MIPS_GOT_LO16
2263 BFD_RELOC_MICROMIPS_GOT_LO16
2265 BFD_RELOC_MIPS_CALL_HI16
2267 BFD_RELOC_MICROMIPS_CALL_HI16
2269 BFD_RELOC_MIPS_CALL_LO16
2271 BFD_RELOC_MICROMIPS_CALL_LO16
2275 BFD_RELOC_MICROMIPS_SUB
2277 BFD_RELOC_MIPS_GOT_PAGE
2279 BFD_RELOC_MICROMIPS_GOT_PAGE
2281 BFD_RELOC_MIPS_GOT_OFST
2283 BFD_RELOC_MICROMIPS_GOT_OFST
2285 BFD_RELOC_MIPS_GOT_DISP
2287 BFD_RELOC_MICROMIPS_GOT_DISP
2289 BFD_RELOC_MIPS_SHIFT5
2291 BFD_RELOC_MIPS_SHIFT6
2293 BFD_RELOC_MIPS_INSERT_A
2295 BFD_RELOC_MIPS_INSERT_B
2297 BFD_RELOC_MIPS_DELETE
2299 BFD_RELOC_MIPS_HIGHEST
2301 BFD_RELOC_MICROMIPS_HIGHEST
2303 BFD_RELOC_MIPS_HIGHER
2305 BFD_RELOC_MICROMIPS_HIGHER
2307 BFD_RELOC_MIPS_SCN_DISP
2309 BFD_RELOC_MICROMIPS_SCN_DISP
2311 BFD_RELOC_MIPS_REL16
2313 BFD_RELOC_MIPS_RELGOT
2317 BFD_RELOC_MICROMIPS_JALR
2319 BFD_RELOC_MIPS_TLS_DTPMOD32
2321 BFD_RELOC_MIPS_TLS_DTPREL32
2323 BFD_RELOC_MIPS_TLS_DTPMOD64
2325 BFD_RELOC_MIPS_TLS_DTPREL64
2327 BFD_RELOC_MIPS_TLS_GD
2329 BFD_RELOC_MICROMIPS_TLS_GD
2331 BFD_RELOC_MIPS_TLS_LDM
2333 BFD_RELOC_MICROMIPS_TLS_LDM
2335 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2337 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2339 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2341 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2343 BFD_RELOC_MIPS_TLS_GOTTPREL
2345 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2347 BFD_RELOC_MIPS_TLS_TPREL32
2349 BFD_RELOC_MIPS_TLS_TPREL64
2351 BFD_RELOC_MIPS_TLS_TPREL_HI16
2353 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2355 BFD_RELOC_MIPS_TLS_TPREL_LO16
2357 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2361 MIPS ELF relocations.
2367 BFD_RELOC_MIPS_JUMP_SLOT
2369 MIPS ELF relocations (VxWorks and PLT extensions).
2373 BFD_RELOC_MOXIE_10_PCREL
2375 Moxie ELF relocations.
2387 BFD_RELOC_FT32_RELAX
2395 BFD_RELOC_FT32_DIFF32
2397 FT32 ELF relocations.
2401 BFD_RELOC_FRV_LABEL16
2403 BFD_RELOC_FRV_LABEL24
2409 BFD_RELOC_FRV_GPREL12
2411 BFD_RELOC_FRV_GPRELU12
2413 BFD_RELOC_FRV_GPREL32
2415 BFD_RELOC_FRV_GPRELHI
2417 BFD_RELOC_FRV_GPRELLO
2425 BFD_RELOC_FRV_FUNCDESC
2427 BFD_RELOC_FRV_FUNCDESC_GOT12
2429 BFD_RELOC_FRV_FUNCDESC_GOTHI
2431 BFD_RELOC_FRV_FUNCDESC_GOTLO
2433 BFD_RELOC_FRV_FUNCDESC_VALUE
2435 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2437 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2439 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2441 BFD_RELOC_FRV_GOTOFF12
2443 BFD_RELOC_FRV_GOTOFFHI
2445 BFD_RELOC_FRV_GOTOFFLO
2447 BFD_RELOC_FRV_GETTLSOFF
2449 BFD_RELOC_FRV_TLSDESC_VALUE
2451 BFD_RELOC_FRV_GOTTLSDESC12
2453 BFD_RELOC_FRV_GOTTLSDESCHI
2455 BFD_RELOC_FRV_GOTTLSDESCLO
2457 BFD_RELOC_FRV_TLSMOFF12
2459 BFD_RELOC_FRV_TLSMOFFHI
2461 BFD_RELOC_FRV_TLSMOFFLO
2463 BFD_RELOC_FRV_GOTTLSOFF12
2465 BFD_RELOC_FRV_GOTTLSOFFHI
2467 BFD_RELOC_FRV_GOTTLSOFFLO
2469 BFD_RELOC_FRV_TLSOFF
2471 BFD_RELOC_FRV_TLSDESC_RELAX
2473 BFD_RELOC_FRV_GETTLSOFF_RELAX
2475 BFD_RELOC_FRV_TLSOFF_RELAX
2477 BFD_RELOC_FRV_TLSMOFF
2479 Fujitsu Frv Relocations.
2483 BFD_RELOC_MN10300_GOTOFF24
2485 This is a 24bit GOT-relative reloc for the mn10300.
2487 BFD_RELOC_MN10300_GOT32
2489 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2492 BFD_RELOC_MN10300_GOT24
2494 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2497 BFD_RELOC_MN10300_GOT16
2499 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2502 BFD_RELOC_MN10300_COPY
2504 Copy symbol at runtime.
2506 BFD_RELOC_MN10300_GLOB_DAT
2510 BFD_RELOC_MN10300_JMP_SLOT
2514 BFD_RELOC_MN10300_RELATIVE
2516 Adjust by program base.
2518 BFD_RELOC_MN10300_SYM_DIFF
2520 Together with another reloc targeted at the same location,
2521 allows for a value that is the difference of two symbols
2522 in the same section.
2524 BFD_RELOC_MN10300_ALIGN
2526 The addend of this reloc is an alignment power that must
2527 be honoured at the offset's location, regardless of linker
2530 BFD_RELOC_MN10300_TLS_GD
2532 BFD_RELOC_MN10300_TLS_LD
2534 BFD_RELOC_MN10300_TLS_LDO
2536 BFD_RELOC_MN10300_TLS_GOTIE
2538 BFD_RELOC_MN10300_TLS_IE
2540 BFD_RELOC_MN10300_TLS_LE
2542 BFD_RELOC_MN10300_TLS_DTPMOD
2544 BFD_RELOC_MN10300_TLS_DTPOFF
2546 BFD_RELOC_MN10300_TLS_TPOFF
2548 Various TLS-related relocations.
2550 BFD_RELOC_MN10300_32_PCREL
2552 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2555 BFD_RELOC_MN10300_16_PCREL
2557 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2568 BFD_RELOC_386_GLOB_DAT
2570 BFD_RELOC_386_JUMP_SLOT
2572 BFD_RELOC_386_RELATIVE
2574 BFD_RELOC_386_GOTOFF
2578 BFD_RELOC_386_TLS_TPOFF
2580 BFD_RELOC_386_TLS_IE
2582 BFD_RELOC_386_TLS_GOTIE
2584 BFD_RELOC_386_TLS_LE
2586 BFD_RELOC_386_TLS_GD
2588 BFD_RELOC_386_TLS_LDM
2590 BFD_RELOC_386_TLS_LDO_32
2592 BFD_RELOC_386_TLS_IE_32
2594 BFD_RELOC_386_TLS_LE_32
2596 BFD_RELOC_386_TLS_DTPMOD32
2598 BFD_RELOC_386_TLS_DTPOFF32
2600 BFD_RELOC_386_TLS_TPOFF32
2602 BFD_RELOC_386_TLS_GOTDESC
2604 BFD_RELOC_386_TLS_DESC_CALL
2606 BFD_RELOC_386_TLS_DESC
2608 BFD_RELOC_386_IRELATIVE
2610 BFD_RELOC_386_GOT32X
2612 i386/elf relocations
2615 BFD_RELOC_X86_64_GOT32
2617 BFD_RELOC_X86_64_PLT32
2619 BFD_RELOC_X86_64_COPY
2621 BFD_RELOC_X86_64_GLOB_DAT
2623 BFD_RELOC_X86_64_JUMP_SLOT
2625 BFD_RELOC_X86_64_RELATIVE
2627 BFD_RELOC_X86_64_GOTPCREL
2629 BFD_RELOC_X86_64_32S
2631 BFD_RELOC_X86_64_DTPMOD64
2633 BFD_RELOC_X86_64_DTPOFF64
2635 BFD_RELOC_X86_64_TPOFF64
2637 BFD_RELOC_X86_64_TLSGD
2639 BFD_RELOC_X86_64_TLSLD
2641 BFD_RELOC_X86_64_DTPOFF32
2643 BFD_RELOC_X86_64_GOTTPOFF
2645 BFD_RELOC_X86_64_TPOFF32
2647 BFD_RELOC_X86_64_GOTOFF64
2649 BFD_RELOC_X86_64_GOTPC32
2651 BFD_RELOC_X86_64_GOT64
2653 BFD_RELOC_X86_64_GOTPCREL64
2655 BFD_RELOC_X86_64_GOTPC64
2657 BFD_RELOC_X86_64_GOTPLT64
2659 BFD_RELOC_X86_64_PLTOFF64
2661 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2663 BFD_RELOC_X86_64_TLSDESC_CALL
2665 BFD_RELOC_X86_64_TLSDESC
2667 BFD_RELOC_X86_64_IRELATIVE
2669 BFD_RELOC_X86_64_PC32_BND
2671 BFD_RELOC_X86_64_PLT32_BND
2673 BFD_RELOC_X86_64_GOTPCRELX
2675 BFD_RELOC_X86_64_REX_GOTPCRELX
2677 x86-64/elf relocations
2680 BFD_RELOC_NS32K_IMM_8
2682 BFD_RELOC_NS32K_IMM_16
2684 BFD_RELOC_NS32K_IMM_32
2686 BFD_RELOC_NS32K_IMM_8_PCREL
2688 BFD_RELOC_NS32K_IMM_16_PCREL
2690 BFD_RELOC_NS32K_IMM_32_PCREL
2692 BFD_RELOC_NS32K_DISP_8
2694 BFD_RELOC_NS32K_DISP_16
2696 BFD_RELOC_NS32K_DISP_32
2698 BFD_RELOC_NS32K_DISP_8_PCREL
2700 BFD_RELOC_NS32K_DISP_16_PCREL
2702 BFD_RELOC_NS32K_DISP_32_PCREL
2707 BFD_RELOC_PDP11_DISP_8_PCREL
2709 BFD_RELOC_PDP11_DISP_6_PCREL
2714 BFD_RELOC_PJ_CODE_HI16
2716 BFD_RELOC_PJ_CODE_LO16
2718 BFD_RELOC_PJ_CODE_DIR16
2720 BFD_RELOC_PJ_CODE_DIR32
2722 BFD_RELOC_PJ_CODE_REL16
2724 BFD_RELOC_PJ_CODE_REL32
2726 Picojava relocs. Not all of these appear in object files.
2737 BFD_RELOC_PPC_B16_BRTAKEN
2739 BFD_RELOC_PPC_B16_BRNTAKEN
2743 BFD_RELOC_PPC_BA16_BRTAKEN
2745 BFD_RELOC_PPC_BA16_BRNTAKEN
2749 BFD_RELOC_PPC_GLOB_DAT
2751 BFD_RELOC_PPC_JMP_SLOT
2753 BFD_RELOC_PPC_RELATIVE
2755 BFD_RELOC_PPC_LOCAL24PC
2757 BFD_RELOC_PPC_EMB_NADDR32
2759 BFD_RELOC_PPC_EMB_NADDR16
2761 BFD_RELOC_PPC_EMB_NADDR16_LO
2763 BFD_RELOC_PPC_EMB_NADDR16_HI
2765 BFD_RELOC_PPC_EMB_NADDR16_HA
2767 BFD_RELOC_PPC_EMB_SDAI16
2769 BFD_RELOC_PPC_EMB_SDA2I16
2771 BFD_RELOC_PPC_EMB_SDA2REL
2773 BFD_RELOC_PPC_EMB_SDA21
2775 BFD_RELOC_PPC_EMB_MRKREF
2777 BFD_RELOC_PPC_EMB_RELSEC16
2779 BFD_RELOC_PPC_EMB_RELST_LO
2781 BFD_RELOC_PPC_EMB_RELST_HI
2783 BFD_RELOC_PPC_EMB_RELST_HA
2785 BFD_RELOC_PPC_EMB_BIT_FLD
2787 BFD_RELOC_PPC_EMB_RELSDA
2789 BFD_RELOC_PPC_VLE_REL8
2791 BFD_RELOC_PPC_VLE_REL15
2793 BFD_RELOC_PPC_VLE_REL24
2795 BFD_RELOC_PPC_VLE_LO16A
2797 BFD_RELOC_PPC_VLE_LO16D
2799 BFD_RELOC_PPC_VLE_HI16A
2801 BFD_RELOC_PPC_VLE_HI16D
2803 BFD_RELOC_PPC_VLE_HA16A
2805 BFD_RELOC_PPC_VLE_HA16D
2807 BFD_RELOC_PPC_VLE_SDA21
2809 BFD_RELOC_PPC_VLE_SDA21_LO
2811 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2813 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2815 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2817 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2819 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2821 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2823 BFD_RELOC_PPC_16DX_HA
2825 BFD_RELOC_PPC_REL16DX_HA
2827 BFD_RELOC_PPC64_HIGHER
2829 BFD_RELOC_PPC64_HIGHER_S
2831 BFD_RELOC_PPC64_HIGHEST
2833 BFD_RELOC_PPC64_HIGHEST_S
2835 BFD_RELOC_PPC64_TOC16_LO
2837 BFD_RELOC_PPC64_TOC16_HI
2839 BFD_RELOC_PPC64_TOC16_HA
2843 BFD_RELOC_PPC64_PLTGOT16
2845 BFD_RELOC_PPC64_PLTGOT16_LO
2847 BFD_RELOC_PPC64_PLTGOT16_HI
2849 BFD_RELOC_PPC64_PLTGOT16_HA
2851 BFD_RELOC_PPC64_ADDR16_DS
2853 BFD_RELOC_PPC64_ADDR16_LO_DS
2855 BFD_RELOC_PPC64_GOT16_DS
2857 BFD_RELOC_PPC64_GOT16_LO_DS
2859 BFD_RELOC_PPC64_PLT16_LO_DS
2861 BFD_RELOC_PPC64_SECTOFF_DS
2863 BFD_RELOC_PPC64_SECTOFF_LO_DS
2865 BFD_RELOC_PPC64_TOC16_DS
2867 BFD_RELOC_PPC64_TOC16_LO_DS
2869 BFD_RELOC_PPC64_PLTGOT16_DS
2871 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2873 BFD_RELOC_PPC64_ADDR16_HIGH
2875 BFD_RELOC_PPC64_ADDR16_HIGHA
2877 BFD_RELOC_PPC64_REL16_HIGH
2879 BFD_RELOC_PPC64_REL16_HIGHA
2881 BFD_RELOC_PPC64_REL16_HIGHER
2883 BFD_RELOC_PPC64_REL16_HIGHERA
2885 BFD_RELOC_PPC64_REL16_HIGHEST
2887 BFD_RELOC_PPC64_REL16_HIGHESTA
2889 BFD_RELOC_PPC64_ADDR64_LOCAL
2891 BFD_RELOC_PPC64_ENTRY
2893 BFD_RELOC_PPC64_REL24_NOTOC
2897 BFD_RELOC_PPC64_D34_LO
2899 BFD_RELOC_PPC64_D34_HI30
2901 BFD_RELOC_PPC64_D34_HA30
2903 BFD_RELOC_PPC64_PCREL34
2905 BFD_RELOC_PPC64_GOT_PCREL34
2907 BFD_RELOC_PPC64_PLT_PCREL34
2909 BFD_RELOC_PPC64_ADDR16_HIGHER34
2911 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2913 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2915 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2917 BFD_RELOC_PPC64_REL16_HIGHER34
2919 BFD_RELOC_PPC64_REL16_HIGHERA34
2921 BFD_RELOC_PPC64_REL16_HIGHEST34
2923 BFD_RELOC_PPC64_REL16_HIGHESTA34
2927 BFD_RELOC_PPC64_PCREL28
2929 Power(rs6000) and PowerPC relocations.
2938 BFD_RELOC_PPC_DTPMOD
2940 BFD_RELOC_PPC_TPREL16
2942 BFD_RELOC_PPC_TPREL16_LO
2944 BFD_RELOC_PPC_TPREL16_HI
2946 BFD_RELOC_PPC_TPREL16_HA
2950 BFD_RELOC_PPC_DTPREL16
2952 BFD_RELOC_PPC_DTPREL16_LO
2954 BFD_RELOC_PPC_DTPREL16_HI
2956 BFD_RELOC_PPC_DTPREL16_HA
2958 BFD_RELOC_PPC_DTPREL
2960 BFD_RELOC_PPC_GOT_TLSGD16
2962 BFD_RELOC_PPC_GOT_TLSGD16_LO
2964 BFD_RELOC_PPC_GOT_TLSGD16_HI
2966 BFD_RELOC_PPC_GOT_TLSGD16_HA
2968 BFD_RELOC_PPC_GOT_TLSLD16
2970 BFD_RELOC_PPC_GOT_TLSLD16_LO
2972 BFD_RELOC_PPC_GOT_TLSLD16_HI
2974 BFD_RELOC_PPC_GOT_TLSLD16_HA
2976 BFD_RELOC_PPC_GOT_TPREL16
2978 BFD_RELOC_PPC_GOT_TPREL16_LO
2980 BFD_RELOC_PPC_GOT_TPREL16_HI
2982 BFD_RELOC_PPC_GOT_TPREL16_HA
2984 BFD_RELOC_PPC_GOT_DTPREL16
2986 BFD_RELOC_PPC_GOT_DTPREL16_LO
2988 BFD_RELOC_PPC_GOT_DTPREL16_HI
2990 BFD_RELOC_PPC_GOT_DTPREL16_HA
2992 BFD_RELOC_PPC64_TPREL16_DS
2994 BFD_RELOC_PPC64_TPREL16_LO_DS
2996 BFD_RELOC_PPC64_TPREL16_HIGH
2998 BFD_RELOC_PPC64_TPREL16_HIGHA
3000 BFD_RELOC_PPC64_TPREL16_HIGHER
3002 BFD_RELOC_PPC64_TPREL16_HIGHERA
3004 BFD_RELOC_PPC64_TPREL16_HIGHEST
3006 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3008 BFD_RELOC_PPC64_DTPREL16_DS
3010 BFD_RELOC_PPC64_DTPREL16_LO_DS
3012 BFD_RELOC_PPC64_DTPREL16_HIGH
3014 BFD_RELOC_PPC64_DTPREL16_HIGHA
3016 BFD_RELOC_PPC64_DTPREL16_HIGHER
3018 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3020 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3022 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3024 BFD_RELOC_PPC64_TPREL34
3026 BFD_RELOC_PPC64_DTPREL34
3028 BFD_RELOC_PPC64_GOT_TLSGD34
3030 BFD_RELOC_PPC64_GOT_TLSLD34
3032 BFD_RELOC_PPC64_GOT_TPREL34
3034 BFD_RELOC_PPC64_GOT_DTPREL34
3036 BFD_RELOC_PPC64_TLS_PCREL
3038 PowerPC and PowerPC64 thread-local storage relocations.
3043 IBM 370/390 relocations
3048 The type of reloc used to build a constructor table - at the moment
3049 probably a 32 bit wide absolute relocation, but the target can choose.
3050 It generally does map to one of the other relocation types.
3053 BFD_RELOC_ARM_PCREL_BRANCH
3055 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3056 not stored in the instruction.
3058 BFD_RELOC_ARM_PCREL_BLX
3060 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3061 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3062 field in the instruction.
3064 BFD_RELOC_THUMB_PCREL_BLX
3066 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3067 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3068 field in the instruction.
3070 BFD_RELOC_ARM_PCREL_CALL
3072 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3074 BFD_RELOC_ARM_PCREL_JUMP
3076 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3079 BFD_RELOC_THUMB_PCREL_BRANCH5
3081 ARM 5-bit pc-relative branch for Branch Future instructions.
3084 BFD_RELOC_THUMB_PCREL_BFCSEL
3086 ARM 6-bit pc-relative branch for BFCSEL instruction.
3089 BFD_RELOC_ARM_THUMB_BF17
3091 ARM 17-bit pc-relative branch for Branch Future instructions.
3094 BFD_RELOC_ARM_THUMB_BF13
3096 ARM 13-bit pc-relative branch for BFCSEL instruction.
3099 BFD_RELOC_ARM_THUMB_BF19
3101 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3104 BFD_RELOC_ARM_THUMB_LOOP12
3106 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3109 BFD_RELOC_THUMB_PCREL_BRANCH7
3111 BFD_RELOC_THUMB_PCREL_BRANCH9
3113 BFD_RELOC_THUMB_PCREL_BRANCH12
3115 BFD_RELOC_THUMB_PCREL_BRANCH20
3117 BFD_RELOC_THUMB_PCREL_BRANCH23
3119 BFD_RELOC_THUMB_PCREL_BRANCH25
3121 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3122 The lowest bit must be zero and is not stored in the instruction.
3123 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3124 "nn" one smaller in all cases. Note further that BRANCH23
3125 corresponds to R_ARM_THM_CALL.
3128 BFD_RELOC_ARM_OFFSET_IMM
3130 12-bit immediate offset, used in ARM-format ldr and str instructions.
3133 BFD_RELOC_ARM_THUMB_OFFSET
3135 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3138 BFD_RELOC_ARM_TARGET1
3140 Pc-relative or absolute relocation depending on target. Used for
3141 entries in .init_array sections.
3143 BFD_RELOC_ARM_ROSEGREL32
3145 Read-only segment base relative address.
3147 BFD_RELOC_ARM_SBREL32
3149 Data segment base relative address.
3151 BFD_RELOC_ARM_TARGET2
3153 This reloc is used for references to RTTI data from exception handling
3154 tables. The actual definition depends on the target. It may be a
3155 pc-relative or some form of GOT-indirect relocation.
3157 BFD_RELOC_ARM_PREL31
3159 31-bit PC relative address.
3165 BFD_RELOC_ARM_MOVW_PCREL
3167 BFD_RELOC_ARM_MOVT_PCREL
3169 BFD_RELOC_ARM_THUMB_MOVW
3171 BFD_RELOC_ARM_THUMB_MOVT
3173 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3175 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3177 Low and High halfword relocations for MOVW and MOVT instructions.
3180 BFD_RELOC_ARM_GOTFUNCDESC
3182 BFD_RELOC_ARM_GOTOFFFUNCDESC
3184 BFD_RELOC_ARM_FUNCDESC
3186 BFD_RELOC_ARM_FUNCDESC_VALUE
3188 BFD_RELOC_ARM_TLS_GD32_FDPIC
3190 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3192 BFD_RELOC_ARM_TLS_IE32_FDPIC
3194 ARM FDPIC specific relocations.
3197 BFD_RELOC_ARM_JUMP_SLOT
3199 BFD_RELOC_ARM_GLOB_DAT
3205 BFD_RELOC_ARM_RELATIVE
3207 BFD_RELOC_ARM_GOTOFF
3211 BFD_RELOC_ARM_GOT_PREL
3213 Relocations for setting up GOTs and PLTs for shared libraries.
3216 BFD_RELOC_ARM_TLS_GD32
3218 BFD_RELOC_ARM_TLS_LDO32
3220 BFD_RELOC_ARM_TLS_LDM32
3222 BFD_RELOC_ARM_TLS_DTPOFF32
3224 BFD_RELOC_ARM_TLS_DTPMOD32
3226 BFD_RELOC_ARM_TLS_TPOFF32
3228 BFD_RELOC_ARM_TLS_IE32
3230 BFD_RELOC_ARM_TLS_LE32
3232 BFD_RELOC_ARM_TLS_GOTDESC
3234 BFD_RELOC_ARM_TLS_CALL
3236 BFD_RELOC_ARM_THM_TLS_CALL
3238 BFD_RELOC_ARM_TLS_DESCSEQ
3240 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3242 BFD_RELOC_ARM_TLS_DESC
3244 ARM thread-local storage relocations.
3247 BFD_RELOC_ARM_ALU_PC_G0_NC
3249 BFD_RELOC_ARM_ALU_PC_G0
3251 BFD_RELOC_ARM_ALU_PC_G1_NC
3253 BFD_RELOC_ARM_ALU_PC_G1
3255 BFD_RELOC_ARM_ALU_PC_G2
3257 BFD_RELOC_ARM_LDR_PC_G0
3259 BFD_RELOC_ARM_LDR_PC_G1
3261 BFD_RELOC_ARM_LDR_PC_G2
3263 BFD_RELOC_ARM_LDRS_PC_G0
3265 BFD_RELOC_ARM_LDRS_PC_G1
3267 BFD_RELOC_ARM_LDRS_PC_G2
3269 BFD_RELOC_ARM_LDC_PC_G0
3271 BFD_RELOC_ARM_LDC_PC_G1
3273 BFD_RELOC_ARM_LDC_PC_G2
3275 BFD_RELOC_ARM_ALU_SB_G0_NC
3277 BFD_RELOC_ARM_ALU_SB_G0
3279 BFD_RELOC_ARM_ALU_SB_G1_NC
3281 BFD_RELOC_ARM_ALU_SB_G1
3283 BFD_RELOC_ARM_ALU_SB_G2
3285 BFD_RELOC_ARM_LDR_SB_G0
3287 BFD_RELOC_ARM_LDR_SB_G1
3289 BFD_RELOC_ARM_LDR_SB_G2
3291 BFD_RELOC_ARM_LDRS_SB_G0
3293 BFD_RELOC_ARM_LDRS_SB_G1
3295 BFD_RELOC_ARM_LDRS_SB_G2
3297 BFD_RELOC_ARM_LDC_SB_G0
3299 BFD_RELOC_ARM_LDC_SB_G1
3301 BFD_RELOC_ARM_LDC_SB_G2
3303 ARM group relocations.
3308 Annotation of BX instructions.
3311 BFD_RELOC_ARM_IRELATIVE
3313 ARM support for STT_GNU_IFUNC.
3316 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3318 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3320 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3322 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3324 Thumb1 relocations to support execute-only code.
3327 BFD_RELOC_ARM_IMMEDIATE
3329 BFD_RELOC_ARM_ADRL_IMMEDIATE
3331 BFD_RELOC_ARM_T32_IMMEDIATE
3333 BFD_RELOC_ARM_T32_ADD_IMM
3335 BFD_RELOC_ARM_T32_IMM12
3337 BFD_RELOC_ARM_T32_ADD_PC12
3339 BFD_RELOC_ARM_SHIFT_IMM
3349 BFD_RELOC_ARM_CP_OFF_IMM
3351 BFD_RELOC_ARM_CP_OFF_IMM_S2
3353 BFD_RELOC_ARM_T32_CP_OFF_IMM
3355 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3357 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3359 BFD_RELOC_ARM_ADR_IMM
3361 BFD_RELOC_ARM_LDR_IMM
3363 BFD_RELOC_ARM_LITERAL
3365 BFD_RELOC_ARM_IN_POOL
3367 BFD_RELOC_ARM_OFFSET_IMM8
3369 BFD_RELOC_ARM_T32_OFFSET_U8
3371 BFD_RELOC_ARM_T32_OFFSET_IMM
3373 BFD_RELOC_ARM_HWLITERAL
3375 BFD_RELOC_ARM_THUMB_ADD
3377 BFD_RELOC_ARM_THUMB_IMM
3379 BFD_RELOC_ARM_THUMB_SHIFT
3381 These relocs are only used within the ARM assembler. They are not
3382 (at present) written to any object files.
3385 BFD_RELOC_SH_PCDISP8BY2
3387 BFD_RELOC_SH_PCDISP12BY2
3395 BFD_RELOC_SH_DISP12BY2
3397 BFD_RELOC_SH_DISP12BY4
3399 BFD_RELOC_SH_DISP12BY8
3403 BFD_RELOC_SH_DISP20BY8
3407 BFD_RELOC_SH_IMM4BY2
3409 BFD_RELOC_SH_IMM4BY4
3413 BFD_RELOC_SH_IMM8BY2
3415 BFD_RELOC_SH_IMM8BY4
3417 BFD_RELOC_SH_PCRELIMM8BY2
3419 BFD_RELOC_SH_PCRELIMM8BY4
3421 BFD_RELOC_SH_SWITCH16
3423 BFD_RELOC_SH_SWITCH32
3437 BFD_RELOC_SH_LOOP_START
3439 BFD_RELOC_SH_LOOP_END
3443 BFD_RELOC_SH_GLOB_DAT
3445 BFD_RELOC_SH_JMP_SLOT
3447 BFD_RELOC_SH_RELATIVE
3451 BFD_RELOC_SH_GOT_LOW16
3453 BFD_RELOC_SH_GOT_MEDLOW16
3455 BFD_RELOC_SH_GOT_MEDHI16
3457 BFD_RELOC_SH_GOT_HI16
3459 BFD_RELOC_SH_GOTPLT_LOW16
3461 BFD_RELOC_SH_GOTPLT_MEDLOW16
3463 BFD_RELOC_SH_GOTPLT_MEDHI16
3465 BFD_RELOC_SH_GOTPLT_HI16
3467 BFD_RELOC_SH_PLT_LOW16
3469 BFD_RELOC_SH_PLT_MEDLOW16
3471 BFD_RELOC_SH_PLT_MEDHI16
3473 BFD_RELOC_SH_PLT_HI16
3475 BFD_RELOC_SH_GOTOFF_LOW16
3477 BFD_RELOC_SH_GOTOFF_MEDLOW16
3479 BFD_RELOC_SH_GOTOFF_MEDHI16
3481 BFD_RELOC_SH_GOTOFF_HI16
3483 BFD_RELOC_SH_GOTPC_LOW16
3485 BFD_RELOC_SH_GOTPC_MEDLOW16
3487 BFD_RELOC_SH_GOTPC_MEDHI16
3489 BFD_RELOC_SH_GOTPC_HI16
3493 BFD_RELOC_SH_GLOB_DAT64
3495 BFD_RELOC_SH_JMP_SLOT64
3497 BFD_RELOC_SH_RELATIVE64
3499 BFD_RELOC_SH_GOT10BY4
3501 BFD_RELOC_SH_GOT10BY8
3503 BFD_RELOC_SH_GOTPLT10BY4
3505 BFD_RELOC_SH_GOTPLT10BY8
3507 BFD_RELOC_SH_GOTPLT32
3509 BFD_RELOC_SH_SHMEDIA_CODE
3515 BFD_RELOC_SH_IMMS6BY32
3521 BFD_RELOC_SH_IMMS10BY2
3523 BFD_RELOC_SH_IMMS10BY4
3525 BFD_RELOC_SH_IMMS10BY8
3531 BFD_RELOC_SH_IMM_LOW16
3533 BFD_RELOC_SH_IMM_LOW16_PCREL
3535 BFD_RELOC_SH_IMM_MEDLOW16
3537 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3539 BFD_RELOC_SH_IMM_MEDHI16
3541 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3543 BFD_RELOC_SH_IMM_HI16
3545 BFD_RELOC_SH_IMM_HI16_PCREL
3549 BFD_RELOC_SH_TLS_GD_32
3551 BFD_RELOC_SH_TLS_LD_32
3553 BFD_RELOC_SH_TLS_LDO_32
3555 BFD_RELOC_SH_TLS_IE_32
3557 BFD_RELOC_SH_TLS_LE_32
3559 BFD_RELOC_SH_TLS_DTPMOD32
3561 BFD_RELOC_SH_TLS_DTPOFF32
3563 BFD_RELOC_SH_TLS_TPOFF32
3567 BFD_RELOC_SH_GOTOFF20
3569 BFD_RELOC_SH_GOTFUNCDESC
3571 BFD_RELOC_SH_GOTFUNCDESC20
3573 BFD_RELOC_SH_GOTOFFFUNCDESC
3575 BFD_RELOC_SH_GOTOFFFUNCDESC20
3577 BFD_RELOC_SH_FUNCDESC
3579 Renesas / SuperH SH relocs. Not all of these appear in object files.
3602 BFD_RELOC_ARC_SECTOFF
3604 BFD_RELOC_ARC_S21H_PCREL
3606 BFD_RELOC_ARC_S21W_PCREL
3608 BFD_RELOC_ARC_S25H_PCREL
3610 BFD_RELOC_ARC_S25W_PCREL
3614 BFD_RELOC_ARC_SDA_LDST
3616 BFD_RELOC_ARC_SDA_LDST1
3618 BFD_RELOC_ARC_SDA_LDST2
3620 BFD_RELOC_ARC_SDA16_LD
3622 BFD_RELOC_ARC_SDA16_LD1
3624 BFD_RELOC_ARC_SDA16_LD2
3626 BFD_RELOC_ARC_S13_PCREL
3632 BFD_RELOC_ARC_32_ME_S
3634 BFD_RELOC_ARC_N32_ME
3636 BFD_RELOC_ARC_SECTOFF_ME
3638 BFD_RELOC_ARC_SDA32_ME
3642 BFD_RELOC_AC_SECTOFF_U8
3644 BFD_RELOC_AC_SECTOFF_U8_1
3646 BFD_RELOC_AC_SECTOFF_U8_2
3648 BFD_RELOC_AC_SECTOFF_S9
3650 BFD_RELOC_AC_SECTOFF_S9_1
3652 BFD_RELOC_AC_SECTOFF_S9_2
3654 BFD_RELOC_ARC_SECTOFF_ME_1
3656 BFD_RELOC_ARC_SECTOFF_ME_2
3658 BFD_RELOC_ARC_SECTOFF_1
3660 BFD_RELOC_ARC_SECTOFF_2
3662 BFD_RELOC_ARC_SDA_12
3664 BFD_RELOC_ARC_SDA16_ST2
3666 BFD_RELOC_ARC_32_PCREL
3672 BFD_RELOC_ARC_GOTPC32
3678 BFD_RELOC_ARC_GLOB_DAT
3680 BFD_RELOC_ARC_JMP_SLOT
3682 BFD_RELOC_ARC_RELATIVE
3684 BFD_RELOC_ARC_GOTOFF
3688 BFD_RELOC_ARC_S21W_PCREL_PLT
3690 BFD_RELOC_ARC_S25H_PCREL_PLT
3692 BFD_RELOC_ARC_TLS_DTPMOD
3694 BFD_RELOC_ARC_TLS_TPOFF
3696 BFD_RELOC_ARC_TLS_GD_GOT
3698 BFD_RELOC_ARC_TLS_GD_LD
3700 BFD_RELOC_ARC_TLS_GD_CALL
3702 BFD_RELOC_ARC_TLS_IE_GOT
3704 BFD_RELOC_ARC_TLS_DTPOFF
3706 BFD_RELOC_ARC_TLS_DTPOFF_S9
3708 BFD_RELOC_ARC_TLS_LE_S9
3710 BFD_RELOC_ARC_TLS_LE_32
3712 BFD_RELOC_ARC_S25W_PCREL_PLT
3714 BFD_RELOC_ARC_S21H_PCREL_PLT
3716 BFD_RELOC_ARC_NPS_CMEM16
3718 BFD_RELOC_ARC_JLI_SECTOFF
3723 BFD_RELOC_BFIN_16_IMM
3725 ADI Blackfin 16 bit immediate absolute reloc.
3727 BFD_RELOC_BFIN_16_HIGH
3729 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3731 BFD_RELOC_BFIN_4_PCREL
3733 ADI Blackfin 'a' part of LSETUP.
3735 BFD_RELOC_BFIN_5_PCREL
3739 BFD_RELOC_BFIN_16_LOW
3741 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3743 BFD_RELOC_BFIN_10_PCREL
3747 BFD_RELOC_BFIN_11_PCREL
3749 ADI Blackfin 'b' part of LSETUP.
3751 BFD_RELOC_BFIN_12_PCREL_JUMP
3755 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3757 ADI Blackfin Short jump, pcrel.
3759 BFD_RELOC_BFIN_24_PCREL_CALL_X
3761 ADI Blackfin Call.x not implemented.
3763 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3765 ADI Blackfin Long Jump pcrel.
3767 BFD_RELOC_BFIN_GOT17M4
3769 BFD_RELOC_BFIN_GOTHI
3771 BFD_RELOC_BFIN_GOTLO
3773 BFD_RELOC_BFIN_FUNCDESC
3775 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3777 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3779 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3781 BFD_RELOC_BFIN_FUNCDESC_VALUE
3783 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3785 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3787 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3789 BFD_RELOC_BFIN_GOTOFF17M4
3791 BFD_RELOC_BFIN_GOTOFFHI
3793 BFD_RELOC_BFIN_GOTOFFLO
3795 ADI Blackfin FD-PIC relocations.
3799 ADI Blackfin GOT relocation.
3801 BFD_RELOC_BFIN_PLTPC
3803 ADI Blackfin PLTPC relocation.
3805 BFD_ARELOC_BFIN_PUSH
3807 ADI Blackfin arithmetic relocation.
3809 BFD_ARELOC_BFIN_CONST
3811 ADI Blackfin arithmetic relocation.
3815 ADI Blackfin arithmetic relocation.
3819 ADI Blackfin arithmetic relocation.
3821 BFD_ARELOC_BFIN_MULT
3823 ADI Blackfin arithmetic relocation.
3827 ADI Blackfin arithmetic relocation.
3831 ADI Blackfin arithmetic relocation.
3833 BFD_ARELOC_BFIN_LSHIFT
3835 ADI Blackfin arithmetic relocation.
3837 BFD_ARELOC_BFIN_RSHIFT
3839 ADI Blackfin arithmetic relocation.
3843 ADI Blackfin arithmetic relocation.
3847 ADI Blackfin arithmetic relocation.
3851 ADI Blackfin arithmetic relocation.
3853 BFD_ARELOC_BFIN_LAND
3855 ADI Blackfin arithmetic relocation.
3859 ADI Blackfin arithmetic relocation.
3863 ADI Blackfin arithmetic relocation.
3867 ADI Blackfin arithmetic relocation.
3869 BFD_ARELOC_BFIN_COMP
3871 ADI Blackfin arithmetic relocation.
3873 BFD_ARELOC_BFIN_PAGE
3875 ADI Blackfin arithmetic relocation.
3877 BFD_ARELOC_BFIN_HWPAGE
3879 ADI Blackfin arithmetic relocation.
3881 BFD_ARELOC_BFIN_ADDR
3883 ADI Blackfin arithmetic relocation.
3886 BFD_RELOC_D10V_10_PCREL_R
3888 Mitsubishi D10V relocs.
3889 This is a 10-bit reloc with the right 2 bits
3892 BFD_RELOC_D10V_10_PCREL_L
3894 Mitsubishi D10V relocs.
3895 This is a 10-bit reloc with the right 2 bits
3896 assumed to be 0. This is the same as the previous reloc
3897 except it is in the left container, i.e.,
3898 shifted left 15 bits.
3902 This is an 18-bit reloc with the right 2 bits
3905 BFD_RELOC_D10V_18_PCREL
3907 This is an 18-bit reloc with the right 2 bits
3913 Mitsubishi D30V relocs.
3914 This is a 6-bit absolute reloc.
3916 BFD_RELOC_D30V_9_PCREL
3918 This is a 6-bit pc-relative reloc with
3919 the right 3 bits assumed to be 0.
3921 BFD_RELOC_D30V_9_PCREL_R
3923 This is a 6-bit pc-relative reloc with
3924 the right 3 bits assumed to be 0. Same
3925 as the previous reloc but on the right side
3930 This is a 12-bit absolute reloc with the
3931 right 3 bitsassumed to be 0.
3933 BFD_RELOC_D30V_15_PCREL
3935 This is a 12-bit pc-relative reloc with
3936 the right 3 bits assumed to be 0.
3938 BFD_RELOC_D30V_15_PCREL_R
3940 This is a 12-bit pc-relative reloc with
3941 the right 3 bits assumed to be 0. Same
3942 as the previous reloc but on the right side
3947 This is an 18-bit absolute reloc with
3948 the right 3 bits assumed to be 0.
3950 BFD_RELOC_D30V_21_PCREL
3952 This is an 18-bit pc-relative reloc with
3953 the right 3 bits assumed to be 0.
3955 BFD_RELOC_D30V_21_PCREL_R
3957 This is an 18-bit pc-relative reloc with
3958 the right 3 bits assumed to be 0. Same
3959 as the previous reloc but on the right side
3964 This is a 32-bit absolute reloc.
3966 BFD_RELOC_D30V_32_PCREL
3968 This is a 32-bit pc-relative reloc.
3971 BFD_RELOC_DLX_HI16_S
3986 BFD_RELOC_M32C_RL_JUMP
3988 BFD_RELOC_M32C_RL_1ADDR
3990 BFD_RELOC_M32C_RL_2ADDR
3992 Renesas M16C/M32C Relocations.
3997 Renesas M32R (formerly Mitsubishi M32R) relocs.
3998 This is a 24 bit absolute address.
4000 BFD_RELOC_M32R_10_PCREL
4002 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4004 BFD_RELOC_M32R_18_PCREL
4006 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4008 BFD_RELOC_M32R_26_PCREL
4010 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4012 BFD_RELOC_M32R_HI16_ULO
4014 This is a 16-bit reloc containing the high 16 bits of an address
4015 used when the lower 16 bits are treated as unsigned.
4017 BFD_RELOC_M32R_HI16_SLO
4019 This is a 16-bit reloc containing the high 16 bits of an address
4020 used when the lower 16 bits are treated as signed.
4024 This is a 16-bit reloc containing the lower 16 bits of an address.
4026 BFD_RELOC_M32R_SDA16
4028 This is a 16-bit reloc containing the small data area offset for use in
4029 add3, load, and store instructions.
4031 BFD_RELOC_M32R_GOT24
4033 BFD_RELOC_M32R_26_PLTREL
4037 BFD_RELOC_M32R_GLOB_DAT
4039 BFD_RELOC_M32R_JMP_SLOT
4041 BFD_RELOC_M32R_RELATIVE
4043 BFD_RELOC_M32R_GOTOFF
4045 BFD_RELOC_M32R_GOTOFF_HI_ULO
4047 BFD_RELOC_M32R_GOTOFF_HI_SLO
4049 BFD_RELOC_M32R_GOTOFF_LO
4051 BFD_RELOC_M32R_GOTPC24
4053 BFD_RELOC_M32R_GOT16_HI_ULO
4055 BFD_RELOC_M32R_GOT16_HI_SLO
4057 BFD_RELOC_M32R_GOT16_LO
4059 BFD_RELOC_M32R_GOTPC_HI_ULO
4061 BFD_RELOC_M32R_GOTPC_HI_SLO
4063 BFD_RELOC_M32R_GOTPC_LO
4072 This is a 20 bit absolute address.
4074 BFD_RELOC_NDS32_9_PCREL
4076 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4078 BFD_RELOC_NDS32_WORD_9_PCREL
4080 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4082 BFD_RELOC_NDS32_15_PCREL
4084 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4086 BFD_RELOC_NDS32_17_PCREL
4088 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4090 BFD_RELOC_NDS32_25_PCREL
4092 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4094 BFD_RELOC_NDS32_HI20
4096 This is a 20-bit reloc containing the high 20 bits of an address
4097 used with the lower 12 bits
4099 BFD_RELOC_NDS32_LO12S3
4101 This is a 12-bit reloc containing the lower 12 bits of an address
4102 then shift right by 3. This is used with ldi,sdi...
4104 BFD_RELOC_NDS32_LO12S2
4106 This is a 12-bit reloc containing the lower 12 bits of an address
4107 then shift left by 2. This is used with lwi,swi...
4109 BFD_RELOC_NDS32_LO12S1
4111 This is a 12-bit reloc containing the lower 12 bits of an address
4112 then shift left by 1. This is used with lhi,shi...
4114 BFD_RELOC_NDS32_LO12S0
4116 This is a 12-bit reloc containing the lower 12 bits of an address
4117 then shift left by 0. This is used with lbisbi...
4119 BFD_RELOC_NDS32_LO12S0_ORI
4121 This is a 12-bit reloc containing the lower 12 bits of an address
4122 then shift left by 0. This is only used with branch relaxations
4124 BFD_RELOC_NDS32_SDA15S3
4126 This is a 15-bit reloc containing the small data area 18-bit signed offset
4127 and shift left by 3 for use in ldi, sdi...
4129 BFD_RELOC_NDS32_SDA15S2
4131 This is a 15-bit reloc containing the small data area 17-bit signed offset
4132 and shift left by 2 for use in lwi, swi...
4134 BFD_RELOC_NDS32_SDA15S1
4136 This is a 15-bit reloc containing the small data area 16-bit signed offset
4137 and shift left by 1 for use in lhi, shi...
4139 BFD_RELOC_NDS32_SDA15S0
4141 This is a 15-bit reloc containing the small data area 15-bit signed offset
4142 and shift left by 0 for use in lbi, sbi...
4144 BFD_RELOC_NDS32_SDA16S3
4146 This is a 16-bit reloc containing the small data area 16-bit signed offset
4149 BFD_RELOC_NDS32_SDA17S2
4151 This is a 17-bit reloc containing the small data area 17-bit signed offset
4152 and shift left by 2 for use in lwi.gp, swi.gp...
4154 BFD_RELOC_NDS32_SDA18S1
4156 This is a 18-bit reloc containing the small data area 18-bit signed offset
4157 and shift left by 1 for use in lhi.gp, shi.gp...
4159 BFD_RELOC_NDS32_SDA19S0
4161 This is a 19-bit reloc containing the small data area 19-bit signed offset
4162 and shift left by 0 for use in lbi.gp, sbi.gp...
4164 BFD_RELOC_NDS32_GOT20
4166 BFD_RELOC_NDS32_9_PLTREL
4168 BFD_RELOC_NDS32_25_PLTREL
4170 BFD_RELOC_NDS32_COPY
4172 BFD_RELOC_NDS32_GLOB_DAT
4174 BFD_RELOC_NDS32_JMP_SLOT
4176 BFD_RELOC_NDS32_RELATIVE
4178 BFD_RELOC_NDS32_GOTOFF
4180 BFD_RELOC_NDS32_GOTOFF_HI20
4182 BFD_RELOC_NDS32_GOTOFF_LO12
4184 BFD_RELOC_NDS32_GOTPC20
4186 BFD_RELOC_NDS32_GOT_HI20
4188 BFD_RELOC_NDS32_GOT_LO12
4190 BFD_RELOC_NDS32_GOTPC_HI20
4192 BFD_RELOC_NDS32_GOTPC_LO12
4196 BFD_RELOC_NDS32_INSN16
4198 BFD_RELOC_NDS32_LABEL
4200 BFD_RELOC_NDS32_LONGCALL1
4202 BFD_RELOC_NDS32_LONGCALL2
4204 BFD_RELOC_NDS32_LONGCALL3
4206 BFD_RELOC_NDS32_LONGJUMP1
4208 BFD_RELOC_NDS32_LONGJUMP2
4210 BFD_RELOC_NDS32_LONGJUMP3
4212 BFD_RELOC_NDS32_LOADSTORE
4214 BFD_RELOC_NDS32_9_FIXED
4216 BFD_RELOC_NDS32_15_FIXED
4218 BFD_RELOC_NDS32_17_FIXED
4220 BFD_RELOC_NDS32_25_FIXED
4222 BFD_RELOC_NDS32_LONGCALL4
4224 BFD_RELOC_NDS32_LONGCALL5
4226 BFD_RELOC_NDS32_LONGCALL6
4228 BFD_RELOC_NDS32_LONGJUMP4
4230 BFD_RELOC_NDS32_LONGJUMP5
4232 BFD_RELOC_NDS32_LONGJUMP6
4234 BFD_RELOC_NDS32_LONGJUMP7
4238 BFD_RELOC_NDS32_PLTREL_HI20
4240 BFD_RELOC_NDS32_PLTREL_LO12
4242 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4244 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4248 BFD_RELOC_NDS32_SDA12S2_DP
4250 BFD_RELOC_NDS32_SDA12S2_SP
4252 BFD_RELOC_NDS32_LO12S2_DP
4254 BFD_RELOC_NDS32_LO12S2_SP
4258 BFD_RELOC_NDS32_DWARF2_OP1
4260 BFD_RELOC_NDS32_DWARF2_OP2
4262 BFD_RELOC_NDS32_DWARF2_LEB
4264 for dwarf2 debug_line.
4266 BFD_RELOC_NDS32_UPDATE_TA
4268 for eliminate 16-bit instructions
4270 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4272 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4274 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4276 BFD_RELOC_NDS32_GOT_LO15
4278 BFD_RELOC_NDS32_GOT_LO19
4280 BFD_RELOC_NDS32_GOTOFF_LO15
4282 BFD_RELOC_NDS32_GOTOFF_LO19
4284 BFD_RELOC_NDS32_GOT15S2
4286 BFD_RELOC_NDS32_GOT17S2
4288 for PIC object relaxation
4293 This is a 5 bit absolute address.
4295 BFD_RELOC_NDS32_10_UPCREL
4297 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4299 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4301 If fp were omitted, fp can used as another gp.
4303 BFD_RELOC_NDS32_RELAX_ENTRY
4305 BFD_RELOC_NDS32_GOT_SUFF
4307 BFD_RELOC_NDS32_GOTOFF_SUFF
4309 BFD_RELOC_NDS32_PLT_GOT_SUFF
4311 BFD_RELOC_NDS32_MULCALL_SUFF
4315 BFD_RELOC_NDS32_PTR_COUNT
4317 BFD_RELOC_NDS32_PTR_RESOLVED
4319 BFD_RELOC_NDS32_PLTBLOCK
4321 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4323 BFD_RELOC_NDS32_RELAX_REGION_END
4325 BFD_RELOC_NDS32_MINUEND
4327 BFD_RELOC_NDS32_SUBTRAHEND
4329 BFD_RELOC_NDS32_DIFF8
4331 BFD_RELOC_NDS32_DIFF16
4333 BFD_RELOC_NDS32_DIFF32
4335 BFD_RELOC_NDS32_DIFF_ULEB128
4337 BFD_RELOC_NDS32_EMPTY
4339 relaxation relative relocation types
4341 BFD_RELOC_NDS32_25_ABS
4343 This is a 25 bit absolute address.
4345 BFD_RELOC_NDS32_DATA
4347 BFD_RELOC_NDS32_TRAN
4349 BFD_RELOC_NDS32_17IFC_PCREL
4351 BFD_RELOC_NDS32_10IFCU_PCREL
4353 For ex9 and ifc using.
4355 BFD_RELOC_NDS32_TPOFF
4357 BFD_RELOC_NDS32_GOTTPOFF
4359 BFD_RELOC_NDS32_TLS_LE_HI20
4361 BFD_RELOC_NDS32_TLS_LE_LO12
4363 BFD_RELOC_NDS32_TLS_LE_20
4365 BFD_RELOC_NDS32_TLS_LE_15S0
4367 BFD_RELOC_NDS32_TLS_LE_15S1
4369 BFD_RELOC_NDS32_TLS_LE_15S2
4371 BFD_RELOC_NDS32_TLS_LE_ADD
4373 BFD_RELOC_NDS32_TLS_LE_LS
4375 BFD_RELOC_NDS32_TLS_IE_HI20
4377 BFD_RELOC_NDS32_TLS_IE_LO12
4379 BFD_RELOC_NDS32_TLS_IE_LO12S2
4381 BFD_RELOC_NDS32_TLS_IEGP_HI20
4383 BFD_RELOC_NDS32_TLS_IEGP_LO12
4385 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4387 BFD_RELOC_NDS32_TLS_IEGP_LW
4389 BFD_RELOC_NDS32_TLS_DESC
4391 BFD_RELOC_NDS32_TLS_DESC_HI20
4393 BFD_RELOC_NDS32_TLS_DESC_LO12
4395 BFD_RELOC_NDS32_TLS_DESC_20
4397 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4399 BFD_RELOC_NDS32_TLS_DESC_ADD
4401 BFD_RELOC_NDS32_TLS_DESC_FUNC
4403 BFD_RELOC_NDS32_TLS_DESC_CALL
4405 BFD_RELOC_NDS32_TLS_DESC_MEM
4407 BFD_RELOC_NDS32_REMOVE
4409 BFD_RELOC_NDS32_GROUP
4415 For floating load store relaxation.
4419 BFD_RELOC_V850_9_PCREL
4421 This is a 9-bit reloc
4423 BFD_RELOC_V850_22_PCREL
4425 This is a 22-bit reloc
4428 BFD_RELOC_V850_SDA_16_16_OFFSET
4430 This is a 16 bit offset from the short data area pointer.
4432 BFD_RELOC_V850_SDA_15_16_OFFSET
4434 This is a 16 bit offset (of which only 15 bits are used) from the
4435 short data area pointer.
4437 BFD_RELOC_V850_ZDA_16_16_OFFSET
4439 This is a 16 bit offset from the zero data area pointer.
4441 BFD_RELOC_V850_ZDA_15_16_OFFSET
4443 This is a 16 bit offset (of which only 15 bits are used) from the
4444 zero data area pointer.
4446 BFD_RELOC_V850_TDA_6_8_OFFSET
4448 This is an 8 bit offset (of which only 6 bits are used) from the
4449 tiny data area pointer.
4451 BFD_RELOC_V850_TDA_7_8_OFFSET
4453 This is an 8bit offset (of which only 7 bits are used) from the tiny
4456 BFD_RELOC_V850_TDA_7_7_OFFSET
4458 This is a 7 bit offset from the tiny data area pointer.
4460 BFD_RELOC_V850_TDA_16_16_OFFSET
4462 This is a 16 bit offset from the tiny data area pointer.
4465 BFD_RELOC_V850_TDA_4_5_OFFSET
4467 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4470 BFD_RELOC_V850_TDA_4_4_OFFSET
4472 This is a 4 bit offset from the tiny data area pointer.
4474 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4476 This is a 16 bit offset from the short data area pointer, with the
4477 bits placed non-contiguously in the instruction.
4479 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4481 This is a 16 bit offset from the zero data area pointer, with the
4482 bits placed non-contiguously in the instruction.
4484 BFD_RELOC_V850_CALLT_6_7_OFFSET
4486 This is a 6 bit offset from the call table base pointer.
4488 BFD_RELOC_V850_CALLT_16_16_OFFSET
4490 This is a 16 bit offset from the call table base pointer.
4492 BFD_RELOC_V850_LONGCALL
4494 Used for relaxing indirect function calls.
4496 BFD_RELOC_V850_LONGJUMP
4498 Used for relaxing indirect jumps.
4500 BFD_RELOC_V850_ALIGN
4502 Used to maintain alignment whilst relaxing.
4504 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4506 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4509 BFD_RELOC_V850_16_PCREL
4511 This is a 16-bit reloc.
4513 BFD_RELOC_V850_17_PCREL
4515 This is a 17-bit reloc.
4519 This is a 23-bit reloc.
4521 BFD_RELOC_V850_32_PCREL
4523 This is a 32-bit reloc.
4525 BFD_RELOC_V850_32_ABS
4527 This is a 32-bit reloc.
4529 BFD_RELOC_V850_16_SPLIT_OFFSET
4531 This is a 16-bit reloc.
4533 BFD_RELOC_V850_16_S1
4535 This is a 16-bit reloc.
4537 BFD_RELOC_V850_LO16_S1
4539 Low 16 bits. 16 bit shifted by 1.
4541 BFD_RELOC_V850_CALLT_15_16_OFFSET
4543 This is a 16 bit offset from the call table base pointer.
4545 BFD_RELOC_V850_32_GOTPCREL
4549 BFD_RELOC_V850_16_GOT
4553 BFD_RELOC_V850_32_GOT
4557 BFD_RELOC_V850_22_PLT_PCREL
4561 BFD_RELOC_V850_32_PLT_PCREL
4569 BFD_RELOC_V850_GLOB_DAT
4573 BFD_RELOC_V850_JMP_SLOT
4577 BFD_RELOC_V850_RELATIVE
4581 BFD_RELOC_V850_16_GOTOFF
4585 BFD_RELOC_V850_32_GOTOFF
4600 This is a 8bit DP reloc for the tms320c30, where the most
4601 significant 8 bits of a 24 bit word are placed into the least
4602 significant 8 bits of the opcode.
4605 BFD_RELOC_TIC54X_PARTLS7
4607 This is a 7bit reloc for the tms320c54x, where the least
4608 significant 7 bits of a 16 bit word are placed into the least
4609 significant 7 bits of the opcode.
4612 BFD_RELOC_TIC54X_PARTMS9
4614 This is a 9bit DP reloc for the tms320c54x, where the most
4615 significant 9 bits of a 16 bit word are placed into the least
4616 significant 9 bits of the opcode.
4621 This is an extended address 23-bit reloc for the tms320c54x.
4624 BFD_RELOC_TIC54X_16_OF_23
4626 This is a 16-bit reloc for the tms320c54x, where the least
4627 significant 16 bits of a 23-bit extended address are placed into
4631 BFD_RELOC_TIC54X_MS7_OF_23
4633 This is a reloc for the tms320c54x, where the most
4634 significant 7 bits of a 23-bit extended address are placed into
4638 BFD_RELOC_C6000_PCR_S21
4640 BFD_RELOC_C6000_PCR_S12
4642 BFD_RELOC_C6000_PCR_S10
4644 BFD_RELOC_C6000_PCR_S7
4646 BFD_RELOC_C6000_ABS_S16
4648 BFD_RELOC_C6000_ABS_L16
4650 BFD_RELOC_C6000_ABS_H16
4652 BFD_RELOC_C6000_SBR_U15_B
4654 BFD_RELOC_C6000_SBR_U15_H
4656 BFD_RELOC_C6000_SBR_U15_W
4658 BFD_RELOC_C6000_SBR_S16
4660 BFD_RELOC_C6000_SBR_L16_B
4662 BFD_RELOC_C6000_SBR_L16_H
4664 BFD_RELOC_C6000_SBR_L16_W
4666 BFD_RELOC_C6000_SBR_H16_B
4668 BFD_RELOC_C6000_SBR_H16_H
4670 BFD_RELOC_C6000_SBR_H16_W
4672 BFD_RELOC_C6000_SBR_GOT_U15_W
4674 BFD_RELOC_C6000_SBR_GOT_L16_W
4676 BFD_RELOC_C6000_SBR_GOT_H16_W
4678 BFD_RELOC_C6000_DSBT_INDEX
4680 BFD_RELOC_C6000_PREL31
4682 BFD_RELOC_C6000_COPY
4684 BFD_RELOC_C6000_JUMP_SLOT
4686 BFD_RELOC_C6000_EHTYPE
4688 BFD_RELOC_C6000_PCR_H16
4690 BFD_RELOC_C6000_PCR_L16
4692 BFD_RELOC_C6000_ALIGN
4694 BFD_RELOC_C6000_FPHEAD
4696 BFD_RELOC_C6000_NOCMP
4698 TMS320C6000 relocations.
4703 This is a 48 bit reloc for the FR30 that stores 32 bits.
4707 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4710 BFD_RELOC_FR30_6_IN_4
4712 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4715 BFD_RELOC_FR30_8_IN_8
4717 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4720 BFD_RELOC_FR30_9_IN_8
4722 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4725 BFD_RELOC_FR30_10_IN_8
4727 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4730 BFD_RELOC_FR30_9_PCREL
4732 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4733 short offset into 8 bits.
4735 BFD_RELOC_FR30_12_PCREL
4737 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4738 short offset into 11 bits.
4741 BFD_RELOC_MCORE_PCREL_IMM8BY4
4743 BFD_RELOC_MCORE_PCREL_IMM11BY2
4745 BFD_RELOC_MCORE_PCREL_IMM4BY2
4747 BFD_RELOC_MCORE_PCREL_32
4749 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4753 Motorola Mcore relocations.
4762 BFD_RELOC_MEP_PCREL8A2
4764 BFD_RELOC_MEP_PCREL12A2
4766 BFD_RELOC_MEP_PCREL17A2
4768 BFD_RELOC_MEP_PCREL24A2
4770 BFD_RELOC_MEP_PCABS24A2
4782 BFD_RELOC_MEP_TPREL7
4784 BFD_RELOC_MEP_TPREL7A2
4786 BFD_RELOC_MEP_TPREL7A4
4788 BFD_RELOC_MEP_UIMM24
4790 BFD_RELOC_MEP_ADDR24A4
4792 BFD_RELOC_MEP_GNU_VTINHERIT
4794 BFD_RELOC_MEP_GNU_VTENTRY
4796 Toshiba Media Processor Relocations.
4800 BFD_RELOC_METAG_HIADDR16
4802 BFD_RELOC_METAG_LOADDR16
4804 BFD_RELOC_METAG_RELBRANCH
4806 BFD_RELOC_METAG_GETSETOFF
4808 BFD_RELOC_METAG_HIOG
4810 BFD_RELOC_METAG_LOOG
4812 BFD_RELOC_METAG_REL8
4814 BFD_RELOC_METAG_REL16
4816 BFD_RELOC_METAG_HI16_GOTOFF
4818 BFD_RELOC_METAG_LO16_GOTOFF
4820 BFD_RELOC_METAG_GETSET_GOTOFF
4822 BFD_RELOC_METAG_GETSET_GOT
4824 BFD_RELOC_METAG_HI16_GOTPC
4826 BFD_RELOC_METAG_LO16_GOTPC
4828 BFD_RELOC_METAG_HI16_PLT
4830 BFD_RELOC_METAG_LO16_PLT
4832 BFD_RELOC_METAG_RELBRANCH_PLT
4834 BFD_RELOC_METAG_GOTOFF
4838 BFD_RELOC_METAG_COPY
4840 BFD_RELOC_METAG_JMP_SLOT
4842 BFD_RELOC_METAG_RELATIVE
4844 BFD_RELOC_METAG_GLOB_DAT
4846 BFD_RELOC_METAG_TLS_GD
4848 BFD_RELOC_METAG_TLS_LDM
4850 BFD_RELOC_METAG_TLS_LDO_HI16
4852 BFD_RELOC_METAG_TLS_LDO_LO16
4854 BFD_RELOC_METAG_TLS_LDO
4856 BFD_RELOC_METAG_TLS_IE
4858 BFD_RELOC_METAG_TLS_IENONPIC
4860 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4862 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4864 BFD_RELOC_METAG_TLS_TPOFF
4866 BFD_RELOC_METAG_TLS_DTPMOD
4868 BFD_RELOC_METAG_TLS_DTPOFF
4870 BFD_RELOC_METAG_TLS_LE
4872 BFD_RELOC_METAG_TLS_LE_HI16
4874 BFD_RELOC_METAG_TLS_LE_LO16
4876 Imagination Technologies Meta relocations.
4881 BFD_RELOC_MMIX_GETA_1
4883 BFD_RELOC_MMIX_GETA_2
4885 BFD_RELOC_MMIX_GETA_3
4887 These are relocations for the GETA instruction.
4889 BFD_RELOC_MMIX_CBRANCH
4891 BFD_RELOC_MMIX_CBRANCH_J
4893 BFD_RELOC_MMIX_CBRANCH_1
4895 BFD_RELOC_MMIX_CBRANCH_2
4897 BFD_RELOC_MMIX_CBRANCH_3
4899 These are relocations for a conditional branch instruction.
4901 BFD_RELOC_MMIX_PUSHJ
4903 BFD_RELOC_MMIX_PUSHJ_1
4905 BFD_RELOC_MMIX_PUSHJ_2
4907 BFD_RELOC_MMIX_PUSHJ_3
4909 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4911 These are relocations for the PUSHJ instruction.
4915 BFD_RELOC_MMIX_JMP_1
4917 BFD_RELOC_MMIX_JMP_2
4919 BFD_RELOC_MMIX_JMP_3
4921 These are relocations for the JMP instruction.
4923 BFD_RELOC_MMIX_ADDR19
4925 This is a relocation for a relative address as in a GETA instruction or
4928 BFD_RELOC_MMIX_ADDR27
4930 This is a relocation for a relative address as in a JMP instruction.
4932 BFD_RELOC_MMIX_REG_OR_BYTE
4934 This is a relocation for an instruction field that may be a general
4935 register or a value 0..255.
4939 This is a relocation for an instruction field that may be a general
4942 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4944 This is a relocation for two instruction fields holding a register and
4945 an offset, the equivalent of the relocation.
4947 BFD_RELOC_MMIX_LOCAL
4949 This relocation is an assertion that the expression is not allocated as
4950 a global register. It does not modify contents.
4953 BFD_RELOC_AVR_7_PCREL
4955 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4956 short offset into 7 bits.
4958 BFD_RELOC_AVR_13_PCREL
4960 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4961 short offset into 12 bits.
4965 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4966 program memory address) into 16 bits.
4968 BFD_RELOC_AVR_LO8_LDI
4970 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4971 data memory address) into 8 bit immediate value of LDI insn.
4973 BFD_RELOC_AVR_HI8_LDI
4975 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4976 of data memory address) into 8 bit immediate value of LDI insn.
4978 BFD_RELOC_AVR_HH8_LDI
4980 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4981 of program memory address) into 8 bit immediate value of LDI insn.
4983 BFD_RELOC_AVR_MS8_LDI
4985 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4986 of 32 bit value) into 8 bit immediate value of LDI insn.
4988 BFD_RELOC_AVR_LO8_LDI_NEG
4990 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4991 (usually data memory address) into 8 bit immediate value of SUBI insn.
4993 BFD_RELOC_AVR_HI8_LDI_NEG
4995 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4996 (high 8 bit of data memory address) into 8 bit immediate value of
4999 BFD_RELOC_AVR_HH8_LDI_NEG
5001 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5002 (most high 8 bit of program memory address) into 8 bit immediate value
5003 of LDI or SUBI insn.
5005 BFD_RELOC_AVR_MS8_LDI_NEG
5007 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5008 of 32 bit value) into 8 bit immediate value of LDI insn.
5010 BFD_RELOC_AVR_LO8_LDI_PM
5012 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5013 command address) into 8 bit immediate value of LDI insn.
5015 BFD_RELOC_AVR_LO8_LDI_GS
5017 This is a 16 bit reloc for the AVR that stores 8 bit value
5018 (command address) into 8 bit immediate value of LDI insn. If the address
5019 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5022 BFD_RELOC_AVR_HI8_LDI_PM
5024 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5025 of command address) into 8 bit immediate value of LDI insn.
5027 BFD_RELOC_AVR_HI8_LDI_GS
5029 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5030 of command address) into 8 bit immediate value of LDI insn. If the address
5031 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5034 BFD_RELOC_AVR_HH8_LDI_PM
5036 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5037 of command address) into 8 bit immediate value of LDI insn.
5039 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5041 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5042 (usually command address) into 8 bit immediate value of SUBI insn.
5044 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5046 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5047 (high 8 bit of 16 bit command address) into 8 bit immediate value
5050 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5052 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5053 (high 6 bit of 22 bit command address) into 8 bit immediate
5058 This is a 32 bit reloc for the AVR that stores 23 bit value
5063 This is a 16 bit reloc for the AVR that stores all needed bits
5064 for absolute addressing with ldi with overflow check to linktime
5068 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5071 BFD_RELOC_AVR_6_ADIW
5073 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5078 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5079 in .byte lo8(symbol)
5083 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5084 in .byte hi8(symbol)
5088 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5089 in .byte hlo8(symbol)
5093 BFD_RELOC_AVR_DIFF16
5095 BFD_RELOC_AVR_DIFF32
5097 AVR relocations to mark the difference of two local symbols.
5098 These are only needed to support linker relaxation and can be ignored
5099 when not relaxing. The field is set to the value of the difference
5100 assuming no relaxation. The relocation encodes the position of the
5101 second symbol so the linker can determine whether to adjust the field
5104 BFD_RELOC_AVR_LDS_STS_16
5106 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5107 lds and sts instructions supported only tiny core.
5111 This is a 6 bit reloc for the AVR that stores an I/O register
5112 number for the IN and OUT instructions
5116 This is a 5 bit reloc for the AVR that stores an I/O register
5117 number for the SBIC, SBIS, SBI and CBI instructions
5120 BFD_RELOC_RISCV_HI20
5122 BFD_RELOC_RISCV_PCREL_HI20
5124 BFD_RELOC_RISCV_PCREL_LO12_I
5126 BFD_RELOC_RISCV_PCREL_LO12_S
5128 BFD_RELOC_RISCV_LO12_I
5130 BFD_RELOC_RISCV_LO12_S
5132 BFD_RELOC_RISCV_GPREL12_I
5134 BFD_RELOC_RISCV_GPREL12_S
5136 BFD_RELOC_RISCV_TPREL_HI20
5138 BFD_RELOC_RISCV_TPREL_LO12_I
5140 BFD_RELOC_RISCV_TPREL_LO12_S
5142 BFD_RELOC_RISCV_TPREL_ADD
5144 BFD_RELOC_RISCV_CALL
5146 BFD_RELOC_RISCV_CALL_PLT
5148 BFD_RELOC_RISCV_ADD8
5150 BFD_RELOC_RISCV_ADD16
5152 BFD_RELOC_RISCV_ADD32
5154 BFD_RELOC_RISCV_ADD64
5156 BFD_RELOC_RISCV_SUB8
5158 BFD_RELOC_RISCV_SUB16
5160 BFD_RELOC_RISCV_SUB32
5162 BFD_RELOC_RISCV_SUB64
5164 BFD_RELOC_RISCV_GOT_HI20
5166 BFD_RELOC_RISCV_TLS_GOT_HI20
5168 BFD_RELOC_RISCV_TLS_GD_HI20
5172 BFD_RELOC_RISCV_TLS_DTPMOD32
5174 BFD_RELOC_RISCV_TLS_DTPREL32
5176 BFD_RELOC_RISCV_TLS_DTPMOD64
5178 BFD_RELOC_RISCV_TLS_DTPREL64
5180 BFD_RELOC_RISCV_TLS_TPREL32
5182 BFD_RELOC_RISCV_TLS_TPREL64
5184 BFD_RELOC_RISCV_ALIGN
5186 BFD_RELOC_RISCV_RVC_BRANCH
5188 BFD_RELOC_RISCV_RVC_JUMP
5190 BFD_RELOC_RISCV_RVC_LUI
5192 BFD_RELOC_RISCV_GPREL_I
5194 BFD_RELOC_RISCV_GPREL_S
5196 BFD_RELOC_RISCV_TPREL_I
5198 BFD_RELOC_RISCV_TPREL_S
5200 BFD_RELOC_RISCV_RELAX
5204 BFD_RELOC_RISCV_SUB6
5206 BFD_RELOC_RISCV_SET6
5208 BFD_RELOC_RISCV_SET8
5210 BFD_RELOC_RISCV_SET16
5212 BFD_RELOC_RISCV_SET32
5214 BFD_RELOC_RISCV_32_PCREL
5221 BFD_RELOC_RL78_NEG16
5223 BFD_RELOC_RL78_NEG24
5225 BFD_RELOC_RL78_NEG32
5227 BFD_RELOC_RL78_16_OP
5229 BFD_RELOC_RL78_24_OP
5231 BFD_RELOC_RL78_32_OP
5239 BFD_RELOC_RL78_DIR3U_PCREL
5243 BFD_RELOC_RL78_GPRELB
5245 BFD_RELOC_RL78_GPRELW
5247 BFD_RELOC_RL78_GPRELL
5251 BFD_RELOC_RL78_OP_SUBTRACT
5253 BFD_RELOC_RL78_OP_NEG
5255 BFD_RELOC_RL78_OP_AND
5257 BFD_RELOC_RL78_OP_SHRA
5261 BFD_RELOC_RL78_ABS16
5263 BFD_RELOC_RL78_ABS16_REV
5265 BFD_RELOC_RL78_ABS32
5267 BFD_RELOC_RL78_ABS32_REV
5269 BFD_RELOC_RL78_ABS16U
5271 BFD_RELOC_RL78_ABS16UW
5273 BFD_RELOC_RL78_ABS16UL
5275 BFD_RELOC_RL78_RELAX
5285 BFD_RELOC_RL78_SADDR
5287 Renesas RL78 Relocations.
5310 BFD_RELOC_RX_DIR3U_PCREL
5322 BFD_RELOC_RX_OP_SUBTRACT
5330 BFD_RELOC_RX_ABS16_REV
5334 BFD_RELOC_RX_ABS32_REV
5338 BFD_RELOC_RX_ABS16UW
5340 BFD_RELOC_RX_ABS16UL
5344 Renesas RX Relocations.
5357 32 bit PC relative PLT address.
5361 Copy symbol at runtime.
5363 BFD_RELOC_390_GLOB_DAT
5367 BFD_RELOC_390_JMP_SLOT
5371 BFD_RELOC_390_RELATIVE
5373 Adjust by program base.
5377 32 bit PC relative offset to GOT.
5383 BFD_RELOC_390_PC12DBL
5385 PC relative 12 bit shifted by 1.
5387 BFD_RELOC_390_PLT12DBL
5389 12 bit PC rel. PLT shifted by 1.
5391 BFD_RELOC_390_PC16DBL
5393 PC relative 16 bit shifted by 1.
5395 BFD_RELOC_390_PLT16DBL
5397 16 bit PC rel. PLT shifted by 1.
5399 BFD_RELOC_390_PC24DBL
5401 PC relative 24 bit shifted by 1.
5403 BFD_RELOC_390_PLT24DBL
5405 24 bit PC rel. PLT shifted by 1.
5407 BFD_RELOC_390_PC32DBL
5409 PC relative 32 bit shifted by 1.
5411 BFD_RELOC_390_PLT32DBL
5413 32 bit PC rel. PLT shifted by 1.
5415 BFD_RELOC_390_GOTPCDBL
5417 32 bit PC rel. GOT shifted by 1.
5425 64 bit PC relative PLT address.
5427 BFD_RELOC_390_GOTENT
5429 32 bit rel. offset to GOT entry.
5431 BFD_RELOC_390_GOTOFF64
5433 64 bit offset to GOT.
5435 BFD_RELOC_390_GOTPLT12
5437 12-bit offset to symbol-entry within GOT, with PLT handling.
5439 BFD_RELOC_390_GOTPLT16
5441 16-bit offset to symbol-entry within GOT, with PLT handling.
5443 BFD_RELOC_390_GOTPLT32
5445 32-bit offset to symbol-entry within GOT, with PLT handling.
5447 BFD_RELOC_390_GOTPLT64
5449 64-bit offset to symbol-entry within GOT, with PLT handling.
5451 BFD_RELOC_390_GOTPLTENT
5453 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5455 BFD_RELOC_390_PLTOFF16
5457 16-bit rel. offset from the GOT to a PLT entry.
5459 BFD_RELOC_390_PLTOFF32
5461 32-bit rel. offset from the GOT to a PLT entry.
5463 BFD_RELOC_390_PLTOFF64
5465 64-bit rel. offset from the GOT to a PLT entry.
5468 BFD_RELOC_390_TLS_LOAD
5470 BFD_RELOC_390_TLS_GDCALL
5472 BFD_RELOC_390_TLS_LDCALL
5474 BFD_RELOC_390_TLS_GD32
5476 BFD_RELOC_390_TLS_GD64
5478 BFD_RELOC_390_TLS_GOTIE12
5480 BFD_RELOC_390_TLS_GOTIE32
5482 BFD_RELOC_390_TLS_GOTIE64
5484 BFD_RELOC_390_TLS_LDM32
5486 BFD_RELOC_390_TLS_LDM64
5488 BFD_RELOC_390_TLS_IE32
5490 BFD_RELOC_390_TLS_IE64
5492 BFD_RELOC_390_TLS_IEENT
5494 BFD_RELOC_390_TLS_LE32
5496 BFD_RELOC_390_TLS_LE64
5498 BFD_RELOC_390_TLS_LDO32
5500 BFD_RELOC_390_TLS_LDO64
5502 BFD_RELOC_390_TLS_DTPMOD
5504 BFD_RELOC_390_TLS_DTPOFF
5506 BFD_RELOC_390_TLS_TPOFF
5508 s390 tls relocations.
5515 BFD_RELOC_390_GOTPLT20
5517 BFD_RELOC_390_TLS_GOTIE20
5519 Long displacement extension.
5522 BFD_RELOC_390_IRELATIVE
5524 STT_GNU_IFUNC relocation.
5527 BFD_RELOC_SCORE_GPREL15
5530 Low 16 bit for load/store
5532 BFD_RELOC_SCORE_DUMMY2
5536 This is a 24-bit reloc with the right 1 bit assumed to be 0
5538 BFD_RELOC_SCORE_BRANCH
5540 This is a 19-bit reloc with the right 1 bit assumed to be 0
5542 BFD_RELOC_SCORE_IMM30
5544 This is a 32-bit reloc for 48-bit instructions.
5546 BFD_RELOC_SCORE_IMM32
5548 This is a 32-bit reloc for 48-bit instructions.
5550 BFD_RELOC_SCORE16_JMP
5552 This is a 11-bit reloc with the right 1 bit assumed to be 0
5554 BFD_RELOC_SCORE16_BRANCH
5556 This is a 8-bit reloc with the right 1 bit assumed to be 0
5558 BFD_RELOC_SCORE_BCMP
5560 This is a 9-bit reloc with the right 1 bit assumed to be 0
5562 BFD_RELOC_SCORE_GOT15
5564 BFD_RELOC_SCORE_GOT_LO16
5566 BFD_RELOC_SCORE_CALL15
5568 BFD_RELOC_SCORE_DUMMY_HI16
5570 Undocumented Score relocs
5575 Scenix IP2K - 9-bit register number / data address
5579 Scenix IP2K - 4-bit register/data bank number
5581 BFD_RELOC_IP2K_ADDR16CJP
5583 Scenix IP2K - low 13 bits of instruction word address
5585 BFD_RELOC_IP2K_PAGE3
5587 Scenix IP2K - high 3 bits of instruction word address
5589 BFD_RELOC_IP2K_LO8DATA
5591 BFD_RELOC_IP2K_HI8DATA
5593 BFD_RELOC_IP2K_EX8DATA
5595 Scenix IP2K - ext/low/high 8 bits of data address
5597 BFD_RELOC_IP2K_LO8INSN
5599 BFD_RELOC_IP2K_HI8INSN
5601 Scenix IP2K - low/high 8 bits of instruction word address
5603 BFD_RELOC_IP2K_PC_SKIP
5605 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5609 Scenix IP2K - 16 bit word address in text section.
5611 BFD_RELOC_IP2K_FR_OFFSET
5613 Scenix IP2K - 7-bit sp or dp offset
5615 BFD_RELOC_VPE4KMATH_DATA
5617 BFD_RELOC_VPE4KMATH_INSN
5619 Scenix VPE4K coprocessor - data/insn-space addressing
5622 BFD_RELOC_VTABLE_INHERIT
5624 BFD_RELOC_VTABLE_ENTRY
5626 These two relocations are used by the linker to determine which of
5627 the entries in a C++ virtual function table are actually used. When
5628 the --gc-sections option is given, the linker will zero out the entries
5629 that are not used, so that the code for those functions need not be
5630 included in the output.
5632 VTABLE_INHERIT is a zero-space relocation used to describe to the
5633 linker the inheritance tree of a C++ virtual function table. The
5634 relocation's symbol should be the parent class' vtable, and the
5635 relocation should be located at the child vtable.
5637 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5638 virtual function table entry. The reloc's symbol should refer to the
5639 table of the class mentioned in the code. Off of that base, an offset
5640 describes the entry that is being used. For Rela hosts, this offset
5641 is stored in the reloc's addend. For Rel hosts, we are forced to put
5642 this offset in the reloc's section offset.
5645 BFD_RELOC_IA64_IMM14
5647 BFD_RELOC_IA64_IMM22
5649 BFD_RELOC_IA64_IMM64
5651 BFD_RELOC_IA64_DIR32MSB
5653 BFD_RELOC_IA64_DIR32LSB
5655 BFD_RELOC_IA64_DIR64MSB
5657 BFD_RELOC_IA64_DIR64LSB
5659 BFD_RELOC_IA64_GPREL22
5661 BFD_RELOC_IA64_GPREL64I
5663 BFD_RELOC_IA64_GPREL32MSB
5665 BFD_RELOC_IA64_GPREL32LSB
5667 BFD_RELOC_IA64_GPREL64MSB
5669 BFD_RELOC_IA64_GPREL64LSB
5671 BFD_RELOC_IA64_LTOFF22
5673 BFD_RELOC_IA64_LTOFF64I
5675 BFD_RELOC_IA64_PLTOFF22
5677 BFD_RELOC_IA64_PLTOFF64I
5679 BFD_RELOC_IA64_PLTOFF64MSB
5681 BFD_RELOC_IA64_PLTOFF64LSB
5683 BFD_RELOC_IA64_FPTR64I
5685 BFD_RELOC_IA64_FPTR32MSB
5687 BFD_RELOC_IA64_FPTR32LSB
5689 BFD_RELOC_IA64_FPTR64MSB
5691 BFD_RELOC_IA64_FPTR64LSB
5693 BFD_RELOC_IA64_PCREL21B
5695 BFD_RELOC_IA64_PCREL21BI
5697 BFD_RELOC_IA64_PCREL21M
5699 BFD_RELOC_IA64_PCREL21F
5701 BFD_RELOC_IA64_PCREL22
5703 BFD_RELOC_IA64_PCREL60B
5705 BFD_RELOC_IA64_PCREL64I
5707 BFD_RELOC_IA64_PCREL32MSB
5709 BFD_RELOC_IA64_PCREL32LSB
5711 BFD_RELOC_IA64_PCREL64MSB
5713 BFD_RELOC_IA64_PCREL64LSB
5715 BFD_RELOC_IA64_LTOFF_FPTR22
5717 BFD_RELOC_IA64_LTOFF_FPTR64I
5719 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5721 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5723 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5725 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5727 BFD_RELOC_IA64_SEGREL32MSB
5729 BFD_RELOC_IA64_SEGREL32LSB
5731 BFD_RELOC_IA64_SEGREL64MSB
5733 BFD_RELOC_IA64_SEGREL64LSB
5735 BFD_RELOC_IA64_SECREL32MSB
5737 BFD_RELOC_IA64_SECREL32LSB
5739 BFD_RELOC_IA64_SECREL64MSB
5741 BFD_RELOC_IA64_SECREL64LSB
5743 BFD_RELOC_IA64_REL32MSB
5745 BFD_RELOC_IA64_REL32LSB
5747 BFD_RELOC_IA64_REL64MSB
5749 BFD_RELOC_IA64_REL64LSB
5751 BFD_RELOC_IA64_LTV32MSB
5753 BFD_RELOC_IA64_LTV32LSB
5755 BFD_RELOC_IA64_LTV64MSB
5757 BFD_RELOC_IA64_LTV64LSB
5759 BFD_RELOC_IA64_IPLTMSB
5761 BFD_RELOC_IA64_IPLTLSB
5765 BFD_RELOC_IA64_LTOFF22X
5767 BFD_RELOC_IA64_LDXMOV
5769 BFD_RELOC_IA64_TPREL14
5771 BFD_RELOC_IA64_TPREL22
5773 BFD_RELOC_IA64_TPREL64I
5775 BFD_RELOC_IA64_TPREL64MSB
5777 BFD_RELOC_IA64_TPREL64LSB
5779 BFD_RELOC_IA64_LTOFF_TPREL22
5781 BFD_RELOC_IA64_DTPMOD64MSB
5783 BFD_RELOC_IA64_DTPMOD64LSB
5785 BFD_RELOC_IA64_LTOFF_DTPMOD22
5787 BFD_RELOC_IA64_DTPREL14
5789 BFD_RELOC_IA64_DTPREL22
5791 BFD_RELOC_IA64_DTPREL64I
5793 BFD_RELOC_IA64_DTPREL32MSB
5795 BFD_RELOC_IA64_DTPREL32LSB
5797 BFD_RELOC_IA64_DTPREL64MSB
5799 BFD_RELOC_IA64_DTPREL64LSB
5801 BFD_RELOC_IA64_LTOFF_DTPREL22
5803 Intel IA64 Relocations.
5806 BFD_RELOC_M68HC11_HI8
5808 Motorola 68HC11 reloc.
5809 This is the 8 bit high part of an absolute address.
5811 BFD_RELOC_M68HC11_LO8
5813 Motorola 68HC11 reloc.
5814 This is the 8 bit low part of an absolute address.
5816 BFD_RELOC_M68HC11_3B
5818 Motorola 68HC11 reloc.
5819 This is the 3 bit of a value.
5821 BFD_RELOC_M68HC11_RL_JUMP
5823 Motorola 68HC11 reloc.
5824 This reloc marks the beginning of a jump/call instruction.
5825 It is used for linker relaxation to correctly identify beginning
5826 of instruction and change some branches to use PC-relative
5829 BFD_RELOC_M68HC11_RL_GROUP
5831 Motorola 68HC11 reloc.
5832 This reloc marks a group of several instructions that gcc generates
5833 and for which the linker relaxation pass can modify and/or remove
5836 BFD_RELOC_M68HC11_LO16
5838 Motorola 68HC11 reloc.
5839 This is the 16-bit lower part of an address. It is used for 'call'
5840 instruction to specify the symbol address without any special
5841 transformation (due to memory bank window).
5843 BFD_RELOC_M68HC11_PAGE
5845 Motorola 68HC11 reloc.
5846 This is a 8-bit reloc that specifies the page number of an address.
5847 It is used by 'call' instruction to specify the page number of
5850 BFD_RELOC_M68HC11_24
5852 Motorola 68HC11 reloc.
5853 This is a 24-bit reloc that represents the address with a 16-bit
5854 value and a 8-bit page number. The symbol address is transformed
5855 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5857 BFD_RELOC_M68HC12_5B
5859 Motorola 68HC12 reloc.
5860 This is the 5 bits of a value.
5862 BFD_RELOC_XGATE_RL_JUMP
5864 Freescale XGATE reloc.
5865 This reloc marks the beginning of a bra/jal instruction.
5867 BFD_RELOC_XGATE_RL_GROUP
5869 Freescale XGATE reloc.
5870 This reloc marks a group of several instructions that gcc generates
5871 and for which the linker relaxation pass can modify and/or remove
5874 BFD_RELOC_XGATE_LO16
5876 Freescale XGATE reloc.
5877 This is the 16-bit lower part of an address. It is used for the '16-bit'
5880 BFD_RELOC_XGATE_GPAGE
5882 Freescale XGATE reloc.
5886 Freescale XGATE reloc.
5888 BFD_RELOC_XGATE_PCREL_9
5890 Freescale XGATE reloc.
5891 This is a 9-bit pc-relative reloc.
5893 BFD_RELOC_XGATE_PCREL_10
5895 Freescale XGATE reloc.
5896 This is a 10-bit pc-relative reloc.
5898 BFD_RELOC_XGATE_IMM8_LO
5900 Freescale XGATE reloc.
5901 This is the 16-bit lower part of an address. It is used for the '16-bit'
5904 BFD_RELOC_XGATE_IMM8_HI
5906 Freescale XGATE reloc.
5907 This is the 16-bit higher part of an address. It is used for the '16-bit'
5910 BFD_RELOC_XGATE_IMM3
5912 Freescale XGATE reloc.
5913 This is a 3-bit pc-relative reloc.
5915 BFD_RELOC_XGATE_IMM4
5917 Freescale XGATE reloc.
5918 This is a 4-bit pc-relative reloc.
5920 BFD_RELOC_XGATE_IMM5
5922 Freescale XGATE reloc.
5923 This is a 5-bit pc-relative reloc.
5925 BFD_RELOC_M68HC12_9B
5927 Motorola 68HC12 reloc.
5928 This is the 9 bits of a value.
5930 BFD_RELOC_M68HC12_16B
5932 Motorola 68HC12 reloc.
5933 This is the 16 bits of a value.
5935 BFD_RELOC_M68HC12_9_PCREL
5937 Motorola 68HC12/XGATE reloc.
5938 This is a PCREL9 branch.
5940 BFD_RELOC_M68HC12_10_PCREL
5942 Motorola 68HC12/XGATE reloc.
5943 This is a PCREL10 branch.
5945 BFD_RELOC_M68HC12_LO8XG
5947 Motorola 68HC12/XGATE reloc.
5948 This is the 8 bit low part of an absolute address and immediately precedes
5949 a matching HI8XG part.
5951 BFD_RELOC_M68HC12_HI8XG
5953 Motorola 68HC12/XGATE reloc.
5954 This is the 8 bit high part of an absolute address and immediately follows
5955 a matching LO8XG part.
5957 BFD_RELOC_S12Z_15_PCREL
5959 Freescale S12Z reloc.
5960 This is a 15 bit relative address. If the most significant bits are all zero
5961 then it may be truncated to 8 bits.
5966 BFD_RELOC_CR16_NUM16
5968 BFD_RELOC_CR16_NUM32
5970 BFD_RELOC_CR16_NUM32a
5972 BFD_RELOC_CR16_REGREL0
5974 BFD_RELOC_CR16_REGREL4
5976 BFD_RELOC_CR16_REGREL4a
5978 BFD_RELOC_CR16_REGREL14
5980 BFD_RELOC_CR16_REGREL14a
5982 BFD_RELOC_CR16_REGREL16
5984 BFD_RELOC_CR16_REGREL20
5986 BFD_RELOC_CR16_REGREL20a
5988 BFD_RELOC_CR16_ABS20
5990 BFD_RELOC_CR16_ABS24
5996 BFD_RELOC_CR16_IMM16
5998 BFD_RELOC_CR16_IMM20
6000 BFD_RELOC_CR16_IMM24
6002 BFD_RELOC_CR16_IMM32
6004 BFD_RELOC_CR16_IMM32a
6006 BFD_RELOC_CR16_DISP4
6008 BFD_RELOC_CR16_DISP8
6010 BFD_RELOC_CR16_DISP16
6012 BFD_RELOC_CR16_DISP20
6014 BFD_RELOC_CR16_DISP24
6016 BFD_RELOC_CR16_DISP24a
6018 BFD_RELOC_CR16_SWITCH8
6020 BFD_RELOC_CR16_SWITCH16
6022 BFD_RELOC_CR16_SWITCH32
6024 BFD_RELOC_CR16_GOT_REGREL20
6026 BFD_RELOC_CR16_GOTC_REGREL20
6028 BFD_RELOC_CR16_GLOB_DAT
6030 NS CR16 Relocations.
6037 BFD_RELOC_CRX_REL8_CMP
6045 BFD_RELOC_CRX_REGREL12
6047 BFD_RELOC_CRX_REGREL22
6049 BFD_RELOC_CRX_REGREL28
6051 BFD_RELOC_CRX_REGREL32
6067 BFD_RELOC_CRX_SWITCH8
6069 BFD_RELOC_CRX_SWITCH16
6071 BFD_RELOC_CRX_SWITCH32
6076 BFD_RELOC_CRIS_BDISP8
6078 BFD_RELOC_CRIS_UNSIGNED_5
6080 BFD_RELOC_CRIS_SIGNED_6
6082 BFD_RELOC_CRIS_UNSIGNED_6
6084 BFD_RELOC_CRIS_SIGNED_8
6086 BFD_RELOC_CRIS_UNSIGNED_8
6088 BFD_RELOC_CRIS_SIGNED_16
6090 BFD_RELOC_CRIS_UNSIGNED_16
6092 BFD_RELOC_CRIS_LAPCQ_OFFSET
6094 BFD_RELOC_CRIS_UNSIGNED_4
6096 These relocs are only used within the CRIS assembler. They are not
6097 (at present) written to any object files.
6101 BFD_RELOC_CRIS_GLOB_DAT
6103 BFD_RELOC_CRIS_JUMP_SLOT
6105 BFD_RELOC_CRIS_RELATIVE
6107 Relocs used in ELF shared libraries for CRIS.
6109 BFD_RELOC_CRIS_32_GOT
6111 32-bit offset to symbol-entry within GOT.
6113 BFD_RELOC_CRIS_16_GOT
6115 16-bit offset to symbol-entry within GOT.
6117 BFD_RELOC_CRIS_32_GOTPLT
6119 32-bit offset to symbol-entry within GOT, with PLT handling.
6121 BFD_RELOC_CRIS_16_GOTPLT
6123 16-bit offset to symbol-entry within GOT, with PLT handling.
6125 BFD_RELOC_CRIS_32_GOTREL
6127 32-bit offset to symbol, relative to GOT.
6129 BFD_RELOC_CRIS_32_PLT_GOTREL
6131 32-bit offset to symbol with PLT entry, relative to GOT.
6133 BFD_RELOC_CRIS_32_PLT_PCREL
6135 32-bit offset to symbol with PLT entry, relative to this relocation.
6138 BFD_RELOC_CRIS_32_GOT_GD
6140 BFD_RELOC_CRIS_16_GOT_GD
6142 BFD_RELOC_CRIS_32_GD
6146 BFD_RELOC_CRIS_32_DTPREL
6148 BFD_RELOC_CRIS_16_DTPREL
6150 BFD_RELOC_CRIS_32_GOT_TPREL
6152 BFD_RELOC_CRIS_16_GOT_TPREL
6154 BFD_RELOC_CRIS_32_TPREL
6156 BFD_RELOC_CRIS_16_TPREL
6158 BFD_RELOC_CRIS_DTPMOD
6160 BFD_RELOC_CRIS_32_IE
6162 Relocs used in TLS code for CRIS.
6165 BFD_RELOC_OR1K_REL_26
6167 BFD_RELOC_OR1K_SLO16
6169 BFD_RELOC_OR1K_PCREL_PG21
6173 BFD_RELOC_OR1K_SLO13
6175 BFD_RELOC_OR1K_GOTPC_HI16
6177 BFD_RELOC_OR1K_GOTPC_LO16
6179 BFD_RELOC_OR1K_GOT16
6181 BFD_RELOC_OR1K_GOT_PG21
6183 BFD_RELOC_OR1K_GOT_LO13
6185 BFD_RELOC_OR1K_PLT26
6187 BFD_RELOC_OR1K_PLTA26
6189 BFD_RELOC_OR1K_GOTOFF_SLO16
6193 BFD_RELOC_OR1K_GLOB_DAT
6195 BFD_RELOC_OR1K_JMP_SLOT
6197 BFD_RELOC_OR1K_RELATIVE
6199 BFD_RELOC_OR1K_TLS_GD_HI16
6201 BFD_RELOC_OR1K_TLS_GD_LO16
6203 BFD_RELOC_OR1K_TLS_GD_PG21
6205 BFD_RELOC_OR1K_TLS_GD_LO13
6207 BFD_RELOC_OR1K_TLS_LDM_HI16
6209 BFD_RELOC_OR1K_TLS_LDM_LO16
6211 BFD_RELOC_OR1K_TLS_LDM_PG21
6213 BFD_RELOC_OR1K_TLS_LDM_LO13
6215 BFD_RELOC_OR1K_TLS_LDO_HI16
6217 BFD_RELOC_OR1K_TLS_LDO_LO16
6219 BFD_RELOC_OR1K_TLS_IE_HI16
6221 BFD_RELOC_OR1K_TLS_IE_AHI16
6223 BFD_RELOC_OR1K_TLS_IE_LO16
6225 BFD_RELOC_OR1K_TLS_IE_PG21
6227 BFD_RELOC_OR1K_TLS_IE_LO13
6229 BFD_RELOC_OR1K_TLS_LE_HI16
6231 BFD_RELOC_OR1K_TLS_LE_AHI16
6233 BFD_RELOC_OR1K_TLS_LE_LO16
6235 BFD_RELOC_OR1K_TLS_LE_SLO16
6237 BFD_RELOC_OR1K_TLS_TPOFF
6239 BFD_RELOC_OR1K_TLS_DTPOFF
6241 BFD_RELOC_OR1K_TLS_DTPMOD
6243 OpenRISC 1000 Relocations.
6246 BFD_RELOC_H8_DIR16A8
6248 BFD_RELOC_H8_DIR16R8
6250 BFD_RELOC_H8_DIR24A8
6252 BFD_RELOC_H8_DIR24R8
6254 BFD_RELOC_H8_DIR32A16
6256 BFD_RELOC_H8_DISP32A16
6261 BFD_RELOC_XSTORMY16_REL_12
6263 BFD_RELOC_XSTORMY16_12
6265 BFD_RELOC_XSTORMY16_24
6267 BFD_RELOC_XSTORMY16_FPTR16
6269 Sony Xstormy16 Relocations.
6274 Self-describing complex relocations.
6286 Infineon Relocations.
6289 BFD_RELOC_VAX_GLOB_DAT
6291 BFD_RELOC_VAX_JMP_SLOT
6293 BFD_RELOC_VAX_RELATIVE
6295 Relocations used by VAX ELF.
6300 Morpho MT - 16 bit immediate relocation.
6304 Morpho MT - Hi 16 bits of an address.
6308 Morpho MT - Low 16 bits of an address.
6310 BFD_RELOC_MT_GNU_VTINHERIT
6312 Morpho MT - Used to tell the linker which vtable entries are used.
6314 BFD_RELOC_MT_GNU_VTENTRY
6316 Morpho MT - Used to tell the linker which vtable entries are used.
6318 BFD_RELOC_MT_PCINSN8
6320 Morpho MT - 8 bit immediate relocation.
6323 BFD_RELOC_MSP430_10_PCREL
6325 BFD_RELOC_MSP430_16_PCREL
6329 BFD_RELOC_MSP430_16_PCREL_BYTE
6331 BFD_RELOC_MSP430_16_BYTE
6333 BFD_RELOC_MSP430_2X_PCREL
6335 BFD_RELOC_MSP430_RL_PCREL
6337 BFD_RELOC_MSP430_ABS8
6339 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6341 BFD_RELOC_MSP430X_PCR20_EXT_DST
6343 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6345 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6347 BFD_RELOC_MSP430X_ABS20_EXT_DST
6349 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6351 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6353 BFD_RELOC_MSP430X_ABS20_ADR_DST
6355 BFD_RELOC_MSP430X_PCR16
6357 BFD_RELOC_MSP430X_PCR20_CALL
6359 BFD_RELOC_MSP430X_ABS16
6361 BFD_RELOC_MSP430_ABS_HI16
6363 BFD_RELOC_MSP430_PREL31
6365 BFD_RELOC_MSP430_SYM_DIFF
6367 msp430 specific relocation codes
6374 BFD_RELOC_NIOS2_CALL26
6376 BFD_RELOC_NIOS2_IMM5
6378 BFD_RELOC_NIOS2_CACHE_OPX
6380 BFD_RELOC_NIOS2_IMM6
6382 BFD_RELOC_NIOS2_IMM8
6384 BFD_RELOC_NIOS2_HI16
6386 BFD_RELOC_NIOS2_LO16
6388 BFD_RELOC_NIOS2_HIADJ16
6390 BFD_RELOC_NIOS2_GPREL
6392 BFD_RELOC_NIOS2_UJMP
6394 BFD_RELOC_NIOS2_CJMP
6396 BFD_RELOC_NIOS2_CALLR
6398 BFD_RELOC_NIOS2_ALIGN
6400 BFD_RELOC_NIOS2_GOT16
6402 BFD_RELOC_NIOS2_CALL16
6404 BFD_RELOC_NIOS2_GOTOFF_LO
6406 BFD_RELOC_NIOS2_GOTOFF_HA
6408 BFD_RELOC_NIOS2_PCREL_LO
6410 BFD_RELOC_NIOS2_PCREL_HA
6412 BFD_RELOC_NIOS2_TLS_GD16
6414 BFD_RELOC_NIOS2_TLS_LDM16
6416 BFD_RELOC_NIOS2_TLS_LDO16
6418 BFD_RELOC_NIOS2_TLS_IE16
6420 BFD_RELOC_NIOS2_TLS_LE16
6422 BFD_RELOC_NIOS2_TLS_DTPMOD
6424 BFD_RELOC_NIOS2_TLS_DTPREL
6426 BFD_RELOC_NIOS2_TLS_TPREL
6428 BFD_RELOC_NIOS2_COPY
6430 BFD_RELOC_NIOS2_GLOB_DAT
6432 BFD_RELOC_NIOS2_JUMP_SLOT
6434 BFD_RELOC_NIOS2_RELATIVE
6436 BFD_RELOC_NIOS2_GOTOFF
6438 BFD_RELOC_NIOS2_CALL26_NOAT
6440 BFD_RELOC_NIOS2_GOT_LO
6442 BFD_RELOC_NIOS2_GOT_HA
6444 BFD_RELOC_NIOS2_CALL_LO
6446 BFD_RELOC_NIOS2_CALL_HA
6448 BFD_RELOC_NIOS2_R2_S12
6450 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6452 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6454 BFD_RELOC_NIOS2_R2_T1I7_2
6456 BFD_RELOC_NIOS2_R2_T2I4
6458 BFD_RELOC_NIOS2_R2_T2I4_1
6460 BFD_RELOC_NIOS2_R2_T2I4_2
6462 BFD_RELOC_NIOS2_R2_X1I7_2
6464 BFD_RELOC_NIOS2_R2_X2L5
6466 BFD_RELOC_NIOS2_R2_F1I5_2
6468 BFD_RELOC_NIOS2_R2_L5I4X1
6470 BFD_RELOC_NIOS2_R2_T1X1I6
6472 BFD_RELOC_NIOS2_R2_T1X1I6_2
6474 Relocations used by the Altera Nios II core.
6479 PRU LDI 16-bit unsigned data-memory relocation.
6481 BFD_RELOC_PRU_U16_PMEMIMM
6483 PRU LDI 16-bit unsigned instruction-memory relocation.
6487 PRU relocation for two consecutive LDI load instructions that load a
6488 32 bit value into a register. If the higher bits are all zero, then
6489 the second instruction may be relaxed.
6491 BFD_RELOC_PRU_S10_PCREL
6493 PRU QBBx 10-bit signed PC-relative relocation.
6495 BFD_RELOC_PRU_U8_PCREL
6497 PRU 8-bit unsigned relocation used for the LOOP instruction.
6499 BFD_RELOC_PRU_32_PMEM
6501 BFD_RELOC_PRU_16_PMEM
6503 PRU Program Memory relocations. Used to convert from byte addressing to
6504 32-bit word addressing.
6506 BFD_RELOC_PRU_GNU_DIFF8
6508 BFD_RELOC_PRU_GNU_DIFF16
6510 BFD_RELOC_PRU_GNU_DIFF32
6512 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6514 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6516 PRU relocations to mark the difference of two local symbols.
6517 These are only needed to support linker relaxation and can be ignored
6518 when not relaxing. The field is set to the value of the difference
6519 assuming no relaxation. The relocation encodes the position of the
6520 second symbol so the linker can determine whether to adjust the field
6521 value. The PMEM variants encode the word difference, instead of byte
6522 difference between symbols.
6525 BFD_RELOC_IQ2000_OFFSET_16
6527 BFD_RELOC_IQ2000_OFFSET_21
6529 BFD_RELOC_IQ2000_UHI16
6534 BFD_RELOC_XTENSA_RTLD
6536 Special Xtensa relocation used only by PLT entries in ELF shared
6537 objects to indicate that the runtime linker should set the value
6538 to one of its own internal functions or data structures.
6540 BFD_RELOC_XTENSA_GLOB_DAT
6542 BFD_RELOC_XTENSA_JMP_SLOT
6544 BFD_RELOC_XTENSA_RELATIVE
6546 Xtensa relocations for ELF shared objects.
6548 BFD_RELOC_XTENSA_PLT
6550 Xtensa relocation used in ELF object files for symbols that may require
6551 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6553 BFD_RELOC_XTENSA_DIFF8
6555 BFD_RELOC_XTENSA_DIFF16
6557 BFD_RELOC_XTENSA_DIFF32
6559 Xtensa relocations to mark the difference of two local symbols.
6560 These are only needed to support linker relaxation and can be ignored
6561 when not relaxing. The field is set to the value of the difference
6562 assuming no relaxation. The relocation encodes the position of the
6563 first symbol so the linker can determine whether to adjust the field
6566 BFD_RELOC_XTENSA_SLOT0_OP
6568 BFD_RELOC_XTENSA_SLOT1_OP
6570 BFD_RELOC_XTENSA_SLOT2_OP
6572 BFD_RELOC_XTENSA_SLOT3_OP
6574 BFD_RELOC_XTENSA_SLOT4_OP
6576 BFD_RELOC_XTENSA_SLOT5_OP
6578 BFD_RELOC_XTENSA_SLOT6_OP
6580 BFD_RELOC_XTENSA_SLOT7_OP
6582 BFD_RELOC_XTENSA_SLOT8_OP
6584 BFD_RELOC_XTENSA_SLOT9_OP
6586 BFD_RELOC_XTENSA_SLOT10_OP
6588 BFD_RELOC_XTENSA_SLOT11_OP
6590 BFD_RELOC_XTENSA_SLOT12_OP
6592 BFD_RELOC_XTENSA_SLOT13_OP
6594 BFD_RELOC_XTENSA_SLOT14_OP
6596 Generic Xtensa relocations for instruction operands. Only the slot
6597 number is encoded in the relocation. The relocation applies to the
6598 last PC-relative immediate operand, or if there are no PC-relative
6599 immediates, to the last immediate operand.
6601 BFD_RELOC_XTENSA_SLOT0_ALT
6603 BFD_RELOC_XTENSA_SLOT1_ALT
6605 BFD_RELOC_XTENSA_SLOT2_ALT
6607 BFD_RELOC_XTENSA_SLOT3_ALT
6609 BFD_RELOC_XTENSA_SLOT4_ALT
6611 BFD_RELOC_XTENSA_SLOT5_ALT
6613 BFD_RELOC_XTENSA_SLOT6_ALT
6615 BFD_RELOC_XTENSA_SLOT7_ALT
6617 BFD_RELOC_XTENSA_SLOT8_ALT
6619 BFD_RELOC_XTENSA_SLOT9_ALT
6621 BFD_RELOC_XTENSA_SLOT10_ALT
6623 BFD_RELOC_XTENSA_SLOT11_ALT
6625 BFD_RELOC_XTENSA_SLOT12_ALT
6627 BFD_RELOC_XTENSA_SLOT13_ALT
6629 BFD_RELOC_XTENSA_SLOT14_ALT
6631 Alternate Xtensa relocations. Only the slot is encoded in the
6632 relocation. The meaning of these relocations is opcode-specific.
6634 BFD_RELOC_XTENSA_OP0
6636 BFD_RELOC_XTENSA_OP1
6638 BFD_RELOC_XTENSA_OP2
6640 Xtensa relocations for backward compatibility. These have all been
6641 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6643 BFD_RELOC_XTENSA_ASM_EXPAND
6645 Xtensa relocation to mark that the assembler expanded the
6646 instructions from an original target. The expansion size is
6647 encoded in the reloc size.
6649 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6651 Xtensa relocation to mark that the linker should simplify
6652 assembler-expanded instructions. This is commonly used
6653 internally by the linker after analysis of a
6654 BFD_RELOC_XTENSA_ASM_EXPAND.
6656 BFD_RELOC_XTENSA_TLSDESC_FN
6658 BFD_RELOC_XTENSA_TLSDESC_ARG
6660 BFD_RELOC_XTENSA_TLS_DTPOFF
6662 BFD_RELOC_XTENSA_TLS_TPOFF
6664 BFD_RELOC_XTENSA_TLS_FUNC
6666 BFD_RELOC_XTENSA_TLS_ARG
6668 BFD_RELOC_XTENSA_TLS_CALL
6670 Xtensa TLS relocations.
6675 8 bit signed offset in (ix+d) or (iy+d).
6679 First 8 bits of multibyte (32, 24 or 16 bit) value.
6683 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6687 Third 8 bits of multibyte (32 or 24 bit) value.
6691 Fourth 8 bits of multibyte (32 bit) value.
6695 Lowest 16 bits of multibyte (32 or 24 bit) value.
6699 Highest 16 bits of multibyte (32 or 24 bit) value.
6703 Like BFD_RELOC_16 but big-endian.
6721 BFD_RELOC_LM32_BRANCH
6723 BFD_RELOC_LM32_16_GOT
6725 BFD_RELOC_LM32_GOTOFF_HI16
6727 BFD_RELOC_LM32_GOTOFF_LO16
6731 BFD_RELOC_LM32_GLOB_DAT
6733 BFD_RELOC_LM32_JMP_SLOT
6735 BFD_RELOC_LM32_RELATIVE
6737 Lattice Mico32 relocations.
6740 BFD_RELOC_MACH_O_SECTDIFF
6742 Difference between two section addreses. Must be followed by a
6743 BFD_RELOC_MACH_O_PAIR.
6745 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6747 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6749 BFD_RELOC_MACH_O_PAIR
6751 Pair of relocation. Contains the first symbol.
6753 BFD_RELOC_MACH_O_SUBTRACTOR32
6755 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6757 BFD_RELOC_MACH_O_SUBTRACTOR64
6759 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6762 BFD_RELOC_MACH_O_X86_64_BRANCH32
6764 BFD_RELOC_MACH_O_X86_64_BRANCH8
6766 PCREL relocations. They are marked as branch to create PLT entry if
6769 BFD_RELOC_MACH_O_X86_64_GOT
6771 Used when referencing a GOT entry.
6773 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6775 Used when loading a GOT entry with movq. It is specially marked so that
6776 the linker could optimize the movq to a leaq if possible.
6778 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6780 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6782 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6784 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6786 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6788 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6790 BFD_RELOC_MACH_O_X86_64_TLV
6792 Used when referencing a TLV entry.
6796 BFD_RELOC_MACH_O_ARM64_ADDEND
6798 Addend for PAGE or PAGEOFF.
6800 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6802 Relative offset to page of GOT slot.
6804 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6806 Relative offset within page of GOT slot.
6808 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6810 Address of a GOT entry.
6813 BFD_RELOC_MICROBLAZE_32_LO
6815 This is a 32 bit reloc for the microblaze that stores the
6816 low 16 bits of a value
6818 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6820 This is a 32 bit pc-relative reloc for the microblaze that
6821 stores the low 16 bits of a value
6823 BFD_RELOC_MICROBLAZE_32_ROSDA
6825 This is a 32 bit reloc for the microblaze that stores a
6826 value relative to the read-only small data area anchor
6828 BFD_RELOC_MICROBLAZE_32_RWSDA
6830 This is a 32 bit reloc for the microblaze that stores a
6831 value relative to the read-write small data area anchor
6833 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6835 This is a 32 bit reloc for the microblaze to handle
6836 expressions of the form "Symbol Op Symbol"
6838 BFD_RELOC_MICROBLAZE_64_NONE
6840 This is a 64 bit reloc that stores the 32 bit pc relative
6841 value in two words (with an imm instruction). No relocation is
6842 done here - only used for relaxing
6844 BFD_RELOC_MICROBLAZE_64_GOTPC
6846 This is a 64 bit reloc that stores the 32 bit pc relative
6847 value in two words (with an imm instruction). The relocation is
6848 PC-relative GOT offset
6850 BFD_RELOC_MICROBLAZE_64_GOT
6852 This is a 64 bit reloc that stores the 32 bit pc relative
6853 value in two words (with an imm instruction). The relocation is
6856 BFD_RELOC_MICROBLAZE_64_PLT
6858 This is a 64 bit reloc that stores the 32 bit pc relative
6859 value in two words (with an imm instruction). The relocation is
6860 PC-relative offset into PLT
6862 BFD_RELOC_MICROBLAZE_64_GOTOFF
6864 This is a 64 bit reloc that stores the 32 bit GOT relative
6865 value in two words (with an imm instruction). The relocation is
6866 relative offset from _GLOBAL_OFFSET_TABLE_
6868 BFD_RELOC_MICROBLAZE_32_GOTOFF
6870 This is a 32 bit reloc that stores the 32 bit GOT relative
6871 value in a word. The relocation is relative offset from
6872 _GLOBAL_OFFSET_TABLE_
6874 BFD_RELOC_MICROBLAZE_COPY
6876 This is used to tell the dynamic linker to copy the value out of
6877 the dynamic object into the runtime process image.
6879 BFD_RELOC_MICROBLAZE_64_TLS
6883 BFD_RELOC_MICROBLAZE_64_TLSGD
6885 This is a 64 bit reloc that stores the 32 bit GOT relative value
6886 of the GOT TLS GD info entry in two words (with an imm instruction). The
6887 relocation is GOT offset.
6889 BFD_RELOC_MICROBLAZE_64_TLSLD
6891 This is a 64 bit reloc that stores the 32 bit GOT relative value
6892 of the GOT TLS LD info entry in two words (with an imm instruction). The
6893 relocation is GOT offset.
6895 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6897 This is a 32 bit reloc that stores the Module ID to GOT(n).
6899 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6901 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6903 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6905 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6908 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6910 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6911 to two words (uses imm instruction).
6913 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6915 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6916 to two words (uses imm instruction).
6918 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6920 This is a 64 bit reloc that stores the 32 bit pc relative
6921 value in two words (with an imm instruction). The relocation is
6922 PC-relative offset from start of TEXT.
6924 BFD_RELOC_MICROBLAZE_64_TEXTREL
6926 This is a 64 bit reloc that stores the 32 bit offset
6927 value in two words (with an imm instruction). The relocation is
6928 relative offset from start of TEXT.
6931 BFD_RELOC_AARCH64_RELOC_START
6933 AArch64 pseudo relocation code to mark the start of the AArch64
6934 relocation enumerators. N.B. the order of the enumerators is
6935 important as several tables in the AArch64 bfd backend are indexed
6936 by these enumerators; make sure they are all synced.
6938 BFD_RELOC_AARCH64_NULL
6940 Deprecated AArch64 null relocation code.
6942 BFD_RELOC_AARCH64_NONE
6944 AArch64 null relocation code.
6946 BFD_RELOC_AARCH64_64
6948 BFD_RELOC_AARCH64_32
6950 BFD_RELOC_AARCH64_16
6952 Basic absolute relocations of N bits. These are equivalent to
6953 BFD_RELOC_N and they were added to assist the indexing of the howto
6956 BFD_RELOC_AARCH64_64_PCREL
6958 BFD_RELOC_AARCH64_32_PCREL
6960 BFD_RELOC_AARCH64_16_PCREL
6962 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6963 and they were added to assist the indexing of the howto table.
6965 BFD_RELOC_AARCH64_MOVW_G0
6967 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6968 of an unsigned address/value.
6970 BFD_RELOC_AARCH64_MOVW_G0_NC
6972 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6973 an address/value. No overflow checking.
6975 BFD_RELOC_AARCH64_MOVW_G1
6977 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6978 of an unsigned address/value.
6980 BFD_RELOC_AARCH64_MOVW_G1_NC
6982 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6983 of an address/value. No overflow checking.
6985 BFD_RELOC_AARCH64_MOVW_G2
6987 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6988 of an unsigned address/value.
6990 BFD_RELOC_AARCH64_MOVW_G2_NC
6992 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6993 of an address/value. No overflow checking.
6995 BFD_RELOC_AARCH64_MOVW_G3
6997 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6998 of a signed or unsigned address/value.
7000 BFD_RELOC_AARCH64_MOVW_G0_S
7002 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7003 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7006 BFD_RELOC_AARCH64_MOVW_G1_S
7008 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7009 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7012 BFD_RELOC_AARCH64_MOVW_G2_S
7014 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7015 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7018 BFD_RELOC_AARCH64_MOVW_PREL_G0
7020 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7021 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7024 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7026 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7027 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7030 BFD_RELOC_AARCH64_MOVW_PREL_G1
7032 AArch64 MOVK instruction with most significant bits 16 to 31
7035 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7037 AArch64 MOVK instruction with most significant bits 16 to 31
7040 BFD_RELOC_AARCH64_MOVW_PREL_G2
7042 AArch64 MOVK instruction with most significant bits 32 to 47
7045 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7047 AArch64 MOVK instruction with most significant bits 32 to 47
7050 BFD_RELOC_AARCH64_MOVW_PREL_G3
7052 AArch64 MOVK instruction with most significant bits 47 to 63
7055 BFD_RELOC_AARCH64_LD_LO19_PCREL
7057 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7058 offset. The lowest two bits must be zero and are not stored in the
7059 instruction, giving a 21 bit signed byte offset.
7061 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7063 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7065 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7067 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7068 offset, giving a 4KB aligned page base address.
7070 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7072 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7073 offset, giving a 4KB aligned page base address, but with no overflow
7076 BFD_RELOC_AARCH64_ADD_LO12
7078 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7079 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7081 BFD_RELOC_AARCH64_LDST8_LO12
7083 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7084 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7086 BFD_RELOC_AARCH64_TSTBR14
7088 AArch64 14 bit pc-relative test bit and branch.
7089 The lowest two bits must be zero and are not stored in the instruction,
7090 giving a 16 bit signed byte offset.
7092 BFD_RELOC_AARCH64_BRANCH19
7094 AArch64 19 bit pc-relative conditional branch and compare & branch.
7095 The lowest two bits must be zero and are not stored in the instruction,
7096 giving a 21 bit signed byte offset.
7098 BFD_RELOC_AARCH64_JUMP26
7100 AArch64 26 bit pc-relative unconditional branch.
7101 The lowest two bits must be zero and are not stored in the instruction,
7102 giving a 28 bit signed byte offset.
7104 BFD_RELOC_AARCH64_CALL26
7106 AArch64 26 bit pc-relative unconditional branch and link.
7107 The lowest two bits must be zero and are not stored in the instruction,
7108 giving a 28 bit signed byte offset.
7110 BFD_RELOC_AARCH64_LDST16_LO12
7112 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7113 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7115 BFD_RELOC_AARCH64_LDST32_LO12
7117 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7118 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7120 BFD_RELOC_AARCH64_LDST64_LO12
7122 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7123 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7125 BFD_RELOC_AARCH64_LDST128_LO12
7127 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7128 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7130 BFD_RELOC_AARCH64_GOT_LD_PREL19
7132 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7133 offset of the global offset table entry for a symbol. The lowest two
7134 bits must be zero and are not stored in the instruction, giving a 21
7135 bit signed byte offset. This relocation type requires signed overflow
7138 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7140 Get to the page base of the global offset table entry for a symbol as
7141 part of an ADRP instruction using a 21 bit PC relative value.Used in
7142 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7144 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7146 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7147 the GOT entry for this symbol. Used in conjunction with
7148 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7150 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7152 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7153 the GOT entry for this symbol. Used in conjunction with
7154 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7156 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7158 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7159 for this symbol. Valid in LP64 ABI only.
7161 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7163 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7164 for this symbol. Valid in LP64 ABI only.
7166 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7168 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7169 the GOT entry for this symbol. Valid in LP64 ABI only.
7171 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7173 Scaled 14 bit byte offset to the page base of the global offset table.
7175 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7177 Scaled 15 bit byte offset to the page base of the global offset table.
7179 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7181 Get to the page base of the global offset table entry for a symbols
7182 tls_index structure as part of an adrp instruction using a 21 bit PC
7183 relative value. Used in conjunction with
7184 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7186 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7188 AArch64 TLS General Dynamic
7190 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7192 Unsigned 12 bit byte offset to global offset table entry for a symbols
7193 tls_index structure. Used in conjunction with
7194 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7196 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7198 AArch64 TLS General Dynamic relocation.
7200 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7202 AArch64 TLS General Dynamic relocation.
7204 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7206 AArch64 TLS INITIAL EXEC relocation.
7208 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7210 AArch64 TLS INITIAL EXEC relocation.
7212 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7214 AArch64 TLS INITIAL EXEC relocation.
7216 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7218 AArch64 TLS INITIAL EXEC relocation.
7220 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7222 AArch64 TLS INITIAL EXEC relocation.
7224 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7226 AArch64 TLS INITIAL EXEC relocation.
7228 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7230 bit[23:12] of byte offset to module TLS base address.
7232 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7234 Unsigned 12 bit byte offset to module TLS base address.
7236 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7238 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7240 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7242 Unsigned 12 bit byte offset to global offset table entry for a symbols
7243 tls_index structure. Used in conjunction with
7244 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7246 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7248 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7251 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7253 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7255 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7257 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7260 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7262 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7264 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7266 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7269 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7271 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7273 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7275 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7278 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7280 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7282 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7284 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7287 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7289 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7291 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7293 bit[15:0] of byte offset to module TLS base address.
7295 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7297 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7299 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7301 bit[31:16] of byte offset to module TLS base address.
7303 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7305 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7307 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7309 bit[47:32] of byte offset to module TLS base address.
7311 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7313 AArch64 TLS LOCAL EXEC relocation.
7315 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7317 AArch64 TLS LOCAL EXEC relocation.
7319 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7321 AArch64 TLS LOCAL EXEC relocation.
7323 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7325 AArch64 TLS LOCAL EXEC relocation.
7327 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7329 AArch64 TLS LOCAL EXEC relocation.
7331 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7333 AArch64 TLS LOCAL EXEC relocation.
7335 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7337 AArch64 TLS LOCAL EXEC relocation.
7339 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7341 AArch64 TLS LOCAL EXEC relocation.
7343 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7345 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7348 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7350 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7352 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7354 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7357 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7359 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7361 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7363 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7366 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7368 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7370 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7372 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7375 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7377 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7379 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7381 AArch64 TLS DESC relocation.
7383 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7385 AArch64 TLS DESC relocation.
7387 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7389 AArch64 TLS DESC relocation.
7391 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7393 AArch64 TLS DESC relocation.
7395 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7397 AArch64 TLS DESC relocation.
7399 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7401 AArch64 TLS DESC relocation.
7403 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7405 AArch64 TLS DESC relocation.
7407 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7409 AArch64 TLS DESC relocation.
7411 BFD_RELOC_AARCH64_TLSDESC_LDR
7413 AArch64 TLS DESC relocation.
7415 BFD_RELOC_AARCH64_TLSDESC_ADD
7417 AArch64 TLS DESC relocation.
7419 BFD_RELOC_AARCH64_TLSDESC_CALL
7421 AArch64 TLS DESC relocation.
7423 BFD_RELOC_AARCH64_COPY
7425 AArch64 TLS relocation.
7427 BFD_RELOC_AARCH64_GLOB_DAT
7429 AArch64 TLS relocation.
7431 BFD_RELOC_AARCH64_JUMP_SLOT
7433 AArch64 TLS relocation.
7435 BFD_RELOC_AARCH64_RELATIVE
7437 AArch64 TLS relocation.
7439 BFD_RELOC_AARCH64_TLS_DTPMOD
7441 AArch64 TLS relocation.
7443 BFD_RELOC_AARCH64_TLS_DTPREL
7445 AArch64 TLS relocation.
7447 BFD_RELOC_AARCH64_TLS_TPREL
7449 AArch64 TLS relocation.
7451 BFD_RELOC_AARCH64_TLSDESC
7453 AArch64 TLS relocation.
7455 BFD_RELOC_AARCH64_IRELATIVE
7457 AArch64 support for STT_GNU_IFUNC.
7459 BFD_RELOC_AARCH64_RELOC_END
7461 AArch64 pseudo relocation code to mark the end of the AArch64
7462 relocation enumerators that have direct mapping to ELF reloc codes.
7463 There are a few more enumerators after this one; those are mainly
7464 used by the AArch64 assembler for the internal fixup or to select
7465 one of the above enumerators.
7467 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7469 AArch64 pseudo relocation code to be used internally by the AArch64
7470 assembler and not (currently) written to any object files.
7472 BFD_RELOC_AARCH64_LDST_LO12
7474 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7475 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7477 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7479 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7480 used internally by the AArch64 assembler and not (currently) written to
7483 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7485 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7487 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7489 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7490 used internally by the AArch64 assembler and not (currently) written to
7493 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7495 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7497 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7499 AArch64 pseudo relocation code to be used internally by the AArch64
7500 assembler and not (currently) written to any object files.
7502 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7504 AArch64 pseudo relocation code to be used internally by the AArch64
7505 assembler and not (currently) written to any object files.
7507 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7509 AArch64 pseudo relocation code to be used internally by the AArch64
7510 assembler and not (currently) written to any object files.
7512 BFD_RELOC_TILEPRO_COPY
7514 BFD_RELOC_TILEPRO_GLOB_DAT
7516 BFD_RELOC_TILEPRO_JMP_SLOT
7518 BFD_RELOC_TILEPRO_RELATIVE
7520 BFD_RELOC_TILEPRO_BROFF_X1
7522 BFD_RELOC_TILEPRO_JOFFLONG_X1
7524 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7526 BFD_RELOC_TILEPRO_IMM8_X0
7528 BFD_RELOC_TILEPRO_IMM8_Y0
7530 BFD_RELOC_TILEPRO_IMM8_X1
7532 BFD_RELOC_TILEPRO_IMM8_Y1
7534 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7536 BFD_RELOC_TILEPRO_MT_IMM15_X1
7538 BFD_RELOC_TILEPRO_MF_IMM15_X1
7540 BFD_RELOC_TILEPRO_IMM16_X0
7542 BFD_RELOC_TILEPRO_IMM16_X1
7544 BFD_RELOC_TILEPRO_IMM16_X0_LO
7546 BFD_RELOC_TILEPRO_IMM16_X1_LO
7548 BFD_RELOC_TILEPRO_IMM16_X0_HI
7550 BFD_RELOC_TILEPRO_IMM16_X1_HI
7552 BFD_RELOC_TILEPRO_IMM16_X0_HA
7554 BFD_RELOC_TILEPRO_IMM16_X1_HA
7556 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7558 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7560 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7562 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7564 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7566 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7568 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7570 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7572 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7574 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7576 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7578 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7580 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7582 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7584 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7586 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7588 BFD_RELOC_TILEPRO_MMSTART_X0
7590 BFD_RELOC_TILEPRO_MMEND_X0
7592 BFD_RELOC_TILEPRO_MMSTART_X1
7594 BFD_RELOC_TILEPRO_MMEND_X1
7596 BFD_RELOC_TILEPRO_SHAMT_X0
7598 BFD_RELOC_TILEPRO_SHAMT_X1
7600 BFD_RELOC_TILEPRO_SHAMT_Y0
7602 BFD_RELOC_TILEPRO_SHAMT_Y1
7604 BFD_RELOC_TILEPRO_TLS_GD_CALL
7606 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7608 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7610 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7612 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7614 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7616 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7618 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7620 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7622 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7624 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7626 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7628 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7630 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7632 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7634 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7636 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7638 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7640 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7642 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7644 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7646 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7648 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7650 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7652 BFD_RELOC_TILEPRO_TLS_TPOFF32
7654 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7656 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7658 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7660 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7662 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7664 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7666 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7668 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7670 Tilera TILEPro Relocations.
7672 BFD_RELOC_TILEGX_HW0
7674 BFD_RELOC_TILEGX_HW1
7676 BFD_RELOC_TILEGX_HW2
7678 BFD_RELOC_TILEGX_HW3
7680 BFD_RELOC_TILEGX_HW0_LAST
7682 BFD_RELOC_TILEGX_HW1_LAST
7684 BFD_RELOC_TILEGX_HW2_LAST
7686 BFD_RELOC_TILEGX_COPY
7688 BFD_RELOC_TILEGX_GLOB_DAT
7690 BFD_RELOC_TILEGX_JMP_SLOT
7692 BFD_RELOC_TILEGX_RELATIVE
7694 BFD_RELOC_TILEGX_BROFF_X1
7696 BFD_RELOC_TILEGX_JUMPOFF_X1
7698 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7700 BFD_RELOC_TILEGX_IMM8_X0
7702 BFD_RELOC_TILEGX_IMM8_Y0
7704 BFD_RELOC_TILEGX_IMM8_X1
7706 BFD_RELOC_TILEGX_IMM8_Y1
7708 BFD_RELOC_TILEGX_DEST_IMM8_X1
7710 BFD_RELOC_TILEGX_MT_IMM14_X1
7712 BFD_RELOC_TILEGX_MF_IMM14_X1
7714 BFD_RELOC_TILEGX_MMSTART_X0
7716 BFD_RELOC_TILEGX_MMEND_X0
7718 BFD_RELOC_TILEGX_SHAMT_X0
7720 BFD_RELOC_TILEGX_SHAMT_X1
7722 BFD_RELOC_TILEGX_SHAMT_Y0
7724 BFD_RELOC_TILEGX_SHAMT_Y1
7726 BFD_RELOC_TILEGX_IMM16_X0_HW0
7728 BFD_RELOC_TILEGX_IMM16_X1_HW0
7730 BFD_RELOC_TILEGX_IMM16_X0_HW1
7732 BFD_RELOC_TILEGX_IMM16_X1_HW1
7734 BFD_RELOC_TILEGX_IMM16_X0_HW2
7736 BFD_RELOC_TILEGX_IMM16_X1_HW2
7738 BFD_RELOC_TILEGX_IMM16_X0_HW3
7740 BFD_RELOC_TILEGX_IMM16_X1_HW3
7742 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7744 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7746 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7748 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7750 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7752 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7754 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7756 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7758 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7760 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7762 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7764 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7766 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7768 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7770 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7772 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7774 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7776 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7778 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7780 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7782 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7784 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7786 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7788 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7790 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7792 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7794 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7796 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7798 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7800 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7802 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7804 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7806 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7810 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7812 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7814 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7816 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7818 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7820 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7822 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7824 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7826 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7828 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7830 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7832 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7834 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7836 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7838 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7840 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7842 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7844 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7846 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7848 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7850 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7852 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7854 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7856 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7858 BFD_RELOC_TILEGX_TLS_DTPMOD64
7860 BFD_RELOC_TILEGX_TLS_DTPOFF64
7862 BFD_RELOC_TILEGX_TLS_TPOFF64
7864 BFD_RELOC_TILEGX_TLS_DTPMOD32
7866 BFD_RELOC_TILEGX_TLS_DTPOFF32
7868 BFD_RELOC_TILEGX_TLS_TPOFF32
7870 BFD_RELOC_TILEGX_TLS_GD_CALL
7872 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7874 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7876 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7878 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7880 BFD_RELOC_TILEGX_TLS_IE_LOAD
7882 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7884 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7886 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7888 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7890 Tilera TILE-Gx Relocations.
7899 BFD_RELOC_BPF_DISP16
7901 BFD_RELOC_BPF_DISP32
7903 Linux eBPF relocations.
7906 BFD_RELOC_EPIPHANY_SIMM8
7908 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7910 BFD_RELOC_EPIPHANY_SIMM24
7912 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7914 BFD_RELOC_EPIPHANY_HIGH
7916 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7918 BFD_RELOC_EPIPHANY_LOW
7920 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7922 BFD_RELOC_EPIPHANY_SIMM11
7924 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7926 BFD_RELOC_EPIPHANY_IMM11
7928 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7930 BFD_RELOC_EPIPHANY_IMM8
7932 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7935 BFD_RELOC_VISIUM_HI16
7937 BFD_RELOC_VISIUM_LO16
7939 BFD_RELOC_VISIUM_IM16
7941 BFD_RELOC_VISIUM_REL16
7943 BFD_RELOC_VISIUM_HI16_PCREL
7945 BFD_RELOC_VISIUM_LO16_PCREL
7947 BFD_RELOC_VISIUM_IM16_PCREL
7952 BFD_RELOC_WASM32_LEB128
7954 BFD_RELOC_WASM32_LEB128_GOT
7956 BFD_RELOC_WASM32_LEB128_GOT_CODE
7958 BFD_RELOC_WASM32_LEB128_PLT
7960 BFD_RELOC_WASM32_PLT_INDEX
7962 BFD_RELOC_WASM32_ABS32_CODE
7964 BFD_RELOC_WASM32_COPY
7966 BFD_RELOC_WASM32_CODE_POINTER
7968 BFD_RELOC_WASM32_INDEX
7970 BFD_RELOC_WASM32_PLT_SIG
7972 WebAssembly relocations.
7975 BFD_RELOC_CKCORE_NONE
7977 BFD_RELOC_CKCORE_ADDR32
7979 BFD_RELOC_CKCORE_PCREL_IMM8BY4
7981 BFD_RELOC_CKCORE_PCREL_IMM11BY2
7983 BFD_RELOC_CKCORE_PCREL_IMM4BY2
7985 BFD_RELOC_CKCORE_PCREL32
7987 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
7989 BFD_RELOC_CKCORE_GNU_VTINHERIT
7991 BFD_RELOC_CKCORE_GNU_VTENTRY
7993 BFD_RELOC_CKCORE_RELATIVE
7995 BFD_RELOC_CKCORE_COPY
7997 BFD_RELOC_CKCORE_GLOB_DAT
7999 BFD_RELOC_CKCORE_JUMP_SLOT
8001 BFD_RELOC_CKCORE_GOTOFF
8003 BFD_RELOC_CKCORE_GOTPC
8005 BFD_RELOC_CKCORE_GOT32
8007 BFD_RELOC_CKCORE_PLT32
8009 BFD_RELOC_CKCORE_ADDRGOT
8011 BFD_RELOC_CKCORE_ADDRPLT
8013 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8015 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8017 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8019 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8021 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8023 BFD_RELOC_CKCORE_ADDR_HI16
8025 BFD_RELOC_CKCORE_ADDR_LO16
8027 BFD_RELOC_CKCORE_GOTPC_HI16
8029 BFD_RELOC_CKCORE_GOTPC_LO16
8031 BFD_RELOC_CKCORE_GOTOFF_HI16
8033 BFD_RELOC_CKCORE_GOTOFF_LO16
8035 BFD_RELOC_CKCORE_GOT12
8037 BFD_RELOC_CKCORE_GOT_HI16
8039 BFD_RELOC_CKCORE_GOT_LO16
8041 BFD_RELOC_CKCORE_PLT12
8043 BFD_RELOC_CKCORE_PLT_HI16
8045 BFD_RELOC_CKCORE_PLT_LO16
8047 BFD_RELOC_CKCORE_ADDRGOT_HI16
8049 BFD_RELOC_CKCORE_ADDRGOT_LO16
8051 BFD_RELOC_CKCORE_ADDRPLT_HI16
8053 BFD_RELOC_CKCORE_ADDRPLT_LO16
8055 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8057 BFD_RELOC_CKCORE_TOFFSET_LO16
8059 BFD_RELOC_CKCORE_DOFFSET_LO16
8061 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8063 BFD_RELOC_CKCORE_DOFFSET_IMM18
8065 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8067 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8069 BFD_RELOC_CKCORE_GOTOFF_IMM18
8071 BFD_RELOC_CKCORE_GOT_IMM18BY4
8073 BFD_RELOC_CKCORE_PLT_IMM18BY4
8075 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8077 BFD_RELOC_CKCORE_TLS_LE32
8079 BFD_RELOC_CKCORE_TLS_IE32
8081 BFD_RELOC_CKCORE_TLS_GD32
8083 BFD_RELOC_CKCORE_TLS_LDM32
8085 BFD_RELOC_CKCORE_TLS_LDO32
8087 BFD_RELOC_CKCORE_TLS_DTPMOD32
8089 BFD_RELOC_CKCORE_TLS_DTPOFF32
8091 BFD_RELOC_CKCORE_TLS_TPOFF32
8093 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8095 BFD_RELOC_CKCORE_NOJSRI
8097 BFD_RELOC_CKCORE_CALLGRAPH
8099 BFD_RELOC_CKCORE_IRELATIVE
8101 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8103 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8116 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8121 bfd_reloc_type_lookup
8122 bfd_reloc_name_lookup
8125 reloc_howto_type *bfd_reloc_type_lookup
8126 (bfd *abfd, bfd_reloc_code_real_type code);
8127 reloc_howto_type *bfd_reloc_name_lookup
8128 (bfd *abfd, const char *reloc_name);
8131 Return a pointer to a howto structure which, when
8132 invoked, will perform the relocation @var{code} on data from the
8138 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8140 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8144 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8146 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8149 static reloc_howto_type bfd_howto_32
=
8150 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8154 bfd_default_reloc_type_lookup
8157 reloc_howto_type *bfd_default_reloc_type_lookup
8158 (bfd *abfd, bfd_reloc_code_real_type code);
8161 Provides a default relocation lookup routine for any architecture.
8166 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8168 /* Very limited support is provided for relocs in generic targets
8169 such as elf32-little. FIXME: Should we always return NULL? */
8170 if (code
== BFD_RELOC_CTOR
8171 && bfd_arch_bits_per_address (abfd
) == 32)
8172 return &bfd_howto_32
;
8178 bfd_get_reloc_code_name
8181 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8184 Provides a printable name for the supplied relocation code.
8185 Useful mainly for printing error messages.
8189 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8191 if (code
> BFD_RELOC_UNUSED
)
8193 return bfd_reloc_code_real_names
[code
];
8198 bfd_generic_relax_section
8201 bfd_boolean bfd_generic_relax_section
8204 struct bfd_link_info *,
8208 Provides default handling for relaxing for back ends which
8213 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8214 asection
*section ATTRIBUTE_UNUSED
,
8215 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8218 if (bfd_link_relocatable (link_info
))
8219 (*link_info
->callbacks
->einfo
)
8220 (_("%P%F: --relax and -r may not be used together\n"));
8228 bfd_generic_gc_sections
8231 bfd_boolean bfd_generic_gc_sections
8232 (bfd *, struct bfd_link_info *);
8235 Provides default handling for relaxing for back ends which
8236 don't do section gc -- i.e., does nothing.
8240 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8241 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8248 bfd_generic_lookup_section_flags
8251 bfd_boolean bfd_generic_lookup_section_flags
8252 (struct bfd_link_info *, struct flag_info *, asection *);
8255 Provides default handling for section flags lookup
8256 -- i.e., does nothing.
8257 Returns FALSE if the section should be omitted, otherwise TRUE.
8261 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8262 struct flag_info
*flaginfo
,
8263 asection
*section ATTRIBUTE_UNUSED
)
8265 if (flaginfo
!= NULL
)
8267 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8275 bfd_generic_merge_sections
8278 bfd_boolean bfd_generic_merge_sections
8279 (bfd *, struct bfd_link_info *);
8282 Provides default handling for SEC_MERGE section merging for back ends
8283 which don't have SEC_MERGE support -- i.e., does nothing.
8287 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8288 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8295 bfd_generic_get_relocated_section_contents
8298 bfd_byte *bfd_generic_get_relocated_section_contents
8300 struct bfd_link_info *link_info,
8301 struct bfd_link_order *link_order,
8303 bfd_boolean relocatable,
8307 Provides default handling of relocation effort for back ends
8308 which can't be bothered to do it efficiently.
8313 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8314 struct bfd_link_info
*link_info
,
8315 struct bfd_link_order
*link_order
,
8317 bfd_boolean relocatable
,
8320 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8321 asection
*input_section
= link_order
->u
.indirect
.section
;
8323 arelent
**reloc_vector
;
8326 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8330 /* Read in the section. */
8331 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8337 if (reloc_size
== 0)
8340 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8341 if (reloc_vector
== NULL
)
8344 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8348 if (reloc_count
< 0)
8351 if (reloc_count
> 0)
8355 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8357 char *error_message
= NULL
;
8359 bfd_reloc_status_type r
;
8361 symbol
= *(*parent
)->sym_ptr_ptr
;
8362 /* PR ld/19628: A specially crafted input file
8363 can result in a NULL symbol pointer here. */
8366 link_info
->callbacks
->einfo
8367 /* xgettext:c-format */
8368 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8369 abfd
, input_section
, (* parent
)->address
);
8373 /* Zap reloc field when the symbol is from a discarded
8374 section, ignoring any addend. Do the same when called
8375 from bfd_simple_get_relocated_section_contents for
8376 undefined symbols in debug sections. This is to keep
8377 debug info reasonably sane, in particular so that
8378 DW_FORM_ref_addr to another file's .debug_info isn't
8379 confused with an offset into the current file's
8381 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8382 || (symbol
->section
== bfd_und_section_ptr
8383 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8384 && link_info
->input_bfds
== link_info
->output_bfd
))
8387 static reloc_howto_type none_howto
8388 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8389 "unused", FALSE
, 0, 0, FALSE
);
8391 off
= ((*parent
)->address
8392 * bfd_octets_per_byte (input_bfd
, input_section
));
8393 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8394 input_section
, data
, off
);
8395 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8396 (*parent
)->addend
= 0;
8397 (*parent
)->howto
= &none_howto
;
8401 r
= bfd_perform_relocation (input_bfd
,
8405 relocatable
? abfd
: NULL
,
8410 asection
*os
= input_section
->output_section
;
8412 /* A partial link, so keep the relocs. */
8413 os
->orelocation
[os
->reloc_count
] = *parent
;
8417 if (r
!= bfd_reloc_ok
)
8421 case bfd_reloc_undefined
:
8422 (*link_info
->callbacks
->undefined_symbol
)
8423 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8424 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8426 case bfd_reloc_dangerous
:
8427 BFD_ASSERT (error_message
!= NULL
);
8428 (*link_info
->callbacks
->reloc_dangerous
)
8429 (link_info
, error_message
,
8430 input_bfd
, input_section
, (*parent
)->address
);
8432 case bfd_reloc_overflow
:
8433 (*link_info
->callbacks
->reloc_overflow
)
8435 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8436 (*parent
)->howto
->name
, (*parent
)->addend
,
8437 input_bfd
, input_section
, (*parent
)->address
);
8439 case bfd_reloc_outofrange
:
8441 This error can result when processing some partially
8442 complete binaries. Do not abort, but issue an error
8444 link_info
->callbacks
->einfo
8445 /* xgettext:c-format */
8446 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8447 abfd
, input_section
, * parent
);
8450 case bfd_reloc_notsupported
:
8452 This error can result when processing a corrupt binary.
8453 Do not abort. Issue an error message instead. */
8454 link_info
->callbacks
->einfo
8455 /* xgettext:c-format */
8456 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8457 abfd
, input_section
, * parent
);
8461 /* PR 17512; file: 90c2a92e.
8462 Report unexpected results, without aborting. */
8463 link_info
->callbacks
->einfo
8464 /* xgettext:c-format */
8465 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8466 abfd
, input_section
, * parent
, r
);
8474 free (reloc_vector
);
8478 free (reloc_vector
);
8484 _bfd_generic_set_reloc
8487 void _bfd_generic_set_reloc
8491 unsigned int count);
8494 Installs a new set of internal relocations in SECTION.
8498 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8503 section
->orelocation
= relptr
;
8504 section
->reloc_count
= count
;
8509 _bfd_unrecognized_reloc
8512 bfd_boolean _bfd_unrecognized_reloc
8515 unsigned int r_type);
8518 Reports an unrecognized reloc.
8519 Written as a function in order to reduce code duplication.
8520 Returns FALSE so that it can be called from a return statement.
8524 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8526 /* xgettext:c-format */
8527 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8528 abfd
, r_type
, section
);
8530 /* PR 21803: Suggest the most likely cause of this error. */
8531 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8532 BFD_VERSION_STRING
);
8534 bfd_set_error (bfd_error_bad_value
);
8539 _bfd_norelocs_bfd_reloc_type_lookup
8541 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8543 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8547 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8548 const char *reloc_name ATTRIBUTE_UNUSED
)
8550 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8554 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8555 arelent
**relp ATTRIBUTE_UNUSED
,
8556 asymbol
**symp ATTRIBUTE_UNUSED
)
8558 return _bfd_long_bfd_n1_error (abfd
);