1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2015 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how
,
489 unsigned int bitsize
,
490 unsigned int rightshift
,
491 unsigned int addrsize
,
494 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
495 bfd_reloc_status_type flag
= bfd_reloc_ok
;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask
= N_ONES (bitsize
);
502 signmask
= ~fieldmask
;
503 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
504 a
= (relocation
& addrmask
) >> rightshift
;
508 case complain_overflow_dont
:
511 case complain_overflow_signed
:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask
= ~ (fieldmask
>> 1);
517 case complain_overflow_bitfield
:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
525 flag
= bfd_reloc_overflow
;
528 case complain_overflow_unsigned
:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a
& signmask
) != 0)
531 flag
= bfd_reloc_overflow
;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd
*abfd
,
574 arelent
*reloc_entry
,
576 asection
*input_section
,
578 char **error_message
)
581 bfd_reloc_status_type flag
= bfd_reloc_ok
;
582 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
583 bfd_vma output_base
= 0;
584 reloc_howto_type
*howto
= reloc_entry
->howto
;
585 asection
*reloc_target_output_section
;
588 symbol
= *(reloc_entry
->sym_ptr_ptr
);
589 if (bfd_is_abs_section (symbol
->section
)
590 && output_bfd
!= NULL
)
592 reloc_entry
->address
+= input_section
->output_offset
;
596 /* PR 17512: file: 0f67f69d. */
598 return bfd_reloc_undefined
;
600 /* If we are not producing relocatable output, return an error if
601 the symbol is not defined. An undefined weak symbol is
602 considered to have a value of zero (SVR4 ABI, p. 4-27). */
603 if (bfd_is_und_section (symbol
->section
)
604 && (symbol
->flags
& BSF_WEAK
) == 0
605 && output_bfd
== NULL
)
606 flag
= bfd_reloc_undefined
;
608 /* If there is a function supplied to handle this relocation type,
609 call it. It'll return `bfd_reloc_continue' if further processing
611 if (howto
->special_function
)
613 bfd_reloc_status_type cont
;
614 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
615 input_section
, output_bfd
,
617 if (cont
!= bfd_reloc_continue
)
621 /* Is the address of the relocation really within the section? */
622 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
)
623 /* PR 17512: file: c146ab8b.
624 PR 17512: file: 46dff27f.
625 Include the size of the reloc in the test for out of range addresses. */
626 - bfd_get_reloc_size (howto
)
627 /* PR 17512: file: 38e53ebf
628 Add make sure that there is enough room for the relocation to be applied. */
629 || bfd_get_reloc_size (howto
) > bfd_get_section_limit (abfd
, input_section
))
630 return bfd_reloc_outofrange
;
632 /* Work out which section the relocation is targeted at and the
633 initial relocation command value. */
635 /* Get symbol value. (Common symbols are special.) */
636 if (bfd_is_com_section (symbol
->section
))
639 relocation
= symbol
->value
;
641 reloc_target_output_section
= symbol
->section
->output_section
;
643 /* Convert input-section-relative symbol value to absolute. */
644 if ((output_bfd
&& ! howto
->partial_inplace
)
645 || reloc_target_output_section
== NULL
)
648 output_base
= reloc_target_output_section
->vma
;
650 relocation
+= output_base
+ symbol
->section
->output_offset
;
652 /* Add in supplied addend. */
653 relocation
+= reloc_entry
->addend
;
655 /* Here the variable relocation holds the final address of the
656 symbol we are relocating against, plus any addend. */
658 if (howto
->pc_relative
)
660 /* This is a PC relative relocation. We want to set RELOCATION
661 to the distance between the address of the symbol and the
662 location. RELOCATION is already the address of the symbol.
664 We start by subtracting the address of the section containing
667 If pcrel_offset is set, we must further subtract the position
668 of the location within the section. Some targets arrange for
669 the addend to be the negative of the position of the location
670 within the section; for example, i386-aout does this. For
671 i386-aout, pcrel_offset is FALSE. Some other targets do not
672 include the position of the location; for example, m88kbcs,
673 or ELF. For those targets, pcrel_offset is TRUE.
675 If we are producing relocatable output, then we must ensure
676 that this reloc will be correctly computed when the final
677 relocation is done. If pcrel_offset is FALSE we want to wind
678 up with the negative of the location within the section,
679 which means we must adjust the existing addend by the change
680 in the location within the section. If pcrel_offset is TRUE
681 we do not want to adjust the existing addend at all.
683 FIXME: This seems logical to me, but for the case of
684 producing relocatable output it is not what the code
685 actually does. I don't want to change it, because it seems
686 far too likely that something will break. */
689 input_section
->output_section
->vma
+ input_section
->output_offset
;
691 if (howto
->pcrel_offset
)
692 relocation
-= reloc_entry
->address
;
695 if (output_bfd
!= NULL
)
697 if (! howto
->partial_inplace
)
699 /* This is a partial relocation, and we want to apply the relocation
700 to the reloc entry rather than the raw data. Modify the reloc
701 inplace to reflect what we now know. */
702 reloc_entry
->addend
= relocation
;
703 reloc_entry
->address
+= input_section
->output_offset
;
708 /* This is a partial relocation, but inplace, so modify the
711 If we've relocated with a symbol with a section, change
712 into a ref to the section belonging to the symbol. */
714 reloc_entry
->address
+= input_section
->output_offset
;
717 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
718 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
719 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
721 /* For m68k-coff, the addend was being subtracted twice during
722 relocation with -r. Removing the line below this comment
723 fixes that problem; see PR 2953.
725 However, Ian wrote the following, regarding removing the line below,
726 which explains why it is still enabled: --djm
728 If you put a patch like that into BFD you need to check all the COFF
729 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
730 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
731 problem in a different way. There may very well be a reason that the
732 code works as it does.
734 Hmmm. The first obvious point is that bfd_perform_relocation should
735 not have any tests that depend upon the flavour. It's seem like
736 entirely the wrong place for such a thing. The second obvious point
737 is that the current code ignores the reloc addend when producing
738 relocatable output for COFF. That's peculiar. In fact, I really
739 have no idea what the point of the line you want to remove is.
741 A typical COFF reloc subtracts the old value of the symbol and adds in
742 the new value to the location in the object file (if it's a pc
743 relative reloc it adds the difference between the symbol value and the
744 location). When relocating we need to preserve that property.
746 BFD handles this by setting the addend to the negative of the old
747 value of the symbol. Unfortunately it handles common symbols in a
748 non-standard way (it doesn't subtract the old value) but that's a
749 different story (we can't change it without losing backward
750 compatibility with old object files) (coff-i386 does subtract the old
751 value, to be compatible with existing coff-i386 targets, like SCO).
753 So everything works fine when not producing relocatable output. When
754 we are producing relocatable output, logically we should do exactly
755 what we do when not producing relocatable output. Therefore, your
756 patch is correct. In fact, it should probably always just set
757 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
758 add the value into the object file. This won't hurt the COFF code,
759 which doesn't use the addend; I'm not sure what it will do to other
760 formats (the thing to check for would be whether any formats both use
761 the addend and set partial_inplace).
763 When I wanted to make coff-i386 produce relocatable output, I ran
764 into the problem that you are running into: I wanted to remove that
765 line. Rather than risk it, I made the coff-i386 relocs use a special
766 function; it's coff_i386_reloc in coff-i386.c. The function
767 specifically adds the addend field into the object file, knowing that
768 bfd_perform_relocation is not going to. If you remove that line, then
769 coff-i386.c will wind up adding the addend field in twice. It's
770 trivial to fix; it just needs to be done.
772 The problem with removing the line is just that it may break some
773 working code. With BFD it's hard to be sure of anything. The right
774 way to deal with this is simply to build and test at least all the
775 supported COFF targets. It should be straightforward if time and disk
776 space consuming. For each target:
778 2) generate some executable, and link it using -r (I would
779 probably use paranoia.o and link against newlib/libc.a, which
780 for all the supported targets would be available in
781 /usr/cygnus/progressive/H-host/target/lib/libc.a).
782 3) make the change to reloc.c
783 4) rebuild the linker
785 6) if the resulting object files are the same, you have at least
787 7) if they are different you have to figure out which version is
790 relocation
-= reloc_entry
->addend
;
791 reloc_entry
->addend
= 0;
795 reloc_entry
->addend
= relocation
;
800 /* FIXME: This overflow checking is incomplete, because the value
801 might have overflowed before we get here. For a correct check we
802 need to compute the value in a size larger than bitsize, but we
803 can't reasonably do that for a reloc the same size as a host
805 FIXME: We should also do overflow checking on the result after
806 adding in the value contained in the object file. */
807 if (howto
->complain_on_overflow
!= complain_overflow_dont
808 && flag
== bfd_reloc_ok
)
809 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
812 bfd_arch_bits_per_address (abfd
),
815 /* Either we are relocating all the way, or we don't want to apply
816 the relocation to the reloc entry (probably because there isn't
817 any room in the output format to describe addends to relocs). */
819 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
820 (OSF version 1.3, compiler version 3.11). It miscompiles the
834 x <<= (unsigned long) s.i0;
838 printf ("succeeded (%lx)\n", x);
842 relocation
>>= (bfd_vma
) howto
->rightshift
;
844 /* Shift everything up to where it's going to be used. */
845 relocation
<<= (bfd_vma
) howto
->bitpos
;
847 /* Wait for the day when all have the mask in them. */
850 i instruction to be left alone
851 o offset within instruction
852 r relocation offset to apply
861 (( i i i i i o o o o o from bfd_get<size>
862 and S S S S S) to get the size offset we want
863 + r r r r r r r r r r) to get the final value to place
864 and D D D D D to chop to right size
865 -----------------------
868 ( i i i i i o o o o o from bfd_get<size>
869 and N N N N N ) get instruction
870 -----------------------
876 -----------------------
877 = R R R R R R R R R R put into bfd_put<size>
881 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
887 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
889 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
895 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
897 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
902 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
904 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
909 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
910 relocation
= -relocation
;
912 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
918 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
919 relocation
= -relocation
;
921 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
932 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
934 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
941 return bfd_reloc_other
;
949 bfd_install_relocation
952 bfd_reloc_status_type bfd_install_relocation
954 arelent *reloc_entry,
955 void *data, bfd_vma data_start,
956 asection *input_section,
957 char **error_message);
960 This looks remarkably like <<bfd_perform_relocation>>, except it
961 does not expect that the section contents have been filled in.
962 I.e., it's suitable for use when creating, rather than applying
965 For now, this function should be considered reserved for the
969 bfd_reloc_status_type
970 bfd_install_relocation (bfd
*abfd
,
971 arelent
*reloc_entry
,
973 bfd_vma data_start_offset
,
974 asection
*input_section
,
975 char **error_message
)
978 bfd_reloc_status_type flag
= bfd_reloc_ok
;
979 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
980 bfd_vma output_base
= 0;
981 reloc_howto_type
*howto
= reloc_entry
->howto
;
982 asection
*reloc_target_output_section
;
986 symbol
= *(reloc_entry
->sym_ptr_ptr
);
987 if (bfd_is_abs_section (symbol
->section
))
989 reloc_entry
->address
+= input_section
->output_offset
;
993 /* If there is a function supplied to handle this relocation type,
994 call it. It'll return `bfd_reloc_continue' if further processing
996 if (howto
->special_function
)
998 bfd_reloc_status_type cont
;
1000 /* XXX - The special_function calls haven't been fixed up to deal
1001 with creating new relocations and section contents. */
1002 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1003 /* XXX - Non-portable! */
1004 ((bfd_byte
*) data_start
1005 - data_start_offset
),
1006 input_section
, abfd
, error_message
);
1007 if (cont
!= bfd_reloc_continue
)
1011 /* Is the address of the relocation really within the section? */
1012 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
))
1013 return bfd_reloc_outofrange
;
1015 /* Work out which section the relocation is targeted at and the
1016 initial relocation command value. */
1018 /* Get symbol value. (Common symbols are special.) */
1019 if (bfd_is_com_section (symbol
->section
))
1022 relocation
= symbol
->value
;
1024 reloc_target_output_section
= symbol
->section
->output_section
;
1026 /* Convert input-section-relative symbol value to absolute. */
1027 if (! howto
->partial_inplace
)
1030 output_base
= reloc_target_output_section
->vma
;
1032 relocation
+= output_base
+ symbol
->section
->output_offset
;
1034 /* Add in supplied addend. */
1035 relocation
+= reloc_entry
->addend
;
1037 /* Here the variable relocation holds the final address of the
1038 symbol we are relocating against, plus any addend. */
1040 if (howto
->pc_relative
)
1042 /* This is a PC relative relocation. We want to set RELOCATION
1043 to the distance between the address of the symbol and the
1044 location. RELOCATION is already the address of the symbol.
1046 We start by subtracting the address of the section containing
1049 If pcrel_offset is set, we must further subtract the position
1050 of the location within the section. Some targets arrange for
1051 the addend to be the negative of the position of the location
1052 within the section; for example, i386-aout does this. For
1053 i386-aout, pcrel_offset is FALSE. Some other targets do not
1054 include the position of the location; for example, m88kbcs,
1055 or ELF. For those targets, pcrel_offset is TRUE.
1057 If we are producing relocatable output, then we must ensure
1058 that this reloc will be correctly computed when the final
1059 relocation is done. If pcrel_offset is FALSE we want to wind
1060 up with the negative of the location within the section,
1061 which means we must adjust the existing addend by the change
1062 in the location within the section. If pcrel_offset is TRUE
1063 we do not want to adjust the existing addend at all.
1065 FIXME: This seems logical to me, but for the case of
1066 producing relocatable output it is not what the code
1067 actually does. I don't want to change it, because it seems
1068 far too likely that something will break. */
1071 input_section
->output_section
->vma
+ input_section
->output_offset
;
1073 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1074 relocation
-= reloc_entry
->address
;
1077 if (! howto
->partial_inplace
)
1079 /* This is a partial relocation, and we want to apply the relocation
1080 to the reloc entry rather than the raw data. Modify the reloc
1081 inplace to reflect what we now know. */
1082 reloc_entry
->addend
= relocation
;
1083 reloc_entry
->address
+= input_section
->output_offset
;
1088 /* This is a partial relocation, but inplace, so modify the
1091 If we've relocated with a symbol with a section, change
1092 into a ref to the section belonging to the symbol. */
1093 reloc_entry
->address
+= input_section
->output_offset
;
1096 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1097 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1098 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1101 /* For m68k-coff, the addend was being subtracted twice during
1102 relocation with -r. Removing the line below this comment
1103 fixes that problem; see PR 2953.
1105 However, Ian wrote the following, regarding removing the line below,
1106 which explains why it is still enabled: --djm
1108 If you put a patch like that into BFD you need to check all the COFF
1109 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1110 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1111 problem in a different way. There may very well be a reason that the
1112 code works as it does.
1114 Hmmm. The first obvious point is that bfd_install_relocation should
1115 not have any tests that depend upon the flavour. It's seem like
1116 entirely the wrong place for such a thing. The second obvious point
1117 is that the current code ignores the reloc addend when producing
1118 relocatable output for COFF. That's peculiar. In fact, I really
1119 have no idea what the point of the line you want to remove is.
1121 A typical COFF reloc subtracts the old value of the symbol and adds in
1122 the new value to the location in the object file (if it's a pc
1123 relative reloc it adds the difference between the symbol value and the
1124 location). When relocating we need to preserve that property.
1126 BFD handles this by setting the addend to the negative of the old
1127 value of the symbol. Unfortunately it handles common symbols in a
1128 non-standard way (it doesn't subtract the old value) but that's a
1129 different story (we can't change it without losing backward
1130 compatibility with old object files) (coff-i386 does subtract the old
1131 value, to be compatible with existing coff-i386 targets, like SCO).
1133 So everything works fine when not producing relocatable output. When
1134 we are producing relocatable output, logically we should do exactly
1135 what we do when not producing relocatable output. Therefore, your
1136 patch is correct. In fact, it should probably always just set
1137 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1138 add the value into the object file. This won't hurt the COFF code,
1139 which doesn't use the addend; I'm not sure what it will do to other
1140 formats (the thing to check for would be whether any formats both use
1141 the addend and set partial_inplace).
1143 When I wanted to make coff-i386 produce relocatable output, I ran
1144 into the problem that you are running into: I wanted to remove that
1145 line. Rather than risk it, I made the coff-i386 relocs use a special
1146 function; it's coff_i386_reloc in coff-i386.c. The function
1147 specifically adds the addend field into the object file, knowing that
1148 bfd_install_relocation is not going to. If you remove that line, then
1149 coff-i386.c will wind up adding the addend field in twice. It's
1150 trivial to fix; it just needs to be done.
1152 The problem with removing the line is just that it may break some
1153 working code. With BFD it's hard to be sure of anything. The right
1154 way to deal with this is simply to build and test at least all the
1155 supported COFF targets. It should be straightforward if time and disk
1156 space consuming. For each target:
1158 2) generate some executable, and link it using -r (I would
1159 probably use paranoia.o and link against newlib/libc.a, which
1160 for all the supported targets would be available in
1161 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1162 3) make the change to reloc.c
1163 4) rebuild the linker
1165 6) if the resulting object files are the same, you have at least
1167 7) if they are different you have to figure out which version is
1169 relocation
-= reloc_entry
->addend
;
1170 /* FIXME: There should be no target specific code here... */
1171 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1172 reloc_entry
->addend
= 0;
1176 reloc_entry
->addend
= relocation
;
1180 /* FIXME: This overflow checking is incomplete, because the value
1181 might have overflowed before we get here. For a correct check we
1182 need to compute the value in a size larger than bitsize, but we
1183 can't reasonably do that for a reloc the same size as a host
1185 FIXME: We should also do overflow checking on the result after
1186 adding in the value contained in the object file. */
1187 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1188 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1191 bfd_arch_bits_per_address (abfd
),
1194 /* Either we are relocating all the way, or we don't want to apply
1195 the relocation to the reloc entry (probably because there isn't
1196 any room in the output format to describe addends to relocs). */
1198 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1199 (OSF version 1.3, compiler version 3.11). It miscompiles the
1213 x <<= (unsigned long) s.i0;
1215 printf ("failed\n");
1217 printf ("succeeded (%lx)\n", x);
1221 relocation
>>= (bfd_vma
) howto
->rightshift
;
1223 /* Shift everything up to where it's going to be used. */
1224 relocation
<<= (bfd_vma
) howto
->bitpos
;
1226 /* Wait for the day when all have the mask in them. */
1229 i instruction to be left alone
1230 o offset within instruction
1231 r relocation offset to apply
1240 (( i i i i i o o o o o from bfd_get<size>
1241 and S S S S S) to get the size offset we want
1242 + r r r r r r r r r r) to get the final value to place
1243 and D D D D D to chop to right size
1244 -----------------------
1247 ( i i i i i o o o o o from bfd_get<size>
1248 and N N N N N ) get instruction
1249 -----------------------
1255 -----------------------
1256 = R R R R R R R R R R put into bfd_put<size>
1260 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1262 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1264 switch (howto
->size
)
1268 char x
= bfd_get_8 (abfd
, data
);
1270 bfd_put_8 (abfd
, x
, data
);
1276 short x
= bfd_get_16 (abfd
, data
);
1278 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1283 long x
= bfd_get_32 (abfd
, data
);
1285 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1290 long x
= bfd_get_32 (abfd
, data
);
1291 relocation
= -relocation
;
1293 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1303 bfd_vma x
= bfd_get_64 (abfd
, data
);
1305 bfd_put_64 (abfd
, x
, data
);
1309 return bfd_reloc_other
;
1315 /* This relocation routine is used by some of the backend linkers.
1316 They do not construct asymbol or arelent structures, so there is no
1317 reason for them to use bfd_perform_relocation. Also,
1318 bfd_perform_relocation is so hacked up it is easier to write a new
1319 function than to try to deal with it.
1321 This routine does a final relocation. Whether it is useful for a
1322 relocatable link depends upon how the object format defines
1325 FIXME: This routine ignores any special_function in the HOWTO,
1326 since the existing special_function values have been written for
1327 bfd_perform_relocation.
1329 HOWTO is the reloc howto information.
1330 INPUT_BFD is the BFD which the reloc applies to.
1331 INPUT_SECTION is the section which the reloc applies to.
1332 CONTENTS is the contents of the section.
1333 ADDRESS is the address of the reloc within INPUT_SECTION.
1334 VALUE is the value of the symbol the reloc refers to.
1335 ADDEND is the addend of the reloc. */
1337 bfd_reloc_status_type
1338 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1340 asection
*input_section
,
1348 /* Sanity check the address. */
1349 if (address
> bfd_get_section_limit (input_bfd
, input_section
))
1350 return bfd_reloc_outofrange
;
1352 /* This function assumes that we are dealing with a basic relocation
1353 against a symbol. We want to compute the value of the symbol to
1354 relocate to. This is just VALUE, the value of the symbol, plus
1355 ADDEND, any addend associated with the reloc. */
1356 relocation
= value
+ addend
;
1358 /* If the relocation is PC relative, we want to set RELOCATION to
1359 the distance between the symbol (currently in RELOCATION) and the
1360 location we are relocating. Some targets (e.g., i386-aout)
1361 arrange for the contents of the section to be the negative of the
1362 offset of the location within the section; for such targets
1363 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1364 simply leave the contents of the section as zero; for such
1365 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1366 need to subtract out the offset of the location within the
1367 section (which is just ADDRESS). */
1368 if (howto
->pc_relative
)
1370 relocation
-= (input_section
->output_section
->vma
1371 + input_section
->output_offset
);
1372 if (howto
->pcrel_offset
)
1373 relocation
-= address
;
1376 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1377 contents
+ address
);
1380 /* Relocate a given location using a given value and howto. */
1382 bfd_reloc_status_type
1383 _bfd_relocate_contents (reloc_howto_type
*howto
,
1390 bfd_reloc_status_type flag
;
1391 unsigned int rightshift
= howto
->rightshift
;
1392 unsigned int bitpos
= howto
->bitpos
;
1394 /* If the size is negative, negate RELOCATION. This isn't very
1396 if (howto
->size
< 0)
1397 relocation
= -relocation
;
1399 /* Get the value we are going to relocate. */
1400 size
= bfd_get_reloc_size (howto
);
1407 x
= bfd_get_8 (input_bfd
, location
);
1410 x
= bfd_get_16 (input_bfd
, location
);
1413 x
= bfd_get_32 (input_bfd
, location
);
1417 x
= bfd_get_64 (input_bfd
, location
);
1424 /* Check for overflow. FIXME: We may drop bits during the addition
1425 which we don't check for. We must either check at every single
1426 operation, which would be tedious, or we must do the computations
1427 in a type larger than bfd_vma, which would be inefficient. */
1428 flag
= bfd_reloc_ok
;
1429 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1431 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1434 /* Get the values to be added together. For signed and unsigned
1435 relocations, we assume that all values should be truncated to
1436 the size of an address. For bitfields, all the bits matter.
1437 See also bfd_check_overflow. */
1438 fieldmask
= N_ONES (howto
->bitsize
);
1439 signmask
= ~fieldmask
;
1440 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1441 | (fieldmask
<< rightshift
));
1442 a
= (relocation
& addrmask
) >> rightshift
;
1443 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1444 addrmask
>>= rightshift
;
1446 switch (howto
->complain_on_overflow
)
1448 case complain_overflow_signed
:
1449 /* If any sign bits are set, all sign bits must be set.
1450 That is, A must be a valid negative address after
1452 signmask
= ~(fieldmask
>> 1);
1455 case complain_overflow_bitfield
:
1456 /* Much like the signed check, but for a field one bit
1457 wider. We allow a bitfield to represent numbers in the
1458 range -2**n to 2**n-1, where n is the number of bits in the
1459 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1460 can't overflow, which is exactly what we want. */
1462 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1463 flag
= bfd_reloc_overflow
;
1465 /* We only need this next bit of code if the sign bit of B
1466 is below the sign bit of A. This would only happen if
1467 SRC_MASK had fewer bits than BITSIZE. Note that if
1468 SRC_MASK has more bits than BITSIZE, we can get into
1469 trouble; we would need to verify that B is in range, as
1470 we do for A above. */
1471 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1474 /* Set all the bits above the sign bit. */
1477 /* Now we can do the addition. */
1480 /* See if the result has the correct sign. Bits above the
1481 sign bit are junk now; ignore them. If the sum is
1482 positive, make sure we did not have all negative inputs;
1483 if the sum is negative, make sure we did not have all
1484 positive inputs. The test below looks only at the sign
1485 bits, and it really just
1486 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1488 We mask with addrmask here to explicitly allow an address
1489 wrap-around. The Linux kernel relies on it, and it is
1490 the only way to write assembler code which can run when
1491 loaded at a location 0x80000000 away from the location at
1492 which it is linked. */
1493 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1494 flag
= bfd_reloc_overflow
;
1497 case complain_overflow_unsigned
:
1498 /* Checking for an unsigned overflow is relatively easy:
1499 trim the addresses and add, and trim the result as well.
1500 Overflow is normally indicated when the result does not
1501 fit in the field. However, we also need to consider the
1502 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1503 input is 0x80000000, and bfd_vma is only 32 bits; then we
1504 will get sum == 0, but there is an overflow, since the
1505 inputs did not fit in the field. Instead of doing a
1506 separate test, we can check for this by or-ing in the
1507 operands when testing for the sum overflowing its final
1509 sum
= (a
+ b
) & addrmask
;
1510 if ((a
| b
| sum
) & signmask
)
1511 flag
= bfd_reloc_overflow
;
1519 /* Put RELOCATION in the right bits. */
1520 relocation
>>= (bfd_vma
) rightshift
;
1521 relocation
<<= (bfd_vma
) bitpos
;
1523 /* Add RELOCATION to the right bits of X. */
1524 x
= ((x
& ~howto
->dst_mask
)
1525 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1527 /* Put the relocated value back in the object file. */
1533 bfd_put_8 (input_bfd
, x
, location
);
1536 bfd_put_16 (input_bfd
, x
, location
);
1539 bfd_put_32 (input_bfd
, x
, location
);
1543 bfd_put_64 (input_bfd
, x
, location
);
1553 /* Clear a given location using a given howto, by applying a fixed relocation
1554 value and discarding any in-place addend. This is used for fixed-up
1555 relocations against discarded symbols, to make ignorable debug or unwind
1556 information more obvious. */
1559 _bfd_clear_contents (reloc_howto_type
*howto
,
1561 asection
*input_section
,
1567 /* Get the value we are going to relocate. */
1568 size
= bfd_get_reloc_size (howto
);
1575 x
= bfd_get_8 (input_bfd
, location
);
1578 x
= bfd_get_16 (input_bfd
, location
);
1581 x
= bfd_get_32 (input_bfd
, location
);
1585 x
= bfd_get_64 (input_bfd
, location
);
1592 /* Zero out the unwanted bits of X. */
1593 x
&= ~howto
->dst_mask
;
1595 /* For a range list, use 1 instead of 0 as placeholder. 0
1596 would terminate the list, hiding any later entries. */
1597 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1598 ".debug_ranges") == 0
1599 && (howto
->dst_mask
& 1) != 0)
1602 /* Put the relocated value back in the object file. */
1609 bfd_put_8 (input_bfd
, x
, location
);
1612 bfd_put_16 (input_bfd
, x
, location
);
1615 bfd_put_32 (input_bfd
, x
, location
);
1619 bfd_put_64 (input_bfd
, x
, location
);
1630 howto manager, , typedef arelent, Relocations
1635 When an application wants to create a relocation, but doesn't
1636 know what the target machine might call it, it can find out by
1637 using this bit of code.
1646 The insides of a reloc code. The idea is that, eventually, there
1647 will be one enumerator for every type of relocation we ever do.
1648 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1649 return a howto pointer.
1651 This does mean that the application must determine the correct
1652 enumerator value; you can't get a howto pointer from a random set
1673 Basic absolute relocations of N bits.
1688 PC-relative relocations. Sometimes these are relative to the address
1689 of the relocation itself; sometimes they are relative to the start of
1690 the section containing the relocation. It depends on the specific target.
1692 The 24-bit relocation is used in some Intel 960 configurations.
1697 Section relative relocations. Some targets need this for DWARF2.
1700 BFD_RELOC_32_GOT_PCREL
1702 BFD_RELOC_16_GOT_PCREL
1704 BFD_RELOC_8_GOT_PCREL
1710 BFD_RELOC_LO16_GOTOFF
1712 BFD_RELOC_HI16_GOTOFF
1714 BFD_RELOC_HI16_S_GOTOFF
1718 BFD_RELOC_64_PLT_PCREL
1720 BFD_RELOC_32_PLT_PCREL
1722 BFD_RELOC_24_PLT_PCREL
1724 BFD_RELOC_16_PLT_PCREL
1726 BFD_RELOC_8_PLT_PCREL
1734 BFD_RELOC_LO16_PLTOFF
1736 BFD_RELOC_HI16_PLTOFF
1738 BFD_RELOC_HI16_S_PLTOFF
1752 BFD_RELOC_68K_GLOB_DAT
1754 BFD_RELOC_68K_JMP_SLOT
1756 BFD_RELOC_68K_RELATIVE
1758 BFD_RELOC_68K_TLS_GD32
1760 BFD_RELOC_68K_TLS_GD16
1762 BFD_RELOC_68K_TLS_GD8
1764 BFD_RELOC_68K_TLS_LDM32
1766 BFD_RELOC_68K_TLS_LDM16
1768 BFD_RELOC_68K_TLS_LDM8
1770 BFD_RELOC_68K_TLS_LDO32
1772 BFD_RELOC_68K_TLS_LDO16
1774 BFD_RELOC_68K_TLS_LDO8
1776 BFD_RELOC_68K_TLS_IE32
1778 BFD_RELOC_68K_TLS_IE16
1780 BFD_RELOC_68K_TLS_IE8
1782 BFD_RELOC_68K_TLS_LE32
1784 BFD_RELOC_68K_TLS_LE16
1786 BFD_RELOC_68K_TLS_LE8
1788 Relocations used by 68K ELF.
1791 BFD_RELOC_32_BASEREL
1793 BFD_RELOC_16_BASEREL
1795 BFD_RELOC_LO16_BASEREL
1797 BFD_RELOC_HI16_BASEREL
1799 BFD_RELOC_HI16_S_BASEREL
1805 Linkage-table relative.
1810 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1813 BFD_RELOC_32_PCREL_S2
1815 BFD_RELOC_16_PCREL_S2
1817 BFD_RELOC_23_PCREL_S2
1819 These PC-relative relocations are stored as word displacements --
1820 i.e., byte displacements shifted right two bits. The 30-bit word
1821 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1822 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1823 signed 16-bit displacement is used on the MIPS, and the 23-bit
1824 displacement is used on the Alpha.
1831 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1832 the target word. These are used on the SPARC.
1839 For systems that allocate a Global Pointer register, these are
1840 displacements off that register. These relocation types are
1841 handled specially, because the value the register will have is
1842 decided relatively late.
1845 BFD_RELOC_I960_CALLJ
1847 Reloc types used for i960/b.out.
1852 BFD_RELOC_SPARC_WDISP22
1858 BFD_RELOC_SPARC_GOT10
1860 BFD_RELOC_SPARC_GOT13
1862 BFD_RELOC_SPARC_GOT22
1864 BFD_RELOC_SPARC_PC10
1866 BFD_RELOC_SPARC_PC22
1868 BFD_RELOC_SPARC_WPLT30
1870 BFD_RELOC_SPARC_COPY
1872 BFD_RELOC_SPARC_GLOB_DAT
1874 BFD_RELOC_SPARC_JMP_SLOT
1876 BFD_RELOC_SPARC_RELATIVE
1878 BFD_RELOC_SPARC_UA16
1880 BFD_RELOC_SPARC_UA32
1882 BFD_RELOC_SPARC_UA64
1884 BFD_RELOC_SPARC_GOTDATA_HIX22
1886 BFD_RELOC_SPARC_GOTDATA_LOX10
1888 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1890 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1892 BFD_RELOC_SPARC_GOTDATA_OP
1894 BFD_RELOC_SPARC_JMP_IREL
1896 BFD_RELOC_SPARC_IRELATIVE
1898 SPARC ELF relocations. There is probably some overlap with other
1899 relocation types already defined.
1902 BFD_RELOC_SPARC_BASE13
1904 BFD_RELOC_SPARC_BASE22
1906 I think these are specific to SPARC a.out (e.g., Sun 4).
1916 BFD_RELOC_SPARC_OLO10
1918 BFD_RELOC_SPARC_HH22
1920 BFD_RELOC_SPARC_HM10
1922 BFD_RELOC_SPARC_LM22
1924 BFD_RELOC_SPARC_PC_HH22
1926 BFD_RELOC_SPARC_PC_HM10
1928 BFD_RELOC_SPARC_PC_LM22
1930 BFD_RELOC_SPARC_WDISP16
1932 BFD_RELOC_SPARC_WDISP19
1940 BFD_RELOC_SPARC_DISP64
1943 BFD_RELOC_SPARC_PLT32
1945 BFD_RELOC_SPARC_PLT64
1947 BFD_RELOC_SPARC_HIX22
1949 BFD_RELOC_SPARC_LOX10
1957 BFD_RELOC_SPARC_REGISTER
1961 BFD_RELOC_SPARC_SIZE32
1963 BFD_RELOC_SPARC_SIZE64
1965 BFD_RELOC_SPARC_WDISP10
1970 BFD_RELOC_SPARC_REV32
1972 SPARC little endian relocation
1974 BFD_RELOC_SPARC_TLS_GD_HI22
1976 BFD_RELOC_SPARC_TLS_GD_LO10
1978 BFD_RELOC_SPARC_TLS_GD_ADD
1980 BFD_RELOC_SPARC_TLS_GD_CALL
1982 BFD_RELOC_SPARC_TLS_LDM_HI22
1984 BFD_RELOC_SPARC_TLS_LDM_LO10
1986 BFD_RELOC_SPARC_TLS_LDM_ADD
1988 BFD_RELOC_SPARC_TLS_LDM_CALL
1990 BFD_RELOC_SPARC_TLS_LDO_HIX22
1992 BFD_RELOC_SPARC_TLS_LDO_LOX10
1994 BFD_RELOC_SPARC_TLS_LDO_ADD
1996 BFD_RELOC_SPARC_TLS_IE_HI22
1998 BFD_RELOC_SPARC_TLS_IE_LO10
2000 BFD_RELOC_SPARC_TLS_IE_LD
2002 BFD_RELOC_SPARC_TLS_IE_LDX
2004 BFD_RELOC_SPARC_TLS_IE_ADD
2006 BFD_RELOC_SPARC_TLS_LE_HIX22
2008 BFD_RELOC_SPARC_TLS_LE_LOX10
2010 BFD_RELOC_SPARC_TLS_DTPMOD32
2012 BFD_RELOC_SPARC_TLS_DTPMOD64
2014 BFD_RELOC_SPARC_TLS_DTPOFF32
2016 BFD_RELOC_SPARC_TLS_DTPOFF64
2018 BFD_RELOC_SPARC_TLS_TPOFF32
2020 BFD_RELOC_SPARC_TLS_TPOFF64
2022 SPARC TLS relocations
2031 BFD_RELOC_SPU_IMM10W
2035 BFD_RELOC_SPU_IMM16W
2039 BFD_RELOC_SPU_PCREL9a
2041 BFD_RELOC_SPU_PCREL9b
2043 BFD_RELOC_SPU_PCREL16
2053 BFD_RELOC_SPU_ADD_PIC
2058 BFD_RELOC_ALPHA_GPDISP_HI16
2060 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2061 "addend" in some special way.
2062 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2063 writing; when reading, it will be the absolute section symbol. The
2064 addend is the displacement in bytes of the "lda" instruction from
2065 the "ldah" instruction (which is at the address of this reloc).
2067 BFD_RELOC_ALPHA_GPDISP_LO16
2069 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2070 with GPDISP_HI16 relocs. The addend is ignored when writing the
2071 relocations out, and is filled in with the file's GP value on
2072 reading, for convenience.
2075 BFD_RELOC_ALPHA_GPDISP
2077 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2078 relocation except that there is no accompanying GPDISP_LO16
2082 BFD_RELOC_ALPHA_LITERAL
2084 BFD_RELOC_ALPHA_ELF_LITERAL
2086 BFD_RELOC_ALPHA_LITUSE
2088 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2089 the assembler turns it into a LDQ instruction to load the address of
2090 the symbol, and then fills in a register in the real instruction.
2092 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2093 section symbol. The addend is ignored when writing, but is filled
2094 in with the file's GP value on reading, for convenience, as with the
2097 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2098 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2099 but it generates output not based on the position within the .got
2100 section, but relative to the GP value chosen for the file during the
2103 The LITUSE reloc, on the instruction using the loaded address, gives
2104 information to the linker that it might be able to use to optimize
2105 away some literal section references. The symbol is ignored (read
2106 as the absolute section symbol), and the "addend" indicates the type
2107 of instruction using the register:
2108 1 - "memory" fmt insn
2109 2 - byte-manipulation (byte offset reg)
2110 3 - jsr (target of branch)
2113 BFD_RELOC_ALPHA_HINT
2115 The HINT relocation indicates a value that should be filled into the
2116 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2117 prediction logic which may be provided on some processors.
2120 BFD_RELOC_ALPHA_LINKAGE
2122 The LINKAGE relocation outputs a linkage pair in the object file,
2123 which is filled by the linker.
2126 BFD_RELOC_ALPHA_CODEADDR
2128 The CODEADDR relocation outputs a STO_CA in the object file,
2129 which is filled by the linker.
2132 BFD_RELOC_ALPHA_GPREL_HI16
2134 BFD_RELOC_ALPHA_GPREL_LO16
2136 The GPREL_HI/LO relocations together form a 32-bit offset from the
2140 BFD_RELOC_ALPHA_BRSGP
2142 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2143 share a common GP, and the target address is adjusted for
2144 STO_ALPHA_STD_GPLOAD.
2149 The NOP relocation outputs a NOP if the longword displacement
2150 between two procedure entry points is < 2^21.
2155 The BSR relocation outputs a BSR if the longword displacement
2156 between two procedure entry points is < 2^21.
2161 The LDA relocation outputs a LDA if the longword displacement
2162 between two procedure entry points is < 2^16.
2167 The BOH relocation outputs a BSR if the longword displacement
2168 between two procedure entry points is < 2^21, or else a hint.
2171 BFD_RELOC_ALPHA_TLSGD
2173 BFD_RELOC_ALPHA_TLSLDM
2175 BFD_RELOC_ALPHA_DTPMOD64
2177 BFD_RELOC_ALPHA_GOTDTPREL16
2179 BFD_RELOC_ALPHA_DTPREL64
2181 BFD_RELOC_ALPHA_DTPREL_HI16
2183 BFD_RELOC_ALPHA_DTPREL_LO16
2185 BFD_RELOC_ALPHA_DTPREL16
2187 BFD_RELOC_ALPHA_GOTTPREL16
2189 BFD_RELOC_ALPHA_TPREL64
2191 BFD_RELOC_ALPHA_TPREL_HI16
2193 BFD_RELOC_ALPHA_TPREL_LO16
2195 BFD_RELOC_ALPHA_TPREL16
2197 Alpha thread-local storage relocations.
2202 BFD_RELOC_MICROMIPS_JMP
2204 The MIPS jump instruction.
2207 BFD_RELOC_MIPS16_JMP
2209 The MIPS16 jump instruction.
2212 BFD_RELOC_MIPS16_GPREL
2214 MIPS16 GP relative reloc.
2219 High 16 bits of 32-bit value; simple reloc.
2224 High 16 bits of 32-bit value but the low 16 bits will be sign
2225 extended and added to form the final result. If the low 16
2226 bits form a negative number, we need to add one to the high value
2227 to compensate for the borrow when the low bits are added.
2235 BFD_RELOC_HI16_PCREL
2237 High 16 bits of 32-bit pc-relative value
2239 BFD_RELOC_HI16_S_PCREL
2241 High 16 bits of 32-bit pc-relative value, adjusted
2243 BFD_RELOC_LO16_PCREL
2245 Low 16 bits of pc-relative value
2248 BFD_RELOC_MIPS16_GOT16
2250 BFD_RELOC_MIPS16_CALL16
2252 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2253 16-bit immediate fields
2255 BFD_RELOC_MIPS16_HI16
2257 MIPS16 high 16 bits of 32-bit value.
2259 BFD_RELOC_MIPS16_HI16_S
2261 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2262 extended and added to form the final result. If the low 16
2263 bits form a negative number, we need to add one to the high value
2264 to compensate for the borrow when the low bits are added.
2266 BFD_RELOC_MIPS16_LO16
2271 BFD_RELOC_MIPS16_TLS_GD
2273 BFD_RELOC_MIPS16_TLS_LDM
2275 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2277 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2279 BFD_RELOC_MIPS16_TLS_GOTTPREL
2281 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2283 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2285 MIPS16 TLS relocations
2288 BFD_RELOC_MIPS_LITERAL
2290 BFD_RELOC_MICROMIPS_LITERAL
2292 Relocation against a MIPS literal section.
2295 BFD_RELOC_MICROMIPS_7_PCREL_S1
2297 BFD_RELOC_MICROMIPS_10_PCREL_S1
2299 BFD_RELOC_MICROMIPS_16_PCREL_S1
2301 microMIPS PC-relative relocations.
2304 BFD_RELOC_MIPS_21_PCREL_S2
2306 BFD_RELOC_MIPS_26_PCREL_S2
2308 BFD_RELOC_MIPS_18_PCREL_S3
2310 BFD_RELOC_MIPS_19_PCREL_S2
2312 MIPS PC-relative relocations.
2315 BFD_RELOC_MICROMIPS_GPREL16
2317 BFD_RELOC_MICROMIPS_HI16
2319 BFD_RELOC_MICROMIPS_HI16_S
2321 BFD_RELOC_MICROMIPS_LO16
2323 microMIPS versions of generic BFD relocs.
2326 BFD_RELOC_MIPS_GOT16
2328 BFD_RELOC_MICROMIPS_GOT16
2330 BFD_RELOC_MIPS_CALL16
2332 BFD_RELOC_MICROMIPS_CALL16
2334 BFD_RELOC_MIPS_GOT_HI16
2336 BFD_RELOC_MICROMIPS_GOT_HI16
2338 BFD_RELOC_MIPS_GOT_LO16
2340 BFD_RELOC_MICROMIPS_GOT_LO16
2342 BFD_RELOC_MIPS_CALL_HI16
2344 BFD_RELOC_MICROMIPS_CALL_HI16
2346 BFD_RELOC_MIPS_CALL_LO16
2348 BFD_RELOC_MICROMIPS_CALL_LO16
2352 BFD_RELOC_MICROMIPS_SUB
2354 BFD_RELOC_MIPS_GOT_PAGE
2356 BFD_RELOC_MICROMIPS_GOT_PAGE
2358 BFD_RELOC_MIPS_GOT_OFST
2360 BFD_RELOC_MICROMIPS_GOT_OFST
2362 BFD_RELOC_MIPS_GOT_DISP
2364 BFD_RELOC_MICROMIPS_GOT_DISP
2366 BFD_RELOC_MIPS_SHIFT5
2368 BFD_RELOC_MIPS_SHIFT6
2370 BFD_RELOC_MIPS_INSERT_A
2372 BFD_RELOC_MIPS_INSERT_B
2374 BFD_RELOC_MIPS_DELETE
2376 BFD_RELOC_MIPS_HIGHEST
2378 BFD_RELOC_MICROMIPS_HIGHEST
2380 BFD_RELOC_MIPS_HIGHER
2382 BFD_RELOC_MICROMIPS_HIGHER
2384 BFD_RELOC_MIPS_SCN_DISP
2386 BFD_RELOC_MICROMIPS_SCN_DISP
2388 BFD_RELOC_MIPS_REL16
2390 BFD_RELOC_MIPS_RELGOT
2394 BFD_RELOC_MICROMIPS_JALR
2396 BFD_RELOC_MIPS_TLS_DTPMOD32
2398 BFD_RELOC_MIPS_TLS_DTPREL32
2400 BFD_RELOC_MIPS_TLS_DTPMOD64
2402 BFD_RELOC_MIPS_TLS_DTPREL64
2404 BFD_RELOC_MIPS_TLS_GD
2406 BFD_RELOC_MICROMIPS_TLS_GD
2408 BFD_RELOC_MIPS_TLS_LDM
2410 BFD_RELOC_MICROMIPS_TLS_LDM
2412 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2414 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2416 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2418 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2420 BFD_RELOC_MIPS_TLS_GOTTPREL
2422 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2424 BFD_RELOC_MIPS_TLS_TPREL32
2426 BFD_RELOC_MIPS_TLS_TPREL64
2428 BFD_RELOC_MIPS_TLS_TPREL_HI16
2430 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2432 BFD_RELOC_MIPS_TLS_TPREL_LO16
2434 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2438 MIPS ELF relocations.
2444 BFD_RELOC_MIPS_JUMP_SLOT
2446 MIPS ELF relocations (VxWorks and PLT extensions).
2450 BFD_RELOC_MOXIE_10_PCREL
2452 Moxie ELF relocations.
2456 BFD_RELOC_FRV_LABEL16
2458 BFD_RELOC_FRV_LABEL24
2464 BFD_RELOC_FRV_GPREL12
2466 BFD_RELOC_FRV_GPRELU12
2468 BFD_RELOC_FRV_GPREL32
2470 BFD_RELOC_FRV_GPRELHI
2472 BFD_RELOC_FRV_GPRELLO
2480 BFD_RELOC_FRV_FUNCDESC
2482 BFD_RELOC_FRV_FUNCDESC_GOT12
2484 BFD_RELOC_FRV_FUNCDESC_GOTHI
2486 BFD_RELOC_FRV_FUNCDESC_GOTLO
2488 BFD_RELOC_FRV_FUNCDESC_VALUE
2490 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2492 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2494 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2496 BFD_RELOC_FRV_GOTOFF12
2498 BFD_RELOC_FRV_GOTOFFHI
2500 BFD_RELOC_FRV_GOTOFFLO
2502 BFD_RELOC_FRV_GETTLSOFF
2504 BFD_RELOC_FRV_TLSDESC_VALUE
2506 BFD_RELOC_FRV_GOTTLSDESC12
2508 BFD_RELOC_FRV_GOTTLSDESCHI
2510 BFD_RELOC_FRV_GOTTLSDESCLO
2512 BFD_RELOC_FRV_TLSMOFF12
2514 BFD_RELOC_FRV_TLSMOFFHI
2516 BFD_RELOC_FRV_TLSMOFFLO
2518 BFD_RELOC_FRV_GOTTLSOFF12
2520 BFD_RELOC_FRV_GOTTLSOFFHI
2522 BFD_RELOC_FRV_GOTTLSOFFLO
2524 BFD_RELOC_FRV_TLSOFF
2526 BFD_RELOC_FRV_TLSDESC_RELAX
2528 BFD_RELOC_FRV_GETTLSOFF_RELAX
2530 BFD_RELOC_FRV_TLSOFF_RELAX
2532 BFD_RELOC_FRV_TLSMOFF
2534 Fujitsu Frv Relocations.
2538 BFD_RELOC_MN10300_GOTOFF24
2540 This is a 24bit GOT-relative reloc for the mn10300.
2542 BFD_RELOC_MN10300_GOT32
2544 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2547 BFD_RELOC_MN10300_GOT24
2549 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2552 BFD_RELOC_MN10300_GOT16
2554 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2557 BFD_RELOC_MN10300_COPY
2559 Copy symbol at runtime.
2561 BFD_RELOC_MN10300_GLOB_DAT
2565 BFD_RELOC_MN10300_JMP_SLOT
2569 BFD_RELOC_MN10300_RELATIVE
2571 Adjust by program base.
2573 BFD_RELOC_MN10300_SYM_DIFF
2575 Together with another reloc targeted at the same location,
2576 allows for a value that is the difference of two symbols
2577 in the same section.
2579 BFD_RELOC_MN10300_ALIGN
2581 The addend of this reloc is an alignment power that must
2582 be honoured at the offset's location, regardless of linker
2585 BFD_RELOC_MN10300_TLS_GD
2587 BFD_RELOC_MN10300_TLS_LD
2589 BFD_RELOC_MN10300_TLS_LDO
2591 BFD_RELOC_MN10300_TLS_GOTIE
2593 BFD_RELOC_MN10300_TLS_IE
2595 BFD_RELOC_MN10300_TLS_LE
2597 BFD_RELOC_MN10300_TLS_DTPMOD
2599 BFD_RELOC_MN10300_TLS_DTPOFF
2601 BFD_RELOC_MN10300_TLS_TPOFF
2603 Various TLS-related relocations.
2605 BFD_RELOC_MN10300_32_PCREL
2607 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2610 BFD_RELOC_MN10300_16_PCREL
2612 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2623 BFD_RELOC_386_GLOB_DAT
2625 BFD_RELOC_386_JUMP_SLOT
2627 BFD_RELOC_386_RELATIVE
2629 BFD_RELOC_386_GOTOFF
2633 BFD_RELOC_386_TLS_TPOFF
2635 BFD_RELOC_386_TLS_IE
2637 BFD_RELOC_386_TLS_GOTIE
2639 BFD_RELOC_386_TLS_LE
2641 BFD_RELOC_386_TLS_GD
2643 BFD_RELOC_386_TLS_LDM
2645 BFD_RELOC_386_TLS_LDO_32
2647 BFD_RELOC_386_TLS_IE_32
2649 BFD_RELOC_386_TLS_LE_32
2651 BFD_RELOC_386_TLS_DTPMOD32
2653 BFD_RELOC_386_TLS_DTPOFF32
2655 BFD_RELOC_386_TLS_TPOFF32
2657 BFD_RELOC_386_TLS_GOTDESC
2659 BFD_RELOC_386_TLS_DESC_CALL
2661 BFD_RELOC_386_TLS_DESC
2663 BFD_RELOC_386_IRELATIVE
2665 i386/elf relocations
2668 BFD_RELOC_X86_64_GOT32
2670 BFD_RELOC_X86_64_PLT32
2672 BFD_RELOC_X86_64_COPY
2674 BFD_RELOC_X86_64_GLOB_DAT
2676 BFD_RELOC_X86_64_JUMP_SLOT
2678 BFD_RELOC_X86_64_RELATIVE
2680 BFD_RELOC_X86_64_GOTPCREL
2682 BFD_RELOC_X86_64_32S
2684 BFD_RELOC_X86_64_DTPMOD64
2686 BFD_RELOC_X86_64_DTPOFF64
2688 BFD_RELOC_X86_64_TPOFF64
2690 BFD_RELOC_X86_64_TLSGD
2692 BFD_RELOC_X86_64_TLSLD
2694 BFD_RELOC_X86_64_DTPOFF32
2696 BFD_RELOC_X86_64_GOTTPOFF
2698 BFD_RELOC_X86_64_TPOFF32
2700 BFD_RELOC_X86_64_GOTOFF64
2702 BFD_RELOC_X86_64_GOTPC32
2704 BFD_RELOC_X86_64_GOT64
2706 BFD_RELOC_X86_64_GOTPCREL64
2708 BFD_RELOC_X86_64_GOTPC64
2710 BFD_RELOC_X86_64_GOTPLT64
2712 BFD_RELOC_X86_64_PLTOFF64
2714 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2716 BFD_RELOC_X86_64_TLSDESC_CALL
2718 BFD_RELOC_X86_64_TLSDESC
2720 BFD_RELOC_X86_64_IRELATIVE
2722 BFD_RELOC_X86_64_PC32_BND
2724 BFD_RELOC_X86_64_PLT32_BND
2726 x86-64/elf relocations
2729 BFD_RELOC_NS32K_IMM_8
2731 BFD_RELOC_NS32K_IMM_16
2733 BFD_RELOC_NS32K_IMM_32
2735 BFD_RELOC_NS32K_IMM_8_PCREL
2737 BFD_RELOC_NS32K_IMM_16_PCREL
2739 BFD_RELOC_NS32K_IMM_32_PCREL
2741 BFD_RELOC_NS32K_DISP_8
2743 BFD_RELOC_NS32K_DISP_16
2745 BFD_RELOC_NS32K_DISP_32
2747 BFD_RELOC_NS32K_DISP_8_PCREL
2749 BFD_RELOC_NS32K_DISP_16_PCREL
2751 BFD_RELOC_NS32K_DISP_32_PCREL
2756 BFD_RELOC_PDP11_DISP_8_PCREL
2758 BFD_RELOC_PDP11_DISP_6_PCREL
2763 BFD_RELOC_PJ_CODE_HI16
2765 BFD_RELOC_PJ_CODE_LO16
2767 BFD_RELOC_PJ_CODE_DIR16
2769 BFD_RELOC_PJ_CODE_DIR32
2771 BFD_RELOC_PJ_CODE_REL16
2773 BFD_RELOC_PJ_CODE_REL32
2775 Picojava relocs. Not all of these appear in object files.
2786 BFD_RELOC_PPC_B16_BRTAKEN
2788 BFD_RELOC_PPC_B16_BRNTAKEN
2792 BFD_RELOC_PPC_BA16_BRTAKEN
2794 BFD_RELOC_PPC_BA16_BRNTAKEN
2798 BFD_RELOC_PPC_GLOB_DAT
2800 BFD_RELOC_PPC_JMP_SLOT
2802 BFD_RELOC_PPC_RELATIVE
2804 BFD_RELOC_PPC_LOCAL24PC
2806 BFD_RELOC_PPC_EMB_NADDR32
2808 BFD_RELOC_PPC_EMB_NADDR16
2810 BFD_RELOC_PPC_EMB_NADDR16_LO
2812 BFD_RELOC_PPC_EMB_NADDR16_HI
2814 BFD_RELOC_PPC_EMB_NADDR16_HA
2816 BFD_RELOC_PPC_EMB_SDAI16
2818 BFD_RELOC_PPC_EMB_SDA2I16
2820 BFD_RELOC_PPC_EMB_SDA2REL
2822 BFD_RELOC_PPC_EMB_SDA21
2824 BFD_RELOC_PPC_EMB_MRKREF
2826 BFD_RELOC_PPC_EMB_RELSEC16
2828 BFD_RELOC_PPC_EMB_RELST_LO
2830 BFD_RELOC_PPC_EMB_RELST_HI
2832 BFD_RELOC_PPC_EMB_RELST_HA
2834 BFD_RELOC_PPC_EMB_BIT_FLD
2836 BFD_RELOC_PPC_EMB_RELSDA
2838 BFD_RELOC_PPC_VLE_REL8
2840 BFD_RELOC_PPC_VLE_REL15
2842 BFD_RELOC_PPC_VLE_REL24
2844 BFD_RELOC_PPC_VLE_LO16A
2846 BFD_RELOC_PPC_VLE_LO16D
2848 BFD_RELOC_PPC_VLE_HI16A
2850 BFD_RELOC_PPC_VLE_HI16D
2852 BFD_RELOC_PPC_VLE_HA16A
2854 BFD_RELOC_PPC_VLE_HA16D
2856 BFD_RELOC_PPC_VLE_SDA21
2858 BFD_RELOC_PPC_VLE_SDA21_LO
2860 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2862 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2864 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2866 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2868 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2870 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2872 BFD_RELOC_PPC64_HIGHER
2874 BFD_RELOC_PPC64_HIGHER_S
2876 BFD_RELOC_PPC64_HIGHEST
2878 BFD_RELOC_PPC64_HIGHEST_S
2880 BFD_RELOC_PPC64_TOC16_LO
2882 BFD_RELOC_PPC64_TOC16_HI
2884 BFD_RELOC_PPC64_TOC16_HA
2888 BFD_RELOC_PPC64_PLTGOT16
2890 BFD_RELOC_PPC64_PLTGOT16_LO
2892 BFD_RELOC_PPC64_PLTGOT16_HI
2894 BFD_RELOC_PPC64_PLTGOT16_HA
2896 BFD_RELOC_PPC64_ADDR16_DS
2898 BFD_RELOC_PPC64_ADDR16_LO_DS
2900 BFD_RELOC_PPC64_GOT16_DS
2902 BFD_RELOC_PPC64_GOT16_LO_DS
2904 BFD_RELOC_PPC64_PLT16_LO_DS
2906 BFD_RELOC_PPC64_SECTOFF_DS
2908 BFD_RELOC_PPC64_SECTOFF_LO_DS
2910 BFD_RELOC_PPC64_TOC16_DS
2912 BFD_RELOC_PPC64_TOC16_LO_DS
2914 BFD_RELOC_PPC64_PLTGOT16_DS
2916 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2918 BFD_RELOC_PPC64_ADDR16_HIGH
2920 BFD_RELOC_PPC64_ADDR16_HIGHA
2922 BFD_RELOC_PPC64_ADDR64_LOCAL
2924 Power(rs6000) and PowerPC relocations.
2933 BFD_RELOC_PPC_DTPMOD
2935 BFD_RELOC_PPC_TPREL16
2937 BFD_RELOC_PPC_TPREL16_LO
2939 BFD_RELOC_PPC_TPREL16_HI
2941 BFD_RELOC_PPC_TPREL16_HA
2945 BFD_RELOC_PPC_DTPREL16
2947 BFD_RELOC_PPC_DTPREL16_LO
2949 BFD_RELOC_PPC_DTPREL16_HI
2951 BFD_RELOC_PPC_DTPREL16_HA
2953 BFD_RELOC_PPC_DTPREL
2955 BFD_RELOC_PPC_GOT_TLSGD16
2957 BFD_RELOC_PPC_GOT_TLSGD16_LO
2959 BFD_RELOC_PPC_GOT_TLSGD16_HI
2961 BFD_RELOC_PPC_GOT_TLSGD16_HA
2963 BFD_RELOC_PPC_GOT_TLSLD16
2965 BFD_RELOC_PPC_GOT_TLSLD16_LO
2967 BFD_RELOC_PPC_GOT_TLSLD16_HI
2969 BFD_RELOC_PPC_GOT_TLSLD16_HA
2971 BFD_RELOC_PPC_GOT_TPREL16
2973 BFD_RELOC_PPC_GOT_TPREL16_LO
2975 BFD_RELOC_PPC_GOT_TPREL16_HI
2977 BFD_RELOC_PPC_GOT_TPREL16_HA
2979 BFD_RELOC_PPC_GOT_DTPREL16
2981 BFD_RELOC_PPC_GOT_DTPREL16_LO
2983 BFD_RELOC_PPC_GOT_DTPREL16_HI
2985 BFD_RELOC_PPC_GOT_DTPREL16_HA
2987 BFD_RELOC_PPC64_TPREL16_DS
2989 BFD_RELOC_PPC64_TPREL16_LO_DS
2991 BFD_RELOC_PPC64_TPREL16_HIGHER
2993 BFD_RELOC_PPC64_TPREL16_HIGHERA
2995 BFD_RELOC_PPC64_TPREL16_HIGHEST
2997 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2999 BFD_RELOC_PPC64_DTPREL16_DS
3001 BFD_RELOC_PPC64_DTPREL16_LO_DS
3003 BFD_RELOC_PPC64_DTPREL16_HIGHER
3005 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3007 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3009 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3011 BFD_RELOC_PPC64_TPREL16_HIGH
3013 BFD_RELOC_PPC64_TPREL16_HIGHA
3015 BFD_RELOC_PPC64_DTPREL16_HIGH
3017 BFD_RELOC_PPC64_DTPREL16_HIGHA
3019 PowerPC and PowerPC64 thread-local storage relocations.
3024 IBM 370/390 relocations
3029 The type of reloc used to build a constructor table - at the moment
3030 probably a 32 bit wide absolute relocation, but the target can choose.
3031 It generally does map to one of the other relocation types.
3034 BFD_RELOC_ARM_PCREL_BRANCH
3036 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3037 not stored in the instruction.
3039 BFD_RELOC_ARM_PCREL_BLX
3041 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3042 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3043 field in the instruction.
3045 BFD_RELOC_THUMB_PCREL_BLX
3047 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3048 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3049 field in the instruction.
3051 BFD_RELOC_ARM_PCREL_CALL
3053 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3055 BFD_RELOC_ARM_PCREL_JUMP
3057 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3060 BFD_RELOC_THUMB_PCREL_BRANCH7
3062 BFD_RELOC_THUMB_PCREL_BRANCH9
3064 BFD_RELOC_THUMB_PCREL_BRANCH12
3066 BFD_RELOC_THUMB_PCREL_BRANCH20
3068 BFD_RELOC_THUMB_PCREL_BRANCH23
3070 BFD_RELOC_THUMB_PCREL_BRANCH25
3072 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3073 The lowest bit must be zero and is not stored in the instruction.
3074 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3075 "nn" one smaller in all cases. Note further that BRANCH23
3076 corresponds to R_ARM_THM_CALL.
3079 BFD_RELOC_ARM_OFFSET_IMM
3081 12-bit immediate offset, used in ARM-format ldr and str instructions.
3084 BFD_RELOC_ARM_THUMB_OFFSET
3086 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3089 BFD_RELOC_ARM_TARGET1
3091 Pc-relative or absolute relocation depending on target. Used for
3092 entries in .init_array sections.
3094 BFD_RELOC_ARM_ROSEGREL32
3096 Read-only segment base relative address.
3098 BFD_RELOC_ARM_SBREL32
3100 Data segment base relative address.
3102 BFD_RELOC_ARM_TARGET2
3104 This reloc is used for references to RTTI data from exception handling
3105 tables. The actual definition depends on the target. It may be a
3106 pc-relative or some form of GOT-indirect relocation.
3108 BFD_RELOC_ARM_PREL31
3110 31-bit PC relative address.
3116 BFD_RELOC_ARM_MOVW_PCREL
3118 BFD_RELOC_ARM_MOVT_PCREL
3120 BFD_RELOC_ARM_THUMB_MOVW
3122 BFD_RELOC_ARM_THUMB_MOVT
3124 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3126 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3128 Low and High halfword relocations for MOVW and MOVT instructions.
3131 BFD_RELOC_ARM_JUMP_SLOT
3133 BFD_RELOC_ARM_GLOB_DAT
3139 BFD_RELOC_ARM_RELATIVE
3141 BFD_RELOC_ARM_GOTOFF
3145 BFD_RELOC_ARM_GOT_PREL
3147 Relocations for setting up GOTs and PLTs for shared libraries.
3150 BFD_RELOC_ARM_TLS_GD32
3152 BFD_RELOC_ARM_TLS_LDO32
3154 BFD_RELOC_ARM_TLS_LDM32
3156 BFD_RELOC_ARM_TLS_DTPOFF32
3158 BFD_RELOC_ARM_TLS_DTPMOD32
3160 BFD_RELOC_ARM_TLS_TPOFF32
3162 BFD_RELOC_ARM_TLS_IE32
3164 BFD_RELOC_ARM_TLS_LE32
3166 BFD_RELOC_ARM_TLS_GOTDESC
3168 BFD_RELOC_ARM_TLS_CALL
3170 BFD_RELOC_ARM_THM_TLS_CALL
3172 BFD_RELOC_ARM_TLS_DESCSEQ
3174 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3176 BFD_RELOC_ARM_TLS_DESC
3178 ARM thread-local storage relocations.
3181 BFD_RELOC_ARM_ALU_PC_G0_NC
3183 BFD_RELOC_ARM_ALU_PC_G0
3185 BFD_RELOC_ARM_ALU_PC_G1_NC
3187 BFD_RELOC_ARM_ALU_PC_G1
3189 BFD_RELOC_ARM_ALU_PC_G2
3191 BFD_RELOC_ARM_LDR_PC_G0
3193 BFD_RELOC_ARM_LDR_PC_G1
3195 BFD_RELOC_ARM_LDR_PC_G2
3197 BFD_RELOC_ARM_LDRS_PC_G0
3199 BFD_RELOC_ARM_LDRS_PC_G1
3201 BFD_RELOC_ARM_LDRS_PC_G2
3203 BFD_RELOC_ARM_LDC_PC_G0
3205 BFD_RELOC_ARM_LDC_PC_G1
3207 BFD_RELOC_ARM_LDC_PC_G2
3209 BFD_RELOC_ARM_ALU_SB_G0_NC
3211 BFD_RELOC_ARM_ALU_SB_G0
3213 BFD_RELOC_ARM_ALU_SB_G1_NC
3215 BFD_RELOC_ARM_ALU_SB_G1
3217 BFD_RELOC_ARM_ALU_SB_G2
3219 BFD_RELOC_ARM_LDR_SB_G0
3221 BFD_RELOC_ARM_LDR_SB_G1
3223 BFD_RELOC_ARM_LDR_SB_G2
3225 BFD_RELOC_ARM_LDRS_SB_G0
3227 BFD_RELOC_ARM_LDRS_SB_G1
3229 BFD_RELOC_ARM_LDRS_SB_G2
3231 BFD_RELOC_ARM_LDC_SB_G0
3233 BFD_RELOC_ARM_LDC_SB_G1
3235 BFD_RELOC_ARM_LDC_SB_G2
3237 ARM group relocations.
3242 Annotation of BX instructions.
3245 BFD_RELOC_ARM_IRELATIVE
3247 ARM support for STT_GNU_IFUNC.
3250 BFD_RELOC_ARM_IMMEDIATE
3252 BFD_RELOC_ARM_ADRL_IMMEDIATE
3254 BFD_RELOC_ARM_T32_IMMEDIATE
3256 BFD_RELOC_ARM_T32_ADD_IMM
3258 BFD_RELOC_ARM_T32_IMM12
3260 BFD_RELOC_ARM_T32_ADD_PC12
3262 BFD_RELOC_ARM_SHIFT_IMM
3272 BFD_RELOC_ARM_CP_OFF_IMM
3274 BFD_RELOC_ARM_CP_OFF_IMM_S2
3276 BFD_RELOC_ARM_T32_CP_OFF_IMM
3278 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3280 BFD_RELOC_ARM_ADR_IMM
3282 BFD_RELOC_ARM_LDR_IMM
3284 BFD_RELOC_ARM_LITERAL
3286 BFD_RELOC_ARM_IN_POOL
3288 BFD_RELOC_ARM_OFFSET_IMM8
3290 BFD_RELOC_ARM_T32_OFFSET_U8
3292 BFD_RELOC_ARM_T32_OFFSET_IMM
3294 BFD_RELOC_ARM_HWLITERAL
3296 BFD_RELOC_ARM_THUMB_ADD
3298 BFD_RELOC_ARM_THUMB_IMM
3300 BFD_RELOC_ARM_THUMB_SHIFT
3302 These relocs are only used within the ARM assembler. They are not
3303 (at present) written to any object files.
3306 BFD_RELOC_SH_PCDISP8BY2
3308 BFD_RELOC_SH_PCDISP12BY2
3316 BFD_RELOC_SH_DISP12BY2
3318 BFD_RELOC_SH_DISP12BY4
3320 BFD_RELOC_SH_DISP12BY8
3324 BFD_RELOC_SH_DISP20BY8
3328 BFD_RELOC_SH_IMM4BY2
3330 BFD_RELOC_SH_IMM4BY4
3334 BFD_RELOC_SH_IMM8BY2
3336 BFD_RELOC_SH_IMM8BY4
3338 BFD_RELOC_SH_PCRELIMM8BY2
3340 BFD_RELOC_SH_PCRELIMM8BY4
3342 BFD_RELOC_SH_SWITCH16
3344 BFD_RELOC_SH_SWITCH32
3358 BFD_RELOC_SH_LOOP_START
3360 BFD_RELOC_SH_LOOP_END
3364 BFD_RELOC_SH_GLOB_DAT
3366 BFD_RELOC_SH_JMP_SLOT
3368 BFD_RELOC_SH_RELATIVE
3372 BFD_RELOC_SH_GOT_LOW16
3374 BFD_RELOC_SH_GOT_MEDLOW16
3376 BFD_RELOC_SH_GOT_MEDHI16
3378 BFD_RELOC_SH_GOT_HI16
3380 BFD_RELOC_SH_GOTPLT_LOW16
3382 BFD_RELOC_SH_GOTPLT_MEDLOW16
3384 BFD_RELOC_SH_GOTPLT_MEDHI16
3386 BFD_RELOC_SH_GOTPLT_HI16
3388 BFD_RELOC_SH_PLT_LOW16
3390 BFD_RELOC_SH_PLT_MEDLOW16
3392 BFD_RELOC_SH_PLT_MEDHI16
3394 BFD_RELOC_SH_PLT_HI16
3396 BFD_RELOC_SH_GOTOFF_LOW16
3398 BFD_RELOC_SH_GOTOFF_MEDLOW16
3400 BFD_RELOC_SH_GOTOFF_MEDHI16
3402 BFD_RELOC_SH_GOTOFF_HI16
3404 BFD_RELOC_SH_GOTPC_LOW16
3406 BFD_RELOC_SH_GOTPC_MEDLOW16
3408 BFD_RELOC_SH_GOTPC_MEDHI16
3410 BFD_RELOC_SH_GOTPC_HI16
3414 BFD_RELOC_SH_GLOB_DAT64
3416 BFD_RELOC_SH_JMP_SLOT64
3418 BFD_RELOC_SH_RELATIVE64
3420 BFD_RELOC_SH_GOT10BY4
3422 BFD_RELOC_SH_GOT10BY8
3424 BFD_RELOC_SH_GOTPLT10BY4
3426 BFD_RELOC_SH_GOTPLT10BY8
3428 BFD_RELOC_SH_GOTPLT32
3430 BFD_RELOC_SH_SHMEDIA_CODE
3436 BFD_RELOC_SH_IMMS6BY32
3442 BFD_RELOC_SH_IMMS10BY2
3444 BFD_RELOC_SH_IMMS10BY4
3446 BFD_RELOC_SH_IMMS10BY8
3452 BFD_RELOC_SH_IMM_LOW16
3454 BFD_RELOC_SH_IMM_LOW16_PCREL
3456 BFD_RELOC_SH_IMM_MEDLOW16
3458 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3460 BFD_RELOC_SH_IMM_MEDHI16
3462 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3464 BFD_RELOC_SH_IMM_HI16
3466 BFD_RELOC_SH_IMM_HI16_PCREL
3470 BFD_RELOC_SH_TLS_GD_32
3472 BFD_RELOC_SH_TLS_LD_32
3474 BFD_RELOC_SH_TLS_LDO_32
3476 BFD_RELOC_SH_TLS_IE_32
3478 BFD_RELOC_SH_TLS_LE_32
3480 BFD_RELOC_SH_TLS_DTPMOD32
3482 BFD_RELOC_SH_TLS_DTPOFF32
3484 BFD_RELOC_SH_TLS_TPOFF32
3488 BFD_RELOC_SH_GOTOFF20
3490 BFD_RELOC_SH_GOTFUNCDESC
3492 BFD_RELOC_SH_GOTFUNCDESC20
3494 BFD_RELOC_SH_GOTOFFFUNCDESC
3496 BFD_RELOC_SH_GOTOFFFUNCDESC20
3498 BFD_RELOC_SH_FUNCDESC
3500 Renesas / SuperH SH relocs. Not all of these appear in object files.
3503 BFD_RELOC_ARC_B22_PCREL
3506 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3507 not stored in the instruction. The high 20 bits are installed in bits 26
3508 through 7 of the instruction.
3512 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3513 stored in the instruction. The high 24 bits are installed in bits 23
3517 BFD_RELOC_BFIN_16_IMM
3519 ADI Blackfin 16 bit immediate absolute reloc.
3521 BFD_RELOC_BFIN_16_HIGH
3523 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3525 BFD_RELOC_BFIN_4_PCREL
3527 ADI Blackfin 'a' part of LSETUP.
3529 BFD_RELOC_BFIN_5_PCREL
3533 BFD_RELOC_BFIN_16_LOW
3535 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3537 BFD_RELOC_BFIN_10_PCREL
3541 BFD_RELOC_BFIN_11_PCREL
3543 ADI Blackfin 'b' part of LSETUP.
3545 BFD_RELOC_BFIN_12_PCREL_JUMP
3549 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3551 ADI Blackfin Short jump, pcrel.
3553 BFD_RELOC_BFIN_24_PCREL_CALL_X
3555 ADI Blackfin Call.x not implemented.
3557 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3559 ADI Blackfin Long Jump pcrel.
3561 BFD_RELOC_BFIN_GOT17M4
3563 BFD_RELOC_BFIN_GOTHI
3565 BFD_RELOC_BFIN_GOTLO
3567 BFD_RELOC_BFIN_FUNCDESC
3569 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3571 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3573 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3575 BFD_RELOC_BFIN_FUNCDESC_VALUE
3577 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3579 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3581 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3583 BFD_RELOC_BFIN_GOTOFF17M4
3585 BFD_RELOC_BFIN_GOTOFFHI
3587 BFD_RELOC_BFIN_GOTOFFLO
3589 ADI Blackfin FD-PIC relocations.
3593 ADI Blackfin GOT relocation.
3595 BFD_RELOC_BFIN_PLTPC
3597 ADI Blackfin PLTPC relocation.
3599 BFD_ARELOC_BFIN_PUSH
3601 ADI Blackfin arithmetic relocation.
3603 BFD_ARELOC_BFIN_CONST
3605 ADI Blackfin arithmetic relocation.
3609 ADI Blackfin arithmetic relocation.
3613 ADI Blackfin arithmetic relocation.
3615 BFD_ARELOC_BFIN_MULT
3617 ADI Blackfin arithmetic relocation.
3621 ADI Blackfin arithmetic relocation.
3625 ADI Blackfin arithmetic relocation.
3627 BFD_ARELOC_BFIN_LSHIFT
3629 ADI Blackfin arithmetic relocation.
3631 BFD_ARELOC_BFIN_RSHIFT
3633 ADI Blackfin arithmetic relocation.
3637 ADI Blackfin arithmetic relocation.
3641 ADI Blackfin arithmetic relocation.
3645 ADI Blackfin arithmetic relocation.
3647 BFD_ARELOC_BFIN_LAND
3649 ADI Blackfin arithmetic relocation.
3653 ADI Blackfin arithmetic relocation.
3657 ADI Blackfin arithmetic relocation.
3661 ADI Blackfin arithmetic relocation.
3663 BFD_ARELOC_BFIN_COMP
3665 ADI Blackfin arithmetic relocation.
3667 BFD_ARELOC_BFIN_PAGE
3669 ADI Blackfin arithmetic relocation.
3671 BFD_ARELOC_BFIN_HWPAGE
3673 ADI Blackfin arithmetic relocation.
3675 BFD_ARELOC_BFIN_ADDR
3677 ADI Blackfin arithmetic relocation.
3680 BFD_RELOC_D10V_10_PCREL_R
3682 Mitsubishi D10V relocs.
3683 This is a 10-bit reloc with the right 2 bits
3686 BFD_RELOC_D10V_10_PCREL_L
3688 Mitsubishi D10V relocs.
3689 This is a 10-bit reloc with the right 2 bits
3690 assumed to be 0. This is the same as the previous reloc
3691 except it is in the left container, i.e.,
3692 shifted left 15 bits.
3696 This is an 18-bit reloc with the right 2 bits
3699 BFD_RELOC_D10V_18_PCREL
3701 This is an 18-bit reloc with the right 2 bits
3707 Mitsubishi D30V relocs.
3708 This is a 6-bit absolute reloc.
3710 BFD_RELOC_D30V_9_PCREL
3712 This is a 6-bit pc-relative reloc with
3713 the right 3 bits assumed to be 0.
3715 BFD_RELOC_D30V_9_PCREL_R
3717 This is a 6-bit pc-relative reloc with
3718 the right 3 bits assumed to be 0. Same
3719 as the previous reloc but on the right side
3724 This is a 12-bit absolute reloc with the
3725 right 3 bitsassumed to be 0.
3727 BFD_RELOC_D30V_15_PCREL
3729 This is a 12-bit pc-relative reloc with
3730 the right 3 bits assumed to be 0.
3732 BFD_RELOC_D30V_15_PCREL_R
3734 This is a 12-bit pc-relative reloc with
3735 the right 3 bits assumed to be 0. Same
3736 as the previous reloc but on the right side
3741 This is an 18-bit absolute reloc with
3742 the right 3 bits assumed to be 0.
3744 BFD_RELOC_D30V_21_PCREL
3746 This is an 18-bit pc-relative reloc with
3747 the right 3 bits assumed to be 0.
3749 BFD_RELOC_D30V_21_PCREL_R
3751 This is an 18-bit pc-relative reloc with
3752 the right 3 bits assumed to be 0. Same
3753 as the previous reloc but on the right side
3758 This is a 32-bit absolute reloc.
3760 BFD_RELOC_D30V_32_PCREL
3762 This is a 32-bit pc-relative reloc.
3765 BFD_RELOC_DLX_HI16_S
3780 BFD_RELOC_M32C_RL_JUMP
3782 BFD_RELOC_M32C_RL_1ADDR
3784 BFD_RELOC_M32C_RL_2ADDR
3786 Renesas M16C/M32C Relocations.
3791 Renesas M32R (formerly Mitsubishi M32R) relocs.
3792 This is a 24 bit absolute address.
3794 BFD_RELOC_M32R_10_PCREL
3796 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3798 BFD_RELOC_M32R_18_PCREL
3800 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3802 BFD_RELOC_M32R_26_PCREL
3804 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3806 BFD_RELOC_M32R_HI16_ULO
3808 This is a 16-bit reloc containing the high 16 bits of an address
3809 used when the lower 16 bits are treated as unsigned.
3811 BFD_RELOC_M32R_HI16_SLO
3813 This is a 16-bit reloc containing the high 16 bits of an address
3814 used when the lower 16 bits are treated as signed.
3818 This is a 16-bit reloc containing the lower 16 bits of an address.
3820 BFD_RELOC_M32R_SDA16
3822 This is a 16-bit reloc containing the small data area offset for use in
3823 add3, load, and store instructions.
3825 BFD_RELOC_M32R_GOT24
3827 BFD_RELOC_M32R_26_PLTREL
3831 BFD_RELOC_M32R_GLOB_DAT
3833 BFD_RELOC_M32R_JMP_SLOT
3835 BFD_RELOC_M32R_RELATIVE
3837 BFD_RELOC_M32R_GOTOFF
3839 BFD_RELOC_M32R_GOTOFF_HI_ULO
3841 BFD_RELOC_M32R_GOTOFF_HI_SLO
3843 BFD_RELOC_M32R_GOTOFF_LO
3845 BFD_RELOC_M32R_GOTPC24
3847 BFD_RELOC_M32R_GOT16_HI_ULO
3849 BFD_RELOC_M32R_GOT16_HI_SLO
3851 BFD_RELOC_M32R_GOT16_LO
3853 BFD_RELOC_M32R_GOTPC_HI_ULO
3855 BFD_RELOC_M32R_GOTPC_HI_SLO
3857 BFD_RELOC_M32R_GOTPC_LO
3866 This is a 20 bit absolute address.
3868 BFD_RELOC_NDS32_9_PCREL
3870 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3872 BFD_RELOC_NDS32_WORD_9_PCREL
3874 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3876 BFD_RELOC_NDS32_15_PCREL
3878 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3880 BFD_RELOC_NDS32_17_PCREL
3882 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3884 BFD_RELOC_NDS32_25_PCREL
3886 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3888 BFD_RELOC_NDS32_HI20
3890 This is a 20-bit reloc containing the high 20 bits of an address
3891 used with the lower 12 bits
3893 BFD_RELOC_NDS32_LO12S3
3895 This is a 12-bit reloc containing the lower 12 bits of an address
3896 then shift right by 3. This is used with ldi,sdi...
3898 BFD_RELOC_NDS32_LO12S2
3900 This is a 12-bit reloc containing the lower 12 bits of an address
3901 then shift left by 2. This is used with lwi,swi...
3903 BFD_RELOC_NDS32_LO12S1
3905 This is a 12-bit reloc containing the lower 12 bits of an address
3906 then shift left by 1. This is used with lhi,shi...
3908 BFD_RELOC_NDS32_LO12S0
3910 This is a 12-bit reloc containing the lower 12 bits of an address
3911 then shift left by 0. This is used with lbisbi...
3913 BFD_RELOC_NDS32_LO12S0_ORI
3915 This is a 12-bit reloc containing the lower 12 bits of an address
3916 then shift left by 0. This is only used with branch relaxations
3918 BFD_RELOC_NDS32_SDA15S3
3920 This is a 15-bit reloc containing the small data area 18-bit signed offset
3921 and shift left by 3 for use in ldi, sdi...
3923 BFD_RELOC_NDS32_SDA15S2
3925 This is a 15-bit reloc containing the small data area 17-bit signed offset
3926 and shift left by 2 for use in lwi, swi...
3928 BFD_RELOC_NDS32_SDA15S1
3930 This is a 15-bit reloc containing the small data area 16-bit signed offset
3931 and shift left by 1 for use in lhi, shi...
3933 BFD_RELOC_NDS32_SDA15S0
3935 This is a 15-bit reloc containing the small data area 15-bit signed offset
3936 and shift left by 0 for use in lbi, sbi...
3938 BFD_RELOC_NDS32_SDA16S3
3940 This is a 16-bit reloc containing the small data area 16-bit signed offset
3943 BFD_RELOC_NDS32_SDA17S2
3945 This is a 17-bit reloc containing the small data area 17-bit signed offset
3946 and shift left by 2 for use in lwi.gp, swi.gp...
3948 BFD_RELOC_NDS32_SDA18S1
3950 This is a 18-bit reloc containing the small data area 18-bit signed offset
3951 and shift left by 1 for use in lhi.gp, shi.gp...
3953 BFD_RELOC_NDS32_SDA19S0
3955 This is a 19-bit reloc containing the small data area 19-bit signed offset
3956 and shift left by 0 for use in lbi.gp, sbi.gp...
3958 BFD_RELOC_NDS32_GOT20
3960 BFD_RELOC_NDS32_9_PLTREL
3962 BFD_RELOC_NDS32_25_PLTREL
3964 BFD_RELOC_NDS32_COPY
3966 BFD_RELOC_NDS32_GLOB_DAT
3968 BFD_RELOC_NDS32_JMP_SLOT
3970 BFD_RELOC_NDS32_RELATIVE
3972 BFD_RELOC_NDS32_GOTOFF
3974 BFD_RELOC_NDS32_GOTOFF_HI20
3976 BFD_RELOC_NDS32_GOTOFF_LO12
3978 BFD_RELOC_NDS32_GOTPC20
3980 BFD_RELOC_NDS32_GOT_HI20
3982 BFD_RELOC_NDS32_GOT_LO12
3984 BFD_RELOC_NDS32_GOTPC_HI20
3986 BFD_RELOC_NDS32_GOTPC_LO12
3990 BFD_RELOC_NDS32_INSN16
3992 BFD_RELOC_NDS32_LABEL
3994 BFD_RELOC_NDS32_LONGCALL1
3996 BFD_RELOC_NDS32_LONGCALL2
3998 BFD_RELOC_NDS32_LONGCALL3
4000 BFD_RELOC_NDS32_LONGJUMP1
4002 BFD_RELOC_NDS32_LONGJUMP2
4004 BFD_RELOC_NDS32_LONGJUMP3
4006 BFD_RELOC_NDS32_LOADSTORE
4008 BFD_RELOC_NDS32_9_FIXED
4010 BFD_RELOC_NDS32_15_FIXED
4012 BFD_RELOC_NDS32_17_FIXED
4014 BFD_RELOC_NDS32_25_FIXED
4016 BFD_RELOC_NDS32_LONGCALL4
4018 BFD_RELOC_NDS32_LONGCALL5
4020 BFD_RELOC_NDS32_LONGCALL6
4022 BFD_RELOC_NDS32_LONGJUMP4
4024 BFD_RELOC_NDS32_LONGJUMP5
4026 BFD_RELOC_NDS32_LONGJUMP6
4028 BFD_RELOC_NDS32_LONGJUMP7
4032 BFD_RELOC_NDS32_PLTREL_HI20
4034 BFD_RELOC_NDS32_PLTREL_LO12
4036 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4038 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4042 BFD_RELOC_NDS32_SDA12S2_DP
4044 BFD_RELOC_NDS32_SDA12S2_SP
4046 BFD_RELOC_NDS32_LO12S2_DP
4048 BFD_RELOC_NDS32_LO12S2_SP
4052 BFD_RELOC_NDS32_DWARF2_OP1
4054 BFD_RELOC_NDS32_DWARF2_OP2
4056 BFD_RELOC_NDS32_DWARF2_LEB
4058 for dwarf2 debug_line.
4060 BFD_RELOC_NDS32_UPDATE_TA
4062 for eliminate 16-bit instructions
4064 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4066 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4068 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4070 BFD_RELOC_NDS32_GOT_LO15
4072 BFD_RELOC_NDS32_GOT_LO19
4074 BFD_RELOC_NDS32_GOTOFF_LO15
4076 BFD_RELOC_NDS32_GOTOFF_LO19
4078 BFD_RELOC_NDS32_GOT15S2
4080 BFD_RELOC_NDS32_GOT17S2
4082 for PIC object relaxation
4087 This is a 5 bit absolute address.
4089 BFD_RELOC_NDS32_10_UPCREL
4091 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4093 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4095 If fp were omitted, fp can used as another gp.
4097 BFD_RELOC_NDS32_RELAX_ENTRY
4099 BFD_RELOC_NDS32_GOT_SUFF
4101 BFD_RELOC_NDS32_GOTOFF_SUFF
4103 BFD_RELOC_NDS32_PLT_GOT_SUFF
4105 BFD_RELOC_NDS32_MULCALL_SUFF
4109 BFD_RELOC_NDS32_PTR_COUNT
4111 BFD_RELOC_NDS32_PTR_RESOLVED
4113 BFD_RELOC_NDS32_PLTBLOCK
4115 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4117 BFD_RELOC_NDS32_RELAX_REGION_END
4119 BFD_RELOC_NDS32_MINUEND
4121 BFD_RELOC_NDS32_SUBTRAHEND
4123 BFD_RELOC_NDS32_DIFF8
4125 BFD_RELOC_NDS32_DIFF16
4127 BFD_RELOC_NDS32_DIFF32
4129 BFD_RELOC_NDS32_DIFF_ULEB128
4131 BFD_RELOC_NDS32_EMPTY
4133 relaxation relative relocation types
4135 BFD_RELOC_NDS32_25_ABS
4137 This is a 25 bit absolute address.
4139 BFD_RELOC_NDS32_DATA
4141 BFD_RELOC_NDS32_TRAN
4143 BFD_RELOC_NDS32_17IFC_PCREL
4145 BFD_RELOC_NDS32_10IFCU_PCREL
4147 For ex9 and ifc using.
4149 BFD_RELOC_NDS32_TPOFF
4151 BFD_RELOC_NDS32_TLS_LE_HI20
4153 BFD_RELOC_NDS32_TLS_LE_LO12
4155 BFD_RELOC_NDS32_TLS_LE_ADD
4157 BFD_RELOC_NDS32_TLS_LE_LS
4159 BFD_RELOC_NDS32_GOTTPOFF
4161 BFD_RELOC_NDS32_TLS_IE_HI20
4163 BFD_RELOC_NDS32_TLS_IE_LO12S2
4165 BFD_RELOC_NDS32_TLS_TPOFF
4167 BFD_RELOC_NDS32_TLS_LE_20
4169 BFD_RELOC_NDS32_TLS_LE_15S0
4171 BFD_RELOC_NDS32_TLS_LE_15S1
4173 BFD_RELOC_NDS32_TLS_LE_15S2
4179 BFD_RELOC_V850_9_PCREL
4181 This is a 9-bit reloc
4183 BFD_RELOC_V850_22_PCREL
4185 This is a 22-bit reloc
4188 BFD_RELOC_V850_SDA_16_16_OFFSET
4190 This is a 16 bit offset from the short data area pointer.
4192 BFD_RELOC_V850_SDA_15_16_OFFSET
4194 This is a 16 bit offset (of which only 15 bits are used) from the
4195 short data area pointer.
4197 BFD_RELOC_V850_ZDA_16_16_OFFSET
4199 This is a 16 bit offset from the zero data area pointer.
4201 BFD_RELOC_V850_ZDA_15_16_OFFSET
4203 This is a 16 bit offset (of which only 15 bits are used) from the
4204 zero data area pointer.
4206 BFD_RELOC_V850_TDA_6_8_OFFSET
4208 This is an 8 bit offset (of which only 6 bits are used) from the
4209 tiny data area pointer.
4211 BFD_RELOC_V850_TDA_7_8_OFFSET
4213 This is an 8bit offset (of which only 7 bits are used) from the tiny
4216 BFD_RELOC_V850_TDA_7_7_OFFSET
4218 This is a 7 bit offset from the tiny data area pointer.
4220 BFD_RELOC_V850_TDA_16_16_OFFSET
4222 This is a 16 bit offset from the tiny data area pointer.
4225 BFD_RELOC_V850_TDA_4_5_OFFSET
4227 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4230 BFD_RELOC_V850_TDA_4_4_OFFSET
4232 This is a 4 bit offset from the tiny data area pointer.
4234 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4236 This is a 16 bit offset from the short data area pointer, with the
4237 bits placed non-contiguously in the instruction.
4239 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4241 This is a 16 bit offset from the zero data area pointer, with the
4242 bits placed non-contiguously in the instruction.
4244 BFD_RELOC_V850_CALLT_6_7_OFFSET
4246 This is a 6 bit offset from the call table base pointer.
4248 BFD_RELOC_V850_CALLT_16_16_OFFSET
4250 This is a 16 bit offset from the call table base pointer.
4252 BFD_RELOC_V850_LONGCALL
4254 Used for relaxing indirect function calls.
4256 BFD_RELOC_V850_LONGJUMP
4258 Used for relaxing indirect jumps.
4260 BFD_RELOC_V850_ALIGN
4262 Used to maintain alignment whilst relaxing.
4264 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4266 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4269 BFD_RELOC_V850_16_PCREL
4271 This is a 16-bit reloc.
4273 BFD_RELOC_V850_17_PCREL
4275 This is a 17-bit reloc.
4279 This is a 23-bit reloc.
4281 BFD_RELOC_V850_32_PCREL
4283 This is a 32-bit reloc.
4285 BFD_RELOC_V850_32_ABS
4287 This is a 32-bit reloc.
4289 BFD_RELOC_V850_16_SPLIT_OFFSET
4291 This is a 16-bit reloc.
4293 BFD_RELOC_V850_16_S1
4295 This is a 16-bit reloc.
4297 BFD_RELOC_V850_LO16_S1
4299 Low 16 bits. 16 bit shifted by 1.
4301 BFD_RELOC_V850_CALLT_15_16_OFFSET
4303 This is a 16 bit offset from the call table base pointer.
4305 BFD_RELOC_V850_32_GOTPCREL
4309 BFD_RELOC_V850_16_GOT
4313 BFD_RELOC_V850_32_GOT
4317 BFD_RELOC_V850_22_PLT_PCREL
4321 BFD_RELOC_V850_32_PLT_PCREL
4329 BFD_RELOC_V850_GLOB_DAT
4333 BFD_RELOC_V850_JMP_SLOT
4337 BFD_RELOC_V850_RELATIVE
4341 BFD_RELOC_V850_16_GOTOFF
4345 BFD_RELOC_V850_32_GOTOFF
4360 This is a 8bit DP reloc for the tms320c30, where the most
4361 significant 8 bits of a 24 bit word are placed into the least
4362 significant 8 bits of the opcode.
4365 BFD_RELOC_TIC54X_PARTLS7
4367 This is a 7bit reloc for the tms320c54x, where the least
4368 significant 7 bits of a 16 bit word are placed into the least
4369 significant 7 bits of the opcode.
4372 BFD_RELOC_TIC54X_PARTMS9
4374 This is a 9bit DP reloc for the tms320c54x, where the most
4375 significant 9 bits of a 16 bit word are placed into the least
4376 significant 9 bits of the opcode.
4381 This is an extended address 23-bit reloc for the tms320c54x.
4384 BFD_RELOC_TIC54X_16_OF_23
4386 This is a 16-bit reloc for the tms320c54x, where the least
4387 significant 16 bits of a 23-bit extended address are placed into
4391 BFD_RELOC_TIC54X_MS7_OF_23
4393 This is a reloc for the tms320c54x, where the most
4394 significant 7 bits of a 23-bit extended address are placed into
4398 BFD_RELOC_C6000_PCR_S21
4400 BFD_RELOC_C6000_PCR_S12
4402 BFD_RELOC_C6000_PCR_S10
4404 BFD_RELOC_C6000_PCR_S7
4406 BFD_RELOC_C6000_ABS_S16
4408 BFD_RELOC_C6000_ABS_L16
4410 BFD_RELOC_C6000_ABS_H16
4412 BFD_RELOC_C6000_SBR_U15_B
4414 BFD_RELOC_C6000_SBR_U15_H
4416 BFD_RELOC_C6000_SBR_U15_W
4418 BFD_RELOC_C6000_SBR_S16
4420 BFD_RELOC_C6000_SBR_L16_B
4422 BFD_RELOC_C6000_SBR_L16_H
4424 BFD_RELOC_C6000_SBR_L16_W
4426 BFD_RELOC_C6000_SBR_H16_B
4428 BFD_RELOC_C6000_SBR_H16_H
4430 BFD_RELOC_C6000_SBR_H16_W
4432 BFD_RELOC_C6000_SBR_GOT_U15_W
4434 BFD_RELOC_C6000_SBR_GOT_L16_W
4436 BFD_RELOC_C6000_SBR_GOT_H16_W
4438 BFD_RELOC_C6000_DSBT_INDEX
4440 BFD_RELOC_C6000_PREL31
4442 BFD_RELOC_C6000_COPY
4444 BFD_RELOC_C6000_JUMP_SLOT
4446 BFD_RELOC_C6000_EHTYPE
4448 BFD_RELOC_C6000_PCR_H16
4450 BFD_RELOC_C6000_PCR_L16
4452 BFD_RELOC_C6000_ALIGN
4454 BFD_RELOC_C6000_FPHEAD
4456 BFD_RELOC_C6000_NOCMP
4458 TMS320C6000 relocations.
4463 This is a 48 bit reloc for the FR30 that stores 32 bits.
4467 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4470 BFD_RELOC_FR30_6_IN_4
4472 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4475 BFD_RELOC_FR30_8_IN_8
4477 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4480 BFD_RELOC_FR30_9_IN_8
4482 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4485 BFD_RELOC_FR30_10_IN_8
4487 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4490 BFD_RELOC_FR30_9_PCREL
4492 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4493 short offset into 8 bits.
4495 BFD_RELOC_FR30_12_PCREL
4497 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4498 short offset into 11 bits.
4501 BFD_RELOC_MCORE_PCREL_IMM8BY4
4503 BFD_RELOC_MCORE_PCREL_IMM11BY2
4505 BFD_RELOC_MCORE_PCREL_IMM4BY2
4507 BFD_RELOC_MCORE_PCREL_32
4509 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4513 Motorola Mcore relocations.
4522 BFD_RELOC_MEP_PCREL8A2
4524 BFD_RELOC_MEP_PCREL12A2
4526 BFD_RELOC_MEP_PCREL17A2
4528 BFD_RELOC_MEP_PCREL24A2
4530 BFD_RELOC_MEP_PCABS24A2
4542 BFD_RELOC_MEP_TPREL7
4544 BFD_RELOC_MEP_TPREL7A2
4546 BFD_RELOC_MEP_TPREL7A4
4548 BFD_RELOC_MEP_UIMM24
4550 BFD_RELOC_MEP_ADDR24A4
4552 BFD_RELOC_MEP_GNU_VTINHERIT
4554 BFD_RELOC_MEP_GNU_VTENTRY
4556 Toshiba Media Processor Relocations.
4560 BFD_RELOC_METAG_HIADDR16
4562 BFD_RELOC_METAG_LOADDR16
4564 BFD_RELOC_METAG_RELBRANCH
4566 BFD_RELOC_METAG_GETSETOFF
4568 BFD_RELOC_METAG_HIOG
4570 BFD_RELOC_METAG_LOOG
4572 BFD_RELOC_METAG_REL8
4574 BFD_RELOC_METAG_REL16
4576 BFD_RELOC_METAG_HI16_GOTOFF
4578 BFD_RELOC_METAG_LO16_GOTOFF
4580 BFD_RELOC_METAG_GETSET_GOTOFF
4582 BFD_RELOC_METAG_GETSET_GOT
4584 BFD_RELOC_METAG_HI16_GOTPC
4586 BFD_RELOC_METAG_LO16_GOTPC
4588 BFD_RELOC_METAG_HI16_PLT
4590 BFD_RELOC_METAG_LO16_PLT
4592 BFD_RELOC_METAG_RELBRANCH_PLT
4594 BFD_RELOC_METAG_GOTOFF
4598 BFD_RELOC_METAG_COPY
4600 BFD_RELOC_METAG_JMP_SLOT
4602 BFD_RELOC_METAG_RELATIVE
4604 BFD_RELOC_METAG_GLOB_DAT
4606 BFD_RELOC_METAG_TLS_GD
4608 BFD_RELOC_METAG_TLS_LDM
4610 BFD_RELOC_METAG_TLS_LDO_HI16
4612 BFD_RELOC_METAG_TLS_LDO_LO16
4614 BFD_RELOC_METAG_TLS_LDO
4616 BFD_RELOC_METAG_TLS_IE
4618 BFD_RELOC_METAG_TLS_IENONPIC
4620 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4622 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4624 BFD_RELOC_METAG_TLS_TPOFF
4626 BFD_RELOC_METAG_TLS_DTPMOD
4628 BFD_RELOC_METAG_TLS_DTPOFF
4630 BFD_RELOC_METAG_TLS_LE
4632 BFD_RELOC_METAG_TLS_LE_HI16
4634 BFD_RELOC_METAG_TLS_LE_LO16
4636 Imagination Technologies Meta relocations.
4641 BFD_RELOC_MMIX_GETA_1
4643 BFD_RELOC_MMIX_GETA_2
4645 BFD_RELOC_MMIX_GETA_3
4647 These are relocations for the GETA instruction.
4649 BFD_RELOC_MMIX_CBRANCH
4651 BFD_RELOC_MMIX_CBRANCH_J
4653 BFD_RELOC_MMIX_CBRANCH_1
4655 BFD_RELOC_MMIX_CBRANCH_2
4657 BFD_RELOC_MMIX_CBRANCH_3
4659 These are relocations for a conditional branch instruction.
4661 BFD_RELOC_MMIX_PUSHJ
4663 BFD_RELOC_MMIX_PUSHJ_1
4665 BFD_RELOC_MMIX_PUSHJ_2
4667 BFD_RELOC_MMIX_PUSHJ_3
4669 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4671 These are relocations for the PUSHJ instruction.
4675 BFD_RELOC_MMIX_JMP_1
4677 BFD_RELOC_MMIX_JMP_2
4679 BFD_RELOC_MMIX_JMP_3
4681 These are relocations for the JMP instruction.
4683 BFD_RELOC_MMIX_ADDR19
4685 This is a relocation for a relative address as in a GETA instruction or
4688 BFD_RELOC_MMIX_ADDR27
4690 This is a relocation for a relative address as in a JMP instruction.
4692 BFD_RELOC_MMIX_REG_OR_BYTE
4694 This is a relocation for an instruction field that may be a general
4695 register or a value 0..255.
4699 This is a relocation for an instruction field that may be a general
4702 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4704 This is a relocation for two instruction fields holding a register and
4705 an offset, the equivalent of the relocation.
4707 BFD_RELOC_MMIX_LOCAL
4709 This relocation is an assertion that the expression is not allocated as
4710 a global register. It does not modify contents.
4713 BFD_RELOC_AVR_7_PCREL
4715 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4716 short offset into 7 bits.
4718 BFD_RELOC_AVR_13_PCREL
4720 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4721 short offset into 12 bits.
4725 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4726 program memory address) into 16 bits.
4728 BFD_RELOC_AVR_LO8_LDI
4730 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4731 data memory address) into 8 bit immediate value of LDI insn.
4733 BFD_RELOC_AVR_HI8_LDI
4735 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4736 of data memory address) into 8 bit immediate value of LDI insn.
4738 BFD_RELOC_AVR_HH8_LDI
4740 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4741 of program memory address) into 8 bit immediate value of LDI insn.
4743 BFD_RELOC_AVR_MS8_LDI
4745 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4746 of 32 bit value) into 8 bit immediate value of LDI insn.
4748 BFD_RELOC_AVR_LO8_LDI_NEG
4750 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4751 (usually data memory address) into 8 bit immediate value of SUBI insn.
4753 BFD_RELOC_AVR_HI8_LDI_NEG
4755 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4756 (high 8 bit of data memory address) into 8 bit immediate value of
4759 BFD_RELOC_AVR_HH8_LDI_NEG
4761 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4762 (most high 8 bit of program memory address) into 8 bit immediate value
4763 of LDI or SUBI insn.
4765 BFD_RELOC_AVR_MS8_LDI_NEG
4767 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4768 of 32 bit value) into 8 bit immediate value of LDI insn.
4770 BFD_RELOC_AVR_LO8_LDI_PM
4772 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4773 command address) into 8 bit immediate value of LDI insn.
4775 BFD_RELOC_AVR_LO8_LDI_GS
4777 This is a 16 bit reloc for the AVR that stores 8 bit value
4778 (command address) into 8 bit immediate value of LDI insn. If the address
4779 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4782 BFD_RELOC_AVR_HI8_LDI_PM
4784 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4785 of command address) into 8 bit immediate value of LDI insn.
4787 BFD_RELOC_AVR_HI8_LDI_GS
4789 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4790 of command address) into 8 bit immediate value of LDI insn. If the address
4791 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4794 BFD_RELOC_AVR_HH8_LDI_PM
4796 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4797 of command address) into 8 bit immediate value of LDI insn.
4799 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4801 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4802 (usually command address) into 8 bit immediate value of SUBI insn.
4804 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4806 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4807 (high 8 bit of 16 bit command address) into 8 bit immediate value
4810 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4812 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4813 (high 6 bit of 22 bit command address) into 8 bit immediate
4818 This is a 32 bit reloc for the AVR that stores 23 bit value
4823 This is a 16 bit reloc for the AVR that stores all needed bits
4824 for absolute addressing with ldi with overflow check to linktime
4828 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4831 BFD_RELOC_AVR_6_ADIW
4833 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4838 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4839 in .byte lo8(symbol)
4843 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4844 in .byte hi8(symbol)
4848 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4849 in .byte hlo8(symbol)
4853 BFD_RELOC_AVR_DIFF16
4855 BFD_RELOC_AVR_DIFF32
4857 AVR relocations to mark the difference of two local symbols.
4858 These are only needed to support linker relaxation and can be ignored
4859 when not relaxing. The field is set to the value of the difference
4860 assuming no relaxation. The relocation encodes the position of the
4861 second symbol so the linker can determine whether to adjust the field
4864 BFD_RELOC_AVR_LDS_STS_16
4866 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4867 lds and sts instructions supported only tiny core.
4871 This is a 6 bit reloc for the AVR that stores an I/O register
4872 number for the IN and OUT instructions
4876 This is a 5 bit reloc for the AVR that stores an I/O register
4877 number for the SBIC, SBIS, SBI and CBI instructions
4881 BFD_RELOC_RL78_NEG16
4883 BFD_RELOC_RL78_NEG24
4885 BFD_RELOC_RL78_NEG32
4887 BFD_RELOC_RL78_16_OP
4889 BFD_RELOC_RL78_24_OP
4891 BFD_RELOC_RL78_32_OP
4899 BFD_RELOC_RL78_DIR3U_PCREL
4903 BFD_RELOC_RL78_GPRELB
4905 BFD_RELOC_RL78_GPRELW
4907 BFD_RELOC_RL78_GPRELL
4911 BFD_RELOC_RL78_OP_SUBTRACT
4913 BFD_RELOC_RL78_OP_NEG
4915 BFD_RELOC_RL78_OP_AND
4917 BFD_RELOC_RL78_OP_SHRA
4921 BFD_RELOC_RL78_ABS16
4923 BFD_RELOC_RL78_ABS16_REV
4925 BFD_RELOC_RL78_ABS32
4927 BFD_RELOC_RL78_ABS32_REV
4929 BFD_RELOC_RL78_ABS16U
4931 BFD_RELOC_RL78_ABS16UW
4933 BFD_RELOC_RL78_ABS16UL
4935 BFD_RELOC_RL78_RELAX
4945 Renesas RL78 Relocations.
4968 BFD_RELOC_RX_DIR3U_PCREL
4980 BFD_RELOC_RX_OP_SUBTRACT
4988 BFD_RELOC_RX_ABS16_REV
4992 BFD_RELOC_RX_ABS32_REV
4996 BFD_RELOC_RX_ABS16UW
4998 BFD_RELOC_RX_ABS16UL
5002 Renesas RX Relocations.
5015 32 bit PC relative PLT address.
5019 Copy symbol at runtime.
5021 BFD_RELOC_390_GLOB_DAT
5025 BFD_RELOC_390_JMP_SLOT
5029 BFD_RELOC_390_RELATIVE
5031 Adjust by program base.
5035 32 bit PC relative offset to GOT.
5041 BFD_RELOC_390_PC12DBL
5043 PC relative 12 bit shifted by 1.
5045 BFD_RELOC_390_PLT12DBL
5047 12 bit PC rel. PLT shifted by 1.
5049 BFD_RELOC_390_PC16DBL
5051 PC relative 16 bit shifted by 1.
5053 BFD_RELOC_390_PLT16DBL
5055 16 bit PC rel. PLT shifted by 1.
5057 BFD_RELOC_390_PC24DBL
5059 PC relative 24 bit shifted by 1.
5061 BFD_RELOC_390_PLT24DBL
5063 24 bit PC rel. PLT shifted by 1.
5065 BFD_RELOC_390_PC32DBL
5067 PC relative 32 bit shifted by 1.
5069 BFD_RELOC_390_PLT32DBL
5071 32 bit PC rel. PLT shifted by 1.
5073 BFD_RELOC_390_GOTPCDBL
5075 32 bit PC rel. GOT shifted by 1.
5083 64 bit PC relative PLT address.
5085 BFD_RELOC_390_GOTENT
5087 32 bit rel. offset to GOT entry.
5089 BFD_RELOC_390_GOTOFF64
5091 64 bit offset to GOT.
5093 BFD_RELOC_390_GOTPLT12
5095 12-bit offset to symbol-entry within GOT, with PLT handling.
5097 BFD_RELOC_390_GOTPLT16
5099 16-bit offset to symbol-entry within GOT, with PLT handling.
5101 BFD_RELOC_390_GOTPLT32
5103 32-bit offset to symbol-entry within GOT, with PLT handling.
5105 BFD_RELOC_390_GOTPLT64
5107 64-bit offset to symbol-entry within GOT, with PLT handling.
5109 BFD_RELOC_390_GOTPLTENT
5111 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5113 BFD_RELOC_390_PLTOFF16
5115 16-bit rel. offset from the GOT to a PLT entry.
5117 BFD_RELOC_390_PLTOFF32
5119 32-bit rel. offset from the GOT to a PLT entry.
5121 BFD_RELOC_390_PLTOFF64
5123 64-bit rel. offset from the GOT to a PLT entry.
5126 BFD_RELOC_390_TLS_LOAD
5128 BFD_RELOC_390_TLS_GDCALL
5130 BFD_RELOC_390_TLS_LDCALL
5132 BFD_RELOC_390_TLS_GD32
5134 BFD_RELOC_390_TLS_GD64
5136 BFD_RELOC_390_TLS_GOTIE12
5138 BFD_RELOC_390_TLS_GOTIE32
5140 BFD_RELOC_390_TLS_GOTIE64
5142 BFD_RELOC_390_TLS_LDM32
5144 BFD_RELOC_390_TLS_LDM64
5146 BFD_RELOC_390_TLS_IE32
5148 BFD_RELOC_390_TLS_IE64
5150 BFD_RELOC_390_TLS_IEENT
5152 BFD_RELOC_390_TLS_LE32
5154 BFD_RELOC_390_TLS_LE64
5156 BFD_RELOC_390_TLS_LDO32
5158 BFD_RELOC_390_TLS_LDO64
5160 BFD_RELOC_390_TLS_DTPMOD
5162 BFD_RELOC_390_TLS_DTPOFF
5164 BFD_RELOC_390_TLS_TPOFF
5166 s390 tls relocations.
5173 BFD_RELOC_390_GOTPLT20
5175 BFD_RELOC_390_TLS_GOTIE20
5177 Long displacement extension.
5180 BFD_RELOC_390_IRELATIVE
5182 STT_GNU_IFUNC relocation.
5185 BFD_RELOC_SCORE_GPREL15
5188 Low 16 bit for load/store
5190 BFD_RELOC_SCORE_DUMMY2
5194 This is a 24-bit reloc with the right 1 bit assumed to be 0
5196 BFD_RELOC_SCORE_BRANCH
5198 This is a 19-bit reloc with the right 1 bit assumed to be 0
5200 BFD_RELOC_SCORE_IMM30
5202 This is a 32-bit reloc for 48-bit instructions.
5204 BFD_RELOC_SCORE_IMM32
5206 This is a 32-bit reloc for 48-bit instructions.
5208 BFD_RELOC_SCORE16_JMP
5210 This is a 11-bit reloc with the right 1 bit assumed to be 0
5212 BFD_RELOC_SCORE16_BRANCH
5214 This is a 8-bit reloc with the right 1 bit assumed to be 0
5216 BFD_RELOC_SCORE_BCMP
5218 This is a 9-bit reloc with the right 1 bit assumed to be 0
5220 BFD_RELOC_SCORE_GOT15
5222 BFD_RELOC_SCORE_GOT_LO16
5224 BFD_RELOC_SCORE_CALL15
5226 BFD_RELOC_SCORE_DUMMY_HI16
5228 Undocumented Score relocs
5233 Scenix IP2K - 9-bit register number / data address
5237 Scenix IP2K - 4-bit register/data bank number
5239 BFD_RELOC_IP2K_ADDR16CJP
5241 Scenix IP2K - low 13 bits of instruction word address
5243 BFD_RELOC_IP2K_PAGE3
5245 Scenix IP2K - high 3 bits of instruction word address
5247 BFD_RELOC_IP2K_LO8DATA
5249 BFD_RELOC_IP2K_HI8DATA
5251 BFD_RELOC_IP2K_EX8DATA
5253 Scenix IP2K - ext/low/high 8 bits of data address
5255 BFD_RELOC_IP2K_LO8INSN
5257 BFD_RELOC_IP2K_HI8INSN
5259 Scenix IP2K - low/high 8 bits of instruction word address
5261 BFD_RELOC_IP2K_PC_SKIP
5263 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5267 Scenix IP2K - 16 bit word address in text section.
5269 BFD_RELOC_IP2K_FR_OFFSET
5271 Scenix IP2K - 7-bit sp or dp offset
5273 BFD_RELOC_VPE4KMATH_DATA
5275 BFD_RELOC_VPE4KMATH_INSN
5277 Scenix VPE4K coprocessor - data/insn-space addressing
5280 BFD_RELOC_VTABLE_INHERIT
5282 BFD_RELOC_VTABLE_ENTRY
5284 These two relocations are used by the linker to determine which of
5285 the entries in a C++ virtual function table are actually used. When
5286 the --gc-sections option is given, the linker will zero out the entries
5287 that are not used, so that the code for those functions need not be
5288 included in the output.
5290 VTABLE_INHERIT is a zero-space relocation used to describe to the
5291 linker the inheritance tree of a C++ virtual function table. The
5292 relocation's symbol should be the parent class' vtable, and the
5293 relocation should be located at the child vtable.
5295 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5296 virtual function table entry. The reloc's symbol should refer to the
5297 table of the class mentioned in the code. Off of that base, an offset
5298 describes the entry that is being used. For Rela hosts, this offset
5299 is stored in the reloc's addend. For Rel hosts, we are forced to put
5300 this offset in the reloc's section offset.
5303 BFD_RELOC_IA64_IMM14
5305 BFD_RELOC_IA64_IMM22
5307 BFD_RELOC_IA64_IMM64
5309 BFD_RELOC_IA64_DIR32MSB
5311 BFD_RELOC_IA64_DIR32LSB
5313 BFD_RELOC_IA64_DIR64MSB
5315 BFD_RELOC_IA64_DIR64LSB
5317 BFD_RELOC_IA64_GPREL22
5319 BFD_RELOC_IA64_GPREL64I
5321 BFD_RELOC_IA64_GPREL32MSB
5323 BFD_RELOC_IA64_GPREL32LSB
5325 BFD_RELOC_IA64_GPREL64MSB
5327 BFD_RELOC_IA64_GPREL64LSB
5329 BFD_RELOC_IA64_LTOFF22
5331 BFD_RELOC_IA64_LTOFF64I
5333 BFD_RELOC_IA64_PLTOFF22
5335 BFD_RELOC_IA64_PLTOFF64I
5337 BFD_RELOC_IA64_PLTOFF64MSB
5339 BFD_RELOC_IA64_PLTOFF64LSB
5341 BFD_RELOC_IA64_FPTR64I
5343 BFD_RELOC_IA64_FPTR32MSB
5345 BFD_RELOC_IA64_FPTR32LSB
5347 BFD_RELOC_IA64_FPTR64MSB
5349 BFD_RELOC_IA64_FPTR64LSB
5351 BFD_RELOC_IA64_PCREL21B
5353 BFD_RELOC_IA64_PCREL21BI
5355 BFD_RELOC_IA64_PCREL21M
5357 BFD_RELOC_IA64_PCREL21F
5359 BFD_RELOC_IA64_PCREL22
5361 BFD_RELOC_IA64_PCREL60B
5363 BFD_RELOC_IA64_PCREL64I
5365 BFD_RELOC_IA64_PCREL32MSB
5367 BFD_RELOC_IA64_PCREL32LSB
5369 BFD_RELOC_IA64_PCREL64MSB
5371 BFD_RELOC_IA64_PCREL64LSB
5373 BFD_RELOC_IA64_LTOFF_FPTR22
5375 BFD_RELOC_IA64_LTOFF_FPTR64I
5377 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5379 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5381 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5383 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5385 BFD_RELOC_IA64_SEGREL32MSB
5387 BFD_RELOC_IA64_SEGREL32LSB
5389 BFD_RELOC_IA64_SEGREL64MSB
5391 BFD_RELOC_IA64_SEGREL64LSB
5393 BFD_RELOC_IA64_SECREL32MSB
5395 BFD_RELOC_IA64_SECREL32LSB
5397 BFD_RELOC_IA64_SECREL64MSB
5399 BFD_RELOC_IA64_SECREL64LSB
5401 BFD_RELOC_IA64_REL32MSB
5403 BFD_RELOC_IA64_REL32LSB
5405 BFD_RELOC_IA64_REL64MSB
5407 BFD_RELOC_IA64_REL64LSB
5409 BFD_RELOC_IA64_LTV32MSB
5411 BFD_RELOC_IA64_LTV32LSB
5413 BFD_RELOC_IA64_LTV64MSB
5415 BFD_RELOC_IA64_LTV64LSB
5417 BFD_RELOC_IA64_IPLTMSB
5419 BFD_RELOC_IA64_IPLTLSB
5423 BFD_RELOC_IA64_LTOFF22X
5425 BFD_RELOC_IA64_LDXMOV
5427 BFD_RELOC_IA64_TPREL14
5429 BFD_RELOC_IA64_TPREL22
5431 BFD_RELOC_IA64_TPREL64I
5433 BFD_RELOC_IA64_TPREL64MSB
5435 BFD_RELOC_IA64_TPREL64LSB
5437 BFD_RELOC_IA64_LTOFF_TPREL22
5439 BFD_RELOC_IA64_DTPMOD64MSB
5441 BFD_RELOC_IA64_DTPMOD64LSB
5443 BFD_RELOC_IA64_LTOFF_DTPMOD22
5445 BFD_RELOC_IA64_DTPREL14
5447 BFD_RELOC_IA64_DTPREL22
5449 BFD_RELOC_IA64_DTPREL64I
5451 BFD_RELOC_IA64_DTPREL32MSB
5453 BFD_RELOC_IA64_DTPREL32LSB
5455 BFD_RELOC_IA64_DTPREL64MSB
5457 BFD_RELOC_IA64_DTPREL64LSB
5459 BFD_RELOC_IA64_LTOFF_DTPREL22
5461 Intel IA64 Relocations.
5464 BFD_RELOC_M68HC11_HI8
5466 Motorola 68HC11 reloc.
5467 This is the 8 bit high part of an absolute address.
5469 BFD_RELOC_M68HC11_LO8
5471 Motorola 68HC11 reloc.
5472 This is the 8 bit low part of an absolute address.
5474 BFD_RELOC_M68HC11_3B
5476 Motorola 68HC11 reloc.
5477 This is the 3 bit of a value.
5479 BFD_RELOC_M68HC11_RL_JUMP
5481 Motorola 68HC11 reloc.
5482 This reloc marks the beginning of a jump/call instruction.
5483 It is used for linker relaxation to correctly identify beginning
5484 of instruction and change some branches to use PC-relative
5487 BFD_RELOC_M68HC11_RL_GROUP
5489 Motorola 68HC11 reloc.
5490 This reloc marks a group of several instructions that gcc generates
5491 and for which the linker relaxation pass can modify and/or remove
5494 BFD_RELOC_M68HC11_LO16
5496 Motorola 68HC11 reloc.
5497 This is the 16-bit lower part of an address. It is used for 'call'
5498 instruction to specify the symbol address without any special
5499 transformation (due to memory bank window).
5501 BFD_RELOC_M68HC11_PAGE
5503 Motorola 68HC11 reloc.
5504 This is a 8-bit reloc that specifies the page number of an address.
5505 It is used by 'call' instruction to specify the page number of
5508 BFD_RELOC_M68HC11_24
5510 Motorola 68HC11 reloc.
5511 This is a 24-bit reloc that represents the address with a 16-bit
5512 value and a 8-bit page number. The symbol address is transformed
5513 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5515 BFD_RELOC_M68HC12_5B
5517 Motorola 68HC12 reloc.
5518 This is the 5 bits of a value.
5520 BFD_RELOC_XGATE_RL_JUMP
5522 Freescale XGATE reloc.
5523 This reloc marks the beginning of a bra/jal instruction.
5525 BFD_RELOC_XGATE_RL_GROUP
5527 Freescale XGATE reloc.
5528 This reloc marks a group of several instructions that gcc generates
5529 and for which the linker relaxation pass can modify and/or remove
5532 BFD_RELOC_XGATE_LO16
5534 Freescale XGATE reloc.
5535 This is the 16-bit lower part of an address. It is used for the '16-bit'
5538 BFD_RELOC_XGATE_GPAGE
5540 Freescale XGATE reloc.
5544 Freescale XGATE reloc.
5546 BFD_RELOC_XGATE_PCREL_9
5548 Freescale XGATE reloc.
5549 This is a 9-bit pc-relative reloc.
5551 BFD_RELOC_XGATE_PCREL_10
5553 Freescale XGATE reloc.
5554 This is a 10-bit pc-relative reloc.
5556 BFD_RELOC_XGATE_IMM8_LO
5558 Freescale XGATE reloc.
5559 This is the 16-bit lower part of an address. It is used for the '16-bit'
5562 BFD_RELOC_XGATE_IMM8_HI
5564 Freescale XGATE reloc.
5565 This is the 16-bit higher part of an address. It is used for the '16-bit'
5568 BFD_RELOC_XGATE_IMM3
5570 Freescale XGATE reloc.
5571 This is a 3-bit pc-relative reloc.
5573 BFD_RELOC_XGATE_IMM4
5575 Freescale XGATE reloc.
5576 This is a 4-bit pc-relative reloc.
5578 BFD_RELOC_XGATE_IMM5
5580 Freescale XGATE reloc.
5581 This is a 5-bit pc-relative reloc.
5583 BFD_RELOC_M68HC12_9B
5585 Motorola 68HC12 reloc.
5586 This is the 9 bits of a value.
5588 BFD_RELOC_M68HC12_16B
5590 Motorola 68HC12 reloc.
5591 This is the 16 bits of a value.
5593 BFD_RELOC_M68HC12_9_PCREL
5595 Motorola 68HC12/XGATE reloc.
5596 This is a PCREL9 branch.
5598 BFD_RELOC_M68HC12_10_PCREL
5600 Motorola 68HC12/XGATE reloc.
5601 This is a PCREL10 branch.
5603 BFD_RELOC_M68HC12_LO8XG
5605 Motorola 68HC12/XGATE reloc.
5606 This is the 8 bit low part of an absolute address and immediately precedes
5607 a matching HI8XG part.
5609 BFD_RELOC_M68HC12_HI8XG
5611 Motorola 68HC12/XGATE reloc.
5612 This is the 8 bit high part of an absolute address and immediately follows
5613 a matching LO8XG part.
5617 BFD_RELOC_16C_NUM08_C
5621 BFD_RELOC_16C_NUM16_C
5625 BFD_RELOC_16C_NUM32_C
5627 BFD_RELOC_16C_DISP04
5629 BFD_RELOC_16C_DISP04_C
5631 BFD_RELOC_16C_DISP08
5633 BFD_RELOC_16C_DISP08_C
5635 BFD_RELOC_16C_DISP16
5637 BFD_RELOC_16C_DISP16_C
5639 BFD_RELOC_16C_DISP24
5641 BFD_RELOC_16C_DISP24_C
5643 BFD_RELOC_16C_DISP24a
5645 BFD_RELOC_16C_DISP24a_C
5649 BFD_RELOC_16C_REG04_C
5651 BFD_RELOC_16C_REG04a
5653 BFD_RELOC_16C_REG04a_C
5657 BFD_RELOC_16C_REG14_C
5661 BFD_RELOC_16C_REG16_C
5665 BFD_RELOC_16C_REG20_C
5669 BFD_RELOC_16C_ABS20_C
5673 BFD_RELOC_16C_ABS24_C
5677 BFD_RELOC_16C_IMM04_C
5681 BFD_RELOC_16C_IMM16_C
5685 BFD_RELOC_16C_IMM20_C
5689 BFD_RELOC_16C_IMM24_C
5693 BFD_RELOC_16C_IMM32_C
5695 NS CR16C Relocations.
5700 BFD_RELOC_CR16_NUM16
5702 BFD_RELOC_CR16_NUM32
5704 BFD_RELOC_CR16_NUM32a
5706 BFD_RELOC_CR16_REGREL0
5708 BFD_RELOC_CR16_REGREL4
5710 BFD_RELOC_CR16_REGREL4a
5712 BFD_RELOC_CR16_REGREL14
5714 BFD_RELOC_CR16_REGREL14a
5716 BFD_RELOC_CR16_REGREL16
5718 BFD_RELOC_CR16_REGREL20
5720 BFD_RELOC_CR16_REGREL20a
5722 BFD_RELOC_CR16_ABS20
5724 BFD_RELOC_CR16_ABS24
5730 BFD_RELOC_CR16_IMM16
5732 BFD_RELOC_CR16_IMM20
5734 BFD_RELOC_CR16_IMM24
5736 BFD_RELOC_CR16_IMM32
5738 BFD_RELOC_CR16_IMM32a
5740 BFD_RELOC_CR16_DISP4
5742 BFD_RELOC_CR16_DISP8
5744 BFD_RELOC_CR16_DISP16
5746 BFD_RELOC_CR16_DISP20
5748 BFD_RELOC_CR16_DISP24
5750 BFD_RELOC_CR16_DISP24a
5752 BFD_RELOC_CR16_SWITCH8
5754 BFD_RELOC_CR16_SWITCH16
5756 BFD_RELOC_CR16_SWITCH32
5758 BFD_RELOC_CR16_GOT_REGREL20
5760 BFD_RELOC_CR16_GOTC_REGREL20
5762 BFD_RELOC_CR16_GLOB_DAT
5764 NS CR16 Relocations.
5771 BFD_RELOC_CRX_REL8_CMP
5779 BFD_RELOC_CRX_REGREL12
5781 BFD_RELOC_CRX_REGREL22
5783 BFD_RELOC_CRX_REGREL28
5785 BFD_RELOC_CRX_REGREL32
5801 BFD_RELOC_CRX_SWITCH8
5803 BFD_RELOC_CRX_SWITCH16
5805 BFD_RELOC_CRX_SWITCH32
5810 BFD_RELOC_CRIS_BDISP8
5812 BFD_RELOC_CRIS_UNSIGNED_5
5814 BFD_RELOC_CRIS_SIGNED_6
5816 BFD_RELOC_CRIS_UNSIGNED_6
5818 BFD_RELOC_CRIS_SIGNED_8
5820 BFD_RELOC_CRIS_UNSIGNED_8
5822 BFD_RELOC_CRIS_SIGNED_16
5824 BFD_RELOC_CRIS_UNSIGNED_16
5826 BFD_RELOC_CRIS_LAPCQ_OFFSET
5828 BFD_RELOC_CRIS_UNSIGNED_4
5830 These relocs are only used within the CRIS assembler. They are not
5831 (at present) written to any object files.
5835 BFD_RELOC_CRIS_GLOB_DAT
5837 BFD_RELOC_CRIS_JUMP_SLOT
5839 BFD_RELOC_CRIS_RELATIVE
5841 Relocs used in ELF shared libraries for CRIS.
5843 BFD_RELOC_CRIS_32_GOT
5845 32-bit offset to symbol-entry within GOT.
5847 BFD_RELOC_CRIS_16_GOT
5849 16-bit offset to symbol-entry within GOT.
5851 BFD_RELOC_CRIS_32_GOTPLT
5853 32-bit offset to symbol-entry within GOT, with PLT handling.
5855 BFD_RELOC_CRIS_16_GOTPLT
5857 16-bit offset to symbol-entry within GOT, with PLT handling.
5859 BFD_RELOC_CRIS_32_GOTREL
5861 32-bit offset to symbol, relative to GOT.
5863 BFD_RELOC_CRIS_32_PLT_GOTREL
5865 32-bit offset to symbol with PLT entry, relative to GOT.
5867 BFD_RELOC_CRIS_32_PLT_PCREL
5869 32-bit offset to symbol with PLT entry, relative to this relocation.
5872 BFD_RELOC_CRIS_32_GOT_GD
5874 BFD_RELOC_CRIS_16_GOT_GD
5876 BFD_RELOC_CRIS_32_GD
5880 BFD_RELOC_CRIS_32_DTPREL
5882 BFD_RELOC_CRIS_16_DTPREL
5884 BFD_RELOC_CRIS_32_GOT_TPREL
5886 BFD_RELOC_CRIS_16_GOT_TPREL
5888 BFD_RELOC_CRIS_32_TPREL
5890 BFD_RELOC_CRIS_16_TPREL
5892 BFD_RELOC_CRIS_DTPMOD
5894 BFD_RELOC_CRIS_32_IE
5896 Relocs used in TLS code for CRIS.
5901 BFD_RELOC_860_GLOB_DAT
5903 BFD_RELOC_860_JUMP_SLOT
5905 BFD_RELOC_860_RELATIVE
5915 BFD_RELOC_860_SPLIT0
5919 BFD_RELOC_860_SPLIT1
5923 BFD_RELOC_860_SPLIT2
5927 BFD_RELOC_860_LOGOT0
5929 BFD_RELOC_860_SPGOT0
5931 BFD_RELOC_860_LOGOT1
5933 BFD_RELOC_860_SPGOT1
5935 BFD_RELOC_860_LOGOTOFF0
5937 BFD_RELOC_860_SPGOTOFF0
5939 BFD_RELOC_860_LOGOTOFF1
5941 BFD_RELOC_860_SPGOTOFF1
5943 BFD_RELOC_860_LOGOTOFF2
5945 BFD_RELOC_860_LOGOTOFF3
5949 BFD_RELOC_860_HIGHADJ
5953 BFD_RELOC_860_HAGOTOFF
5961 BFD_RELOC_860_HIGOTOFF
5963 Intel i860 Relocations.
5966 BFD_RELOC_OR1K_REL_26
5968 BFD_RELOC_OR1K_GOTPC_HI16
5970 BFD_RELOC_OR1K_GOTPC_LO16
5972 BFD_RELOC_OR1K_GOT16
5974 BFD_RELOC_OR1K_PLT26
5976 BFD_RELOC_OR1K_GOTOFF_HI16
5978 BFD_RELOC_OR1K_GOTOFF_LO16
5982 BFD_RELOC_OR1K_GLOB_DAT
5984 BFD_RELOC_OR1K_JMP_SLOT
5986 BFD_RELOC_OR1K_RELATIVE
5988 BFD_RELOC_OR1K_TLS_GD_HI16
5990 BFD_RELOC_OR1K_TLS_GD_LO16
5992 BFD_RELOC_OR1K_TLS_LDM_HI16
5994 BFD_RELOC_OR1K_TLS_LDM_LO16
5996 BFD_RELOC_OR1K_TLS_LDO_HI16
5998 BFD_RELOC_OR1K_TLS_LDO_LO16
6000 BFD_RELOC_OR1K_TLS_IE_HI16
6002 BFD_RELOC_OR1K_TLS_IE_LO16
6004 BFD_RELOC_OR1K_TLS_LE_HI16
6006 BFD_RELOC_OR1K_TLS_LE_LO16
6008 BFD_RELOC_OR1K_TLS_TPOFF
6010 BFD_RELOC_OR1K_TLS_DTPOFF
6012 BFD_RELOC_OR1K_TLS_DTPMOD
6014 OpenRISC 1000 Relocations.
6017 BFD_RELOC_H8_DIR16A8
6019 BFD_RELOC_H8_DIR16R8
6021 BFD_RELOC_H8_DIR24A8
6023 BFD_RELOC_H8_DIR24R8
6025 BFD_RELOC_H8_DIR32A16
6027 BFD_RELOC_H8_DISP32A16
6032 BFD_RELOC_XSTORMY16_REL_12
6034 BFD_RELOC_XSTORMY16_12
6036 BFD_RELOC_XSTORMY16_24
6038 BFD_RELOC_XSTORMY16_FPTR16
6040 Sony Xstormy16 Relocations.
6045 Self-describing complex relocations.
6057 Infineon Relocations.
6060 BFD_RELOC_VAX_GLOB_DAT
6062 BFD_RELOC_VAX_JMP_SLOT
6064 BFD_RELOC_VAX_RELATIVE
6066 Relocations used by VAX ELF.
6071 Morpho MT - 16 bit immediate relocation.
6075 Morpho MT - Hi 16 bits of an address.
6079 Morpho MT - Low 16 bits of an address.
6081 BFD_RELOC_MT_GNU_VTINHERIT
6083 Morpho MT - Used to tell the linker which vtable entries are used.
6085 BFD_RELOC_MT_GNU_VTENTRY
6087 Morpho MT - Used to tell the linker which vtable entries are used.
6089 BFD_RELOC_MT_PCINSN8
6091 Morpho MT - 8 bit immediate relocation.
6094 BFD_RELOC_MSP430_10_PCREL
6096 BFD_RELOC_MSP430_16_PCREL
6100 BFD_RELOC_MSP430_16_PCREL_BYTE
6102 BFD_RELOC_MSP430_16_BYTE
6104 BFD_RELOC_MSP430_2X_PCREL
6106 BFD_RELOC_MSP430_RL_PCREL
6108 BFD_RELOC_MSP430_ABS8
6110 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6112 BFD_RELOC_MSP430X_PCR20_EXT_DST
6114 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6116 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6118 BFD_RELOC_MSP430X_ABS20_EXT_DST
6120 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6122 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6124 BFD_RELOC_MSP430X_ABS20_ADR_DST
6126 BFD_RELOC_MSP430X_PCR16
6128 BFD_RELOC_MSP430X_PCR20_CALL
6130 BFD_RELOC_MSP430X_ABS16
6132 BFD_RELOC_MSP430_ABS_HI16
6134 BFD_RELOC_MSP430_PREL31
6136 BFD_RELOC_MSP430_SYM_DIFF
6138 msp430 specific relocation codes
6145 BFD_RELOC_NIOS2_CALL26
6147 BFD_RELOC_NIOS2_IMM5
6149 BFD_RELOC_NIOS2_CACHE_OPX
6151 BFD_RELOC_NIOS2_IMM6
6153 BFD_RELOC_NIOS2_IMM8
6155 BFD_RELOC_NIOS2_HI16
6157 BFD_RELOC_NIOS2_LO16
6159 BFD_RELOC_NIOS2_HIADJ16
6161 BFD_RELOC_NIOS2_GPREL
6163 BFD_RELOC_NIOS2_UJMP
6165 BFD_RELOC_NIOS2_CJMP
6167 BFD_RELOC_NIOS2_CALLR
6169 BFD_RELOC_NIOS2_ALIGN
6171 BFD_RELOC_NIOS2_GOT16
6173 BFD_RELOC_NIOS2_CALL16
6175 BFD_RELOC_NIOS2_GOTOFF_LO
6177 BFD_RELOC_NIOS2_GOTOFF_HA
6179 BFD_RELOC_NIOS2_PCREL_LO
6181 BFD_RELOC_NIOS2_PCREL_HA
6183 BFD_RELOC_NIOS2_TLS_GD16
6185 BFD_RELOC_NIOS2_TLS_LDM16
6187 BFD_RELOC_NIOS2_TLS_LDO16
6189 BFD_RELOC_NIOS2_TLS_IE16
6191 BFD_RELOC_NIOS2_TLS_LE16
6193 BFD_RELOC_NIOS2_TLS_DTPMOD
6195 BFD_RELOC_NIOS2_TLS_DTPREL
6197 BFD_RELOC_NIOS2_TLS_TPREL
6199 BFD_RELOC_NIOS2_COPY
6201 BFD_RELOC_NIOS2_GLOB_DAT
6203 BFD_RELOC_NIOS2_JUMP_SLOT
6205 BFD_RELOC_NIOS2_RELATIVE
6207 BFD_RELOC_NIOS2_GOTOFF
6209 BFD_RELOC_NIOS2_CALL26_NOAT
6211 BFD_RELOC_NIOS2_GOT_LO
6213 BFD_RELOC_NIOS2_GOT_HA
6215 BFD_RELOC_NIOS2_CALL_LO
6217 BFD_RELOC_NIOS2_CALL_HA
6219 Relocations used by the Altera Nios II core.
6222 BFD_RELOC_IQ2000_OFFSET_16
6224 BFD_RELOC_IQ2000_OFFSET_21
6226 BFD_RELOC_IQ2000_UHI16
6231 BFD_RELOC_XTENSA_RTLD
6233 Special Xtensa relocation used only by PLT entries in ELF shared
6234 objects to indicate that the runtime linker should set the value
6235 to one of its own internal functions or data structures.
6237 BFD_RELOC_XTENSA_GLOB_DAT
6239 BFD_RELOC_XTENSA_JMP_SLOT
6241 BFD_RELOC_XTENSA_RELATIVE
6243 Xtensa relocations for ELF shared objects.
6245 BFD_RELOC_XTENSA_PLT
6247 Xtensa relocation used in ELF object files for symbols that may require
6248 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6250 BFD_RELOC_XTENSA_DIFF8
6252 BFD_RELOC_XTENSA_DIFF16
6254 BFD_RELOC_XTENSA_DIFF32
6256 Xtensa relocations to mark the difference of two local symbols.
6257 These are only needed to support linker relaxation and can be ignored
6258 when not relaxing. The field is set to the value of the difference
6259 assuming no relaxation. The relocation encodes the position of the
6260 first symbol so the linker can determine whether to adjust the field
6263 BFD_RELOC_XTENSA_SLOT0_OP
6265 BFD_RELOC_XTENSA_SLOT1_OP
6267 BFD_RELOC_XTENSA_SLOT2_OP
6269 BFD_RELOC_XTENSA_SLOT3_OP
6271 BFD_RELOC_XTENSA_SLOT4_OP
6273 BFD_RELOC_XTENSA_SLOT5_OP
6275 BFD_RELOC_XTENSA_SLOT6_OP
6277 BFD_RELOC_XTENSA_SLOT7_OP
6279 BFD_RELOC_XTENSA_SLOT8_OP
6281 BFD_RELOC_XTENSA_SLOT9_OP
6283 BFD_RELOC_XTENSA_SLOT10_OP
6285 BFD_RELOC_XTENSA_SLOT11_OP
6287 BFD_RELOC_XTENSA_SLOT12_OP
6289 BFD_RELOC_XTENSA_SLOT13_OP
6291 BFD_RELOC_XTENSA_SLOT14_OP
6293 Generic Xtensa relocations for instruction operands. Only the slot
6294 number is encoded in the relocation. The relocation applies to the
6295 last PC-relative immediate operand, or if there are no PC-relative
6296 immediates, to the last immediate operand.
6298 BFD_RELOC_XTENSA_SLOT0_ALT
6300 BFD_RELOC_XTENSA_SLOT1_ALT
6302 BFD_RELOC_XTENSA_SLOT2_ALT
6304 BFD_RELOC_XTENSA_SLOT3_ALT
6306 BFD_RELOC_XTENSA_SLOT4_ALT
6308 BFD_RELOC_XTENSA_SLOT5_ALT
6310 BFD_RELOC_XTENSA_SLOT6_ALT
6312 BFD_RELOC_XTENSA_SLOT7_ALT
6314 BFD_RELOC_XTENSA_SLOT8_ALT
6316 BFD_RELOC_XTENSA_SLOT9_ALT
6318 BFD_RELOC_XTENSA_SLOT10_ALT
6320 BFD_RELOC_XTENSA_SLOT11_ALT
6322 BFD_RELOC_XTENSA_SLOT12_ALT
6324 BFD_RELOC_XTENSA_SLOT13_ALT
6326 BFD_RELOC_XTENSA_SLOT14_ALT
6328 Alternate Xtensa relocations. Only the slot is encoded in the
6329 relocation. The meaning of these relocations is opcode-specific.
6331 BFD_RELOC_XTENSA_OP0
6333 BFD_RELOC_XTENSA_OP1
6335 BFD_RELOC_XTENSA_OP2
6337 Xtensa relocations for backward compatibility. These have all been
6338 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6340 BFD_RELOC_XTENSA_ASM_EXPAND
6342 Xtensa relocation to mark that the assembler expanded the
6343 instructions from an original target. The expansion size is
6344 encoded in the reloc size.
6346 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6348 Xtensa relocation to mark that the linker should simplify
6349 assembler-expanded instructions. This is commonly used
6350 internally by the linker after analysis of a
6351 BFD_RELOC_XTENSA_ASM_EXPAND.
6353 BFD_RELOC_XTENSA_TLSDESC_FN
6355 BFD_RELOC_XTENSA_TLSDESC_ARG
6357 BFD_RELOC_XTENSA_TLS_DTPOFF
6359 BFD_RELOC_XTENSA_TLS_TPOFF
6361 BFD_RELOC_XTENSA_TLS_FUNC
6363 BFD_RELOC_XTENSA_TLS_ARG
6365 BFD_RELOC_XTENSA_TLS_CALL
6367 Xtensa TLS relocations.
6372 8 bit signed offset in (ix+d) or (iy+d).
6390 BFD_RELOC_LM32_BRANCH
6392 BFD_RELOC_LM32_16_GOT
6394 BFD_RELOC_LM32_GOTOFF_HI16
6396 BFD_RELOC_LM32_GOTOFF_LO16
6400 BFD_RELOC_LM32_GLOB_DAT
6402 BFD_RELOC_LM32_JMP_SLOT
6404 BFD_RELOC_LM32_RELATIVE
6406 Lattice Mico32 relocations.
6409 BFD_RELOC_MACH_O_SECTDIFF
6411 Difference between two section addreses. Must be followed by a
6412 BFD_RELOC_MACH_O_PAIR.
6414 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6416 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6418 BFD_RELOC_MACH_O_PAIR
6420 Pair of relocation. Contains the first symbol.
6423 BFD_RELOC_MACH_O_X86_64_BRANCH32
6425 BFD_RELOC_MACH_O_X86_64_BRANCH8
6427 PCREL relocations. They are marked as branch to create PLT entry if
6430 BFD_RELOC_MACH_O_X86_64_GOT
6432 Used when referencing a GOT entry.
6434 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6436 Used when loading a GOT entry with movq. It is specially marked so that
6437 the linker could optimize the movq to a leaq if possible.
6439 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
6441 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6443 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
6445 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6447 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6449 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6451 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6453 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6455 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6457 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6460 BFD_RELOC_MICROBLAZE_32_LO
6462 This is a 32 bit reloc for the microblaze that stores the
6463 low 16 bits of a value
6465 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6467 This is a 32 bit pc-relative reloc for the microblaze that
6468 stores the low 16 bits of a value
6470 BFD_RELOC_MICROBLAZE_32_ROSDA
6472 This is a 32 bit reloc for the microblaze that stores a
6473 value relative to the read-only small data area anchor
6475 BFD_RELOC_MICROBLAZE_32_RWSDA
6477 This is a 32 bit reloc for the microblaze that stores a
6478 value relative to the read-write small data area anchor
6480 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6482 This is a 32 bit reloc for the microblaze to handle
6483 expressions of the form "Symbol Op Symbol"
6485 BFD_RELOC_MICROBLAZE_64_NONE
6487 This is a 64 bit reloc that stores the 32 bit pc relative
6488 value in two words (with an imm instruction). No relocation is
6489 done here - only used for relaxing
6491 BFD_RELOC_MICROBLAZE_64_GOTPC
6493 This is a 64 bit reloc that stores the 32 bit pc relative
6494 value in two words (with an imm instruction). The relocation is
6495 PC-relative GOT offset
6497 BFD_RELOC_MICROBLAZE_64_GOT
6499 This is a 64 bit reloc that stores the 32 bit pc relative
6500 value in two words (with an imm instruction). The relocation is
6503 BFD_RELOC_MICROBLAZE_64_PLT
6505 This is a 64 bit reloc that stores the 32 bit pc relative
6506 value in two words (with an imm instruction). The relocation is
6507 PC-relative offset into PLT
6509 BFD_RELOC_MICROBLAZE_64_GOTOFF
6511 This is a 64 bit reloc that stores the 32 bit GOT relative
6512 value in two words (with an imm instruction). The relocation is
6513 relative offset from _GLOBAL_OFFSET_TABLE_
6515 BFD_RELOC_MICROBLAZE_32_GOTOFF
6517 This is a 32 bit reloc that stores the 32 bit GOT relative
6518 value in a word. The relocation is relative offset from
6519 _GLOBAL_OFFSET_TABLE_
6521 BFD_RELOC_MICROBLAZE_COPY
6523 This is used to tell the dynamic linker to copy the value out of
6524 the dynamic object into the runtime process image.
6526 BFD_RELOC_MICROBLAZE_64_TLS
6530 BFD_RELOC_MICROBLAZE_64_TLSGD
6532 This is a 64 bit reloc that stores the 32 bit GOT relative value
6533 of the GOT TLS GD info entry in two words (with an imm instruction). The
6534 relocation is GOT offset.
6536 BFD_RELOC_MICROBLAZE_64_TLSLD
6538 This is a 64 bit reloc that stores the 32 bit GOT relative value
6539 of the GOT TLS LD info entry in two words (with an imm instruction). The
6540 relocation is GOT offset.
6542 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6544 This is a 32 bit reloc that stores the Module ID to GOT(n).
6546 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6548 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6550 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6552 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6555 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6557 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6558 to two words (uses imm instruction).
6560 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6562 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6563 to two words (uses imm instruction).
6566 BFD_RELOC_AARCH64_RELOC_START
6568 AArch64 pseudo relocation code to mark the start of the AArch64
6569 relocation enumerators. N.B. the order of the enumerators is
6570 important as several tables in the AArch64 bfd backend are indexed
6571 by these enumerators; make sure they are all synced.
6573 BFD_RELOC_AARCH64_NONE
6575 AArch64 null relocation code.
6577 BFD_RELOC_AARCH64_64
6579 BFD_RELOC_AARCH64_32
6581 BFD_RELOC_AARCH64_16
6583 Basic absolute relocations of N bits. These are equivalent to
6584 BFD_RELOC_N and they were added to assist the indexing of the howto
6587 BFD_RELOC_AARCH64_64_PCREL
6589 BFD_RELOC_AARCH64_32_PCREL
6591 BFD_RELOC_AARCH64_16_PCREL
6593 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6594 and they were added to assist the indexing of the howto table.
6596 BFD_RELOC_AARCH64_MOVW_G0
6598 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6599 of an unsigned address/value.
6601 BFD_RELOC_AARCH64_MOVW_G0_NC
6603 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6604 an address/value. No overflow checking.
6606 BFD_RELOC_AARCH64_MOVW_G1
6608 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6609 of an unsigned address/value.
6611 BFD_RELOC_AARCH64_MOVW_G1_NC
6613 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6614 of an address/value. No overflow checking.
6616 BFD_RELOC_AARCH64_MOVW_G2
6618 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6619 of an unsigned address/value.
6621 BFD_RELOC_AARCH64_MOVW_G2_NC
6623 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6624 of an address/value. No overflow checking.
6626 BFD_RELOC_AARCH64_MOVW_G3
6628 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6629 of a signed or unsigned address/value.
6631 BFD_RELOC_AARCH64_MOVW_G0_S
6633 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6634 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6637 BFD_RELOC_AARCH64_MOVW_G1_S
6639 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6640 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6643 BFD_RELOC_AARCH64_MOVW_G2_S
6645 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6646 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6649 BFD_RELOC_AARCH64_LD_LO19_PCREL
6651 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6652 offset. The lowest two bits must be zero and are not stored in the
6653 instruction, giving a 21 bit signed byte offset.
6655 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6657 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6659 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6661 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6662 offset, giving a 4KB aligned page base address.
6664 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6666 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6667 offset, giving a 4KB aligned page base address, but with no overflow
6670 BFD_RELOC_AARCH64_ADD_LO12
6672 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6673 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6675 BFD_RELOC_AARCH64_LDST8_LO12
6677 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6678 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6680 BFD_RELOC_AARCH64_TSTBR14
6682 AArch64 14 bit pc-relative test bit and branch.
6683 The lowest two bits must be zero and are not stored in the instruction,
6684 giving a 16 bit signed byte offset.
6686 BFD_RELOC_AARCH64_BRANCH19
6688 AArch64 19 bit pc-relative conditional branch and compare & branch.
6689 The lowest two bits must be zero and are not stored in the instruction,
6690 giving a 21 bit signed byte offset.
6692 BFD_RELOC_AARCH64_JUMP26
6694 AArch64 26 bit pc-relative unconditional branch.
6695 The lowest two bits must be zero and are not stored in the instruction,
6696 giving a 28 bit signed byte offset.
6698 BFD_RELOC_AARCH64_CALL26
6700 AArch64 26 bit pc-relative unconditional branch and link.
6701 The lowest two bits must be zero and are not stored in the instruction,
6702 giving a 28 bit signed byte offset.
6704 BFD_RELOC_AARCH64_LDST16_LO12
6706 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6707 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6709 BFD_RELOC_AARCH64_LDST32_LO12
6711 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6712 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6714 BFD_RELOC_AARCH64_LDST64_LO12
6716 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6717 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6719 BFD_RELOC_AARCH64_LDST128_LO12
6721 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6722 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6724 BFD_RELOC_AARCH64_GOT_LD_PREL19
6726 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6727 offset of the global offset table entry for a symbol. The lowest two
6728 bits must be zero and are not stored in the instruction, giving a 21
6729 bit signed byte offset. This relocation type requires signed overflow
6732 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6734 Get to the page base of the global offset table entry for a symbol as
6735 part of an ADRP instruction using a 21 bit PC relative value.Used in
6736 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6738 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6740 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6741 the GOT entry for this symbol. Used in conjunction with
6742 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6744 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6746 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6747 the GOT entry for this symbol. Used in conjunction with
6748 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6750 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6752 Get to the page base of the global offset table entry for a symbols
6753 tls_index structure as part of an adrp instruction using a 21 bit PC
6754 relative value. Used in conjunction with
6755 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6757 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6759 Unsigned 12 bit byte offset to global offset table entry for a symbols
6760 tls_index structure. Used in conjunction with
6761 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6763 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6765 AArch64 TLS INITIAL EXEC relocation.
6767 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6769 AArch64 TLS INITIAL EXEC relocation.
6771 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6773 AArch64 TLS INITIAL EXEC relocation.
6775 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6777 AArch64 TLS INITIAL EXEC relocation.
6779 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6781 AArch64 TLS INITIAL EXEC relocation.
6783 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6785 AArch64 TLS INITIAL EXEC relocation.
6787 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6789 AArch64 TLS LOCAL EXEC relocation.
6791 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6793 AArch64 TLS LOCAL EXEC relocation.
6795 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6797 AArch64 TLS LOCAL EXEC relocation.
6799 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6801 AArch64 TLS LOCAL EXEC relocation.
6803 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6805 AArch64 TLS LOCAL EXEC relocation.
6807 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6809 AArch64 TLS LOCAL EXEC relocation.
6811 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6813 AArch64 TLS LOCAL EXEC relocation.
6815 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6817 AArch64 TLS LOCAL EXEC relocation.
6819 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
6821 AArch64 TLS DESC relocation.
6823 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6825 AArch64 TLS DESC relocation.
6827 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
6829 AArch64 TLS DESC relocation.
6831 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6833 AArch64 TLS DESC relocation.
6835 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6837 AArch64 TLS DESC relocation.
6839 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6841 AArch64 TLS DESC relocation.
6843 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6845 AArch64 TLS DESC relocation.
6847 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6849 AArch64 TLS DESC relocation.
6851 BFD_RELOC_AARCH64_TLSDESC_LDR
6853 AArch64 TLS DESC relocation.
6855 BFD_RELOC_AARCH64_TLSDESC_ADD
6857 AArch64 TLS DESC relocation.
6859 BFD_RELOC_AARCH64_TLSDESC_CALL
6861 AArch64 TLS DESC relocation.
6863 BFD_RELOC_AARCH64_COPY
6865 AArch64 TLS relocation.
6867 BFD_RELOC_AARCH64_GLOB_DAT
6869 AArch64 TLS relocation.
6871 BFD_RELOC_AARCH64_JUMP_SLOT
6873 AArch64 TLS relocation.
6875 BFD_RELOC_AARCH64_RELATIVE
6877 AArch64 TLS relocation.
6879 BFD_RELOC_AARCH64_TLS_DTPMOD
6881 AArch64 TLS relocation.
6883 BFD_RELOC_AARCH64_TLS_DTPREL
6885 AArch64 TLS relocation.
6887 BFD_RELOC_AARCH64_TLS_TPREL
6889 AArch64 TLS relocation.
6891 BFD_RELOC_AARCH64_TLSDESC
6893 AArch64 TLS relocation.
6895 BFD_RELOC_AARCH64_IRELATIVE
6897 AArch64 support for STT_GNU_IFUNC.
6899 BFD_RELOC_AARCH64_RELOC_END
6901 AArch64 pseudo relocation code to mark the end of the AArch64
6902 relocation enumerators that have direct mapping to ELF reloc codes.
6903 There are a few more enumerators after this one; those are mainly
6904 used by the AArch64 assembler for the internal fixup or to select
6905 one of the above enumerators.
6907 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6909 AArch64 pseudo relocation code to be used internally by the AArch64
6910 assembler and not (currently) written to any object files.
6912 BFD_RELOC_AARCH64_LDST_LO12
6914 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6915 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6917 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
6919 AArch64 pseudo relocation code to be used internally by the AArch64
6920 assembler and not (currently) written to any object files.
6922 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
6924 AArch64 pseudo relocation code to be used internally by the AArch64
6925 assembler and not (currently) written to any object files.
6927 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
6929 AArch64 pseudo relocation code to be used internally by the AArch64
6930 assembler and not (currently) written to any object files.
6933 BFD_RELOC_TILEPRO_COPY
6935 BFD_RELOC_TILEPRO_GLOB_DAT
6937 BFD_RELOC_TILEPRO_JMP_SLOT
6939 BFD_RELOC_TILEPRO_RELATIVE
6941 BFD_RELOC_TILEPRO_BROFF_X1
6943 BFD_RELOC_TILEPRO_JOFFLONG_X1
6945 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6947 BFD_RELOC_TILEPRO_IMM8_X0
6949 BFD_RELOC_TILEPRO_IMM8_Y0
6951 BFD_RELOC_TILEPRO_IMM8_X1
6953 BFD_RELOC_TILEPRO_IMM8_Y1
6955 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6957 BFD_RELOC_TILEPRO_MT_IMM15_X1
6959 BFD_RELOC_TILEPRO_MF_IMM15_X1
6961 BFD_RELOC_TILEPRO_IMM16_X0
6963 BFD_RELOC_TILEPRO_IMM16_X1
6965 BFD_RELOC_TILEPRO_IMM16_X0_LO
6967 BFD_RELOC_TILEPRO_IMM16_X1_LO
6969 BFD_RELOC_TILEPRO_IMM16_X0_HI
6971 BFD_RELOC_TILEPRO_IMM16_X1_HI
6973 BFD_RELOC_TILEPRO_IMM16_X0_HA
6975 BFD_RELOC_TILEPRO_IMM16_X1_HA
6977 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6979 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6981 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6983 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6985 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6987 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6989 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6991 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6993 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6995 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6997 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6999 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7001 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7003 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7005 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7007 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7009 BFD_RELOC_TILEPRO_MMSTART_X0
7011 BFD_RELOC_TILEPRO_MMEND_X0
7013 BFD_RELOC_TILEPRO_MMSTART_X1
7015 BFD_RELOC_TILEPRO_MMEND_X1
7017 BFD_RELOC_TILEPRO_SHAMT_X0
7019 BFD_RELOC_TILEPRO_SHAMT_X1
7021 BFD_RELOC_TILEPRO_SHAMT_Y0
7023 BFD_RELOC_TILEPRO_SHAMT_Y1
7025 BFD_RELOC_TILEPRO_TLS_GD_CALL
7027 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7029 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7031 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7033 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7035 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7037 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7039 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7041 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7043 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7045 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7047 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7049 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7051 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7053 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7055 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7057 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7059 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7061 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7063 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7065 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7067 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7069 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7071 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7073 BFD_RELOC_TILEPRO_TLS_TPOFF32
7075 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7077 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7079 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7081 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7083 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7085 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7087 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7089 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7091 Tilera TILEPro Relocations.
7093 BFD_RELOC_TILEGX_HW0
7095 BFD_RELOC_TILEGX_HW1
7097 BFD_RELOC_TILEGX_HW2
7099 BFD_RELOC_TILEGX_HW3
7101 BFD_RELOC_TILEGX_HW0_LAST
7103 BFD_RELOC_TILEGX_HW1_LAST
7105 BFD_RELOC_TILEGX_HW2_LAST
7107 BFD_RELOC_TILEGX_COPY
7109 BFD_RELOC_TILEGX_GLOB_DAT
7111 BFD_RELOC_TILEGX_JMP_SLOT
7113 BFD_RELOC_TILEGX_RELATIVE
7115 BFD_RELOC_TILEGX_BROFF_X1
7117 BFD_RELOC_TILEGX_JUMPOFF_X1
7119 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7121 BFD_RELOC_TILEGX_IMM8_X0
7123 BFD_RELOC_TILEGX_IMM8_Y0
7125 BFD_RELOC_TILEGX_IMM8_X1
7127 BFD_RELOC_TILEGX_IMM8_Y1
7129 BFD_RELOC_TILEGX_DEST_IMM8_X1
7131 BFD_RELOC_TILEGX_MT_IMM14_X1
7133 BFD_RELOC_TILEGX_MF_IMM14_X1
7135 BFD_RELOC_TILEGX_MMSTART_X0
7137 BFD_RELOC_TILEGX_MMEND_X0
7139 BFD_RELOC_TILEGX_SHAMT_X0
7141 BFD_RELOC_TILEGX_SHAMT_X1
7143 BFD_RELOC_TILEGX_SHAMT_Y0
7145 BFD_RELOC_TILEGX_SHAMT_Y1
7147 BFD_RELOC_TILEGX_IMM16_X0_HW0
7149 BFD_RELOC_TILEGX_IMM16_X1_HW0
7151 BFD_RELOC_TILEGX_IMM16_X0_HW1
7153 BFD_RELOC_TILEGX_IMM16_X1_HW1
7155 BFD_RELOC_TILEGX_IMM16_X0_HW2
7157 BFD_RELOC_TILEGX_IMM16_X1_HW2
7159 BFD_RELOC_TILEGX_IMM16_X0_HW3
7161 BFD_RELOC_TILEGX_IMM16_X1_HW3
7163 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7165 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7167 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7169 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7171 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7173 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7175 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7177 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7179 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7181 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7183 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7185 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7187 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7189 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7191 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7193 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7195 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7197 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7199 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7201 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7203 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7205 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7207 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7209 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7211 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7213 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7215 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7217 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7219 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7221 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7223 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7225 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7227 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7229 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7231 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7233 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7235 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7237 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7239 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7241 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7243 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7245 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7247 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7249 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7251 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7253 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7255 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7257 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7259 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7261 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7263 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7265 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7267 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7269 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7271 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7273 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7275 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7277 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7279 BFD_RELOC_TILEGX_TLS_DTPMOD64
7281 BFD_RELOC_TILEGX_TLS_DTPOFF64
7283 BFD_RELOC_TILEGX_TLS_TPOFF64
7285 BFD_RELOC_TILEGX_TLS_DTPMOD32
7287 BFD_RELOC_TILEGX_TLS_DTPOFF32
7289 BFD_RELOC_TILEGX_TLS_TPOFF32
7291 BFD_RELOC_TILEGX_TLS_GD_CALL
7293 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7295 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7297 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7299 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7301 BFD_RELOC_TILEGX_TLS_IE_LOAD
7303 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7305 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7307 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7309 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7311 Tilera TILE-Gx Relocations.
7314 BFD_RELOC_EPIPHANY_SIMM8
7316 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7318 BFD_RELOC_EPIPHANY_SIMM24
7320 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7322 BFD_RELOC_EPIPHANY_HIGH
7324 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7326 BFD_RELOC_EPIPHANY_LOW
7328 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7330 BFD_RELOC_EPIPHANY_SIMM11
7332 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7334 BFD_RELOC_EPIPHANY_IMM11
7336 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7338 BFD_RELOC_EPIPHANY_IMM8
7340 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7343 BFD_RELOC_VISIUM_HI16
7345 BFD_RELOC_VISIUM_LO16
7347 BFD_RELOC_VISIUM_IM16
7349 BFD_RELOC_VISIUM_REL16
7351 BFD_RELOC_VISIUM_HI16_PCREL
7353 BFD_RELOC_VISIUM_LO16_PCREL
7355 BFD_RELOC_VISIUM_IM16_PCREL
7363 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7368 bfd_reloc_type_lookup
7369 bfd_reloc_name_lookup
7372 reloc_howto_type *bfd_reloc_type_lookup
7373 (bfd *abfd, bfd_reloc_code_real_type code);
7374 reloc_howto_type *bfd_reloc_name_lookup
7375 (bfd *abfd, const char *reloc_name);
7378 Return a pointer to a howto structure which, when
7379 invoked, will perform the relocation @var{code} on data from the
7385 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7387 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7391 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7393 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7396 static reloc_howto_type bfd_howto_32
=
7397 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7401 bfd_default_reloc_type_lookup
7404 reloc_howto_type *bfd_default_reloc_type_lookup
7405 (bfd *abfd, bfd_reloc_code_real_type code);
7408 Provides a default relocation lookup routine for any architecture.
7413 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7417 case BFD_RELOC_CTOR
:
7418 /* The type of reloc used in a ctor, which will be as wide as the
7419 address - so either a 64, 32, or 16 bitter. */
7420 switch (bfd_arch_bits_per_address (abfd
))
7425 return &bfd_howto_32
;
7439 bfd_get_reloc_code_name
7442 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7445 Provides a printable name for the supplied relocation code.
7446 Useful mainly for printing error messages.
7450 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7452 if (code
> BFD_RELOC_UNUSED
)
7454 return bfd_reloc_code_real_names
[code
];
7459 bfd_generic_relax_section
7462 bfd_boolean bfd_generic_relax_section
7465 struct bfd_link_info *,
7469 Provides default handling for relaxing for back ends which
7474 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
7475 asection
*section ATTRIBUTE_UNUSED
,
7476 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
7479 if (link_info
->relocatable
)
7480 (*link_info
->callbacks
->einfo
)
7481 (_("%P%F: --relax and -r may not be used together\n"));
7489 bfd_generic_gc_sections
7492 bfd_boolean bfd_generic_gc_sections
7493 (bfd *, struct bfd_link_info *);
7496 Provides default handling for relaxing for back ends which
7497 don't do section gc -- i.e., does nothing.
7501 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7502 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
7509 bfd_generic_lookup_section_flags
7512 bfd_boolean bfd_generic_lookup_section_flags
7513 (struct bfd_link_info *, struct flag_info *, asection *);
7516 Provides default handling for section flags lookup
7517 -- i.e., does nothing.
7518 Returns FALSE if the section should be omitted, otherwise TRUE.
7522 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
7523 struct flag_info
*flaginfo
,
7524 asection
*section ATTRIBUTE_UNUSED
)
7526 if (flaginfo
!= NULL
)
7528 (*_bfd_error_handler
) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7536 bfd_generic_merge_sections
7539 bfd_boolean bfd_generic_merge_sections
7540 (bfd *, struct bfd_link_info *);
7543 Provides default handling for SEC_MERGE section merging for back ends
7544 which don't have SEC_MERGE support -- i.e., does nothing.
7548 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7549 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
7556 bfd_generic_get_relocated_section_contents
7559 bfd_byte *bfd_generic_get_relocated_section_contents
7561 struct bfd_link_info *link_info,
7562 struct bfd_link_order *link_order,
7564 bfd_boolean relocatable,
7568 Provides default handling of relocation effort for back ends
7569 which can't be bothered to do it efficiently.
7574 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
7575 struct bfd_link_info
*link_info
,
7576 struct bfd_link_order
*link_order
,
7578 bfd_boolean relocatable
,
7581 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
7582 asection
*input_section
= link_order
->u
.indirect
.section
;
7584 arelent
**reloc_vector
;
7587 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
7591 /* Read in the section. */
7592 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
7595 if (reloc_size
== 0)
7598 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
7599 if (reloc_vector
== NULL
)
7602 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
7606 if (reloc_count
< 0)
7609 if (reloc_count
> 0)
7612 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
7614 char *error_message
= NULL
;
7616 bfd_reloc_status_type r
;
7618 symbol
= *(*parent
)->sym_ptr_ptr
;
7619 if (symbol
->section
&& discarded_section (symbol
->section
))
7622 static reloc_howto_type none_howto
7623 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
7624 "unused", FALSE
, 0, 0, FALSE
);
7626 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
7627 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
7629 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
7630 (*parent
)->addend
= 0;
7631 (*parent
)->howto
= &none_howto
;
7635 r
= bfd_perform_relocation (input_bfd
,
7639 relocatable
? abfd
: NULL
,
7644 asection
*os
= input_section
->output_section
;
7646 /* A partial link, so keep the relocs. */
7647 os
->orelocation
[os
->reloc_count
] = *parent
;
7651 if (r
!= bfd_reloc_ok
)
7655 case bfd_reloc_undefined
:
7656 if (!((*link_info
->callbacks
->undefined_symbol
)
7657 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7658 input_bfd
, input_section
, (*parent
)->address
,
7662 case bfd_reloc_dangerous
:
7663 BFD_ASSERT (error_message
!= NULL
);
7664 if (!((*link_info
->callbacks
->reloc_dangerous
)
7665 (link_info
, error_message
, input_bfd
, input_section
,
7666 (*parent
)->address
)))
7669 case bfd_reloc_overflow
:
7670 if (!((*link_info
->callbacks
->reloc_overflow
)
7672 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7673 (*parent
)->howto
->name
, (*parent
)->addend
,
7674 input_bfd
, input_section
, (*parent
)->address
)))
7677 case bfd_reloc_outofrange
:
7679 This error can result when processing some partially
7680 complete binaries. Do not abort, but issue an error
7682 link_info
->callbacks
->einfo
7683 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7684 abfd
, input_section
, * parent
);
7687 case bfd_reloc_notsupported
:
7689 This error can result when processing a corrupt binary.
7690 Do not abort. Issue an error message instead. */
7691 link_info
->callbacks
->einfo
7692 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
7693 abfd
, input_section
, * parent
);
7697 /* PR 17512; file: 90c2a92e.
7698 Report unexpected results, without aborting. */
7699 link_info
->callbacks
->einfo
7700 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
7701 abfd
, input_section
, * parent
, r
);
7709 free (reloc_vector
);
7713 free (reloc_vector
);