1 /* Xtensa configuration-specific ISA information.
2 Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 3 of the
9 License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
22 #include <xtensa-isa.h>
23 #include "xtensa-isa-internal.h"
28 static xtensa_sysreg_internal sysregs
[] = {
32 { "PTEVADDR", 83, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
41 { "CCOMPARE0", 240, 0 },
42 { "CCOMPARE1", 241, 0 },
43 { "CCOMPARE2", 242, 0 },
48 { "EXCSAVE1", 209, 0 },
49 { "EXCSAVE2", 210, 0 },
50 { "EXCSAVE3", 211, 0 },
51 { "EXCSAVE4", 212, 0 },
55 { "EXCCAUSE", 232, 0 },
57 { "EXCVADDR", 238, 0 },
58 { "WINDOWBASE", 72, 0 },
59 { "WINDOWSTART", 73, 0 },
65 { "INTENABLE", 228, 0 },
66 { "DBREAKA0", 144, 0 },
67 { "DBREAKC0", 160, 0 },
68 { "DBREAKA1", 145, 0 },
69 { "DBREAKC1", 161, 0 },
70 { "IBREAKA0", 128, 0 },
71 { "IBREAKA1", 129, 0 },
72 { "IBREAKENABLE", 96, 0 },
73 { "ICOUNTLEVEL", 237, 0 },
74 { "DEBUGCAUSE", 233, 0 },
80 #define NUM_SYSREGS 49
81 #define MAX_SPECIAL_REG 245
82 #define MAX_USER_REG 0
85 /* Processor states. */
87 static xtensa_state_internal states
[] = {
92 { "INTERRUPT", 17, 0 },
99 { "EXCSAVE1", 32, 0 },
100 { "EXCSAVE2", 32, 0 },
101 { "EXCSAVE3", 32, 0 },
102 { "EXCSAVE4", 32, 0 },
106 { "EXCCAUSE", 6, 0 },
107 { "PSINTLEVEL", 4, 0 },
113 { "EXCVADDR", 32, 0 },
114 { "WindowBase", 4, 0 },
115 { "WindowStart", 16, 0 },
116 { "PSCALLINC", 2, 0 },
121 { "LITBADDR", 20, 0 },
125 { "InOCDMode", 1, 0 },
126 { "INTENABLE", 17, 0 },
127 { "DBREAKA0", 32, 0 },
128 { "DBREAKC0", 8, 0 },
129 { "DBREAKA1", 32, 0 },
130 { "DBREAKC1", 8, 0 },
131 { "IBREAKA0", 32, 0 },
132 { "IBREAKA1", 32, 0 },
133 { "IBREAKENABLE", 2, 0 },
134 { "ICOUNTLEVEL", 4, 0 },
135 { "DEBUGCAUSE", 6, 0 },
137 { "CCOMPARE0", 32, 0 },
138 { "CCOMPARE1", 32, 0 },
139 { "CCOMPARE2", 32, 0 },
143 { "INSTPGSZID4", 2, 0 },
144 { "DATAPGSZID4", 2, 0 },
148 #define NUM_STATES 58
150 enum xtensa_state_id
{
212 /* Field definitions. */
215 Field_t_Slot_inst_get (const xtensa_insnbuf insn
)
218 tie_t
= (tie_t
<< 4) | ((insn
[0] << 12) >> 28);
223 Field_t_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
226 tie_t
= (val
<< 28) >> 28;
227 insn
[0] = (insn
[0] & ~0xf0000) | (tie_t
<< 16);
231 Field_s_Slot_inst_get (const xtensa_insnbuf insn
)
234 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
239 Field_s_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
242 tie_t
= (val
<< 28) >> 28;
243 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
247 Field_r_Slot_inst_get (const xtensa_insnbuf insn
)
250 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
255 Field_r_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
258 tie_t
= (val
<< 28) >> 28;
259 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
263 Field_op2_Slot_inst_get (const xtensa_insnbuf insn
)
266 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
271 Field_op2_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
274 tie_t
= (val
<< 28) >> 28;
275 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
279 Field_op1_Slot_inst_get (const xtensa_insnbuf insn
)
282 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
287 Field_op1_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
290 tie_t
= (val
<< 28) >> 28;
291 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
295 Field_op0_Slot_inst_get (const xtensa_insnbuf insn
)
298 tie_t
= (tie_t
<< 4) | ((insn
[0] << 8) >> 28);
303 Field_op0_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
306 tie_t
= (val
<< 28) >> 28;
307 insn
[0] = (insn
[0] & ~0xf00000) | (tie_t
<< 20);
311 Field_n_Slot_inst_get (const xtensa_insnbuf insn
)
314 tie_t
= (tie_t
<< 2) | ((insn
[0] << 12) >> 30);
319 Field_n_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
322 tie_t
= (val
<< 30) >> 30;
323 insn
[0] = (insn
[0] & ~0xc0000) | (tie_t
<< 18);
327 Field_m_Slot_inst_get (const xtensa_insnbuf insn
)
330 tie_t
= (tie_t
<< 2) | ((insn
[0] << 14) >> 30);
335 Field_m_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
338 tie_t
= (val
<< 30) >> 30;
339 insn
[0] = (insn
[0] & ~0x30000) | (tie_t
<< 16);
343 Field_sr_Slot_inst_get (const xtensa_insnbuf insn
)
346 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
347 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
352 Field_sr_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
355 tie_t
= (val
<< 28) >> 28;
356 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
357 tie_t
= (val
<< 24) >> 28;
358 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
362 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn
)
365 tie_t
= (tie_t
<< 3) | ((insn
[0] << 12) >> 29);
370 Field_thi3_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
373 tie_t
= (val
<< 29) >> 29;
374 insn
[0] = (insn
[0] & ~0xe0000) | (tie_t
<< 17);
378 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn
)
381 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
386 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
389 tie_t
= (val
<< 28) >> 28;
390 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
394 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn
)
397 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
402 Field_t_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
405 tie_t
= (val
<< 28) >> 28;
406 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
410 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn
)
413 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
418 Field_r_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
421 tie_t
= (val
<< 28) >> 28;
422 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
426 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn
)
429 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
434 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
437 tie_t
= (val
<< 28) >> 28;
438 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
442 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn
)
445 tie_t
= (tie_t
<< 1) | ((insn
[0] << 21) >> 31);
450 Field_z_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
453 tie_t
= (val
<< 31) >> 31;
454 insn
[0] = (insn
[0] & ~0x400) | (tie_t
<< 10);
458 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn
)
461 tie_t
= (tie_t
<< 1) | ((insn
[0] << 20) >> 31);
466 Field_i_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
469 tie_t
= (val
<< 31) >> 31;
470 insn
[0] = (insn
[0] & ~0x800) | (tie_t
<< 11);
474 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn
)
477 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
482 Field_s_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
485 tie_t
= (val
<< 28) >> 28;
486 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
490 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn
)
493 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
498 Field_t_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
501 tie_t
= (val
<< 28) >> 28;
502 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
506 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn
)
509 tie_t
= (tie_t
<< 1) | ((insn
[0] << 23) >> 31);
514 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
517 tie_t
= (val
<< 31) >> 31;
518 insn
[0] = (insn
[0] & ~0x100) | (tie_t
<< 8);
522 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn
)
525 tie_t
= (tie_t
<< 1) | ((insn
[0] << 23) >> 31);
526 tie_t
= (tie_t
<< 4) | ((insn
[0] << 12) >> 28);
531 Field_bbi_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
534 tie_t
= (val
<< 28) >> 28;
535 insn
[0] = (insn
[0] & ~0xf0000) | (tie_t
<< 16);
536 tie_t
= (val
<< 27) >> 31;
537 insn
[0] = (insn
[0] & ~0x100) | (tie_t
<< 8);
541 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn
)
544 tie_t
= (tie_t
<< 12) | ((insn
[0] << 20) >> 20);
549 Field_imm12_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
552 tie_t
= (val
<< 20) >> 20;
553 insn
[0] = (insn
[0] & ~0xfff) | (tie_t
<< 0);
557 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn
)
560 tie_t
= (tie_t
<< 8) | ((insn
[0] << 24) >> 24);
565 Field_imm8_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
568 tie_t
= (val
<< 24) >> 24;
569 insn
[0] = (insn
[0] & ~0xff) | (tie_t
<< 0);
573 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn
)
576 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
581 Field_s_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
584 tie_t
= (val
<< 28) >> 28;
585 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
589 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn
)
592 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
593 tie_t
= (tie_t
<< 8) | ((insn
[0] << 24) >> 24);
598 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
601 tie_t
= (val
<< 24) >> 24;
602 insn
[0] = (insn
[0] & ~0xff) | (tie_t
<< 0);
603 tie_t
= (val
<< 20) >> 28;
604 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
608 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn
)
611 tie_t
= (tie_t
<< 16) | ((insn
[0] << 16) >> 16);
616 Field_imm16_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
619 tie_t
= (val
<< 16) >> 16;
620 insn
[0] = (insn
[0] & ~0xffff) | (tie_t
<< 0);
624 Field_offset_Slot_inst_get (const xtensa_insnbuf insn
)
627 tie_t
= (tie_t
<< 18) | ((insn
[0] << 14) >> 14);
632 Field_offset_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
635 tie_t
= (val
<< 14) >> 14;
636 insn
[0] = (insn
[0] & ~0x3ffff) | (tie_t
<< 0);
640 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn
)
643 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
648 Field_r_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
651 tie_t
= (val
<< 28) >> 28;
652 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
656 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn
)
659 tie_t
= (tie_t
<< 1) | ((insn
[0] << 31) >> 31);
664 Field_sa4_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
667 tie_t
= (val
<< 31) >> 31;
668 insn
[0] = (insn
[0] & ~0x1) | (tie_t
<< 0);
672 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn
)
675 tie_t
= (tie_t
<< 1) | ((insn
[0] << 27) >> 31);
680 Field_sae4_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
683 tie_t
= (val
<< 31) >> 31;
684 insn
[0] = (insn
[0] & ~0x10) | (tie_t
<< 4);
688 Field_sae_Slot_inst_get (const xtensa_insnbuf insn
)
691 tie_t
= (tie_t
<< 1) | ((insn
[0] << 27) >> 31);
692 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
697 Field_sae_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
700 tie_t
= (val
<< 28) >> 28;
701 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
702 tie_t
= (val
<< 27) >> 31;
703 insn
[0] = (insn
[0] & ~0x10) | (tie_t
<< 4);
707 Field_sal_Slot_inst_get (const xtensa_insnbuf insn
)
710 tie_t
= (tie_t
<< 1) | ((insn
[0] << 31) >> 31);
711 tie_t
= (tie_t
<< 4) | ((insn
[0] << 12) >> 28);
716 Field_sal_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
719 tie_t
= (val
<< 28) >> 28;
720 insn
[0] = (insn
[0] & ~0xf0000) | (tie_t
<< 16);
721 tie_t
= (val
<< 27) >> 31;
722 insn
[0] = (insn
[0] & ~0x1) | (tie_t
<< 0);
726 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn
)
729 tie_t
= (tie_t
<< 1) | ((insn
[0] << 31) >> 31);
730 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
735 Field_sargt_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
738 tie_t
= (val
<< 28) >> 28;
739 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
740 tie_t
= (val
<< 27) >> 31;
741 insn
[0] = (insn
[0] & ~0x1) | (tie_t
<< 0);
745 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn
)
748 tie_t
= (tie_t
<< 1) | ((insn
[0] << 15) >> 31);
753 Field_sas4_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
756 tie_t
= (val
<< 31) >> 31;
757 insn
[0] = (insn
[0] & ~0x10000) | (tie_t
<< 16);
761 Field_sas_Slot_inst_get (const xtensa_insnbuf insn
)
764 tie_t
= (tie_t
<< 1) | ((insn
[0] << 15) >> 31);
765 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
770 Field_sas_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
773 tie_t
= (val
<< 28) >> 28;
774 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
775 tie_t
= (val
<< 27) >> 31;
776 insn
[0] = (insn
[0] & ~0x10000) | (tie_t
<< 16);
780 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn
)
783 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
784 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
789 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
792 tie_t
= (val
<< 28) >> 28;
793 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
794 tie_t
= (val
<< 24) >> 28;
795 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
799 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn
)
802 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
803 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
808 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
811 tie_t
= (val
<< 28) >> 28;
812 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
813 tie_t
= (val
<< 24) >> 28;
814 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
818 Field_st_Slot_inst_get (const xtensa_insnbuf insn
)
821 tie_t
= (tie_t
<< 4) | ((insn
[0] << 16) >> 28);
822 tie_t
= (tie_t
<< 4) | ((insn
[0] << 12) >> 28);
827 Field_st_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
830 tie_t
= (val
<< 28) >> 28;
831 insn
[0] = (insn
[0] & ~0xf0000) | (tie_t
<< 16);
832 tie_t
= (val
<< 24) >> 28;
833 insn
[0] = (insn
[0] & ~0xf000) | (tie_t
<< 12);
837 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn
)
840 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
841 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
846 Field_st_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
849 tie_t
= (val
<< 28) >> 28;
850 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
851 tie_t
= (val
<< 24) >> 28;
852 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
856 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn
)
859 tie_t
= (tie_t
<< 4) | ((insn
[0] << 24) >> 28);
860 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
865 Field_st_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
868 tie_t
= (val
<< 28) >> 28;
869 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
870 tie_t
= (val
<< 24) >> 28;
871 insn
[0] = (insn
[0] & ~0xf0) | (tie_t
<< 4);
875 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn
)
878 tie_t
= (tie_t
<< 4) | ((insn
[0] << 20) >> 28);
883 Field_imm4_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
886 tie_t
= (val
<< 28) >> 28;
887 insn
[0] = (insn
[0] & ~0xf00) | (tie_t
<< 8);
891 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn
)
894 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
899 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
902 tie_t
= (val
<< 28) >> 28;
903 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
907 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn
)
910 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
915 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
918 tie_t
= (val
<< 28) >> 28;
919 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
923 Field_mn_Slot_inst_get (const xtensa_insnbuf insn
)
926 tie_t
= (tie_t
<< 2) | ((insn
[0] << 12) >> 30);
927 tie_t
= (tie_t
<< 2) | ((insn
[0] << 14) >> 30);
932 Field_mn_Slot_inst_set (xtensa_insnbuf insn
, uint32 val
)
935 tie_t
= (val
<< 30) >> 30;
936 insn
[0] = (insn
[0] & ~0x30000) | (tie_t
<< 16);
937 tie_t
= (val
<< 28) >> 30;
938 insn
[0] = (insn
[0] & ~0xc0000) | (tie_t
<< 18);
942 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn
)
945 tie_t
= (tie_t
<< 1) | ((insn
[0] << 20) >> 31);
950 Field_i_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
953 tie_t
= (val
<< 31) >> 31;
954 insn
[0] = (insn
[0] & ~0x800) | (tie_t
<< 11);
958 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn
)
961 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
966 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
969 tie_t
= (val
<< 28) >> 28;
970 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
974 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn
)
977 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
982 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
985 tie_t
= (val
<< 28) >> 28;
986 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
990 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn
)
993 tie_t
= (tie_t
<< 2) | ((insn
[0] << 22) >> 30);
998 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1001 tie_t
= (val
<< 30) >> 30;
1002 insn
[0] = (insn
[0] & ~0x300) | (tie_t
<< 8);
1006 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn
)
1009 tie_t
= (tie_t
<< 2) | ((insn
[0] << 22) >> 30);
1014 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
1017 tie_t
= (val
<< 30) >> 30;
1018 insn
[0] = (insn
[0] & ~0x300) | (tie_t
<< 8);
1022 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn
)
1025 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1030 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1033 tie_t
= (val
<< 28) >> 28;
1034 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1038 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn
)
1041 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1046 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
1049 tie_t
= (val
<< 28) >> 28;
1050 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1054 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn
)
1057 tie_t
= (tie_t
<< 3) | ((insn
[0] << 21) >> 29);
1062 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1065 tie_t
= (val
<< 29) >> 29;
1066 insn
[0] = (insn
[0] & ~0x700) | (tie_t
<< 8);
1070 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn
)
1073 tie_t
= (tie_t
<< 3) | ((insn
[0] << 21) >> 29);
1078 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
1081 tie_t
= (val
<< 29) >> 29;
1082 insn
[0] = (insn
[0] & ~0x700) | (tie_t
<< 8);
1086 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn
)
1089 tie_t
= (tie_t
<< 1) | ((insn
[0] << 21) >> 31);
1094 Field_z_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1097 tie_t
= (val
<< 31) >> 31;
1098 insn
[0] = (insn
[0] & ~0x400) | (tie_t
<< 10);
1102 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn
)
1105 tie_t
= (tie_t
<< 2) | ((insn
[0] << 22) >> 30);
1106 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1111 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1114 tie_t
= (val
<< 28) >> 28;
1115 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1116 tie_t
= (val
<< 26) >> 30;
1117 insn
[0] = (insn
[0] & ~0x300) | (tie_t
<< 8);
1121 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn
)
1124 tie_t
= (tie_t
<< 2) | ((insn
[0] << 22) >> 30);
1125 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1130 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
1133 tie_t
= (val
<< 28) >> 28;
1134 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1135 tie_t
= (val
<< 26) >> 30;
1136 insn
[0] = (insn
[0] & ~0x300) | (tie_t
<< 8);
1140 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn
)
1143 tie_t
= (tie_t
<< 3) | ((insn
[0] << 21) >> 29);
1144 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1149 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn
, uint32 val
)
1152 tie_t
= (val
<< 28) >> 28;
1153 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1154 tie_t
= (val
<< 25) >> 29;
1155 insn
[0] = (insn
[0] & ~0x700) | (tie_t
<< 8);
1159 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn
)
1162 tie_t
= (tie_t
<< 3) | ((insn
[0] << 21) >> 29);
1163 tie_t
= (tie_t
<< 4) | ((insn
[0] << 28) >> 28);
1168 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn
, uint32 val
)
1171 tie_t
= (val
<< 28) >> 28;
1172 insn
[0] = (insn
[0] & ~0xf) | (tie_t
<< 0);
1173 tie_t
= (val
<< 25) >> 29;
1174 insn
[0] = (insn
[0] & ~0x700) | (tie_t
<< 8);
1178 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED
,
1179 uint32 val ATTRIBUTE_UNUSED
)
1185 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED
)
1191 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED
)
1197 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED
)
1203 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED
)
1208 enum xtensa_field_id
{
1251 /* Functional units. */
1253 static xtensa_funcUnit_internal funcUnits
[] = {
1258 /* Register files. */
1260 enum xtensa_regfile_id
{
1264 static xtensa_regfile_internal regfiles
[] = {
1265 { "AR", "a", REGFILE_AR
, 32, 64 }
1271 static xtensa_interface_internal interfaces
[] = {
1276 /* Constant tables. */
1278 /* constant table ai4c */
1279 static const unsigned CONST_TBL_ai4c_0
[] = {
1299 /* constant table b4c */
1300 static const unsigned CONST_TBL_b4c_0
[] = {
1320 /* constant table b4cu */
1321 static const unsigned CONST_TBL_b4cu_0
[] = {
1342 /* Instruction operands. */
1345 Operand_soffsetx4_decode (uint32
*valp
)
1347 unsigned soffsetx4_0
, offset_0
;
1348 offset_0
= *valp
& 0x3ffff;
1349 soffsetx4_0
= 0x4 + ((((int) offset_0
<< 14) >> 14) << 2);
1350 *valp
= soffsetx4_0
;
1355 Operand_soffsetx4_encode (uint32
*valp
)
1357 unsigned offset_0
, soffsetx4_0
;
1358 soffsetx4_0
= *valp
;
1359 offset_0
= ((soffsetx4_0
- 0x4) >> 2) & 0x3ffff;
1365 Operand_soffsetx4_ator (uint32
*valp
, uint32 pc
)
1367 *valp
-= (pc
& ~0x3);
1372 Operand_soffsetx4_rtoa (uint32
*valp
, uint32 pc
)
1374 *valp
+= (pc
& ~0x3);
1379 Operand_uimm12x8_decode (uint32
*valp
)
1381 unsigned uimm12x8_0
, imm12_0
;
1382 imm12_0
= *valp
& 0xfff;
1383 uimm12x8_0
= imm12_0
<< 3;
1389 Operand_uimm12x8_encode (uint32
*valp
)
1391 unsigned imm12_0
, uimm12x8_0
;
1393 imm12_0
= ((uimm12x8_0
>> 3) & 0xfff);
1399 Operand_simm4_decode (uint32
*valp
)
1401 unsigned simm4_0
, mn_0
;
1403 simm4_0
= ((int) mn_0
<< 28) >> 28;
1409 Operand_simm4_encode (uint32
*valp
)
1411 unsigned mn_0
, simm4_0
;
1413 mn_0
= (simm4_0
& 0xf);
1419 Operand_arr_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1425 Operand_arr_encode (uint32
*valp
)
1428 error
= (*valp
& ~0xf) != 0;
1433 Operand_ars_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1439 Operand_ars_encode (uint32
*valp
)
1442 error
= (*valp
& ~0xf) != 0;
1447 Operand_art_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1453 Operand_art_encode (uint32
*valp
)
1456 error
= (*valp
& ~0xf) != 0;
1461 Operand_ar0_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1467 Operand_ar0_encode (uint32
*valp
)
1470 error
= (*valp
& ~0x3f) != 0;
1475 Operand_ar4_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1481 Operand_ar4_encode (uint32
*valp
)
1484 error
= (*valp
& ~0x3f) != 0;
1489 Operand_ar8_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1495 Operand_ar8_encode (uint32
*valp
)
1498 error
= (*valp
& ~0x3f) != 0;
1503 Operand_ar12_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1509 Operand_ar12_encode (uint32
*valp
)
1512 error
= (*valp
& ~0x3f) != 0;
1517 Operand_ars_entry_decode (uint32
*valp ATTRIBUTE_UNUSED
)
1523 Operand_ars_entry_encode (uint32
*valp
)
1526 error
= (*valp
& ~0x3f) != 0;
1531 Operand_immrx4_decode (uint32
*valp
)
1533 unsigned immrx4_0
, r_0
;
1535 immrx4_0
= (((0xfffffff) << 4) | r_0
) << 2;
1541 Operand_immrx4_encode (uint32
*valp
)
1543 unsigned r_0
, immrx4_0
;
1545 r_0
= ((immrx4_0
>> 2) & 0xf);
1551 Operand_lsi4x4_decode (uint32
*valp
)
1553 unsigned lsi4x4_0
, r_0
;
1555 lsi4x4_0
= r_0
<< 2;
1561 Operand_lsi4x4_encode (uint32
*valp
)
1563 unsigned r_0
, lsi4x4_0
;
1565 r_0
= ((lsi4x4_0
>> 2) & 0xf);
1571 Operand_simm7_decode (uint32
*valp
)
1573 unsigned simm7_0
, imm7_0
;
1574 imm7_0
= *valp
& 0x7f;
1575 simm7_0
= ((((-((((imm7_0
>> 6) & 1)) & (((imm7_0
>> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0
;
1581 Operand_simm7_encode (uint32
*valp
)
1583 unsigned imm7_0
, simm7_0
;
1585 imm7_0
= (simm7_0
& 0x7f);
1591 Operand_uimm6_decode (uint32
*valp
)
1593 unsigned uimm6_0
, imm6_0
;
1594 imm6_0
= *valp
& 0x3f;
1595 uimm6_0
= 0x4 + (((0) << 6) | imm6_0
);
1601 Operand_uimm6_encode (uint32
*valp
)
1603 unsigned imm6_0
, uimm6_0
;
1605 imm6_0
= (uimm6_0
- 0x4) & 0x3f;
1611 Operand_uimm6_ator (uint32
*valp
, uint32 pc
)
1618 Operand_uimm6_rtoa (uint32
*valp
, uint32 pc
)
1625 Operand_ai4const_decode (uint32
*valp
)
1627 unsigned ai4const_0
, t_0
;
1629 ai4const_0
= CONST_TBL_ai4c_0
[t_0
& 0xf];
1635 Operand_ai4const_encode (uint32
*valp
)
1637 unsigned t_0
, ai4const_0
;
1641 case 0xffffffff: t_0
= 0; break;
1642 case 0x1: t_0
= 0x1; break;
1643 case 0x2: t_0
= 0x2; break;
1644 case 0x3: t_0
= 0x3; break;
1645 case 0x4: t_0
= 0x4; break;
1646 case 0x5: t_0
= 0x5; break;
1647 case 0x6: t_0
= 0x6; break;
1648 case 0x7: t_0
= 0x7; break;
1649 case 0x8: t_0
= 0x8; break;
1650 case 0x9: t_0
= 0x9; break;
1651 case 0xa: t_0
= 0xa; break;
1652 case 0xb: t_0
= 0xb; break;
1653 case 0xc: t_0
= 0xc; break;
1654 case 0xd: t_0
= 0xd; break;
1655 case 0xe: t_0
= 0xe; break;
1656 default: t_0
= 0xf; break;
1663 Operand_b4const_decode (uint32
*valp
)
1665 unsigned b4const_0
, r_0
;
1667 b4const_0
= CONST_TBL_b4c_0
[r_0
& 0xf];
1673 Operand_b4const_encode (uint32
*valp
)
1675 unsigned r_0
, b4const_0
;
1679 case 0xffffffff: r_0
= 0; break;
1680 case 0x1: r_0
= 0x1; break;
1681 case 0x2: r_0
= 0x2; break;
1682 case 0x3: r_0
= 0x3; break;
1683 case 0x4: r_0
= 0x4; break;
1684 case 0x5: r_0
= 0x5; break;
1685 case 0x6: r_0
= 0x6; break;
1686 case 0x7: r_0
= 0x7; break;
1687 case 0x8: r_0
= 0x8; break;
1688 case 0xa: r_0
= 0x9; break;
1689 case 0xc: r_0
= 0xa; break;
1690 case 0x10: r_0
= 0xb; break;
1691 case 0x20: r_0
= 0xc; break;
1692 case 0x40: r_0
= 0xd; break;
1693 case 0x80: r_0
= 0xe; break;
1694 default: r_0
= 0xf; break;
1701 Operand_b4constu_decode (uint32
*valp
)
1703 unsigned b4constu_0
, r_0
;
1705 b4constu_0
= CONST_TBL_b4cu_0
[r_0
& 0xf];
1711 Operand_b4constu_encode (uint32
*valp
)
1713 unsigned r_0
, b4constu_0
;
1717 case 0x8000: r_0
= 0; break;
1718 case 0x10000: r_0
= 0x1; break;
1719 case 0x2: r_0
= 0x2; break;
1720 case 0x3: r_0
= 0x3; break;
1721 case 0x4: r_0
= 0x4; break;
1722 case 0x5: r_0
= 0x5; break;
1723 case 0x6: r_0
= 0x6; break;
1724 case 0x7: r_0
= 0x7; break;
1725 case 0x8: r_0
= 0x8; break;
1726 case 0xa: r_0
= 0x9; break;
1727 case 0xc: r_0
= 0xa; break;
1728 case 0x10: r_0
= 0xb; break;
1729 case 0x20: r_0
= 0xc; break;
1730 case 0x40: r_0
= 0xd; break;
1731 case 0x80: r_0
= 0xe; break;
1732 default: r_0
= 0xf; break;
1739 Operand_uimm8_decode (uint32
*valp
)
1741 unsigned uimm8_0
, imm8_0
;
1742 imm8_0
= *valp
& 0xff;
1749 Operand_uimm8_encode (uint32
*valp
)
1751 unsigned imm8_0
, uimm8_0
;
1753 imm8_0
= (uimm8_0
& 0xff);
1759 Operand_uimm8x2_decode (uint32
*valp
)
1761 unsigned uimm8x2_0
, imm8_0
;
1762 imm8_0
= *valp
& 0xff;
1763 uimm8x2_0
= imm8_0
<< 1;
1769 Operand_uimm8x2_encode (uint32
*valp
)
1771 unsigned imm8_0
, uimm8x2_0
;
1773 imm8_0
= ((uimm8x2_0
>> 1) & 0xff);
1779 Operand_uimm8x4_decode (uint32
*valp
)
1781 unsigned uimm8x4_0
, imm8_0
;
1782 imm8_0
= *valp
& 0xff;
1783 uimm8x4_0
= imm8_0
<< 2;
1789 Operand_uimm8x4_encode (uint32
*valp
)
1791 unsigned imm8_0
, uimm8x4_0
;
1793 imm8_0
= ((uimm8x4_0
>> 2) & 0xff);
1799 Operand_uimm4x16_decode (uint32
*valp
)
1801 unsigned uimm4x16_0
, op2_0
;
1802 op2_0
= *valp
& 0xf;
1803 uimm4x16_0
= op2_0
<< 4;
1809 Operand_uimm4x16_encode (uint32
*valp
)
1811 unsigned op2_0
, uimm4x16_0
;
1813 op2_0
= ((uimm4x16_0
>> 4) & 0xf);
1819 Operand_simm8_decode (uint32
*valp
)
1821 unsigned simm8_0
, imm8_0
;
1822 imm8_0
= *valp
& 0xff;
1823 simm8_0
= ((int) imm8_0
<< 24) >> 24;
1829 Operand_simm8_encode (uint32
*valp
)
1831 unsigned imm8_0
, simm8_0
;
1833 imm8_0
= (simm8_0
& 0xff);
1839 Operand_simm8x256_decode (uint32
*valp
)
1841 unsigned simm8x256_0
, imm8_0
;
1842 imm8_0
= *valp
& 0xff;
1843 simm8x256_0
= (((int) imm8_0
<< 24) >> 24) << 8;
1844 *valp
= simm8x256_0
;
1849 Operand_simm8x256_encode (uint32
*valp
)
1851 unsigned imm8_0
, simm8x256_0
;
1852 simm8x256_0
= *valp
;
1853 imm8_0
= ((simm8x256_0
>> 8) & 0xff);
1859 Operand_simm12b_decode (uint32
*valp
)
1861 unsigned simm12b_0
, imm12b_0
;
1862 imm12b_0
= *valp
& 0xfff;
1863 simm12b_0
= ((int) imm12b_0
<< 20) >> 20;
1869 Operand_simm12b_encode (uint32
*valp
)
1871 unsigned imm12b_0
, simm12b_0
;
1873 imm12b_0
= (simm12b_0
& 0xfff);
1879 Operand_msalp32_decode (uint32
*valp
)
1881 unsigned msalp32_0
, sal_0
;
1882 sal_0
= *valp
& 0x1f;
1883 msalp32_0
= 0x20 - sal_0
;
1889 Operand_msalp32_encode (uint32
*valp
)
1891 unsigned sal_0
, msalp32_0
;
1893 sal_0
= (0x20 - msalp32_0
) & 0x1f;
1899 Operand_op2p1_decode (uint32
*valp
)
1901 unsigned op2p1_0
, op2_0
;
1902 op2_0
= *valp
& 0xf;
1903 op2p1_0
= op2_0
+ 0x1;
1909 Operand_op2p1_encode (uint32
*valp
)
1911 unsigned op2_0
, op2p1_0
;
1913 op2_0
= (op2p1_0
- 0x1) & 0xf;
1919 Operand_label8_decode (uint32
*valp
)
1921 unsigned label8_0
, imm8_0
;
1922 imm8_0
= *valp
& 0xff;
1923 label8_0
= 0x4 + (((int) imm8_0
<< 24) >> 24);
1929 Operand_label8_encode (uint32
*valp
)
1931 unsigned imm8_0
, label8_0
;
1933 imm8_0
= (label8_0
- 0x4) & 0xff;
1939 Operand_label8_ator (uint32
*valp
, uint32 pc
)
1946 Operand_label8_rtoa (uint32
*valp
, uint32 pc
)
1953 Operand_ulabel8_decode (uint32
*valp
)
1955 unsigned ulabel8_0
, imm8_0
;
1956 imm8_0
= *valp
& 0xff;
1957 ulabel8_0
= 0x4 + (((0) << 8) | imm8_0
);
1963 Operand_ulabel8_encode (uint32
*valp
)
1965 unsigned imm8_0
, ulabel8_0
;
1967 imm8_0
= (ulabel8_0
- 0x4) & 0xff;
1973 Operand_ulabel8_ator (uint32
*valp
, uint32 pc
)
1980 Operand_ulabel8_rtoa (uint32
*valp
, uint32 pc
)
1987 Operand_label12_decode (uint32
*valp
)
1989 unsigned label12_0
, imm12_0
;
1990 imm12_0
= *valp
& 0xfff;
1991 label12_0
= 0x4 + (((int) imm12_0
<< 20) >> 20);
1997 Operand_label12_encode (uint32
*valp
)
1999 unsigned imm12_0
, label12_0
;
2001 imm12_0
= (label12_0
- 0x4) & 0xfff;
2007 Operand_label12_ator (uint32
*valp
, uint32 pc
)
2014 Operand_label12_rtoa (uint32
*valp
, uint32 pc
)
2021 Operand_soffset_decode (uint32
*valp
)
2023 unsigned soffset_0
, offset_0
;
2024 offset_0
= *valp
& 0x3ffff;
2025 soffset_0
= 0x4 + (((int) offset_0
<< 14) >> 14);
2031 Operand_soffset_encode (uint32
*valp
)
2033 unsigned offset_0
, soffset_0
;
2035 offset_0
= (soffset_0
- 0x4) & 0x3ffff;
2041 Operand_soffset_ator (uint32
*valp
, uint32 pc
)
2048 Operand_soffset_rtoa (uint32
*valp
, uint32 pc
)
2055 Operand_uimm16x4_decode (uint32
*valp
)
2057 unsigned uimm16x4_0
, imm16_0
;
2058 imm16_0
= *valp
& 0xffff;
2059 uimm16x4_0
= (((0xffff) << 16) | imm16_0
) << 2;
2065 Operand_uimm16x4_encode (uint32
*valp
)
2067 unsigned imm16_0
, uimm16x4_0
;
2069 imm16_0
= (uimm16x4_0
>> 2) & 0xffff;
2075 Operand_uimm16x4_ator (uint32
*valp
, uint32 pc
)
2077 *valp
-= ((pc
+ 3) & ~0x3);
2082 Operand_uimm16x4_rtoa (uint32
*valp
, uint32 pc
)
2084 *valp
+= ((pc
+ 3) & ~0x3);
2089 Operand_immt_decode (uint32
*valp
)
2091 unsigned immt_0
, t_0
;
2099 Operand_immt_encode (uint32
*valp
)
2101 unsigned t_0
, immt_0
;
2109 Operand_imms_decode (uint32
*valp
)
2111 unsigned imms_0
, s_0
;
2119 Operand_imms_encode (uint32
*valp
)
2121 unsigned s_0
, imms_0
;
2128 static xtensa_operand_internal operands
[] = {
2129 { "soffsetx4", FIELD_offset
, -1, 0,
2130 XTENSA_OPERAND_IS_PCRELATIVE
,
2131 Operand_soffsetx4_encode
, Operand_soffsetx4_decode
,
2132 Operand_soffsetx4_ator
, Operand_soffsetx4_rtoa
},
2133 { "uimm12x8", FIELD_imm12
, -1, 0,
2135 Operand_uimm12x8_encode
, Operand_uimm12x8_decode
,
2137 { "simm4", FIELD_mn
, -1, 0,
2139 Operand_simm4_encode
, Operand_simm4_decode
,
2141 { "arr", FIELD_r
, REGFILE_AR
, 1,
2142 XTENSA_OPERAND_IS_REGISTER
,
2143 Operand_arr_encode
, Operand_arr_decode
,
2145 { "ars", FIELD_s
, REGFILE_AR
, 1,
2146 XTENSA_OPERAND_IS_REGISTER
,
2147 Operand_ars_encode
, Operand_ars_decode
,
2149 { "*ars_invisible", FIELD_s
, REGFILE_AR
, 1,
2150 XTENSA_OPERAND_IS_REGISTER
| XTENSA_OPERAND_IS_INVISIBLE
,
2151 Operand_ars_encode
, Operand_ars_decode
,
2153 { "art", FIELD_t
, REGFILE_AR
, 1,
2154 XTENSA_OPERAND_IS_REGISTER
,
2155 Operand_art_encode
, Operand_art_decode
,
2157 { "ar0", FIELD__ar0
, REGFILE_AR
, 1,
2158 XTENSA_OPERAND_IS_REGISTER
| XTENSA_OPERAND_IS_INVISIBLE
,
2159 Operand_ar0_encode
, Operand_ar0_decode
,
2161 { "ar4", FIELD__ar4
, REGFILE_AR
, 1,
2162 XTENSA_OPERAND_IS_REGISTER
| XTENSA_OPERAND_IS_INVISIBLE
,
2163 Operand_ar4_encode
, Operand_ar4_decode
,
2165 { "ar8", FIELD__ar8
, REGFILE_AR
, 1,
2166 XTENSA_OPERAND_IS_REGISTER
| XTENSA_OPERAND_IS_INVISIBLE
,
2167 Operand_ar8_encode
, Operand_ar8_decode
,
2169 { "ar12", FIELD__ar12
, REGFILE_AR
, 1,
2170 XTENSA_OPERAND_IS_REGISTER
| XTENSA_OPERAND_IS_INVISIBLE
,
2171 Operand_ar12_encode
, Operand_ar12_decode
,
2173 { "ars_entry", FIELD_s
, REGFILE_AR
, 1,
2174 XTENSA_OPERAND_IS_REGISTER
,
2175 Operand_ars_entry_encode
, Operand_ars_entry_decode
,
2177 { "immrx4", FIELD_r
, -1, 0,
2179 Operand_immrx4_encode
, Operand_immrx4_decode
,
2181 { "lsi4x4", FIELD_r
, -1, 0,
2183 Operand_lsi4x4_encode
, Operand_lsi4x4_decode
,
2185 { "simm7", FIELD_imm7
, -1, 0,
2187 Operand_simm7_encode
, Operand_simm7_decode
,
2189 { "uimm6", FIELD_imm6
, -1, 0,
2190 XTENSA_OPERAND_IS_PCRELATIVE
,
2191 Operand_uimm6_encode
, Operand_uimm6_decode
,
2192 Operand_uimm6_ator
, Operand_uimm6_rtoa
},
2193 { "ai4const", FIELD_t
, -1, 0,
2195 Operand_ai4const_encode
, Operand_ai4const_decode
,
2197 { "b4const", FIELD_r
, -1, 0,
2199 Operand_b4const_encode
, Operand_b4const_decode
,
2201 { "b4constu", FIELD_r
, -1, 0,
2203 Operand_b4constu_encode
, Operand_b4constu_decode
,
2205 { "uimm8", FIELD_imm8
, -1, 0,
2207 Operand_uimm8_encode
, Operand_uimm8_decode
,
2209 { "uimm8x2", FIELD_imm8
, -1, 0,
2211 Operand_uimm8x2_encode
, Operand_uimm8x2_decode
,
2213 { "uimm8x4", FIELD_imm8
, -1, 0,
2215 Operand_uimm8x4_encode
, Operand_uimm8x4_decode
,
2217 { "uimm4x16", FIELD_op2
, -1, 0,
2219 Operand_uimm4x16_encode
, Operand_uimm4x16_decode
,
2221 { "simm8", FIELD_imm8
, -1, 0,
2223 Operand_simm8_encode
, Operand_simm8_decode
,
2225 { "simm8x256", FIELD_imm8
, -1, 0,
2227 Operand_simm8x256_encode
, Operand_simm8x256_decode
,
2229 { "simm12b", FIELD_imm12b
, -1, 0,
2231 Operand_simm12b_encode
, Operand_simm12b_decode
,
2233 { "msalp32", FIELD_sal
, -1, 0,
2235 Operand_msalp32_encode
, Operand_msalp32_decode
,
2237 { "op2p1", FIELD_op2
, -1, 0,
2239 Operand_op2p1_encode
, Operand_op2p1_decode
,
2241 { "label8", FIELD_imm8
, -1, 0,
2242 XTENSA_OPERAND_IS_PCRELATIVE
,
2243 Operand_label8_encode
, Operand_label8_decode
,
2244 Operand_label8_ator
, Operand_label8_rtoa
},
2245 { "ulabel8", FIELD_imm8
, -1, 0,
2246 XTENSA_OPERAND_IS_PCRELATIVE
,
2247 Operand_ulabel8_encode
, Operand_ulabel8_decode
,
2248 Operand_ulabel8_ator
, Operand_ulabel8_rtoa
},
2249 { "label12", FIELD_imm12
, -1, 0,
2250 XTENSA_OPERAND_IS_PCRELATIVE
,
2251 Operand_label12_encode
, Operand_label12_decode
,
2252 Operand_label12_ator
, Operand_label12_rtoa
},
2253 { "soffset", FIELD_offset
, -1, 0,
2254 XTENSA_OPERAND_IS_PCRELATIVE
,
2255 Operand_soffset_encode
, Operand_soffset_decode
,
2256 Operand_soffset_ator
, Operand_soffset_rtoa
},
2257 { "uimm16x4", FIELD_imm16
, -1, 0,
2258 XTENSA_OPERAND_IS_PCRELATIVE
,
2259 Operand_uimm16x4_encode
, Operand_uimm16x4_decode
,
2260 Operand_uimm16x4_ator
, Operand_uimm16x4_rtoa
},
2261 { "immt", FIELD_t
, -1, 0,
2263 Operand_immt_encode
, Operand_immt_decode
,
2265 { "imms", FIELD_s
, -1, 0,
2267 Operand_imms_encode
, Operand_imms_decode
,
2269 { "t", FIELD_t
, -1, 0, 0, 0, 0, 0, 0 },
2270 { "bbi4", FIELD_bbi4
, -1, 0, 0, 0, 0, 0, 0 },
2271 { "bbi", FIELD_bbi
, -1, 0, 0, 0, 0, 0, 0 },
2272 { "imm12", FIELD_imm12
, -1, 0, 0, 0, 0, 0, 0 },
2273 { "imm8", FIELD_imm8
, -1, 0, 0, 0, 0, 0, 0 },
2274 { "s", FIELD_s
, -1, 0, 0, 0, 0, 0, 0 },
2275 { "imm12b", FIELD_imm12b
, -1, 0, 0, 0, 0, 0, 0 },
2276 { "imm16", FIELD_imm16
, -1, 0, 0, 0, 0, 0, 0 },
2277 { "m", FIELD_m
, -1, 0, 0, 0, 0, 0, 0 },
2278 { "n", FIELD_n
, -1, 0, 0, 0, 0, 0, 0 },
2279 { "offset", FIELD_offset
, -1, 0, 0, 0, 0, 0, 0 },
2280 { "op0", FIELD_op0
, -1, 0, 0, 0, 0, 0, 0 },
2281 { "op1", FIELD_op1
, -1, 0, 0, 0, 0, 0, 0 },
2282 { "op2", FIELD_op2
, -1, 0, 0, 0, 0, 0, 0 },
2283 { "r", FIELD_r
, -1, 0, 0, 0, 0, 0, 0 },
2284 { "sa4", FIELD_sa4
, -1, 0, 0, 0, 0, 0, 0 },
2285 { "sae4", FIELD_sae4
, -1, 0, 0, 0, 0, 0, 0 },
2286 { "sae", FIELD_sae
, -1, 0, 0, 0, 0, 0, 0 },
2287 { "sal", FIELD_sal
, -1, 0, 0, 0, 0, 0, 0 },
2288 { "sargt", FIELD_sargt
, -1, 0, 0, 0, 0, 0, 0 },
2289 { "sas4", FIELD_sas4
, -1, 0, 0, 0, 0, 0, 0 },
2290 { "sas", FIELD_sas
, -1, 0, 0, 0, 0, 0, 0 },
2291 { "sr", FIELD_sr
, -1, 0, 0, 0, 0, 0, 0 },
2292 { "st", FIELD_st
, -1, 0, 0, 0, 0, 0, 0 },
2293 { "thi3", FIELD_thi3
, -1, 0, 0, 0, 0, 0, 0 },
2294 { "imm4", FIELD_imm4
, -1, 0, 0, 0, 0, 0, 0 },
2295 { "mn", FIELD_mn
, -1, 0, 0, 0, 0, 0, 0 },
2296 { "i", FIELD_i
, -1, 0, 0, 0, 0, 0, 0 },
2297 { "imm6lo", FIELD_imm6lo
, -1, 0, 0, 0, 0, 0, 0 },
2298 { "imm6hi", FIELD_imm6hi
, -1, 0, 0, 0, 0, 0, 0 },
2299 { "imm7lo", FIELD_imm7lo
, -1, 0, 0, 0, 0, 0, 0 },
2300 { "imm7hi", FIELD_imm7hi
, -1, 0, 0, 0, 0, 0, 0 },
2301 { "z", FIELD_z
, -1, 0, 0, 0, 0, 0, 0 },
2302 { "imm6", FIELD_imm6
, -1, 0, 0, 0, 0, 0, 0 },
2303 { "imm7", FIELD_imm7
, -1, 0, 0, 0, 0, 0, 0 }
2306 enum xtensa_operand_id
{
2312 OPERAND__ars_invisible
,
2382 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs
[] = {
2383 { { STATE_PSRING
}, 'i' },
2384 { { STATE_PSEXCM
}, 'm' },
2385 { { STATE_EPC1
}, 'i' }
2388 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs
[] = {
2389 { { STATE_PSEXCM
}, 'i' },
2390 { { STATE_PSRING
}, 'i' },
2391 { { STATE_DEPC
}, 'i' }
2394 static xtensa_arg_internal Iclass_xt_iclass_call12_args
[] = {
2395 { { OPERAND_soffsetx4
}, 'i' },
2396 { { OPERAND_ar12
}, 'o' }
2399 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs
[] = {
2400 { { STATE_PSCALLINC
}, 'o' }
2403 static xtensa_arg_internal Iclass_xt_iclass_call8_args
[] = {
2404 { { OPERAND_soffsetx4
}, 'i' },
2405 { { OPERAND_ar8
}, 'o' }
2408 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs
[] = {
2409 { { STATE_PSCALLINC
}, 'o' }
2412 static xtensa_arg_internal Iclass_xt_iclass_call4_args
[] = {
2413 { { OPERAND_soffsetx4
}, 'i' },
2414 { { OPERAND_ar4
}, 'o' }
2417 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs
[] = {
2418 { { STATE_PSCALLINC
}, 'o' }
2421 static xtensa_arg_internal Iclass_xt_iclass_callx12_args
[] = {
2422 { { OPERAND_ars
}, 'i' },
2423 { { OPERAND_ar12
}, 'o' }
2426 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs
[] = {
2427 { { STATE_PSCALLINC
}, 'o' }
2430 static xtensa_arg_internal Iclass_xt_iclass_callx8_args
[] = {
2431 { { OPERAND_ars
}, 'i' },
2432 { { OPERAND_ar8
}, 'o' }
2435 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs
[] = {
2436 { { STATE_PSCALLINC
}, 'o' }
2439 static xtensa_arg_internal Iclass_xt_iclass_callx4_args
[] = {
2440 { { OPERAND_ars
}, 'i' },
2441 { { OPERAND_ar4
}, 'o' }
2444 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs
[] = {
2445 { { STATE_PSCALLINC
}, 'o' }
2448 static xtensa_arg_internal Iclass_xt_iclass_entry_args
[] = {
2449 { { OPERAND_ars_entry
}, 's' },
2450 { { OPERAND_ars
}, 'i' },
2451 { { OPERAND_uimm12x8
}, 'i' }
2454 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs
[] = {
2455 { { STATE_PSCALLINC
}, 'i' },
2456 { { STATE_PSEXCM
}, 'i' },
2457 { { STATE_PSWOE
}, 'i' },
2458 { { STATE_WindowBase
}, 'm' },
2459 { { STATE_WindowStart
}, 'm' }
2462 static xtensa_arg_internal Iclass_xt_iclass_movsp_args
[] = {
2463 { { OPERAND_art
}, 'o' },
2464 { { OPERAND_ars
}, 'i' }
2467 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs
[] = {
2468 { { STATE_WindowBase
}, 'i' },
2469 { { STATE_WindowStart
}, 'i' }
2472 static xtensa_arg_internal Iclass_xt_iclass_rotw_args
[] = {
2473 { { OPERAND_simm4
}, 'i' }
2476 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs
[] = {
2477 { { STATE_PSEXCM
}, 'i' },
2478 { { STATE_PSRING
}, 'i' },
2479 { { STATE_WindowBase
}, 'm' }
2482 static xtensa_arg_internal Iclass_xt_iclass_retw_args
[] = {
2483 { { OPERAND__ars_invisible
}, 'i' }
2486 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs
[] = {
2487 { { STATE_WindowBase
}, 'm' },
2488 { { STATE_WindowStart
}, 'm' },
2489 { { STATE_PSEXCM
}, 'i' },
2490 { { STATE_PSWOE
}, 'i' }
2493 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs
[] = {
2494 { { STATE_EPC1
}, 'i' },
2495 { { STATE_PSEXCM
}, 'm' },
2496 { { STATE_PSRING
}, 'i' },
2497 { { STATE_WindowBase
}, 'm' },
2498 { { STATE_WindowStart
}, 'm' },
2499 { { STATE_PSOWB
}, 'i' }
2502 static xtensa_arg_internal Iclass_xt_iclass_l32e_args
[] = {
2503 { { OPERAND_art
}, 'o' },
2504 { { OPERAND_ars
}, 'i' },
2505 { { OPERAND_immrx4
}, 'i' }
2508 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs
[] = {
2509 { { STATE_PSEXCM
}, 'i' },
2510 { { STATE_PSRING
}, 'i' }
2513 static xtensa_arg_internal Iclass_xt_iclass_s32e_args
[] = {
2514 { { OPERAND_art
}, 'i' },
2515 { { OPERAND_ars
}, 'i' },
2516 { { OPERAND_immrx4
}, 'i' }
2519 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs
[] = {
2520 { { STATE_PSEXCM
}, 'i' },
2521 { { STATE_PSRING
}, 'i' }
2524 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args
[] = {
2525 { { OPERAND_art
}, 'o' }
2528 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs
[] = {
2529 { { STATE_PSEXCM
}, 'i' },
2530 { { STATE_PSRING
}, 'i' },
2531 { { STATE_WindowBase
}, 'i' }
2534 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args
[] = {
2535 { { OPERAND_art
}, 'i' }
2538 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs
[] = {
2539 { { STATE_PSEXCM
}, 'i' },
2540 { { STATE_PSRING
}, 'i' },
2541 { { STATE_WindowBase
}, 'o' }
2544 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args
[] = {
2545 { { OPERAND_art
}, 'm' }
2548 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs
[] = {
2549 { { STATE_PSEXCM
}, 'i' },
2550 { { STATE_PSRING
}, 'i' },
2551 { { STATE_WindowBase
}, 'm' }
2554 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args
[] = {
2555 { { OPERAND_art
}, 'o' }
2558 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs
[] = {
2559 { { STATE_PSEXCM
}, 'i' },
2560 { { STATE_PSRING
}, 'i' },
2561 { { STATE_WindowStart
}, 'i' }
2564 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args
[] = {
2565 { { OPERAND_art
}, 'i' }
2568 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs
[] = {
2569 { { STATE_PSEXCM
}, 'i' },
2570 { { STATE_PSRING
}, 'i' },
2571 { { STATE_WindowStart
}, 'o' }
2574 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args
[] = {
2575 { { OPERAND_art
}, 'm' }
2578 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs
[] = {
2579 { { STATE_PSEXCM
}, 'i' },
2580 { { STATE_PSRING
}, 'i' },
2581 { { STATE_WindowStart
}, 'm' }
2584 static xtensa_arg_internal Iclass_xt_iclass_add_n_args
[] = {
2585 { { OPERAND_arr
}, 'o' },
2586 { { OPERAND_ars
}, 'i' },
2587 { { OPERAND_art
}, 'i' }
2590 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args
[] = {
2591 { { OPERAND_arr
}, 'o' },
2592 { { OPERAND_ars
}, 'i' },
2593 { { OPERAND_ai4const
}, 'i' }
2596 static xtensa_arg_internal Iclass_xt_iclass_bz6_args
[] = {
2597 { { OPERAND_ars
}, 'i' },
2598 { { OPERAND_uimm6
}, 'i' }
2601 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args
[] = {
2602 { { OPERAND_art
}, 'o' },
2603 { { OPERAND_ars
}, 'i' },
2604 { { OPERAND_lsi4x4
}, 'i' }
2607 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args
[] = {
2608 { { OPERAND_art
}, 'o' },
2609 { { OPERAND_ars
}, 'i' }
2612 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args
[] = {
2613 { { OPERAND_ars
}, 'o' },
2614 { { OPERAND_simm7
}, 'i' }
2617 static xtensa_arg_internal Iclass_xt_iclass_retn_args
[] = {
2618 { { OPERAND__ars_invisible
}, 'i' }
2621 static xtensa_arg_internal Iclass_xt_iclass_storei4_args
[] = {
2622 { { OPERAND_art
}, 'i' },
2623 { { OPERAND_ars
}, 'i' },
2624 { { OPERAND_lsi4x4
}, 'i' }
2627 static xtensa_arg_internal Iclass_xt_iclass_addi_args
[] = {
2628 { { OPERAND_art
}, 'o' },
2629 { { OPERAND_ars
}, 'i' },
2630 { { OPERAND_simm8
}, 'i' }
2633 static xtensa_arg_internal Iclass_xt_iclass_addmi_args
[] = {
2634 { { OPERAND_art
}, 'o' },
2635 { { OPERAND_ars
}, 'i' },
2636 { { OPERAND_simm8x256
}, 'i' }
2639 static xtensa_arg_internal Iclass_xt_iclass_addsub_args
[] = {
2640 { { OPERAND_arr
}, 'o' },
2641 { { OPERAND_ars
}, 'i' },
2642 { { OPERAND_art
}, 'i' }
2645 static xtensa_arg_internal Iclass_xt_iclass_bit_args
[] = {
2646 { { OPERAND_arr
}, 'o' },
2647 { { OPERAND_ars
}, 'i' },
2648 { { OPERAND_art
}, 'i' }
2651 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args
[] = {
2652 { { OPERAND_ars
}, 'i' },
2653 { { OPERAND_b4const
}, 'i' },
2654 { { OPERAND_label8
}, 'i' }
2657 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args
[] = {
2658 { { OPERAND_ars
}, 'i' },
2659 { { OPERAND_bbi
}, 'i' },
2660 { { OPERAND_label8
}, 'i' }
2663 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args
[] = {
2664 { { OPERAND_ars
}, 'i' },
2665 { { OPERAND_b4constu
}, 'i' },
2666 { { OPERAND_label8
}, 'i' }
2669 static xtensa_arg_internal Iclass_xt_iclass_bst8_args
[] = {
2670 { { OPERAND_ars
}, 'i' },
2671 { { OPERAND_art
}, 'i' },
2672 { { OPERAND_label8
}, 'i' }
2675 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args
[] = {
2676 { { OPERAND_ars
}, 'i' },
2677 { { OPERAND_label12
}, 'i' }
2680 static xtensa_arg_internal Iclass_xt_iclass_call0_args
[] = {
2681 { { OPERAND_soffsetx4
}, 'i' },
2682 { { OPERAND_ar0
}, 'o' }
2685 static xtensa_arg_internal Iclass_xt_iclass_callx0_args
[] = {
2686 { { OPERAND_ars
}, 'i' },
2687 { { OPERAND_ar0
}, 'o' }
2690 static xtensa_arg_internal Iclass_xt_iclass_exti_args
[] = {
2691 { { OPERAND_arr
}, 'o' },
2692 { { OPERAND_art
}, 'i' },
2693 { { OPERAND_sae
}, 'i' },
2694 { { OPERAND_op2p1
}, 'i' }
2697 static xtensa_arg_internal Iclass_xt_iclass_jump_args
[] = {
2698 { { OPERAND_soffset
}, 'i' }
2701 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args
[] = {
2702 { { OPERAND_ars
}, 'i' }
2705 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args
[] = {
2706 { { OPERAND_art
}, 'o' },
2707 { { OPERAND_ars
}, 'i' },
2708 { { OPERAND_uimm8x2
}, 'i' }
2711 static xtensa_arg_internal Iclass_xt_iclass_l16si_args
[] = {
2712 { { OPERAND_art
}, 'o' },
2713 { { OPERAND_ars
}, 'i' },
2714 { { OPERAND_uimm8x2
}, 'i' }
2717 static xtensa_arg_internal Iclass_xt_iclass_l32i_args
[] = {
2718 { { OPERAND_art
}, 'o' },
2719 { { OPERAND_ars
}, 'i' },
2720 { { OPERAND_uimm8x4
}, 'i' }
2723 static xtensa_arg_internal Iclass_xt_iclass_l32r_args
[] = {
2724 { { OPERAND_art
}, 'o' },
2725 { { OPERAND_uimm16x4
}, 'i' }
2728 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs
[] = {
2729 { { STATE_LITBADDR
}, 'i' },
2730 { { STATE_LITBEN
}, 'i' }
2733 static xtensa_arg_internal Iclass_xt_iclass_l8i_args
[] = {
2734 { { OPERAND_art
}, 'o' },
2735 { { OPERAND_ars
}, 'i' },
2736 { { OPERAND_uimm8
}, 'i' }
2739 static xtensa_arg_internal Iclass_xt_iclass_loop_args
[] = {
2740 { { OPERAND_ars
}, 'i' },
2741 { { OPERAND_ulabel8
}, 'i' }
2744 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs
[] = {
2745 { { STATE_LBEG
}, 'o' },
2746 { { STATE_LEND
}, 'o' },
2747 { { STATE_LCOUNT
}, 'o' }
2750 static xtensa_arg_internal Iclass_xt_iclass_loopz_args
[] = {
2751 { { OPERAND_ars
}, 'i' },
2752 { { OPERAND_ulabel8
}, 'i' }
2755 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs
[] = {
2756 { { STATE_LBEG
}, 'o' },
2757 { { STATE_LEND
}, 'o' },
2758 { { STATE_LCOUNT
}, 'o' }
2761 static xtensa_arg_internal Iclass_xt_iclass_movi_args
[] = {
2762 { { OPERAND_art
}, 'o' },
2763 { { OPERAND_simm12b
}, 'i' }
2766 static xtensa_arg_internal Iclass_xt_iclass_movz_args
[] = {
2767 { { OPERAND_arr
}, 'm' },
2768 { { OPERAND_ars
}, 'i' },
2769 { { OPERAND_art
}, 'i' }
2772 static xtensa_arg_internal Iclass_xt_iclass_neg_args
[] = {
2773 { { OPERAND_arr
}, 'o' },
2774 { { OPERAND_art
}, 'i' }
2777 static xtensa_arg_internal Iclass_xt_iclass_return_args
[] = {
2778 { { OPERAND__ars_invisible
}, 'i' }
2781 static xtensa_arg_internal Iclass_xt_iclass_s16i_args
[] = {
2782 { { OPERAND_art
}, 'i' },
2783 { { OPERAND_ars
}, 'i' },
2784 { { OPERAND_uimm8x2
}, 'i' }
2787 static xtensa_arg_internal Iclass_xt_iclass_s32i_args
[] = {
2788 { { OPERAND_art
}, 'i' },
2789 { { OPERAND_ars
}, 'i' },
2790 { { OPERAND_uimm8x4
}, 'i' }
2793 static xtensa_arg_internal Iclass_xt_iclass_s8i_args
[] = {
2794 { { OPERAND_art
}, 'i' },
2795 { { OPERAND_ars
}, 'i' },
2796 { { OPERAND_uimm8
}, 'i' }
2799 static xtensa_arg_internal Iclass_xt_iclass_sar_args
[] = {
2800 { { OPERAND_ars
}, 'i' }
2803 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs
[] = {
2804 { { STATE_SAR
}, 'o' }
2807 static xtensa_arg_internal Iclass_xt_iclass_sari_args
[] = {
2808 { { OPERAND_sas
}, 'i' }
2811 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs
[] = {
2812 { { STATE_SAR
}, 'o' }
2815 static xtensa_arg_internal Iclass_xt_iclass_shifts_args
[] = {
2816 { { OPERAND_arr
}, 'o' },
2817 { { OPERAND_ars
}, 'i' }
2820 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs
[] = {
2821 { { STATE_SAR
}, 'i' }
2824 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args
[] = {
2825 { { OPERAND_arr
}, 'o' },
2826 { { OPERAND_ars
}, 'i' },
2827 { { OPERAND_art
}, 'i' }
2830 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs
[] = {
2831 { { STATE_SAR
}, 'i' }
2834 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args
[] = {
2835 { { OPERAND_arr
}, 'o' },
2836 { { OPERAND_art
}, 'i' }
2839 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs
[] = {
2840 { { STATE_SAR
}, 'i' }
2843 static xtensa_arg_internal Iclass_xt_iclass_slli_args
[] = {
2844 { { OPERAND_arr
}, 'o' },
2845 { { OPERAND_ars
}, 'i' },
2846 { { OPERAND_msalp32
}, 'i' }
2849 static xtensa_arg_internal Iclass_xt_iclass_srai_args
[] = {
2850 { { OPERAND_arr
}, 'o' },
2851 { { OPERAND_art
}, 'i' },
2852 { { OPERAND_sargt
}, 'i' }
2855 static xtensa_arg_internal Iclass_xt_iclass_srli_args
[] = {
2856 { { OPERAND_arr
}, 'o' },
2857 { { OPERAND_art
}, 'i' },
2858 { { OPERAND_s
}, 'i' }
2861 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs
[] = {
2862 { { STATE_XTSYNC
}, 'i' }
2865 static xtensa_arg_internal Iclass_xt_iclass_rsil_args
[] = {
2866 { { OPERAND_art
}, 'o' },
2867 { { OPERAND_s
}, 'i' }
2870 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs
[] = {
2871 { { STATE_PSWOE
}, 'i' },
2872 { { STATE_PSCALLINC
}, 'i' },
2873 { { STATE_PSOWB
}, 'i' },
2874 { { STATE_PSRING
}, 'i' },
2875 { { STATE_PSUM
}, 'i' },
2876 { { STATE_PSEXCM
}, 'i' },
2877 { { STATE_PSINTLEVEL
}, 'm' }
2880 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args
[] = {
2881 { { OPERAND_art
}, 'o' }
2884 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs
[] = {
2885 { { STATE_LEND
}, 'i' }
2888 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args
[] = {
2889 { { OPERAND_art
}, 'i' }
2892 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs
[] = {
2893 { { STATE_LEND
}, 'o' }
2896 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args
[] = {
2897 { { OPERAND_art
}, 'm' }
2900 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs
[] = {
2901 { { STATE_LEND
}, 'm' }
2904 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args
[] = {
2905 { { OPERAND_art
}, 'o' }
2908 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs
[] = {
2909 { { STATE_LCOUNT
}, 'i' }
2912 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args
[] = {
2913 { { OPERAND_art
}, 'i' }
2916 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs
[] = {
2917 { { STATE_XTSYNC
}, 'o' },
2918 { { STATE_LCOUNT
}, 'o' }
2921 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args
[] = {
2922 { { OPERAND_art
}, 'm' }
2925 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs
[] = {
2926 { { STATE_XTSYNC
}, 'o' },
2927 { { STATE_LCOUNT
}, 'm' }
2930 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args
[] = {
2931 { { OPERAND_art
}, 'o' }
2934 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs
[] = {
2935 { { STATE_LBEG
}, 'i' }
2938 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args
[] = {
2939 { { OPERAND_art
}, 'i' }
2942 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs
[] = {
2943 { { STATE_LBEG
}, 'o' }
2946 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args
[] = {
2947 { { OPERAND_art
}, 'm' }
2950 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs
[] = {
2951 { { STATE_LBEG
}, 'm' }
2954 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args
[] = {
2955 { { OPERAND_art
}, 'o' }
2958 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs
[] = {
2959 { { STATE_SAR
}, 'i' }
2962 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args
[] = {
2963 { { OPERAND_art
}, 'i' }
2966 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs
[] = {
2967 { { STATE_SAR
}, 'o' },
2968 { { STATE_XTSYNC
}, 'o' }
2971 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args
[] = {
2972 { { OPERAND_art
}, 'm' }
2975 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs
[] = {
2976 { { STATE_SAR
}, 'm' }
2979 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args
[] = {
2980 { { OPERAND_art
}, 'o' }
2983 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs
[] = {
2984 { { STATE_LITBADDR
}, 'i' },
2985 { { STATE_LITBEN
}, 'i' }
2988 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args
[] = {
2989 { { OPERAND_art
}, 'i' }
2992 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs
[] = {
2993 { { STATE_LITBADDR
}, 'o' },
2994 { { STATE_LITBEN
}, 'o' }
2997 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args
[] = {
2998 { { OPERAND_art
}, 'm' }
3001 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs
[] = {
3002 { { STATE_LITBADDR
}, 'm' },
3003 { { STATE_LITBEN
}, 'm' }
3006 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args
[] = {
3007 { { OPERAND_art
}, 'o' }
3010 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs
[] = {
3011 { { STATE_PSEXCM
}, 'i' },
3012 { { STATE_PSRING
}, 'i' }
3015 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args
[] = {
3016 { { OPERAND_art
}, 'o' }
3019 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs
[] = {
3020 { { STATE_PSEXCM
}, 'i' },
3021 { { STATE_PSRING
}, 'i' }
3024 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args
[] = {
3025 { { OPERAND_art
}, 'o' }
3028 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs
[] = {
3029 { { STATE_PSWOE
}, 'i' },
3030 { { STATE_PSCALLINC
}, 'i' },
3031 { { STATE_PSOWB
}, 'i' },
3032 { { STATE_PSRING
}, 'i' },
3033 { { STATE_PSUM
}, 'i' },
3034 { { STATE_PSEXCM
}, 'i' },
3035 { { STATE_PSINTLEVEL
}, 'i' }
3038 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args
[] = {
3039 { { OPERAND_art
}, 'i' }
3042 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs
[] = {
3043 { { STATE_PSWOE
}, 'o' },
3044 { { STATE_PSCALLINC
}, 'o' },
3045 { { STATE_PSOWB
}, 'o' },
3046 { { STATE_PSRING
}, 'm' },
3047 { { STATE_PSUM
}, 'o' },
3048 { { STATE_PSEXCM
}, 'm' },
3049 { { STATE_PSINTLEVEL
}, 'o' }
3052 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args
[] = {
3053 { { OPERAND_art
}, 'm' }
3056 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs
[] = {
3057 { { STATE_PSWOE
}, 'm' },
3058 { { STATE_PSCALLINC
}, 'm' },
3059 { { STATE_PSOWB
}, 'm' },
3060 { { STATE_PSRING
}, 'm' },
3061 { { STATE_PSUM
}, 'm' },
3062 { { STATE_PSEXCM
}, 'm' },
3063 { { STATE_PSINTLEVEL
}, 'm' }
3066 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args
[] = {
3067 { { OPERAND_art
}, 'o' }
3070 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs
[] = {
3071 { { STATE_PSEXCM
}, 'i' },
3072 { { STATE_PSRING
}, 'i' },
3073 { { STATE_EPC1
}, 'i' }
3076 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args
[] = {
3077 { { OPERAND_art
}, 'i' }
3080 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs
[] = {
3081 { { STATE_PSEXCM
}, 'i' },
3082 { { STATE_PSRING
}, 'i' },
3083 { { STATE_EPC1
}, 'o' }
3086 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args
[] = {
3087 { { OPERAND_art
}, 'm' }
3090 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs
[] = {
3091 { { STATE_PSEXCM
}, 'i' },
3092 { { STATE_PSRING
}, 'i' },
3093 { { STATE_EPC1
}, 'm' }
3096 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args
[] = {
3097 { { OPERAND_art
}, 'o' }
3100 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs
[] = {
3101 { { STATE_PSEXCM
}, 'i' },
3102 { { STATE_PSRING
}, 'i' },
3103 { { STATE_EXCSAVE1
}, 'i' }
3106 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args
[] = {
3107 { { OPERAND_art
}, 'i' }
3110 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs
[] = {
3111 { { STATE_PSEXCM
}, 'i' },
3112 { { STATE_PSRING
}, 'i' },
3113 { { STATE_EXCSAVE1
}, 'o' }
3116 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args
[] = {
3117 { { OPERAND_art
}, 'm' }
3120 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs
[] = {
3121 { { STATE_PSEXCM
}, 'i' },
3122 { { STATE_PSRING
}, 'i' },
3123 { { STATE_EXCSAVE1
}, 'm' }
3126 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args
[] = {
3127 { { OPERAND_art
}, 'o' }
3130 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs
[] = {
3131 { { STATE_PSEXCM
}, 'i' },
3132 { { STATE_PSRING
}, 'i' },
3133 { { STATE_EPC2
}, 'i' }
3136 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args
[] = {
3137 { { OPERAND_art
}, 'i' }
3140 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs
[] = {
3141 { { STATE_PSEXCM
}, 'i' },
3142 { { STATE_PSRING
}, 'i' },
3143 { { STATE_EPC2
}, 'o' }
3146 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args
[] = {
3147 { { OPERAND_art
}, 'm' }
3150 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs
[] = {
3151 { { STATE_PSEXCM
}, 'i' },
3152 { { STATE_PSRING
}, 'i' },
3153 { { STATE_EPC2
}, 'm' }
3156 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args
[] = {
3157 { { OPERAND_art
}, 'o' }
3160 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs
[] = {
3161 { { STATE_PSEXCM
}, 'i' },
3162 { { STATE_PSRING
}, 'i' },
3163 { { STATE_EXCSAVE2
}, 'i' }
3166 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args
[] = {
3167 { { OPERAND_art
}, 'i' }
3170 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs
[] = {
3171 { { STATE_PSEXCM
}, 'i' },
3172 { { STATE_PSRING
}, 'i' },
3173 { { STATE_EXCSAVE2
}, 'o' }
3176 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args
[] = {
3177 { { OPERAND_art
}, 'm' }
3180 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs
[] = {
3181 { { STATE_PSEXCM
}, 'i' },
3182 { { STATE_PSRING
}, 'i' },
3183 { { STATE_EXCSAVE2
}, 'm' }
3186 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args
[] = {
3187 { { OPERAND_art
}, 'o' }
3190 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs
[] = {
3191 { { STATE_PSEXCM
}, 'i' },
3192 { { STATE_PSRING
}, 'i' },
3193 { { STATE_EPC3
}, 'i' }
3196 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args
[] = {
3197 { { OPERAND_art
}, 'i' }
3200 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs
[] = {
3201 { { STATE_PSEXCM
}, 'i' },
3202 { { STATE_PSRING
}, 'i' },
3203 { { STATE_EPC3
}, 'o' }
3206 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args
[] = {
3207 { { OPERAND_art
}, 'm' }
3210 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs
[] = {
3211 { { STATE_PSEXCM
}, 'i' },
3212 { { STATE_PSRING
}, 'i' },
3213 { { STATE_EPC3
}, 'm' }
3216 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args
[] = {
3217 { { OPERAND_art
}, 'o' }
3220 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs
[] = {
3221 { { STATE_PSEXCM
}, 'i' },
3222 { { STATE_PSRING
}, 'i' },
3223 { { STATE_EXCSAVE3
}, 'i' }
3226 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args
[] = {
3227 { { OPERAND_art
}, 'i' }
3230 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs
[] = {
3231 { { STATE_PSEXCM
}, 'i' },
3232 { { STATE_PSRING
}, 'i' },
3233 { { STATE_EXCSAVE3
}, 'o' }
3236 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args
[] = {
3237 { { OPERAND_art
}, 'm' }
3240 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs
[] = {
3241 { { STATE_PSEXCM
}, 'i' },
3242 { { STATE_PSRING
}, 'i' },
3243 { { STATE_EXCSAVE3
}, 'm' }
3246 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args
[] = {
3247 { { OPERAND_art
}, 'o' }
3250 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs
[] = {
3251 { { STATE_PSEXCM
}, 'i' },
3252 { { STATE_PSRING
}, 'i' },
3253 { { STATE_EPC4
}, 'i' }
3256 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args
[] = {
3257 { { OPERAND_art
}, 'i' }
3260 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs
[] = {
3261 { { STATE_PSEXCM
}, 'i' },
3262 { { STATE_PSRING
}, 'i' },
3263 { { STATE_EPC4
}, 'o' }
3266 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args
[] = {
3267 { { OPERAND_art
}, 'm' }
3270 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs
[] = {
3271 { { STATE_PSEXCM
}, 'i' },
3272 { { STATE_PSRING
}, 'i' },
3273 { { STATE_EPC4
}, 'm' }
3276 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args
[] = {
3277 { { OPERAND_art
}, 'o' }
3280 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs
[] = {
3281 { { STATE_PSEXCM
}, 'i' },
3282 { { STATE_PSRING
}, 'i' },
3283 { { STATE_EXCSAVE4
}, 'i' }
3286 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args
[] = {
3287 { { OPERAND_art
}, 'i' }
3290 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs
[] = {
3291 { { STATE_PSEXCM
}, 'i' },
3292 { { STATE_PSRING
}, 'i' },
3293 { { STATE_EXCSAVE4
}, 'o' }
3296 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args
[] = {
3297 { { OPERAND_art
}, 'm' }
3300 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs
[] = {
3301 { { STATE_PSEXCM
}, 'i' },
3302 { { STATE_PSRING
}, 'i' },
3303 { { STATE_EXCSAVE4
}, 'm' }
3306 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args
[] = {
3307 { { OPERAND_art
}, 'o' }
3310 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs
[] = {
3311 { { STATE_PSEXCM
}, 'i' },
3312 { { STATE_PSRING
}, 'i' },
3313 { { STATE_EPS2
}, 'i' }
3316 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args
[] = {
3317 { { OPERAND_art
}, 'i' }
3320 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs
[] = {
3321 { { STATE_PSEXCM
}, 'i' },
3322 { { STATE_PSRING
}, 'i' },
3323 { { STATE_EPS2
}, 'o' }
3326 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args
[] = {
3327 { { OPERAND_art
}, 'm' }
3330 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs
[] = {
3331 { { STATE_PSEXCM
}, 'i' },
3332 { { STATE_PSRING
}, 'i' },
3333 { { STATE_EPS2
}, 'm' }
3336 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args
[] = {
3337 { { OPERAND_art
}, 'o' }
3340 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs
[] = {
3341 { { STATE_PSEXCM
}, 'i' },
3342 { { STATE_PSRING
}, 'i' },
3343 { { STATE_EPS3
}, 'i' }
3346 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args
[] = {
3347 { { OPERAND_art
}, 'i' }
3350 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs
[] = {
3351 { { STATE_PSEXCM
}, 'i' },
3352 { { STATE_PSRING
}, 'i' },
3353 { { STATE_EPS3
}, 'o' }
3356 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args
[] = {
3357 { { OPERAND_art
}, 'm' }
3360 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs
[] = {
3361 { { STATE_PSEXCM
}, 'i' },
3362 { { STATE_PSRING
}, 'i' },
3363 { { STATE_EPS3
}, 'm' }
3366 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args
[] = {
3367 { { OPERAND_art
}, 'o' }
3370 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs
[] = {
3371 { { STATE_PSEXCM
}, 'i' },
3372 { { STATE_PSRING
}, 'i' },
3373 { { STATE_EPS4
}, 'i' }
3376 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args
[] = {
3377 { { OPERAND_art
}, 'i' }
3380 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs
[] = {
3381 { { STATE_PSEXCM
}, 'i' },
3382 { { STATE_PSRING
}, 'i' },
3383 { { STATE_EPS4
}, 'o' }
3386 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args
[] = {
3387 { { OPERAND_art
}, 'm' }
3390 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs
[] = {
3391 { { STATE_PSEXCM
}, 'i' },
3392 { { STATE_PSRING
}, 'i' },
3393 { { STATE_EPS4
}, 'm' }
3396 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args
[] = {
3397 { { OPERAND_art
}, 'o' }
3400 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs
[] = {
3401 { { STATE_PSEXCM
}, 'i' },
3402 { { STATE_PSRING
}, 'i' },
3403 { { STATE_EXCVADDR
}, 'i' }
3406 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args
[] = {
3407 { { OPERAND_art
}, 'i' }
3410 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs
[] = {
3411 { { STATE_PSEXCM
}, 'i' },
3412 { { STATE_PSRING
}, 'i' },
3413 { { STATE_EXCVADDR
}, 'o' }
3416 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args
[] = {
3417 { { OPERAND_art
}, 'm' }
3420 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs
[] = {
3421 { { STATE_PSEXCM
}, 'i' },
3422 { { STATE_PSRING
}, 'i' },
3423 { { STATE_EXCVADDR
}, 'm' }
3426 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args
[] = {
3427 { { OPERAND_art
}, 'o' }
3430 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs
[] = {
3431 { { STATE_PSEXCM
}, 'i' },
3432 { { STATE_PSRING
}, 'i' },
3433 { { STATE_DEPC
}, 'i' }
3436 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args
[] = {
3437 { { OPERAND_art
}, 'i' }
3440 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs
[] = {
3441 { { STATE_PSEXCM
}, 'i' },
3442 { { STATE_PSRING
}, 'i' },
3443 { { STATE_DEPC
}, 'o' }
3446 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args
[] = {
3447 { { OPERAND_art
}, 'm' }
3450 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs
[] = {
3451 { { STATE_PSEXCM
}, 'i' },
3452 { { STATE_PSRING
}, 'i' },
3453 { { STATE_DEPC
}, 'm' }
3456 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args
[] = {
3457 { { OPERAND_art
}, 'o' }
3460 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs
[] = {
3461 { { STATE_PSEXCM
}, 'i' },
3462 { { STATE_PSRING
}, 'i' },
3463 { { STATE_EXCCAUSE
}, 'i' },
3464 { { STATE_XTSYNC
}, 'i' }
3467 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args
[] = {
3468 { { OPERAND_art
}, 'i' }
3471 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs
[] = {
3472 { { STATE_PSEXCM
}, 'i' },
3473 { { STATE_PSRING
}, 'i' },
3474 { { STATE_EXCCAUSE
}, 'o' }
3477 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args
[] = {
3478 { { OPERAND_art
}, 'm' }
3481 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs
[] = {
3482 { { STATE_PSEXCM
}, 'i' },
3483 { { STATE_PSRING
}, 'i' },
3484 { { STATE_EXCCAUSE
}, 'm' }
3487 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args
[] = {
3488 { { OPERAND_art
}, 'o' }
3491 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs
[] = {
3492 { { STATE_PSEXCM
}, 'i' },
3493 { { STATE_PSRING
}, 'i' },
3494 { { STATE_MISC0
}, 'i' }
3497 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args
[] = {
3498 { { OPERAND_art
}, 'i' }
3501 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs
[] = {
3502 { { STATE_PSEXCM
}, 'i' },
3503 { { STATE_PSRING
}, 'i' },
3504 { { STATE_MISC0
}, 'o' }
3507 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args
[] = {
3508 { { OPERAND_art
}, 'm' }
3511 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs
[] = {
3512 { { STATE_PSEXCM
}, 'i' },
3513 { { STATE_PSRING
}, 'i' },
3514 { { STATE_MISC0
}, 'm' }
3517 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args
[] = {
3518 { { OPERAND_art
}, 'o' }
3521 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs
[] = {
3522 { { STATE_PSEXCM
}, 'i' },
3523 { { STATE_PSRING
}, 'i' },
3524 { { STATE_MISC1
}, 'i' }
3527 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args
[] = {
3528 { { OPERAND_art
}, 'i' }
3531 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs
[] = {
3532 { { STATE_PSEXCM
}, 'i' },
3533 { { STATE_PSRING
}, 'i' },
3534 { { STATE_MISC1
}, 'o' }
3537 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args
[] = {
3538 { { OPERAND_art
}, 'm' }
3541 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs
[] = {
3542 { { STATE_PSEXCM
}, 'i' },
3543 { { STATE_PSRING
}, 'i' },
3544 { { STATE_MISC1
}, 'm' }
3547 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args
[] = {
3548 { { OPERAND_art
}, 'o' }
3551 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs
[] = {
3552 { { STATE_PSEXCM
}, 'i' },
3553 { { STATE_PSRING
}, 'i' }
3556 static xtensa_arg_internal Iclass_xt_iclass_rfi_args
[] = {
3557 { { OPERAND_s
}, 'i' }
3560 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs
[] = {
3561 { { STATE_PSWOE
}, 'o' },
3562 { { STATE_PSCALLINC
}, 'o' },
3563 { { STATE_PSOWB
}, 'o' },
3564 { { STATE_PSRING
}, 'm' },
3565 { { STATE_PSUM
}, 'o' },
3566 { { STATE_PSEXCM
}, 'm' },
3567 { { STATE_PSINTLEVEL
}, 'o' },
3568 { { STATE_EPC1
}, 'i' },
3569 { { STATE_EPC2
}, 'i' },
3570 { { STATE_EPC3
}, 'i' },
3571 { { STATE_EPC4
}, 'i' },
3572 { { STATE_EPS2
}, 'i' },
3573 { { STATE_EPS3
}, 'i' },
3574 { { STATE_EPS4
}, 'i' },
3575 { { STATE_InOCDMode
}, 'm' }
3578 static xtensa_arg_internal Iclass_xt_iclass_wait_args
[] = {
3579 { { OPERAND_s
}, 'i' }
3582 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs
[] = {
3583 { { STATE_PSEXCM
}, 'i' },
3584 { { STATE_PSRING
}, 'i' },
3585 { { STATE_PSINTLEVEL
}, 'o' }
3588 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args
[] = {
3589 { { OPERAND_art
}, 'o' }
3592 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs
[] = {
3593 { { STATE_PSEXCM
}, 'i' },
3594 { { STATE_PSRING
}, 'i' },
3595 { { STATE_INTERRUPT
}, 'i' }
3598 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args
[] = {
3599 { { OPERAND_art
}, 'i' }
3602 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs
[] = {
3603 { { STATE_PSEXCM
}, 'i' },
3604 { { STATE_PSRING
}, 'i' },
3605 { { STATE_XTSYNC
}, 'o' },
3606 { { STATE_INTERRUPT
}, 'm' }
3609 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args
[] = {
3610 { { OPERAND_art
}, 'i' }
3613 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs
[] = {
3614 { { STATE_PSEXCM
}, 'i' },
3615 { { STATE_PSRING
}, 'i' },
3616 { { STATE_XTSYNC
}, 'o' },
3617 { { STATE_INTERRUPT
}, 'm' }
3620 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args
[] = {
3621 { { OPERAND_art
}, 'o' }
3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs
[] = {
3625 { { STATE_PSEXCM
}, 'i' },
3626 { { STATE_PSRING
}, 'i' },
3627 { { STATE_INTENABLE
}, 'i' }
3630 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args
[] = {
3631 { { OPERAND_art
}, 'i' }
3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs
[] = {
3635 { { STATE_PSEXCM
}, 'i' },
3636 { { STATE_PSRING
}, 'i' },
3637 { { STATE_INTENABLE
}, 'o' }
3640 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args
[] = {
3641 { { OPERAND_art
}, 'm' }
3644 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs
[] = {
3645 { { STATE_PSEXCM
}, 'i' },
3646 { { STATE_PSRING
}, 'i' },
3647 { { STATE_INTENABLE
}, 'm' }
3650 static xtensa_arg_internal Iclass_xt_iclass_break_args
[] = {
3651 { { OPERAND_imms
}, 'i' },
3652 { { OPERAND_immt
}, 'i' }
3655 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs
[] = {
3656 { { STATE_PSEXCM
}, 'i' },
3657 { { STATE_PSINTLEVEL
}, 'i' }
3660 static xtensa_arg_internal Iclass_xt_iclass_break_n_args
[] = {
3661 { { OPERAND_imms
}, 'i' }
3664 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs
[] = {
3665 { { STATE_PSEXCM
}, 'i' },
3666 { { STATE_PSINTLEVEL
}, 'i' }
3669 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args
[] = {
3670 { { OPERAND_art
}, 'o' }
3673 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs
[] = {
3674 { { STATE_PSEXCM
}, 'i' },
3675 { { STATE_PSRING
}, 'i' },
3676 { { STATE_DBREAKA0
}, 'i' }
3679 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args
[] = {
3680 { { OPERAND_art
}, 'i' }
3683 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs
[] = {
3684 { { STATE_PSEXCM
}, 'i' },
3685 { { STATE_PSRING
}, 'i' },
3686 { { STATE_DBREAKA0
}, 'o' },
3687 { { STATE_XTSYNC
}, 'o' }
3690 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args
[] = {
3691 { { OPERAND_art
}, 'm' }
3694 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs
[] = {
3695 { { STATE_PSEXCM
}, 'i' },
3696 { { STATE_PSRING
}, 'i' },
3697 { { STATE_DBREAKA0
}, 'm' },
3698 { { STATE_XTSYNC
}, 'o' }
3701 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args
[] = {
3702 { { OPERAND_art
}, 'o' }
3705 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs
[] = {
3706 { { STATE_PSEXCM
}, 'i' },
3707 { { STATE_PSRING
}, 'i' },
3708 { { STATE_DBREAKC0
}, 'i' }
3711 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args
[] = {
3712 { { OPERAND_art
}, 'i' }
3715 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs
[] = {
3716 { { STATE_PSEXCM
}, 'i' },
3717 { { STATE_PSRING
}, 'i' },
3718 { { STATE_DBREAKC0
}, 'o' },
3719 { { STATE_XTSYNC
}, 'o' }
3722 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args
[] = {
3723 { { OPERAND_art
}, 'm' }
3726 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs
[] = {
3727 { { STATE_PSEXCM
}, 'i' },
3728 { { STATE_PSRING
}, 'i' },
3729 { { STATE_DBREAKC0
}, 'm' },
3730 { { STATE_XTSYNC
}, 'o' }
3733 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args
[] = {
3734 { { OPERAND_art
}, 'o' }
3737 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs
[] = {
3738 { { STATE_PSEXCM
}, 'i' },
3739 { { STATE_PSRING
}, 'i' },
3740 { { STATE_DBREAKA1
}, 'i' }
3743 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args
[] = {
3744 { { OPERAND_art
}, 'i' }
3747 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs
[] = {
3748 { { STATE_PSEXCM
}, 'i' },
3749 { { STATE_PSRING
}, 'i' },
3750 { { STATE_DBREAKA1
}, 'o' },
3751 { { STATE_XTSYNC
}, 'o' }
3754 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args
[] = {
3755 { { OPERAND_art
}, 'm' }
3758 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs
[] = {
3759 { { STATE_PSEXCM
}, 'i' },
3760 { { STATE_PSRING
}, 'i' },
3761 { { STATE_DBREAKA1
}, 'm' },
3762 { { STATE_XTSYNC
}, 'o' }
3765 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args
[] = {
3766 { { OPERAND_art
}, 'o' }
3769 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs
[] = {
3770 { { STATE_PSEXCM
}, 'i' },
3771 { { STATE_PSRING
}, 'i' },
3772 { { STATE_DBREAKC1
}, 'i' }
3775 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args
[] = {
3776 { { OPERAND_art
}, 'i' }
3779 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs
[] = {
3780 { { STATE_PSEXCM
}, 'i' },
3781 { { STATE_PSRING
}, 'i' },
3782 { { STATE_DBREAKC1
}, 'o' },
3783 { { STATE_XTSYNC
}, 'o' }
3786 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args
[] = {
3787 { { OPERAND_art
}, 'm' }
3790 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs
[] = {
3791 { { STATE_PSEXCM
}, 'i' },
3792 { { STATE_PSRING
}, 'i' },
3793 { { STATE_DBREAKC1
}, 'm' },
3794 { { STATE_XTSYNC
}, 'o' }
3797 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args
[] = {
3798 { { OPERAND_art
}, 'o' }
3801 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs
[] = {
3802 { { STATE_PSEXCM
}, 'i' },
3803 { { STATE_PSRING
}, 'i' },
3804 { { STATE_IBREAKA0
}, 'i' }
3807 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args
[] = {
3808 { { OPERAND_art
}, 'i' }
3811 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs
[] = {
3812 { { STATE_PSEXCM
}, 'i' },
3813 { { STATE_PSRING
}, 'i' },
3814 { { STATE_IBREAKA0
}, 'o' }
3817 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args
[] = {
3818 { { OPERAND_art
}, 'm' }
3821 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs
[] = {
3822 { { STATE_PSEXCM
}, 'i' },
3823 { { STATE_PSRING
}, 'i' },
3824 { { STATE_IBREAKA0
}, 'm' }
3827 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args
[] = {
3828 { { OPERAND_art
}, 'o' }
3831 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs
[] = {
3832 { { STATE_PSEXCM
}, 'i' },
3833 { { STATE_PSRING
}, 'i' },
3834 { { STATE_IBREAKA1
}, 'i' }
3837 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args
[] = {
3838 { { OPERAND_art
}, 'i' }
3841 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs
[] = {
3842 { { STATE_PSEXCM
}, 'i' },
3843 { { STATE_PSRING
}, 'i' },
3844 { { STATE_IBREAKA1
}, 'o' }
3847 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args
[] = {
3848 { { OPERAND_art
}, 'm' }
3851 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs
[] = {
3852 { { STATE_PSEXCM
}, 'i' },
3853 { { STATE_PSRING
}, 'i' },
3854 { { STATE_IBREAKA1
}, 'm' }
3857 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args
[] = {
3858 { { OPERAND_art
}, 'o' }
3861 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs
[] = {
3862 { { STATE_PSEXCM
}, 'i' },
3863 { { STATE_PSRING
}, 'i' },
3864 { { STATE_IBREAKENABLE
}, 'i' }
3867 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args
[] = {
3868 { { OPERAND_art
}, 'i' }
3871 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs
[] = {
3872 { { STATE_PSEXCM
}, 'i' },
3873 { { STATE_PSRING
}, 'i' },
3874 { { STATE_IBREAKENABLE
}, 'o' }
3877 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args
[] = {
3878 { { OPERAND_art
}, 'm' }
3881 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs
[] = {
3882 { { STATE_PSEXCM
}, 'i' },
3883 { { STATE_PSRING
}, 'i' },
3884 { { STATE_IBREAKENABLE
}, 'm' }
3887 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args
[] = {
3888 { { OPERAND_art
}, 'o' }
3891 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs
[] = {
3892 { { STATE_PSEXCM
}, 'i' },
3893 { { STATE_PSRING
}, 'i' },
3894 { { STATE_DEBUGCAUSE
}, 'i' },
3895 { { STATE_DBNUM
}, 'i' }
3898 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args
[] = {
3899 { { OPERAND_art
}, 'i' }
3902 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs
[] = {
3903 { { STATE_PSEXCM
}, 'i' },
3904 { { STATE_PSRING
}, 'i' },
3905 { { STATE_DEBUGCAUSE
}, 'o' },
3906 { { STATE_DBNUM
}, 'o' }
3909 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args
[] = {
3910 { { OPERAND_art
}, 'm' }
3913 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs
[] = {
3914 { { STATE_PSEXCM
}, 'i' },
3915 { { STATE_PSRING
}, 'i' },
3916 { { STATE_DEBUGCAUSE
}, 'm' },
3917 { { STATE_DBNUM
}, 'm' }
3920 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args
[] = {
3921 { { OPERAND_art
}, 'o' }
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs
[] = {
3925 { { STATE_PSEXCM
}, 'i' },
3926 { { STATE_PSRING
}, 'i' },
3927 { { STATE_ICOUNT
}, 'i' }
3930 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args
[] = {
3931 { { OPERAND_art
}, 'i' }
3934 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs
[] = {
3935 { { STATE_PSEXCM
}, 'i' },
3936 { { STATE_PSRING
}, 'i' },
3937 { { STATE_XTSYNC
}, 'o' },
3938 { { STATE_ICOUNT
}, 'o' }
3941 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args
[] = {
3942 { { OPERAND_art
}, 'm' }
3945 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs
[] = {
3946 { { STATE_PSEXCM
}, 'i' },
3947 { { STATE_PSRING
}, 'i' },
3948 { { STATE_XTSYNC
}, 'o' },
3949 { { STATE_ICOUNT
}, 'm' }
3952 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args
[] = {
3953 { { OPERAND_art
}, 'o' }
3956 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs
[] = {
3957 { { STATE_PSEXCM
}, 'i' },
3958 { { STATE_PSRING
}, 'i' },
3959 { { STATE_ICOUNTLEVEL
}, 'i' }
3962 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args
[] = {
3963 { { OPERAND_art
}, 'i' }
3966 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs
[] = {
3967 { { STATE_PSEXCM
}, 'i' },
3968 { { STATE_PSRING
}, 'i' },
3969 { { STATE_ICOUNTLEVEL
}, 'o' }
3972 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args
[] = {
3973 { { OPERAND_art
}, 'm' }
3976 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs
[] = {
3977 { { STATE_PSEXCM
}, 'i' },
3978 { { STATE_PSRING
}, 'i' },
3979 { { STATE_ICOUNTLEVEL
}, 'm' }
3982 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args
[] = {
3983 { { OPERAND_art
}, 'o' }
3986 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs
[] = {
3987 { { STATE_PSEXCM
}, 'i' },
3988 { { STATE_PSRING
}, 'i' },
3989 { { STATE_DDR
}, 'i' }
3992 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args
[] = {
3993 { { OPERAND_art
}, 'i' }
3996 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs
[] = {
3997 { { STATE_PSEXCM
}, 'i' },
3998 { { STATE_PSRING
}, 'i' },
3999 { { STATE_XTSYNC
}, 'o' },
4000 { { STATE_DDR
}, 'o' }
4003 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args
[] = {
4004 { { OPERAND_art
}, 'm' }
4007 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs
[] = {
4008 { { STATE_PSEXCM
}, 'i' },
4009 { { STATE_PSRING
}, 'i' },
4010 { { STATE_XTSYNC
}, 'o' },
4011 { { STATE_DDR
}, 'm' }
4014 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs
[] = {
4015 { { STATE_InOCDMode
}, 'm' },
4016 { { STATE_EPC4
}, 'i' },
4017 { { STATE_PSWOE
}, 'o' },
4018 { { STATE_PSCALLINC
}, 'o' },
4019 { { STATE_PSOWB
}, 'o' },
4020 { { STATE_PSRING
}, 'o' },
4021 { { STATE_PSUM
}, 'o' },
4022 { { STATE_PSEXCM
}, 'o' },
4023 { { STATE_PSINTLEVEL
}, 'o' },
4024 { { STATE_EPS4
}, 'i' }
4027 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs
[] = {
4028 { { STATE_InOCDMode
}, 'm' }
4031 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args
[] = {
4032 { { OPERAND_art
}, 'o' }
4035 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs
[] = {
4036 { { STATE_PSEXCM
}, 'i' },
4037 { { STATE_PSRING
}, 'i' },
4038 { { STATE_CCOUNT
}, 'i' }
4041 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args
[] = {
4042 { { OPERAND_art
}, 'i' }
4045 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs
[] = {
4046 { { STATE_PSEXCM
}, 'i' },
4047 { { STATE_PSRING
}, 'i' },
4048 { { STATE_XTSYNC
}, 'o' },
4049 { { STATE_CCOUNT
}, 'o' }
4052 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args
[] = {
4053 { { OPERAND_art
}, 'm' }
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs
[] = {
4057 { { STATE_PSEXCM
}, 'i' },
4058 { { STATE_PSRING
}, 'i' },
4059 { { STATE_XTSYNC
}, 'o' },
4060 { { STATE_CCOUNT
}, 'm' }
4063 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args
[] = {
4064 { { OPERAND_art
}, 'o' }
4067 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs
[] = {
4068 { { STATE_PSEXCM
}, 'i' },
4069 { { STATE_PSRING
}, 'i' },
4070 { { STATE_CCOMPARE0
}, 'i' }
4073 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args
[] = {
4074 { { OPERAND_art
}, 'i' }
4077 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs
[] = {
4078 { { STATE_PSEXCM
}, 'i' },
4079 { { STATE_PSRING
}, 'i' },
4080 { { STATE_CCOMPARE0
}, 'o' },
4081 { { STATE_INTERRUPT
}, 'm' }
4084 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args
[] = {
4085 { { OPERAND_art
}, 'm' }
4088 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs
[] = {
4089 { { STATE_PSEXCM
}, 'i' },
4090 { { STATE_PSRING
}, 'i' },
4091 { { STATE_CCOMPARE0
}, 'm' },
4092 { { STATE_INTERRUPT
}, 'm' }
4095 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args
[] = {
4096 { { OPERAND_art
}, 'o' }
4099 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs
[] = {
4100 { { STATE_PSEXCM
}, 'i' },
4101 { { STATE_PSRING
}, 'i' },
4102 { { STATE_CCOMPARE1
}, 'i' }
4105 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args
[] = {
4106 { { OPERAND_art
}, 'i' }
4109 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs
[] = {
4110 { { STATE_PSEXCM
}, 'i' },
4111 { { STATE_PSRING
}, 'i' },
4112 { { STATE_CCOMPARE1
}, 'o' },
4113 { { STATE_INTERRUPT
}, 'm' }
4116 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args
[] = {
4117 { { OPERAND_art
}, 'm' }
4120 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs
[] = {
4121 { { STATE_PSEXCM
}, 'i' },
4122 { { STATE_PSRING
}, 'i' },
4123 { { STATE_CCOMPARE1
}, 'm' },
4124 { { STATE_INTERRUPT
}, 'm' }
4127 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args
[] = {
4128 { { OPERAND_art
}, 'o' }
4131 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs
[] = {
4132 { { STATE_PSEXCM
}, 'i' },
4133 { { STATE_PSRING
}, 'i' },
4134 { { STATE_CCOMPARE2
}, 'i' }
4137 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args
[] = {
4138 { { OPERAND_art
}, 'i' }
4141 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs
[] = {
4142 { { STATE_PSEXCM
}, 'i' },
4143 { { STATE_PSRING
}, 'i' },
4144 { { STATE_CCOMPARE2
}, 'o' },
4145 { { STATE_INTERRUPT
}, 'm' }
4148 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args
[] = {
4149 { { OPERAND_art
}, 'm' }
4152 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs
[] = {
4153 { { STATE_PSEXCM
}, 'i' },
4154 { { STATE_PSRING
}, 'i' },
4155 { { STATE_CCOMPARE2
}, 'm' },
4156 { { STATE_INTERRUPT
}, 'm' }
4159 static xtensa_arg_internal Iclass_xt_iclass_icache_args
[] = {
4160 { { OPERAND_ars
}, 'i' },
4161 { { OPERAND_uimm8x4
}, 'i' }
4164 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args
[] = {
4165 { { OPERAND_ars
}, 'i' },
4166 { { OPERAND_uimm8x4
}, 'i' }
4169 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs
[] = {
4170 { { STATE_PSEXCM
}, 'i' },
4171 { { STATE_PSRING
}, 'i' }
4174 static xtensa_arg_internal Iclass_xt_iclass_licx_args
[] = {
4175 { { OPERAND_art
}, 'o' },
4176 { { OPERAND_ars
}, 'i' }
4179 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs
[] = {
4180 { { STATE_PSEXCM
}, 'i' },
4181 { { STATE_PSRING
}, 'i' }
4184 static xtensa_arg_internal Iclass_xt_iclass_sicx_args
[] = {
4185 { { OPERAND_art
}, 'i' },
4186 { { OPERAND_ars
}, 'i' }
4189 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs
[] = {
4190 { { STATE_PSEXCM
}, 'i' },
4191 { { STATE_PSRING
}, 'i' }
4194 static xtensa_arg_internal Iclass_xt_iclass_dcache_args
[] = {
4195 { { OPERAND_ars
}, 'i' },
4196 { { OPERAND_uimm8x4
}, 'i' }
4199 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args
[] = {
4200 { { OPERAND_ars
}, 'i' },
4201 { { OPERAND_uimm4x16
}, 'i' }
4204 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs
[] = {
4205 { { STATE_PSEXCM
}, 'i' },
4206 { { STATE_PSRING
}, 'i' }
4209 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args
[] = {
4210 { { OPERAND_ars
}, 'i' },
4211 { { OPERAND_uimm8x4
}, 'i' }
4214 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs
[] = {
4215 { { STATE_PSEXCM
}, 'i' },
4216 { { STATE_PSRING
}, 'i' }
4219 static xtensa_arg_internal Iclass_xt_iclass_dpf_args
[] = {
4220 { { OPERAND_ars
}, 'i' },
4221 { { OPERAND_uimm8x4
}, 'i' }
4224 static xtensa_arg_internal Iclass_xt_iclass_sdct_args
[] = {
4225 { { OPERAND_art
}, 'i' },
4226 { { OPERAND_ars
}, 'i' }
4229 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs
[] = {
4230 { { STATE_PSEXCM
}, 'i' },
4231 { { STATE_PSRING
}, 'i' }
4234 static xtensa_arg_internal Iclass_xt_iclass_ldct_args
[] = {
4235 { { OPERAND_art
}, 'o' },
4236 { { OPERAND_ars
}, 'i' }
4239 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs
[] = {
4240 { { STATE_PSEXCM
}, 'i' },
4241 { { STATE_PSRING
}, 'i' }
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args
[] = {
4245 { { OPERAND_art
}, 'i' }
4248 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs
[] = {
4249 { { STATE_PSEXCM
}, 'i' },
4250 { { STATE_PSRING
}, 'i' },
4251 { { STATE_PTBASE
}, 'o' },
4252 { { STATE_XTSYNC
}, 'o' }
4255 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args
[] = {
4256 { { OPERAND_art
}, 'o' }
4259 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs
[] = {
4260 { { STATE_PSEXCM
}, 'i' },
4261 { { STATE_PSRING
}, 'i' },
4262 { { STATE_PTBASE
}, 'i' },
4263 { { STATE_EXCVADDR
}, 'i' }
4266 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args
[] = {
4267 { { OPERAND_art
}, 'm' }
4270 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs
[] = {
4271 { { STATE_PSEXCM
}, 'i' },
4272 { { STATE_PSRING
}, 'i' },
4273 { { STATE_PTBASE
}, 'm' },
4274 { { STATE_EXCVADDR
}, 'i' },
4275 { { STATE_XTSYNC
}, 'o' }
4278 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args
[] = {
4279 { { OPERAND_art
}, 'o' }
4282 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs
[] = {
4283 { { STATE_PSEXCM
}, 'i' },
4284 { { STATE_PSRING
}, 'i' },
4285 { { STATE_ASID3
}, 'i' },
4286 { { STATE_ASID2
}, 'i' },
4287 { { STATE_ASID1
}, 'i' }
4290 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args
[] = {
4291 { { OPERAND_art
}, 'i' }
4294 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs
[] = {
4295 { { STATE_XTSYNC
}, 'o' },
4296 { { STATE_PSEXCM
}, 'i' },
4297 { { STATE_PSRING
}, 'i' },
4298 { { STATE_ASID3
}, 'o' },
4299 { { STATE_ASID2
}, 'o' },
4300 { { STATE_ASID1
}, 'o' }
4303 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args
[] = {
4304 { { OPERAND_art
}, 'm' }
4307 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs
[] = {
4308 { { STATE_XTSYNC
}, 'o' },
4309 { { STATE_PSEXCM
}, 'i' },
4310 { { STATE_PSRING
}, 'i' },
4311 { { STATE_ASID3
}, 'm' },
4312 { { STATE_ASID2
}, 'm' },
4313 { { STATE_ASID1
}, 'm' }
4316 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args
[] = {
4317 { { OPERAND_art
}, 'o' }
4320 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs
[] = {
4321 { { STATE_PSEXCM
}, 'i' },
4322 { { STATE_PSRING
}, 'i' },
4323 { { STATE_INSTPGSZID4
}, 'i' }
4326 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args
[] = {
4327 { { OPERAND_art
}, 'i' }
4330 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs
[] = {
4331 { { STATE_XTSYNC
}, 'o' },
4332 { { STATE_PSEXCM
}, 'i' },
4333 { { STATE_PSRING
}, 'i' },
4334 { { STATE_INSTPGSZID4
}, 'o' }
4337 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args
[] = {
4338 { { OPERAND_art
}, 'm' }
4341 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs
[] = {
4342 { { STATE_XTSYNC
}, 'o' },
4343 { { STATE_PSEXCM
}, 'i' },
4344 { { STATE_PSRING
}, 'i' },
4345 { { STATE_INSTPGSZID4
}, 'm' }
4348 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args
[] = {
4349 { { OPERAND_art
}, 'o' }
4352 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs
[] = {
4353 { { STATE_PSEXCM
}, 'i' },
4354 { { STATE_PSRING
}, 'i' },
4355 { { STATE_DATAPGSZID4
}, 'i' }
4358 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args
[] = {
4359 { { OPERAND_art
}, 'i' }
4362 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs
[] = {
4363 { { STATE_XTSYNC
}, 'o' },
4364 { { STATE_PSEXCM
}, 'i' },
4365 { { STATE_PSRING
}, 'i' },
4366 { { STATE_DATAPGSZID4
}, 'o' }
4369 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args
[] = {
4370 { { OPERAND_art
}, 'm' }
4373 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs
[] = {
4374 { { STATE_XTSYNC
}, 'o' },
4375 { { STATE_PSEXCM
}, 'i' },
4376 { { STATE_PSRING
}, 'i' },
4377 { { STATE_DATAPGSZID4
}, 'm' }
4380 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args
[] = {
4381 { { OPERAND_ars
}, 'i' }
4384 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs
[] = {
4385 { { STATE_PSEXCM
}, 'i' },
4386 { { STATE_PSRING
}, 'i' },
4387 { { STATE_XTSYNC
}, 'o' }
4390 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args
[] = {
4391 { { OPERAND_art
}, 'o' },
4392 { { OPERAND_ars
}, 'i' }
4395 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs
[] = {
4396 { { STATE_PSEXCM
}, 'i' },
4397 { { STATE_PSRING
}, 'i' }
4400 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args
[] = {
4401 { { OPERAND_art
}, 'i' },
4402 { { OPERAND_ars
}, 'i' }
4405 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs
[] = {
4406 { { STATE_PSEXCM
}, 'i' },
4407 { { STATE_PSRING
}, 'i' },
4408 { { STATE_XTSYNC
}, 'o' }
4411 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args
[] = {
4412 { { OPERAND_ars
}, 'i' }
4415 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs
[] = {
4416 { { STATE_PSEXCM
}, 'i' },
4417 { { STATE_PSRING
}, 'i' }
4420 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args
[] = {
4421 { { OPERAND_art
}, 'o' },
4422 { { OPERAND_ars
}, 'i' }
4425 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs
[] = {
4426 { { STATE_PSEXCM
}, 'i' },
4427 { { STATE_PSRING
}, 'i' }
4430 static xtensa_arg_internal Iclass_xt_iclass_witlb_args
[] = {
4431 { { OPERAND_art
}, 'i' },
4432 { { OPERAND_ars
}, 'i' }
4435 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs
[] = {
4436 { { STATE_PSEXCM
}, 'i' },
4437 { { STATE_PSRING
}, 'i' }
4440 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs
[] = {
4441 { { STATE_PTBASE
}, 'i' },
4442 { { STATE_EXCVADDR
}, 'i' }
4445 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs
[] = {
4446 { { STATE_EXCVADDR
}, 'i' }
4449 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs
[] = {
4450 { { STATE_EXCVADDR
}, 'i' }
4453 static xtensa_arg_internal Iclass_xt_iclass_nsa_args
[] = {
4454 { { OPERAND_art
}, 'o' },
4455 { { OPERAND_ars
}, 'i' }
4458 static xtensa_iclass_internal iclasses
[] = {
4459 { 0, 0 /* xt_iclass_excw */,
4461 { 0, 0 /* xt_iclass_rfe */,
4462 3, Iclass_xt_iclass_rfe_stateArgs
, 0, 0 },
4463 { 0, 0 /* xt_iclass_rfde */,
4464 3, Iclass_xt_iclass_rfde_stateArgs
, 0, 0 },
4465 { 0, 0 /* xt_iclass_syscall */,
4467 { 0, 0 /* xt_iclass_simcall */,
4469 { 2, Iclass_xt_iclass_call12_args
,
4470 1, Iclass_xt_iclass_call12_stateArgs
, 0, 0 },
4471 { 2, Iclass_xt_iclass_call8_args
,
4472 1, Iclass_xt_iclass_call8_stateArgs
, 0, 0 },
4473 { 2, Iclass_xt_iclass_call4_args
,
4474 1, Iclass_xt_iclass_call4_stateArgs
, 0, 0 },
4475 { 2, Iclass_xt_iclass_callx12_args
,
4476 1, Iclass_xt_iclass_callx12_stateArgs
, 0, 0 },
4477 { 2, Iclass_xt_iclass_callx8_args
,
4478 1, Iclass_xt_iclass_callx8_stateArgs
, 0, 0 },
4479 { 2, Iclass_xt_iclass_callx4_args
,
4480 1, Iclass_xt_iclass_callx4_stateArgs
, 0, 0 },
4481 { 3, Iclass_xt_iclass_entry_args
,
4482 5, Iclass_xt_iclass_entry_stateArgs
, 0, 0 },
4483 { 2, Iclass_xt_iclass_movsp_args
,
4484 2, Iclass_xt_iclass_movsp_stateArgs
, 0, 0 },
4485 { 1, Iclass_xt_iclass_rotw_args
,
4486 3, Iclass_xt_iclass_rotw_stateArgs
, 0, 0 },
4487 { 1, Iclass_xt_iclass_retw_args
,
4488 4, Iclass_xt_iclass_retw_stateArgs
, 0, 0 },
4489 { 0, 0 /* xt_iclass_rfwou */,
4490 6, Iclass_xt_iclass_rfwou_stateArgs
, 0, 0 },
4491 { 3, Iclass_xt_iclass_l32e_args
,
4492 2, Iclass_xt_iclass_l32e_stateArgs
, 0, 0 },
4493 { 3, Iclass_xt_iclass_s32e_args
,
4494 2, Iclass_xt_iclass_s32e_stateArgs
, 0, 0 },
4495 { 1, Iclass_xt_iclass_rsr_windowbase_args
,
4496 3, Iclass_xt_iclass_rsr_windowbase_stateArgs
, 0, 0 },
4497 { 1, Iclass_xt_iclass_wsr_windowbase_args
,
4498 3, Iclass_xt_iclass_wsr_windowbase_stateArgs
, 0, 0 },
4499 { 1, Iclass_xt_iclass_xsr_windowbase_args
,
4500 3, Iclass_xt_iclass_xsr_windowbase_stateArgs
, 0, 0 },
4501 { 1, Iclass_xt_iclass_rsr_windowstart_args
,
4502 3, Iclass_xt_iclass_rsr_windowstart_stateArgs
, 0, 0 },
4503 { 1, Iclass_xt_iclass_wsr_windowstart_args
,
4504 3, Iclass_xt_iclass_wsr_windowstart_stateArgs
, 0, 0 },
4505 { 1, Iclass_xt_iclass_xsr_windowstart_args
,
4506 3, Iclass_xt_iclass_xsr_windowstart_stateArgs
, 0, 0 },
4507 { 3, Iclass_xt_iclass_add_n_args
,
4509 { 3, Iclass_xt_iclass_addi_n_args
,
4511 { 2, Iclass_xt_iclass_bz6_args
,
4513 { 0, 0 /* xt_iclass_ill_n */,
4515 { 3, Iclass_xt_iclass_loadi4_args
,
4517 { 2, Iclass_xt_iclass_mov_n_args
,
4519 { 2, Iclass_xt_iclass_movi_n_args
,
4521 { 0, 0 /* xt_iclass_nopn */,
4523 { 1, Iclass_xt_iclass_retn_args
,
4525 { 3, Iclass_xt_iclass_storei4_args
,
4527 { 3, Iclass_xt_iclass_addi_args
,
4529 { 3, Iclass_xt_iclass_addmi_args
,
4531 { 3, Iclass_xt_iclass_addsub_args
,
4533 { 3, Iclass_xt_iclass_bit_args
,
4535 { 3, Iclass_xt_iclass_bsi8_args
,
4537 { 3, Iclass_xt_iclass_bsi8b_args
,
4539 { 3, Iclass_xt_iclass_bsi8u_args
,
4541 { 3, Iclass_xt_iclass_bst8_args
,
4543 { 2, Iclass_xt_iclass_bsz12_args
,
4545 { 2, Iclass_xt_iclass_call0_args
,
4547 { 2, Iclass_xt_iclass_callx0_args
,
4549 { 4, Iclass_xt_iclass_exti_args
,
4551 { 0, 0 /* xt_iclass_ill */,
4553 { 1, Iclass_xt_iclass_jump_args
,
4555 { 1, Iclass_xt_iclass_jumpx_args
,
4557 { 3, Iclass_xt_iclass_l16ui_args
,
4559 { 3, Iclass_xt_iclass_l16si_args
,
4561 { 3, Iclass_xt_iclass_l32i_args
,
4563 { 2, Iclass_xt_iclass_l32r_args
,
4564 2, Iclass_xt_iclass_l32r_stateArgs
, 0, 0 },
4565 { 3, Iclass_xt_iclass_l8i_args
,
4567 { 2, Iclass_xt_iclass_loop_args
,
4568 3, Iclass_xt_iclass_loop_stateArgs
, 0, 0 },
4569 { 2, Iclass_xt_iclass_loopz_args
,
4570 3, Iclass_xt_iclass_loopz_stateArgs
, 0, 0 },
4571 { 2, Iclass_xt_iclass_movi_args
,
4573 { 3, Iclass_xt_iclass_movz_args
,
4575 { 2, Iclass_xt_iclass_neg_args
,
4577 { 0, 0 /* xt_iclass_nop */,
4579 { 1, Iclass_xt_iclass_return_args
,
4581 { 3, Iclass_xt_iclass_s16i_args
,
4583 { 3, Iclass_xt_iclass_s32i_args
,
4585 { 3, Iclass_xt_iclass_s8i_args
,
4587 { 1, Iclass_xt_iclass_sar_args
,
4588 1, Iclass_xt_iclass_sar_stateArgs
, 0, 0 },
4589 { 1, Iclass_xt_iclass_sari_args
,
4590 1, Iclass_xt_iclass_sari_stateArgs
, 0, 0 },
4591 { 2, Iclass_xt_iclass_shifts_args
,
4592 1, Iclass_xt_iclass_shifts_stateArgs
, 0, 0 },
4593 { 3, Iclass_xt_iclass_shiftst_args
,
4594 1, Iclass_xt_iclass_shiftst_stateArgs
, 0, 0 },
4595 { 2, Iclass_xt_iclass_shiftt_args
,
4596 1, Iclass_xt_iclass_shiftt_stateArgs
, 0, 0 },
4597 { 3, Iclass_xt_iclass_slli_args
,
4599 { 3, Iclass_xt_iclass_srai_args
,
4601 { 3, Iclass_xt_iclass_srli_args
,
4603 { 0, 0 /* xt_iclass_memw */,
4605 { 0, 0 /* xt_iclass_extw */,
4607 { 0, 0 /* xt_iclass_isync */,
4609 { 0, 0 /* xt_iclass_sync */,
4610 1, Iclass_xt_iclass_sync_stateArgs
, 0, 0 },
4611 { 2, Iclass_xt_iclass_rsil_args
,
4612 7, Iclass_xt_iclass_rsil_stateArgs
, 0, 0 },
4613 { 1, Iclass_xt_iclass_rsr_lend_args
,
4614 1, Iclass_xt_iclass_rsr_lend_stateArgs
, 0, 0 },
4615 { 1, Iclass_xt_iclass_wsr_lend_args
,
4616 1, Iclass_xt_iclass_wsr_lend_stateArgs
, 0, 0 },
4617 { 1, Iclass_xt_iclass_xsr_lend_args
,
4618 1, Iclass_xt_iclass_xsr_lend_stateArgs
, 0, 0 },
4619 { 1, Iclass_xt_iclass_rsr_lcount_args
,
4620 1, Iclass_xt_iclass_rsr_lcount_stateArgs
, 0, 0 },
4621 { 1, Iclass_xt_iclass_wsr_lcount_args
,
4622 2, Iclass_xt_iclass_wsr_lcount_stateArgs
, 0, 0 },
4623 { 1, Iclass_xt_iclass_xsr_lcount_args
,
4624 2, Iclass_xt_iclass_xsr_lcount_stateArgs
, 0, 0 },
4625 { 1, Iclass_xt_iclass_rsr_lbeg_args
,
4626 1, Iclass_xt_iclass_rsr_lbeg_stateArgs
, 0, 0 },
4627 { 1, Iclass_xt_iclass_wsr_lbeg_args
,
4628 1, Iclass_xt_iclass_wsr_lbeg_stateArgs
, 0, 0 },
4629 { 1, Iclass_xt_iclass_xsr_lbeg_args
,
4630 1, Iclass_xt_iclass_xsr_lbeg_stateArgs
, 0, 0 },
4631 { 1, Iclass_xt_iclass_rsr_sar_args
,
4632 1, Iclass_xt_iclass_rsr_sar_stateArgs
, 0, 0 },
4633 { 1, Iclass_xt_iclass_wsr_sar_args
,
4634 2, Iclass_xt_iclass_wsr_sar_stateArgs
, 0, 0 },
4635 { 1, Iclass_xt_iclass_xsr_sar_args
,
4636 1, Iclass_xt_iclass_xsr_sar_stateArgs
, 0, 0 },
4637 { 1, Iclass_xt_iclass_rsr_litbase_args
,
4638 2, Iclass_xt_iclass_rsr_litbase_stateArgs
, 0, 0 },
4639 { 1, Iclass_xt_iclass_wsr_litbase_args
,
4640 2, Iclass_xt_iclass_wsr_litbase_stateArgs
, 0, 0 },
4641 { 1, Iclass_xt_iclass_xsr_litbase_args
,
4642 2, Iclass_xt_iclass_xsr_litbase_stateArgs
, 0, 0 },
4643 { 1, Iclass_xt_iclass_rsr_176_args
,
4644 2, Iclass_xt_iclass_rsr_176_stateArgs
, 0, 0 },
4645 { 1, Iclass_xt_iclass_rsr_208_args
,
4646 2, Iclass_xt_iclass_rsr_208_stateArgs
, 0, 0 },
4647 { 1, Iclass_xt_iclass_rsr_ps_args
,
4648 7, Iclass_xt_iclass_rsr_ps_stateArgs
, 0, 0 },
4649 { 1, Iclass_xt_iclass_wsr_ps_args
,
4650 7, Iclass_xt_iclass_wsr_ps_stateArgs
, 0, 0 },
4651 { 1, Iclass_xt_iclass_xsr_ps_args
,
4652 7, Iclass_xt_iclass_xsr_ps_stateArgs
, 0, 0 },
4653 { 1, Iclass_xt_iclass_rsr_epc1_args
,
4654 3, Iclass_xt_iclass_rsr_epc1_stateArgs
, 0, 0 },
4655 { 1, Iclass_xt_iclass_wsr_epc1_args
,
4656 3, Iclass_xt_iclass_wsr_epc1_stateArgs
, 0, 0 },
4657 { 1, Iclass_xt_iclass_xsr_epc1_args
,
4658 3, Iclass_xt_iclass_xsr_epc1_stateArgs
, 0, 0 },
4659 { 1, Iclass_xt_iclass_rsr_excsave1_args
,
4660 3, Iclass_xt_iclass_rsr_excsave1_stateArgs
, 0, 0 },
4661 { 1, Iclass_xt_iclass_wsr_excsave1_args
,
4662 3, Iclass_xt_iclass_wsr_excsave1_stateArgs
, 0, 0 },
4663 { 1, Iclass_xt_iclass_xsr_excsave1_args
,
4664 3, Iclass_xt_iclass_xsr_excsave1_stateArgs
, 0, 0 },
4665 { 1, Iclass_xt_iclass_rsr_epc2_args
,
4666 3, Iclass_xt_iclass_rsr_epc2_stateArgs
, 0, 0 },
4667 { 1, Iclass_xt_iclass_wsr_epc2_args
,
4668 3, Iclass_xt_iclass_wsr_epc2_stateArgs
, 0, 0 },
4669 { 1, Iclass_xt_iclass_xsr_epc2_args
,
4670 3, Iclass_xt_iclass_xsr_epc2_stateArgs
, 0, 0 },
4671 { 1, Iclass_xt_iclass_rsr_excsave2_args
,
4672 3, Iclass_xt_iclass_rsr_excsave2_stateArgs
, 0, 0 },
4673 { 1, Iclass_xt_iclass_wsr_excsave2_args
,
4674 3, Iclass_xt_iclass_wsr_excsave2_stateArgs
, 0, 0 },
4675 { 1, Iclass_xt_iclass_xsr_excsave2_args
,
4676 3, Iclass_xt_iclass_xsr_excsave2_stateArgs
, 0, 0 },
4677 { 1, Iclass_xt_iclass_rsr_epc3_args
,
4678 3, Iclass_xt_iclass_rsr_epc3_stateArgs
, 0, 0 },
4679 { 1, Iclass_xt_iclass_wsr_epc3_args
,
4680 3, Iclass_xt_iclass_wsr_epc3_stateArgs
, 0, 0 },
4681 { 1, Iclass_xt_iclass_xsr_epc3_args
,
4682 3, Iclass_xt_iclass_xsr_epc3_stateArgs
, 0, 0 },
4683 { 1, Iclass_xt_iclass_rsr_excsave3_args
,
4684 3, Iclass_xt_iclass_rsr_excsave3_stateArgs
, 0, 0 },
4685 { 1, Iclass_xt_iclass_wsr_excsave3_args
,
4686 3, Iclass_xt_iclass_wsr_excsave3_stateArgs
, 0, 0 },
4687 { 1, Iclass_xt_iclass_xsr_excsave3_args
,
4688 3, Iclass_xt_iclass_xsr_excsave3_stateArgs
, 0, 0 },
4689 { 1, Iclass_xt_iclass_rsr_epc4_args
,
4690 3, Iclass_xt_iclass_rsr_epc4_stateArgs
, 0, 0 },
4691 { 1, Iclass_xt_iclass_wsr_epc4_args
,
4692 3, Iclass_xt_iclass_wsr_epc4_stateArgs
, 0, 0 },
4693 { 1, Iclass_xt_iclass_xsr_epc4_args
,
4694 3, Iclass_xt_iclass_xsr_epc4_stateArgs
, 0, 0 },
4695 { 1, Iclass_xt_iclass_rsr_excsave4_args
,
4696 3, Iclass_xt_iclass_rsr_excsave4_stateArgs
, 0, 0 },
4697 { 1, Iclass_xt_iclass_wsr_excsave4_args
,
4698 3, Iclass_xt_iclass_wsr_excsave4_stateArgs
, 0, 0 },
4699 { 1, Iclass_xt_iclass_xsr_excsave4_args
,
4700 3, Iclass_xt_iclass_xsr_excsave4_stateArgs
, 0, 0 },
4701 { 1, Iclass_xt_iclass_rsr_eps2_args
,
4702 3, Iclass_xt_iclass_rsr_eps2_stateArgs
, 0, 0 },
4703 { 1, Iclass_xt_iclass_wsr_eps2_args
,
4704 3, Iclass_xt_iclass_wsr_eps2_stateArgs
, 0, 0 },
4705 { 1, Iclass_xt_iclass_xsr_eps2_args
,
4706 3, Iclass_xt_iclass_xsr_eps2_stateArgs
, 0, 0 },
4707 { 1, Iclass_xt_iclass_rsr_eps3_args
,
4708 3, Iclass_xt_iclass_rsr_eps3_stateArgs
, 0, 0 },
4709 { 1, Iclass_xt_iclass_wsr_eps3_args
,
4710 3, Iclass_xt_iclass_wsr_eps3_stateArgs
, 0, 0 },
4711 { 1, Iclass_xt_iclass_xsr_eps3_args
,
4712 3, Iclass_xt_iclass_xsr_eps3_stateArgs
, 0, 0 },
4713 { 1, Iclass_xt_iclass_rsr_eps4_args
,
4714 3, Iclass_xt_iclass_rsr_eps4_stateArgs
, 0, 0 },
4715 { 1, Iclass_xt_iclass_wsr_eps4_args
,
4716 3, Iclass_xt_iclass_wsr_eps4_stateArgs
, 0, 0 },
4717 { 1, Iclass_xt_iclass_xsr_eps4_args
,
4718 3, Iclass_xt_iclass_xsr_eps4_stateArgs
, 0, 0 },
4719 { 1, Iclass_xt_iclass_rsr_excvaddr_args
,
4720 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs
, 0, 0 },
4721 { 1, Iclass_xt_iclass_wsr_excvaddr_args
,
4722 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs
, 0, 0 },
4723 { 1, Iclass_xt_iclass_xsr_excvaddr_args
,
4724 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs
, 0, 0 },
4725 { 1, Iclass_xt_iclass_rsr_depc_args
,
4726 3, Iclass_xt_iclass_rsr_depc_stateArgs
, 0, 0 },
4727 { 1, Iclass_xt_iclass_wsr_depc_args
,
4728 3, Iclass_xt_iclass_wsr_depc_stateArgs
, 0, 0 },
4729 { 1, Iclass_xt_iclass_xsr_depc_args
,
4730 3, Iclass_xt_iclass_xsr_depc_stateArgs
, 0, 0 },
4731 { 1, Iclass_xt_iclass_rsr_exccause_args
,
4732 4, Iclass_xt_iclass_rsr_exccause_stateArgs
, 0, 0 },
4733 { 1, Iclass_xt_iclass_wsr_exccause_args
,
4734 3, Iclass_xt_iclass_wsr_exccause_stateArgs
, 0, 0 },
4735 { 1, Iclass_xt_iclass_xsr_exccause_args
,
4736 3, Iclass_xt_iclass_xsr_exccause_stateArgs
, 0, 0 },
4737 { 1, Iclass_xt_iclass_rsr_misc0_args
,
4738 3, Iclass_xt_iclass_rsr_misc0_stateArgs
, 0, 0 },
4739 { 1, Iclass_xt_iclass_wsr_misc0_args
,
4740 3, Iclass_xt_iclass_wsr_misc0_stateArgs
, 0, 0 },
4741 { 1, Iclass_xt_iclass_xsr_misc0_args
,
4742 3, Iclass_xt_iclass_xsr_misc0_stateArgs
, 0, 0 },
4743 { 1, Iclass_xt_iclass_rsr_misc1_args
,
4744 3, Iclass_xt_iclass_rsr_misc1_stateArgs
, 0, 0 },
4745 { 1, Iclass_xt_iclass_wsr_misc1_args
,
4746 3, Iclass_xt_iclass_wsr_misc1_stateArgs
, 0, 0 },
4747 { 1, Iclass_xt_iclass_xsr_misc1_args
,
4748 3, Iclass_xt_iclass_xsr_misc1_stateArgs
, 0, 0 },
4749 { 1, Iclass_xt_iclass_rsr_prid_args
,
4750 2, Iclass_xt_iclass_rsr_prid_stateArgs
, 0, 0 },
4751 { 1, Iclass_xt_iclass_rfi_args
,
4752 15, Iclass_xt_iclass_rfi_stateArgs
, 0, 0 },
4753 { 1, Iclass_xt_iclass_wait_args
,
4754 3, Iclass_xt_iclass_wait_stateArgs
, 0, 0 },
4755 { 1, Iclass_xt_iclass_rsr_interrupt_args
,
4756 3, Iclass_xt_iclass_rsr_interrupt_stateArgs
, 0, 0 },
4757 { 1, Iclass_xt_iclass_wsr_intset_args
,
4758 4, Iclass_xt_iclass_wsr_intset_stateArgs
, 0, 0 },
4759 { 1, Iclass_xt_iclass_wsr_intclear_args
,
4760 4, Iclass_xt_iclass_wsr_intclear_stateArgs
, 0, 0 },
4761 { 1, Iclass_xt_iclass_rsr_intenable_args
,
4762 3, Iclass_xt_iclass_rsr_intenable_stateArgs
, 0, 0 },
4763 { 1, Iclass_xt_iclass_wsr_intenable_args
,
4764 3, Iclass_xt_iclass_wsr_intenable_stateArgs
, 0, 0 },
4765 { 1, Iclass_xt_iclass_xsr_intenable_args
,
4766 3, Iclass_xt_iclass_xsr_intenable_stateArgs
, 0, 0 },
4767 { 2, Iclass_xt_iclass_break_args
,
4768 2, Iclass_xt_iclass_break_stateArgs
, 0, 0 },
4769 { 1, Iclass_xt_iclass_break_n_args
,
4770 2, Iclass_xt_iclass_break_n_stateArgs
, 0, 0 },
4771 { 1, Iclass_xt_iclass_rsr_dbreaka0_args
,
4772 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs
, 0, 0 },
4773 { 1, Iclass_xt_iclass_wsr_dbreaka0_args
,
4774 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs
, 0, 0 },
4775 { 1, Iclass_xt_iclass_xsr_dbreaka0_args
,
4776 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs
, 0, 0 },
4777 { 1, Iclass_xt_iclass_rsr_dbreakc0_args
,
4778 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs
, 0, 0 },
4779 { 1, Iclass_xt_iclass_wsr_dbreakc0_args
,
4780 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs
, 0, 0 },
4781 { 1, Iclass_xt_iclass_xsr_dbreakc0_args
,
4782 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs
, 0, 0 },
4783 { 1, Iclass_xt_iclass_rsr_dbreaka1_args
,
4784 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs
, 0, 0 },
4785 { 1, Iclass_xt_iclass_wsr_dbreaka1_args
,
4786 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs
, 0, 0 },
4787 { 1, Iclass_xt_iclass_xsr_dbreaka1_args
,
4788 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs
, 0, 0 },
4789 { 1, Iclass_xt_iclass_rsr_dbreakc1_args
,
4790 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs
, 0, 0 },
4791 { 1, Iclass_xt_iclass_wsr_dbreakc1_args
,
4792 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs
, 0, 0 },
4793 { 1, Iclass_xt_iclass_xsr_dbreakc1_args
,
4794 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs
, 0, 0 },
4795 { 1, Iclass_xt_iclass_rsr_ibreaka0_args
,
4796 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs
, 0, 0 },
4797 { 1, Iclass_xt_iclass_wsr_ibreaka0_args
,
4798 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs
, 0, 0 },
4799 { 1, Iclass_xt_iclass_xsr_ibreaka0_args
,
4800 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs
, 0, 0 },
4801 { 1, Iclass_xt_iclass_rsr_ibreaka1_args
,
4802 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs
, 0, 0 },
4803 { 1, Iclass_xt_iclass_wsr_ibreaka1_args
,
4804 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs
, 0, 0 },
4805 { 1, Iclass_xt_iclass_xsr_ibreaka1_args
,
4806 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs
, 0, 0 },
4807 { 1, Iclass_xt_iclass_rsr_ibreakenable_args
,
4808 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs
, 0, 0 },
4809 { 1, Iclass_xt_iclass_wsr_ibreakenable_args
,
4810 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs
, 0, 0 },
4811 { 1, Iclass_xt_iclass_xsr_ibreakenable_args
,
4812 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs
, 0, 0 },
4813 { 1, Iclass_xt_iclass_rsr_debugcause_args
,
4814 4, Iclass_xt_iclass_rsr_debugcause_stateArgs
, 0, 0 },
4815 { 1, Iclass_xt_iclass_wsr_debugcause_args
,
4816 4, Iclass_xt_iclass_wsr_debugcause_stateArgs
, 0, 0 },
4817 { 1, Iclass_xt_iclass_xsr_debugcause_args
,
4818 4, Iclass_xt_iclass_xsr_debugcause_stateArgs
, 0, 0 },
4819 { 1, Iclass_xt_iclass_rsr_icount_args
,
4820 3, Iclass_xt_iclass_rsr_icount_stateArgs
, 0, 0 },
4821 { 1, Iclass_xt_iclass_wsr_icount_args
,
4822 4, Iclass_xt_iclass_wsr_icount_stateArgs
, 0, 0 },
4823 { 1, Iclass_xt_iclass_xsr_icount_args
,
4824 4, Iclass_xt_iclass_xsr_icount_stateArgs
, 0, 0 },
4825 { 1, Iclass_xt_iclass_rsr_icountlevel_args
,
4826 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs
, 0, 0 },
4827 { 1, Iclass_xt_iclass_wsr_icountlevel_args
,
4828 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs
, 0, 0 },
4829 { 1, Iclass_xt_iclass_xsr_icountlevel_args
,
4830 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs
, 0, 0 },
4831 { 1, Iclass_xt_iclass_rsr_ddr_args
,
4832 3, Iclass_xt_iclass_rsr_ddr_stateArgs
, 0, 0 },
4833 { 1, Iclass_xt_iclass_wsr_ddr_args
,
4834 4, Iclass_xt_iclass_wsr_ddr_stateArgs
, 0, 0 },
4835 { 1, Iclass_xt_iclass_xsr_ddr_args
,
4836 4, Iclass_xt_iclass_xsr_ddr_stateArgs
, 0, 0 },
4837 { 0, 0 /* xt_iclass_rfdo */,
4838 10, Iclass_xt_iclass_rfdo_stateArgs
, 0, 0 },
4839 { 0, 0 /* xt_iclass_rfdd */,
4840 1, Iclass_xt_iclass_rfdd_stateArgs
, 0, 0 },
4841 { 1, Iclass_xt_iclass_rsr_ccount_args
,
4842 3, Iclass_xt_iclass_rsr_ccount_stateArgs
, 0, 0 },
4843 { 1, Iclass_xt_iclass_wsr_ccount_args
,
4844 4, Iclass_xt_iclass_wsr_ccount_stateArgs
, 0, 0 },
4845 { 1, Iclass_xt_iclass_xsr_ccount_args
,
4846 4, Iclass_xt_iclass_xsr_ccount_stateArgs
, 0, 0 },
4847 { 1, Iclass_xt_iclass_rsr_ccompare0_args
,
4848 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs
, 0, 0 },
4849 { 1, Iclass_xt_iclass_wsr_ccompare0_args
,
4850 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs
, 0, 0 },
4851 { 1, Iclass_xt_iclass_xsr_ccompare0_args
,
4852 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs
, 0, 0 },
4853 { 1, Iclass_xt_iclass_rsr_ccompare1_args
,
4854 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs
, 0, 0 },
4855 { 1, Iclass_xt_iclass_wsr_ccompare1_args
,
4856 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs
, 0, 0 },
4857 { 1, Iclass_xt_iclass_xsr_ccompare1_args
,
4858 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs
, 0, 0 },
4859 { 1, Iclass_xt_iclass_rsr_ccompare2_args
,
4860 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs
, 0, 0 },
4861 { 1, Iclass_xt_iclass_wsr_ccompare2_args
,
4862 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs
, 0, 0 },
4863 { 1, Iclass_xt_iclass_xsr_ccompare2_args
,
4864 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs
, 0, 0 },
4865 { 2, Iclass_xt_iclass_icache_args
,
4867 { 2, Iclass_xt_iclass_icache_inv_args
,
4868 2, Iclass_xt_iclass_icache_inv_stateArgs
, 0, 0 },
4869 { 2, Iclass_xt_iclass_licx_args
,
4870 2, Iclass_xt_iclass_licx_stateArgs
, 0, 0 },
4871 { 2, Iclass_xt_iclass_sicx_args
,
4872 2, Iclass_xt_iclass_sicx_stateArgs
, 0, 0 },
4873 { 2, Iclass_xt_iclass_dcache_args
,
4875 { 2, Iclass_xt_iclass_dcache_ind_args
,
4876 2, Iclass_xt_iclass_dcache_ind_stateArgs
, 0, 0 },
4877 { 2, Iclass_xt_iclass_dcache_inv_args
,
4878 2, Iclass_xt_iclass_dcache_inv_stateArgs
, 0, 0 },
4879 { 2, Iclass_xt_iclass_dpf_args
,
4881 { 2, Iclass_xt_iclass_sdct_args
,
4882 2, Iclass_xt_iclass_sdct_stateArgs
, 0, 0 },
4883 { 2, Iclass_xt_iclass_ldct_args
,
4884 2, Iclass_xt_iclass_ldct_stateArgs
, 0, 0 },
4885 { 1, Iclass_xt_iclass_wsr_ptevaddr_args
,
4886 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs
, 0, 0 },
4887 { 1, Iclass_xt_iclass_rsr_ptevaddr_args
,
4888 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs
, 0, 0 },
4889 { 1, Iclass_xt_iclass_xsr_ptevaddr_args
,
4890 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs
, 0, 0 },
4891 { 1, Iclass_xt_iclass_rsr_rasid_args
,
4892 5, Iclass_xt_iclass_rsr_rasid_stateArgs
, 0, 0 },
4893 { 1, Iclass_xt_iclass_wsr_rasid_args
,
4894 6, Iclass_xt_iclass_wsr_rasid_stateArgs
, 0, 0 },
4895 { 1, Iclass_xt_iclass_xsr_rasid_args
,
4896 6, Iclass_xt_iclass_xsr_rasid_stateArgs
, 0, 0 },
4897 { 1, Iclass_xt_iclass_rsr_itlbcfg_args
,
4898 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs
, 0, 0 },
4899 { 1, Iclass_xt_iclass_wsr_itlbcfg_args
,
4900 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs
, 0, 0 },
4901 { 1, Iclass_xt_iclass_xsr_itlbcfg_args
,
4902 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs
, 0, 0 },
4903 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args
,
4904 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs
, 0, 0 },
4905 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args
,
4906 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs
, 0, 0 },
4907 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args
,
4908 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs
, 0, 0 },
4909 { 1, Iclass_xt_iclass_idtlb_args
,
4910 3, Iclass_xt_iclass_idtlb_stateArgs
, 0, 0 },
4911 { 2, Iclass_xt_iclass_rdtlb_args
,
4912 2, Iclass_xt_iclass_rdtlb_stateArgs
, 0, 0 },
4913 { 2, Iclass_xt_iclass_wdtlb_args
,
4914 3, Iclass_xt_iclass_wdtlb_stateArgs
, 0, 0 },
4915 { 1, Iclass_xt_iclass_iitlb_args
,
4916 2, Iclass_xt_iclass_iitlb_stateArgs
, 0, 0 },
4917 { 2, Iclass_xt_iclass_ritlb_args
,
4918 2, Iclass_xt_iclass_ritlb_stateArgs
, 0, 0 },
4919 { 2, Iclass_xt_iclass_witlb_args
,
4920 2, Iclass_xt_iclass_witlb_stateArgs
, 0, 0 },
4921 { 0, 0 /* xt_iclass_ldpte */,
4922 2, Iclass_xt_iclass_ldpte_stateArgs
, 0, 0 },
4923 { 0, 0 /* xt_iclass_hwwitlba */,
4924 1, Iclass_xt_iclass_hwwitlba_stateArgs
, 0, 0 },
4925 { 0, 0 /* xt_iclass_hwwdtlba */,
4926 1, Iclass_xt_iclass_hwwdtlba_stateArgs
, 0, 0 },
4927 { 2, Iclass_xt_iclass_nsa_args
,
4931 enum xtensa_iclass_id
{
4932 ICLASS_xt_iclass_excw
,
4933 ICLASS_xt_iclass_rfe
,
4934 ICLASS_xt_iclass_rfde
,
4935 ICLASS_xt_iclass_syscall
,
4936 ICLASS_xt_iclass_simcall
,
4937 ICLASS_xt_iclass_call12
,
4938 ICLASS_xt_iclass_call8
,
4939 ICLASS_xt_iclass_call4
,
4940 ICLASS_xt_iclass_callx12
,
4941 ICLASS_xt_iclass_callx8
,
4942 ICLASS_xt_iclass_callx4
,
4943 ICLASS_xt_iclass_entry
,
4944 ICLASS_xt_iclass_movsp
,
4945 ICLASS_xt_iclass_rotw
,
4946 ICLASS_xt_iclass_retw
,
4947 ICLASS_xt_iclass_rfwou
,
4948 ICLASS_xt_iclass_l32e
,
4949 ICLASS_xt_iclass_s32e
,
4950 ICLASS_xt_iclass_rsr_windowbase
,
4951 ICLASS_xt_iclass_wsr_windowbase
,
4952 ICLASS_xt_iclass_xsr_windowbase
,
4953 ICLASS_xt_iclass_rsr_windowstart
,
4954 ICLASS_xt_iclass_wsr_windowstart
,
4955 ICLASS_xt_iclass_xsr_windowstart
,
4956 ICLASS_xt_iclass_add_n
,
4957 ICLASS_xt_iclass_addi_n
,
4958 ICLASS_xt_iclass_bz6
,
4959 ICLASS_xt_iclass_ill_n
,
4960 ICLASS_xt_iclass_loadi4
,
4961 ICLASS_xt_iclass_mov_n
,
4962 ICLASS_xt_iclass_movi_n
,
4963 ICLASS_xt_iclass_nopn
,
4964 ICLASS_xt_iclass_retn
,
4965 ICLASS_xt_iclass_storei4
,
4966 ICLASS_xt_iclass_addi
,
4967 ICLASS_xt_iclass_addmi
,
4968 ICLASS_xt_iclass_addsub
,
4969 ICLASS_xt_iclass_bit
,
4970 ICLASS_xt_iclass_bsi8
,
4971 ICLASS_xt_iclass_bsi8b
,
4972 ICLASS_xt_iclass_bsi8u
,
4973 ICLASS_xt_iclass_bst8
,
4974 ICLASS_xt_iclass_bsz12
,
4975 ICLASS_xt_iclass_call0
,
4976 ICLASS_xt_iclass_callx0
,
4977 ICLASS_xt_iclass_exti
,
4978 ICLASS_xt_iclass_ill
,
4979 ICLASS_xt_iclass_jump
,
4980 ICLASS_xt_iclass_jumpx
,
4981 ICLASS_xt_iclass_l16ui
,
4982 ICLASS_xt_iclass_l16si
,
4983 ICLASS_xt_iclass_l32i
,
4984 ICLASS_xt_iclass_l32r
,
4985 ICLASS_xt_iclass_l8i
,
4986 ICLASS_xt_iclass_loop
,
4987 ICLASS_xt_iclass_loopz
,
4988 ICLASS_xt_iclass_movi
,
4989 ICLASS_xt_iclass_movz
,
4990 ICLASS_xt_iclass_neg
,
4991 ICLASS_xt_iclass_nop
,
4992 ICLASS_xt_iclass_return
,
4993 ICLASS_xt_iclass_s16i
,
4994 ICLASS_xt_iclass_s32i
,
4995 ICLASS_xt_iclass_s8i
,
4996 ICLASS_xt_iclass_sar
,
4997 ICLASS_xt_iclass_sari
,
4998 ICLASS_xt_iclass_shifts
,
4999 ICLASS_xt_iclass_shiftst
,
5000 ICLASS_xt_iclass_shiftt
,
5001 ICLASS_xt_iclass_slli
,
5002 ICLASS_xt_iclass_srai
,
5003 ICLASS_xt_iclass_srli
,
5004 ICLASS_xt_iclass_memw
,
5005 ICLASS_xt_iclass_extw
,
5006 ICLASS_xt_iclass_isync
,
5007 ICLASS_xt_iclass_sync
,
5008 ICLASS_xt_iclass_rsil
,
5009 ICLASS_xt_iclass_rsr_lend
,
5010 ICLASS_xt_iclass_wsr_lend
,
5011 ICLASS_xt_iclass_xsr_lend
,
5012 ICLASS_xt_iclass_rsr_lcount
,
5013 ICLASS_xt_iclass_wsr_lcount
,
5014 ICLASS_xt_iclass_xsr_lcount
,
5015 ICLASS_xt_iclass_rsr_lbeg
,
5016 ICLASS_xt_iclass_wsr_lbeg
,
5017 ICLASS_xt_iclass_xsr_lbeg
,
5018 ICLASS_xt_iclass_rsr_sar
,
5019 ICLASS_xt_iclass_wsr_sar
,
5020 ICLASS_xt_iclass_xsr_sar
,
5021 ICLASS_xt_iclass_rsr_litbase
,
5022 ICLASS_xt_iclass_wsr_litbase
,
5023 ICLASS_xt_iclass_xsr_litbase
,
5024 ICLASS_xt_iclass_rsr_176
,
5025 ICLASS_xt_iclass_rsr_208
,
5026 ICLASS_xt_iclass_rsr_ps
,
5027 ICLASS_xt_iclass_wsr_ps
,
5028 ICLASS_xt_iclass_xsr_ps
,
5029 ICLASS_xt_iclass_rsr_epc1
,
5030 ICLASS_xt_iclass_wsr_epc1
,
5031 ICLASS_xt_iclass_xsr_epc1
,
5032 ICLASS_xt_iclass_rsr_excsave1
,
5033 ICLASS_xt_iclass_wsr_excsave1
,
5034 ICLASS_xt_iclass_xsr_excsave1
,
5035 ICLASS_xt_iclass_rsr_epc2
,
5036 ICLASS_xt_iclass_wsr_epc2
,
5037 ICLASS_xt_iclass_xsr_epc2
,
5038 ICLASS_xt_iclass_rsr_excsave2
,
5039 ICLASS_xt_iclass_wsr_excsave2
,
5040 ICLASS_xt_iclass_xsr_excsave2
,
5041 ICLASS_xt_iclass_rsr_epc3
,
5042 ICLASS_xt_iclass_wsr_epc3
,
5043 ICLASS_xt_iclass_xsr_epc3
,
5044 ICLASS_xt_iclass_rsr_excsave3
,
5045 ICLASS_xt_iclass_wsr_excsave3
,
5046 ICLASS_xt_iclass_xsr_excsave3
,
5047 ICLASS_xt_iclass_rsr_epc4
,
5048 ICLASS_xt_iclass_wsr_epc4
,
5049 ICLASS_xt_iclass_xsr_epc4
,
5050 ICLASS_xt_iclass_rsr_excsave4
,
5051 ICLASS_xt_iclass_wsr_excsave4
,
5052 ICLASS_xt_iclass_xsr_excsave4
,
5053 ICLASS_xt_iclass_rsr_eps2
,
5054 ICLASS_xt_iclass_wsr_eps2
,
5055 ICLASS_xt_iclass_xsr_eps2
,
5056 ICLASS_xt_iclass_rsr_eps3
,
5057 ICLASS_xt_iclass_wsr_eps3
,
5058 ICLASS_xt_iclass_xsr_eps3
,
5059 ICLASS_xt_iclass_rsr_eps4
,
5060 ICLASS_xt_iclass_wsr_eps4
,
5061 ICLASS_xt_iclass_xsr_eps4
,
5062 ICLASS_xt_iclass_rsr_excvaddr
,
5063 ICLASS_xt_iclass_wsr_excvaddr
,
5064 ICLASS_xt_iclass_xsr_excvaddr
,
5065 ICLASS_xt_iclass_rsr_depc
,
5066 ICLASS_xt_iclass_wsr_depc
,
5067 ICLASS_xt_iclass_xsr_depc
,
5068 ICLASS_xt_iclass_rsr_exccause
,
5069 ICLASS_xt_iclass_wsr_exccause
,
5070 ICLASS_xt_iclass_xsr_exccause
,
5071 ICLASS_xt_iclass_rsr_misc0
,
5072 ICLASS_xt_iclass_wsr_misc0
,
5073 ICLASS_xt_iclass_xsr_misc0
,
5074 ICLASS_xt_iclass_rsr_misc1
,
5075 ICLASS_xt_iclass_wsr_misc1
,
5076 ICLASS_xt_iclass_xsr_misc1
,
5077 ICLASS_xt_iclass_rsr_prid
,
5078 ICLASS_xt_iclass_rfi
,
5079 ICLASS_xt_iclass_wait
,
5080 ICLASS_xt_iclass_rsr_interrupt
,
5081 ICLASS_xt_iclass_wsr_intset
,
5082 ICLASS_xt_iclass_wsr_intclear
,
5083 ICLASS_xt_iclass_rsr_intenable
,
5084 ICLASS_xt_iclass_wsr_intenable
,
5085 ICLASS_xt_iclass_xsr_intenable
,
5086 ICLASS_xt_iclass_break
,
5087 ICLASS_xt_iclass_break_n
,
5088 ICLASS_xt_iclass_rsr_dbreaka0
,
5089 ICLASS_xt_iclass_wsr_dbreaka0
,
5090 ICLASS_xt_iclass_xsr_dbreaka0
,
5091 ICLASS_xt_iclass_rsr_dbreakc0
,
5092 ICLASS_xt_iclass_wsr_dbreakc0
,
5093 ICLASS_xt_iclass_xsr_dbreakc0
,
5094 ICLASS_xt_iclass_rsr_dbreaka1
,
5095 ICLASS_xt_iclass_wsr_dbreaka1
,
5096 ICLASS_xt_iclass_xsr_dbreaka1
,
5097 ICLASS_xt_iclass_rsr_dbreakc1
,
5098 ICLASS_xt_iclass_wsr_dbreakc1
,
5099 ICLASS_xt_iclass_xsr_dbreakc1
,
5100 ICLASS_xt_iclass_rsr_ibreaka0
,
5101 ICLASS_xt_iclass_wsr_ibreaka0
,
5102 ICLASS_xt_iclass_xsr_ibreaka0
,
5103 ICLASS_xt_iclass_rsr_ibreaka1
,
5104 ICLASS_xt_iclass_wsr_ibreaka1
,
5105 ICLASS_xt_iclass_xsr_ibreaka1
,
5106 ICLASS_xt_iclass_rsr_ibreakenable
,
5107 ICLASS_xt_iclass_wsr_ibreakenable
,
5108 ICLASS_xt_iclass_xsr_ibreakenable
,
5109 ICLASS_xt_iclass_rsr_debugcause
,
5110 ICLASS_xt_iclass_wsr_debugcause
,
5111 ICLASS_xt_iclass_xsr_debugcause
,
5112 ICLASS_xt_iclass_rsr_icount
,
5113 ICLASS_xt_iclass_wsr_icount
,
5114 ICLASS_xt_iclass_xsr_icount
,
5115 ICLASS_xt_iclass_rsr_icountlevel
,
5116 ICLASS_xt_iclass_wsr_icountlevel
,
5117 ICLASS_xt_iclass_xsr_icountlevel
,
5118 ICLASS_xt_iclass_rsr_ddr
,
5119 ICLASS_xt_iclass_wsr_ddr
,
5120 ICLASS_xt_iclass_xsr_ddr
,
5121 ICLASS_xt_iclass_rfdo
,
5122 ICLASS_xt_iclass_rfdd
,
5123 ICLASS_xt_iclass_rsr_ccount
,
5124 ICLASS_xt_iclass_wsr_ccount
,
5125 ICLASS_xt_iclass_xsr_ccount
,
5126 ICLASS_xt_iclass_rsr_ccompare0
,
5127 ICLASS_xt_iclass_wsr_ccompare0
,
5128 ICLASS_xt_iclass_xsr_ccompare0
,
5129 ICLASS_xt_iclass_rsr_ccompare1
,
5130 ICLASS_xt_iclass_wsr_ccompare1
,
5131 ICLASS_xt_iclass_xsr_ccompare1
,
5132 ICLASS_xt_iclass_rsr_ccompare2
,
5133 ICLASS_xt_iclass_wsr_ccompare2
,
5134 ICLASS_xt_iclass_xsr_ccompare2
,
5135 ICLASS_xt_iclass_icache
,
5136 ICLASS_xt_iclass_icache_inv
,
5137 ICLASS_xt_iclass_licx
,
5138 ICLASS_xt_iclass_sicx
,
5139 ICLASS_xt_iclass_dcache
,
5140 ICLASS_xt_iclass_dcache_ind
,
5141 ICLASS_xt_iclass_dcache_inv
,
5142 ICLASS_xt_iclass_dpf
,
5143 ICLASS_xt_iclass_sdct
,
5144 ICLASS_xt_iclass_ldct
,
5145 ICLASS_xt_iclass_wsr_ptevaddr
,
5146 ICLASS_xt_iclass_rsr_ptevaddr
,
5147 ICLASS_xt_iclass_xsr_ptevaddr
,
5148 ICLASS_xt_iclass_rsr_rasid
,
5149 ICLASS_xt_iclass_wsr_rasid
,
5150 ICLASS_xt_iclass_xsr_rasid
,
5151 ICLASS_xt_iclass_rsr_itlbcfg
,
5152 ICLASS_xt_iclass_wsr_itlbcfg
,
5153 ICLASS_xt_iclass_xsr_itlbcfg
,
5154 ICLASS_xt_iclass_rsr_dtlbcfg
,
5155 ICLASS_xt_iclass_wsr_dtlbcfg
,
5156 ICLASS_xt_iclass_xsr_dtlbcfg
,
5157 ICLASS_xt_iclass_idtlb
,
5158 ICLASS_xt_iclass_rdtlb
,
5159 ICLASS_xt_iclass_wdtlb
,
5160 ICLASS_xt_iclass_iitlb
,
5161 ICLASS_xt_iclass_ritlb
,
5162 ICLASS_xt_iclass_witlb
,
5163 ICLASS_xt_iclass_ldpte
,
5164 ICLASS_xt_iclass_hwwitlba
,
5165 ICLASS_xt_iclass_hwwdtlba
,
5166 ICLASS_xt_iclass_nsa
5170 /* Opcode encodings. */
5173 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5175 slotbuf
[0] = 0x80200;
5179 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5185 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5187 slotbuf
[0] = 0x2300;
5191 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5197 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5199 slotbuf
[0] = 0x1500;
5203 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5205 slotbuf
[0] = 0x5c0000;
5209 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5211 slotbuf
[0] = 0x580000;
5215 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5217 slotbuf
[0] = 0x540000;
5221 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5223 slotbuf
[0] = 0xf0000;
5227 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5229 slotbuf
[0] = 0xb0000;
5233 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5235 slotbuf
[0] = 0x70000;
5239 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5241 slotbuf
[0] = 0x6c0000;
5245 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5251 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5257 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5259 slotbuf
[0] = 0x60000;
5263 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5265 slotbuf
[0] = 0xd10f;
5269 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5271 slotbuf
[0] = 0x4300;
5275 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5277 slotbuf
[0] = 0x5300;
5281 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5287 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5293 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5295 slotbuf
[0] = 0x4830;
5299 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5301 slotbuf
[0] = 0x4831;
5305 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5307 slotbuf
[0] = 0x4816;
5311 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5313 slotbuf
[0] = 0x4930;
5317 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5319 slotbuf
[0] = 0x4931;
5323 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5325 slotbuf
[0] = 0x4916;
5329 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf
)
5331 slotbuf
[0] = 0xa000;
5335 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf
)
5337 slotbuf
[0] = 0xb000;
5341 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5343 slotbuf
[0] = 0xc800;
5347 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5349 slotbuf
[0] = 0xcc00;
5353 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5355 slotbuf
[0] = 0xd60f;
5359 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf
)
5361 slotbuf
[0] = 0x8000;
5365 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5367 slotbuf
[0] = 0xd000;
5371 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5373 slotbuf
[0] = 0xc000;
5377 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5379 slotbuf
[0] = 0xd30f;
5383 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
5385 slotbuf
[0] = 0xd00f;
5389 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf
)
5391 slotbuf
[0] = 0x9000;
5395 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5397 slotbuf
[0] = 0x200c00;
5401 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5403 slotbuf
[0] = 0x200d00;
5407 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5413 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5419 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5425 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5431 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5437 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5443 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5449 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5455 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5461 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5467 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5473 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5475 slotbuf
[0] = 0x680000;
5479 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5481 slotbuf
[0] = 0x690000;
5485 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5487 slotbuf
[0] = 0x6b0000;
5491 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5493 slotbuf
[0] = 0x6a0000;
5497 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5499 slotbuf
[0] = 0x700600;
5503 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5505 slotbuf
[0] = 0x700e00;
5509 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5511 slotbuf
[0] = 0x6f0000;
5515 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5517 slotbuf
[0] = 0x6e0000;
5521 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5523 slotbuf
[0] = 0x700100;
5527 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5529 slotbuf
[0] = 0x700900;
5533 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5535 slotbuf
[0] = 0x700a00;
5539 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5541 slotbuf
[0] = 0x700200;
5545 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5547 slotbuf
[0] = 0x700b00;
5551 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5553 slotbuf
[0] = 0x700300;
5557 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5559 slotbuf
[0] = 0x700800;
5563 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5565 slotbuf
[0] = 0x700000;
5569 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5571 slotbuf
[0] = 0x700400;
5575 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5577 slotbuf
[0] = 0x700c00;
5581 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5583 slotbuf
[0] = 0x700500;
5587 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5589 slotbuf
[0] = 0x700d00;
5593 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5595 slotbuf
[0] = 0x640000;
5599 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5601 slotbuf
[0] = 0x650000;
5605 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5607 slotbuf
[0] = 0x670000;
5611 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5613 slotbuf
[0] = 0x660000;
5617 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5619 slotbuf
[0] = 0x500000;
5623 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5625 slotbuf
[0] = 0x30000;
5629 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5635 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5641 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5643 slotbuf
[0] = 0x600000;
5647 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5649 slotbuf
[0] = 0xa0000;
5653 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5655 slotbuf
[0] = 0x200100;
5659 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5661 slotbuf
[0] = 0x200900;
5665 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5667 slotbuf
[0] = 0x200200;
5671 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5673 slotbuf
[0] = 0x100000;
5677 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5679 slotbuf
[0] = 0x200000;
5683 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5685 slotbuf
[0] = 0x6d0800;
5689 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5691 slotbuf
[0] = 0x6d0900;
5695 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5697 slotbuf
[0] = 0x6d0a00;
5701 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5703 slotbuf
[0] = 0x200a00;
5707 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5713 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5719 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5725 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5731 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5737 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5739 slotbuf
[0] = 0x1006;
5743 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5745 slotbuf
[0] = 0xf0200;
5749 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5751 slotbuf
[0] = 0x20000;
5755 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5757 slotbuf
[0] = 0x200500;
5761 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5763 slotbuf
[0] = 0x200600;
5767 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5769 slotbuf
[0] = 0x200400;
5773 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5779 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5785 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5791 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5797 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5803 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5809 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5815 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5821 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5827 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5833 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5839 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5845 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5847 slotbuf
[0] = 0xc0200;
5851 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5853 slotbuf
[0] = 0xd0200;
5857 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5863 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5865 slotbuf
[0] = 0x10200;
5869 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5871 slotbuf
[0] = 0x20200;
5875 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5877 slotbuf
[0] = 0x30200;
5881 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5887 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5893 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5899 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5905 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5911 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5917 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5923 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5929 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5935 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5941 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5947 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5953 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5959 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5965 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5971 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5977 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5979 slotbuf
[0] = 0xb030;
5983 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5985 slotbuf
[0] = 0xd030;
5989 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5991 slotbuf
[0] = 0xe630;
5995 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf
)
5997 slotbuf
[0] = 0xe631;
6001 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6003 slotbuf
[0] = 0xe616;
6007 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6009 slotbuf
[0] = 0xb130;
6013 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6015 slotbuf
[0] = 0xb131;
6019 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6021 slotbuf
[0] = 0xb116;
6025 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6027 slotbuf
[0] = 0xd130;
6031 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6033 slotbuf
[0] = 0xd131;
6037 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6039 slotbuf
[0] = 0xd116;
6043 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6045 slotbuf
[0] = 0xb230;
6049 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6051 slotbuf
[0] = 0xb231;
6055 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6057 slotbuf
[0] = 0xb216;
6061 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6063 slotbuf
[0] = 0xd230;
6067 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6069 slotbuf
[0] = 0xd231;
6073 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6075 slotbuf
[0] = 0xd216;
6079 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6081 slotbuf
[0] = 0xb330;
6085 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6087 slotbuf
[0] = 0xb331;
6091 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6093 slotbuf
[0] = 0xb316;
6097 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6099 slotbuf
[0] = 0xd330;
6103 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6105 slotbuf
[0] = 0xd331;
6109 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6111 slotbuf
[0] = 0xd316;
6115 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6117 slotbuf
[0] = 0xb430;
6121 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6123 slotbuf
[0] = 0xb431;
6127 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6129 slotbuf
[0] = 0xb416;
6133 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6135 slotbuf
[0] = 0xd430;
6139 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6141 slotbuf
[0] = 0xd431;
6145 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6147 slotbuf
[0] = 0xd416;
6151 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6153 slotbuf
[0] = 0xc230;
6157 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6159 slotbuf
[0] = 0xc231;
6163 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6165 slotbuf
[0] = 0xc216;
6169 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6171 slotbuf
[0] = 0xc330;
6175 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6177 slotbuf
[0] = 0xc331;
6181 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6183 slotbuf
[0] = 0xc316;
6187 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6189 slotbuf
[0] = 0xc430;
6193 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6195 slotbuf
[0] = 0xc431;
6199 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6201 slotbuf
[0] = 0xc416;
6205 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6207 slotbuf
[0] = 0xee30;
6211 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6213 slotbuf
[0] = 0xee31;
6217 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6219 slotbuf
[0] = 0xee16;
6223 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6225 slotbuf
[0] = 0xc030;
6229 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6231 slotbuf
[0] = 0xc031;
6235 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6237 slotbuf
[0] = 0xc016;
6241 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6243 slotbuf
[0] = 0xe830;
6247 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6249 slotbuf
[0] = 0xe831;
6253 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6255 slotbuf
[0] = 0xe816;
6259 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6261 slotbuf
[0] = 0xf430;
6265 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6267 slotbuf
[0] = 0xf431;
6271 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6273 slotbuf
[0] = 0xf416;
6277 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6279 slotbuf
[0] = 0xf530;
6283 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6285 slotbuf
[0] = 0xf531;
6289 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6291 slotbuf
[0] = 0xf516;
6295 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6297 slotbuf
[0] = 0xeb30;
6301 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6303 slotbuf
[0] = 0x10300;
6307 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6313 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6315 slotbuf
[0] = 0xe230;
6319 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6321 slotbuf
[0] = 0xe231;
6325 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6327 slotbuf
[0] = 0xe331;
6331 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6333 slotbuf
[0] = 0xe430;
6337 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6339 slotbuf
[0] = 0xe431;
6343 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6345 slotbuf
[0] = 0xe416;
6349 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6355 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf
)
6357 slotbuf
[0] = 0xd20f;
6361 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6363 slotbuf
[0] = 0x9030;
6367 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6369 slotbuf
[0] = 0x9031;
6373 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6375 slotbuf
[0] = 0x9016;
6379 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6381 slotbuf
[0] = 0xa030;
6385 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6387 slotbuf
[0] = 0xa031;
6391 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6393 slotbuf
[0] = 0xa016;
6397 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6399 slotbuf
[0] = 0x9130;
6403 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6405 slotbuf
[0] = 0x9131;
6409 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6411 slotbuf
[0] = 0x9116;
6415 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6417 slotbuf
[0] = 0xa130;
6421 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6423 slotbuf
[0] = 0xa131;
6427 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6429 slotbuf
[0] = 0xa116;
6433 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6435 slotbuf
[0] = 0x8030;
6439 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6441 slotbuf
[0] = 0x8031;
6445 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6447 slotbuf
[0] = 0x8016;
6451 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6453 slotbuf
[0] = 0x8130;
6457 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6459 slotbuf
[0] = 0x8131;
6463 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6465 slotbuf
[0] = 0x8116;
6469 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6471 slotbuf
[0] = 0x6030;
6475 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6477 slotbuf
[0] = 0x6031;
6481 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6483 slotbuf
[0] = 0x6016;
6487 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6489 slotbuf
[0] = 0xe930;
6493 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6495 slotbuf
[0] = 0xe931;
6499 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6501 slotbuf
[0] = 0xe916;
6505 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6507 slotbuf
[0] = 0xec30;
6511 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6513 slotbuf
[0] = 0xec31;
6517 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6519 slotbuf
[0] = 0xec16;
6523 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6525 slotbuf
[0] = 0xed30;
6529 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6531 slotbuf
[0] = 0xed31;
6535 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6537 slotbuf
[0] = 0xed16;
6541 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6543 slotbuf
[0] = 0x6830;
6547 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6549 slotbuf
[0] = 0x6831;
6553 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6555 slotbuf
[0] = 0x6816;
6559 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6565 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6567 slotbuf
[0] = 0x10e1f;
6571 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6573 slotbuf
[0] = 0xea30;
6577 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6579 slotbuf
[0] = 0xea31;
6583 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6585 slotbuf
[0] = 0xea16;
6589 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6591 slotbuf
[0] = 0xf030;
6595 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6597 slotbuf
[0] = 0xf031;
6601 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6603 slotbuf
[0] = 0xf016;
6607 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6609 slotbuf
[0] = 0xf130;
6613 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6615 slotbuf
[0] = 0xf131;
6619 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6621 slotbuf
[0] = 0xf116;
6625 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6627 slotbuf
[0] = 0xf230;
6631 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6633 slotbuf
[0] = 0xf231;
6637 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6639 slotbuf
[0] = 0xf216;
6643 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6645 slotbuf
[0] = 0x2c0700;
6649 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6651 slotbuf
[0] = 0x2e0700;
6655 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6657 slotbuf
[0] = 0x2f0700;
6661 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6667 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6673 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6679 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6685 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6687 slotbuf
[0] = 0x240700;
6691 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6693 slotbuf
[0] = 0x250700;
6697 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6699 slotbuf
[0] = 0x280740;
6703 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6705 slotbuf
[0] = 0x280750;
6709 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6711 slotbuf
[0] = 0x260700;
6715 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6717 slotbuf
[0] = 0x270700;
6721 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6723 slotbuf
[0] = 0x200700;
6727 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6729 slotbuf
[0] = 0x210700;
6733 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6735 slotbuf
[0] = 0x220700;
6739 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6741 slotbuf
[0] = 0x230700;
6745 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6751 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6757 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6759 slotbuf
[0] = 0x5331;
6763 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6765 slotbuf
[0] = 0x5330;
6769 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6771 slotbuf
[0] = 0x5316;
6775 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6777 slotbuf
[0] = 0x5a30;
6781 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6783 slotbuf
[0] = 0x5a31;
6787 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6789 slotbuf
[0] = 0x5a16;
6793 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6795 slotbuf
[0] = 0x5b30;
6799 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6801 slotbuf
[0] = 0x5b31;
6805 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6807 slotbuf
[0] = 0x5b16;
6811 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6813 slotbuf
[0] = 0x5c30;
6817 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6819 slotbuf
[0] = 0x5c31;
6823 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6825 slotbuf
[0] = 0x5c16;
6829 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6835 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6841 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6847 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6853 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6859 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6865 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6871 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6877 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6883 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6889 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6895 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6901 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6907 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6913 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf
)
6918 xtensa_opcode_encode_fn Opcode_excw_encode_fns
[] = {
6919 Opcode_excw_Slot_inst_encode
, 0, 0
6922 xtensa_opcode_encode_fn Opcode_rfe_encode_fns
[] = {
6923 Opcode_rfe_Slot_inst_encode
, 0, 0
6926 xtensa_opcode_encode_fn Opcode_rfde_encode_fns
[] = {
6927 Opcode_rfde_Slot_inst_encode
, 0, 0
6930 xtensa_opcode_encode_fn Opcode_syscall_encode_fns
[] = {
6931 Opcode_syscall_Slot_inst_encode
, 0, 0
6934 xtensa_opcode_encode_fn Opcode_simcall_encode_fns
[] = {
6935 Opcode_simcall_Slot_inst_encode
, 0, 0
6938 xtensa_opcode_encode_fn Opcode_call12_encode_fns
[] = {
6939 Opcode_call12_Slot_inst_encode
, 0, 0
6942 xtensa_opcode_encode_fn Opcode_call8_encode_fns
[] = {
6943 Opcode_call8_Slot_inst_encode
, 0, 0
6946 xtensa_opcode_encode_fn Opcode_call4_encode_fns
[] = {
6947 Opcode_call4_Slot_inst_encode
, 0, 0
6950 xtensa_opcode_encode_fn Opcode_callx12_encode_fns
[] = {
6951 Opcode_callx12_Slot_inst_encode
, 0, 0
6954 xtensa_opcode_encode_fn Opcode_callx8_encode_fns
[] = {
6955 Opcode_callx8_Slot_inst_encode
, 0, 0
6958 xtensa_opcode_encode_fn Opcode_callx4_encode_fns
[] = {
6959 Opcode_callx4_Slot_inst_encode
, 0, 0
6962 xtensa_opcode_encode_fn Opcode_entry_encode_fns
[] = {
6963 Opcode_entry_Slot_inst_encode
, 0, 0
6966 xtensa_opcode_encode_fn Opcode_movsp_encode_fns
[] = {
6967 Opcode_movsp_Slot_inst_encode
, 0, 0
6970 xtensa_opcode_encode_fn Opcode_rotw_encode_fns
[] = {
6971 Opcode_rotw_Slot_inst_encode
, 0, 0
6974 xtensa_opcode_encode_fn Opcode_retw_encode_fns
[] = {
6975 Opcode_retw_Slot_inst_encode
, 0, 0
6978 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns
[] = {
6979 0, 0, Opcode_retw_n_Slot_inst16b_encode
6982 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns
[] = {
6983 Opcode_rfwo_Slot_inst_encode
, 0, 0
6986 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns
[] = {
6987 Opcode_rfwu_Slot_inst_encode
, 0, 0
6990 xtensa_opcode_encode_fn Opcode_l32e_encode_fns
[] = {
6991 Opcode_l32e_Slot_inst_encode
, 0, 0
6994 xtensa_opcode_encode_fn Opcode_s32e_encode_fns
[] = {
6995 Opcode_s32e_Slot_inst_encode
, 0, 0
6998 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns
[] = {
6999 Opcode_rsr_windowbase_Slot_inst_encode
, 0, 0
7002 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns
[] = {
7003 Opcode_wsr_windowbase_Slot_inst_encode
, 0, 0
7006 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns
[] = {
7007 Opcode_xsr_windowbase_Slot_inst_encode
, 0, 0
7010 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns
[] = {
7011 Opcode_rsr_windowstart_Slot_inst_encode
, 0, 0
7014 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns
[] = {
7015 Opcode_wsr_windowstart_Slot_inst_encode
, 0, 0
7018 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns
[] = {
7019 Opcode_xsr_windowstart_Slot_inst_encode
, 0, 0
7022 xtensa_opcode_encode_fn Opcode_add_n_encode_fns
[] = {
7023 0, Opcode_add_n_Slot_inst16a_encode
, 0
7026 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns
[] = {
7027 0, Opcode_addi_n_Slot_inst16a_encode
, 0
7030 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns
[] = {
7031 0, 0, Opcode_beqz_n_Slot_inst16b_encode
7034 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns
[] = {
7035 0, 0, Opcode_bnez_n_Slot_inst16b_encode
7038 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns
[] = {
7039 0, 0, Opcode_ill_n_Slot_inst16b_encode
7042 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns
[] = {
7043 0, Opcode_l32i_n_Slot_inst16a_encode
, 0
7046 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns
[] = {
7047 0, 0, Opcode_mov_n_Slot_inst16b_encode
7050 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns
[] = {
7051 0, 0, Opcode_movi_n_Slot_inst16b_encode
7054 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns
[] = {
7055 0, 0, Opcode_nop_n_Slot_inst16b_encode
7058 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns
[] = {
7059 0, 0, Opcode_ret_n_Slot_inst16b_encode
7062 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns
[] = {
7063 0, Opcode_s32i_n_Slot_inst16a_encode
, 0
7066 xtensa_opcode_encode_fn Opcode_addi_encode_fns
[] = {
7067 Opcode_addi_Slot_inst_encode
, 0, 0
7070 xtensa_opcode_encode_fn Opcode_addmi_encode_fns
[] = {
7071 Opcode_addmi_Slot_inst_encode
, 0, 0
7074 xtensa_opcode_encode_fn Opcode_add_encode_fns
[] = {
7075 Opcode_add_Slot_inst_encode
, 0, 0
7078 xtensa_opcode_encode_fn Opcode_sub_encode_fns
[] = {
7079 Opcode_sub_Slot_inst_encode
, 0, 0
7082 xtensa_opcode_encode_fn Opcode_addx2_encode_fns
[] = {
7083 Opcode_addx2_Slot_inst_encode
, 0, 0
7086 xtensa_opcode_encode_fn Opcode_addx4_encode_fns
[] = {
7087 Opcode_addx4_Slot_inst_encode
, 0, 0
7090 xtensa_opcode_encode_fn Opcode_addx8_encode_fns
[] = {
7091 Opcode_addx8_Slot_inst_encode
, 0, 0
7094 xtensa_opcode_encode_fn Opcode_subx2_encode_fns
[] = {
7095 Opcode_subx2_Slot_inst_encode
, 0, 0
7098 xtensa_opcode_encode_fn Opcode_subx4_encode_fns
[] = {
7099 Opcode_subx4_Slot_inst_encode
, 0, 0
7102 xtensa_opcode_encode_fn Opcode_subx8_encode_fns
[] = {
7103 Opcode_subx8_Slot_inst_encode
, 0, 0
7106 xtensa_opcode_encode_fn Opcode_and_encode_fns
[] = {
7107 Opcode_and_Slot_inst_encode
, 0, 0
7110 xtensa_opcode_encode_fn Opcode_or_encode_fns
[] = {
7111 Opcode_or_Slot_inst_encode
, 0, 0
7114 xtensa_opcode_encode_fn Opcode_xor_encode_fns
[] = {
7115 Opcode_xor_Slot_inst_encode
, 0, 0
7118 xtensa_opcode_encode_fn Opcode_beqi_encode_fns
[] = {
7119 Opcode_beqi_Slot_inst_encode
, 0, 0
7122 xtensa_opcode_encode_fn Opcode_bnei_encode_fns
[] = {
7123 Opcode_bnei_Slot_inst_encode
, 0, 0
7126 xtensa_opcode_encode_fn Opcode_bgei_encode_fns
[] = {
7127 Opcode_bgei_Slot_inst_encode
, 0, 0
7130 xtensa_opcode_encode_fn Opcode_blti_encode_fns
[] = {
7131 Opcode_blti_Slot_inst_encode
, 0, 0
7134 xtensa_opcode_encode_fn Opcode_bbci_encode_fns
[] = {
7135 Opcode_bbci_Slot_inst_encode
, 0, 0
7138 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns
[] = {
7139 Opcode_bbsi_Slot_inst_encode
, 0, 0
7142 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns
[] = {
7143 Opcode_bgeui_Slot_inst_encode
, 0, 0
7146 xtensa_opcode_encode_fn Opcode_bltui_encode_fns
[] = {
7147 Opcode_bltui_Slot_inst_encode
, 0, 0
7150 xtensa_opcode_encode_fn Opcode_beq_encode_fns
[] = {
7151 Opcode_beq_Slot_inst_encode
, 0, 0
7154 xtensa_opcode_encode_fn Opcode_bne_encode_fns
[] = {
7155 Opcode_bne_Slot_inst_encode
, 0, 0
7158 xtensa_opcode_encode_fn Opcode_bge_encode_fns
[] = {
7159 Opcode_bge_Slot_inst_encode
, 0, 0
7162 xtensa_opcode_encode_fn Opcode_blt_encode_fns
[] = {
7163 Opcode_blt_Slot_inst_encode
, 0, 0
7166 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns
[] = {
7167 Opcode_bgeu_Slot_inst_encode
, 0, 0
7170 xtensa_opcode_encode_fn Opcode_bltu_encode_fns
[] = {
7171 Opcode_bltu_Slot_inst_encode
, 0, 0
7174 xtensa_opcode_encode_fn Opcode_bany_encode_fns
[] = {
7175 Opcode_bany_Slot_inst_encode
, 0, 0
7178 xtensa_opcode_encode_fn Opcode_bnone_encode_fns
[] = {
7179 Opcode_bnone_Slot_inst_encode
, 0, 0
7182 xtensa_opcode_encode_fn Opcode_ball_encode_fns
[] = {
7183 Opcode_ball_Slot_inst_encode
, 0, 0
7186 xtensa_opcode_encode_fn Opcode_bnall_encode_fns
[] = {
7187 Opcode_bnall_Slot_inst_encode
, 0, 0
7190 xtensa_opcode_encode_fn Opcode_bbc_encode_fns
[] = {
7191 Opcode_bbc_Slot_inst_encode
, 0, 0
7194 xtensa_opcode_encode_fn Opcode_bbs_encode_fns
[] = {
7195 Opcode_bbs_Slot_inst_encode
, 0, 0
7198 xtensa_opcode_encode_fn Opcode_beqz_encode_fns
[] = {
7199 Opcode_beqz_Slot_inst_encode
, 0, 0
7202 xtensa_opcode_encode_fn Opcode_bnez_encode_fns
[] = {
7203 Opcode_bnez_Slot_inst_encode
, 0, 0
7206 xtensa_opcode_encode_fn Opcode_bgez_encode_fns
[] = {
7207 Opcode_bgez_Slot_inst_encode
, 0, 0
7210 xtensa_opcode_encode_fn Opcode_bltz_encode_fns
[] = {
7211 Opcode_bltz_Slot_inst_encode
, 0, 0
7214 xtensa_opcode_encode_fn Opcode_call0_encode_fns
[] = {
7215 Opcode_call0_Slot_inst_encode
, 0, 0
7218 xtensa_opcode_encode_fn Opcode_callx0_encode_fns
[] = {
7219 Opcode_callx0_Slot_inst_encode
, 0, 0
7222 xtensa_opcode_encode_fn Opcode_extui_encode_fns
[] = {
7223 Opcode_extui_Slot_inst_encode
, 0, 0
7226 xtensa_opcode_encode_fn Opcode_ill_encode_fns
[] = {
7227 Opcode_ill_Slot_inst_encode
, 0, 0
7230 xtensa_opcode_encode_fn Opcode_j_encode_fns
[] = {
7231 Opcode_j_Slot_inst_encode
, 0, 0
7234 xtensa_opcode_encode_fn Opcode_jx_encode_fns
[] = {
7235 Opcode_jx_Slot_inst_encode
, 0, 0
7238 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns
[] = {
7239 Opcode_l16ui_Slot_inst_encode
, 0, 0
7242 xtensa_opcode_encode_fn Opcode_l16si_encode_fns
[] = {
7243 Opcode_l16si_Slot_inst_encode
, 0, 0
7246 xtensa_opcode_encode_fn Opcode_l32i_encode_fns
[] = {
7247 Opcode_l32i_Slot_inst_encode
, 0, 0
7250 xtensa_opcode_encode_fn Opcode_l32r_encode_fns
[] = {
7251 Opcode_l32r_Slot_inst_encode
, 0, 0
7254 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns
[] = {
7255 Opcode_l8ui_Slot_inst_encode
, 0, 0
7258 xtensa_opcode_encode_fn Opcode_loop_encode_fns
[] = {
7259 Opcode_loop_Slot_inst_encode
, 0, 0
7262 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns
[] = {
7263 Opcode_loopnez_Slot_inst_encode
, 0, 0
7266 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns
[] = {
7267 Opcode_loopgtz_Slot_inst_encode
, 0, 0
7270 xtensa_opcode_encode_fn Opcode_movi_encode_fns
[] = {
7271 Opcode_movi_Slot_inst_encode
, 0, 0
7274 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns
[] = {
7275 Opcode_moveqz_Slot_inst_encode
, 0, 0
7278 xtensa_opcode_encode_fn Opcode_movnez_encode_fns
[] = {
7279 Opcode_movnez_Slot_inst_encode
, 0, 0
7282 xtensa_opcode_encode_fn Opcode_movltz_encode_fns
[] = {
7283 Opcode_movltz_Slot_inst_encode
, 0, 0
7286 xtensa_opcode_encode_fn Opcode_movgez_encode_fns
[] = {
7287 Opcode_movgez_Slot_inst_encode
, 0, 0
7290 xtensa_opcode_encode_fn Opcode_neg_encode_fns
[] = {
7291 Opcode_neg_Slot_inst_encode
, 0, 0
7294 xtensa_opcode_encode_fn Opcode_abs_encode_fns
[] = {
7295 Opcode_abs_Slot_inst_encode
, 0, 0
7298 xtensa_opcode_encode_fn Opcode_nop_encode_fns
[] = {
7299 Opcode_nop_Slot_inst_encode
, 0, 0
7302 xtensa_opcode_encode_fn Opcode_ret_encode_fns
[] = {
7303 Opcode_ret_Slot_inst_encode
, 0, 0
7306 xtensa_opcode_encode_fn Opcode_s16i_encode_fns
[] = {
7307 Opcode_s16i_Slot_inst_encode
, 0, 0
7310 xtensa_opcode_encode_fn Opcode_s32i_encode_fns
[] = {
7311 Opcode_s32i_Slot_inst_encode
, 0, 0
7314 xtensa_opcode_encode_fn Opcode_s8i_encode_fns
[] = {
7315 Opcode_s8i_Slot_inst_encode
, 0, 0
7318 xtensa_opcode_encode_fn Opcode_ssr_encode_fns
[] = {
7319 Opcode_ssr_Slot_inst_encode
, 0, 0
7322 xtensa_opcode_encode_fn Opcode_ssl_encode_fns
[] = {
7323 Opcode_ssl_Slot_inst_encode
, 0, 0
7326 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns
[] = {
7327 Opcode_ssa8l_Slot_inst_encode
, 0, 0
7330 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns
[] = {
7331 Opcode_ssa8b_Slot_inst_encode
, 0, 0
7334 xtensa_opcode_encode_fn Opcode_ssai_encode_fns
[] = {
7335 Opcode_ssai_Slot_inst_encode
, 0, 0
7338 xtensa_opcode_encode_fn Opcode_sll_encode_fns
[] = {
7339 Opcode_sll_Slot_inst_encode
, 0, 0
7342 xtensa_opcode_encode_fn Opcode_src_encode_fns
[] = {
7343 Opcode_src_Slot_inst_encode
, 0, 0
7346 xtensa_opcode_encode_fn Opcode_srl_encode_fns
[] = {
7347 Opcode_srl_Slot_inst_encode
, 0, 0
7350 xtensa_opcode_encode_fn Opcode_sra_encode_fns
[] = {
7351 Opcode_sra_Slot_inst_encode
, 0, 0
7354 xtensa_opcode_encode_fn Opcode_slli_encode_fns
[] = {
7355 Opcode_slli_Slot_inst_encode
, 0, 0
7358 xtensa_opcode_encode_fn Opcode_srai_encode_fns
[] = {
7359 Opcode_srai_Slot_inst_encode
, 0, 0
7362 xtensa_opcode_encode_fn Opcode_srli_encode_fns
[] = {
7363 Opcode_srli_Slot_inst_encode
, 0, 0
7366 xtensa_opcode_encode_fn Opcode_memw_encode_fns
[] = {
7367 Opcode_memw_Slot_inst_encode
, 0, 0
7370 xtensa_opcode_encode_fn Opcode_extw_encode_fns
[] = {
7371 Opcode_extw_Slot_inst_encode
, 0, 0
7374 xtensa_opcode_encode_fn Opcode_isync_encode_fns
[] = {
7375 Opcode_isync_Slot_inst_encode
, 0, 0
7378 xtensa_opcode_encode_fn Opcode_rsync_encode_fns
[] = {
7379 Opcode_rsync_Slot_inst_encode
, 0, 0
7382 xtensa_opcode_encode_fn Opcode_esync_encode_fns
[] = {
7383 Opcode_esync_Slot_inst_encode
, 0, 0
7386 xtensa_opcode_encode_fn Opcode_dsync_encode_fns
[] = {
7387 Opcode_dsync_Slot_inst_encode
, 0, 0
7390 xtensa_opcode_encode_fn Opcode_rsil_encode_fns
[] = {
7391 Opcode_rsil_Slot_inst_encode
, 0, 0
7394 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns
[] = {
7395 Opcode_rsr_lend_Slot_inst_encode
, 0, 0
7398 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns
[] = {
7399 Opcode_wsr_lend_Slot_inst_encode
, 0, 0
7402 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns
[] = {
7403 Opcode_xsr_lend_Slot_inst_encode
, 0, 0
7406 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns
[] = {
7407 Opcode_rsr_lcount_Slot_inst_encode
, 0, 0
7410 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns
[] = {
7411 Opcode_wsr_lcount_Slot_inst_encode
, 0, 0
7414 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns
[] = {
7415 Opcode_xsr_lcount_Slot_inst_encode
, 0, 0
7418 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns
[] = {
7419 Opcode_rsr_lbeg_Slot_inst_encode
, 0, 0
7422 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns
[] = {
7423 Opcode_wsr_lbeg_Slot_inst_encode
, 0, 0
7426 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns
[] = {
7427 Opcode_xsr_lbeg_Slot_inst_encode
, 0, 0
7430 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns
[] = {
7431 Opcode_rsr_sar_Slot_inst_encode
, 0, 0
7434 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns
[] = {
7435 Opcode_wsr_sar_Slot_inst_encode
, 0, 0
7438 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns
[] = {
7439 Opcode_xsr_sar_Slot_inst_encode
, 0, 0
7442 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns
[] = {
7443 Opcode_rsr_litbase_Slot_inst_encode
, 0, 0
7446 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns
[] = {
7447 Opcode_wsr_litbase_Slot_inst_encode
, 0, 0
7450 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns
[] = {
7451 Opcode_xsr_litbase_Slot_inst_encode
, 0, 0
7454 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns
[] = {
7455 Opcode_rsr_176_Slot_inst_encode
, 0, 0
7458 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns
[] = {
7459 Opcode_rsr_208_Slot_inst_encode
, 0, 0
7462 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns
[] = {
7463 Opcode_rsr_ps_Slot_inst_encode
, 0, 0
7466 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns
[] = {
7467 Opcode_wsr_ps_Slot_inst_encode
, 0, 0
7470 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns
[] = {
7471 Opcode_xsr_ps_Slot_inst_encode
, 0, 0
7474 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns
[] = {
7475 Opcode_rsr_epc1_Slot_inst_encode
, 0, 0
7478 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns
[] = {
7479 Opcode_wsr_epc1_Slot_inst_encode
, 0, 0
7482 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns
[] = {
7483 Opcode_xsr_epc1_Slot_inst_encode
, 0, 0
7486 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns
[] = {
7487 Opcode_rsr_excsave1_Slot_inst_encode
, 0, 0
7490 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns
[] = {
7491 Opcode_wsr_excsave1_Slot_inst_encode
, 0, 0
7494 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns
[] = {
7495 Opcode_xsr_excsave1_Slot_inst_encode
, 0, 0
7498 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns
[] = {
7499 Opcode_rsr_epc2_Slot_inst_encode
, 0, 0
7502 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns
[] = {
7503 Opcode_wsr_epc2_Slot_inst_encode
, 0, 0
7506 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns
[] = {
7507 Opcode_xsr_epc2_Slot_inst_encode
, 0, 0
7510 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns
[] = {
7511 Opcode_rsr_excsave2_Slot_inst_encode
, 0, 0
7514 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns
[] = {
7515 Opcode_wsr_excsave2_Slot_inst_encode
, 0, 0
7518 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns
[] = {
7519 Opcode_xsr_excsave2_Slot_inst_encode
, 0, 0
7522 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns
[] = {
7523 Opcode_rsr_epc3_Slot_inst_encode
, 0, 0
7526 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns
[] = {
7527 Opcode_wsr_epc3_Slot_inst_encode
, 0, 0
7530 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns
[] = {
7531 Opcode_xsr_epc3_Slot_inst_encode
, 0, 0
7534 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns
[] = {
7535 Opcode_rsr_excsave3_Slot_inst_encode
, 0, 0
7538 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns
[] = {
7539 Opcode_wsr_excsave3_Slot_inst_encode
, 0, 0
7542 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns
[] = {
7543 Opcode_xsr_excsave3_Slot_inst_encode
, 0, 0
7546 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns
[] = {
7547 Opcode_rsr_epc4_Slot_inst_encode
, 0, 0
7550 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns
[] = {
7551 Opcode_wsr_epc4_Slot_inst_encode
, 0, 0
7554 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns
[] = {
7555 Opcode_xsr_epc4_Slot_inst_encode
, 0, 0
7558 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns
[] = {
7559 Opcode_rsr_excsave4_Slot_inst_encode
, 0, 0
7562 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns
[] = {
7563 Opcode_wsr_excsave4_Slot_inst_encode
, 0, 0
7566 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns
[] = {
7567 Opcode_xsr_excsave4_Slot_inst_encode
, 0, 0
7570 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns
[] = {
7571 Opcode_rsr_eps2_Slot_inst_encode
, 0, 0
7574 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns
[] = {
7575 Opcode_wsr_eps2_Slot_inst_encode
, 0, 0
7578 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns
[] = {
7579 Opcode_xsr_eps2_Slot_inst_encode
, 0, 0
7582 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns
[] = {
7583 Opcode_rsr_eps3_Slot_inst_encode
, 0, 0
7586 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns
[] = {
7587 Opcode_wsr_eps3_Slot_inst_encode
, 0, 0
7590 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns
[] = {
7591 Opcode_xsr_eps3_Slot_inst_encode
, 0, 0
7594 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns
[] = {
7595 Opcode_rsr_eps4_Slot_inst_encode
, 0, 0
7598 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns
[] = {
7599 Opcode_wsr_eps4_Slot_inst_encode
, 0, 0
7602 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns
[] = {
7603 Opcode_xsr_eps4_Slot_inst_encode
, 0, 0
7606 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns
[] = {
7607 Opcode_rsr_excvaddr_Slot_inst_encode
, 0, 0
7610 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns
[] = {
7611 Opcode_wsr_excvaddr_Slot_inst_encode
, 0, 0
7614 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns
[] = {
7615 Opcode_xsr_excvaddr_Slot_inst_encode
, 0, 0
7618 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns
[] = {
7619 Opcode_rsr_depc_Slot_inst_encode
, 0, 0
7622 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns
[] = {
7623 Opcode_wsr_depc_Slot_inst_encode
, 0, 0
7626 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns
[] = {
7627 Opcode_xsr_depc_Slot_inst_encode
, 0, 0
7630 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns
[] = {
7631 Opcode_rsr_exccause_Slot_inst_encode
, 0, 0
7634 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns
[] = {
7635 Opcode_wsr_exccause_Slot_inst_encode
, 0, 0
7638 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns
[] = {
7639 Opcode_xsr_exccause_Slot_inst_encode
, 0, 0
7642 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns
[] = {
7643 Opcode_rsr_misc0_Slot_inst_encode
, 0, 0
7646 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns
[] = {
7647 Opcode_wsr_misc0_Slot_inst_encode
, 0, 0
7650 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns
[] = {
7651 Opcode_xsr_misc0_Slot_inst_encode
, 0, 0
7654 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns
[] = {
7655 Opcode_rsr_misc1_Slot_inst_encode
, 0, 0
7658 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns
[] = {
7659 Opcode_wsr_misc1_Slot_inst_encode
, 0, 0
7662 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns
[] = {
7663 Opcode_xsr_misc1_Slot_inst_encode
, 0, 0
7666 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns
[] = {
7667 Opcode_rsr_prid_Slot_inst_encode
, 0, 0
7670 xtensa_opcode_encode_fn Opcode_rfi_encode_fns
[] = {
7671 Opcode_rfi_Slot_inst_encode
, 0, 0
7674 xtensa_opcode_encode_fn Opcode_waiti_encode_fns
[] = {
7675 Opcode_waiti_Slot_inst_encode
, 0, 0
7678 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns
[] = {
7679 Opcode_rsr_interrupt_Slot_inst_encode
, 0, 0
7682 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns
[] = {
7683 Opcode_wsr_intset_Slot_inst_encode
, 0, 0
7686 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns
[] = {
7687 Opcode_wsr_intclear_Slot_inst_encode
, 0, 0
7690 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns
[] = {
7691 Opcode_rsr_intenable_Slot_inst_encode
, 0, 0
7694 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns
[] = {
7695 Opcode_wsr_intenable_Slot_inst_encode
, 0, 0
7698 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns
[] = {
7699 Opcode_xsr_intenable_Slot_inst_encode
, 0, 0
7702 xtensa_opcode_encode_fn Opcode_break_encode_fns
[] = {
7703 Opcode_break_Slot_inst_encode
, 0, 0
7706 xtensa_opcode_encode_fn Opcode_break_n_encode_fns
[] = {
7707 0, 0, Opcode_break_n_Slot_inst16b_encode
7710 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns
[] = {
7711 Opcode_rsr_dbreaka0_Slot_inst_encode
, 0, 0
7714 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns
[] = {
7715 Opcode_wsr_dbreaka0_Slot_inst_encode
, 0, 0
7718 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns
[] = {
7719 Opcode_xsr_dbreaka0_Slot_inst_encode
, 0, 0
7722 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns
[] = {
7723 Opcode_rsr_dbreakc0_Slot_inst_encode
, 0, 0
7726 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns
[] = {
7727 Opcode_wsr_dbreakc0_Slot_inst_encode
, 0, 0
7730 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns
[] = {
7731 Opcode_xsr_dbreakc0_Slot_inst_encode
, 0, 0
7734 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns
[] = {
7735 Opcode_rsr_dbreaka1_Slot_inst_encode
, 0, 0
7738 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns
[] = {
7739 Opcode_wsr_dbreaka1_Slot_inst_encode
, 0, 0
7742 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns
[] = {
7743 Opcode_xsr_dbreaka1_Slot_inst_encode
, 0, 0
7746 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns
[] = {
7747 Opcode_rsr_dbreakc1_Slot_inst_encode
, 0, 0
7750 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns
[] = {
7751 Opcode_wsr_dbreakc1_Slot_inst_encode
, 0, 0
7754 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns
[] = {
7755 Opcode_xsr_dbreakc1_Slot_inst_encode
, 0, 0
7758 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns
[] = {
7759 Opcode_rsr_ibreaka0_Slot_inst_encode
, 0, 0
7762 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns
[] = {
7763 Opcode_wsr_ibreaka0_Slot_inst_encode
, 0, 0
7766 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns
[] = {
7767 Opcode_xsr_ibreaka0_Slot_inst_encode
, 0, 0
7770 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns
[] = {
7771 Opcode_rsr_ibreaka1_Slot_inst_encode
, 0, 0
7774 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns
[] = {
7775 Opcode_wsr_ibreaka1_Slot_inst_encode
, 0, 0
7778 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns
[] = {
7779 Opcode_xsr_ibreaka1_Slot_inst_encode
, 0, 0
7782 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns
[] = {
7783 Opcode_rsr_ibreakenable_Slot_inst_encode
, 0, 0
7786 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns
[] = {
7787 Opcode_wsr_ibreakenable_Slot_inst_encode
, 0, 0
7790 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns
[] = {
7791 Opcode_xsr_ibreakenable_Slot_inst_encode
, 0, 0
7794 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns
[] = {
7795 Opcode_rsr_debugcause_Slot_inst_encode
, 0, 0
7798 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns
[] = {
7799 Opcode_wsr_debugcause_Slot_inst_encode
, 0, 0
7802 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns
[] = {
7803 Opcode_xsr_debugcause_Slot_inst_encode
, 0, 0
7806 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns
[] = {
7807 Opcode_rsr_icount_Slot_inst_encode
, 0, 0
7810 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns
[] = {
7811 Opcode_wsr_icount_Slot_inst_encode
, 0, 0
7814 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns
[] = {
7815 Opcode_xsr_icount_Slot_inst_encode
, 0, 0
7818 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns
[] = {
7819 Opcode_rsr_icountlevel_Slot_inst_encode
, 0, 0
7822 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns
[] = {
7823 Opcode_wsr_icountlevel_Slot_inst_encode
, 0, 0
7826 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns
[] = {
7827 Opcode_xsr_icountlevel_Slot_inst_encode
, 0, 0
7830 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns
[] = {
7831 Opcode_rsr_ddr_Slot_inst_encode
, 0, 0
7834 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns
[] = {
7835 Opcode_wsr_ddr_Slot_inst_encode
, 0, 0
7838 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns
[] = {
7839 Opcode_xsr_ddr_Slot_inst_encode
, 0, 0
7842 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns
[] = {
7843 Opcode_rfdo_Slot_inst_encode
, 0, 0
7846 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns
[] = {
7847 Opcode_rfdd_Slot_inst_encode
, 0, 0
7850 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns
[] = {
7851 Opcode_rsr_ccount_Slot_inst_encode
, 0, 0
7854 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns
[] = {
7855 Opcode_wsr_ccount_Slot_inst_encode
, 0, 0
7858 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns
[] = {
7859 Opcode_xsr_ccount_Slot_inst_encode
, 0, 0
7862 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns
[] = {
7863 Opcode_rsr_ccompare0_Slot_inst_encode
, 0, 0
7866 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns
[] = {
7867 Opcode_wsr_ccompare0_Slot_inst_encode
, 0, 0
7870 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns
[] = {
7871 Opcode_xsr_ccompare0_Slot_inst_encode
, 0, 0
7874 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns
[] = {
7875 Opcode_rsr_ccompare1_Slot_inst_encode
, 0, 0
7878 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns
[] = {
7879 Opcode_wsr_ccompare1_Slot_inst_encode
, 0, 0
7882 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns
[] = {
7883 Opcode_xsr_ccompare1_Slot_inst_encode
, 0, 0
7886 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns
[] = {
7887 Opcode_rsr_ccompare2_Slot_inst_encode
, 0, 0
7890 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns
[] = {
7891 Opcode_wsr_ccompare2_Slot_inst_encode
, 0, 0
7894 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns
[] = {
7895 Opcode_xsr_ccompare2_Slot_inst_encode
, 0, 0
7898 xtensa_opcode_encode_fn Opcode_ipf_encode_fns
[] = {
7899 Opcode_ipf_Slot_inst_encode
, 0, 0
7902 xtensa_opcode_encode_fn Opcode_ihi_encode_fns
[] = {
7903 Opcode_ihi_Slot_inst_encode
, 0, 0
7906 xtensa_opcode_encode_fn Opcode_iii_encode_fns
[] = {
7907 Opcode_iii_Slot_inst_encode
, 0, 0
7910 xtensa_opcode_encode_fn Opcode_lict_encode_fns
[] = {
7911 Opcode_lict_Slot_inst_encode
, 0, 0
7914 xtensa_opcode_encode_fn Opcode_licw_encode_fns
[] = {
7915 Opcode_licw_Slot_inst_encode
, 0, 0
7918 xtensa_opcode_encode_fn Opcode_sict_encode_fns
[] = {
7919 Opcode_sict_Slot_inst_encode
, 0, 0
7922 xtensa_opcode_encode_fn Opcode_sicw_encode_fns
[] = {
7923 Opcode_sicw_Slot_inst_encode
, 0, 0
7926 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns
[] = {
7927 Opcode_dhwb_Slot_inst_encode
, 0, 0
7930 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns
[] = {
7931 Opcode_dhwbi_Slot_inst_encode
, 0, 0
7934 xtensa_opcode_encode_fn Opcode_diwb_encode_fns
[] = {
7935 Opcode_diwb_Slot_inst_encode
, 0, 0
7938 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns
[] = {
7939 Opcode_diwbi_Slot_inst_encode
, 0, 0
7942 xtensa_opcode_encode_fn Opcode_dhi_encode_fns
[] = {
7943 Opcode_dhi_Slot_inst_encode
, 0, 0
7946 xtensa_opcode_encode_fn Opcode_dii_encode_fns
[] = {
7947 Opcode_dii_Slot_inst_encode
, 0, 0
7950 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns
[] = {
7951 Opcode_dpfr_Slot_inst_encode
, 0, 0
7954 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns
[] = {
7955 Opcode_dpfw_Slot_inst_encode
, 0, 0
7958 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns
[] = {
7959 Opcode_dpfro_Slot_inst_encode
, 0, 0
7962 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns
[] = {
7963 Opcode_dpfwo_Slot_inst_encode
, 0, 0
7966 xtensa_opcode_encode_fn Opcode_sdct_encode_fns
[] = {
7967 Opcode_sdct_Slot_inst_encode
, 0, 0
7970 xtensa_opcode_encode_fn Opcode_ldct_encode_fns
[] = {
7971 Opcode_ldct_Slot_inst_encode
, 0, 0
7974 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns
[] = {
7975 Opcode_wsr_ptevaddr_Slot_inst_encode
, 0, 0
7978 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns
[] = {
7979 Opcode_rsr_ptevaddr_Slot_inst_encode
, 0, 0
7982 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns
[] = {
7983 Opcode_xsr_ptevaddr_Slot_inst_encode
, 0, 0
7986 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns
[] = {
7987 Opcode_rsr_rasid_Slot_inst_encode
, 0, 0
7990 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns
[] = {
7991 Opcode_wsr_rasid_Slot_inst_encode
, 0, 0
7994 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns
[] = {
7995 Opcode_xsr_rasid_Slot_inst_encode
, 0, 0
7998 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns
[] = {
7999 Opcode_rsr_itlbcfg_Slot_inst_encode
, 0, 0
8002 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns
[] = {
8003 Opcode_wsr_itlbcfg_Slot_inst_encode
, 0, 0
8006 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns
[] = {
8007 Opcode_xsr_itlbcfg_Slot_inst_encode
, 0, 0
8010 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns
[] = {
8011 Opcode_rsr_dtlbcfg_Slot_inst_encode
, 0, 0
8014 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns
[] = {
8015 Opcode_wsr_dtlbcfg_Slot_inst_encode
, 0, 0
8018 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns
[] = {
8019 Opcode_xsr_dtlbcfg_Slot_inst_encode
, 0, 0
8022 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns
[] = {
8023 Opcode_idtlb_Slot_inst_encode
, 0, 0
8026 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns
[] = {
8027 Opcode_pdtlb_Slot_inst_encode
, 0, 0
8030 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns
[] = {
8031 Opcode_rdtlb0_Slot_inst_encode
, 0, 0
8034 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns
[] = {
8035 Opcode_rdtlb1_Slot_inst_encode
, 0, 0
8038 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns
[] = {
8039 Opcode_wdtlb_Slot_inst_encode
, 0, 0
8042 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns
[] = {
8043 Opcode_iitlb_Slot_inst_encode
, 0, 0
8046 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns
[] = {
8047 Opcode_pitlb_Slot_inst_encode
, 0, 0
8050 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns
[] = {
8051 Opcode_ritlb0_Slot_inst_encode
, 0, 0
8054 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns
[] = {
8055 Opcode_ritlb1_Slot_inst_encode
, 0, 0
8058 xtensa_opcode_encode_fn Opcode_witlb_encode_fns
[] = {
8059 Opcode_witlb_Slot_inst_encode
, 0, 0
8062 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns
[] = {
8063 Opcode_ldpte_Slot_inst_encode
, 0, 0
8066 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns
[] = {
8067 Opcode_hwwitlba_Slot_inst_encode
, 0, 0
8070 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns
[] = {
8071 Opcode_hwwdtlba_Slot_inst_encode
, 0, 0
8074 xtensa_opcode_encode_fn Opcode_nsa_encode_fns
[] = {
8075 Opcode_nsa_Slot_inst_encode
, 0, 0
8078 xtensa_opcode_encode_fn Opcode_nsau_encode_fns
[] = {
8079 Opcode_nsau_Slot_inst_encode
, 0, 0
8085 static xtensa_opcode_internal opcodes
[] = {
8086 { "excw", ICLASS_xt_iclass_excw
,
8088 Opcode_excw_encode_fns
, 0, 0 },
8089 { "rfe", ICLASS_xt_iclass_rfe
,
8090 XTENSA_OPCODE_IS_JUMP
,
8091 Opcode_rfe_encode_fns
, 0, 0 },
8092 { "rfde", ICLASS_xt_iclass_rfde
,
8093 XTENSA_OPCODE_IS_JUMP
,
8094 Opcode_rfde_encode_fns
, 0, 0 },
8095 { "syscall", ICLASS_xt_iclass_syscall
,
8097 Opcode_syscall_encode_fns
, 0, 0 },
8098 { "simcall", ICLASS_xt_iclass_simcall
,
8100 Opcode_simcall_encode_fns
, 0, 0 },
8101 { "call12", ICLASS_xt_iclass_call12
,
8102 XTENSA_OPCODE_IS_CALL
,
8103 Opcode_call12_encode_fns
, 0, 0 },
8104 { "call8", ICLASS_xt_iclass_call8
,
8105 XTENSA_OPCODE_IS_CALL
,
8106 Opcode_call8_encode_fns
, 0, 0 },
8107 { "call4", ICLASS_xt_iclass_call4
,
8108 XTENSA_OPCODE_IS_CALL
,
8109 Opcode_call4_encode_fns
, 0, 0 },
8110 { "callx12", ICLASS_xt_iclass_callx12
,
8111 XTENSA_OPCODE_IS_CALL
,
8112 Opcode_callx12_encode_fns
, 0, 0 },
8113 { "callx8", ICLASS_xt_iclass_callx8
,
8114 XTENSA_OPCODE_IS_CALL
,
8115 Opcode_callx8_encode_fns
, 0, 0 },
8116 { "callx4", ICLASS_xt_iclass_callx4
,
8117 XTENSA_OPCODE_IS_CALL
,
8118 Opcode_callx4_encode_fns
, 0, 0 },
8119 { "entry", ICLASS_xt_iclass_entry
,
8121 Opcode_entry_encode_fns
, 0, 0 },
8122 { "movsp", ICLASS_xt_iclass_movsp
,
8124 Opcode_movsp_encode_fns
, 0, 0 },
8125 { "rotw", ICLASS_xt_iclass_rotw
,
8127 Opcode_rotw_encode_fns
, 0, 0 },
8128 { "retw", ICLASS_xt_iclass_retw
,
8129 XTENSA_OPCODE_IS_JUMP
,
8130 Opcode_retw_encode_fns
, 0, 0 },
8131 { "retw.n", ICLASS_xt_iclass_retw
,
8132 XTENSA_OPCODE_IS_JUMP
,
8133 Opcode_retw_n_encode_fns
, 0, 0 },
8134 { "rfwo", ICLASS_xt_iclass_rfwou
,
8135 XTENSA_OPCODE_IS_JUMP
,
8136 Opcode_rfwo_encode_fns
, 0, 0 },
8137 { "rfwu", ICLASS_xt_iclass_rfwou
,
8138 XTENSA_OPCODE_IS_JUMP
,
8139 Opcode_rfwu_encode_fns
, 0, 0 },
8140 { "l32e", ICLASS_xt_iclass_l32e
,
8142 Opcode_l32e_encode_fns
, 0, 0 },
8143 { "s32e", ICLASS_xt_iclass_s32e
,
8145 Opcode_s32e_encode_fns
, 0, 0 },
8146 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase
,
8148 Opcode_rsr_windowbase_encode_fns
, 0, 0 },
8149 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase
,
8151 Opcode_wsr_windowbase_encode_fns
, 0, 0 },
8152 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase
,
8154 Opcode_xsr_windowbase_encode_fns
, 0, 0 },
8155 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart
,
8157 Opcode_rsr_windowstart_encode_fns
, 0, 0 },
8158 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart
,
8160 Opcode_wsr_windowstart_encode_fns
, 0, 0 },
8161 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart
,
8163 Opcode_xsr_windowstart_encode_fns
, 0, 0 },
8164 { "add.n", ICLASS_xt_iclass_add_n
,
8166 Opcode_add_n_encode_fns
, 0, 0 },
8167 { "addi.n", ICLASS_xt_iclass_addi_n
,
8169 Opcode_addi_n_encode_fns
, 0, 0 },
8170 { "beqz.n", ICLASS_xt_iclass_bz6
,
8171 XTENSA_OPCODE_IS_BRANCH
,
8172 Opcode_beqz_n_encode_fns
, 0, 0 },
8173 { "bnez.n", ICLASS_xt_iclass_bz6
,
8174 XTENSA_OPCODE_IS_BRANCH
,
8175 Opcode_bnez_n_encode_fns
, 0, 0 },
8176 { "ill.n", ICLASS_xt_iclass_ill_n
,
8178 Opcode_ill_n_encode_fns
, 0, 0 },
8179 { "l32i.n", ICLASS_xt_iclass_loadi4
,
8181 Opcode_l32i_n_encode_fns
, 0, 0 },
8182 { "mov.n", ICLASS_xt_iclass_mov_n
,
8184 Opcode_mov_n_encode_fns
, 0, 0 },
8185 { "movi.n", ICLASS_xt_iclass_movi_n
,
8187 Opcode_movi_n_encode_fns
, 0, 0 },
8188 { "nop.n", ICLASS_xt_iclass_nopn
,
8190 Opcode_nop_n_encode_fns
, 0, 0 },
8191 { "ret.n", ICLASS_xt_iclass_retn
,
8192 XTENSA_OPCODE_IS_JUMP
,
8193 Opcode_ret_n_encode_fns
, 0, 0 },
8194 { "s32i.n", ICLASS_xt_iclass_storei4
,
8196 Opcode_s32i_n_encode_fns
, 0, 0 },
8197 { "addi", ICLASS_xt_iclass_addi
,
8199 Opcode_addi_encode_fns
, 0, 0 },
8200 { "addmi", ICLASS_xt_iclass_addmi
,
8202 Opcode_addmi_encode_fns
, 0, 0 },
8203 { "add", ICLASS_xt_iclass_addsub
,
8205 Opcode_add_encode_fns
, 0, 0 },
8206 { "sub", ICLASS_xt_iclass_addsub
,
8208 Opcode_sub_encode_fns
, 0, 0 },
8209 { "addx2", ICLASS_xt_iclass_addsub
,
8211 Opcode_addx2_encode_fns
, 0, 0 },
8212 { "addx4", ICLASS_xt_iclass_addsub
,
8214 Opcode_addx4_encode_fns
, 0, 0 },
8215 { "addx8", ICLASS_xt_iclass_addsub
,
8217 Opcode_addx8_encode_fns
, 0, 0 },
8218 { "subx2", ICLASS_xt_iclass_addsub
,
8220 Opcode_subx2_encode_fns
, 0, 0 },
8221 { "subx4", ICLASS_xt_iclass_addsub
,
8223 Opcode_subx4_encode_fns
, 0, 0 },
8224 { "subx8", ICLASS_xt_iclass_addsub
,
8226 Opcode_subx8_encode_fns
, 0, 0 },
8227 { "and", ICLASS_xt_iclass_bit
,
8229 Opcode_and_encode_fns
, 0, 0 },
8230 { "or", ICLASS_xt_iclass_bit
,
8232 Opcode_or_encode_fns
, 0, 0 },
8233 { "xor", ICLASS_xt_iclass_bit
,
8235 Opcode_xor_encode_fns
, 0, 0 },
8236 { "beqi", ICLASS_xt_iclass_bsi8
,
8237 XTENSA_OPCODE_IS_BRANCH
,
8238 Opcode_beqi_encode_fns
, 0, 0 },
8239 { "bnei", ICLASS_xt_iclass_bsi8
,
8240 XTENSA_OPCODE_IS_BRANCH
,
8241 Opcode_bnei_encode_fns
, 0, 0 },
8242 { "bgei", ICLASS_xt_iclass_bsi8
,
8243 XTENSA_OPCODE_IS_BRANCH
,
8244 Opcode_bgei_encode_fns
, 0, 0 },
8245 { "blti", ICLASS_xt_iclass_bsi8
,
8246 XTENSA_OPCODE_IS_BRANCH
,
8247 Opcode_blti_encode_fns
, 0, 0 },
8248 { "bbci", ICLASS_xt_iclass_bsi8b
,
8249 XTENSA_OPCODE_IS_BRANCH
,
8250 Opcode_bbci_encode_fns
, 0, 0 },
8251 { "bbsi", ICLASS_xt_iclass_bsi8b
,
8252 XTENSA_OPCODE_IS_BRANCH
,
8253 Opcode_bbsi_encode_fns
, 0, 0 },
8254 { "bgeui", ICLASS_xt_iclass_bsi8u
,
8255 XTENSA_OPCODE_IS_BRANCH
,
8256 Opcode_bgeui_encode_fns
, 0, 0 },
8257 { "bltui", ICLASS_xt_iclass_bsi8u
,
8258 XTENSA_OPCODE_IS_BRANCH
,
8259 Opcode_bltui_encode_fns
, 0, 0 },
8260 { "beq", ICLASS_xt_iclass_bst8
,
8261 XTENSA_OPCODE_IS_BRANCH
,
8262 Opcode_beq_encode_fns
, 0, 0 },
8263 { "bne", ICLASS_xt_iclass_bst8
,
8264 XTENSA_OPCODE_IS_BRANCH
,
8265 Opcode_bne_encode_fns
, 0, 0 },
8266 { "bge", ICLASS_xt_iclass_bst8
,
8267 XTENSA_OPCODE_IS_BRANCH
,
8268 Opcode_bge_encode_fns
, 0, 0 },
8269 { "blt", ICLASS_xt_iclass_bst8
,
8270 XTENSA_OPCODE_IS_BRANCH
,
8271 Opcode_blt_encode_fns
, 0, 0 },
8272 { "bgeu", ICLASS_xt_iclass_bst8
,
8273 XTENSA_OPCODE_IS_BRANCH
,
8274 Opcode_bgeu_encode_fns
, 0, 0 },
8275 { "bltu", ICLASS_xt_iclass_bst8
,
8276 XTENSA_OPCODE_IS_BRANCH
,
8277 Opcode_bltu_encode_fns
, 0, 0 },
8278 { "bany", ICLASS_xt_iclass_bst8
,
8279 XTENSA_OPCODE_IS_BRANCH
,
8280 Opcode_bany_encode_fns
, 0, 0 },
8281 { "bnone", ICLASS_xt_iclass_bst8
,
8282 XTENSA_OPCODE_IS_BRANCH
,
8283 Opcode_bnone_encode_fns
, 0, 0 },
8284 { "ball", ICLASS_xt_iclass_bst8
,
8285 XTENSA_OPCODE_IS_BRANCH
,
8286 Opcode_ball_encode_fns
, 0, 0 },
8287 { "bnall", ICLASS_xt_iclass_bst8
,
8288 XTENSA_OPCODE_IS_BRANCH
,
8289 Opcode_bnall_encode_fns
, 0, 0 },
8290 { "bbc", ICLASS_xt_iclass_bst8
,
8291 XTENSA_OPCODE_IS_BRANCH
,
8292 Opcode_bbc_encode_fns
, 0, 0 },
8293 { "bbs", ICLASS_xt_iclass_bst8
,
8294 XTENSA_OPCODE_IS_BRANCH
,
8295 Opcode_bbs_encode_fns
, 0, 0 },
8296 { "beqz", ICLASS_xt_iclass_bsz12
,
8297 XTENSA_OPCODE_IS_BRANCH
,
8298 Opcode_beqz_encode_fns
, 0, 0 },
8299 { "bnez", ICLASS_xt_iclass_bsz12
,
8300 XTENSA_OPCODE_IS_BRANCH
,
8301 Opcode_bnez_encode_fns
, 0, 0 },
8302 { "bgez", ICLASS_xt_iclass_bsz12
,
8303 XTENSA_OPCODE_IS_BRANCH
,
8304 Opcode_bgez_encode_fns
, 0, 0 },
8305 { "bltz", ICLASS_xt_iclass_bsz12
,
8306 XTENSA_OPCODE_IS_BRANCH
,
8307 Opcode_bltz_encode_fns
, 0, 0 },
8308 { "call0", ICLASS_xt_iclass_call0
,
8309 XTENSA_OPCODE_IS_CALL
,
8310 Opcode_call0_encode_fns
, 0, 0 },
8311 { "callx0", ICLASS_xt_iclass_callx0
,
8312 XTENSA_OPCODE_IS_CALL
,
8313 Opcode_callx0_encode_fns
, 0, 0 },
8314 { "extui", ICLASS_xt_iclass_exti
,
8316 Opcode_extui_encode_fns
, 0, 0 },
8317 { "ill", ICLASS_xt_iclass_ill
,
8319 Opcode_ill_encode_fns
, 0, 0 },
8320 { "j", ICLASS_xt_iclass_jump
,
8321 XTENSA_OPCODE_IS_JUMP
,
8322 Opcode_j_encode_fns
, 0, 0 },
8323 { "jx", ICLASS_xt_iclass_jumpx
,
8324 XTENSA_OPCODE_IS_JUMP
,
8325 Opcode_jx_encode_fns
, 0, 0 },
8326 { "l16ui", ICLASS_xt_iclass_l16ui
,
8328 Opcode_l16ui_encode_fns
, 0, 0 },
8329 { "l16si", ICLASS_xt_iclass_l16si
,
8331 Opcode_l16si_encode_fns
, 0, 0 },
8332 { "l32i", ICLASS_xt_iclass_l32i
,
8334 Opcode_l32i_encode_fns
, 0, 0 },
8335 { "l32r", ICLASS_xt_iclass_l32r
,
8337 Opcode_l32r_encode_fns
, 0, 0 },
8338 { "l8ui", ICLASS_xt_iclass_l8i
,
8340 Opcode_l8ui_encode_fns
, 0, 0 },
8341 { "loop", ICLASS_xt_iclass_loop
,
8342 XTENSA_OPCODE_IS_LOOP
,
8343 Opcode_loop_encode_fns
, 0, 0 },
8344 { "loopnez", ICLASS_xt_iclass_loopz
,
8345 XTENSA_OPCODE_IS_LOOP
,
8346 Opcode_loopnez_encode_fns
, 0, 0 },
8347 { "loopgtz", ICLASS_xt_iclass_loopz
,
8348 XTENSA_OPCODE_IS_LOOP
,
8349 Opcode_loopgtz_encode_fns
, 0, 0 },
8350 { "movi", ICLASS_xt_iclass_movi
,
8352 Opcode_movi_encode_fns
, 0, 0 },
8353 { "moveqz", ICLASS_xt_iclass_movz
,
8355 Opcode_moveqz_encode_fns
, 0, 0 },
8356 { "movnez", ICLASS_xt_iclass_movz
,
8358 Opcode_movnez_encode_fns
, 0, 0 },
8359 { "movltz", ICLASS_xt_iclass_movz
,
8361 Opcode_movltz_encode_fns
, 0, 0 },
8362 { "movgez", ICLASS_xt_iclass_movz
,
8364 Opcode_movgez_encode_fns
, 0, 0 },
8365 { "neg", ICLASS_xt_iclass_neg
,
8367 Opcode_neg_encode_fns
, 0, 0 },
8368 { "abs", ICLASS_xt_iclass_neg
,
8370 Opcode_abs_encode_fns
, 0, 0 },
8371 { "nop", ICLASS_xt_iclass_nop
,
8373 Opcode_nop_encode_fns
, 0, 0 },
8374 { "ret", ICLASS_xt_iclass_return
,
8375 XTENSA_OPCODE_IS_JUMP
,
8376 Opcode_ret_encode_fns
, 0, 0 },
8377 { "s16i", ICLASS_xt_iclass_s16i
,
8379 Opcode_s16i_encode_fns
, 0, 0 },
8380 { "s32i", ICLASS_xt_iclass_s32i
,
8382 Opcode_s32i_encode_fns
, 0, 0 },
8383 { "s8i", ICLASS_xt_iclass_s8i
,
8385 Opcode_s8i_encode_fns
, 0, 0 },
8386 { "ssr", ICLASS_xt_iclass_sar
,
8388 Opcode_ssr_encode_fns
, 0, 0 },
8389 { "ssl", ICLASS_xt_iclass_sar
,
8391 Opcode_ssl_encode_fns
, 0, 0 },
8392 { "ssa8l", ICLASS_xt_iclass_sar
,
8394 Opcode_ssa8l_encode_fns
, 0, 0 },
8395 { "ssa8b", ICLASS_xt_iclass_sar
,
8397 Opcode_ssa8b_encode_fns
, 0, 0 },
8398 { "ssai", ICLASS_xt_iclass_sari
,
8400 Opcode_ssai_encode_fns
, 0, 0 },
8401 { "sll", ICLASS_xt_iclass_shifts
,
8403 Opcode_sll_encode_fns
, 0, 0 },
8404 { "src", ICLASS_xt_iclass_shiftst
,
8406 Opcode_src_encode_fns
, 0, 0 },
8407 { "srl", ICLASS_xt_iclass_shiftt
,
8409 Opcode_srl_encode_fns
, 0, 0 },
8410 { "sra", ICLASS_xt_iclass_shiftt
,
8412 Opcode_sra_encode_fns
, 0, 0 },
8413 { "slli", ICLASS_xt_iclass_slli
,
8415 Opcode_slli_encode_fns
, 0, 0 },
8416 { "srai", ICLASS_xt_iclass_srai
,
8418 Opcode_srai_encode_fns
, 0, 0 },
8419 { "srli", ICLASS_xt_iclass_srli
,
8421 Opcode_srli_encode_fns
, 0, 0 },
8422 { "memw", ICLASS_xt_iclass_memw
,
8424 Opcode_memw_encode_fns
, 0, 0 },
8425 { "extw", ICLASS_xt_iclass_extw
,
8427 Opcode_extw_encode_fns
, 0, 0 },
8428 { "isync", ICLASS_xt_iclass_isync
,
8430 Opcode_isync_encode_fns
, 0, 0 },
8431 { "rsync", ICLASS_xt_iclass_sync
,
8433 Opcode_rsync_encode_fns
, 0, 0 },
8434 { "esync", ICLASS_xt_iclass_sync
,
8436 Opcode_esync_encode_fns
, 0, 0 },
8437 { "dsync", ICLASS_xt_iclass_sync
,
8439 Opcode_dsync_encode_fns
, 0, 0 },
8440 { "rsil", ICLASS_xt_iclass_rsil
,
8442 Opcode_rsil_encode_fns
, 0, 0 },
8443 { "rsr.lend", ICLASS_xt_iclass_rsr_lend
,
8445 Opcode_rsr_lend_encode_fns
, 0, 0 },
8446 { "wsr.lend", ICLASS_xt_iclass_wsr_lend
,
8448 Opcode_wsr_lend_encode_fns
, 0, 0 },
8449 { "xsr.lend", ICLASS_xt_iclass_xsr_lend
,
8451 Opcode_xsr_lend_encode_fns
, 0, 0 },
8452 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount
,
8454 Opcode_rsr_lcount_encode_fns
, 0, 0 },
8455 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount
,
8457 Opcode_wsr_lcount_encode_fns
, 0, 0 },
8458 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount
,
8460 Opcode_xsr_lcount_encode_fns
, 0, 0 },
8461 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg
,
8463 Opcode_rsr_lbeg_encode_fns
, 0, 0 },
8464 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg
,
8466 Opcode_wsr_lbeg_encode_fns
, 0, 0 },
8467 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg
,
8469 Opcode_xsr_lbeg_encode_fns
, 0, 0 },
8470 { "rsr.sar", ICLASS_xt_iclass_rsr_sar
,
8472 Opcode_rsr_sar_encode_fns
, 0, 0 },
8473 { "wsr.sar", ICLASS_xt_iclass_wsr_sar
,
8475 Opcode_wsr_sar_encode_fns
, 0, 0 },
8476 { "xsr.sar", ICLASS_xt_iclass_xsr_sar
,
8478 Opcode_xsr_sar_encode_fns
, 0, 0 },
8479 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase
,
8481 Opcode_rsr_litbase_encode_fns
, 0, 0 },
8482 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase
,
8484 Opcode_wsr_litbase_encode_fns
, 0, 0 },
8485 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase
,
8487 Opcode_xsr_litbase_encode_fns
, 0, 0 },
8488 { "rsr.176", ICLASS_xt_iclass_rsr_176
,
8490 Opcode_rsr_176_encode_fns
, 0, 0 },
8491 { "rsr.208", ICLASS_xt_iclass_rsr_208
,
8493 Opcode_rsr_208_encode_fns
, 0, 0 },
8494 { "rsr.ps", ICLASS_xt_iclass_rsr_ps
,
8496 Opcode_rsr_ps_encode_fns
, 0, 0 },
8497 { "wsr.ps", ICLASS_xt_iclass_wsr_ps
,
8499 Opcode_wsr_ps_encode_fns
, 0, 0 },
8500 { "xsr.ps", ICLASS_xt_iclass_xsr_ps
,
8502 Opcode_xsr_ps_encode_fns
, 0, 0 },
8503 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1
,
8505 Opcode_rsr_epc1_encode_fns
, 0, 0 },
8506 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1
,
8508 Opcode_wsr_epc1_encode_fns
, 0, 0 },
8509 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1
,
8511 Opcode_xsr_epc1_encode_fns
, 0, 0 },
8512 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1
,
8514 Opcode_rsr_excsave1_encode_fns
, 0, 0 },
8515 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1
,
8517 Opcode_wsr_excsave1_encode_fns
, 0, 0 },
8518 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1
,
8520 Opcode_xsr_excsave1_encode_fns
, 0, 0 },
8521 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2
,
8523 Opcode_rsr_epc2_encode_fns
, 0, 0 },
8524 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2
,
8526 Opcode_wsr_epc2_encode_fns
, 0, 0 },
8527 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2
,
8529 Opcode_xsr_epc2_encode_fns
, 0, 0 },
8530 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2
,
8532 Opcode_rsr_excsave2_encode_fns
, 0, 0 },
8533 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2
,
8535 Opcode_wsr_excsave2_encode_fns
, 0, 0 },
8536 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2
,
8538 Opcode_xsr_excsave2_encode_fns
, 0, 0 },
8539 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3
,
8541 Opcode_rsr_epc3_encode_fns
, 0, 0 },
8542 { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3
,
8544 Opcode_wsr_epc3_encode_fns
, 0, 0 },
8545 { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3
,
8547 Opcode_xsr_epc3_encode_fns
, 0, 0 },
8548 { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3
,
8550 Opcode_rsr_excsave3_encode_fns
, 0, 0 },
8551 { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3
,
8553 Opcode_wsr_excsave3_encode_fns
, 0, 0 },
8554 { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3
,
8556 Opcode_xsr_excsave3_encode_fns
, 0, 0 },
8557 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4
,
8559 Opcode_rsr_epc4_encode_fns
, 0, 0 },
8560 { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4
,
8562 Opcode_wsr_epc4_encode_fns
, 0, 0 },
8563 { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4
,
8565 Opcode_xsr_epc4_encode_fns
, 0, 0 },
8566 { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4
,
8568 Opcode_rsr_excsave4_encode_fns
, 0, 0 },
8569 { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4
,
8571 Opcode_wsr_excsave4_encode_fns
, 0, 0 },
8572 { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4
,
8574 Opcode_xsr_excsave4_encode_fns
, 0, 0 },
8575 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2
,
8577 Opcode_rsr_eps2_encode_fns
, 0, 0 },
8578 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2
,
8580 Opcode_wsr_eps2_encode_fns
, 0, 0 },
8581 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2
,
8583 Opcode_xsr_eps2_encode_fns
, 0, 0 },
8584 { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3
,
8586 Opcode_rsr_eps3_encode_fns
, 0, 0 },
8587 { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3
,
8589 Opcode_wsr_eps3_encode_fns
, 0, 0 },
8590 { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3
,
8592 Opcode_xsr_eps3_encode_fns
, 0, 0 },
8593 { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4
,
8595 Opcode_rsr_eps4_encode_fns
, 0, 0 },
8596 { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4
,
8598 Opcode_wsr_eps4_encode_fns
, 0, 0 },
8599 { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4
,
8601 Opcode_xsr_eps4_encode_fns
, 0, 0 },
8602 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr
,
8604 Opcode_rsr_excvaddr_encode_fns
, 0, 0 },
8605 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr
,
8607 Opcode_wsr_excvaddr_encode_fns
, 0, 0 },
8608 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr
,
8610 Opcode_xsr_excvaddr_encode_fns
, 0, 0 },
8611 { "rsr.depc", ICLASS_xt_iclass_rsr_depc
,
8613 Opcode_rsr_depc_encode_fns
, 0, 0 },
8614 { "wsr.depc", ICLASS_xt_iclass_wsr_depc
,
8616 Opcode_wsr_depc_encode_fns
, 0, 0 },
8617 { "xsr.depc", ICLASS_xt_iclass_xsr_depc
,
8619 Opcode_xsr_depc_encode_fns
, 0, 0 },
8620 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause
,
8622 Opcode_rsr_exccause_encode_fns
, 0, 0 },
8623 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause
,
8625 Opcode_wsr_exccause_encode_fns
, 0, 0 },
8626 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause
,
8628 Opcode_xsr_exccause_encode_fns
, 0, 0 },
8629 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0
,
8631 Opcode_rsr_misc0_encode_fns
, 0, 0 },
8632 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0
,
8634 Opcode_wsr_misc0_encode_fns
, 0, 0 },
8635 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0
,
8637 Opcode_xsr_misc0_encode_fns
, 0, 0 },
8638 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1
,
8640 Opcode_rsr_misc1_encode_fns
, 0, 0 },
8641 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1
,
8643 Opcode_wsr_misc1_encode_fns
, 0, 0 },
8644 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1
,
8646 Opcode_xsr_misc1_encode_fns
, 0, 0 },
8647 { "rsr.prid", ICLASS_xt_iclass_rsr_prid
,
8649 Opcode_rsr_prid_encode_fns
, 0, 0 },
8650 { "rfi", ICLASS_xt_iclass_rfi
,
8651 XTENSA_OPCODE_IS_JUMP
,
8652 Opcode_rfi_encode_fns
, 0, 0 },
8653 { "waiti", ICLASS_xt_iclass_wait
,
8655 Opcode_waiti_encode_fns
, 0, 0 },
8656 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt
,
8658 Opcode_rsr_interrupt_encode_fns
, 0, 0 },
8659 { "wsr.intset", ICLASS_xt_iclass_wsr_intset
,
8661 Opcode_wsr_intset_encode_fns
, 0, 0 },
8662 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear
,
8664 Opcode_wsr_intclear_encode_fns
, 0, 0 },
8665 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable
,
8667 Opcode_rsr_intenable_encode_fns
, 0, 0 },
8668 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable
,
8670 Opcode_wsr_intenable_encode_fns
, 0, 0 },
8671 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable
,
8673 Opcode_xsr_intenable_encode_fns
, 0, 0 },
8674 { "break", ICLASS_xt_iclass_break
,
8676 Opcode_break_encode_fns
, 0, 0 },
8677 { "break.n", ICLASS_xt_iclass_break_n
,
8679 Opcode_break_n_encode_fns
, 0, 0 },
8680 { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0
,
8682 Opcode_rsr_dbreaka0_encode_fns
, 0, 0 },
8683 { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0
,
8685 Opcode_wsr_dbreaka0_encode_fns
, 0, 0 },
8686 { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0
,
8688 Opcode_xsr_dbreaka0_encode_fns
, 0, 0 },
8689 { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0
,
8691 Opcode_rsr_dbreakc0_encode_fns
, 0, 0 },
8692 { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0
,
8694 Opcode_wsr_dbreakc0_encode_fns
, 0, 0 },
8695 { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0
,
8697 Opcode_xsr_dbreakc0_encode_fns
, 0, 0 },
8698 { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1
,
8700 Opcode_rsr_dbreaka1_encode_fns
, 0, 0 },
8701 { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1
,
8703 Opcode_wsr_dbreaka1_encode_fns
, 0, 0 },
8704 { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1
,
8706 Opcode_xsr_dbreaka1_encode_fns
, 0, 0 },
8707 { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1
,
8709 Opcode_rsr_dbreakc1_encode_fns
, 0, 0 },
8710 { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1
,
8712 Opcode_wsr_dbreakc1_encode_fns
, 0, 0 },
8713 { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1
,
8715 Opcode_xsr_dbreakc1_encode_fns
, 0, 0 },
8716 { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0
,
8718 Opcode_rsr_ibreaka0_encode_fns
, 0, 0 },
8719 { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0
,
8721 Opcode_wsr_ibreaka0_encode_fns
, 0, 0 },
8722 { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0
,
8724 Opcode_xsr_ibreaka0_encode_fns
, 0, 0 },
8725 { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1
,
8727 Opcode_rsr_ibreaka1_encode_fns
, 0, 0 },
8728 { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1
,
8730 Opcode_wsr_ibreaka1_encode_fns
, 0, 0 },
8731 { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1
,
8733 Opcode_xsr_ibreaka1_encode_fns
, 0, 0 },
8734 { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable
,
8736 Opcode_rsr_ibreakenable_encode_fns
, 0, 0 },
8737 { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable
,
8739 Opcode_wsr_ibreakenable_encode_fns
, 0, 0 },
8740 { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable
,
8742 Opcode_xsr_ibreakenable_encode_fns
, 0, 0 },
8743 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause
,
8745 Opcode_rsr_debugcause_encode_fns
, 0, 0 },
8746 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause
,
8748 Opcode_wsr_debugcause_encode_fns
, 0, 0 },
8749 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause
,
8751 Opcode_xsr_debugcause_encode_fns
, 0, 0 },
8752 { "rsr.icount", ICLASS_xt_iclass_rsr_icount
,
8754 Opcode_rsr_icount_encode_fns
, 0, 0 },
8755 { "wsr.icount", ICLASS_xt_iclass_wsr_icount
,
8757 Opcode_wsr_icount_encode_fns
, 0, 0 },
8758 { "xsr.icount", ICLASS_xt_iclass_xsr_icount
,
8760 Opcode_xsr_icount_encode_fns
, 0, 0 },
8761 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel
,
8763 Opcode_rsr_icountlevel_encode_fns
, 0, 0 },
8764 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel
,
8766 Opcode_wsr_icountlevel_encode_fns
, 0, 0 },
8767 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel
,
8769 Opcode_xsr_icountlevel_encode_fns
, 0, 0 },
8770 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr
,
8772 Opcode_rsr_ddr_encode_fns
, 0, 0 },
8773 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr
,
8775 Opcode_wsr_ddr_encode_fns
, 0, 0 },
8776 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr
,
8778 Opcode_xsr_ddr_encode_fns
, 0, 0 },
8779 { "rfdo", ICLASS_xt_iclass_rfdo
,
8780 XTENSA_OPCODE_IS_JUMP
,
8781 Opcode_rfdo_encode_fns
, 0, 0 },
8782 { "rfdd", ICLASS_xt_iclass_rfdd
,
8783 XTENSA_OPCODE_IS_JUMP
,
8784 Opcode_rfdd_encode_fns
, 0, 0 },
8785 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount
,
8787 Opcode_rsr_ccount_encode_fns
, 0, 0 },
8788 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount
,
8790 Opcode_wsr_ccount_encode_fns
, 0, 0 },
8791 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount
,
8793 Opcode_xsr_ccount_encode_fns
, 0, 0 },
8794 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0
,
8796 Opcode_rsr_ccompare0_encode_fns
, 0, 0 },
8797 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0
,
8799 Opcode_wsr_ccompare0_encode_fns
, 0, 0 },
8800 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0
,
8802 Opcode_xsr_ccompare0_encode_fns
, 0, 0 },
8803 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1
,
8805 Opcode_rsr_ccompare1_encode_fns
, 0, 0 },
8806 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1
,
8808 Opcode_wsr_ccompare1_encode_fns
, 0, 0 },
8809 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1
,
8811 Opcode_xsr_ccompare1_encode_fns
, 0, 0 },
8812 { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2
,
8814 Opcode_rsr_ccompare2_encode_fns
, 0, 0 },
8815 { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2
,
8817 Opcode_wsr_ccompare2_encode_fns
, 0, 0 },
8818 { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2
,
8820 Opcode_xsr_ccompare2_encode_fns
, 0, 0 },
8821 { "ipf", ICLASS_xt_iclass_icache
,
8823 Opcode_ipf_encode_fns
, 0, 0 },
8824 { "ihi", ICLASS_xt_iclass_icache
,
8826 Opcode_ihi_encode_fns
, 0, 0 },
8827 { "iii", ICLASS_xt_iclass_icache_inv
,
8829 Opcode_iii_encode_fns
, 0, 0 },
8830 { "lict", ICLASS_xt_iclass_licx
,
8832 Opcode_lict_encode_fns
, 0, 0 },
8833 { "licw", ICLASS_xt_iclass_licx
,
8835 Opcode_licw_encode_fns
, 0, 0 },
8836 { "sict", ICLASS_xt_iclass_sicx
,
8838 Opcode_sict_encode_fns
, 0, 0 },
8839 { "sicw", ICLASS_xt_iclass_sicx
,
8841 Opcode_sicw_encode_fns
, 0, 0 },
8842 { "dhwb", ICLASS_xt_iclass_dcache
,
8844 Opcode_dhwb_encode_fns
, 0, 0 },
8845 { "dhwbi", ICLASS_xt_iclass_dcache
,
8847 Opcode_dhwbi_encode_fns
, 0, 0 },
8848 { "diwb", ICLASS_xt_iclass_dcache_ind
,
8850 Opcode_diwb_encode_fns
, 0, 0 },
8851 { "diwbi", ICLASS_xt_iclass_dcache_ind
,
8853 Opcode_diwbi_encode_fns
, 0, 0 },
8854 { "dhi", ICLASS_xt_iclass_dcache_inv
,
8856 Opcode_dhi_encode_fns
, 0, 0 },
8857 { "dii", ICLASS_xt_iclass_dcache_inv
,
8859 Opcode_dii_encode_fns
, 0, 0 },
8860 { "dpfr", ICLASS_xt_iclass_dpf
,
8862 Opcode_dpfr_encode_fns
, 0, 0 },
8863 { "dpfw", ICLASS_xt_iclass_dpf
,
8865 Opcode_dpfw_encode_fns
, 0, 0 },
8866 { "dpfro", ICLASS_xt_iclass_dpf
,
8868 Opcode_dpfro_encode_fns
, 0, 0 },
8869 { "dpfwo", ICLASS_xt_iclass_dpf
,
8871 Opcode_dpfwo_encode_fns
, 0, 0 },
8872 { "sdct", ICLASS_xt_iclass_sdct
,
8874 Opcode_sdct_encode_fns
, 0, 0 },
8875 { "ldct", ICLASS_xt_iclass_ldct
,
8877 Opcode_ldct_encode_fns
, 0, 0 },
8878 { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr
,
8880 Opcode_wsr_ptevaddr_encode_fns
, 0, 0 },
8881 { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr
,
8883 Opcode_rsr_ptevaddr_encode_fns
, 0, 0 },
8884 { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr
,
8886 Opcode_xsr_ptevaddr_encode_fns
, 0, 0 },
8887 { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid
,
8889 Opcode_rsr_rasid_encode_fns
, 0, 0 },
8890 { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid
,
8892 Opcode_wsr_rasid_encode_fns
, 0, 0 },
8893 { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid
,
8895 Opcode_xsr_rasid_encode_fns
, 0, 0 },
8896 { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg
,
8898 Opcode_rsr_itlbcfg_encode_fns
, 0, 0 },
8899 { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg
,
8901 Opcode_wsr_itlbcfg_encode_fns
, 0, 0 },
8902 { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg
,
8904 Opcode_xsr_itlbcfg_encode_fns
, 0, 0 },
8905 { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg
,
8907 Opcode_rsr_dtlbcfg_encode_fns
, 0, 0 },
8908 { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg
,
8910 Opcode_wsr_dtlbcfg_encode_fns
, 0, 0 },
8911 { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg
,
8913 Opcode_xsr_dtlbcfg_encode_fns
, 0, 0 },
8914 { "idtlb", ICLASS_xt_iclass_idtlb
,
8916 Opcode_idtlb_encode_fns
, 0, 0 },
8917 { "pdtlb", ICLASS_xt_iclass_rdtlb
,
8919 Opcode_pdtlb_encode_fns
, 0, 0 },
8920 { "rdtlb0", ICLASS_xt_iclass_rdtlb
,
8922 Opcode_rdtlb0_encode_fns
, 0, 0 },
8923 { "rdtlb1", ICLASS_xt_iclass_rdtlb
,
8925 Opcode_rdtlb1_encode_fns
, 0, 0 },
8926 { "wdtlb", ICLASS_xt_iclass_wdtlb
,
8928 Opcode_wdtlb_encode_fns
, 0, 0 },
8929 { "iitlb", ICLASS_xt_iclass_iitlb
,
8931 Opcode_iitlb_encode_fns
, 0, 0 },
8932 { "pitlb", ICLASS_xt_iclass_ritlb
,
8934 Opcode_pitlb_encode_fns
, 0, 0 },
8935 { "ritlb0", ICLASS_xt_iclass_ritlb
,
8937 Opcode_ritlb0_encode_fns
, 0, 0 },
8938 { "ritlb1", ICLASS_xt_iclass_ritlb
,
8940 Opcode_ritlb1_encode_fns
, 0, 0 },
8941 { "witlb", ICLASS_xt_iclass_witlb
,
8943 Opcode_witlb_encode_fns
, 0, 0 },
8944 { "ldpte", ICLASS_xt_iclass_ldpte
,
8946 Opcode_ldpte_encode_fns
, 0, 0 },
8947 { "hwwitlba", ICLASS_xt_iclass_hwwitlba
,
8948 XTENSA_OPCODE_IS_BRANCH
,
8949 Opcode_hwwitlba_encode_fns
, 0, 0 },
8950 { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba
,
8952 Opcode_hwwdtlba_encode_fns
, 0, 0 },
8953 { "nsa", ICLASS_xt_iclass_nsa
,
8955 Opcode_nsa_encode_fns
, 0, 0 },
8956 { "nsau", ICLASS_xt_iclass_nsa
,
8958 Opcode_nsau_encode_fns
, 0, 0 }
8961 enum xtensa_opcode_id
{
8982 OPCODE_RSR_WINDOWBASE
,
8983 OPCODE_WSR_WINDOWBASE
,
8984 OPCODE_XSR_WINDOWBASE
,
8985 OPCODE_RSR_WINDOWSTART
,
8986 OPCODE_WSR_WINDOWSTART
,
8987 OPCODE_XSR_WINDOWSTART
,
9104 OPCODE_RSR_EXCSAVE1
,
9105 OPCODE_WSR_EXCSAVE1
,
9106 OPCODE_XSR_EXCSAVE1
,
9110 OPCODE_RSR_EXCSAVE2
,
9111 OPCODE_WSR_EXCSAVE2
,
9112 OPCODE_XSR_EXCSAVE2
,
9116 OPCODE_RSR_EXCSAVE3
,
9117 OPCODE_WSR_EXCSAVE3
,
9118 OPCODE_XSR_EXCSAVE3
,
9122 OPCODE_RSR_EXCSAVE4
,
9123 OPCODE_WSR_EXCSAVE4
,
9124 OPCODE_XSR_EXCSAVE4
,
9134 OPCODE_RSR_EXCVADDR
,
9135 OPCODE_WSR_EXCVADDR
,
9136 OPCODE_XSR_EXCVADDR
,
9140 OPCODE_RSR_EXCCAUSE
,
9141 OPCODE_WSR_EXCCAUSE
,
9142 OPCODE_XSR_EXCCAUSE
,
9152 OPCODE_RSR_INTERRUPT
,
9154 OPCODE_WSR_INTCLEAR
,
9155 OPCODE_RSR_INTENABLE
,
9156 OPCODE_WSR_INTENABLE
,
9157 OPCODE_XSR_INTENABLE
,
9160 OPCODE_RSR_DBREAKA0
,
9161 OPCODE_WSR_DBREAKA0
,
9162 OPCODE_XSR_DBREAKA0
,
9163 OPCODE_RSR_DBREAKC0
,
9164 OPCODE_WSR_DBREAKC0
,
9165 OPCODE_XSR_DBREAKC0
,
9166 OPCODE_RSR_DBREAKA1
,
9167 OPCODE_WSR_DBREAKA1
,
9168 OPCODE_XSR_DBREAKA1
,
9169 OPCODE_RSR_DBREAKC1
,
9170 OPCODE_WSR_DBREAKC1
,
9171 OPCODE_XSR_DBREAKC1
,
9172 OPCODE_RSR_IBREAKA0
,
9173 OPCODE_WSR_IBREAKA0
,
9174 OPCODE_XSR_IBREAKA0
,
9175 OPCODE_RSR_IBREAKA1
,
9176 OPCODE_WSR_IBREAKA1
,
9177 OPCODE_XSR_IBREAKA1
,
9178 OPCODE_RSR_IBREAKENABLE
,
9179 OPCODE_WSR_IBREAKENABLE
,
9180 OPCODE_XSR_IBREAKENABLE
,
9181 OPCODE_RSR_DEBUGCAUSE
,
9182 OPCODE_WSR_DEBUGCAUSE
,
9183 OPCODE_XSR_DEBUGCAUSE
,
9187 OPCODE_RSR_ICOUNTLEVEL
,
9188 OPCODE_WSR_ICOUNTLEVEL
,
9189 OPCODE_XSR_ICOUNTLEVEL
,
9198 OPCODE_RSR_CCOMPARE0
,
9199 OPCODE_WSR_CCOMPARE0
,
9200 OPCODE_XSR_CCOMPARE0
,
9201 OPCODE_RSR_CCOMPARE1
,
9202 OPCODE_WSR_CCOMPARE1
,
9203 OPCODE_XSR_CCOMPARE1
,
9204 OPCODE_RSR_CCOMPARE2
,
9205 OPCODE_WSR_CCOMPARE2
,
9206 OPCODE_XSR_CCOMPARE2
,
9226 OPCODE_WSR_PTEVADDR
,
9227 OPCODE_RSR_PTEVADDR
,
9228 OPCODE_XSR_PTEVADDR
,
9256 /* Slot-specific opcode decode functions. */
9259 Slot_inst_decode (const xtensa_insnbuf insn
)
9261 switch (Field_op0_Slot_inst_get (insn
))
9264 switch (Field_op1_Slot_inst_get (insn
))
9267 switch (Field_op2_Slot_inst_get (insn
))
9270 switch (Field_r_Slot_inst_get (insn
))
9273 switch (Field_m_Slot_inst_get (insn
))
9276 if (Field_s_Slot_inst_get (insn
) == 0 &&
9277 Field_n_Slot_inst_get (insn
) == 0)
9281 switch (Field_n_Slot_inst_get (insn
))
9292 switch (Field_n_Slot_inst_get (insn
))
9295 return OPCODE_CALLX0
;
9297 return OPCODE_CALLX4
;
9299 return OPCODE_CALLX8
;
9301 return OPCODE_CALLX12
;
9307 return OPCODE_MOVSP
;
9309 if (Field_s_Slot_inst_get (insn
) == 0)
9311 switch (Field_t_Slot_inst_get (insn
))
9314 return OPCODE_ISYNC
;
9316 return OPCODE_RSYNC
;
9318 return OPCODE_ESYNC
;
9320 return OPCODE_DSYNC
;
9333 switch (Field_t_Slot_inst_get (insn
))
9336 switch (Field_s_Slot_inst_get (insn
))
9353 return OPCODE_BREAK
;
9355 switch (Field_s_Slot_inst_get (insn
))
9358 if (Field_t_Slot_inst_get (insn
) == 0)
9359 return OPCODE_SYSCALL
;
9362 if (Field_t_Slot_inst_get (insn
) == 0)
9363 return OPCODE_SIMCALL
;
9370 if (Field_t_Slot_inst_get (insn
) == 0)
9371 return OPCODE_WAITI
;
9382 switch (Field_r_Slot_inst_get (insn
))
9385 if (Field_t_Slot_inst_get (insn
) == 0)
9389 if (Field_t_Slot_inst_get (insn
) == 0)
9393 if (Field_t_Slot_inst_get (insn
) == 0)
9394 return OPCODE_SSA8L
;
9397 if (Field_t_Slot_inst_get (insn
) == 0)
9398 return OPCODE_SSA8B
;
9401 if (Field_thi3_Slot_inst_get (insn
) == 0)
9405 if (Field_s_Slot_inst_get (insn
) == 0)
9415 switch (Field_r_Slot_inst_get (insn
))
9418 return OPCODE_HWWITLBA
;
9420 return OPCODE_RITLB0
;
9422 if (Field_t_Slot_inst_get (insn
) == 0)
9423 return OPCODE_IITLB
;
9426 return OPCODE_PITLB
;
9428 return OPCODE_WITLB
;
9430 return OPCODE_RITLB1
;
9432 return OPCODE_HWWDTLBA
;
9434 return OPCODE_RDTLB0
;
9436 if (Field_t_Slot_inst_get (insn
) == 0)
9437 return OPCODE_IDTLB
;
9440 return OPCODE_PDTLB
;
9442 return OPCODE_WDTLB
;
9444 return OPCODE_RDTLB1
;
9448 switch (Field_s_Slot_inst_get (insn
))
9459 return OPCODE_ADDX2
;
9461 return OPCODE_ADDX4
;
9463 return OPCODE_ADDX8
;
9467 return OPCODE_SUBX2
;
9469 return OPCODE_SUBX4
;
9471 return OPCODE_SUBX8
;
9475 switch (Field_op2_Slot_inst_get (insn
))
9486 switch (Field_sr_Slot_inst_get (insn
))
9489 return OPCODE_XSR_LBEG
;
9491 return OPCODE_XSR_LEND
;
9493 return OPCODE_XSR_LCOUNT
;
9495 return OPCODE_XSR_SAR
;
9497 return OPCODE_XSR_LITBASE
;
9499 return OPCODE_XSR_WINDOWBASE
;
9501 return OPCODE_XSR_WINDOWSTART
;
9503 return OPCODE_XSR_PTEVADDR
;
9505 return OPCODE_XSR_RASID
;
9507 return OPCODE_XSR_ITLBCFG
;
9509 return OPCODE_XSR_DTLBCFG
;
9511 return OPCODE_XSR_IBREAKENABLE
;
9513 return OPCODE_XSR_DDR
;
9515 return OPCODE_XSR_IBREAKA0
;
9517 return OPCODE_XSR_IBREAKA1
;
9519 return OPCODE_XSR_DBREAKA0
;
9521 return OPCODE_XSR_DBREAKA1
;
9523 return OPCODE_XSR_DBREAKC0
;
9525 return OPCODE_XSR_DBREAKC1
;
9527 return OPCODE_XSR_EPC1
;
9529 return OPCODE_XSR_EPC2
;
9531 return OPCODE_XSR_EPC3
;
9533 return OPCODE_XSR_EPC4
;
9535 return OPCODE_XSR_DEPC
;
9537 return OPCODE_XSR_EPS2
;
9539 return OPCODE_XSR_EPS3
;
9541 return OPCODE_XSR_EPS4
;
9543 return OPCODE_XSR_EXCSAVE1
;
9545 return OPCODE_XSR_EXCSAVE2
;
9547 return OPCODE_XSR_EXCSAVE3
;
9549 return OPCODE_XSR_EXCSAVE4
;
9551 return OPCODE_XSR_INTENABLE
;
9553 return OPCODE_XSR_PS
;
9555 return OPCODE_XSR_EXCCAUSE
;
9557 return OPCODE_XSR_DEBUGCAUSE
;
9559 return OPCODE_XSR_CCOUNT
;
9561 return OPCODE_XSR_ICOUNT
;
9563 return OPCODE_XSR_ICOUNTLEVEL
;
9565 return OPCODE_XSR_EXCVADDR
;
9567 return OPCODE_XSR_CCOMPARE0
;
9569 return OPCODE_XSR_CCOMPARE1
;
9571 return OPCODE_XSR_CCOMPARE2
;
9573 return OPCODE_XSR_MISC0
;
9575 return OPCODE_XSR_MISC1
;
9581 if (Field_s_Slot_inst_get (insn
) == 0)
9585 if (Field_t_Slot_inst_get (insn
) == 0)
9589 if (Field_s_Slot_inst_get (insn
) == 0)
9593 switch (Field_r_Slot_inst_get (insn
))
9608 if (Field_t_Slot_inst_get (insn
) == 0)
9610 if (Field_t_Slot_inst_get (insn
) == 1)
9614 return OPCODE_LDPTE
;
9620 switch (Field_op2_Slot_inst_get (insn
))
9623 switch (Field_sr_Slot_inst_get (insn
))
9626 return OPCODE_RSR_LBEG
;
9628 return OPCODE_RSR_LEND
;
9630 return OPCODE_RSR_LCOUNT
;
9632 return OPCODE_RSR_SAR
;
9634 return OPCODE_RSR_LITBASE
;
9636 return OPCODE_RSR_WINDOWBASE
;
9638 return OPCODE_RSR_WINDOWSTART
;
9640 return OPCODE_RSR_PTEVADDR
;
9642 return OPCODE_RSR_RASID
;
9644 return OPCODE_RSR_ITLBCFG
;
9646 return OPCODE_RSR_DTLBCFG
;
9648 return OPCODE_RSR_IBREAKENABLE
;
9650 return OPCODE_RSR_DDR
;
9652 return OPCODE_RSR_IBREAKA0
;
9654 return OPCODE_RSR_IBREAKA1
;
9656 return OPCODE_RSR_DBREAKA0
;
9658 return OPCODE_RSR_DBREAKA1
;
9660 return OPCODE_RSR_DBREAKC0
;
9662 return OPCODE_RSR_DBREAKC1
;
9664 return OPCODE_RSR_176
;
9666 return OPCODE_RSR_EPC1
;
9668 return OPCODE_RSR_EPC2
;
9670 return OPCODE_RSR_EPC3
;
9672 return OPCODE_RSR_EPC4
;
9674 return OPCODE_RSR_DEPC
;
9676 return OPCODE_RSR_EPS2
;
9678 return OPCODE_RSR_EPS3
;
9680 return OPCODE_RSR_EPS4
;
9682 return OPCODE_RSR_208
;
9684 return OPCODE_RSR_EXCSAVE1
;
9686 return OPCODE_RSR_EXCSAVE2
;
9688 return OPCODE_RSR_EXCSAVE3
;
9690 return OPCODE_RSR_EXCSAVE4
;
9692 return OPCODE_RSR_INTERRUPT
;
9694 return OPCODE_RSR_INTENABLE
;
9696 return OPCODE_RSR_PS
;
9698 return OPCODE_RSR_EXCCAUSE
;
9700 return OPCODE_RSR_DEBUGCAUSE
;
9702 return OPCODE_RSR_CCOUNT
;
9704 return OPCODE_RSR_PRID
;
9706 return OPCODE_RSR_ICOUNT
;
9708 return OPCODE_RSR_ICOUNTLEVEL
;
9710 return OPCODE_RSR_EXCVADDR
;
9712 return OPCODE_RSR_CCOMPARE0
;
9714 return OPCODE_RSR_CCOMPARE1
;
9716 return OPCODE_RSR_CCOMPARE2
;
9718 return OPCODE_RSR_MISC0
;
9720 return OPCODE_RSR_MISC1
;
9724 switch (Field_sr_Slot_inst_get (insn
))
9727 return OPCODE_WSR_LBEG
;
9729 return OPCODE_WSR_LEND
;
9731 return OPCODE_WSR_LCOUNT
;
9733 return OPCODE_WSR_SAR
;
9735 return OPCODE_WSR_LITBASE
;
9737 return OPCODE_WSR_WINDOWBASE
;
9739 return OPCODE_WSR_WINDOWSTART
;
9741 return OPCODE_WSR_PTEVADDR
;
9743 return OPCODE_WSR_RASID
;
9745 return OPCODE_WSR_ITLBCFG
;
9747 return OPCODE_WSR_DTLBCFG
;
9749 return OPCODE_WSR_IBREAKENABLE
;
9751 return OPCODE_WSR_DDR
;
9753 return OPCODE_WSR_IBREAKA0
;
9755 return OPCODE_WSR_IBREAKA1
;
9757 return OPCODE_WSR_DBREAKA0
;
9759 return OPCODE_WSR_DBREAKA1
;
9761 return OPCODE_WSR_DBREAKC0
;
9763 return OPCODE_WSR_DBREAKC1
;
9765 return OPCODE_WSR_EPC1
;
9767 return OPCODE_WSR_EPC2
;
9769 return OPCODE_WSR_EPC3
;
9771 return OPCODE_WSR_EPC4
;
9773 return OPCODE_WSR_DEPC
;
9775 return OPCODE_WSR_EPS2
;
9777 return OPCODE_WSR_EPS3
;
9779 return OPCODE_WSR_EPS4
;
9781 return OPCODE_WSR_EXCSAVE1
;
9783 return OPCODE_WSR_EXCSAVE2
;
9785 return OPCODE_WSR_EXCSAVE3
;
9787 return OPCODE_WSR_EXCSAVE4
;
9789 return OPCODE_WSR_INTSET
;
9791 return OPCODE_WSR_INTCLEAR
;
9793 return OPCODE_WSR_INTENABLE
;
9795 return OPCODE_WSR_PS
;
9797 return OPCODE_WSR_EXCCAUSE
;
9799 return OPCODE_WSR_DEBUGCAUSE
;
9801 return OPCODE_WSR_CCOUNT
;
9803 return OPCODE_WSR_ICOUNT
;
9805 return OPCODE_WSR_ICOUNTLEVEL
;
9807 return OPCODE_WSR_EXCVADDR
;
9809 return OPCODE_WSR_CCOMPARE0
;
9811 return OPCODE_WSR_CCOMPARE1
;
9813 return OPCODE_WSR_CCOMPARE2
;
9815 return OPCODE_WSR_MISC0
;
9817 return OPCODE_WSR_MISC1
;
9821 return OPCODE_MOVEQZ
;
9823 return OPCODE_MOVNEZ
;
9825 return OPCODE_MOVLTZ
;
9827 return OPCODE_MOVGEZ
;
9832 return OPCODE_EXTUI
;
9834 switch (Field_op2_Slot_inst_get (insn
))
9847 switch (Field_r_Slot_inst_get (insn
))
9852 return OPCODE_L16UI
;
9862 switch (Field_t_Slot_inst_get (insn
))
9869 return OPCODE_DPFRO
;
9871 return OPCODE_DPFWO
;
9875 return OPCODE_DHWBI
;
9881 switch (Field_op1_Slot_inst_get (insn
))
9886 return OPCODE_DIWBI
;
9898 return OPCODE_L16SI
;
9904 return OPCODE_ADDMI
;
9908 switch (Field_n_Slot_inst_get (insn
))
9911 return OPCODE_CALL0
;
9913 return OPCODE_CALL4
;
9915 return OPCODE_CALL8
;
9917 return OPCODE_CALL12
;
9921 switch (Field_n_Slot_inst_get (insn
))
9926 switch (Field_m_Slot_inst_get (insn
))
9939 switch (Field_m_Slot_inst_get (insn
))
9952 switch (Field_m_Slot_inst_get (insn
))
9955 return OPCODE_ENTRY
;
9957 switch (Field_r_Slot_inst_get (insn
))
9962 return OPCODE_LOOPNEZ
;
9964 return OPCODE_LOOPGTZ
;
9968 return OPCODE_BLTUI
;
9970 return OPCODE_BGEUI
;
9976 switch (Field_r_Slot_inst_get (insn
))
9979 return OPCODE_BNONE
;
10000 return OPCODE_BGEU
;
10002 return OPCODE_BNALL
;
10007 return OPCODE_BBSI
;
10015 Slot_inst16b_decode (const xtensa_insnbuf insn
)
10017 switch (Field_op0_Slot_inst16b_get (insn
))
10020 switch (Field_i_Slot_inst16b_get (insn
))
10023 return OPCODE_MOVI_N
;
10025 switch (Field_z_Slot_inst16b_get (insn
))
10028 return OPCODE_BEQZ_N
;
10030 return OPCODE_BNEZ_N
;
10036 switch (Field_r_Slot_inst16b_get (insn
))
10039 return OPCODE_MOV_N
;
10041 switch (Field_t_Slot_inst16b_get (insn
))
10044 return OPCODE_RET_N
;
10046 return OPCODE_RETW_N
;
10048 return OPCODE_BREAK_N
;
10050 if (Field_s_Slot_inst16b_get (insn
) == 0)
10051 return OPCODE_NOP_N
;
10054 if (Field_s_Slot_inst16b_get (insn
) == 0)
10055 return OPCODE_ILL_N
;
10066 Slot_inst16a_decode (const xtensa_insnbuf insn
)
10068 switch (Field_op0_Slot_inst16a_get (insn
))
10071 return OPCODE_L32I_N
;
10073 return OPCODE_S32I_N
;
10075 return OPCODE_ADD_N
;
10077 return OPCODE_ADDI_N
;
10083 /* Instruction slots. */
10086 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn
,
10087 xtensa_insnbuf slotbuf
)
10089 slotbuf
[0] = (insn
[0] & 0xffffff);
10093 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn
,
10094 const xtensa_insnbuf slotbuf
)
10096 insn
[0] = (insn
[0] & ~0xffffff) | (slotbuf
[0] & 0xffffff);
10100 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn
,
10101 xtensa_insnbuf slotbuf
)
10103 slotbuf
[0] = ((insn
[0] & 0xffff00) >> 8);
10107 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn
,
10108 const xtensa_insnbuf slotbuf
)
10110 insn
[0] = (insn
[0] & ~0xffff00) | ((slotbuf
[0] & 0xffff) << 8);
10114 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn
,
10115 xtensa_insnbuf slotbuf
)
10117 slotbuf
[0] = ((insn
[0] & 0xffff00) >> 8);
10121 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn
,
10122 const xtensa_insnbuf slotbuf
)
10124 insn
[0] = (insn
[0] & ~0xffff00) | ((slotbuf
[0] & 0xffff) << 8);
10127 static xtensa_get_field_fn
10128 Slot_inst_get_field_fns
[] = {
10129 Field_t_Slot_inst_get
,
10130 Field_bbi4_Slot_inst_get
,
10131 Field_bbi_Slot_inst_get
,
10132 Field_imm12_Slot_inst_get
,
10133 Field_imm8_Slot_inst_get
,
10134 Field_s_Slot_inst_get
,
10135 Field_imm12b_Slot_inst_get
,
10136 Field_imm16_Slot_inst_get
,
10137 Field_m_Slot_inst_get
,
10138 Field_n_Slot_inst_get
,
10139 Field_offset_Slot_inst_get
,
10140 Field_op0_Slot_inst_get
,
10141 Field_op1_Slot_inst_get
,
10142 Field_op2_Slot_inst_get
,
10143 Field_r_Slot_inst_get
,
10144 Field_sa4_Slot_inst_get
,
10145 Field_sae4_Slot_inst_get
,
10146 Field_sae_Slot_inst_get
,
10147 Field_sal_Slot_inst_get
,
10148 Field_sargt_Slot_inst_get
,
10149 Field_sas4_Slot_inst_get
,
10150 Field_sas_Slot_inst_get
,
10151 Field_sr_Slot_inst_get
,
10152 Field_st_Slot_inst_get
,
10153 Field_thi3_Slot_inst_get
,
10154 Field_imm4_Slot_inst_get
,
10155 Field_mn_Slot_inst_get
,
10164 Implicit_Field_ar0_get
,
10165 Implicit_Field_ar4_get
,
10166 Implicit_Field_ar8_get
,
10167 Implicit_Field_ar12_get
10170 static xtensa_set_field_fn
10171 Slot_inst_set_field_fns
[] = {
10172 Field_t_Slot_inst_set
,
10173 Field_bbi4_Slot_inst_set
,
10174 Field_bbi_Slot_inst_set
,
10175 Field_imm12_Slot_inst_set
,
10176 Field_imm8_Slot_inst_set
,
10177 Field_s_Slot_inst_set
,
10178 Field_imm12b_Slot_inst_set
,
10179 Field_imm16_Slot_inst_set
,
10180 Field_m_Slot_inst_set
,
10181 Field_n_Slot_inst_set
,
10182 Field_offset_Slot_inst_set
,
10183 Field_op0_Slot_inst_set
,
10184 Field_op1_Slot_inst_set
,
10185 Field_op2_Slot_inst_set
,
10186 Field_r_Slot_inst_set
,
10187 Field_sa4_Slot_inst_set
,
10188 Field_sae4_Slot_inst_set
,
10189 Field_sae_Slot_inst_set
,
10190 Field_sal_Slot_inst_set
,
10191 Field_sargt_Slot_inst_set
,
10192 Field_sas4_Slot_inst_set
,
10193 Field_sas_Slot_inst_set
,
10194 Field_sr_Slot_inst_set
,
10195 Field_st_Slot_inst_set
,
10196 Field_thi3_Slot_inst_set
,
10197 Field_imm4_Slot_inst_set
,
10198 Field_mn_Slot_inst_set
,
10207 Implicit_Field_set
,
10208 Implicit_Field_set
,
10209 Implicit_Field_set
,
10213 static xtensa_get_field_fn
10214 Slot_inst16a_get_field_fns
[] = {
10215 Field_t_Slot_inst16a_get
,
10220 Field_s_Slot_inst16a_get
,
10226 Field_op0_Slot_inst16a_get
,
10229 Field_r_Slot_inst16a_get
,
10237 Field_sr_Slot_inst16a_get
,
10238 Field_st_Slot_inst16a_get
,
10240 Field_imm4_Slot_inst16a_get
,
10242 Field_i_Slot_inst16a_get
,
10243 Field_imm6lo_Slot_inst16a_get
,
10244 Field_imm6hi_Slot_inst16a_get
,
10245 Field_imm7lo_Slot_inst16a_get
,
10246 Field_imm7hi_Slot_inst16a_get
,
10247 Field_z_Slot_inst16a_get
,
10248 Field_imm6_Slot_inst16a_get
,
10249 Field_imm7_Slot_inst16a_get
,
10250 Implicit_Field_ar0_get
,
10251 Implicit_Field_ar4_get
,
10252 Implicit_Field_ar8_get
,
10253 Implicit_Field_ar12_get
10256 static xtensa_set_field_fn
10257 Slot_inst16a_set_field_fns
[] = {
10258 Field_t_Slot_inst16a_set
,
10263 Field_s_Slot_inst16a_set
,
10269 Field_op0_Slot_inst16a_set
,
10272 Field_r_Slot_inst16a_set
,
10280 Field_sr_Slot_inst16a_set
,
10281 Field_st_Slot_inst16a_set
,
10283 Field_imm4_Slot_inst16a_set
,
10285 Field_i_Slot_inst16a_set
,
10286 Field_imm6lo_Slot_inst16a_set
,
10287 Field_imm6hi_Slot_inst16a_set
,
10288 Field_imm7lo_Slot_inst16a_set
,
10289 Field_imm7hi_Slot_inst16a_set
,
10290 Field_z_Slot_inst16a_set
,
10291 Field_imm6_Slot_inst16a_set
,
10292 Field_imm7_Slot_inst16a_set
,
10293 Implicit_Field_set
,
10294 Implicit_Field_set
,
10295 Implicit_Field_set
,
10299 static xtensa_get_field_fn
10300 Slot_inst16b_get_field_fns
[] = {
10301 Field_t_Slot_inst16b_get
,
10306 Field_s_Slot_inst16b_get
,
10312 Field_op0_Slot_inst16b_get
,
10315 Field_r_Slot_inst16b_get
,
10323 Field_sr_Slot_inst16b_get
,
10324 Field_st_Slot_inst16b_get
,
10326 Field_imm4_Slot_inst16b_get
,
10328 Field_i_Slot_inst16b_get
,
10329 Field_imm6lo_Slot_inst16b_get
,
10330 Field_imm6hi_Slot_inst16b_get
,
10331 Field_imm7lo_Slot_inst16b_get
,
10332 Field_imm7hi_Slot_inst16b_get
,
10333 Field_z_Slot_inst16b_get
,
10334 Field_imm6_Slot_inst16b_get
,
10335 Field_imm7_Slot_inst16b_get
,
10336 Implicit_Field_ar0_get
,
10337 Implicit_Field_ar4_get
,
10338 Implicit_Field_ar8_get
,
10339 Implicit_Field_ar12_get
10342 static xtensa_set_field_fn
10343 Slot_inst16b_set_field_fns
[] = {
10344 Field_t_Slot_inst16b_set
,
10349 Field_s_Slot_inst16b_set
,
10355 Field_op0_Slot_inst16b_set
,
10358 Field_r_Slot_inst16b_set
,
10366 Field_sr_Slot_inst16b_set
,
10367 Field_st_Slot_inst16b_set
,
10369 Field_imm4_Slot_inst16b_set
,
10371 Field_i_Slot_inst16b_set
,
10372 Field_imm6lo_Slot_inst16b_set
,
10373 Field_imm6hi_Slot_inst16b_set
,
10374 Field_imm7lo_Slot_inst16b_set
,
10375 Field_imm7hi_Slot_inst16b_set
,
10376 Field_z_Slot_inst16b_set
,
10377 Field_imm6_Slot_inst16b_set
,
10378 Field_imm7_Slot_inst16b_set
,
10379 Implicit_Field_set
,
10380 Implicit_Field_set
,
10381 Implicit_Field_set
,
10385 static xtensa_slot_internal slots
[] = {
10386 { "Inst", "x24", 0,
10387 Slot_x24_Format_inst_0_get
, Slot_x24_Format_inst_0_set
,
10388 Slot_inst_get_field_fns
, Slot_inst_set_field_fns
,
10389 Slot_inst_decode
, "nop" },
10390 { "Inst16a", "x16a", 0,
10391 Slot_x16a_Format_inst16a_0_get
, Slot_x16a_Format_inst16a_0_set
,
10392 Slot_inst16a_get_field_fns
, Slot_inst16a_set_field_fns
,
10393 Slot_inst16a_decode
, "" },
10394 { "Inst16b", "x16b", 0,
10395 Slot_x16b_Format_inst16b_0_get
, Slot_x16b_Format_inst16b_0_set
,
10396 Slot_inst16b_get_field_fns
, Slot_inst16b_set_field_fns
,
10397 Slot_inst16b_decode
, "nop.n" }
10401 /* Instruction formats. */
10404 Format_x24_encode (xtensa_insnbuf insn
)
10410 Format_x16a_encode (xtensa_insnbuf insn
)
10412 insn
[0] = 0x800000;
10416 Format_x16b_encode (xtensa_insnbuf insn
)
10418 insn
[0] = 0xc00000;
10421 static int Format_x24_slots
[] = { 0 };
10423 static int Format_x16a_slots
[] = { 1 };
10425 static int Format_x16b_slots
[] = { 2 };
10427 static xtensa_format_internal formats
[] = {
10428 { "x24", 3, Format_x24_encode
, 1, Format_x24_slots
},
10429 { "x16a", 2, Format_x16a_encode
, 1, Format_x16a_slots
},
10430 { "x16b", 2, Format_x16b_encode
, 1, Format_x16b_slots
}
10435 format_decoder (const xtensa_insnbuf insn
)
10437 if ((insn
[0] & 0x800000) == 0)
10438 return 0; /* x24 */
10439 if ((insn
[0] & 0xc00000) == 0x800000)
10440 return 1; /* x16a */
10441 if ((insn
[0] & 0xe00000) == 0xc00000)
10442 return 2; /* x16b */
10446 static int length_table
[16] = {
10466 length_decoder (const unsigned char *insn
)
10468 int op0
= (insn
[0] >> 4) & 0xf;
10469 return length_table
[op0
];
10473 /* Top-level ISA structure. */
10475 xtensa_isa_internal xtensa_modules
= {
10476 1 /* big-endian */,
10477 3 /* insn_size */, 0,
10478 3, formats
, format_decoder
, length_decoder
,
10480 39 /* num_fields */,
10485 NUM_STATES
, states
, 0,
10486 NUM_SYSREGS
, sysregs
, 0,
10487 { MAX_SPECIAL_REG
, MAX_USER_REG
}, { 0, 0 },