bfd/xtensa-modules.c

   1 /* Xtensa configuration-specific ISA information.
   2    Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
   3
   4    This file is part of BFD, the Binary File Descriptor library.
   5
   6    This program is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU General Public License as
   8    published by the Free Software Foundation; either version 3 of the
   9    License, or (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "ansidecl.h"
  22 #include <xtensa-isa.h>
  23 #include "xtensa-isa-internal.h"
  24
  25 \f
  26 /* Sysregs.  */
  27
  28 static xtensa_sysreg_internal sysregs[] = {
  29   { "LBEG", 0, 0 },
  30   { "LEND", 1, 0 },
  31   { "LCOUNT", 2, 0 },
  32   { "PTEVADDR", 83, 0 },
  33   { "DDR", 104, 0 },
  34   { "176", 176, 0 },
  35   { "208", 208, 0 },
  36   { "INTERRUPT", 226, 0 },
  37   { "INTCLEAR", 227, 0 },
  38   { "CCOUNT", 234, 0 },
  39   { "PRID", 235, 0 },
  40   { "ICOUNT", 236, 0 },
  41   { "CCOMPARE0", 240, 0 },
  42   { "CCOMPARE1", 241, 0 },
  43   { "CCOMPARE2", 242, 0 },
  44   { "EPC1", 177, 0 },
  45   { "EPC2", 178, 0 },
  46   { "EPC3", 179, 0 },
  47   { "EPC4", 180, 0 },
  48   { "EXCSAVE1", 209, 0 },
  49   { "EXCSAVE2", 210, 0 },
  50   { "EXCSAVE3", 211, 0 },
  51   { "EXCSAVE4", 212, 0 },
  52   { "EPS2", 194, 0 },
  53   { "EPS3", 195, 0 },
  54   { "EPS4", 196, 0 },
  55   { "EXCCAUSE", 232, 0 },
  56   { "DEPC", 192, 0 },
  57   { "EXCVADDR", 238, 0 },
  58   { "WINDOWBASE", 72, 0 },
  59   { "WINDOWSTART", 73, 0 },
  60   { "SAR", 3, 0 },
  61   { "LITBASE", 5, 0 },
  62   { "PS", 230, 0 },
  63   { "MISC0", 244, 0 },
  64   { "MISC1", 245, 0 },
  65   { "INTENABLE", 228, 0 },
  66   { "DBREAKA0", 144, 0 },
  67   { "DBREAKC0", 160, 0 },
  68   { "DBREAKA1", 145, 0 },
  69   { "DBREAKC1", 161, 0 },
  70   { "IBREAKA0", 128, 0 },
  71   { "IBREAKA1", 129, 0 },
  72   { "IBREAKENABLE", 96, 0 },
  73   { "ICOUNTLEVEL", 237, 0 },
  74   { "DEBUGCAUSE", 233, 0 },
  75   { "RASID", 90, 0 },
  76   { "ITLBCFG", 91, 0 },
  77   { "DTLBCFG", 92, 0 }
  78 };
  79
  80 #define NUM_SYSREGS 49
  81 #define MAX_SPECIAL_REG 245
  82 #define MAX_USER_REG 0
  83
  84 \f
  85 /* Processor states.  */
  86
  87 static xtensa_state_internal states[] = {
  88   { "LCOUNT", 32, 0 },
  89   { "PC", 32, 0 },
  90   { "ICOUNT", 32, 0 },
  91   { "DDR", 32, 0 },
  92   { "INTERRUPT", 17, 0 },
  93   { "CCOUNT", 32, 0 },
  94   { "XTSYNC", 1, 0 },
  95   { "EPC1", 32, 0 },
  96   { "EPC2", 32, 0 },
  97   { "EPC3", 32, 0 },
  98   { "EPC4", 32, 0 },
  99   { "EXCSAVE1", 32, 0 },
 100   { "EXCSAVE2", 32, 0 },
 101   { "EXCSAVE3", 32, 0 },
 102   { "EXCSAVE4", 32, 0 },
 103   { "EPS2", 15, 0 },
 104   { "EPS3", 15, 0 },
 105   { "EPS4", 15, 0 },
 106   { "EXCCAUSE", 6, 0 },
 107   { "PSINTLEVEL", 4, 0 },
 108   { "PSUM", 1, 0 },
 109   { "PSWOE", 1, 0 },
 110   { "PSRING", 2, 0 },
 111   { "PSEXCM", 1, 0 },
 112   { "DEPC", 32, 0 },
 113   { "EXCVADDR", 32, 0 },
 114   { "WindowBase", 4, 0 },
 115   { "WindowStart", 16, 0 },
 116   { "PSCALLINC", 2, 0 },
 117   { "PSOWB", 4, 0 },
 118   { "LBEG", 32, 0 },
 119   { "LEND", 32, 0 },
 120   { "SAR", 6, 0 },
 121   { "LITBADDR", 20, 0 },
 122   { "LITBEN", 1, 0 },
 123   { "MISC0", 32, 0 },
 124   { "MISC1", 32, 0 },
 125   { "InOCDMode", 1, 0 },
 126   { "INTENABLE", 17, 0 },
 127   { "DBREAKA0", 32, 0 },
 128   { "DBREAKC0", 8, 0 },
 129   { "DBREAKA1", 32, 0 },
 130   { "DBREAKC1", 8, 0 },
 131   { "IBREAKA0", 32, 0 },
 132   { "IBREAKA1", 32, 0 },
 133   { "IBREAKENABLE", 2, 0 },
 134   { "ICOUNTLEVEL", 4, 0 },
 135   { "DEBUGCAUSE", 6, 0 },
 136   { "DBNUM", 4, 0 },
 137   { "CCOMPARE0", 32, 0 },
 138   { "CCOMPARE1", 32, 0 },
 139   { "CCOMPARE2", 32, 0 },
 140   { "ASID3", 8, 0 },
 141   { "ASID2", 8, 0 },
 142   { "ASID1", 8, 0 },
 143   { "INSTPGSZID4", 2, 0 },
 144   { "DATAPGSZID4", 2, 0 },
 145   { "PTBASE", 10, 0 }
 146 };
 147
 148 #define NUM_STATES 58
 149
 150 enum xtensa_state_id {
 151   STATE_LCOUNT,
 152   STATE_PC,
 153   STATE_ICOUNT,
 154   STATE_DDR,
 155   STATE_INTERRUPT,
 156   STATE_CCOUNT,
 157   STATE_XTSYNC,
 158   STATE_EPC1,
 159   STATE_EPC2,
 160   STATE_EPC3,
 161   STATE_EPC4,
 162   STATE_EXCSAVE1,
 163   STATE_EXCSAVE2,
 164   STATE_EXCSAVE3,
 165   STATE_EXCSAVE4,
 166   STATE_EPS2,
 167   STATE_EPS3,
 168   STATE_EPS4,
 169   STATE_EXCCAUSE,
 170   STATE_PSINTLEVEL,
 171   STATE_PSUM,
 172   STATE_PSWOE,
 173   STATE_PSRING,
 174   STATE_PSEXCM,
 175   STATE_DEPC,
 176   STATE_EXCVADDR,
 177   STATE_WindowBase,
 178   STATE_WindowStart,
 179   STATE_PSCALLINC,
 180   STATE_PSOWB,
 181   STATE_LBEG,
 182   STATE_LEND,
 183   STATE_SAR,
 184   STATE_LITBADDR,
 185   STATE_LITBEN,
 186   STATE_MISC0,
 187   STATE_MISC1,
 188   STATE_InOCDMode,
 189   STATE_INTENABLE,
 190   STATE_DBREAKA0,
 191   STATE_DBREAKC0,
 192   STATE_DBREAKA1,
 193   STATE_DBREAKC1,
 194   STATE_IBREAKA0,
 195   STATE_IBREAKA1,
 196   STATE_IBREAKENABLE,
 197   STATE_ICOUNTLEVEL,
 198   STATE_DEBUGCAUSE,
 199   STATE_DBNUM,
 200   STATE_CCOMPARE0,
 201   STATE_CCOMPARE1,
 202   STATE_CCOMPARE2,
 203   STATE_ASID3,
 204   STATE_ASID2,
 205   STATE_ASID1,
 206   STATE_INSTPGSZID4,
 207   STATE_DATAPGSZID4,
 208   STATE_PTBASE
 209 };
 210
 211 \f
 212 /* Field definitions.  */
 213
 214 static unsigned
 215 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 216 {
 217   unsigned tie_t = 0;
 218   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 219   return tie_t;
 220 }
 221
 222 static void
 223 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 224 {
 225   uint32 tie_t;
 226   tie_t = (val << 28) >> 28;
 227   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 228 }
 229
 230 static unsigned
 231 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 232 {
 233   unsigned tie_t = 0;
 234   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 235   return tie_t;
 236 }
 237
 238 static void
 239 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 240 {
 241   uint32 tie_t;
 242   tie_t = (val << 28) >> 28;
 243   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 244 }
 245
 246 static unsigned
 247 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 248 {
 249   unsigned tie_t = 0;
 250   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 251   return tie_t;
 252 }
 253
 254 static void
 255 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 256 {
 257   uint32 tie_t;
 258   tie_t = (val << 28) >> 28;
 259   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 260 }
 261
 262 static unsigned
 263 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 264 {
 265   unsigned tie_t = 0;
 266   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 267   return tie_t;
 268 }
 269
 270 static void
 271 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 272 {
 273   uint32 tie_t;
 274   tie_t = (val << 28) >> 28;
 275   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 276 }
 277
 278 static unsigned
 279 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 280 {
 281   unsigned tie_t = 0;
 282   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 283   return tie_t;
 284 }
 285
 286 static void
 287 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 288 {
 289   uint32 tie_t;
 290   tie_t = (val << 28) >> 28;
 291   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 292 }
 293
 294 static unsigned
 295 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 296 {
 297   unsigned tie_t = 0;
 298   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 299   return tie_t;
 300 }
 301
 302 static void
 303 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 304 {
 305   uint32 tie_t;
 306   tie_t = (val << 28) >> 28;
 307   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 308 }
 309
 310 static unsigned
 311 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 312 {
 313   unsigned tie_t = 0;
 314   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 315   return tie_t;
 316 }
 317
 318 static void
 319 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 320 {
 321   uint32 tie_t;
 322   tie_t = (val << 30) >> 30;
 323   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 324 }
 325
 326 static unsigned
 327 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 328 {
 329   unsigned tie_t = 0;
 330   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 331   return tie_t;
 332 }
 333
 334 static void
 335 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 336 {
 337   uint32 tie_t;
 338   tie_t = (val << 30) >> 30;
 339   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 340 }
 341
 342 static unsigned
 343 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 344 {
 345   unsigned tie_t = 0;
 346   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 347   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 348   return tie_t;
 349 }
 350
 351 static void
 352 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 353 {
 354   uint32 tie_t;
 355   tie_t = (val << 28) >> 28;
 356   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 357   tie_t = (val << 24) >> 28;
 358   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 359 }
 360
 361 static unsigned
 362 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 363 {
 364   unsigned tie_t = 0;
 365   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
 366   return tie_t;
 367 }
 368
 369 static void
 370 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 371 {
 372   uint32 tie_t;
 373   tie_t = (val << 29) >> 29;
 374   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
 375 }
 376
 377 static unsigned
 378 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 379 {
 380   unsigned tie_t = 0;
 381   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 382   return tie_t;
 383 }
 384
 385 static void
 386 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 387 {
 388   uint32 tie_t;
 389   tie_t = (val << 28) >> 28;
 390   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 391 }
 392
 393 static unsigned
 394 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 395 {
 396   unsigned tie_t = 0;
 397   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 398   return tie_t;
 399 }
 400
 401 static void
 402 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 403 {
 404   uint32 tie_t;
 405   tie_t = (val << 28) >> 28;
 406   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 407 }
 408
 409 static unsigned
 410 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 411 {
 412   unsigned tie_t = 0;
 413   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 414   return tie_t;
 415 }
 416
 417 static void
 418 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 419 {
 420   uint32 tie_t;
 421   tie_t = (val << 28) >> 28;
 422   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 423 }
 424
 425 static unsigned
 426 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 427 {
 428   unsigned tie_t = 0;
 429   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 430   return tie_t;
 431 }
 432
 433 static void
 434 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 435 {
 436   uint32 tie_t;
 437   tie_t = (val << 28) >> 28;
 438   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 439 }
 440
 441 static unsigned
 442 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
 443 {
 444   unsigned tie_t = 0;
 445   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
 446   return tie_t;
 447 }
 448
 449 static void
 450 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 451 {
 452   uint32 tie_t;
 453   tie_t = (val << 31) >> 31;
 454   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
 455 }
 456
 457 static unsigned
 458 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 459 {
 460   unsigned tie_t = 0;
 461   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 462   return tie_t;
 463 }
 464
 465 static void
 466 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 467 {
 468   uint32 tie_t;
 469   tie_t = (val << 31) >> 31;
 470   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 471 }
 472
 473 static unsigned
 474 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 475 {
 476   unsigned tie_t = 0;
 477   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 478   return tie_t;
 479 }
 480
 481 static void
 482 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 483 {
 484   uint32 tie_t;
 485   tie_t = (val << 28) >> 28;
 486   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 487 }
 488
 489 static unsigned
 490 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 491 {
 492   unsigned tie_t = 0;
 493   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 494   return tie_t;
 495 }
 496
 497 static void
 498 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 499 {
 500   uint32 tie_t;
 501   tie_t = (val << 28) >> 28;
 502   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 503 }
 504
 505 static unsigned
 506 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 507 {
 508   unsigned tie_t = 0;
 509   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 510   return tie_t;
 511 }
 512
 513 static void
 514 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 515 {
 516   uint32 tie_t;
 517   tie_t = (val << 31) >> 31;
 518   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 519 }
 520
 521 static unsigned
 522 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 523 {
 524   unsigned tie_t = 0;
 525   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 526   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 527   return tie_t;
 528 }
 529
 530 static void
 531 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 532 {
 533   uint32 tie_t;
 534   tie_t = (val << 28) >> 28;
 535   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 536   tie_t = (val << 27) >> 31;
 537   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 538 }
 539
 540 static unsigned
 541 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 542 {
 543   unsigned tie_t = 0;
 544   tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
 545   return tie_t;
 546 }
 547
 548 static void
 549 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 550 {
 551   uint32 tie_t;
 552   tie_t = (val << 20) >> 20;
 553   insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
 554 }
 555
 556 static unsigned
 557 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 558 {
 559   unsigned tie_t = 0;
 560   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 561   return tie_t;
 562 }
 563
 564 static void
 565 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 566 {
 567   uint32 tie_t;
 568   tie_t = (val << 24) >> 24;
 569   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 570 }
 571
 572 static unsigned
 573 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 574 {
 575   unsigned tie_t = 0;
 576   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 577   return tie_t;
 578 }
 579
 580 static void
 581 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 582 {
 583   uint32 tie_t;
 584   tie_t = (val << 28) >> 28;
 585   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 586 }
 587
 588 static unsigned
 589 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 590 {
 591   unsigned tie_t = 0;
 592   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 593   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 594   return tie_t;
 595 }
 596
 597 static void
 598 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 599 {
 600   uint32 tie_t;
 601   tie_t = (val << 24) >> 24;
 602   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 603   tie_t = (val << 20) >> 28;
 604   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 605 }
 606
 607 static unsigned
 608 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 609 {
 610   unsigned tie_t = 0;
 611   tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
 612   return tie_t;
 613 }
 614
 615 static void
 616 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 617 {
 618   uint32 tie_t;
 619   tie_t = (val << 16) >> 16;
 620   insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
 621 }
 622
 623 static unsigned
 624 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 625 {
 626   unsigned tie_t = 0;
 627   tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
 628   return tie_t;
 629 }
 630
 631 static void
 632 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 633 {
 634   uint32 tie_t;
 635   tie_t = (val << 14) >> 14;
 636   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
 637 }
 638
 639 static unsigned
 640 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 641 {
 642   unsigned tie_t = 0;
 643   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 644   return tie_t;
 645 }
 646
 647 static void
 648 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 649 {
 650   uint32 tie_t;
 651   tie_t = (val << 28) >> 28;
 652   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 653 }
 654
 655 static unsigned
 656 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 657 {
 658   unsigned tie_t = 0;
 659   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 660   return tie_t;
 661 }
 662
 663 static void
 664 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 665 {
 666   uint32 tie_t;
 667   tie_t = (val << 31) >> 31;
 668   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 669 }
 670
 671 static unsigned
 672 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 673 {
 674   unsigned tie_t = 0;
 675   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 676   return tie_t;
 677 }
 678
 679 static void
 680 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 681 {
 682   uint32 tie_t;
 683   tie_t = (val << 31) >> 31;
 684   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 685 }
 686
 687 static unsigned
 688 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
 689 {
 690   unsigned tie_t = 0;
 691   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 692   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 693   return tie_t;
 694 }
 695
 696 static void
 697 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 698 {
 699   uint32 tie_t;
 700   tie_t = (val << 28) >> 28;
 701   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 702   tie_t = (val << 27) >> 31;
 703   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 704 }
 705
 706 static unsigned
 707 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
 708 {
 709   unsigned tie_t = 0;
 710   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 711   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 712   return tie_t;
 713 }
 714
 715 static void
 716 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 717 {
 718   uint32 tie_t;
 719   tie_t = (val << 28) >> 28;
 720   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 721   tie_t = (val << 27) >> 31;
 722   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 723 }
 724
 725 static unsigned
 726 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
 727 {
 728   unsigned tie_t = 0;
 729   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 730   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 731   return tie_t;
 732 }
 733
 734 static void
 735 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 736 {
 737   uint32 tie_t;
 738   tie_t = (val << 28) >> 28;
 739   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 740   tie_t = (val << 27) >> 31;
 741   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 742 }
 743
 744 static unsigned
 745 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
 746 {
 747   unsigned tie_t = 0;
 748   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 749   return tie_t;
 750 }
 751
 752 static void
 753 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 754 {
 755   uint32 tie_t;
 756   tie_t = (val << 31) >> 31;
 757   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 758 }
 759
 760 static unsigned
 761 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
 762 {
 763   unsigned tie_t = 0;
 764   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 765   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 766   return tie_t;
 767 }
 768
 769 static void
 770 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 771 {
 772   uint32 tie_t;
 773   tie_t = (val << 28) >> 28;
 774   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 775   tie_t = (val << 27) >> 31;
 776   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 777 }
 778
 779 static unsigned
 780 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
 781 {
 782   unsigned tie_t = 0;
 783   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 784   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 785   return tie_t;
 786 }
 787
 788 static void
 789 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 790 {
 791   uint32 tie_t;
 792   tie_t = (val << 28) >> 28;
 793   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 794   tie_t = (val << 24) >> 28;
 795   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 796 }
 797
 798 static unsigned
 799 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
 800 {
 801   unsigned tie_t = 0;
 802   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 803   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 804   return tie_t;
 805 }
 806
 807 static void
 808 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 809 {
 810   uint32 tie_t;
 811   tie_t = (val << 28) >> 28;
 812   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 813   tie_t = (val << 24) >> 28;
 814   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 815 }
 816
 817 static unsigned
 818 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 819 {
 820   unsigned tie_t = 0;
 821   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 822   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 823   return tie_t;
 824 }
 825
 826 static void
 827 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 828 {
 829   uint32 tie_t;
 830   tie_t = (val << 28) >> 28;
 831   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 832   tie_t = (val << 24) >> 28;
 833   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 834 }
 835
 836 static unsigned
 837 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
 838 {
 839   unsigned tie_t = 0;
 840   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 841   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 842   return tie_t;
 843 }
 844
 845 static void
 846 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 847 {
 848   uint32 tie_t;
 849   tie_t = (val << 28) >> 28;
 850   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 851   tie_t = (val << 24) >> 28;
 852   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 853 }
 854
 855 static unsigned
 856 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
 857 {
 858   unsigned tie_t = 0;
 859   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 860   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 861   return tie_t;
 862 }
 863
 864 static void
 865 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 866 {
 867   uint32 tie_t;
 868   tie_t = (val << 28) >> 28;
 869   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 870   tie_t = (val << 24) >> 28;
 871   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 872 }
 873
 874 static unsigned
 875 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
 876 {
 877   unsigned tie_t = 0;
 878   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 879   return tie_t;
 880 }
 881
 882 static void
 883 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 884 {
 885   uint32 tie_t;
 886   tie_t = (val << 28) >> 28;
 887   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 888 }
 889
 890 static unsigned
 891 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
 892 {
 893   unsigned tie_t = 0;
 894   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 895   return tie_t;
 896 }
 897
 898 static void
 899 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 900 {
 901   uint32 tie_t;
 902   tie_t = (val << 28) >> 28;
 903   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 904 }
 905
 906 static unsigned
 907 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
 908 {
 909   unsigned tie_t = 0;
 910   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 911   return tie_t;
 912 }
 913
 914 static void
 915 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 916 {
 917   uint32 tie_t;
 918   tie_t = (val << 28) >> 28;
 919   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 920 }
 921
 922 static unsigned
 923 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
 924 {
 925   unsigned tie_t = 0;
 926   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 927   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 928   return tie_t;
 929 }
 930
 931 static void
 932 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 933 {
 934   uint32 tie_t;
 935   tie_t = (val << 30) >> 30;
 936   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 937   tie_t = (val << 28) >> 30;
 938   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 939 }
 940
 941 static unsigned
 942 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
 943 {
 944   unsigned tie_t = 0;
 945   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 946   return tie_t;
 947 }
 948
 949 static void
 950 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 951 {
 952   uint32 tie_t;
 953   tie_t = (val << 31) >> 31;
 954   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 955 }
 956
 957 static unsigned
 958 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
 959 {
 960   unsigned tie_t = 0;
 961   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 962   return tie_t;
 963 }
 964
 965 static void
 966 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 967 {
 968   uint32 tie_t;
 969   tie_t = (val << 28) >> 28;
 970   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 971 }
 972
 973 static unsigned
 974 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
 975 {
 976   unsigned tie_t = 0;
 977   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 978   return tie_t;
 979 }
 980
 981 static void
 982 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 983 {
 984   uint32 tie_t;
 985   tie_t = (val << 28) >> 28;
 986   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 987 }
 988
 989 static unsigned
 990 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
 991 {
 992   unsigned tie_t = 0;
 993   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
 994   return tie_t;
 995 }
 996
 997 static void
 998 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 999 {
1000   uint32 tie_t;
1001   tie_t = (val << 30) >> 30;
1002   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1003 }
1004
1005 static unsigned
1006 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1007 {
1008   unsigned tie_t = 0;
1009   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1010   return tie_t;
1011 }
1012
1013 static void
1014 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1015 {
1016   uint32 tie_t;
1017   tie_t = (val << 30) >> 30;
1018   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1019 }
1020
1021 static unsigned
1022 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1023 {
1024   unsigned tie_t = 0;
1025   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1026   return tie_t;
1027 }
1028
1029 static void
1030 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1031 {
1032   uint32 tie_t;
1033   tie_t = (val << 28) >> 28;
1034   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1035 }
1036
1037 static unsigned
1038 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1039 {
1040   unsigned tie_t = 0;
1041   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1042   return tie_t;
1043 }
1044
1045 static void
1046 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1047 {
1048   uint32 tie_t;
1049   tie_t = (val << 28) >> 28;
1050   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1051 }
1052
1053 static unsigned
1054 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1055 {
1056   unsigned tie_t = 0;
1057   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1058   return tie_t;
1059 }
1060
1061 static void
1062 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1063 {
1064   uint32 tie_t;
1065   tie_t = (val << 29) >> 29;
1066   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1067 }
1068
1069 static unsigned
1070 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1071 {
1072   unsigned tie_t = 0;
1073   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1074   return tie_t;
1075 }
1076
1077 static void
1078 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1079 {
1080   uint32 tie_t;
1081   tie_t = (val << 29) >> 29;
1082   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1083 }
1084
1085 static unsigned
1086 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1087 {
1088   unsigned tie_t = 0;
1089   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1090   return tie_t;
1091 }
1092
1093 static void
1094 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1095 {
1096   uint32 tie_t;
1097   tie_t = (val << 31) >> 31;
1098   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1099 }
1100
1101 static unsigned
1102 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1103 {
1104   unsigned tie_t = 0;
1105   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1106   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1107   return tie_t;
1108 }
1109
1110 static void
1111 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1112 {
1113   uint32 tie_t;
1114   tie_t = (val << 28) >> 28;
1115   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1116   tie_t = (val << 26) >> 30;
1117   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1118 }
1119
1120 static unsigned
1121 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1122 {
1123   unsigned tie_t = 0;
1124   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1125   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1126   return tie_t;
1127 }
1128
1129 static void
1130 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1131 {
1132   uint32 tie_t;
1133   tie_t = (val << 28) >> 28;
1134   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1135   tie_t = (val << 26) >> 30;
1136   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1137 }
1138
1139 static unsigned
1140 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1141 {
1142   unsigned tie_t = 0;
1143   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1144   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1145   return tie_t;
1146 }
1147
1148 static void
1149 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1150 {
1151   uint32 tie_t;
1152   tie_t = (val << 28) >> 28;
1153   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1154   tie_t = (val << 25) >> 29;
1155   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1156 }
1157
1158 static unsigned
1159 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1160 {
1161   unsigned tie_t = 0;
1162   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1163   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1164   return tie_t;
1165 }
1166
1167 static void
1168 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1169 {
1170   uint32 tie_t;
1171   tie_t = (val << 28) >> 28;
1172   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1173   tie_t = (val << 25) >> 29;
1174   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1175 }
1176
1177 static void
1178 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1179                     uint32 val ATTRIBUTE_UNUSED)
1180 {
1181   /* Do nothing.  */
1182 }
1183
1184 static unsigned
1185 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1186 {
1187   return 0;
1188 }
1189
1190 static unsigned
1191 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1192 {
1193   return 4;
1194 }
1195
1196 static unsigned
1197 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1198 {
1199   return 8;
1200 }
1201
1202 static unsigned
1203 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1204 {
1205   return 12;
1206 }
1207
1208 enum xtensa_field_id {
1209   FIELD_t,
1210   FIELD_bbi4,
1211   FIELD_bbi,
1212   FIELD_imm12,
1213   FIELD_imm8,
1214   FIELD_s,
1215   FIELD_imm12b,
1216   FIELD_imm16,
1217   FIELD_m,
1218   FIELD_n,
1219   FIELD_offset,
1220   FIELD_op0,
1221   FIELD_op1,
1222   FIELD_op2,
1223   FIELD_r,
1224   FIELD_sa4,
1225   FIELD_sae4,
1226   FIELD_sae,
1227   FIELD_sal,
1228   FIELD_sargt,
1229   FIELD_sas4,
1230   FIELD_sas,
1231   FIELD_sr,
1232   FIELD_st,
1233   FIELD_thi3,
1234   FIELD_imm4,
1235   FIELD_mn,
1236   FIELD_i,
1237   FIELD_imm6lo,
1238   FIELD_imm6hi,
1239   FIELD_imm7lo,
1240   FIELD_imm7hi,
1241   FIELD_z,
1242   FIELD_imm6,
1243   FIELD_imm7,
1244   FIELD__ar0,
1245   FIELD__ar4,
1246   FIELD__ar8,
1247   FIELD__ar12
1248 };
1249
1250 \f
1251 /* Functional units.  */
1252
1253 static xtensa_funcUnit_internal funcUnits[] = {
1254
1255 };
1256
1257 \f
1258 /* Register files.  */
1259
1260 enum xtensa_regfile_id {
1261   REGFILE_AR
1262 };
1263
1264 static xtensa_regfile_internal regfiles[] = {
1265   { "AR", "a", REGFILE_AR, 32, 64 }
1266 };
1267
1268 \f
1269 /* Interfaces.  */
1270
1271 static xtensa_interface_internal interfaces[] = {
1272
1273 };
1274
1275 \f
1276 /* Constant tables.  */
1277
1278 /* constant table ai4c */
1279 static const unsigned CONST_TBL_ai4c_0[] = {
1280   0xffffffff,
1281   0x1,
1282   0x2,
1283   0x3,
1284   0x4,
1285   0x5,
1286   0x6,
1287   0x7,
1288   0x8,
1289   0x9,
1290   0xa,
1291   0xb,
1292   0xc,
1293   0xd,
1294   0xe,
1295   0xf,
1296   0
1297 };
1298
1299 /* constant table b4c */
1300 static const unsigned CONST_TBL_b4c_0[] = {
1301   0xffffffff,
1302   0x1,
1303   0x2,
1304   0x3,
1305   0x4,
1306   0x5,
1307   0x6,
1308   0x7,
1309   0x8,
1310   0xa,
1311   0xc,
1312   0x10,
1313   0x20,
1314   0x40,
1315   0x80,
1316   0x100,
1317   0
1318 };
1319
1320 /* constant table b4cu */
1321 static const unsigned CONST_TBL_b4cu_0[] = {
1322   0x8000,
1323   0x10000,
1324   0x2,
1325   0x3,
1326   0x4,
1327   0x5,
1328   0x6,
1329   0x7,
1330   0x8,
1331   0xa,
1332   0xc,
1333   0x10,
1334   0x20,
1335   0x40,
1336   0x80,
1337   0x100,
1338   0
1339 };
1340
1341 \f
1342 /* Instruction operands.  */
1343
1344 static int
1345 Operand_soffsetx4_decode (uint32 *valp)
1346 {
1347   unsigned soffsetx4_0, offset_0;
1348   offset_0 = *valp & 0x3ffff;
1349   soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1350   *valp = soffsetx4_0;
1351   return 0;
1352 }
1353
1354 static int
1355 Operand_soffsetx4_encode (uint32 *valp)
1356 {
1357   unsigned offset_0, soffsetx4_0;
1358   soffsetx4_0 = *valp;
1359   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1360   *valp = offset_0;
1361   return 0;
1362 }
1363
1364 static int
1365 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1366 {
1367   *valp -= (pc & ~0x3);
1368   return 0;
1369 }
1370
1371 static int
1372 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1373 {
1374   *valp += (pc & ~0x3);
1375   return 0;
1376 }
1377
1378 static int
1379 Operand_uimm12x8_decode (uint32 *valp)
1380 {
1381   unsigned uimm12x8_0, imm12_0;
1382   imm12_0 = *valp & 0xfff;
1383   uimm12x8_0 = imm12_0 << 3;
1384   *valp = uimm12x8_0;
1385   return 0;
1386 }
1387
1388 static int
1389 Operand_uimm12x8_encode (uint32 *valp)
1390 {
1391   unsigned imm12_0, uimm12x8_0;
1392   uimm12x8_0 = *valp;
1393   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1394   *valp = imm12_0;
1395   return 0;
1396 }
1397
1398 static int
1399 Operand_simm4_decode (uint32 *valp)
1400 {
1401   unsigned simm4_0, mn_0;
1402   mn_0 = *valp & 0xf;
1403   simm4_0 = ((int) mn_0 << 28) >> 28;
1404   *valp = simm4_0;
1405   return 0;
1406 }
1407
1408 static int
1409 Operand_simm4_encode (uint32 *valp)
1410 {
1411   unsigned mn_0, simm4_0;
1412   simm4_0 = *valp;
1413   mn_0 = (simm4_0 & 0xf);
1414   *valp = mn_0;
1415   return 0;
1416 }
1417
1418 static int
1419 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1420 {
1421   return 0;
1422 }
1423
1424 static int
1425 Operand_arr_encode (uint32 *valp)
1426 {
1427   int error;
1428   error = (*valp & ~0xf) != 0;
1429   return error;
1430 }
1431
1432 static int
1433 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1434 {
1435   return 0;
1436 }
1437
1438 static int
1439 Operand_ars_encode (uint32 *valp)
1440 {
1441   int error;
1442   error = (*valp & ~0xf) != 0;
1443   return error;
1444 }
1445
1446 static int
1447 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1448 {
1449   return 0;
1450 }
1451
1452 static int
1453 Operand_art_encode (uint32 *valp)
1454 {
1455   int error;
1456   error = (*valp & ~0xf) != 0;
1457   return error;
1458 }
1459
1460 static int
1461 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1462 {
1463   return 0;
1464 }
1465
1466 static int
1467 Operand_ar0_encode (uint32 *valp)
1468 {
1469   int error;
1470   error = (*valp & ~0x3f) != 0;
1471   return error;
1472 }
1473
1474 static int
1475 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1476 {
1477   return 0;
1478 }
1479
1480 static int
1481 Operand_ar4_encode (uint32 *valp)
1482 {
1483   int error;
1484   error = (*valp & ~0x3f) != 0;
1485   return error;
1486 }
1487
1488 static int
1489 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1490 {
1491   return 0;
1492 }
1493
1494 static int
1495 Operand_ar8_encode (uint32 *valp)
1496 {
1497   int error;
1498   error = (*valp & ~0x3f) != 0;
1499   return error;
1500 }
1501
1502 static int
1503 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1504 {
1505   return 0;
1506 }
1507
1508 static int
1509 Operand_ar12_encode (uint32 *valp)
1510 {
1511   int error;
1512   error = (*valp & ~0x3f) != 0;
1513   return error;
1514 }
1515
1516 static int
1517 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1518 {
1519   return 0;
1520 }
1521
1522 static int
1523 Operand_ars_entry_encode (uint32 *valp)
1524 {
1525   int error;
1526   error = (*valp & ~0x3f) != 0;
1527   return error;
1528 }
1529
1530 static int
1531 Operand_immrx4_decode (uint32 *valp)
1532 {
1533   unsigned immrx4_0, r_0;
1534   r_0 = *valp & 0xf;
1535   immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1536   *valp = immrx4_0;
1537   return 0;
1538 }
1539
1540 static int
1541 Operand_immrx4_encode (uint32 *valp)
1542 {
1543   unsigned r_0, immrx4_0;
1544   immrx4_0 = *valp;
1545   r_0 = ((immrx4_0 >> 2) & 0xf);
1546   *valp = r_0;
1547   return 0;
1548 }
1549
1550 static int
1551 Operand_lsi4x4_decode (uint32 *valp)
1552 {
1553   unsigned lsi4x4_0, r_0;
1554   r_0 = *valp & 0xf;
1555   lsi4x4_0 = r_0 << 2;
1556   *valp = lsi4x4_0;
1557   return 0;
1558 }
1559
1560 static int
1561 Operand_lsi4x4_encode (uint32 *valp)
1562 {
1563   unsigned r_0, lsi4x4_0;
1564   lsi4x4_0 = *valp;
1565   r_0 = ((lsi4x4_0 >> 2) & 0xf);
1566   *valp = r_0;
1567   return 0;
1568 }
1569
1570 static int
1571 Operand_simm7_decode (uint32 *valp)
1572 {
1573   unsigned simm7_0, imm7_0;
1574   imm7_0 = *valp & 0x7f;
1575   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1576   *valp = simm7_0;
1577   return 0;
1578 }
1579
1580 static int
1581 Operand_simm7_encode (uint32 *valp)
1582 {
1583   unsigned imm7_0, simm7_0;
1584   simm7_0 = *valp;
1585   imm7_0 = (simm7_0 & 0x7f);
1586   *valp = imm7_0;
1587   return 0;
1588 }
1589
1590 static int
1591 Operand_uimm6_decode (uint32 *valp)
1592 {
1593   unsigned uimm6_0, imm6_0;
1594   imm6_0 = *valp & 0x3f;
1595   uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1596   *valp = uimm6_0;
1597   return 0;
1598 }
1599
1600 static int
1601 Operand_uimm6_encode (uint32 *valp)
1602 {
1603   unsigned imm6_0, uimm6_0;
1604   uimm6_0 = *valp;
1605   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1606   *valp = imm6_0;
1607   return 0;
1608 }
1609
1610 static int
1611 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1612 {
1613   *valp -= pc;
1614   return 0;
1615 }
1616
1617 static int
1618 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1619 {
1620   *valp += pc;
1621   return 0;
1622 }
1623
1624 static int
1625 Operand_ai4const_decode (uint32 *valp)
1626 {
1627   unsigned ai4const_0, t_0;
1628   t_0 = *valp & 0xf;
1629   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1630   *valp = ai4const_0;
1631   return 0;
1632 }
1633
1634 static int
1635 Operand_ai4const_encode (uint32 *valp)
1636 {
1637   unsigned t_0, ai4const_0;
1638   ai4const_0 = *valp;
1639   switch (ai4const_0)
1640     {
1641     case 0xffffffff: t_0 = 0; break;
1642     case 0x1: t_0 = 0x1; break;
1643     case 0x2: t_0 = 0x2; break;
1644     case 0x3: t_0 = 0x3; break;
1645     case 0x4: t_0 = 0x4; break;
1646     case 0x5: t_0 = 0x5; break;
1647     case 0x6: t_0 = 0x6; break;
1648     case 0x7: t_0 = 0x7; break;
1649     case 0x8: t_0 = 0x8; break;
1650     case 0x9: t_0 = 0x9; break;
1651     case 0xa: t_0 = 0xa; break;
1652     case 0xb: t_0 = 0xb; break;
1653     case 0xc: t_0 = 0xc; break;
1654     case 0xd: t_0 = 0xd; break;
1655     case 0xe: t_0 = 0xe; break;
1656     default: t_0 = 0xf; break;
1657     }
1658   *valp = t_0;
1659   return 0;
1660 }
1661
1662 static int
1663 Operand_b4const_decode (uint32 *valp)
1664 {
1665   unsigned b4const_0, r_0;
1666   r_0 = *valp & 0xf;
1667   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1668   *valp = b4const_0;
1669   return 0;
1670 }
1671
1672 static int
1673 Operand_b4const_encode (uint32 *valp)
1674 {
1675   unsigned r_0, b4const_0;
1676   b4const_0 = *valp;
1677   switch (b4const_0)
1678     {
1679     case 0xffffffff: r_0 = 0; break;
1680     case 0x1: r_0 = 0x1; break;
1681     case 0x2: r_0 = 0x2; break;
1682     case 0x3: r_0 = 0x3; break;
1683     case 0x4: r_0 = 0x4; break;
1684     case 0x5: r_0 = 0x5; break;
1685     case 0x6: r_0 = 0x6; break;
1686     case 0x7: r_0 = 0x7; break;
1687     case 0x8: r_0 = 0x8; break;
1688     case 0xa: r_0 = 0x9; break;
1689     case 0xc: r_0 = 0xa; break;
1690     case 0x10: r_0 = 0xb; break;
1691     case 0x20: r_0 = 0xc; break;
1692     case 0x40: r_0 = 0xd; break;
1693     case 0x80: r_0 = 0xe; break;
1694     default: r_0 = 0xf; break;
1695     }
1696   *valp = r_0;
1697   return 0;
1698 }
1699
1700 static int
1701 Operand_b4constu_decode (uint32 *valp)
1702 {
1703   unsigned b4constu_0, r_0;
1704   r_0 = *valp & 0xf;
1705   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1706   *valp = b4constu_0;
1707   return 0;
1708 }
1709
1710 static int
1711 Operand_b4constu_encode (uint32 *valp)
1712 {
1713   unsigned r_0, b4constu_0;
1714   b4constu_0 = *valp;
1715   switch (b4constu_0)
1716     {
1717     case 0x8000: r_0 = 0; break;
1718     case 0x10000: r_0 = 0x1; break;
1719     case 0x2: r_0 = 0x2; break;
1720     case 0x3: r_0 = 0x3; break;
1721     case 0x4: r_0 = 0x4; break;
1722     case 0x5: r_0 = 0x5; break;
1723     case 0x6: r_0 = 0x6; break;
1724     case 0x7: r_0 = 0x7; break;
1725     case 0x8: r_0 = 0x8; break;
1726     case 0xa: r_0 = 0x9; break;
1727     case 0xc: r_0 = 0xa; break;
1728     case 0x10: r_0 = 0xb; break;
1729     case 0x20: r_0 = 0xc; break;
1730     case 0x40: r_0 = 0xd; break;
1731     case 0x80: r_0 = 0xe; break;
1732     default: r_0 = 0xf; break;
1733     }
1734   *valp = r_0;
1735   return 0;
1736 }
1737
1738 static int
1739 Operand_uimm8_decode (uint32 *valp)
1740 {
1741   unsigned uimm8_0, imm8_0;
1742   imm8_0 = *valp & 0xff;
1743   uimm8_0 = imm8_0;
1744   *valp = uimm8_0;
1745   return 0;
1746 }
1747
1748 static int
1749 Operand_uimm8_encode (uint32 *valp)
1750 {
1751   unsigned imm8_0, uimm8_0;
1752   uimm8_0 = *valp;
1753   imm8_0 = (uimm8_0 & 0xff);
1754   *valp = imm8_0;
1755   return 0;
1756 }
1757
1758 static int
1759 Operand_uimm8x2_decode (uint32 *valp)
1760 {
1761   unsigned uimm8x2_0, imm8_0;
1762   imm8_0 = *valp & 0xff;
1763   uimm8x2_0 = imm8_0 << 1;
1764   *valp = uimm8x2_0;
1765   return 0;
1766 }
1767
1768 static int
1769 Operand_uimm8x2_encode (uint32 *valp)
1770 {
1771   unsigned imm8_0, uimm8x2_0;
1772   uimm8x2_0 = *valp;
1773   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1774   *valp = imm8_0;
1775   return 0;
1776 }
1777
1778 static int
1779 Operand_uimm8x4_decode (uint32 *valp)
1780 {
1781   unsigned uimm8x4_0, imm8_0;
1782   imm8_0 = *valp & 0xff;
1783   uimm8x4_0 = imm8_0 << 2;
1784   *valp = uimm8x4_0;
1785   return 0;
1786 }
1787
1788 static int
1789 Operand_uimm8x4_encode (uint32 *valp)
1790 {
1791   unsigned imm8_0, uimm8x4_0;
1792   uimm8x4_0 = *valp;
1793   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1794   *valp = imm8_0;
1795   return 0;
1796 }
1797
1798 static int
1799 Operand_uimm4x16_decode (uint32 *valp)
1800 {
1801   unsigned uimm4x16_0, op2_0;
1802   op2_0 = *valp & 0xf;
1803   uimm4x16_0 = op2_0 << 4;
1804   *valp = uimm4x16_0;
1805   return 0;
1806 }
1807
1808 static int
1809 Operand_uimm4x16_encode (uint32 *valp)
1810 {
1811   unsigned op2_0, uimm4x16_0;
1812   uimm4x16_0 = *valp;
1813   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1814   *valp = op2_0;
1815   return 0;
1816 }
1817
1818 static int
1819 Operand_simm8_decode (uint32 *valp)
1820 {
1821   unsigned simm8_0, imm8_0;
1822   imm8_0 = *valp & 0xff;
1823   simm8_0 = ((int) imm8_0 << 24) >> 24;
1824   *valp = simm8_0;
1825   return 0;
1826 }
1827
1828 static int
1829 Operand_simm8_encode (uint32 *valp)
1830 {
1831   unsigned imm8_0, simm8_0;
1832   simm8_0 = *valp;
1833   imm8_0 = (simm8_0 & 0xff);
1834   *valp = imm8_0;
1835   return 0;
1836 }
1837
1838 static int
1839 Operand_simm8x256_decode (uint32 *valp)
1840 {
1841   unsigned simm8x256_0, imm8_0;
1842   imm8_0 = *valp & 0xff;
1843   simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1844   *valp = simm8x256_0;
1845   return 0;
1846 }
1847
1848 static int
1849 Operand_simm8x256_encode (uint32 *valp)
1850 {
1851   unsigned imm8_0, simm8x256_0;
1852   simm8x256_0 = *valp;
1853   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1854   *valp = imm8_0;
1855   return 0;
1856 }
1857
1858 static int
1859 Operand_simm12b_decode (uint32 *valp)
1860 {
1861   unsigned simm12b_0, imm12b_0;
1862   imm12b_0 = *valp & 0xfff;
1863   simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1864   *valp = simm12b_0;
1865   return 0;
1866 }
1867
1868 static int
1869 Operand_simm12b_encode (uint32 *valp)
1870 {
1871   unsigned imm12b_0, simm12b_0;
1872   simm12b_0 = *valp;
1873   imm12b_0 = (simm12b_0 & 0xfff);
1874   *valp = imm12b_0;
1875   return 0;
1876 }
1877
1878 static int
1879 Operand_msalp32_decode (uint32 *valp)
1880 {
1881   unsigned msalp32_0, sal_0;
1882   sal_0 = *valp & 0x1f;
1883   msalp32_0 = 0x20 - sal_0;
1884   *valp = msalp32_0;
1885   return 0;
1886 }
1887
1888 static int
1889 Operand_msalp32_encode (uint32 *valp)
1890 {
1891   unsigned sal_0, msalp32_0;
1892   msalp32_0 = *valp;
1893   sal_0 = (0x20 - msalp32_0) & 0x1f;
1894   *valp = sal_0;
1895   return 0;
1896 }
1897
1898 static int
1899 Operand_op2p1_decode (uint32 *valp)
1900 {
1901   unsigned op2p1_0, op2_0;
1902   op2_0 = *valp & 0xf;
1903   op2p1_0 = op2_0 + 0x1;
1904   *valp = op2p1_0;
1905   return 0;
1906 }
1907
1908 static int
1909 Operand_op2p1_encode (uint32 *valp)
1910 {
1911   unsigned op2_0, op2p1_0;
1912   op2p1_0 = *valp;
1913   op2_0 = (op2p1_0 - 0x1) & 0xf;
1914   *valp = op2_0;
1915   return 0;
1916 }
1917
1918 static int
1919 Operand_label8_decode (uint32 *valp)
1920 {
1921   unsigned label8_0, imm8_0;
1922   imm8_0 = *valp & 0xff;
1923   label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1924   *valp = label8_0;
1925   return 0;
1926 }
1927
1928 static int
1929 Operand_label8_encode (uint32 *valp)
1930 {
1931   unsigned imm8_0, label8_0;
1932   label8_0 = *valp;
1933   imm8_0 = (label8_0 - 0x4) & 0xff;
1934   *valp = imm8_0;
1935   return 0;
1936 }
1937
1938 static int
1939 Operand_label8_ator (uint32 *valp, uint32 pc)
1940 {
1941   *valp -= pc;
1942   return 0;
1943 }
1944
1945 static int
1946 Operand_label8_rtoa (uint32 *valp, uint32 pc)
1947 {
1948   *valp += pc;
1949   return 0;
1950 }
1951
1952 static int
1953 Operand_ulabel8_decode (uint32 *valp)
1954 {
1955   unsigned ulabel8_0, imm8_0;
1956   imm8_0 = *valp & 0xff;
1957   ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
1958   *valp = ulabel8_0;
1959   return 0;
1960 }
1961
1962 static int
1963 Operand_ulabel8_encode (uint32 *valp)
1964 {
1965   unsigned imm8_0, ulabel8_0;
1966   ulabel8_0 = *valp;
1967   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
1968   *valp = imm8_0;
1969   return 0;
1970 }
1971
1972 static int
1973 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
1974 {
1975   *valp -= pc;
1976   return 0;
1977 }
1978
1979 static int
1980 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
1981 {
1982   *valp += pc;
1983   return 0;
1984 }
1985
1986 static int
1987 Operand_label12_decode (uint32 *valp)
1988 {
1989   unsigned label12_0, imm12_0;
1990   imm12_0 = *valp & 0xfff;
1991   label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
1992   *valp = label12_0;
1993   return 0;
1994 }
1995
1996 static int
1997 Operand_label12_encode (uint32 *valp)
1998 {
1999   unsigned imm12_0, label12_0;
2000   label12_0 = *valp;
2001   imm12_0 = (label12_0 - 0x4) & 0xfff;
2002   *valp = imm12_0;
2003   return 0;
2004 }
2005
2006 static int
2007 Operand_label12_ator (uint32 *valp, uint32 pc)
2008 {
2009   *valp -= pc;
2010   return 0;
2011 }
2012
2013 static int
2014 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2015 {
2016   *valp += pc;
2017   return 0;
2018 }
2019
2020 static int
2021 Operand_soffset_decode (uint32 *valp)
2022 {
2023   unsigned soffset_0, offset_0;
2024   offset_0 = *valp & 0x3ffff;
2025   soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2026   *valp = soffset_0;
2027   return 0;
2028 }
2029
2030 static int
2031 Operand_soffset_encode (uint32 *valp)
2032 {
2033   unsigned offset_0, soffset_0;
2034   soffset_0 = *valp;
2035   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2036   *valp = offset_0;
2037   return 0;
2038 }
2039
2040 static int
2041 Operand_soffset_ator (uint32 *valp, uint32 pc)
2042 {
2043   *valp -= pc;
2044   return 0;
2045 }
2046
2047 static int
2048 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2049 {
2050   *valp += pc;
2051   return 0;
2052 }
2053
2054 static int
2055 Operand_uimm16x4_decode (uint32 *valp)
2056 {
2057   unsigned uimm16x4_0, imm16_0;
2058   imm16_0 = *valp & 0xffff;
2059   uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2060   *valp = uimm16x4_0;
2061   return 0;
2062 }
2063
2064 static int
2065 Operand_uimm16x4_encode (uint32 *valp)
2066 {
2067   unsigned imm16_0, uimm16x4_0;
2068   uimm16x4_0 = *valp;
2069   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2070   *valp = imm16_0;
2071   return 0;
2072 }
2073
2074 static int
2075 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2076 {
2077   *valp -= ((pc + 3) & ~0x3);
2078   return 0;
2079 }
2080
2081 static int
2082 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2083 {
2084   *valp += ((pc + 3) & ~0x3);
2085   return 0;
2086 }
2087
2088 static int
2089 Operand_immt_decode (uint32 *valp)
2090 {
2091   unsigned immt_0, t_0;
2092   t_0 = *valp & 0xf;
2093   immt_0 = t_0;
2094   *valp = immt_0;
2095   return 0;
2096 }
2097
2098 static int
2099 Operand_immt_encode (uint32 *valp)
2100 {
2101   unsigned t_0, immt_0;
2102   immt_0 = *valp;
2103   t_0 = immt_0 & 0xf;
2104   *valp = t_0;
2105   return 0;
2106 }
2107
2108 static int
2109 Operand_imms_decode (uint32 *valp)
2110 {
2111   unsigned imms_0, s_0;
2112   s_0 = *valp & 0xf;
2113   imms_0 = s_0;
2114   *valp = imms_0;
2115   return 0;
2116 }
2117
2118 static int
2119 Operand_imms_encode (uint32 *valp)
2120 {
2121   unsigned s_0, imms_0;
2122   imms_0 = *valp;
2123   s_0 = imms_0 & 0xf;
2124   *valp = s_0;
2125   return 0;
2126 }
2127
2128 static xtensa_operand_internal operands[] = {
2129   { "soffsetx4", FIELD_offset, -1, 0,
2130     XTENSA_OPERAND_IS_PCRELATIVE,
2131     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2132     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2133   { "uimm12x8", FIELD_imm12, -1, 0,
2134     0,
2135     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2136     0, 0 },
2137   { "simm4", FIELD_mn, -1, 0,
2138     0,
2139     Operand_simm4_encode, Operand_simm4_decode,
2140     0, 0 },
2141   { "arr", FIELD_r, REGFILE_AR, 1,
2142     XTENSA_OPERAND_IS_REGISTER,
2143     Operand_arr_encode, Operand_arr_decode,
2144     0, 0 },
2145   { "ars", FIELD_s, REGFILE_AR, 1,
2146     XTENSA_OPERAND_IS_REGISTER,
2147     Operand_ars_encode, Operand_ars_decode,
2148     0, 0 },
2149   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2150     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2151     Operand_ars_encode, Operand_ars_decode,
2152     0, 0 },
2153   { "art", FIELD_t, REGFILE_AR, 1,
2154     XTENSA_OPERAND_IS_REGISTER,
2155     Operand_art_encode, Operand_art_decode,
2156     0, 0 },
2157   { "ar0", FIELD__ar0, REGFILE_AR, 1,
2158     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2159     Operand_ar0_encode, Operand_ar0_decode,
2160     0, 0 },
2161   { "ar4", FIELD__ar4, REGFILE_AR, 1,
2162     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2163     Operand_ar4_encode, Operand_ar4_decode,
2164     0, 0 },
2165   { "ar8", FIELD__ar8, REGFILE_AR, 1,
2166     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2167     Operand_ar8_encode, Operand_ar8_decode,
2168     0, 0 },
2169   { "ar12", FIELD__ar12, REGFILE_AR, 1,
2170     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2171     Operand_ar12_encode, Operand_ar12_decode,
2172     0, 0 },
2173   { "ars_entry", FIELD_s, REGFILE_AR, 1,
2174     XTENSA_OPERAND_IS_REGISTER,
2175     Operand_ars_entry_encode, Operand_ars_entry_decode,
2176     0, 0 },
2177   { "immrx4", FIELD_r, -1, 0,
2178     0,
2179     Operand_immrx4_encode, Operand_immrx4_decode,
2180     0, 0 },
2181   { "lsi4x4", FIELD_r, -1, 0,
2182     0,
2183     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2184     0, 0 },
2185   { "simm7", FIELD_imm7, -1, 0,
2186     0,
2187     Operand_simm7_encode, Operand_simm7_decode,
2188     0, 0 },
2189   { "uimm6", FIELD_imm6, -1, 0,
2190     XTENSA_OPERAND_IS_PCRELATIVE,
2191     Operand_uimm6_encode, Operand_uimm6_decode,
2192     Operand_uimm6_ator, Operand_uimm6_rtoa },
2193   { "ai4const", FIELD_t, -1, 0,
2194     0,
2195     Operand_ai4const_encode, Operand_ai4const_decode,
2196     0, 0 },
2197   { "b4const", FIELD_r, -1, 0,
2198     0,
2199     Operand_b4const_encode, Operand_b4const_decode,
2200     0, 0 },
2201   { "b4constu", FIELD_r, -1, 0,
2202     0,
2203     Operand_b4constu_encode, Operand_b4constu_decode,
2204     0, 0 },
2205   { "uimm8", FIELD_imm8, -1, 0,
2206     0,
2207     Operand_uimm8_encode, Operand_uimm8_decode,
2208     0, 0 },
2209   { "uimm8x2", FIELD_imm8, -1, 0,
2210     0,
2211     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2212     0, 0 },
2213   { "uimm8x4", FIELD_imm8, -1, 0,
2214     0,
2215     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2216     0, 0 },
2217   { "uimm4x16", FIELD_op2, -1, 0,
2218     0,
2219     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2220     0, 0 },
2221   { "simm8", FIELD_imm8, -1, 0,
2222     0,
2223     Operand_simm8_encode, Operand_simm8_decode,
2224     0, 0 },
2225   { "simm8x256", FIELD_imm8, -1, 0,
2226     0,
2227     Operand_simm8x256_encode, Operand_simm8x256_decode,
2228     0, 0 },
2229   { "simm12b", FIELD_imm12b, -1, 0,
2230     0,
2231     Operand_simm12b_encode, Operand_simm12b_decode,
2232     0, 0 },
2233   { "msalp32", FIELD_sal, -1, 0,
2234     0,
2235     Operand_msalp32_encode, Operand_msalp32_decode,
2236     0, 0 },
2237   { "op2p1", FIELD_op2, -1, 0,
2238     0,
2239     Operand_op2p1_encode, Operand_op2p1_decode,
2240     0, 0 },
2241   { "label8", FIELD_imm8, -1, 0,
2242     XTENSA_OPERAND_IS_PCRELATIVE,
2243     Operand_label8_encode, Operand_label8_decode,
2244     Operand_label8_ator, Operand_label8_rtoa },
2245   { "ulabel8", FIELD_imm8, -1, 0,
2246     XTENSA_OPERAND_IS_PCRELATIVE,
2247     Operand_ulabel8_encode, Operand_ulabel8_decode,
2248     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2249   { "label12", FIELD_imm12, -1, 0,
2250     XTENSA_OPERAND_IS_PCRELATIVE,
2251     Operand_label12_encode, Operand_label12_decode,
2252     Operand_label12_ator, Operand_label12_rtoa },
2253   { "soffset", FIELD_offset, -1, 0,
2254     XTENSA_OPERAND_IS_PCRELATIVE,
2255     Operand_soffset_encode, Operand_soffset_decode,
2256     Operand_soffset_ator, Operand_soffset_rtoa },
2257   { "uimm16x4", FIELD_imm16, -1, 0,
2258     XTENSA_OPERAND_IS_PCRELATIVE,
2259     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2260     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2261   { "immt", FIELD_t, -1, 0,
2262     0,
2263     Operand_immt_encode, Operand_immt_decode,
2264     0, 0 },
2265   { "imms", FIELD_s, -1, 0,
2266     0,
2267     Operand_imms_encode, Operand_imms_decode,
2268     0, 0 },
2269   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2270   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2271   { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
2272   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2273   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2274   { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
2275   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2276   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2277   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2278   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2279   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2280   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2281   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2282   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2283   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2284   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2285   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2286   { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
2287   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2288   { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
2289   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2290   { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
2291   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2292   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2293   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2294   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2295   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2296   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2297   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2298   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2299   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2300   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2301   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2302   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2303   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }
2304 };
2305
2306 enum xtensa_operand_id {
2307   OPERAND_soffsetx4,
2308   OPERAND_uimm12x8,
2309   OPERAND_simm4,
2310   OPERAND_arr,
2311   OPERAND_ars,
2312   OPERAND__ars_invisible,
2313   OPERAND_art,
2314   OPERAND_ar0,
2315   OPERAND_ar4,
2316   OPERAND_ar8,
2317   OPERAND_ar12,
2318   OPERAND_ars_entry,
2319   OPERAND_immrx4,
2320   OPERAND_lsi4x4,
2321   OPERAND_simm7,
2322   OPERAND_uimm6,
2323   OPERAND_ai4const,
2324   OPERAND_b4const,
2325   OPERAND_b4constu,
2326   OPERAND_uimm8,
2327   OPERAND_uimm8x2,
2328   OPERAND_uimm8x4,
2329   OPERAND_uimm4x16,
2330   OPERAND_simm8,
2331   OPERAND_simm8x256,
2332   OPERAND_simm12b,
2333   OPERAND_msalp32,
2334   OPERAND_op2p1,
2335   OPERAND_label8,
2336   OPERAND_ulabel8,
2337   OPERAND_label12,
2338   OPERAND_soffset,
2339   OPERAND_uimm16x4,
2340   OPERAND_immt,
2341   OPERAND_imms,
2342   OPERAND_t,
2343   OPERAND_bbi4,
2344   OPERAND_bbi,
2345   OPERAND_imm12,
2346   OPERAND_imm8,
2347   OPERAND_s,
2348   OPERAND_imm12b,
2349   OPERAND_imm16,
2350   OPERAND_m,
2351   OPERAND_n,
2352   OPERAND_offset,
2353   OPERAND_op0,
2354   OPERAND_op1,
2355   OPERAND_op2,
2356   OPERAND_r,
2357   OPERAND_sa4,
2358   OPERAND_sae4,
2359   OPERAND_sae,
2360   OPERAND_sal,
2361   OPERAND_sargt,
2362   OPERAND_sas4,
2363   OPERAND_sas,
2364   OPERAND_sr,
2365   OPERAND_st,
2366   OPERAND_thi3,
2367   OPERAND_imm4,
2368   OPERAND_mn,
2369   OPERAND_i,
2370   OPERAND_imm6lo,
2371   OPERAND_imm6hi,
2372   OPERAND_imm7lo,
2373   OPERAND_imm7hi,
2374   OPERAND_z,
2375   OPERAND_imm6,
2376   OPERAND_imm7
2377 };
2378
2379 \f
2380 /* Iclass table.  */
2381
2382 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2383   { { STATE_PSRING }, 'i' },
2384   { { STATE_PSEXCM }, 'm' },
2385   { { STATE_EPC1 }, 'i' }
2386 };
2387
2388 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2389   { { STATE_PSEXCM }, 'i' },
2390   { { STATE_PSRING }, 'i' },
2391   { { STATE_DEPC }, 'i' }
2392 };
2393
2394 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2395   { { OPERAND_soffsetx4 }, 'i' },
2396   { { OPERAND_ar12 }, 'o' }
2397 };
2398
2399 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2400   { { STATE_PSCALLINC }, 'o' }
2401 };
2402
2403 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2404   { { OPERAND_soffsetx4 }, 'i' },
2405   { { OPERAND_ar8 }, 'o' }
2406 };
2407
2408 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2409   { { STATE_PSCALLINC }, 'o' }
2410 };
2411
2412 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2413   { { OPERAND_soffsetx4 }, 'i' },
2414   { { OPERAND_ar4 }, 'o' }
2415 };
2416
2417 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2418   { { STATE_PSCALLINC }, 'o' }
2419 };
2420
2421 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2422   { { OPERAND_ars }, 'i' },
2423   { { OPERAND_ar12 }, 'o' }
2424 };
2425
2426 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2427   { { STATE_PSCALLINC }, 'o' }
2428 };
2429
2430 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2431   { { OPERAND_ars }, 'i' },
2432   { { OPERAND_ar8 }, 'o' }
2433 };
2434
2435 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2436   { { STATE_PSCALLINC }, 'o' }
2437 };
2438
2439 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2440   { { OPERAND_ars }, 'i' },
2441   { { OPERAND_ar4 }, 'o' }
2442 };
2443
2444 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2445   { { STATE_PSCALLINC }, 'o' }
2446 };
2447
2448 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2449   { { OPERAND_ars_entry }, 's' },
2450   { { OPERAND_ars }, 'i' },
2451   { { OPERAND_uimm12x8 }, 'i' }
2452 };
2453
2454 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2455   { { STATE_PSCALLINC }, 'i' },
2456   { { STATE_PSEXCM }, 'i' },
2457   { { STATE_PSWOE }, 'i' },
2458   { { STATE_WindowBase }, 'm' },
2459   { { STATE_WindowStart }, 'm' }
2460 };
2461
2462 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2463   { { OPERAND_art }, 'o' },
2464   { { OPERAND_ars }, 'i' }
2465 };
2466
2467 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2468   { { STATE_WindowBase }, 'i' },
2469   { { STATE_WindowStart }, 'i' }
2470 };
2471
2472 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2473   { { OPERAND_simm4 }, 'i' }
2474 };
2475
2476 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2477   { { STATE_PSEXCM }, 'i' },
2478   { { STATE_PSRING }, 'i' },
2479   { { STATE_WindowBase }, 'm' }
2480 };
2481
2482 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2483   { { OPERAND__ars_invisible }, 'i' }
2484 };
2485
2486 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2487   { { STATE_WindowBase }, 'm' },
2488   { { STATE_WindowStart }, 'm' },
2489   { { STATE_PSEXCM }, 'i' },
2490   { { STATE_PSWOE }, 'i' }
2491 };
2492
2493 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2494   { { STATE_EPC1 }, 'i' },
2495   { { STATE_PSEXCM }, 'm' },
2496   { { STATE_PSRING }, 'i' },
2497   { { STATE_WindowBase }, 'm' },
2498   { { STATE_WindowStart }, 'm' },
2499   { { STATE_PSOWB }, 'i' }
2500 };
2501
2502 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2503   { { OPERAND_art }, 'o' },
2504   { { OPERAND_ars }, 'i' },
2505   { { OPERAND_immrx4 }, 'i' }
2506 };
2507
2508 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2509   { { STATE_PSEXCM }, 'i' },
2510   { { STATE_PSRING }, 'i' }
2511 };
2512
2513 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2514   { { OPERAND_art }, 'i' },
2515   { { OPERAND_ars }, 'i' },
2516   { { OPERAND_immrx4 }, 'i' }
2517 };
2518
2519 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2520   { { STATE_PSEXCM }, 'i' },
2521   { { STATE_PSRING }, 'i' }
2522 };
2523
2524 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2525   { { OPERAND_art }, 'o' }
2526 };
2527
2528 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2529   { { STATE_PSEXCM }, 'i' },
2530   { { STATE_PSRING }, 'i' },
2531   { { STATE_WindowBase }, 'i' }
2532 };
2533
2534 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2535   { { OPERAND_art }, 'i' }
2536 };
2537
2538 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2539   { { STATE_PSEXCM }, 'i' },
2540   { { STATE_PSRING }, 'i' },
2541   { { STATE_WindowBase }, 'o' }
2542 };
2543
2544 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2545   { { OPERAND_art }, 'm' }
2546 };
2547
2548 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2549   { { STATE_PSEXCM }, 'i' },
2550   { { STATE_PSRING }, 'i' },
2551   { { STATE_WindowBase }, 'm' }
2552 };
2553
2554 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2555   { { OPERAND_art }, 'o' }
2556 };
2557
2558 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2559   { { STATE_PSEXCM }, 'i' },
2560   { { STATE_PSRING }, 'i' },
2561   { { STATE_WindowStart }, 'i' }
2562 };
2563
2564 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2565   { { OPERAND_art }, 'i' }
2566 };
2567
2568 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2569   { { STATE_PSEXCM }, 'i' },
2570   { { STATE_PSRING }, 'i' },
2571   { { STATE_WindowStart }, 'o' }
2572 };
2573
2574 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2575   { { OPERAND_art }, 'm' }
2576 };
2577
2578 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2579   { { STATE_PSEXCM }, 'i' },
2580   { { STATE_PSRING }, 'i' },
2581   { { STATE_WindowStart }, 'm' }
2582 };
2583
2584 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2585   { { OPERAND_arr }, 'o' },
2586   { { OPERAND_ars }, 'i' },
2587   { { OPERAND_art }, 'i' }
2588 };
2589
2590 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2591   { { OPERAND_arr }, 'o' },
2592   { { OPERAND_ars }, 'i' },
2593   { { OPERAND_ai4const }, 'i' }
2594 };
2595
2596 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2597   { { OPERAND_ars }, 'i' },
2598   { { OPERAND_uimm6 }, 'i' }
2599 };
2600
2601 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2602   { { OPERAND_art }, 'o' },
2603   { { OPERAND_ars }, 'i' },
2604   { { OPERAND_lsi4x4 }, 'i' }
2605 };
2606
2607 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2608   { { OPERAND_art }, 'o' },
2609   { { OPERAND_ars }, 'i' }
2610 };
2611
2612 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2613   { { OPERAND_ars }, 'o' },
2614   { { OPERAND_simm7 }, 'i' }
2615 };
2616
2617 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2618   { { OPERAND__ars_invisible }, 'i' }
2619 };
2620
2621 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2622   { { OPERAND_art }, 'i' },
2623   { { OPERAND_ars }, 'i' },
2624   { { OPERAND_lsi4x4 }, 'i' }
2625 };
2626
2627 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2628   { { OPERAND_art }, 'o' },
2629   { { OPERAND_ars }, 'i' },
2630   { { OPERAND_simm8 }, 'i' }
2631 };
2632
2633 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2634   { { OPERAND_art }, 'o' },
2635   { { OPERAND_ars }, 'i' },
2636   { { OPERAND_simm8x256 }, 'i' }
2637 };
2638
2639 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2640   { { OPERAND_arr }, 'o' },
2641   { { OPERAND_ars }, 'i' },
2642   { { OPERAND_art }, 'i' }
2643 };
2644
2645 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2646   { { OPERAND_arr }, 'o' },
2647   { { OPERAND_ars }, 'i' },
2648   { { OPERAND_art }, 'i' }
2649 };
2650
2651 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2652   { { OPERAND_ars }, 'i' },
2653   { { OPERAND_b4const }, 'i' },
2654   { { OPERAND_label8 }, 'i' }
2655 };
2656
2657 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2658   { { OPERAND_ars }, 'i' },
2659   { { OPERAND_bbi }, 'i' },
2660   { { OPERAND_label8 }, 'i' }
2661 };
2662
2663 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2664   { { OPERAND_ars }, 'i' },
2665   { { OPERAND_b4constu }, 'i' },
2666   { { OPERAND_label8 }, 'i' }
2667 };
2668
2669 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2670   { { OPERAND_ars }, 'i' },
2671   { { OPERAND_art }, 'i' },
2672   { { OPERAND_label8 }, 'i' }
2673 };
2674
2675 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2676   { { OPERAND_ars }, 'i' },
2677   { { OPERAND_label12 }, 'i' }
2678 };
2679
2680 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2681   { { OPERAND_soffsetx4 }, 'i' },
2682   { { OPERAND_ar0 }, 'o' }
2683 };
2684
2685 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2686   { { OPERAND_ars }, 'i' },
2687   { { OPERAND_ar0 }, 'o' }
2688 };
2689
2690 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2691   { { OPERAND_arr }, 'o' },
2692   { { OPERAND_art }, 'i' },
2693   { { OPERAND_sae }, 'i' },
2694   { { OPERAND_op2p1 }, 'i' }
2695 };
2696
2697 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
2698   { { OPERAND_soffset }, 'i' }
2699 };
2700
2701 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
2702   { { OPERAND_ars }, 'i' }
2703 };
2704
2705 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
2706   { { OPERAND_art }, 'o' },
2707   { { OPERAND_ars }, 'i' },
2708   { { OPERAND_uimm8x2 }, 'i' }
2709 };
2710
2711 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
2712   { { OPERAND_art }, 'o' },
2713   { { OPERAND_ars }, 'i' },
2714   { { OPERAND_uimm8x2 }, 'i' }
2715 };
2716
2717 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
2718   { { OPERAND_art }, 'o' },
2719   { { OPERAND_ars }, 'i' },
2720   { { OPERAND_uimm8x4 }, 'i' }
2721 };
2722
2723 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
2724   { { OPERAND_art }, 'o' },
2725   { { OPERAND_uimm16x4 }, 'i' }
2726 };
2727
2728 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2729   { { STATE_LITBADDR }, 'i' },
2730   { { STATE_LITBEN }, 'i' }
2731 };
2732
2733 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
2734   { { OPERAND_art }, 'o' },
2735   { { OPERAND_ars }, 'i' },
2736   { { OPERAND_uimm8 }, 'i' }
2737 };
2738
2739 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
2740   { { OPERAND_ars }, 'i' },
2741   { { OPERAND_ulabel8 }, 'i' }
2742 };
2743
2744 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
2745   { { STATE_LBEG }, 'o' },
2746   { { STATE_LEND }, 'o' },
2747   { { STATE_LCOUNT }, 'o' }
2748 };
2749
2750 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
2751   { { OPERAND_ars }, 'i' },
2752   { { OPERAND_ulabel8 }, 'i' }
2753 };
2754
2755 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
2756   { { STATE_LBEG }, 'o' },
2757   { { STATE_LEND }, 'o' },
2758   { { STATE_LCOUNT }, 'o' }
2759 };
2760
2761 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
2762   { { OPERAND_art }, 'o' },
2763   { { OPERAND_simm12b }, 'i' }
2764 };
2765
2766 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
2767   { { OPERAND_arr }, 'm' },
2768   { { OPERAND_ars }, 'i' },
2769   { { OPERAND_art }, 'i' }
2770 };
2771
2772 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
2773   { { OPERAND_arr }, 'o' },
2774   { { OPERAND_art }, 'i' }
2775 };
2776
2777 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
2778   { { OPERAND__ars_invisible }, 'i' }
2779 };
2780
2781 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
2782   { { OPERAND_art }, 'i' },
2783   { { OPERAND_ars }, 'i' },
2784   { { OPERAND_uimm8x2 }, 'i' }
2785 };
2786
2787 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
2788   { { OPERAND_art }, 'i' },
2789   { { OPERAND_ars }, 'i' },
2790   { { OPERAND_uimm8x4 }, 'i' }
2791 };
2792
2793 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
2794   { { OPERAND_art }, 'i' },
2795   { { OPERAND_ars }, 'i' },
2796   { { OPERAND_uimm8 }, 'i' }
2797 };
2798
2799 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
2800   { { OPERAND_ars }, 'i' }
2801 };
2802
2803 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
2804   { { STATE_SAR }, 'o' }
2805 };
2806
2807 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
2808   { { OPERAND_sas }, 'i' }
2809 };
2810
2811 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
2812   { { STATE_SAR }, 'o' }
2813 };
2814
2815 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
2816   { { OPERAND_arr }, 'o' },
2817   { { OPERAND_ars }, 'i' }
2818 };
2819
2820 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
2821   { { STATE_SAR }, 'i' }
2822 };
2823
2824 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
2825   { { OPERAND_arr }, 'o' },
2826   { { OPERAND_ars }, 'i' },
2827   { { OPERAND_art }, 'i' }
2828 };
2829
2830 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
2831   { { STATE_SAR }, 'i' }
2832 };
2833
2834 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
2835   { { OPERAND_arr }, 'o' },
2836   { { OPERAND_art }, 'i' }
2837 };
2838
2839 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
2840   { { STATE_SAR }, 'i' }
2841 };
2842
2843 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
2844   { { OPERAND_arr }, 'o' },
2845   { { OPERAND_ars }, 'i' },
2846   { { OPERAND_msalp32 }, 'i' }
2847 };
2848
2849 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
2850   { { OPERAND_arr }, 'o' },
2851   { { OPERAND_art }, 'i' },
2852   { { OPERAND_sargt }, 'i' }
2853 };
2854
2855 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
2856   { { OPERAND_arr }, 'o' },
2857   { { OPERAND_art }, 'i' },
2858   { { OPERAND_s }, 'i' }
2859 };
2860
2861 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
2862   { { STATE_XTSYNC }, 'i' }
2863 };
2864
2865 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
2866   { { OPERAND_art }, 'o' },
2867   { { OPERAND_s }, 'i' }
2868 };
2869
2870 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
2871   { { STATE_PSWOE }, 'i' },
2872   { { STATE_PSCALLINC }, 'i' },
2873   { { STATE_PSOWB }, 'i' },
2874   { { STATE_PSRING }, 'i' },
2875   { { STATE_PSUM }, 'i' },
2876   { { STATE_PSEXCM }, 'i' },
2877   { { STATE_PSINTLEVEL }, 'm' }
2878 };
2879
2880 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
2881   { { OPERAND_art }, 'o' }
2882 };
2883
2884 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
2885   { { STATE_LEND }, 'i' }
2886 };
2887
2888 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
2889   { { OPERAND_art }, 'i' }
2890 };
2891
2892 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
2893   { { STATE_LEND }, 'o' }
2894 };
2895
2896 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
2897   { { OPERAND_art }, 'm' }
2898 };
2899
2900 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
2901   { { STATE_LEND }, 'm' }
2902 };
2903
2904 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
2905   { { OPERAND_art }, 'o' }
2906 };
2907
2908 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
2909   { { STATE_LCOUNT }, 'i' }
2910 };
2911
2912 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
2913   { { OPERAND_art }, 'i' }
2914 };
2915
2916 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
2917   { { STATE_XTSYNC }, 'o' },
2918   { { STATE_LCOUNT }, 'o' }
2919 };
2920
2921 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
2922   { { OPERAND_art }, 'm' }
2923 };
2924
2925 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
2926   { { STATE_XTSYNC }, 'o' },
2927   { { STATE_LCOUNT }, 'm' }
2928 };
2929
2930 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
2931   { { OPERAND_art }, 'o' }
2932 };
2933
2934 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
2935   { { STATE_LBEG }, 'i' }
2936 };
2937
2938 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
2939   { { OPERAND_art }, 'i' }
2940 };
2941
2942 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
2943   { { STATE_LBEG }, 'o' }
2944 };
2945
2946 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
2947   { { OPERAND_art }, 'm' }
2948 };
2949
2950 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
2951   { { STATE_LBEG }, 'm' }
2952 };
2953
2954 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
2955   { { OPERAND_art }, 'o' }
2956 };
2957
2958 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
2959   { { STATE_SAR }, 'i' }
2960 };
2961
2962 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
2963   { { OPERAND_art }, 'i' }
2964 };
2965
2966 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
2967   { { STATE_SAR }, 'o' },
2968   { { STATE_XTSYNC }, 'o' }
2969 };
2970
2971 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
2972   { { OPERAND_art }, 'm' }
2973 };
2974
2975 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
2976   { { STATE_SAR }, 'm' }
2977 };
2978
2979 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
2980   { { OPERAND_art }, 'o' }
2981 };
2982
2983 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
2984   { { STATE_LITBADDR }, 'i' },
2985   { { STATE_LITBEN }, 'i' }
2986 };
2987
2988 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
2989   { { OPERAND_art }, 'i' }
2990 };
2991
2992 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
2993   { { STATE_LITBADDR }, 'o' },
2994   { { STATE_LITBEN }, 'o' }
2995 };
2996
2997 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
2998   { { OPERAND_art }, 'm' }
2999 };
3000
3001 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3002   { { STATE_LITBADDR }, 'm' },
3003   { { STATE_LITBEN }, 'm' }
3004 };
3005
3006 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
3007   { { OPERAND_art }, 'o' }
3008 };
3009
3010 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3011   { { STATE_PSEXCM }, 'i' },
3012   { { STATE_PSRING }, 'i' }
3013 };
3014
3015 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
3016   { { OPERAND_art }, 'o' }
3017 };
3018
3019 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3020   { { STATE_PSEXCM }, 'i' },
3021   { { STATE_PSRING }, 'i' }
3022 };
3023
3024 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3025   { { OPERAND_art }, 'o' }
3026 };
3027
3028 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3029   { { STATE_PSWOE }, 'i' },
3030   { { STATE_PSCALLINC }, 'i' },
3031   { { STATE_PSOWB }, 'i' },
3032   { { STATE_PSRING }, 'i' },
3033   { { STATE_PSUM }, 'i' },
3034   { { STATE_PSEXCM }, 'i' },
3035   { { STATE_PSINTLEVEL }, 'i' }
3036 };
3037
3038 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3039   { { OPERAND_art }, 'i' }
3040 };
3041
3042 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3043   { { STATE_PSWOE }, 'o' },
3044   { { STATE_PSCALLINC }, 'o' },
3045   { { STATE_PSOWB }, 'o' },
3046   { { STATE_PSRING }, 'm' },
3047   { { STATE_PSUM }, 'o' },
3048   { { STATE_PSEXCM }, 'm' },
3049   { { STATE_PSINTLEVEL }, 'o' }
3050 };
3051
3052 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3053   { { OPERAND_art }, 'm' }
3054 };
3055
3056 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3057   { { STATE_PSWOE }, 'm' },
3058   { { STATE_PSCALLINC }, 'm' },
3059   { { STATE_PSOWB }, 'm' },
3060   { { STATE_PSRING }, 'm' },
3061   { { STATE_PSUM }, 'm' },
3062   { { STATE_PSEXCM }, 'm' },
3063   { { STATE_PSINTLEVEL }, 'm' }
3064 };
3065
3066 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3067   { { OPERAND_art }, 'o' }
3068 };
3069
3070 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3071   { { STATE_PSEXCM }, 'i' },
3072   { { STATE_PSRING }, 'i' },
3073   { { STATE_EPC1 }, 'i' }
3074 };
3075
3076 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3077   { { OPERAND_art }, 'i' }
3078 };
3079
3080 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3081   { { STATE_PSEXCM }, 'i' },
3082   { { STATE_PSRING }, 'i' },
3083   { { STATE_EPC1 }, 'o' }
3084 };
3085
3086 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3087   { { OPERAND_art }, 'm' }
3088 };
3089
3090 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3091   { { STATE_PSEXCM }, 'i' },
3092   { { STATE_PSRING }, 'i' },
3093   { { STATE_EPC1 }, 'm' }
3094 };
3095
3096 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3097   { { OPERAND_art }, 'o' }
3098 };
3099
3100 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3101   { { STATE_PSEXCM }, 'i' },
3102   { { STATE_PSRING }, 'i' },
3103   { { STATE_EXCSAVE1 }, 'i' }
3104 };
3105
3106 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3107   { { OPERAND_art }, 'i' }
3108 };
3109
3110 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3111   { { STATE_PSEXCM }, 'i' },
3112   { { STATE_PSRING }, 'i' },
3113   { { STATE_EXCSAVE1 }, 'o' }
3114 };
3115
3116 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3117   { { OPERAND_art }, 'm' }
3118 };
3119
3120 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3121   { { STATE_PSEXCM }, 'i' },
3122   { { STATE_PSRING }, 'i' },
3123   { { STATE_EXCSAVE1 }, 'm' }
3124 };
3125
3126 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3127   { { OPERAND_art }, 'o' }
3128 };
3129
3130 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3131   { { STATE_PSEXCM }, 'i' },
3132   { { STATE_PSRING }, 'i' },
3133   { { STATE_EPC2 }, 'i' }
3134 };
3135
3136 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3137   { { OPERAND_art }, 'i' }
3138 };
3139
3140 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3141   { { STATE_PSEXCM }, 'i' },
3142   { { STATE_PSRING }, 'i' },
3143   { { STATE_EPC2 }, 'o' }
3144 };
3145
3146 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3147   { { OPERAND_art }, 'm' }
3148 };
3149
3150 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3151   { { STATE_PSEXCM }, 'i' },
3152   { { STATE_PSRING }, 'i' },
3153   { { STATE_EPC2 }, 'm' }
3154 };
3155
3156 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3157   { { OPERAND_art }, 'o' }
3158 };
3159
3160 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3161   { { STATE_PSEXCM }, 'i' },
3162   { { STATE_PSRING }, 'i' },
3163   { { STATE_EXCSAVE2 }, 'i' }
3164 };
3165
3166 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3167   { { OPERAND_art }, 'i' }
3168 };
3169
3170 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3171   { { STATE_PSEXCM }, 'i' },
3172   { { STATE_PSRING }, 'i' },
3173   { { STATE_EXCSAVE2 }, 'o' }
3174 };
3175
3176 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3177   { { OPERAND_art }, 'm' }
3178 };
3179
3180 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3181   { { STATE_PSEXCM }, 'i' },
3182   { { STATE_PSRING }, 'i' },
3183   { { STATE_EXCSAVE2 }, 'm' }
3184 };
3185
3186 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3187   { { OPERAND_art }, 'o' }
3188 };
3189
3190 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3191   { { STATE_PSEXCM }, 'i' },
3192   { { STATE_PSRING }, 'i' },
3193   { { STATE_EPC3 }, 'i' }
3194 };
3195
3196 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3197   { { OPERAND_art }, 'i' }
3198 };
3199
3200 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3201   { { STATE_PSEXCM }, 'i' },
3202   { { STATE_PSRING }, 'i' },
3203   { { STATE_EPC3 }, 'o' }
3204 };
3205
3206 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3207   { { OPERAND_art }, 'm' }
3208 };
3209
3210 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3211   { { STATE_PSEXCM }, 'i' },
3212   { { STATE_PSRING }, 'i' },
3213   { { STATE_EPC3 }, 'm' }
3214 };
3215
3216 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3217   { { OPERAND_art }, 'o' }
3218 };
3219
3220 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3221   { { STATE_PSEXCM }, 'i' },
3222   { { STATE_PSRING }, 'i' },
3223   { { STATE_EXCSAVE3 }, 'i' }
3224 };
3225
3226 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3227   { { OPERAND_art }, 'i' }
3228 };
3229
3230 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3231   { { STATE_PSEXCM }, 'i' },
3232   { { STATE_PSRING }, 'i' },
3233   { { STATE_EXCSAVE3 }, 'o' }
3234 };
3235
3236 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3237   { { OPERAND_art }, 'm' }
3238 };
3239
3240 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3241   { { STATE_PSEXCM }, 'i' },
3242   { { STATE_PSRING }, 'i' },
3243   { { STATE_EXCSAVE3 }, 'm' }
3244 };
3245
3246 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3247   { { OPERAND_art }, 'o' }
3248 };
3249
3250 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3251   { { STATE_PSEXCM }, 'i' },
3252   { { STATE_PSRING }, 'i' },
3253   { { STATE_EPC4 }, 'i' }
3254 };
3255
3256 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3257   { { OPERAND_art }, 'i' }
3258 };
3259
3260 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3261   { { STATE_PSEXCM }, 'i' },
3262   { { STATE_PSRING }, 'i' },
3263   { { STATE_EPC4 }, 'o' }
3264 };
3265
3266 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3267   { { OPERAND_art }, 'm' }
3268 };
3269
3270 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3271   { { STATE_PSEXCM }, 'i' },
3272   { { STATE_PSRING }, 'i' },
3273   { { STATE_EPC4 }, 'm' }
3274 };
3275
3276 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3277   { { OPERAND_art }, 'o' }
3278 };
3279
3280 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3281   { { STATE_PSEXCM }, 'i' },
3282   { { STATE_PSRING }, 'i' },
3283   { { STATE_EXCSAVE4 }, 'i' }
3284 };
3285
3286 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3287   { { OPERAND_art }, 'i' }
3288 };
3289
3290 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3291   { { STATE_PSEXCM }, 'i' },
3292   { { STATE_PSRING }, 'i' },
3293   { { STATE_EXCSAVE4 }, 'o' }
3294 };
3295
3296 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3297   { { OPERAND_art }, 'm' }
3298 };
3299
3300 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3301   { { STATE_PSEXCM }, 'i' },
3302   { { STATE_PSRING }, 'i' },
3303   { { STATE_EXCSAVE4 }, 'm' }
3304 };
3305
3306 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3307   { { OPERAND_art }, 'o' }
3308 };
3309
3310 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3311   { { STATE_PSEXCM }, 'i' },
3312   { { STATE_PSRING }, 'i' },
3313   { { STATE_EPS2 }, 'i' }
3314 };
3315
3316 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3317   { { OPERAND_art }, 'i' }
3318 };
3319
3320 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3321   { { STATE_PSEXCM }, 'i' },
3322   { { STATE_PSRING }, 'i' },
3323   { { STATE_EPS2 }, 'o' }
3324 };
3325
3326 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3327   { { OPERAND_art }, 'm' }
3328 };
3329
3330 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3331   { { STATE_PSEXCM }, 'i' },
3332   { { STATE_PSRING }, 'i' },
3333   { { STATE_EPS2 }, 'm' }
3334 };
3335
3336 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3337   { { OPERAND_art }, 'o' }
3338 };
3339
3340 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3341   { { STATE_PSEXCM }, 'i' },
3342   { { STATE_PSRING }, 'i' },
3343   { { STATE_EPS3 }, 'i' }
3344 };
3345
3346 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3347   { { OPERAND_art }, 'i' }
3348 };
3349
3350 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3351   { { STATE_PSEXCM }, 'i' },
3352   { { STATE_PSRING }, 'i' },
3353   { { STATE_EPS3 }, 'o' }
3354 };
3355
3356 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3357   { { OPERAND_art }, 'm' }
3358 };
3359
3360 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3361   { { STATE_PSEXCM }, 'i' },
3362   { { STATE_PSRING }, 'i' },
3363   { { STATE_EPS3 }, 'm' }
3364 };
3365
3366 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3367   { { OPERAND_art }, 'o' }
3368 };
3369
3370 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3371   { { STATE_PSEXCM }, 'i' },
3372   { { STATE_PSRING }, 'i' },
3373   { { STATE_EPS4 }, 'i' }
3374 };
3375
3376 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3377   { { OPERAND_art }, 'i' }
3378 };
3379
3380 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3381   { { STATE_PSEXCM }, 'i' },
3382   { { STATE_PSRING }, 'i' },
3383   { { STATE_EPS4 }, 'o' }
3384 };
3385
3386 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3387   { { OPERAND_art }, 'm' }
3388 };
3389
3390 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3391   { { STATE_PSEXCM }, 'i' },
3392   { { STATE_PSRING }, 'i' },
3393   { { STATE_EPS4 }, 'm' }
3394 };
3395
3396 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3397   { { OPERAND_art }, 'o' }
3398 };
3399
3400 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3401   { { STATE_PSEXCM }, 'i' },
3402   { { STATE_PSRING }, 'i' },
3403   { { STATE_EXCVADDR }, 'i' }
3404 };
3405
3406 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3407   { { OPERAND_art }, 'i' }
3408 };
3409
3410 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3411   { { STATE_PSEXCM }, 'i' },
3412   { { STATE_PSRING }, 'i' },
3413   { { STATE_EXCVADDR }, 'o' }
3414 };
3415
3416 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3417   { { OPERAND_art }, 'm' }
3418 };
3419
3420 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3421   { { STATE_PSEXCM }, 'i' },
3422   { { STATE_PSRING }, 'i' },
3423   { { STATE_EXCVADDR }, 'm' }
3424 };
3425
3426 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3427   { { OPERAND_art }, 'o' }
3428 };
3429
3430 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3431   { { STATE_PSEXCM }, 'i' },
3432   { { STATE_PSRING }, 'i' },
3433   { { STATE_DEPC }, 'i' }
3434 };
3435
3436 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3437   { { OPERAND_art }, 'i' }
3438 };
3439
3440 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3441   { { STATE_PSEXCM }, 'i' },
3442   { { STATE_PSRING }, 'i' },
3443   { { STATE_DEPC }, 'o' }
3444 };
3445
3446 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3447   { { OPERAND_art }, 'm' }
3448 };
3449
3450 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3451   { { STATE_PSEXCM }, 'i' },
3452   { { STATE_PSRING }, 'i' },
3453   { { STATE_DEPC }, 'm' }
3454 };
3455
3456 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3457   { { OPERAND_art }, 'o' }
3458 };
3459
3460 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3461   { { STATE_PSEXCM }, 'i' },
3462   { { STATE_PSRING }, 'i' },
3463   { { STATE_EXCCAUSE }, 'i' },
3464   { { STATE_XTSYNC }, 'i' }
3465 };
3466
3467 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3468   { { OPERAND_art }, 'i' }
3469 };
3470
3471 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3472   { { STATE_PSEXCM }, 'i' },
3473   { { STATE_PSRING }, 'i' },
3474   { { STATE_EXCCAUSE }, 'o' }
3475 };
3476
3477 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3478   { { OPERAND_art }, 'm' }
3479 };
3480
3481 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3482   { { STATE_PSEXCM }, 'i' },
3483   { { STATE_PSRING }, 'i' },
3484   { { STATE_EXCCAUSE }, 'm' }
3485 };
3486
3487 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3488   { { OPERAND_art }, 'o' }
3489 };
3490
3491 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3492   { { STATE_PSEXCM }, 'i' },
3493   { { STATE_PSRING }, 'i' },
3494   { { STATE_MISC0 }, 'i' }
3495 };
3496
3497 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3498   { { OPERAND_art }, 'i' }
3499 };
3500
3501 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3502   { { STATE_PSEXCM }, 'i' },
3503   { { STATE_PSRING }, 'i' },
3504   { { STATE_MISC0 }, 'o' }
3505 };
3506
3507 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3508   { { OPERAND_art }, 'm' }
3509 };
3510
3511 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3512   { { STATE_PSEXCM }, 'i' },
3513   { { STATE_PSRING }, 'i' },
3514   { { STATE_MISC0 }, 'm' }
3515 };
3516
3517 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3518   { { OPERAND_art }, 'o' }
3519 };
3520
3521 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3522   { { STATE_PSEXCM }, 'i' },
3523   { { STATE_PSRING }, 'i' },
3524   { { STATE_MISC1 }, 'i' }
3525 };
3526
3527 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3528   { { OPERAND_art }, 'i' }
3529 };
3530
3531 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3532   { { STATE_PSEXCM }, 'i' },
3533   { { STATE_PSRING }, 'i' },
3534   { { STATE_MISC1 }, 'o' }
3535 };
3536
3537 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3538   { { OPERAND_art }, 'm' }
3539 };
3540
3541 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3542   { { STATE_PSEXCM }, 'i' },
3543   { { STATE_PSRING }, 'i' },
3544   { { STATE_MISC1 }, 'm' }
3545 };
3546
3547 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3548   { { OPERAND_art }, 'o' }
3549 };
3550
3551 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
3552   { { STATE_PSEXCM }, 'i' },
3553   { { STATE_PSRING }, 'i' }
3554 };
3555
3556 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3557   { { OPERAND_s }, 'i' }
3558 };
3559
3560 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3561   { { STATE_PSWOE }, 'o' },
3562   { { STATE_PSCALLINC }, 'o' },
3563   { { STATE_PSOWB }, 'o' },
3564   { { STATE_PSRING }, 'm' },
3565   { { STATE_PSUM }, 'o' },
3566   { { STATE_PSEXCM }, 'm' },
3567   { { STATE_PSINTLEVEL }, 'o' },
3568   { { STATE_EPC1 }, 'i' },
3569   { { STATE_EPC2 }, 'i' },
3570   { { STATE_EPC3 }, 'i' },
3571   { { STATE_EPC4 }, 'i' },
3572   { { STATE_EPS2 }, 'i' },
3573   { { STATE_EPS3 }, 'i' },
3574   { { STATE_EPS4 }, 'i' },
3575   { { STATE_InOCDMode }, 'm' }
3576 };
3577
3578 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3579   { { OPERAND_s }, 'i' }
3580 };
3581
3582 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3583   { { STATE_PSEXCM }, 'i' },
3584   { { STATE_PSRING }, 'i' },
3585   { { STATE_PSINTLEVEL }, 'o' }
3586 };
3587
3588 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3589   { { OPERAND_art }, 'o' }
3590 };
3591
3592 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3593   { { STATE_PSEXCM }, 'i' },
3594   { { STATE_PSRING }, 'i' },
3595   { { STATE_INTERRUPT }, 'i' }
3596 };
3597
3598 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3599   { { OPERAND_art }, 'i' }
3600 };
3601
3602 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3603   { { STATE_PSEXCM }, 'i' },
3604   { { STATE_PSRING }, 'i' },
3605   { { STATE_XTSYNC }, 'o' },
3606   { { STATE_INTERRUPT }, 'm' }
3607 };
3608
3609 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
3610   { { OPERAND_art }, 'i' }
3611 };
3612
3613 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
3614   { { STATE_PSEXCM }, 'i' },
3615   { { STATE_PSRING }, 'i' },
3616   { { STATE_XTSYNC }, 'o' },
3617   { { STATE_INTERRUPT }, 'm' }
3618 };
3619
3620 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
3621   { { OPERAND_art }, 'o' }
3622 };
3623
3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
3625   { { STATE_PSEXCM }, 'i' },
3626   { { STATE_PSRING }, 'i' },
3627   { { STATE_INTENABLE }, 'i' }
3628 };
3629
3630 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
3631   { { OPERAND_art }, 'i' }
3632 };
3633
3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
3635   { { STATE_PSEXCM }, 'i' },
3636   { { STATE_PSRING }, 'i' },
3637   { { STATE_INTENABLE }, 'o' }
3638 };
3639
3640 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
3641   { { OPERAND_art }, 'm' }
3642 };
3643
3644 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
3645   { { STATE_PSEXCM }, 'i' },
3646   { { STATE_PSRING }, 'i' },
3647   { { STATE_INTENABLE }, 'm' }
3648 };
3649
3650 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
3651   { { OPERAND_imms }, 'i' },
3652   { { OPERAND_immt }, 'i' }
3653 };
3654
3655 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
3656   { { STATE_PSEXCM }, 'i' },
3657   { { STATE_PSINTLEVEL }, 'i' }
3658 };
3659
3660 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
3661   { { OPERAND_imms }, 'i' }
3662 };
3663
3664 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
3665   { { STATE_PSEXCM }, 'i' },
3666   { { STATE_PSINTLEVEL }, 'i' }
3667 };
3668
3669 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
3670   { { OPERAND_art }, 'o' }
3671 };
3672
3673 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
3674   { { STATE_PSEXCM }, 'i' },
3675   { { STATE_PSRING }, 'i' },
3676   { { STATE_DBREAKA0 }, 'i' }
3677 };
3678
3679 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
3680   { { OPERAND_art }, 'i' }
3681 };
3682
3683 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
3684   { { STATE_PSEXCM }, 'i' },
3685   { { STATE_PSRING }, 'i' },
3686   { { STATE_DBREAKA0 }, 'o' },
3687   { { STATE_XTSYNC }, 'o' }
3688 };
3689
3690 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
3691   { { OPERAND_art }, 'm' }
3692 };
3693
3694 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
3695   { { STATE_PSEXCM }, 'i' },
3696   { { STATE_PSRING }, 'i' },
3697   { { STATE_DBREAKA0 }, 'm' },
3698   { { STATE_XTSYNC }, 'o' }
3699 };
3700
3701 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
3702   { { OPERAND_art }, 'o' }
3703 };
3704
3705 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
3706   { { STATE_PSEXCM }, 'i' },
3707   { { STATE_PSRING }, 'i' },
3708   { { STATE_DBREAKC0 }, 'i' }
3709 };
3710
3711 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
3712   { { OPERAND_art }, 'i' }
3713 };
3714
3715 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
3716   { { STATE_PSEXCM }, 'i' },
3717   { { STATE_PSRING }, 'i' },
3718   { { STATE_DBREAKC0 }, 'o' },
3719   { { STATE_XTSYNC }, 'o' }
3720 };
3721
3722 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
3723   { { OPERAND_art }, 'm' }
3724 };
3725
3726 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
3727   { { STATE_PSEXCM }, 'i' },
3728   { { STATE_PSRING }, 'i' },
3729   { { STATE_DBREAKC0 }, 'm' },
3730   { { STATE_XTSYNC }, 'o' }
3731 };
3732
3733 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
3734   { { OPERAND_art }, 'o' }
3735 };
3736
3737 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
3738   { { STATE_PSEXCM }, 'i' },
3739   { { STATE_PSRING }, 'i' },
3740   { { STATE_DBREAKA1 }, 'i' }
3741 };
3742
3743 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
3744   { { OPERAND_art }, 'i' }
3745 };
3746
3747 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
3748   { { STATE_PSEXCM }, 'i' },
3749   { { STATE_PSRING }, 'i' },
3750   { { STATE_DBREAKA1 }, 'o' },
3751   { { STATE_XTSYNC }, 'o' }
3752 };
3753
3754 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
3755   { { OPERAND_art }, 'm' }
3756 };
3757
3758 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
3759   { { STATE_PSEXCM }, 'i' },
3760   { { STATE_PSRING }, 'i' },
3761   { { STATE_DBREAKA1 }, 'm' },
3762   { { STATE_XTSYNC }, 'o' }
3763 };
3764
3765 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
3766   { { OPERAND_art }, 'o' }
3767 };
3768
3769 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
3770   { { STATE_PSEXCM }, 'i' },
3771   { { STATE_PSRING }, 'i' },
3772   { { STATE_DBREAKC1 }, 'i' }
3773 };
3774
3775 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
3776   { { OPERAND_art }, 'i' }
3777 };
3778
3779 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
3780   { { STATE_PSEXCM }, 'i' },
3781   { { STATE_PSRING }, 'i' },
3782   { { STATE_DBREAKC1 }, 'o' },
3783   { { STATE_XTSYNC }, 'o' }
3784 };
3785
3786 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
3787   { { OPERAND_art }, 'm' }
3788 };
3789
3790 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
3791   { { STATE_PSEXCM }, 'i' },
3792   { { STATE_PSRING }, 'i' },
3793   { { STATE_DBREAKC1 }, 'm' },
3794   { { STATE_XTSYNC }, 'o' }
3795 };
3796
3797 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
3798   { { OPERAND_art }, 'o' }
3799 };
3800
3801 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
3802   { { STATE_PSEXCM }, 'i' },
3803   { { STATE_PSRING }, 'i' },
3804   { { STATE_IBREAKA0 }, 'i' }
3805 };
3806
3807 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
3808   { { OPERAND_art }, 'i' }
3809 };
3810
3811 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
3812   { { STATE_PSEXCM }, 'i' },
3813   { { STATE_PSRING }, 'i' },
3814   { { STATE_IBREAKA0 }, 'o' }
3815 };
3816
3817 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
3818   { { OPERAND_art }, 'm' }
3819 };
3820
3821 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
3822   { { STATE_PSEXCM }, 'i' },
3823   { { STATE_PSRING }, 'i' },
3824   { { STATE_IBREAKA0 }, 'm' }
3825 };
3826
3827 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
3828   { { OPERAND_art }, 'o' }
3829 };
3830
3831 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
3832   { { STATE_PSEXCM }, 'i' },
3833   { { STATE_PSRING }, 'i' },
3834   { { STATE_IBREAKA1 }, 'i' }
3835 };
3836
3837 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
3838   { { OPERAND_art }, 'i' }
3839 };
3840
3841 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
3842   { { STATE_PSEXCM }, 'i' },
3843   { { STATE_PSRING }, 'i' },
3844   { { STATE_IBREAKA1 }, 'o' }
3845 };
3846
3847 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
3848   { { OPERAND_art }, 'm' }
3849 };
3850
3851 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
3852   { { STATE_PSEXCM }, 'i' },
3853   { { STATE_PSRING }, 'i' },
3854   { { STATE_IBREAKA1 }, 'm' }
3855 };
3856
3857 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
3858   { { OPERAND_art }, 'o' }
3859 };
3860
3861 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
3862   { { STATE_PSEXCM }, 'i' },
3863   { { STATE_PSRING }, 'i' },
3864   { { STATE_IBREAKENABLE }, 'i' }
3865 };
3866
3867 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
3868   { { OPERAND_art }, 'i' }
3869 };
3870
3871 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
3872   { { STATE_PSEXCM }, 'i' },
3873   { { STATE_PSRING }, 'i' },
3874   { { STATE_IBREAKENABLE }, 'o' }
3875 };
3876
3877 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
3878   { { OPERAND_art }, 'm' }
3879 };
3880
3881 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
3882   { { STATE_PSEXCM }, 'i' },
3883   { { STATE_PSRING }, 'i' },
3884   { { STATE_IBREAKENABLE }, 'm' }
3885 };
3886
3887 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
3888   { { OPERAND_art }, 'o' }
3889 };
3890
3891 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
3892   { { STATE_PSEXCM }, 'i' },
3893   { { STATE_PSRING }, 'i' },
3894   { { STATE_DEBUGCAUSE }, 'i' },
3895   { { STATE_DBNUM }, 'i' }
3896 };
3897
3898 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
3899   { { OPERAND_art }, 'i' }
3900 };
3901
3902 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
3903   { { STATE_PSEXCM }, 'i' },
3904   { { STATE_PSRING }, 'i' },
3905   { { STATE_DEBUGCAUSE }, 'o' },
3906   { { STATE_DBNUM }, 'o' }
3907 };
3908
3909 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
3910   { { OPERAND_art }, 'm' }
3911 };
3912
3913 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
3914   { { STATE_PSEXCM }, 'i' },
3915   { { STATE_PSRING }, 'i' },
3916   { { STATE_DEBUGCAUSE }, 'm' },
3917   { { STATE_DBNUM }, 'm' }
3918 };
3919
3920 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
3921   { { OPERAND_art }, 'o' }
3922 };
3923
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
3925   { { STATE_PSEXCM }, 'i' },
3926   { { STATE_PSRING }, 'i' },
3927   { { STATE_ICOUNT }, 'i' }
3928 };
3929
3930 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
3931   { { OPERAND_art }, 'i' }
3932 };
3933
3934 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
3935   { { STATE_PSEXCM }, 'i' },
3936   { { STATE_PSRING }, 'i' },
3937   { { STATE_XTSYNC }, 'o' },
3938   { { STATE_ICOUNT }, 'o' }
3939 };
3940
3941 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
3942   { { OPERAND_art }, 'm' }
3943 };
3944
3945 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
3946   { { STATE_PSEXCM }, 'i' },
3947   { { STATE_PSRING }, 'i' },
3948   { { STATE_XTSYNC }, 'o' },
3949   { { STATE_ICOUNT }, 'm' }
3950 };
3951
3952 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
3953   { { OPERAND_art }, 'o' }
3954 };
3955
3956 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
3957   { { STATE_PSEXCM }, 'i' },
3958   { { STATE_PSRING }, 'i' },
3959   { { STATE_ICOUNTLEVEL }, 'i' }
3960 };
3961
3962 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
3963   { { OPERAND_art }, 'i' }
3964 };
3965
3966 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
3967   { { STATE_PSEXCM }, 'i' },
3968   { { STATE_PSRING }, 'i' },
3969   { { STATE_ICOUNTLEVEL }, 'o' }
3970 };
3971
3972 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
3973   { { OPERAND_art }, 'm' }
3974 };
3975
3976 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
3977   { { STATE_PSEXCM }, 'i' },
3978   { { STATE_PSRING }, 'i' },
3979   { { STATE_ICOUNTLEVEL }, 'm' }
3980 };
3981
3982 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
3983   { { OPERAND_art }, 'o' }
3984 };
3985
3986 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
3987   { { STATE_PSEXCM }, 'i' },
3988   { { STATE_PSRING }, 'i' },
3989   { { STATE_DDR }, 'i' }
3990 };
3991
3992 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
3993   { { OPERAND_art }, 'i' }
3994 };
3995
3996 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
3997   { { STATE_PSEXCM }, 'i' },
3998   { { STATE_PSRING }, 'i' },
3999   { { STATE_XTSYNC }, 'o' },
4000   { { STATE_DDR }, 'o' }
4001 };
4002
4003 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4004   { { OPERAND_art }, 'm' }
4005 };
4006
4007 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4008   { { STATE_PSEXCM }, 'i' },
4009   { { STATE_PSRING }, 'i' },
4010   { { STATE_XTSYNC }, 'o' },
4011   { { STATE_DDR }, 'm' }
4012 };
4013
4014 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
4015   { { STATE_InOCDMode }, 'm' },
4016   { { STATE_EPC4 }, 'i' },
4017   { { STATE_PSWOE }, 'o' },
4018   { { STATE_PSCALLINC }, 'o' },
4019   { { STATE_PSOWB }, 'o' },
4020   { { STATE_PSRING }, 'o' },
4021   { { STATE_PSUM }, 'o' },
4022   { { STATE_PSEXCM }, 'o' },
4023   { { STATE_PSINTLEVEL }, 'o' },
4024   { { STATE_EPS4 }, 'i' }
4025 };
4026
4027 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
4028   { { STATE_InOCDMode }, 'm' }
4029 };
4030
4031 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
4032   { { OPERAND_art }, 'o' }
4033 };
4034
4035 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
4036   { { STATE_PSEXCM }, 'i' },
4037   { { STATE_PSRING }, 'i' },
4038   { { STATE_CCOUNT }, 'i' }
4039 };
4040
4041 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
4042   { { OPERAND_art }, 'i' }
4043 };
4044
4045 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
4046   { { STATE_PSEXCM }, 'i' },
4047   { { STATE_PSRING }, 'i' },
4048   { { STATE_XTSYNC }, 'o' },
4049   { { STATE_CCOUNT }, 'o' }
4050 };
4051
4052 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
4053   { { OPERAND_art }, 'm' }
4054 };
4055
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
4057   { { STATE_PSEXCM }, 'i' },
4058   { { STATE_PSRING }, 'i' },
4059   { { STATE_XTSYNC }, 'o' },
4060   { { STATE_CCOUNT }, 'm' }
4061 };
4062
4063 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
4064   { { OPERAND_art }, 'o' }
4065 };
4066
4067 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
4068   { { STATE_PSEXCM }, 'i' },
4069   { { STATE_PSRING }, 'i' },
4070   { { STATE_CCOMPARE0 }, 'i' }
4071 };
4072
4073 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
4074   { { OPERAND_art }, 'i' }
4075 };
4076
4077 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
4078   { { STATE_PSEXCM }, 'i' },
4079   { { STATE_PSRING }, 'i' },
4080   { { STATE_CCOMPARE0 }, 'o' },
4081   { { STATE_INTERRUPT }, 'm' }
4082 };
4083
4084 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
4085   { { OPERAND_art }, 'm' }
4086 };
4087
4088 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
4089   { { STATE_PSEXCM }, 'i' },
4090   { { STATE_PSRING }, 'i' },
4091   { { STATE_CCOMPARE0 }, 'm' },
4092   { { STATE_INTERRUPT }, 'm' }
4093 };
4094
4095 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
4096   { { OPERAND_art }, 'o' }
4097 };
4098
4099 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
4100   { { STATE_PSEXCM }, 'i' },
4101   { { STATE_PSRING }, 'i' },
4102   { { STATE_CCOMPARE1 }, 'i' }
4103 };
4104
4105 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
4106   { { OPERAND_art }, 'i' }
4107 };
4108
4109 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
4110   { { STATE_PSEXCM }, 'i' },
4111   { { STATE_PSRING }, 'i' },
4112   { { STATE_CCOMPARE1 }, 'o' },
4113   { { STATE_INTERRUPT }, 'm' }
4114 };
4115
4116 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
4117   { { OPERAND_art }, 'm' }
4118 };
4119
4120 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
4121   { { STATE_PSEXCM }, 'i' },
4122   { { STATE_PSRING }, 'i' },
4123   { { STATE_CCOMPARE1 }, 'm' },
4124   { { STATE_INTERRUPT }, 'm' }
4125 };
4126
4127 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
4128   { { OPERAND_art }, 'o' }
4129 };
4130
4131 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
4132   { { STATE_PSEXCM }, 'i' },
4133   { { STATE_PSRING }, 'i' },
4134   { { STATE_CCOMPARE2 }, 'i' }
4135 };
4136
4137 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4138   { { OPERAND_art }, 'i' }
4139 };
4140
4141 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4142   { { STATE_PSEXCM }, 'i' },
4143   { { STATE_PSRING }, 'i' },
4144   { { STATE_CCOMPARE2 }, 'o' },
4145   { { STATE_INTERRUPT }, 'm' }
4146 };
4147
4148 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4149   { { OPERAND_art }, 'm' }
4150 };
4151
4152 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4153   { { STATE_PSEXCM }, 'i' },
4154   { { STATE_PSRING }, 'i' },
4155   { { STATE_CCOMPARE2 }, 'm' },
4156   { { STATE_INTERRUPT }, 'm' }
4157 };
4158
4159 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
4160   { { OPERAND_ars }, 'i' },
4161   { { OPERAND_uimm8x4 }, 'i' }
4162 };
4163
4164 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
4165   { { OPERAND_ars }, 'i' },
4166   { { OPERAND_uimm8x4 }, 'i' }
4167 };
4168
4169 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
4170   { { STATE_PSEXCM }, 'i' },
4171   { { STATE_PSRING }, 'i' }
4172 };
4173
4174 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
4175   { { OPERAND_art }, 'o' },
4176   { { OPERAND_ars }, 'i' }
4177 };
4178
4179 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
4180   { { STATE_PSEXCM }, 'i' },
4181   { { STATE_PSRING }, 'i' }
4182 };
4183
4184 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
4185   { { OPERAND_art }, 'i' },
4186   { { OPERAND_ars }, 'i' }
4187 };
4188
4189 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
4190   { { STATE_PSEXCM }, 'i' },
4191   { { STATE_PSRING }, 'i' }
4192 };
4193
4194 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
4195   { { OPERAND_ars }, 'i' },
4196   { { OPERAND_uimm8x4 }, 'i' }
4197 };
4198
4199 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
4200   { { OPERAND_ars }, 'i' },
4201   { { OPERAND_uimm4x16 }, 'i' }
4202 };
4203
4204 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
4205   { { STATE_PSEXCM }, 'i' },
4206   { { STATE_PSRING }, 'i' }
4207 };
4208
4209 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
4210   { { OPERAND_ars }, 'i' },
4211   { { OPERAND_uimm8x4 }, 'i' }
4212 };
4213
4214 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
4215   { { STATE_PSEXCM }, 'i' },
4216   { { STATE_PSRING }, 'i' }
4217 };
4218
4219 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
4220   { { OPERAND_ars }, 'i' },
4221   { { OPERAND_uimm8x4 }, 'i' }
4222 };
4223
4224 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
4225   { { OPERAND_art }, 'i' },
4226   { { OPERAND_ars }, 'i' }
4227 };
4228
4229 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
4230   { { STATE_PSEXCM }, 'i' },
4231   { { STATE_PSRING }, 'i' }
4232 };
4233
4234 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
4235   { { OPERAND_art }, 'o' },
4236   { { OPERAND_ars }, 'i' }
4237 };
4238
4239 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
4240   { { STATE_PSEXCM }, 'i' },
4241   { { STATE_PSRING }, 'i' }
4242 };
4243
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
4245   { { OPERAND_art }, 'i' }
4246 };
4247
4248 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
4249   { { STATE_PSEXCM }, 'i' },
4250   { { STATE_PSRING }, 'i' },
4251   { { STATE_PTBASE }, 'o' },
4252   { { STATE_XTSYNC }, 'o' }
4253 };
4254
4255 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
4256   { { OPERAND_art }, 'o' }
4257 };
4258
4259 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
4260   { { STATE_PSEXCM }, 'i' },
4261   { { STATE_PSRING }, 'i' },
4262   { { STATE_PTBASE }, 'i' },
4263   { { STATE_EXCVADDR }, 'i' }
4264 };
4265
4266 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
4267   { { OPERAND_art }, 'm' }
4268 };
4269
4270 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
4271   { { STATE_PSEXCM }, 'i' },
4272   { { STATE_PSRING }, 'i' },
4273   { { STATE_PTBASE }, 'm' },
4274   { { STATE_EXCVADDR }, 'i' },
4275   { { STATE_XTSYNC }, 'o' }
4276 };
4277
4278 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
4279   { { OPERAND_art }, 'o' }
4280 };
4281
4282 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
4283   { { STATE_PSEXCM }, 'i' },
4284   { { STATE_PSRING }, 'i' },
4285   { { STATE_ASID3 }, 'i' },
4286   { { STATE_ASID2 }, 'i' },
4287   { { STATE_ASID1 }, 'i' }
4288 };
4289
4290 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
4291   { { OPERAND_art }, 'i' }
4292 };
4293
4294 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
4295   { { STATE_XTSYNC }, 'o' },
4296   { { STATE_PSEXCM }, 'i' },
4297   { { STATE_PSRING }, 'i' },
4298   { { STATE_ASID3 }, 'o' },
4299   { { STATE_ASID2 }, 'o' },
4300   { { STATE_ASID1 }, 'o' }
4301 };
4302
4303 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
4304   { { OPERAND_art }, 'm' }
4305 };
4306
4307 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
4308   { { STATE_XTSYNC }, 'o' },
4309   { { STATE_PSEXCM }, 'i' },
4310   { { STATE_PSRING }, 'i' },
4311   { { STATE_ASID3 }, 'm' },
4312   { { STATE_ASID2 }, 'm' },
4313   { { STATE_ASID1 }, 'm' }
4314 };
4315
4316 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
4317   { { OPERAND_art }, 'o' }
4318 };
4319
4320 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
4321   { { STATE_PSEXCM }, 'i' },
4322   { { STATE_PSRING }, 'i' },
4323   { { STATE_INSTPGSZID4 }, 'i' }
4324 };
4325
4326 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
4327   { { OPERAND_art }, 'i' }
4328 };
4329
4330 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
4331   { { STATE_XTSYNC }, 'o' },
4332   { { STATE_PSEXCM }, 'i' },
4333   { { STATE_PSRING }, 'i' },
4334   { { STATE_INSTPGSZID4 }, 'o' }
4335 };
4336
4337 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
4338   { { OPERAND_art }, 'm' }
4339 };
4340
4341 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
4342   { { STATE_XTSYNC }, 'o' },
4343   { { STATE_PSEXCM }, 'i' },
4344   { { STATE_PSRING }, 'i' },
4345   { { STATE_INSTPGSZID4 }, 'm' }
4346 };
4347
4348 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
4349   { { OPERAND_art }, 'o' }
4350 };
4351
4352 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
4353   { { STATE_PSEXCM }, 'i' },
4354   { { STATE_PSRING }, 'i' },
4355   { { STATE_DATAPGSZID4 }, 'i' }
4356 };
4357
4358 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
4359   { { OPERAND_art }, 'i' }
4360 };
4361
4362 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
4363   { { STATE_XTSYNC }, 'o' },
4364   { { STATE_PSEXCM }, 'i' },
4365   { { STATE_PSRING }, 'i' },
4366   { { STATE_DATAPGSZID4 }, 'o' }
4367 };
4368
4369 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
4370   { { OPERAND_art }, 'm' }
4371 };
4372
4373 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
4374   { { STATE_XTSYNC }, 'o' },
4375   { { STATE_PSEXCM }, 'i' },
4376   { { STATE_PSRING }, 'i' },
4377   { { STATE_DATAPGSZID4 }, 'm' }
4378 };
4379
4380 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4381   { { OPERAND_ars }, 'i' }
4382 };
4383
4384 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4385   { { STATE_PSEXCM }, 'i' },
4386   { { STATE_PSRING }, 'i' },
4387   { { STATE_XTSYNC }, 'o' }
4388 };
4389
4390 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4391   { { OPERAND_art }, 'o' },
4392   { { OPERAND_ars }, 'i' }
4393 };
4394
4395 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
4396   { { STATE_PSEXCM }, 'i' },
4397   { { STATE_PSRING }, 'i' }
4398 };
4399
4400 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4401   { { OPERAND_art }, 'i' },
4402   { { OPERAND_ars }, 'i' }
4403 };
4404
4405 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4406   { { STATE_PSEXCM }, 'i' },
4407   { { STATE_PSRING }, 'i' },
4408   { { STATE_XTSYNC }, 'o' }
4409 };
4410
4411 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4412   { { OPERAND_ars }, 'i' }
4413 };
4414
4415 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
4416   { { STATE_PSEXCM }, 'i' },
4417   { { STATE_PSRING }, 'i' }
4418 };
4419
4420 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4421   { { OPERAND_art }, 'o' },
4422   { { OPERAND_ars }, 'i' }
4423 };
4424
4425 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
4426   { { STATE_PSEXCM }, 'i' },
4427   { { STATE_PSRING }, 'i' }
4428 };
4429
4430 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4431   { { OPERAND_art }, 'i' },
4432   { { OPERAND_ars }, 'i' }
4433 };
4434
4435 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
4436   { { STATE_PSEXCM }, 'i' },
4437   { { STATE_PSRING }, 'i' }
4438 };
4439
4440 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
4441   { { STATE_PTBASE }, 'i' },
4442   { { STATE_EXCVADDR }, 'i' }
4443 };
4444
4445 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
4446   { { STATE_EXCVADDR }, 'i' }
4447 };
4448
4449 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
4450   { { STATE_EXCVADDR }, 'i' }
4451 };
4452
4453 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4454   { { OPERAND_art }, 'o' },
4455   { { OPERAND_ars }, 'i' }
4456 };
4457
4458 static xtensa_iclass_internal iclasses[] = {
4459   { 0, 0 /* xt_iclass_excw */,
4460     0, 0, 0, 0 },
4461   { 0, 0 /* xt_iclass_rfe */,
4462     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4463   { 0, 0 /* xt_iclass_rfde */,
4464     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4465   { 0, 0 /* xt_iclass_syscall */,
4466     0, 0, 0, 0 },
4467   { 0, 0 /* xt_iclass_simcall */,
4468     0, 0, 0, 0 },
4469   { 2, Iclass_xt_iclass_call12_args,
4470     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
4471   { 2, Iclass_xt_iclass_call8_args,
4472     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
4473   { 2, Iclass_xt_iclass_call4_args,
4474     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
4475   { 2, Iclass_xt_iclass_callx12_args,
4476     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
4477   { 2, Iclass_xt_iclass_callx8_args,
4478     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
4479   { 2, Iclass_xt_iclass_callx4_args,
4480     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
4481   { 3, Iclass_xt_iclass_entry_args,
4482     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
4483   { 2, Iclass_xt_iclass_movsp_args,
4484     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
4485   { 1, Iclass_xt_iclass_rotw_args,
4486     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
4487   { 1, Iclass_xt_iclass_retw_args,
4488     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
4489   { 0, 0 /* xt_iclass_rfwou */,
4490     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
4491   { 3, Iclass_xt_iclass_l32e_args,
4492     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
4493   { 3, Iclass_xt_iclass_s32e_args,
4494     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
4495   { 1, Iclass_xt_iclass_rsr_windowbase_args,
4496     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
4497   { 1, Iclass_xt_iclass_wsr_windowbase_args,
4498     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
4499   { 1, Iclass_xt_iclass_xsr_windowbase_args,
4500     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
4501   { 1, Iclass_xt_iclass_rsr_windowstart_args,
4502     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
4503   { 1, Iclass_xt_iclass_wsr_windowstart_args,
4504     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
4505   { 1, Iclass_xt_iclass_xsr_windowstart_args,
4506     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
4507   { 3, Iclass_xt_iclass_add_n_args,
4508     0, 0, 0, 0 },
4509   { 3, Iclass_xt_iclass_addi_n_args,
4510     0, 0, 0, 0 },
4511   { 2, Iclass_xt_iclass_bz6_args,
4512     0, 0, 0, 0 },
4513   { 0, 0 /* xt_iclass_ill_n */,
4514     0, 0, 0, 0 },
4515   { 3, Iclass_xt_iclass_loadi4_args,
4516     0, 0, 0, 0 },
4517   { 2, Iclass_xt_iclass_mov_n_args,
4518     0, 0, 0, 0 },
4519   { 2, Iclass_xt_iclass_movi_n_args,
4520     0, 0, 0, 0 },
4521   { 0, 0 /* xt_iclass_nopn */,
4522     0, 0, 0, 0 },
4523   { 1, Iclass_xt_iclass_retn_args,
4524     0, 0, 0, 0 },
4525   { 3, Iclass_xt_iclass_storei4_args,
4526     0, 0, 0, 0 },
4527   { 3, Iclass_xt_iclass_addi_args,
4528     0, 0, 0, 0 },
4529   { 3, Iclass_xt_iclass_addmi_args,
4530     0, 0, 0, 0 },
4531   { 3, Iclass_xt_iclass_addsub_args,
4532     0, 0, 0, 0 },
4533   { 3, Iclass_xt_iclass_bit_args,
4534     0, 0, 0, 0 },
4535   { 3, Iclass_xt_iclass_bsi8_args,
4536     0, 0, 0, 0 },
4537   { 3, Iclass_xt_iclass_bsi8b_args,
4538     0, 0, 0, 0 },
4539   { 3, Iclass_xt_iclass_bsi8u_args,
4540     0, 0, 0, 0 },
4541   { 3, Iclass_xt_iclass_bst8_args,
4542     0, 0, 0, 0 },
4543   { 2, Iclass_xt_iclass_bsz12_args,
4544     0, 0, 0, 0 },
4545   { 2, Iclass_xt_iclass_call0_args,
4546     0, 0, 0, 0 },
4547   { 2, Iclass_xt_iclass_callx0_args,
4548     0, 0, 0, 0 },
4549   { 4, Iclass_xt_iclass_exti_args,
4550     0, 0, 0, 0 },
4551   { 0, 0 /* xt_iclass_ill */,
4552     0, 0, 0, 0 },
4553   { 1, Iclass_xt_iclass_jump_args,
4554     0, 0, 0, 0 },
4555   { 1, Iclass_xt_iclass_jumpx_args,
4556     0, 0, 0, 0 },
4557   { 3, Iclass_xt_iclass_l16ui_args,
4558     0, 0, 0, 0 },
4559   { 3, Iclass_xt_iclass_l16si_args,
4560     0, 0, 0, 0 },
4561   { 3, Iclass_xt_iclass_l32i_args,
4562     0, 0, 0, 0 },
4563   { 2, Iclass_xt_iclass_l32r_args,
4564     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
4565   { 3, Iclass_xt_iclass_l8i_args,
4566     0, 0, 0, 0 },
4567   { 2, Iclass_xt_iclass_loop_args,
4568     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
4569   { 2, Iclass_xt_iclass_loopz_args,
4570     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
4571   { 2, Iclass_xt_iclass_movi_args,
4572     0, 0, 0, 0 },
4573   { 3, Iclass_xt_iclass_movz_args,
4574     0, 0, 0, 0 },
4575   { 2, Iclass_xt_iclass_neg_args,
4576     0, 0, 0, 0 },
4577   { 0, 0 /* xt_iclass_nop */,
4578     0, 0, 0, 0 },
4579   { 1, Iclass_xt_iclass_return_args,
4580     0, 0, 0, 0 },
4581   { 3, Iclass_xt_iclass_s16i_args,
4582     0, 0, 0, 0 },
4583   { 3, Iclass_xt_iclass_s32i_args,
4584     0, 0, 0, 0 },
4585   { 3, Iclass_xt_iclass_s8i_args,
4586     0, 0, 0, 0 },
4587   { 1, Iclass_xt_iclass_sar_args,
4588     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
4589   { 1, Iclass_xt_iclass_sari_args,
4590     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
4591   { 2, Iclass_xt_iclass_shifts_args,
4592     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
4593   { 3, Iclass_xt_iclass_shiftst_args,
4594     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
4595   { 2, Iclass_xt_iclass_shiftt_args,
4596     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
4597   { 3, Iclass_xt_iclass_slli_args,
4598     0, 0, 0, 0 },
4599   { 3, Iclass_xt_iclass_srai_args,
4600     0, 0, 0, 0 },
4601   { 3, Iclass_xt_iclass_srli_args,
4602     0, 0, 0, 0 },
4603   { 0, 0 /* xt_iclass_memw */,
4604     0, 0, 0, 0 },
4605   { 0, 0 /* xt_iclass_extw */,
4606     0, 0, 0, 0 },
4607   { 0, 0 /* xt_iclass_isync */,
4608     0, 0, 0, 0 },
4609   { 0, 0 /* xt_iclass_sync */,
4610     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
4611   { 2, Iclass_xt_iclass_rsil_args,
4612     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
4613   { 1, Iclass_xt_iclass_rsr_lend_args,
4614     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
4615   { 1, Iclass_xt_iclass_wsr_lend_args,
4616     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
4617   { 1, Iclass_xt_iclass_xsr_lend_args,
4618     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
4619   { 1, Iclass_xt_iclass_rsr_lcount_args,
4620     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
4621   { 1, Iclass_xt_iclass_wsr_lcount_args,
4622     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
4623   { 1, Iclass_xt_iclass_xsr_lcount_args,
4624     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
4625   { 1, Iclass_xt_iclass_rsr_lbeg_args,
4626     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
4627   { 1, Iclass_xt_iclass_wsr_lbeg_args,
4628     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
4629   { 1, Iclass_xt_iclass_xsr_lbeg_args,
4630     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
4631   { 1, Iclass_xt_iclass_rsr_sar_args,
4632     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
4633   { 1, Iclass_xt_iclass_wsr_sar_args,
4634     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
4635   { 1, Iclass_xt_iclass_xsr_sar_args,
4636     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
4637   { 1, Iclass_xt_iclass_rsr_litbase_args,
4638     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
4639   { 1, Iclass_xt_iclass_wsr_litbase_args,
4640     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
4641   { 1, Iclass_xt_iclass_xsr_litbase_args,
4642     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
4643   { 1, Iclass_xt_iclass_rsr_176_args,
4644     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
4645   { 1, Iclass_xt_iclass_rsr_208_args,
4646     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
4647   { 1, Iclass_xt_iclass_rsr_ps_args,
4648     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
4649   { 1, Iclass_xt_iclass_wsr_ps_args,
4650     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
4651   { 1, Iclass_xt_iclass_xsr_ps_args,
4652     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
4653   { 1, Iclass_xt_iclass_rsr_epc1_args,
4654     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
4655   { 1, Iclass_xt_iclass_wsr_epc1_args,
4656     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
4657   { 1, Iclass_xt_iclass_xsr_epc1_args,
4658     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
4659   { 1, Iclass_xt_iclass_rsr_excsave1_args,
4660     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
4661   { 1, Iclass_xt_iclass_wsr_excsave1_args,
4662     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
4663   { 1, Iclass_xt_iclass_xsr_excsave1_args,
4664     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
4665   { 1, Iclass_xt_iclass_rsr_epc2_args,
4666     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
4667   { 1, Iclass_xt_iclass_wsr_epc2_args,
4668     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
4669   { 1, Iclass_xt_iclass_xsr_epc2_args,
4670     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
4671   { 1, Iclass_xt_iclass_rsr_excsave2_args,
4672     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
4673   { 1, Iclass_xt_iclass_wsr_excsave2_args,
4674     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
4675   { 1, Iclass_xt_iclass_xsr_excsave2_args,
4676     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
4677   { 1, Iclass_xt_iclass_rsr_epc3_args,
4678     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
4679   { 1, Iclass_xt_iclass_wsr_epc3_args,
4680     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
4681   { 1, Iclass_xt_iclass_xsr_epc3_args,
4682     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
4683   { 1, Iclass_xt_iclass_rsr_excsave3_args,
4684     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
4685   { 1, Iclass_xt_iclass_wsr_excsave3_args,
4686     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
4687   { 1, Iclass_xt_iclass_xsr_excsave3_args,
4688     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
4689   { 1, Iclass_xt_iclass_rsr_epc4_args,
4690     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
4691   { 1, Iclass_xt_iclass_wsr_epc4_args,
4692     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
4693   { 1, Iclass_xt_iclass_xsr_epc4_args,
4694     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
4695   { 1, Iclass_xt_iclass_rsr_excsave4_args,
4696     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
4697   { 1, Iclass_xt_iclass_wsr_excsave4_args,
4698     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
4699   { 1, Iclass_xt_iclass_xsr_excsave4_args,
4700     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
4701   { 1, Iclass_xt_iclass_rsr_eps2_args,
4702     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
4703   { 1, Iclass_xt_iclass_wsr_eps2_args,
4704     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
4705   { 1, Iclass_xt_iclass_xsr_eps2_args,
4706     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
4707   { 1, Iclass_xt_iclass_rsr_eps3_args,
4708     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
4709   { 1, Iclass_xt_iclass_wsr_eps3_args,
4710     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
4711   { 1, Iclass_xt_iclass_xsr_eps3_args,
4712     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
4713   { 1, Iclass_xt_iclass_rsr_eps4_args,
4714     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
4715   { 1, Iclass_xt_iclass_wsr_eps4_args,
4716     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
4717   { 1, Iclass_xt_iclass_xsr_eps4_args,
4718     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
4719   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
4720     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
4721   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
4722     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
4723   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
4724     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
4725   { 1, Iclass_xt_iclass_rsr_depc_args,
4726     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
4727   { 1, Iclass_xt_iclass_wsr_depc_args,
4728     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
4729   { 1, Iclass_xt_iclass_xsr_depc_args,
4730     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
4731   { 1, Iclass_xt_iclass_rsr_exccause_args,
4732     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
4733   { 1, Iclass_xt_iclass_wsr_exccause_args,
4734     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
4735   { 1, Iclass_xt_iclass_xsr_exccause_args,
4736     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
4737   { 1, Iclass_xt_iclass_rsr_misc0_args,
4738     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
4739   { 1, Iclass_xt_iclass_wsr_misc0_args,
4740     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
4741   { 1, Iclass_xt_iclass_xsr_misc0_args,
4742     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
4743   { 1, Iclass_xt_iclass_rsr_misc1_args,
4744     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
4745   { 1, Iclass_xt_iclass_wsr_misc1_args,
4746     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
4747   { 1, Iclass_xt_iclass_xsr_misc1_args,
4748     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
4749   { 1, Iclass_xt_iclass_rsr_prid_args,
4750     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
4751   { 1, Iclass_xt_iclass_rfi_args,
4752     15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
4753   { 1, Iclass_xt_iclass_wait_args,
4754     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
4755   { 1, Iclass_xt_iclass_rsr_interrupt_args,
4756     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
4757   { 1, Iclass_xt_iclass_wsr_intset_args,
4758     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
4759   { 1, Iclass_xt_iclass_wsr_intclear_args,
4760     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
4761   { 1, Iclass_xt_iclass_rsr_intenable_args,
4762     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
4763   { 1, Iclass_xt_iclass_wsr_intenable_args,
4764     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
4765   { 1, Iclass_xt_iclass_xsr_intenable_args,
4766     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
4767   { 2, Iclass_xt_iclass_break_args,
4768     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
4769   { 1, Iclass_xt_iclass_break_n_args,
4770     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
4771   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
4772     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
4773   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
4774     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
4775   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
4776     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
4777   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
4778     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
4779   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
4780     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
4781   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
4782     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
4783   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
4784     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
4785   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
4786     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
4787   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
4788     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
4789   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
4790     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
4791   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
4792     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
4793   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
4794     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
4795   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
4796     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
4797   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
4798     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
4799   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
4800     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
4801   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
4802     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
4803   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
4804     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
4805   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
4806     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
4807   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
4808     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
4809   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
4810     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
4811   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
4812     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
4813   { 1, Iclass_xt_iclass_rsr_debugcause_args,
4814     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
4815   { 1, Iclass_xt_iclass_wsr_debugcause_args,
4816     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
4817   { 1, Iclass_xt_iclass_xsr_debugcause_args,
4818     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
4819   { 1, Iclass_xt_iclass_rsr_icount_args,
4820     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
4821   { 1, Iclass_xt_iclass_wsr_icount_args,
4822     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
4823   { 1, Iclass_xt_iclass_xsr_icount_args,
4824     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
4825   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
4826     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
4827   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
4828     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
4829   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
4830     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
4831   { 1, Iclass_xt_iclass_rsr_ddr_args,
4832     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
4833   { 1, Iclass_xt_iclass_wsr_ddr_args,
4834     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
4835   { 1, Iclass_xt_iclass_xsr_ddr_args,
4836     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
4837   { 0, 0 /* xt_iclass_rfdo */,
4838     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
4839   { 0, 0 /* xt_iclass_rfdd */,
4840     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
4841   { 1, Iclass_xt_iclass_rsr_ccount_args,
4842     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
4843   { 1, Iclass_xt_iclass_wsr_ccount_args,
4844     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
4845   { 1, Iclass_xt_iclass_xsr_ccount_args,
4846     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
4847   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
4848     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
4849   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
4850     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
4851   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
4852     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
4853   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
4854     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
4855   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
4856     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
4857   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
4858     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
4859   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
4860     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
4861   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
4862     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
4863   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
4864     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
4865   { 2, Iclass_xt_iclass_icache_args,
4866     0, 0, 0, 0 },
4867   { 2, Iclass_xt_iclass_icache_inv_args,
4868     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
4869   { 2, Iclass_xt_iclass_licx_args,
4870     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
4871   { 2, Iclass_xt_iclass_sicx_args,
4872     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
4873   { 2, Iclass_xt_iclass_dcache_args,
4874     0, 0, 0, 0 },
4875   { 2, Iclass_xt_iclass_dcache_ind_args,
4876     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
4877   { 2, Iclass_xt_iclass_dcache_inv_args,
4878     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
4879   { 2, Iclass_xt_iclass_dpf_args,
4880     0, 0, 0, 0 },
4881   { 2, Iclass_xt_iclass_sdct_args,
4882     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
4883   { 2, Iclass_xt_iclass_ldct_args,
4884     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
4885   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
4886     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
4887   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
4888     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
4889   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
4890     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
4891   { 1, Iclass_xt_iclass_rsr_rasid_args,
4892     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
4893   { 1, Iclass_xt_iclass_wsr_rasid_args,
4894     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
4895   { 1, Iclass_xt_iclass_xsr_rasid_args,
4896     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
4897   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
4898     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
4899   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
4900     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
4901   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
4902     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
4903   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
4904     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
4905   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
4906     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
4907   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
4908     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
4909   { 1, Iclass_xt_iclass_idtlb_args,
4910     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
4911   { 2, Iclass_xt_iclass_rdtlb_args,
4912     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
4913   { 2, Iclass_xt_iclass_wdtlb_args,
4914     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
4915   { 1, Iclass_xt_iclass_iitlb_args,
4916     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
4917   { 2, Iclass_xt_iclass_ritlb_args,
4918     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
4919   { 2, Iclass_xt_iclass_witlb_args,
4920     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
4921   { 0, 0 /* xt_iclass_ldpte */,
4922     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
4923   { 0, 0 /* xt_iclass_hwwitlba */,
4924     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
4925   { 0, 0 /* xt_iclass_hwwdtlba */,
4926     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
4927   { 2, Iclass_xt_iclass_nsa_args,
4928     0, 0, 0, 0 }
4929 };
4930
4931 enum xtensa_iclass_id {
4932   ICLASS_xt_iclass_excw,
4933   ICLASS_xt_iclass_rfe,
4934   ICLASS_xt_iclass_rfde,
4935   ICLASS_xt_iclass_syscall,
4936   ICLASS_xt_iclass_simcall,
4937   ICLASS_xt_iclass_call12,
4938   ICLASS_xt_iclass_call8,
4939   ICLASS_xt_iclass_call4,
4940   ICLASS_xt_iclass_callx12,
4941   ICLASS_xt_iclass_callx8,
4942   ICLASS_xt_iclass_callx4,
4943   ICLASS_xt_iclass_entry,
4944   ICLASS_xt_iclass_movsp,
4945   ICLASS_xt_iclass_rotw,
4946   ICLASS_xt_iclass_retw,
4947   ICLASS_xt_iclass_rfwou,
4948   ICLASS_xt_iclass_l32e,
4949   ICLASS_xt_iclass_s32e,
4950   ICLASS_xt_iclass_rsr_windowbase,
4951   ICLASS_xt_iclass_wsr_windowbase,
4952   ICLASS_xt_iclass_xsr_windowbase,
4953   ICLASS_xt_iclass_rsr_windowstart,
4954   ICLASS_xt_iclass_wsr_windowstart,
4955   ICLASS_xt_iclass_xsr_windowstart,
4956   ICLASS_xt_iclass_add_n,
4957   ICLASS_xt_iclass_addi_n,
4958   ICLASS_xt_iclass_bz6,
4959   ICLASS_xt_iclass_ill_n,
4960   ICLASS_xt_iclass_loadi4,
4961   ICLASS_xt_iclass_mov_n,
4962   ICLASS_xt_iclass_movi_n,
4963   ICLASS_xt_iclass_nopn,
4964   ICLASS_xt_iclass_retn,
4965   ICLASS_xt_iclass_storei4,
4966   ICLASS_xt_iclass_addi,
4967   ICLASS_xt_iclass_addmi,
4968   ICLASS_xt_iclass_addsub,
4969   ICLASS_xt_iclass_bit,
4970   ICLASS_xt_iclass_bsi8,
4971   ICLASS_xt_iclass_bsi8b,
4972   ICLASS_xt_iclass_bsi8u,
4973   ICLASS_xt_iclass_bst8,
4974   ICLASS_xt_iclass_bsz12,
4975   ICLASS_xt_iclass_call0,
4976   ICLASS_xt_iclass_callx0,
4977   ICLASS_xt_iclass_exti,
4978   ICLASS_xt_iclass_ill,
4979   ICLASS_xt_iclass_jump,
4980   ICLASS_xt_iclass_jumpx,
4981   ICLASS_xt_iclass_l16ui,
4982   ICLASS_xt_iclass_l16si,
4983   ICLASS_xt_iclass_l32i,
4984   ICLASS_xt_iclass_l32r,
4985   ICLASS_xt_iclass_l8i,
4986   ICLASS_xt_iclass_loop,
4987   ICLASS_xt_iclass_loopz,
4988   ICLASS_xt_iclass_movi,
4989   ICLASS_xt_iclass_movz,
4990   ICLASS_xt_iclass_neg,
4991   ICLASS_xt_iclass_nop,
4992   ICLASS_xt_iclass_return,
4993   ICLASS_xt_iclass_s16i,
4994   ICLASS_xt_iclass_s32i,
4995   ICLASS_xt_iclass_s8i,
4996   ICLASS_xt_iclass_sar,
4997   ICLASS_xt_iclass_sari,
4998   ICLASS_xt_iclass_shifts,
4999   ICLASS_xt_iclass_shiftst,
5000   ICLASS_xt_iclass_shiftt,
5001   ICLASS_xt_iclass_slli,
5002   ICLASS_xt_iclass_srai,
5003   ICLASS_xt_iclass_srli,
5004   ICLASS_xt_iclass_memw,
5005   ICLASS_xt_iclass_extw,
5006   ICLASS_xt_iclass_isync,
5007   ICLASS_xt_iclass_sync,
5008   ICLASS_xt_iclass_rsil,
5009   ICLASS_xt_iclass_rsr_lend,
5010   ICLASS_xt_iclass_wsr_lend,
5011   ICLASS_xt_iclass_xsr_lend,
5012   ICLASS_xt_iclass_rsr_lcount,
5013   ICLASS_xt_iclass_wsr_lcount,
5014   ICLASS_xt_iclass_xsr_lcount,
5015   ICLASS_xt_iclass_rsr_lbeg,
5016   ICLASS_xt_iclass_wsr_lbeg,
5017   ICLASS_xt_iclass_xsr_lbeg,
5018   ICLASS_xt_iclass_rsr_sar,
5019   ICLASS_xt_iclass_wsr_sar,
5020   ICLASS_xt_iclass_xsr_sar,
5021   ICLASS_xt_iclass_rsr_litbase,
5022   ICLASS_xt_iclass_wsr_litbase,
5023   ICLASS_xt_iclass_xsr_litbase,
5024   ICLASS_xt_iclass_rsr_176,
5025   ICLASS_xt_iclass_rsr_208,
5026   ICLASS_xt_iclass_rsr_ps,
5027   ICLASS_xt_iclass_wsr_ps,
5028   ICLASS_xt_iclass_xsr_ps,
5029   ICLASS_xt_iclass_rsr_epc1,
5030   ICLASS_xt_iclass_wsr_epc1,
5031   ICLASS_xt_iclass_xsr_epc1,
5032   ICLASS_xt_iclass_rsr_excsave1,
5033   ICLASS_xt_iclass_wsr_excsave1,
5034   ICLASS_xt_iclass_xsr_excsave1,
5035   ICLASS_xt_iclass_rsr_epc2,
5036   ICLASS_xt_iclass_wsr_epc2,
5037   ICLASS_xt_iclass_xsr_epc2,
5038   ICLASS_xt_iclass_rsr_excsave2,
5039   ICLASS_xt_iclass_wsr_excsave2,
5040   ICLASS_xt_iclass_xsr_excsave2,
5041   ICLASS_xt_iclass_rsr_epc3,
5042   ICLASS_xt_iclass_wsr_epc3,
5043   ICLASS_xt_iclass_xsr_epc3,
5044   ICLASS_xt_iclass_rsr_excsave3,
5045   ICLASS_xt_iclass_wsr_excsave3,
5046   ICLASS_xt_iclass_xsr_excsave3,
5047   ICLASS_xt_iclass_rsr_epc4,
5048   ICLASS_xt_iclass_wsr_epc4,
5049   ICLASS_xt_iclass_xsr_epc4,
5050   ICLASS_xt_iclass_rsr_excsave4,
5051   ICLASS_xt_iclass_wsr_excsave4,
5052   ICLASS_xt_iclass_xsr_excsave4,
5053   ICLASS_xt_iclass_rsr_eps2,
5054   ICLASS_xt_iclass_wsr_eps2,
5055   ICLASS_xt_iclass_xsr_eps2,
5056   ICLASS_xt_iclass_rsr_eps3,
5057   ICLASS_xt_iclass_wsr_eps3,
5058   ICLASS_xt_iclass_xsr_eps3,
5059   ICLASS_xt_iclass_rsr_eps4,
5060   ICLASS_xt_iclass_wsr_eps4,
5061   ICLASS_xt_iclass_xsr_eps4,
5062   ICLASS_xt_iclass_rsr_excvaddr,
5063   ICLASS_xt_iclass_wsr_excvaddr,
5064   ICLASS_xt_iclass_xsr_excvaddr,
5065   ICLASS_xt_iclass_rsr_depc,
5066   ICLASS_xt_iclass_wsr_depc,
5067   ICLASS_xt_iclass_xsr_depc,
5068   ICLASS_xt_iclass_rsr_exccause,
5069   ICLASS_xt_iclass_wsr_exccause,
5070   ICLASS_xt_iclass_xsr_exccause,
5071   ICLASS_xt_iclass_rsr_misc0,
5072   ICLASS_xt_iclass_wsr_misc0,
5073   ICLASS_xt_iclass_xsr_misc0,
5074   ICLASS_xt_iclass_rsr_misc1,
5075   ICLASS_xt_iclass_wsr_misc1,
5076   ICLASS_xt_iclass_xsr_misc1,
5077   ICLASS_xt_iclass_rsr_prid,
5078   ICLASS_xt_iclass_rfi,
5079   ICLASS_xt_iclass_wait,
5080   ICLASS_xt_iclass_rsr_interrupt,
5081   ICLASS_xt_iclass_wsr_intset,
5082   ICLASS_xt_iclass_wsr_intclear,
5083   ICLASS_xt_iclass_rsr_intenable,
5084   ICLASS_xt_iclass_wsr_intenable,
5085   ICLASS_xt_iclass_xsr_intenable,
5086   ICLASS_xt_iclass_break,
5087   ICLASS_xt_iclass_break_n,
5088   ICLASS_xt_iclass_rsr_dbreaka0,
5089   ICLASS_xt_iclass_wsr_dbreaka0,
5090   ICLASS_xt_iclass_xsr_dbreaka0,
5091   ICLASS_xt_iclass_rsr_dbreakc0,
5092   ICLASS_xt_iclass_wsr_dbreakc0,
5093   ICLASS_xt_iclass_xsr_dbreakc0,
5094   ICLASS_xt_iclass_rsr_dbreaka1,
5095   ICLASS_xt_iclass_wsr_dbreaka1,
5096   ICLASS_xt_iclass_xsr_dbreaka1,
5097   ICLASS_xt_iclass_rsr_dbreakc1,
5098   ICLASS_xt_iclass_wsr_dbreakc1,
5099   ICLASS_xt_iclass_xsr_dbreakc1,
5100   ICLASS_xt_iclass_rsr_ibreaka0,
5101   ICLASS_xt_iclass_wsr_ibreaka0,
5102   ICLASS_xt_iclass_xsr_ibreaka0,
5103   ICLASS_xt_iclass_rsr_ibreaka1,
5104   ICLASS_xt_iclass_wsr_ibreaka1,
5105   ICLASS_xt_iclass_xsr_ibreaka1,
5106   ICLASS_xt_iclass_rsr_ibreakenable,
5107   ICLASS_xt_iclass_wsr_ibreakenable,
5108   ICLASS_xt_iclass_xsr_ibreakenable,
5109   ICLASS_xt_iclass_rsr_debugcause,
5110   ICLASS_xt_iclass_wsr_debugcause,
5111   ICLASS_xt_iclass_xsr_debugcause,
5112   ICLASS_xt_iclass_rsr_icount,
5113   ICLASS_xt_iclass_wsr_icount,
5114   ICLASS_xt_iclass_xsr_icount,
5115   ICLASS_xt_iclass_rsr_icountlevel,
5116   ICLASS_xt_iclass_wsr_icountlevel,
5117   ICLASS_xt_iclass_xsr_icountlevel,
5118   ICLASS_xt_iclass_rsr_ddr,
5119   ICLASS_xt_iclass_wsr_ddr,
5120   ICLASS_xt_iclass_xsr_ddr,
5121   ICLASS_xt_iclass_rfdo,
5122   ICLASS_xt_iclass_rfdd,
5123   ICLASS_xt_iclass_rsr_ccount,
5124   ICLASS_xt_iclass_wsr_ccount,
5125   ICLASS_xt_iclass_xsr_ccount,
5126   ICLASS_xt_iclass_rsr_ccompare0,
5127   ICLASS_xt_iclass_wsr_ccompare0,
5128   ICLASS_xt_iclass_xsr_ccompare0,
5129   ICLASS_xt_iclass_rsr_ccompare1,
5130   ICLASS_xt_iclass_wsr_ccompare1,
5131   ICLASS_xt_iclass_xsr_ccompare1,
5132   ICLASS_xt_iclass_rsr_ccompare2,
5133   ICLASS_xt_iclass_wsr_ccompare2,
5134   ICLASS_xt_iclass_xsr_ccompare2,
5135   ICLASS_xt_iclass_icache,
5136   ICLASS_xt_iclass_icache_inv,
5137   ICLASS_xt_iclass_licx,
5138   ICLASS_xt_iclass_sicx,
5139   ICLASS_xt_iclass_dcache,
5140   ICLASS_xt_iclass_dcache_ind,
5141   ICLASS_xt_iclass_dcache_inv,
5142   ICLASS_xt_iclass_dpf,
5143   ICLASS_xt_iclass_sdct,
5144   ICLASS_xt_iclass_ldct,
5145   ICLASS_xt_iclass_wsr_ptevaddr,
5146   ICLASS_xt_iclass_rsr_ptevaddr,
5147   ICLASS_xt_iclass_xsr_ptevaddr,
5148   ICLASS_xt_iclass_rsr_rasid,
5149   ICLASS_xt_iclass_wsr_rasid,
5150   ICLASS_xt_iclass_xsr_rasid,
5151   ICLASS_xt_iclass_rsr_itlbcfg,
5152   ICLASS_xt_iclass_wsr_itlbcfg,
5153   ICLASS_xt_iclass_xsr_itlbcfg,
5154   ICLASS_xt_iclass_rsr_dtlbcfg,
5155   ICLASS_xt_iclass_wsr_dtlbcfg,
5156   ICLASS_xt_iclass_xsr_dtlbcfg,
5157   ICLASS_xt_iclass_idtlb,
5158   ICLASS_xt_iclass_rdtlb,
5159   ICLASS_xt_iclass_wdtlb,
5160   ICLASS_xt_iclass_iitlb,
5161   ICLASS_xt_iclass_ritlb,
5162   ICLASS_xt_iclass_witlb,
5163   ICLASS_xt_iclass_ldpte,
5164   ICLASS_xt_iclass_hwwitlba,
5165   ICLASS_xt_iclass_hwwdtlba,
5166   ICLASS_xt_iclass_nsa
5167 };
5168
5169 \f
5170 /*  Opcode encodings.  */
5171
5172 static void
5173 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5174 {
5175   slotbuf[0] = 0x80200;
5176 }
5177
5178 static void
5179 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
5180 {
5181   slotbuf[0] = 0x300;
5182 }
5183
5184 static void
5185 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
5186 {
5187   slotbuf[0] = 0x2300;
5188 }
5189
5190 static void
5191 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5192 {
5193   slotbuf[0] = 0x500;
5194 }
5195
5196 static void
5197 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5198 {
5199   slotbuf[0] = 0x1500;
5200 }
5201
5202 static void
5203 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
5204 {
5205   slotbuf[0] = 0x5c0000;
5206 }
5207
5208 static void
5209 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5210 {
5211   slotbuf[0] = 0x580000;
5212 }
5213
5214 static void
5215 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5216 {
5217   slotbuf[0] = 0x540000;
5218 }
5219
5220 static void
5221 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
5222 {
5223   slotbuf[0] = 0xf0000;
5224 }
5225
5226 static void
5227 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5228 {
5229   slotbuf[0] = 0xb0000;
5230 }
5231
5232 static void
5233 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5234 {
5235   slotbuf[0] = 0x70000;
5236 }
5237
5238 static void
5239 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
5240 {
5241   slotbuf[0] = 0x6c0000;
5242 }
5243
5244 static void
5245 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
5246 {
5247   slotbuf[0] = 0x100;
5248 }
5249
5250 static void
5251 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5252 {
5253   slotbuf[0] = 0x804;
5254 }
5255
5256 static void
5257 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5258 {
5259   slotbuf[0] = 0x60000;
5260 }
5261
5262 static void
5263 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5264 {
5265   slotbuf[0] = 0xd10f;
5266 }
5267
5268 static void
5269 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
5270 {
5271   slotbuf[0] = 0x4300;
5272 }
5273
5274 static void
5275 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5276 {
5277   slotbuf[0] = 0x5300;
5278 }
5279
5280 static void
5281 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
5282 {
5283   slotbuf[0] = 0x90;
5284 }
5285
5286 static void
5287 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
5288 {
5289   slotbuf[0] = 0x94;
5290 }
5291
5292 static void
5293 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5294 {
5295   slotbuf[0] = 0x4830;
5296 }
5297
5298 static void
5299 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5300 {
5301   slotbuf[0] = 0x4831;
5302 }
5303
5304 static void
5305 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5306 {
5307   slotbuf[0] = 0x4816;
5308 }
5309
5310 static void
5311 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5312 {
5313   slotbuf[0] = 0x4930;
5314 }
5315
5316 static void
5317 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5318 {
5319   slotbuf[0] = 0x4931;
5320 }
5321
5322 static void
5323 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5324 {
5325   slotbuf[0] = 0x4916;
5326 }
5327
5328 static void
5329 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5330 {
5331   slotbuf[0] = 0xa000;
5332 }
5333
5334 static void
5335 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5336 {
5337   slotbuf[0] = 0xb000;
5338 }
5339
5340 static void
5341 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5342 {
5343   slotbuf[0] = 0xc800;
5344 }
5345
5346 static void
5347 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5348 {
5349   slotbuf[0] = 0xcc00;
5350 }
5351
5352 static void
5353 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5354 {
5355   slotbuf[0] = 0xd60f;
5356 }
5357
5358 static void
5359 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5360 {
5361   slotbuf[0] = 0x8000;
5362 }
5363
5364 static void
5365 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5366 {
5367   slotbuf[0] = 0xd000;
5368 }
5369
5370 static void
5371 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5372 {
5373   slotbuf[0] = 0xc000;
5374 }
5375
5376 static void
5377 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5378 {
5379   slotbuf[0] = 0xd30f;
5380 }
5381
5382 static void
5383 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5384 {
5385   slotbuf[0] = 0xd00f;
5386 }
5387
5388 static void
5389 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5390 {
5391   slotbuf[0] = 0x9000;
5392 }
5393
5394 static void
5395 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5396 {
5397   slotbuf[0] = 0x200c00;
5398 }
5399
5400 static void
5401 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5402 {
5403   slotbuf[0] = 0x200d00;
5404 }
5405
5406 static void
5407 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
5408 {
5409   slotbuf[0] = 0x8;
5410 }
5411
5412 static void
5413 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
5414 {
5415   slotbuf[0] = 0xc;
5416 }
5417
5418 static void
5419 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5420 {
5421   slotbuf[0] = 0x9;
5422 }
5423
5424 static void
5425 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5426 {
5427   slotbuf[0] = 0xa;
5428 }
5429
5430 static void
5431 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5432 {
5433   slotbuf[0] = 0xb;
5434 }
5435
5436 static void
5437 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5438 {
5439   slotbuf[0] = 0xd;
5440 }
5441
5442 static void
5443 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5444 {
5445   slotbuf[0] = 0xe;
5446 }
5447
5448 static void
5449 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5450 {
5451   slotbuf[0] = 0xf;
5452 }
5453
5454 static void
5455 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
5456 {
5457   slotbuf[0] = 0x1;
5458 }
5459
5460 static void
5461 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
5462 {
5463   slotbuf[0] = 0x2;
5464 }
5465
5466 static void
5467 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
5468 {
5469   slotbuf[0] = 0x3;
5470 }
5471
5472 static void
5473 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5474 {
5475   slotbuf[0] = 0x680000;
5476 }
5477
5478 static void
5479 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5480 {
5481   slotbuf[0] = 0x690000;
5482 }
5483
5484 static void
5485 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5486 {
5487   slotbuf[0] = 0x6b0000;
5488 }
5489
5490 static void
5491 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
5492 {
5493   slotbuf[0] = 0x6a0000;
5494 }
5495
5496 static void
5497 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
5498 {
5499   slotbuf[0] = 0x700600;
5500 }
5501
5502 static void
5503 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5504 {
5505   slotbuf[0] = 0x700e00;
5506 }
5507
5508 static void
5509 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5510 {
5511   slotbuf[0] = 0x6f0000;
5512 }
5513
5514 static void
5515 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5516 {
5517   slotbuf[0] = 0x6e0000;
5518 }
5519
5520 static void
5521 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
5522 {
5523   slotbuf[0] = 0x700100;
5524 }
5525
5526 static void
5527 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
5528 {
5529   slotbuf[0] = 0x700900;
5530 }
5531
5532 static void
5533 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
5534 {
5535   slotbuf[0] = 0x700a00;
5536 }
5537
5538 static void
5539 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
5540 {
5541   slotbuf[0] = 0x700200;
5542 }
5543
5544 static void
5545 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5546 {
5547   slotbuf[0] = 0x700b00;
5548 }
5549
5550 static void
5551 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5552 {
5553   slotbuf[0] = 0x700300;
5554 }
5555
5556 static void
5557 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
5558 {
5559   slotbuf[0] = 0x700800;
5560 }
5561
5562 static void
5563 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
5564 {
5565   slotbuf[0] = 0x700000;
5566 }
5567
5568 static void
5569 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
5570 {
5571   slotbuf[0] = 0x700400;
5572 }
5573
5574 static void
5575 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5576 {
5577   slotbuf[0] = 0x700c00;
5578 }
5579
5580 static void
5581 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5582 {
5583   slotbuf[0] = 0x700500;
5584 }
5585
5586 static void
5587 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
5588 {
5589   slotbuf[0] = 0x700d00;
5590 }
5591
5592 static void
5593 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5594 {
5595   slotbuf[0] = 0x640000;
5596 }
5597
5598 static void
5599 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5600 {
5601   slotbuf[0] = 0x650000;
5602 }
5603
5604 static void
5605 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5606 {
5607   slotbuf[0] = 0x670000;
5608 }
5609
5610 static void
5611 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5612 {
5613   slotbuf[0] = 0x660000;
5614 }
5615
5616 static void
5617 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
5618 {
5619   slotbuf[0] = 0x500000;
5620 }
5621
5622 static void
5623 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
5624 {
5625   slotbuf[0] = 0x30000;
5626 }
5627
5628 static void
5629 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5630 {
5631   slotbuf[0] = 0x40;
5632 }
5633
5634 static void
5635 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
5636 {
5637   slotbuf[0] = 0;
5638 }
5639
5640 static void
5641 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
5642 {
5643   slotbuf[0] = 0x600000;
5644 }
5645
5646 static void
5647 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
5648 {
5649   slotbuf[0] = 0xa0000;
5650 }
5651
5652 static void
5653 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5654 {
5655   slotbuf[0] = 0x200100;
5656 }
5657
5658 static void
5659 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
5660 {
5661   slotbuf[0] = 0x200900;
5662 }
5663
5664 static void
5665 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5666 {
5667   slotbuf[0] = 0x200200;
5668 }
5669
5670 static void
5671 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
5672 {
5673   slotbuf[0] = 0x100000;
5674 }
5675
5676 static void
5677 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5678 {
5679   slotbuf[0] = 0x200000;
5680 }
5681
5682 static void
5683 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
5684 {
5685   slotbuf[0] = 0x6d0800;
5686 }
5687
5688 static void
5689 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5690 {
5691   slotbuf[0] = 0x6d0900;
5692 }
5693
5694 static void
5695 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5696 {
5697   slotbuf[0] = 0x6d0a00;
5698 }
5699
5700 static void
5701 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5702 {
5703   slotbuf[0] = 0x200a00;
5704 }
5705
5706 static void
5707 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5708 {
5709   slotbuf[0] = 0x38;
5710 }
5711
5712 static void
5713 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5714 {
5715   slotbuf[0] = 0x39;
5716 }
5717
5718 static void
5719 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
5720 {
5721   slotbuf[0] = 0x3a;
5722 }
5723
5724 static void
5725 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
5726 {
5727   slotbuf[0] = 0x3b;
5728 }
5729
5730 static void
5731 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5732 {
5733   slotbuf[0] = 0x6;
5734 }
5735
5736 static void
5737 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
5738 {
5739   slotbuf[0] = 0x1006;
5740 }
5741
5742 static void
5743 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
5744 {
5745   slotbuf[0] = 0xf0200;
5746 }
5747
5748 static void
5749 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
5750 {
5751   slotbuf[0] = 0x20000;
5752 }
5753
5754 static void
5755 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5756 {
5757   slotbuf[0] = 0x200500;
5758 }
5759
5760 static void
5761 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5762 {
5763   slotbuf[0] = 0x200600;
5764 }
5765
5766 static void
5767 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
5768 {
5769   slotbuf[0] = 0x200400;
5770 }
5771
5772 static void
5773 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5774 {
5775   slotbuf[0] = 0x4;
5776 }
5777
5778 static void
5779 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
5780 {
5781   slotbuf[0] = 0x104;
5782 }
5783
5784 static void
5785 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
5786 {
5787   slotbuf[0] = 0x204;
5788 }
5789
5790 static void
5791 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
5792 {
5793   slotbuf[0] = 0x304;
5794 }
5795
5796 static void
5797 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
5798 {
5799   slotbuf[0] = 0x404;
5800 }
5801
5802 static void
5803 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
5804 {
5805   slotbuf[0] = 0x1a;
5806 }
5807
5808 static void
5809 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
5810 {
5811   slotbuf[0] = 0x18;
5812 }
5813
5814 static void
5815 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
5816 {
5817   slotbuf[0] = 0x19;
5818 }
5819
5820 static void
5821 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
5822 {
5823   slotbuf[0] = 0x1b;
5824 }
5825
5826 static void
5827 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
5828 {
5829   slotbuf[0] = 0x10;
5830 }
5831
5832 static void
5833 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
5834 {
5835   slotbuf[0] = 0x12;
5836 }
5837
5838 static void
5839 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
5840 {
5841   slotbuf[0] = 0x14;
5842 }
5843
5844 static void
5845 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5846 {
5847   slotbuf[0] = 0xc0200;
5848 }
5849
5850 static void
5851 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5852 {
5853   slotbuf[0] = 0xd0200;
5854 }
5855
5856 static void
5857 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5858 {
5859   slotbuf[0] = 0x200;
5860 }
5861
5862 static void
5863 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5864 {
5865   slotbuf[0] = 0x10200;
5866 }
5867
5868 static void
5869 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5870 {
5871   slotbuf[0] = 0x20200;
5872 }
5873
5874 static void
5875 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
5876 {
5877   slotbuf[0] = 0x30200;
5878 }
5879
5880 static void
5881 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
5882 {
5883   slotbuf[0] = 0x600;
5884 }
5885
5886 static void
5887 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5888 {
5889   slotbuf[0] = 0x130;
5890 }
5891
5892 static void
5893 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5894 {
5895   slotbuf[0] = 0x131;
5896 }
5897
5898 static void
5899 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
5900 {
5901   slotbuf[0] = 0x116;
5902 }
5903
5904 static void
5905 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5906 {
5907   slotbuf[0] = 0x230;
5908 }
5909
5910 static void
5911 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5912 {
5913   slotbuf[0] = 0x231;
5914 }
5915
5916 static void
5917 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
5918 {
5919   slotbuf[0] = 0x216;
5920 }
5921
5922 static void
5923 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5924 {
5925   slotbuf[0] = 0x30;
5926 }
5927
5928 static void
5929 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5930 {
5931   slotbuf[0] = 0x31;
5932 }
5933
5934 static void
5935 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
5936 {
5937   slotbuf[0] = 0x16;
5938 }
5939
5940 static void
5941 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5942 {
5943   slotbuf[0] = 0x330;
5944 }
5945
5946 static void
5947 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5948 {
5949   slotbuf[0] = 0x331;
5950 }
5951
5952 static void
5953 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
5954 {
5955   slotbuf[0] = 0x316;
5956 }
5957
5958 static void
5959 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5960 {
5961   slotbuf[0] = 0x530;
5962 }
5963
5964 static void
5965 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5966 {
5967   slotbuf[0] = 0x531;
5968 }
5969
5970 static void
5971 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5972 {
5973   slotbuf[0] = 0x516;
5974 }
5975
5976 static void
5977 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
5978 {
5979   slotbuf[0] = 0xb030;
5980 }
5981
5982 static void
5983 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
5984 {
5985   slotbuf[0] = 0xd030;
5986 }
5987
5988 static void
5989 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
5990 {
5991   slotbuf[0] = 0xe630;
5992 }
5993
5994 static void
5995 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
5996 {
5997   slotbuf[0] = 0xe631;
5998 }
5999
6000 static void
6001 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6002 {
6003   slotbuf[0] = 0xe616;
6004 }
6005
6006 static void
6007 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6008 {
6009   slotbuf[0] = 0xb130;
6010 }
6011
6012 static void
6013 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6014 {
6015   slotbuf[0] = 0xb131;
6016 }
6017
6018 static void
6019 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6020 {
6021   slotbuf[0] = 0xb116;
6022 }
6023
6024 static void
6025 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6026 {
6027   slotbuf[0] = 0xd130;
6028 }
6029
6030 static void
6031 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6032 {
6033   slotbuf[0] = 0xd131;
6034 }
6035
6036 static void
6037 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6038 {
6039   slotbuf[0] = 0xd116;
6040 }
6041
6042 static void
6043 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6044 {
6045   slotbuf[0] = 0xb230;
6046 }
6047
6048 static void
6049 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6050 {
6051   slotbuf[0] = 0xb231;
6052 }
6053
6054 static void
6055 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6056 {
6057   slotbuf[0] = 0xb216;
6058 }
6059
6060 static void
6061 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6062 {
6063   slotbuf[0] = 0xd230;
6064 }
6065
6066 static void
6067 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6068 {
6069   slotbuf[0] = 0xd231;
6070 }
6071
6072 static void
6073 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6074 {
6075   slotbuf[0] = 0xd216;
6076 }
6077
6078 static void
6079 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6080 {
6081   slotbuf[0] = 0xb330;
6082 }
6083
6084 static void
6085 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6086 {
6087   slotbuf[0] = 0xb331;
6088 }
6089
6090 static void
6091 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6092 {
6093   slotbuf[0] = 0xb316;
6094 }
6095
6096 static void
6097 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6098 {
6099   slotbuf[0] = 0xd330;
6100 }
6101
6102 static void
6103 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6104 {
6105   slotbuf[0] = 0xd331;
6106 }
6107
6108 static void
6109 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6110 {
6111   slotbuf[0] = 0xd316;
6112 }
6113
6114 static void
6115 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6116 {
6117   slotbuf[0] = 0xb430;
6118 }
6119
6120 static void
6121 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6122 {
6123   slotbuf[0] = 0xb431;
6124 }
6125
6126 static void
6127 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6128 {
6129   slotbuf[0] = 0xb416;
6130 }
6131
6132 static void
6133 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6134 {
6135   slotbuf[0] = 0xd430;
6136 }
6137
6138 static void
6139 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6140 {
6141   slotbuf[0] = 0xd431;
6142 }
6143
6144 static void
6145 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6146 {
6147   slotbuf[0] = 0xd416;
6148 }
6149
6150 static void
6151 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6152 {
6153   slotbuf[0] = 0xc230;
6154 }
6155
6156 static void
6157 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6158 {
6159   slotbuf[0] = 0xc231;
6160 }
6161
6162 static void
6163 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6164 {
6165   slotbuf[0] = 0xc216;
6166 }
6167
6168 static void
6169 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6170 {
6171   slotbuf[0] = 0xc330;
6172 }
6173
6174 static void
6175 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6176 {
6177   slotbuf[0] = 0xc331;
6178 }
6179
6180 static void
6181 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6182 {
6183   slotbuf[0] = 0xc316;
6184 }
6185
6186 static void
6187 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6188 {
6189   slotbuf[0] = 0xc430;
6190 }
6191
6192 static void
6193 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6194 {
6195   slotbuf[0] = 0xc431;
6196 }
6197
6198 static void
6199 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6200 {
6201   slotbuf[0] = 0xc416;
6202 }
6203
6204 static void
6205 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6206 {
6207   slotbuf[0] = 0xee30;
6208 }
6209
6210 static void
6211 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6212 {
6213   slotbuf[0] = 0xee31;
6214 }
6215
6216 static void
6217 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6218 {
6219   slotbuf[0] = 0xee16;
6220 }
6221
6222 static void
6223 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6224 {
6225   slotbuf[0] = 0xc030;
6226 }
6227
6228 static void
6229 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6230 {
6231   slotbuf[0] = 0xc031;
6232 }
6233
6234 static void
6235 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6236 {
6237   slotbuf[0] = 0xc016;
6238 }
6239
6240 static void
6241 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6242 {
6243   slotbuf[0] = 0xe830;
6244 }
6245
6246 static void
6247 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6248 {
6249   slotbuf[0] = 0xe831;
6250 }
6251
6252 static void
6253 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6254 {
6255   slotbuf[0] = 0xe816;
6256 }
6257
6258 static void
6259 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6260 {
6261   slotbuf[0] = 0xf430;
6262 }
6263
6264 static void
6265 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6266 {
6267   slotbuf[0] = 0xf431;
6268 }
6269
6270 static void
6271 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6272 {
6273   slotbuf[0] = 0xf416;
6274 }
6275
6276 static void
6277 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6278 {
6279   slotbuf[0] = 0xf530;
6280 }
6281
6282 static void
6283 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6284 {
6285   slotbuf[0] = 0xf531;
6286 }
6287
6288 static void
6289 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6290 {
6291   slotbuf[0] = 0xf516;
6292 }
6293
6294 static void
6295 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
6296 {
6297   slotbuf[0] = 0xeb30;
6298 }
6299
6300 static void
6301 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6302 {
6303   slotbuf[0] = 0x10300;
6304 }
6305
6306 static void
6307 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6308 {
6309   slotbuf[0] = 0x700;
6310 }
6311
6312 static void
6313 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6314 {
6315   slotbuf[0] = 0xe230;
6316 }
6317
6318 static void
6319 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
6320 {
6321   slotbuf[0] = 0xe231;
6322 }
6323
6324 static void
6325 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
6326 {
6327   slotbuf[0] = 0xe331;
6328 }
6329
6330 static void
6331 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6332 {
6333   slotbuf[0] = 0xe430;
6334 }
6335
6336 static void
6337 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6338 {
6339   slotbuf[0] = 0xe431;
6340 }
6341
6342 static void
6343 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6344 {
6345   slotbuf[0] = 0xe416;
6346 }
6347
6348 static void
6349 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
6350 {
6351   slotbuf[0] = 0x400;
6352 }
6353
6354 static void
6355 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6356 {
6357   slotbuf[0] = 0xd20f;
6358 }
6359
6360 static void
6361 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6362 {
6363   slotbuf[0] = 0x9030;
6364 }
6365
6366 static void
6367 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6368 {
6369   slotbuf[0] = 0x9031;
6370 }
6371
6372 static void
6373 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6374 {
6375   slotbuf[0] = 0x9016;
6376 }
6377
6378 static void
6379 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6380 {
6381   slotbuf[0] = 0xa030;
6382 }
6383
6384 static void
6385 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6386 {
6387   slotbuf[0] = 0xa031;
6388 }
6389
6390 static void
6391 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6392 {
6393   slotbuf[0] = 0xa016;
6394 }
6395
6396 static void
6397 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6398 {
6399   slotbuf[0] = 0x9130;
6400 }
6401
6402 static void
6403 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6404 {
6405   slotbuf[0] = 0x9131;
6406 }
6407
6408 static void
6409 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6410 {
6411   slotbuf[0] = 0x9116;
6412 }
6413
6414 static void
6415 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6416 {
6417   slotbuf[0] = 0xa130;
6418 }
6419
6420 static void
6421 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6422 {
6423   slotbuf[0] = 0xa131;
6424 }
6425
6426 static void
6427 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6428 {
6429   slotbuf[0] = 0xa116;
6430 }
6431
6432 static void
6433 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6434 {
6435   slotbuf[0] = 0x8030;
6436 }
6437
6438 static void
6439 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6440 {
6441   slotbuf[0] = 0x8031;
6442 }
6443
6444 static void
6445 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6446 {
6447   slotbuf[0] = 0x8016;
6448 }
6449
6450 static void
6451 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6452 {
6453   slotbuf[0] = 0x8130;
6454 }
6455
6456 static void
6457 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6458 {
6459   slotbuf[0] = 0x8131;
6460 }
6461
6462 static void
6463 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6464 {
6465   slotbuf[0] = 0x8116;
6466 }
6467
6468 static void
6469 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6470 {
6471   slotbuf[0] = 0x6030;
6472 }
6473
6474 static void
6475 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6476 {
6477   slotbuf[0] = 0x6031;
6478 }
6479
6480 static void
6481 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6482 {
6483   slotbuf[0] = 0x6016;
6484 }
6485
6486 static void
6487 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6488 {
6489   slotbuf[0] = 0xe930;
6490 }
6491
6492 static void
6493 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6494 {
6495   slotbuf[0] = 0xe931;
6496 }
6497
6498 static void
6499 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6500 {
6501   slotbuf[0] = 0xe916;
6502 }
6503
6504 static void
6505 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6506 {
6507   slotbuf[0] = 0xec30;
6508 }
6509
6510 static void
6511 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6512 {
6513   slotbuf[0] = 0xec31;
6514 }
6515
6516 static void
6517 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6518 {
6519   slotbuf[0] = 0xec16;
6520 }
6521
6522 static void
6523 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
6524 {
6525   slotbuf[0] = 0xed30;
6526 }
6527
6528 static void
6529 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
6530 {
6531   slotbuf[0] = 0xed31;
6532 }
6533
6534 static void
6535 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
6536 {
6537   slotbuf[0] = 0xed16;
6538 }
6539
6540 static void
6541 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6542 {
6543   slotbuf[0] = 0x6830;
6544 }
6545
6546 static void
6547 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6548 {
6549   slotbuf[0] = 0x6831;
6550 }
6551
6552 static void
6553 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6554 {
6555   slotbuf[0] = 0x6816;
6556 }
6557
6558 static void
6559 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6560 {
6561   slotbuf[0] = 0xe1f;
6562 }
6563
6564 static void
6565 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
6566 {
6567   slotbuf[0] = 0x10e1f;
6568 }
6569
6570 static void
6571 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6572 {
6573   slotbuf[0] = 0xea30;
6574 }
6575
6576 static void
6577 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6578 {
6579   slotbuf[0] = 0xea31;
6580 }
6581
6582 static void
6583 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6584 {
6585   slotbuf[0] = 0xea16;
6586 }
6587
6588 static void
6589 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6590 {
6591   slotbuf[0] = 0xf030;
6592 }
6593
6594 static void
6595 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6596 {
6597   slotbuf[0] = 0xf031;
6598 }
6599
6600 static void
6601 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6602 {
6603   slotbuf[0] = 0xf016;
6604 }
6605
6606 static void
6607 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6608 {
6609   slotbuf[0] = 0xf130;
6610 }
6611
6612 static void
6613 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6614 {
6615   slotbuf[0] = 0xf131;
6616 }
6617
6618 static void
6619 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6620 {
6621   slotbuf[0] = 0xf116;
6622 }
6623
6624 static void
6625 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6626 {
6627   slotbuf[0] = 0xf230;
6628 }
6629
6630 static void
6631 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6632 {
6633   slotbuf[0] = 0xf231;
6634 }
6635
6636 static void
6637 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6638 {
6639   slotbuf[0] = 0xf216;
6640 }
6641
6642 static void
6643 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
6644 {
6645   slotbuf[0] = 0x2c0700;
6646 }
6647
6648 static void
6649 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6650 {
6651   slotbuf[0] = 0x2e0700;
6652 }
6653
6654 static void
6655 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
6656 {
6657   slotbuf[0] = 0x2f0700;
6658 }
6659
6660 static void
6661 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
6662 {
6663   slotbuf[0] = 0x1f;
6664 }
6665
6666 static void
6667 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6668 {
6669   slotbuf[0] = 0x21f;
6670 }
6671
6672 static void
6673 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
6674 {
6675   slotbuf[0] = 0x11f;
6676 }
6677
6678 static void
6679 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6680 {
6681   slotbuf[0] = 0x31f;
6682 }
6683
6684 static void
6685 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6686 {
6687   slotbuf[0] = 0x240700;
6688 }
6689
6690 static void
6691 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6692 {
6693   slotbuf[0] = 0x250700;
6694 }
6695
6696 static void
6697 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6698 {
6699   slotbuf[0] = 0x280740;
6700 }
6701
6702 static void
6703 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6704 {
6705   slotbuf[0] = 0x280750;
6706 }
6707
6708 static void
6709 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6710 {
6711   slotbuf[0] = 0x260700;
6712 }
6713
6714 static void
6715 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
6716 {
6717   slotbuf[0] = 0x270700;
6718 }
6719
6720 static void
6721 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6722 {
6723   slotbuf[0] = 0x200700;
6724 }
6725
6726 static void
6727 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6728 {
6729   slotbuf[0] = 0x210700;
6730 }
6731
6732 static void
6733 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
6734 {
6735   slotbuf[0] = 0x220700;
6736 }
6737
6738 static void
6739 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6740 {
6741   slotbuf[0] = 0x230700;
6742 }
6743
6744 static void
6745 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
6746 {
6747   slotbuf[0] = 0x91f;
6748 }
6749
6750 static void
6751 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
6752 {
6753   slotbuf[0] = 0x81f;
6754 }
6755
6756 static void
6757 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6758 {
6759   slotbuf[0] = 0x5331;
6760 }
6761
6762 static void
6763 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6764 {
6765   slotbuf[0] = 0x5330;
6766 }
6767
6768 static void
6769 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6770 {
6771   slotbuf[0] = 0x5316;
6772 }
6773
6774 static void
6775 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
6776 {
6777   slotbuf[0] = 0x5a30;
6778 }
6779
6780 static void
6781 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
6782 {
6783   slotbuf[0] = 0x5a31;
6784 }
6785
6786 static void
6787 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
6788 {
6789   slotbuf[0] = 0x5a16;
6790 }
6791
6792 static void
6793 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6794 {
6795   slotbuf[0] = 0x5b30;
6796 }
6797
6798 static void
6799 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6800 {
6801   slotbuf[0] = 0x5b31;
6802 }
6803
6804 static void
6805 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6806 {
6807   slotbuf[0] = 0x5b16;
6808 }
6809
6810 static void
6811 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6812 {
6813   slotbuf[0] = 0x5c30;
6814 }
6815
6816 static void
6817 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6818 {
6819   slotbuf[0] = 0x5c31;
6820 }
6821
6822 static void
6823 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6824 {
6825   slotbuf[0] = 0x5c16;
6826 }
6827
6828 static void
6829 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6830 {
6831   slotbuf[0] = 0xc05;
6832 }
6833
6834 static void
6835 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6836 {
6837   slotbuf[0] = 0xd05;
6838 }
6839
6840 static void
6841 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6842 {
6843   slotbuf[0] = 0xb05;
6844 }
6845
6846 static void
6847 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6848 {
6849   slotbuf[0] = 0xf05;
6850 }
6851
6852 static void
6853 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6854 {
6855   slotbuf[0] = 0xe05;
6856 }
6857
6858 static void
6859 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6860 {
6861   slotbuf[0] = 0x405;
6862 }
6863
6864 static void
6865 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6866 {
6867   slotbuf[0] = 0x505;
6868 }
6869
6870 static void
6871 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6872 {
6873   slotbuf[0] = 0x305;
6874 }
6875
6876 static void
6877 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6878 {
6879   slotbuf[0] = 0x705;
6880 }
6881
6882 static void
6883 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6884 {
6885   slotbuf[0] = 0x605;
6886 }
6887
6888 static void
6889 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
6890 {
6891   slotbuf[0] = 0xf1f;
6892 }
6893
6894 static void
6895 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
6896 {
6897   slotbuf[0] = 0x105;
6898 }
6899
6900 static void
6901 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
6902 {
6903   slotbuf[0] = 0x905;
6904 }
6905
6906 static void
6907 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
6908 {
6909   slotbuf[0] = 0xe04;
6910 }
6911
6912 static void
6913 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
6914 {
6915   slotbuf[0] = 0xf04;
6916 }
6917
6918 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
6919   Opcode_excw_Slot_inst_encode, 0, 0
6920 };
6921
6922 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
6923   Opcode_rfe_Slot_inst_encode, 0, 0
6924 };
6925
6926 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
6927   Opcode_rfde_Slot_inst_encode, 0, 0
6928 };
6929
6930 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
6931   Opcode_syscall_Slot_inst_encode, 0, 0
6932 };
6933
6934 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
6935   Opcode_simcall_Slot_inst_encode, 0, 0
6936 };
6937
6938 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
6939   Opcode_call12_Slot_inst_encode, 0, 0
6940 };
6941
6942 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
6943   Opcode_call8_Slot_inst_encode, 0, 0
6944 };
6945
6946 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
6947   Opcode_call4_Slot_inst_encode, 0, 0
6948 };
6949
6950 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
6951   Opcode_callx12_Slot_inst_encode, 0, 0
6952 };
6953
6954 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
6955   Opcode_callx8_Slot_inst_encode, 0, 0
6956 };
6957
6958 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
6959   Opcode_callx4_Slot_inst_encode, 0, 0
6960 };
6961
6962 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
6963   Opcode_entry_Slot_inst_encode, 0, 0
6964 };
6965
6966 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
6967   Opcode_movsp_Slot_inst_encode, 0, 0
6968 };
6969
6970 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
6971   Opcode_rotw_Slot_inst_encode, 0, 0
6972 };
6973
6974 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
6975   Opcode_retw_Slot_inst_encode, 0, 0
6976 };
6977
6978 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
6979   0, 0, Opcode_retw_n_Slot_inst16b_encode
6980 };
6981
6982 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
6983   Opcode_rfwo_Slot_inst_encode, 0, 0
6984 };
6985
6986 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
6987   Opcode_rfwu_Slot_inst_encode, 0, 0
6988 };
6989
6990 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
6991   Opcode_l32e_Slot_inst_encode, 0, 0
6992 };
6993
6994 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
6995   Opcode_s32e_Slot_inst_encode, 0, 0
6996 };
6997
6998 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
6999   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
7000 };
7001
7002 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
7003   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
7004 };
7005
7006 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
7007   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
7008 };
7009
7010 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
7011   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
7012 };
7013
7014 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
7015   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
7016 };
7017
7018 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
7019   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
7020 };
7021
7022 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
7023   0, Opcode_add_n_Slot_inst16a_encode, 0
7024 };
7025
7026 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
7027   0, Opcode_addi_n_Slot_inst16a_encode, 0
7028 };
7029
7030 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
7031   0, 0, Opcode_beqz_n_Slot_inst16b_encode
7032 };
7033
7034 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
7035   0, 0, Opcode_bnez_n_Slot_inst16b_encode
7036 };
7037
7038 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
7039   0, 0, Opcode_ill_n_Slot_inst16b_encode
7040 };
7041
7042 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
7043   0, Opcode_l32i_n_Slot_inst16a_encode, 0
7044 };
7045
7046 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
7047   0, 0, Opcode_mov_n_Slot_inst16b_encode
7048 };
7049
7050 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
7051   0, 0, Opcode_movi_n_Slot_inst16b_encode
7052 };
7053
7054 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
7055   0, 0, Opcode_nop_n_Slot_inst16b_encode
7056 };
7057
7058 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
7059   0, 0, Opcode_ret_n_Slot_inst16b_encode
7060 };
7061
7062 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
7063   0, Opcode_s32i_n_Slot_inst16a_encode, 0
7064 };
7065
7066 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
7067   Opcode_addi_Slot_inst_encode, 0, 0
7068 };
7069
7070 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
7071   Opcode_addmi_Slot_inst_encode, 0, 0
7072 };
7073
7074 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
7075   Opcode_add_Slot_inst_encode, 0, 0
7076 };
7077
7078 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
7079   Opcode_sub_Slot_inst_encode, 0, 0
7080 };
7081
7082 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
7083   Opcode_addx2_Slot_inst_encode, 0, 0
7084 };
7085
7086 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
7087   Opcode_addx4_Slot_inst_encode, 0, 0
7088 };
7089
7090 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
7091   Opcode_addx8_Slot_inst_encode, 0, 0
7092 };
7093
7094 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
7095   Opcode_subx2_Slot_inst_encode, 0, 0
7096 };
7097
7098 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
7099   Opcode_subx4_Slot_inst_encode, 0, 0
7100 };
7101
7102 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
7103   Opcode_subx8_Slot_inst_encode, 0, 0
7104 };
7105
7106 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
7107   Opcode_and_Slot_inst_encode, 0, 0
7108 };
7109
7110 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
7111   Opcode_or_Slot_inst_encode, 0, 0
7112 };
7113
7114 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
7115   Opcode_xor_Slot_inst_encode, 0, 0
7116 };
7117
7118 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
7119   Opcode_beqi_Slot_inst_encode, 0, 0
7120 };
7121
7122 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
7123   Opcode_bnei_Slot_inst_encode, 0, 0
7124 };
7125
7126 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
7127   Opcode_bgei_Slot_inst_encode, 0, 0
7128 };
7129
7130 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
7131   Opcode_blti_Slot_inst_encode, 0, 0
7132 };
7133
7134 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
7135   Opcode_bbci_Slot_inst_encode, 0, 0
7136 };
7137
7138 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
7139   Opcode_bbsi_Slot_inst_encode, 0, 0
7140 };
7141
7142 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
7143   Opcode_bgeui_Slot_inst_encode, 0, 0
7144 };
7145
7146 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
7147   Opcode_bltui_Slot_inst_encode, 0, 0
7148 };
7149
7150 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
7151   Opcode_beq_Slot_inst_encode, 0, 0
7152 };
7153
7154 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
7155   Opcode_bne_Slot_inst_encode, 0, 0
7156 };
7157
7158 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
7159   Opcode_bge_Slot_inst_encode, 0, 0
7160 };
7161
7162 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
7163   Opcode_blt_Slot_inst_encode, 0, 0
7164 };
7165
7166 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
7167   Opcode_bgeu_Slot_inst_encode, 0, 0
7168 };
7169
7170 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
7171   Opcode_bltu_Slot_inst_encode, 0, 0
7172 };
7173
7174 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
7175   Opcode_bany_Slot_inst_encode, 0, 0
7176 };
7177
7178 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
7179   Opcode_bnone_Slot_inst_encode, 0, 0
7180 };
7181
7182 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
7183   Opcode_ball_Slot_inst_encode, 0, 0
7184 };
7185
7186 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
7187   Opcode_bnall_Slot_inst_encode, 0, 0
7188 };
7189
7190 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
7191   Opcode_bbc_Slot_inst_encode, 0, 0
7192 };
7193
7194 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
7195   Opcode_bbs_Slot_inst_encode, 0, 0
7196 };
7197
7198 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
7199   Opcode_beqz_Slot_inst_encode, 0, 0
7200 };
7201
7202 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
7203   Opcode_bnez_Slot_inst_encode, 0, 0
7204 };
7205
7206 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
7207   Opcode_bgez_Slot_inst_encode, 0, 0
7208 };
7209
7210 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
7211   Opcode_bltz_Slot_inst_encode, 0, 0
7212 };
7213
7214 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
7215   Opcode_call0_Slot_inst_encode, 0, 0
7216 };
7217
7218 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
7219   Opcode_callx0_Slot_inst_encode, 0, 0
7220 };
7221
7222 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
7223   Opcode_extui_Slot_inst_encode, 0, 0
7224 };
7225
7226 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
7227   Opcode_ill_Slot_inst_encode, 0, 0
7228 };
7229
7230 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
7231   Opcode_j_Slot_inst_encode, 0, 0
7232 };
7233
7234 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
7235   Opcode_jx_Slot_inst_encode, 0, 0
7236 };
7237
7238 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
7239   Opcode_l16ui_Slot_inst_encode, 0, 0
7240 };
7241
7242 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
7243   Opcode_l16si_Slot_inst_encode, 0, 0
7244 };
7245
7246 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
7247   Opcode_l32i_Slot_inst_encode, 0, 0
7248 };
7249
7250 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
7251   Opcode_l32r_Slot_inst_encode, 0, 0
7252 };
7253
7254 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
7255   Opcode_l8ui_Slot_inst_encode, 0, 0
7256 };
7257
7258 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
7259   Opcode_loop_Slot_inst_encode, 0, 0
7260 };
7261
7262 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
7263   Opcode_loopnez_Slot_inst_encode, 0, 0
7264 };
7265
7266 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
7267   Opcode_loopgtz_Slot_inst_encode, 0, 0
7268 };
7269
7270 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
7271   Opcode_movi_Slot_inst_encode, 0, 0
7272 };
7273
7274 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
7275   Opcode_moveqz_Slot_inst_encode, 0, 0
7276 };
7277
7278 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
7279   Opcode_movnez_Slot_inst_encode, 0, 0
7280 };
7281
7282 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
7283   Opcode_movltz_Slot_inst_encode, 0, 0
7284 };
7285
7286 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
7287   Opcode_movgez_Slot_inst_encode, 0, 0
7288 };
7289
7290 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
7291   Opcode_neg_Slot_inst_encode, 0, 0
7292 };
7293
7294 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
7295   Opcode_abs_Slot_inst_encode, 0, 0
7296 };
7297
7298 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
7299   Opcode_nop_Slot_inst_encode, 0, 0
7300 };
7301
7302 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
7303   Opcode_ret_Slot_inst_encode, 0, 0
7304 };
7305
7306 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
7307   Opcode_s16i_Slot_inst_encode, 0, 0
7308 };
7309
7310 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
7311   Opcode_s32i_Slot_inst_encode, 0, 0
7312 };
7313
7314 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
7315   Opcode_s8i_Slot_inst_encode, 0, 0
7316 };
7317
7318 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
7319   Opcode_ssr_Slot_inst_encode, 0, 0
7320 };
7321
7322 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
7323   Opcode_ssl_Slot_inst_encode, 0, 0
7324 };
7325
7326 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
7327   Opcode_ssa8l_Slot_inst_encode, 0, 0
7328 };
7329
7330 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
7331   Opcode_ssa8b_Slot_inst_encode, 0, 0
7332 };
7333
7334 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
7335   Opcode_ssai_Slot_inst_encode, 0, 0
7336 };
7337
7338 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
7339   Opcode_sll_Slot_inst_encode, 0, 0
7340 };
7341
7342 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
7343   Opcode_src_Slot_inst_encode, 0, 0
7344 };
7345
7346 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
7347   Opcode_srl_Slot_inst_encode, 0, 0
7348 };
7349
7350 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
7351   Opcode_sra_Slot_inst_encode, 0, 0
7352 };
7353
7354 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
7355   Opcode_slli_Slot_inst_encode, 0, 0
7356 };
7357
7358 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
7359   Opcode_srai_Slot_inst_encode, 0, 0
7360 };
7361
7362 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
7363   Opcode_srli_Slot_inst_encode, 0, 0
7364 };
7365
7366 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
7367   Opcode_memw_Slot_inst_encode, 0, 0
7368 };
7369
7370 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
7371   Opcode_extw_Slot_inst_encode, 0, 0
7372 };
7373
7374 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
7375   Opcode_isync_Slot_inst_encode, 0, 0
7376 };
7377
7378 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
7379   Opcode_rsync_Slot_inst_encode, 0, 0
7380 };
7381
7382 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
7383   Opcode_esync_Slot_inst_encode, 0, 0
7384 };
7385
7386 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
7387   Opcode_dsync_Slot_inst_encode, 0, 0
7388 };
7389
7390 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
7391   Opcode_rsil_Slot_inst_encode, 0, 0
7392 };
7393
7394 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
7395   Opcode_rsr_lend_Slot_inst_encode, 0, 0
7396 };
7397
7398 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
7399   Opcode_wsr_lend_Slot_inst_encode, 0, 0
7400 };
7401
7402 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
7403   Opcode_xsr_lend_Slot_inst_encode, 0, 0
7404 };
7405
7406 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
7407   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
7408 };
7409
7410 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
7411   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
7412 };
7413
7414 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
7415   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
7416 };
7417
7418 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
7419   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
7420 };
7421
7422 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
7423   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
7424 };
7425
7426 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
7427   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
7428 };
7429
7430 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
7431   Opcode_rsr_sar_Slot_inst_encode, 0, 0
7432 };
7433
7434 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
7435   Opcode_wsr_sar_Slot_inst_encode, 0, 0
7436 };
7437
7438 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
7439   Opcode_xsr_sar_Slot_inst_encode, 0, 0
7440 };
7441
7442 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
7443   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
7444 };
7445
7446 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
7447   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
7448 };
7449
7450 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
7451   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
7452 };
7453
7454 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
7455   Opcode_rsr_176_Slot_inst_encode, 0, 0
7456 };
7457
7458 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
7459   Opcode_rsr_208_Slot_inst_encode, 0, 0
7460 };
7461
7462 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
7463   Opcode_rsr_ps_Slot_inst_encode, 0, 0
7464 };
7465
7466 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
7467   Opcode_wsr_ps_Slot_inst_encode, 0, 0
7468 };
7469
7470 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
7471   Opcode_xsr_ps_Slot_inst_encode, 0, 0
7472 };
7473
7474 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
7475   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
7476 };
7477
7478 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
7479   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
7480 };
7481
7482 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
7483   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
7484 };
7485
7486 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
7487   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
7488 };
7489
7490 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
7491   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
7492 };
7493
7494 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
7495   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
7496 };
7497
7498 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
7499   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
7500 };
7501
7502 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
7503   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
7504 };
7505
7506 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
7507   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
7508 };
7509
7510 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
7511   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
7512 };
7513
7514 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
7515   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
7516 };
7517
7518 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
7519   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
7520 };
7521
7522 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
7523   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
7524 };
7525
7526 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
7527   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
7528 };
7529
7530 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
7531   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
7532 };
7533
7534 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
7535   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
7536 };
7537
7538 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
7539   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
7540 };
7541
7542 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
7543   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
7544 };
7545
7546 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
7547   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
7548 };
7549
7550 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
7551   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
7552 };
7553
7554 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
7555   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
7556 };
7557
7558 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
7559   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
7560 };
7561
7562 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
7563   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
7564 };
7565
7566 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
7567   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
7568 };
7569
7570 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
7571   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
7572 };
7573
7574 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
7575   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
7576 };
7577
7578 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
7579   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
7580 };
7581
7582 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
7583   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
7584 };
7585
7586 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
7587   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
7588 };
7589
7590 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
7591   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
7592 };
7593
7594 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
7595   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
7596 };
7597
7598 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
7599   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
7600 };
7601
7602 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
7603   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
7604 };
7605
7606 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
7607   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
7608 };
7609
7610 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
7611   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
7612 };
7613
7614 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
7615   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
7616 };
7617
7618 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
7619   Opcode_rsr_depc_Slot_inst_encode, 0, 0
7620 };
7621
7622 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
7623   Opcode_wsr_depc_Slot_inst_encode, 0, 0
7624 };
7625
7626 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
7627   Opcode_xsr_depc_Slot_inst_encode, 0, 0
7628 };
7629
7630 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
7631   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
7632 };
7633
7634 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
7635   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
7636 };
7637
7638 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
7639   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
7640 };
7641
7642 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
7643   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
7644 };
7645
7646 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
7647   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
7648 };
7649
7650 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
7651   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
7652 };
7653
7654 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
7655   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
7656 };
7657
7658 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
7659   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
7660 };
7661
7662 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
7663   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
7664 };
7665
7666 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
7667   Opcode_rsr_prid_Slot_inst_encode, 0, 0
7668 };
7669
7670 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
7671   Opcode_rfi_Slot_inst_encode, 0, 0
7672 };
7673
7674 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
7675   Opcode_waiti_Slot_inst_encode, 0, 0
7676 };
7677
7678 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
7679   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
7680 };
7681
7682 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
7683   Opcode_wsr_intset_Slot_inst_encode, 0, 0
7684 };
7685
7686 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
7687   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
7688 };
7689
7690 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
7691   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
7692 };
7693
7694 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
7695   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
7696 };
7697
7698 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
7699   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
7700 };
7701
7702 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
7703   Opcode_break_Slot_inst_encode, 0, 0
7704 };
7705
7706 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
7707   0, 0, Opcode_break_n_Slot_inst16b_encode
7708 };
7709
7710 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
7711   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
7712 };
7713
7714 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
7715   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
7716 };
7717
7718 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
7719   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
7720 };
7721
7722 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
7723   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
7724 };
7725
7726 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
7727   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
7728 };
7729
7730 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
7731   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
7732 };
7733
7734 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
7735   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
7736 };
7737
7738 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
7739   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
7740 };
7741
7742 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
7743   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
7744 };
7745
7746 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
7747   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
7748 };
7749
7750 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
7751   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
7752 };
7753
7754 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
7755   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
7756 };
7757
7758 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
7759   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
7760 };
7761
7762 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
7763   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
7764 };
7765
7766 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
7767   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
7768 };
7769
7770 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
7771   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
7772 };
7773
7774 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
7775   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
7776 };
7777
7778 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
7779   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
7780 };
7781
7782 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
7783   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
7784 };
7785
7786 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
7787   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
7788 };
7789
7790 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
7791   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
7792 };
7793
7794 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
7795   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
7796 };
7797
7798 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
7799   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
7800 };
7801
7802 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
7803   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
7804 };
7805
7806 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
7807   Opcode_rsr_icount_Slot_inst_encode, 0, 0
7808 };
7809
7810 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
7811   Opcode_wsr_icount_Slot_inst_encode, 0, 0
7812 };
7813
7814 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
7815   Opcode_xsr_icount_Slot_inst_encode, 0, 0
7816 };
7817
7818 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
7819   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
7820 };
7821
7822 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
7823   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
7824 };
7825
7826 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
7827   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
7828 };
7829
7830 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
7831   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
7832 };
7833
7834 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
7835   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
7836 };
7837
7838 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
7839   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
7840 };
7841
7842 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
7843   Opcode_rfdo_Slot_inst_encode, 0, 0
7844 };
7845
7846 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
7847   Opcode_rfdd_Slot_inst_encode, 0, 0
7848 };
7849
7850 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
7851   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
7852 };
7853
7854 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
7855   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
7856 };
7857
7858 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
7859   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
7860 };
7861
7862 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
7863   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
7864 };
7865
7866 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
7867   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
7868 };
7869
7870 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
7871   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
7872 };
7873
7874 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
7875   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
7876 };
7877
7878 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
7879   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
7880 };
7881
7882 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
7883   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
7884 };
7885
7886 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
7887   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
7888 };
7889
7890 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
7891   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
7892 };
7893
7894 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
7895   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
7896 };
7897
7898 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
7899   Opcode_ipf_Slot_inst_encode, 0, 0
7900 };
7901
7902 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
7903   Opcode_ihi_Slot_inst_encode, 0, 0
7904 };
7905
7906 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
7907   Opcode_iii_Slot_inst_encode, 0, 0
7908 };
7909
7910 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
7911   Opcode_lict_Slot_inst_encode, 0, 0
7912 };
7913
7914 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
7915   Opcode_licw_Slot_inst_encode, 0, 0
7916 };
7917
7918 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
7919   Opcode_sict_Slot_inst_encode, 0, 0
7920 };
7921
7922 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
7923   Opcode_sicw_Slot_inst_encode, 0, 0
7924 };
7925
7926 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
7927   Opcode_dhwb_Slot_inst_encode, 0, 0
7928 };
7929
7930 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
7931   Opcode_dhwbi_Slot_inst_encode, 0, 0
7932 };
7933
7934 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
7935   Opcode_diwb_Slot_inst_encode, 0, 0
7936 };
7937
7938 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
7939   Opcode_diwbi_Slot_inst_encode, 0, 0
7940 };
7941
7942 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
7943   Opcode_dhi_Slot_inst_encode, 0, 0
7944 };
7945
7946 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
7947   Opcode_dii_Slot_inst_encode, 0, 0
7948 };
7949
7950 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
7951   Opcode_dpfr_Slot_inst_encode, 0, 0
7952 };
7953
7954 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
7955   Opcode_dpfw_Slot_inst_encode, 0, 0
7956 };
7957
7958 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
7959   Opcode_dpfro_Slot_inst_encode, 0, 0
7960 };
7961
7962 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
7963   Opcode_dpfwo_Slot_inst_encode, 0, 0
7964 };
7965
7966 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
7967   Opcode_sdct_Slot_inst_encode, 0, 0
7968 };
7969
7970 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
7971   Opcode_ldct_Slot_inst_encode, 0, 0
7972 };
7973
7974 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
7975   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
7976 };
7977
7978 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
7979   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
7980 };
7981
7982 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
7983   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
7984 };
7985
7986 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
7987   Opcode_rsr_rasid_Slot_inst_encode, 0, 0
7988 };
7989
7990 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
7991   Opcode_wsr_rasid_Slot_inst_encode, 0, 0
7992 };
7993
7994 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
7995   Opcode_xsr_rasid_Slot_inst_encode, 0, 0
7996 };
7997
7998 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
7999   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
8000 };
8001
8002 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
8003   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
8004 };
8005
8006 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
8007   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
8008 };
8009
8010 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
8011   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
8012 };
8013
8014 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
8015   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
8016 };
8017
8018 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
8019   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
8020 };
8021
8022 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
8023   Opcode_idtlb_Slot_inst_encode, 0, 0
8024 };
8025
8026 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
8027   Opcode_pdtlb_Slot_inst_encode, 0, 0
8028 };
8029
8030 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
8031   Opcode_rdtlb0_Slot_inst_encode, 0, 0
8032 };
8033
8034 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
8035   Opcode_rdtlb1_Slot_inst_encode, 0, 0
8036 };
8037
8038 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
8039   Opcode_wdtlb_Slot_inst_encode, 0, 0
8040 };
8041
8042 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
8043   Opcode_iitlb_Slot_inst_encode, 0, 0
8044 };
8045
8046 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
8047   Opcode_pitlb_Slot_inst_encode, 0, 0
8048 };
8049
8050 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
8051   Opcode_ritlb0_Slot_inst_encode, 0, 0
8052 };
8053
8054 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
8055   Opcode_ritlb1_Slot_inst_encode, 0, 0
8056 };
8057
8058 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
8059   Opcode_witlb_Slot_inst_encode, 0, 0
8060 };
8061
8062 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
8063   Opcode_ldpte_Slot_inst_encode, 0, 0
8064 };
8065
8066 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
8067   Opcode_hwwitlba_Slot_inst_encode, 0, 0
8068 };
8069
8070 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
8071   Opcode_hwwdtlba_Slot_inst_encode, 0, 0
8072 };
8073
8074 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
8075   Opcode_nsa_Slot_inst_encode, 0, 0
8076 };
8077
8078 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
8079   Opcode_nsau_Slot_inst_encode, 0, 0
8080 };
8081
8082 \f
8083 /* Opcode table.  */
8084
8085 static xtensa_opcode_internal opcodes[] = {
8086   { "excw", ICLASS_xt_iclass_excw,
8087     0,
8088     Opcode_excw_encode_fns, 0, 0 },
8089   { "rfe", ICLASS_xt_iclass_rfe,
8090     XTENSA_OPCODE_IS_JUMP,
8091     Opcode_rfe_encode_fns, 0, 0 },
8092   { "rfde", ICLASS_xt_iclass_rfde,
8093     XTENSA_OPCODE_IS_JUMP,
8094     Opcode_rfde_encode_fns, 0, 0 },
8095   { "syscall", ICLASS_xt_iclass_syscall,
8096     0,
8097     Opcode_syscall_encode_fns, 0, 0 },
8098   { "simcall", ICLASS_xt_iclass_simcall,
8099     0,
8100     Opcode_simcall_encode_fns, 0, 0 },
8101   { "call12", ICLASS_xt_iclass_call12,
8102     XTENSA_OPCODE_IS_CALL,
8103     Opcode_call12_encode_fns, 0, 0 },
8104   { "call8", ICLASS_xt_iclass_call8,
8105     XTENSA_OPCODE_IS_CALL,
8106     Opcode_call8_encode_fns, 0, 0 },
8107   { "call4", ICLASS_xt_iclass_call4,
8108     XTENSA_OPCODE_IS_CALL,
8109     Opcode_call4_encode_fns, 0, 0 },
8110   { "callx12", ICLASS_xt_iclass_callx12,
8111     XTENSA_OPCODE_IS_CALL,
8112     Opcode_callx12_encode_fns, 0, 0 },
8113   { "callx8", ICLASS_xt_iclass_callx8,
8114     XTENSA_OPCODE_IS_CALL,
8115     Opcode_callx8_encode_fns, 0, 0 },
8116   { "callx4", ICLASS_xt_iclass_callx4,
8117     XTENSA_OPCODE_IS_CALL,
8118     Opcode_callx4_encode_fns, 0, 0 },
8119   { "entry", ICLASS_xt_iclass_entry,
8120     0,
8121     Opcode_entry_encode_fns, 0, 0 },
8122   { "movsp", ICLASS_xt_iclass_movsp,
8123     0,
8124     Opcode_movsp_encode_fns, 0, 0 },
8125   { "rotw", ICLASS_xt_iclass_rotw,
8126     0,
8127     Opcode_rotw_encode_fns, 0, 0 },
8128   { "retw", ICLASS_xt_iclass_retw,
8129     XTENSA_OPCODE_IS_JUMP,
8130     Opcode_retw_encode_fns, 0, 0 },
8131   { "retw.n", ICLASS_xt_iclass_retw,
8132     XTENSA_OPCODE_IS_JUMP,
8133     Opcode_retw_n_encode_fns, 0, 0 },
8134   { "rfwo", ICLASS_xt_iclass_rfwou,
8135     XTENSA_OPCODE_IS_JUMP,
8136     Opcode_rfwo_encode_fns, 0, 0 },
8137   { "rfwu", ICLASS_xt_iclass_rfwou,
8138     XTENSA_OPCODE_IS_JUMP,
8139     Opcode_rfwu_encode_fns, 0, 0 },
8140   { "l32e", ICLASS_xt_iclass_l32e,
8141     0,
8142     Opcode_l32e_encode_fns, 0, 0 },
8143   { "s32e", ICLASS_xt_iclass_s32e,
8144     0,
8145     Opcode_s32e_encode_fns, 0, 0 },
8146   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
8147     0,
8148     Opcode_rsr_windowbase_encode_fns, 0, 0 },
8149   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
8150     0,
8151     Opcode_wsr_windowbase_encode_fns, 0, 0 },
8152   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
8153     0,
8154     Opcode_xsr_windowbase_encode_fns, 0, 0 },
8155   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
8156     0,
8157     Opcode_rsr_windowstart_encode_fns, 0, 0 },
8158   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
8159     0,
8160     Opcode_wsr_windowstart_encode_fns, 0, 0 },
8161   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
8162     0,
8163     Opcode_xsr_windowstart_encode_fns, 0, 0 },
8164   { "add.n", ICLASS_xt_iclass_add_n,
8165     0,
8166     Opcode_add_n_encode_fns, 0, 0 },
8167   { "addi.n", ICLASS_xt_iclass_addi_n,
8168     0,
8169     Opcode_addi_n_encode_fns, 0, 0 },
8170   { "beqz.n", ICLASS_xt_iclass_bz6,
8171     XTENSA_OPCODE_IS_BRANCH,
8172     Opcode_beqz_n_encode_fns, 0, 0 },
8173   { "bnez.n", ICLASS_xt_iclass_bz6,
8174     XTENSA_OPCODE_IS_BRANCH,
8175     Opcode_bnez_n_encode_fns, 0, 0 },
8176   { "ill.n", ICLASS_xt_iclass_ill_n,
8177     0,
8178     Opcode_ill_n_encode_fns, 0, 0 },
8179   { "l32i.n", ICLASS_xt_iclass_loadi4,
8180     0,
8181     Opcode_l32i_n_encode_fns, 0, 0 },
8182   { "mov.n", ICLASS_xt_iclass_mov_n,
8183     0,
8184     Opcode_mov_n_encode_fns, 0, 0 },
8185   { "movi.n", ICLASS_xt_iclass_movi_n,
8186     0,
8187     Opcode_movi_n_encode_fns, 0, 0 },
8188   { "nop.n", ICLASS_xt_iclass_nopn,
8189     0,
8190     Opcode_nop_n_encode_fns, 0, 0 },
8191   { "ret.n", ICLASS_xt_iclass_retn,
8192     XTENSA_OPCODE_IS_JUMP,
8193     Opcode_ret_n_encode_fns, 0, 0 },
8194   { "s32i.n", ICLASS_xt_iclass_storei4,
8195     0,
8196     Opcode_s32i_n_encode_fns, 0, 0 },
8197   { "addi", ICLASS_xt_iclass_addi,
8198     0,
8199     Opcode_addi_encode_fns, 0, 0 },
8200   { "addmi", ICLASS_xt_iclass_addmi,
8201     0,
8202     Opcode_addmi_encode_fns, 0, 0 },
8203   { "add", ICLASS_xt_iclass_addsub,
8204     0,
8205     Opcode_add_encode_fns, 0, 0 },
8206   { "sub", ICLASS_xt_iclass_addsub,
8207     0,
8208     Opcode_sub_encode_fns, 0, 0 },
8209   { "addx2", ICLASS_xt_iclass_addsub,
8210     0,
8211     Opcode_addx2_encode_fns, 0, 0 },
8212   { "addx4", ICLASS_xt_iclass_addsub,
8213     0,
8214     Opcode_addx4_encode_fns, 0, 0 },
8215   { "addx8", ICLASS_xt_iclass_addsub,
8216     0,
8217     Opcode_addx8_encode_fns, 0, 0 },
8218   { "subx2", ICLASS_xt_iclass_addsub,
8219     0,
8220     Opcode_subx2_encode_fns, 0, 0 },
8221   { "subx4", ICLASS_xt_iclass_addsub,
8222     0,
8223     Opcode_subx4_encode_fns, 0, 0 },
8224   { "subx8", ICLASS_xt_iclass_addsub,
8225     0,
8226     Opcode_subx8_encode_fns, 0, 0 },
8227   { "and", ICLASS_xt_iclass_bit,
8228     0,
8229     Opcode_and_encode_fns, 0, 0 },
8230   { "or", ICLASS_xt_iclass_bit,
8231     0,
8232     Opcode_or_encode_fns, 0, 0 },
8233   { "xor", ICLASS_xt_iclass_bit,
8234     0,
8235     Opcode_xor_encode_fns, 0, 0 },
8236   { "beqi", ICLASS_xt_iclass_bsi8,
8237     XTENSA_OPCODE_IS_BRANCH,
8238     Opcode_beqi_encode_fns, 0, 0 },
8239   { "bnei", ICLASS_xt_iclass_bsi8,
8240     XTENSA_OPCODE_IS_BRANCH,
8241     Opcode_bnei_encode_fns, 0, 0 },
8242   { "bgei", ICLASS_xt_iclass_bsi8,
8243     XTENSA_OPCODE_IS_BRANCH,
8244     Opcode_bgei_encode_fns, 0, 0 },
8245   { "blti", ICLASS_xt_iclass_bsi8,
8246     XTENSA_OPCODE_IS_BRANCH,
8247     Opcode_blti_encode_fns, 0, 0 },
8248   { "bbci", ICLASS_xt_iclass_bsi8b,
8249     XTENSA_OPCODE_IS_BRANCH,
8250     Opcode_bbci_encode_fns, 0, 0 },
8251   { "bbsi", ICLASS_xt_iclass_bsi8b,
8252     XTENSA_OPCODE_IS_BRANCH,
8253     Opcode_bbsi_encode_fns, 0, 0 },
8254   { "bgeui", ICLASS_xt_iclass_bsi8u,
8255     XTENSA_OPCODE_IS_BRANCH,
8256     Opcode_bgeui_encode_fns, 0, 0 },
8257   { "bltui", ICLASS_xt_iclass_bsi8u,
8258     XTENSA_OPCODE_IS_BRANCH,
8259     Opcode_bltui_encode_fns, 0, 0 },
8260   { "beq", ICLASS_xt_iclass_bst8,
8261     XTENSA_OPCODE_IS_BRANCH,
8262     Opcode_beq_encode_fns, 0, 0 },
8263   { "bne", ICLASS_xt_iclass_bst8,
8264     XTENSA_OPCODE_IS_BRANCH,
8265     Opcode_bne_encode_fns, 0, 0 },
8266   { "bge", ICLASS_xt_iclass_bst8,
8267     XTENSA_OPCODE_IS_BRANCH,
8268     Opcode_bge_encode_fns, 0, 0 },
8269   { "blt", ICLASS_xt_iclass_bst8,
8270     XTENSA_OPCODE_IS_BRANCH,
8271     Opcode_blt_encode_fns, 0, 0 },
8272   { "bgeu", ICLASS_xt_iclass_bst8,
8273     XTENSA_OPCODE_IS_BRANCH,
8274     Opcode_bgeu_encode_fns, 0, 0 },
8275   { "bltu", ICLASS_xt_iclass_bst8,
8276     XTENSA_OPCODE_IS_BRANCH,
8277     Opcode_bltu_encode_fns, 0, 0 },
8278   { "bany", ICLASS_xt_iclass_bst8,
8279     XTENSA_OPCODE_IS_BRANCH,
8280     Opcode_bany_encode_fns, 0, 0 },
8281   { "bnone", ICLASS_xt_iclass_bst8,
8282     XTENSA_OPCODE_IS_BRANCH,
8283     Opcode_bnone_encode_fns, 0, 0 },
8284   { "ball", ICLASS_xt_iclass_bst8,
8285     XTENSA_OPCODE_IS_BRANCH,
8286     Opcode_ball_encode_fns, 0, 0 },
8287   { "bnall", ICLASS_xt_iclass_bst8,
8288     XTENSA_OPCODE_IS_BRANCH,
8289     Opcode_bnall_encode_fns, 0, 0 },
8290   { "bbc", ICLASS_xt_iclass_bst8,
8291     XTENSA_OPCODE_IS_BRANCH,
8292     Opcode_bbc_encode_fns, 0, 0 },
8293   { "bbs", ICLASS_xt_iclass_bst8,
8294     XTENSA_OPCODE_IS_BRANCH,
8295     Opcode_bbs_encode_fns, 0, 0 },
8296   { "beqz", ICLASS_xt_iclass_bsz12,
8297     XTENSA_OPCODE_IS_BRANCH,
8298     Opcode_beqz_encode_fns, 0, 0 },
8299   { "bnez", ICLASS_xt_iclass_bsz12,
8300     XTENSA_OPCODE_IS_BRANCH,
8301     Opcode_bnez_encode_fns, 0, 0 },
8302   { "bgez", ICLASS_xt_iclass_bsz12,
8303     XTENSA_OPCODE_IS_BRANCH,
8304     Opcode_bgez_encode_fns, 0, 0 },
8305   { "bltz", ICLASS_xt_iclass_bsz12,
8306     XTENSA_OPCODE_IS_BRANCH,
8307     Opcode_bltz_encode_fns, 0, 0 },
8308   { "call0", ICLASS_xt_iclass_call0,
8309     XTENSA_OPCODE_IS_CALL,
8310     Opcode_call0_encode_fns, 0, 0 },
8311   { "callx0", ICLASS_xt_iclass_callx0,
8312     XTENSA_OPCODE_IS_CALL,
8313     Opcode_callx0_encode_fns, 0, 0 },
8314   { "extui", ICLASS_xt_iclass_exti,
8315     0,
8316     Opcode_extui_encode_fns, 0, 0 },
8317   { "ill", ICLASS_xt_iclass_ill,
8318     0,
8319     Opcode_ill_encode_fns, 0, 0 },
8320   { "j", ICLASS_xt_iclass_jump,
8321     XTENSA_OPCODE_IS_JUMP,
8322     Opcode_j_encode_fns, 0, 0 },
8323   { "jx", ICLASS_xt_iclass_jumpx,
8324     XTENSA_OPCODE_IS_JUMP,
8325     Opcode_jx_encode_fns, 0, 0 },
8326   { "l16ui", ICLASS_xt_iclass_l16ui,
8327     0,
8328     Opcode_l16ui_encode_fns, 0, 0 },
8329   { "l16si", ICLASS_xt_iclass_l16si,
8330     0,
8331     Opcode_l16si_encode_fns, 0, 0 },
8332   { "l32i", ICLASS_xt_iclass_l32i,
8333     0,
8334     Opcode_l32i_encode_fns, 0, 0 },
8335   { "l32r", ICLASS_xt_iclass_l32r,
8336     0,
8337     Opcode_l32r_encode_fns, 0, 0 },
8338   { "l8ui", ICLASS_xt_iclass_l8i,
8339     0,
8340     Opcode_l8ui_encode_fns, 0, 0 },
8341   { "loop", ICLASS_xt_iclass_loop,
8342     XTENSA_OPCODE_IS_LOOP,
8343     Opcode_loop_encode_fns, 0, 0 },
8344   { "loopnez", ICLASS_xt_iclass_loopz,
8345     XTENSA_OPCODE_IS_LOOP,
8346     Opcode_loopnez_encode_fns, 0, 0 },
8347   { "loopgtz", ICLASS_xt_iclass_loopz,
8348     XTENSA_OPCODE_IS_LOOP,
8349     Opcode_loopgtz_encode_fns, 0, 0 },
8350   { "movi", ICLASS_xt_iclass_movi,
8351     0,
8352     Opcode_movi_encode_fns, 0, 0 },
8353   { "moveqz", ICLASS_xt_iclass_movz,
8354     0,
8355     Opcode_moveqz_encode_fns, 0, 0 },
8356   { "movnez", ICLASS_xt_iclass_movz,
8357     0,
8358     Opcode_movnez_encode_fns, 0, 0 },
8359   { "movltz", ICLASS_xt_iclass_movz,
8360     0,
8361     Opcode_movltz_encode_fns, 0, 0 },
8362   { "movgez", ICLASS_xt_iclass_movz,
8363     0,
8364     Opcode_movgez_encode_fns, 0, 0 },
8365   { "neg", ICLASS_xt_iclass_neg,
8366     0,
8367     Opcode_neg_encode_fns, 0, 0 },
8368   { "abs", ICLASS_xt_iclass_neg,
8369     0,
8370     Opcode_abs_encode_fns, 0, 0 },
8371   { "nop", ICLASS_xt_iclass_nop,
8372     0,
8373     Opcode_nop_encode_fns, 0, 0 },
8374   { "ret", ICLASS_xt_iclass_return,
8375     XTENSA_OPCODE_IS_JUMP,
8376     Opcode_ret_encode_fns, 0, 0 },
8377   { "s16i", ICLASS_xt_iclass_s16i,
8378     0,
8379     Opcode_s16i_encode_fns, 0, 0 },
8380   { "s32i", ICLASS_xt_iclass_s32i,
8381     0,
8382     Opcode_s32i_encode_fns, 0, 0 },
8383   { "s8i", ICLASS_xt_iclass_s8i,
8384     0,
8385     Opcode_s8i_encode_fns, 0, 0 },
8386   { "ssr", ICLASS_xt_iclass_sar,
8387     0,
8388     Opcode_ssr_encode_fns, 0, 0 },
8389   { "ssl", ICLASS_xt_iclass_sar,
8390     0,
8391     Opcode_ssl_encode_fns, 0, 0 },
8392   { "ssa8l", ICLASS_xt_iclass_sar,
8393     0,
8394     Opcode_ssa8l_encode_fns, 0, 0 },
8395   { "ssa8b", ICLASS_xt_iclass_sar,
8396     0,
8397     Opcode_ssa8b_encode_fns, 0, 0 },
8398   { "ssai", ICLASS_xt_iclass_sari,
8399     0,
8400     Opcode_ssai_encode_fns, 0, 0 },
8401   { "sll", ICLASS_xt_iclass_shifts,
8402     0,
8403     Opcode_sll_encode_fns, 0, 0 },
8404   { "src", ICLASS_xt_iclass_shiftst,
8405     0,
8406     Opcode_src_encode_fns, 0, 0 },
8407   { "srl", ICLASS_xt_iclass_shiftt,
8408     0,
8409     Opcode_srl_encode_fns, 0, 0 },
8410   { "sra", ICLASS_xt_iclass_shiftt,
8411     0,
8412     Opcode_sra_encode_fns, 0, 0 },
8413   { "slli", ICLASS_xt_iclass_slli,
8414     0,
8415     Opcode_slli_encode_fns, 0, 0 },
8416   { "srai", ICLASS_xt_iclass_srai,
8417     0,
8418     Opcode_srai_encode_fns, 0, 0 },
8419   { "srli", ICLASS_xt_iclass_srli,
8420     0,
8421     Opcode_srli_encode_fns, 0, 0 },
8422   { "memw", ICLASS_xt_iclass_memw,
8423     0,
8424     Opcode_memw_encode_fns, 0, 0 },
8425   { "extw", ICLASS_xt_iclass_extw,
8426     0,
8427     Opcode_extw_encode_fns, 0, 0 },
8428   { "isync", ICLASS_xt_iclass_isync,
8429     0,
8430     Opcode_isync_encode_fns, 0, 0 },
8431   { "rsync", ICLASS_xt_iclass_sync,
8432     0,
8433     Opcode_rsync_encode_fns, 0, 0 },
8434   { "esync", ICLASS_xt_iclass_sync,
8435     0,
8436     Opcode_esync_encode_fns, 0, 0 },
8437   { "dsync", ICLASS_xt_iclass_sync,
8438     0,
8439     Opcode_dsync_encode_fns, 0, 0 },
8440   { "rsil", ICLASS_xt_iclass_rsil,
8441     0,
8442     Opcode_rsil_encode_fns, 0, 0 },
8443   { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
8444     0,
8445     Opcode_rsr_lend_encode_fns, 0, 0 },
8446   { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
8447     0,
8448     Opcode_wsr_lend_encode_fns, 0, 0 },
8449   { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
8450     0,
8451     Opcode_xsr_lend_encode_fns, 0, 0 },
8452   { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
8453     0,
8454     Opcode_rsr_lcount_encode_fns, 0, 0 },
8455   { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
8456     0,
8457     Opcode_wsr_lcount_encode_fns, 0, 0 },
8458   { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
8459     0,
8460     Opcode_xsr_lcount_encode_fns, 0, 0 },
8461   { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
8462     0,
8463     Opcode_rsr_lbeg_encode_fns, 0, 0 },
8464   { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
8465     0,
8466     Opcode_wsr_lbeg_encode_fns, 0, 0 },
8467   { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
8468     0,
8469     Opcode_xsr_lbeg_encode_fns, 0, 0 },
8470   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
8471     0,
8472     Opcode_rsr_sar_encode_fns, 0, 0 },
8473   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
8474     0,
8475     Opcode_wsr_sar_encode_fns, 0, 0 },
8476   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
8477     0,
8478     Opcode_xsr_sar_encode_fns, 0, 0 },
8479   { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
8480     0,
8481     Opcode_rsr_litbase_encode_fns, 0, 0 },
8482   { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
8483     0,
8484     Opcode_wsr_litbase_encode_fns, 0, 0 },
8485   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
8486     0,
8487     Opcode_xsr_litbase_encode_fns, 0, 0 },
8488   { "rsr.176", ICLASS_xt_iclass_rsr_176,
8489     0,
8490     Opcode_rsr_176_encode_fns, 0, 0 },
8491   { "rsr.208", ICLASS_xt_iclass_rsr_208,
8492     0,
8493     Opcode_rsr_208_encode_fns, 0, 0 },
8494   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
8495     0,
8496     Opcode_rsr_ps_encode_fns, 0, 0 },
8497   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
8498     0,
8499     Opcode_wsr_ps_encode_fns, 0, 0 },
8500   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
8501     0,
8502     Opcode_xsr_ps_encode_fns, 0, 0 },
8503   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
8504     0,
8505     Opcode_rsr_epc1_encode_fns, 0, 0 },
8506   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
8507     0,
8508     Opcode_wsr_epc1_encode_fns, 0, 0 },
8509   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
8510     0,
8511     Opcode_xsr_epc1_encode_fns, 0, 0 },
8512   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
8513     0,
8514     Opcode_rsr_excsave1_encode_fns, 0, 0 },
8515   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
8516     0,
8517     Opcode_wsr_excsave1_encode_fns, 0, 0 },
8518   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
8519     0,
8520     Opcode_xsr_excsave1_encode_fns, 0, 0 },
8521   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
8522     0,
8523     Opcode_rsr_epc2_encode_fns, 0, 0 },
8524   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
8525     0,
8526     Opcode_wsr_epc2_encode_fns, 0, 0 },
8527   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
8528     0,
8529     Opcode_xsr_epc2_encode_fns, 0, 0 },
8530   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
8531     0,
8532     Opcode_rsr_excsave2_encode_fns, 0, 0 },
8533   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
8534     0,
8535     Opcode_wsr_excsave2_encode_fns, 0, 0 },
8536   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
8537     0,
8538     Opcode_xsr_excsave2_encode_fns, 0, 0 },
8539   { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
8540     0,
8541     Opcode_rsr_epc3_encode_fns, 0, 0 },
8542   { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
8543     0,
8544     Opcode_wsr_epc3_encode_fns, 0, 0 },
8545   { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
8546     0,
8547     Opcode_xsr_epc3_encode_fns, 0, 0 },
8548   { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
8549     0,
8550     Opcode_rsr_excsave3_encode_fns, 0, 0 },
8551   { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
8552     0,
8553     Opcode_wsr_excsave3_encode_fns, 0, 0 },
8554   { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
8555     0,
8556     Opcode_xsr_excsave3_encode_fns, 0, 0 },
8557   { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
8558     0,
8559     Opcode_rsr_epc4_encode_fns, 0, 0 },
8560   { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
8561     0,
8562     Opcode_wsr_epc4_encode_fns, 0, 0 },
8563   { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
8564     0,
8565     Opcode_xsr_epc4_encode_fns, 0, 0 },
8566   { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
8567     0,
8568     Opcode_rsr_excsave4_encode_fns, 0, 0 },
8569   { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
8570     0,
8571     Opcode_wsr_excsave4_encode_fns, 0, 0 },
8572   { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
8573     0,
8574     Opcode_xsr_excsave4_encode_fns, 0, 0 },
8575   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
8576     0,
8577     Opcode_rsr_eps2_encode_fns, 0, 0 },
8578   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
8579     0,
8580     Opcode_wsr_eps2_encode_fns, 0, 0 },
8581   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
8582     0,
8583     Opcode_xsr_eps2_encode_fns, 0, 0 },
8584   { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
8585     0,
8586     Opcode_rsr_eps3_encode_fns, 0, 0 },
8587   { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
8588     0,
8589     Opcode_wsr_eps3_encode_fns, 0, 0 },
8590   { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
8591     0,
8592     Opcode_xsr_eps3_encode_fns, 0, 0 },
8593   { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
8594     0,
8595     Opcode_rsr_eps4_encode_fns, 0, 0 },
8596   { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
8597     0,
8598     Opcode_wsr_eps4_encode_fns, 0, 0 },
8599   { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
8600     0,
8601     Opcode_xsr_eps4_encode_fns, 0, 0 },
8602   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
8603     0,
8604     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
8605   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
8606     0,
8607     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
8608   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
8609     0,
8610     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
8611   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
8612     0,
8613     Opcode_rsr_depc_encode_fns, 0, 0 },
8614   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
8615     0,
8616     Opcode_wsr_depc_encode_fns, 0, 0 },
8617   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
8618     0,
8619     Opcode_xsr_depc_encode_fns, 0, 0 },
8620   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
8621     0,
8622     Opcode_rsr_exccause_encode_fns, 0, 0 },
8623   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
8624     0,
8625     Opcode_wsr_exccause_encode_fns, 0, 0 },
8626   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
8627     0,
8628     Opcode_xsr_exccause_encode_fns, 0, 0 },
8629   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
8630     0,
8631     Opcode_rsr_misc0_encode_fns, 0, 0 },
8632   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
8633     0,
8634     Opcode_wsr_misc0_encode_fns, 0, 0 },
8635   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
8636     0,
8637     Opcode_xsr_misc0_encode_fns, 0, 0 },
8638   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
8639     0,
8640     Opcode_rsr_misc1_encode_fns, 0, 0 },
8641   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
8642     0,
8643     Opcode_wsr_misc1_encode_fns, 0, 0 },
8644   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
8645     0,
8646     Opcode_xsr_misc1_encode_fns, 0, 0 },
8647   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
8648     0,
8649     Opcode_rsr_prid_encode_fns, 0, 0 },
8650   { "rfi", ICLASS_xt_iclass_rfi,
8651     XTENSA_OPCODE_IS_JUMP,
8652     Opcode_rfi_encode_fns, 0, 0 },
8653   { "waiti", ICLASS_xt_iclass_wait,
8654     0,
8655     Opcode_waiti_encode_fns, 0, 0 },
8656   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
8657     0,
8658     Opcode_rsr_interrupt_encode_fns, 0, 0 },
8659   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
8660     0,
8661     Opcode_wsr_intset_encode_fns, 0, 0 },
8662   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
8663     0,
8664     Opcode_wsr_intclear_encode_fns, 0, 0 },
8665   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
8666     0,
8667     Opcode_rsr_intenable_encode_fns, 0, 0 },
8668   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
8669     0,
8670     Opcode_wsr_intenable_encode_fns, 0, 0 },
8671   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
8672     0,
8673     Opcode_xsr_intenable_encode_fns, 0, 0 },
8674   { "break", ICLASS_xt_iclass_break,
8675     0,
8676     Opcode_break_encode_fns, 0, 0 },
8677   { "break.n", ICLASS_xt_iclass_break_n,
8678     0,
8679     Opcode_break_n_encode_fns, 0, 0 },
8680   { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
8681     0,
8682     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
8683   { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
8684     0,
8685     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
8686   { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
8687     0,
8688     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
8689   { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
8690     0,
8691     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
8692   { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
8693     0,
8694     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
8695   { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
8696     0,
8697     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
8698   { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
8699     0,
8700     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
8701   { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
8702     0,
8703     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
8704   { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
8705     0,
8706     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
8707   { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
8708     0,
8709     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
8710   { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
8711     0,
8712     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
8713   { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
8714     0,
8715     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
8716   { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
8717     0,
8718     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
8719   { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
8720     0,
8721     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
8722   { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
8723     0,
8724     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
8725   { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
8726     0,
8727     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
8728   { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
8729     0,
8730     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
8731   { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
8732     0,
8733     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
8734   { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
8735     0,
8736     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
8737   { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
8738     0,
8739     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
8740   { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
8741     0,
8742     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
8743   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
8744     0,
8745     Opcode_rsr_debugcause_encode_fns, 0, 0 },
8746   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
8747     0,
8748     Opcode_wsr_debugcause_encode_fns, 0, 0 },
8749   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
8750     0,
8751     Opcode_xsr_debugcause_encode_fns, 0, 0 },
8752   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
8753     0,
8754     Opcode_rsr_icount_encode_fns, 0, 0 },
8755   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
8756     0,
8757     Opcode_wsr_icount_encode_fns, 0, 0 },
8758   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
8759     0,
8760     Opcode_xsr_icount_encode_fns, 0, 0 },
8761   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
8762     0,
8763     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
8764   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
8765     0,
8766     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
8767   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
8768     0,
8769     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
8770   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
8771     0,
8772     Opcode_rsr_ddr_encode_fns, 0, 0 },
8773   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
8774     0,
8775     Opcode_wsr_ddr_encode_fns, 0, 0 },
8776   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
8777     0,
8778     Opcode_xsr_ddr_encode_fns, 0, 0 },
8779   { "rfdo", ICLASS_xt_iclass_rfdo,
8780     XTENSA_OPCODE_IS_JUMP,
8781     Opcode_rfdo_encode_fns, 0, 0 },
8782   { "rfdd", ICLASS_xt_iclass_rfdd,
8783     XTENSA_OPCODE_IS_JUMP,
8784     Opcode_rfdd_encode_fns, 0, 0 },
8785   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
8786     0,
8787     Opcode_rsr_ccount_encode_fns, 0, 0 },
8788   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
8789     0,
8790     Opcode_wsr_ccount_encode_fns, 0, 0 },
8791   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
8792     0,
8793     Opcode_xsr_ccount_encode_fns, 0, 0 },
8794   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
8795     0,
8796     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
8797   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
8798     0,
8799     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
8800   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
8801     0,
8802     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
8803   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
8804     0,
8805     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
8806   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
8807     0,
8808     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
8809   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
8810     0,
8811     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
8812   { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
8813     0,
8814     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
8815   { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
8816     0,
8817     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
8818   { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
8819     0,
8820     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
8821   { "ipf", ICLASS_xt_iclass_icache,
8822     0,
8823     Opcode_ipf_encode_fns, 0, 0 },
8824   { "ihi", ICLASS_xt_iclass_icache,
8825     0,
8826     Opcode_ihi_encode_fns, 0, 0 },
8827   { "iii", ICLASS_xt_iclass_icache_inv,
8828     0,
8829     Opcode_iii_encode_fns, 0, 0 },
8830   { "lict", ICLASS_xt_iclass_licx,
8831     0,
8832     Opcode_lict_encode_fns, 0, 0 },
8833   { "licw", ICLASS_xt_iclass_licx,
8834     0,
8835     Opcode_licw_encode_fns, 0, 0 },
8836   { "sict", ICLASS_xt_iclass_sicx,
8837     0,
8838     Opcode_sict_encode_fns, 0, 0 },
8839   { "sicw", ICLASS_xt_iclass_sicx,
8840     0,
8841     Opcode_sicw_encode_fns, 0, 0 },
8842   { "dhwb", ICLASS_xt_iclass_dcache,
8843     0,
8844     Opcode_dhwb_encode_fns, 0, 0 },
8845   { "dhwbi", ICLASS_xt_iclass_dcache,
8846     0,
8847     Opcode_dhwbi_encode_fns, 0, 0 },
8848   { "diwb", ICLASS_xt_iclass_dcache_ind,
8849     0,
8850     Opcode_diwb_encode_fns, 0, 0 },
8851   { "diwbi", ICLASS_xt_iclass_dcache_ind,
8852     0,
8853     Opcode_diwbi_encode_fns, 0, 0 },
8854   { "dhi", ICLASS_xt_iclass_dcache_inv,
8855     0,
8856     Opcode_dhi_encode_fns, 0, 0 },
8857   { "dii", ICLASS_xt_iclass_dcache_inv,
8858     0,
8859     Opcode_dii_encode_fns, 0, 0 },
8860   { "dpfr", ICLASS_xt_iclass_dpf,
8861     0,
8862     Opcode_dpfr_encode_fns, 0, 0 },
8863   { "dpfw", ICLASS_xt_iclass_dpf,
8864     0,
8865     Opcode_dpfw_encode_fns, 0, 0 },
8866   { "dpfro", ICLASS_xt_iclass_dpf,
8867     0,
8868     Opcode_dpfro_encode_fns, 0, 0 },
8869   { "dpfwo", ICLASS_xt_iclass_dpf,
8870     0,
8871     Opcode_dpfwo_encode_fns, 0, 0 },
8872   { "sdct", ICLASS_xt_iclass_sdct,
8873     0,
8874     Opcode_sdct_encode_fns, 0, 0 },
8875   { "ldct", ICLASS_xt_iclass_ldct,
8876     0,
8877     Opcode_ldct_encode_fns, 0, 0 },
8878   { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
8879     0,
8880     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
8881   { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
8882     0,
8883     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
8884   { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
8885     0,
8886     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
8887   { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
8888     0,
8889     Opcode_rsr_rasid_encode_fns, 0, 0 },
8890   { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
8891     0,
8892     Opcode_wsr_rasid_encode_fns, 0, 0 },
8893   { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
8894     0,
8895     Opcode_xsr_rasid_encode_fns, 0, 0 },
8896   { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
8897     0,
8898     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
8899   { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
8900     0,
8901     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
8902   { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
8903     0,
8904     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
8905   { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
8906     0,
8907     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
8908   { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
8909     0,
8910     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
8911   { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
8912     0,
8913     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
8914   { "idtlb", ICLASS_xt_iclass_idtlb,
8915     0,
8916     Opcode_idtlb_encode_fns, 0, 0 },
8917   { "pdtlb", ICLASS_xt_iclass_rdtlb,
8918     0,
8919     Opcode_pdtlb_encode_fns, 0, 0 },
8920   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
8921     0,
8922     Opcode_rdtlb0_encode_fns, 0, 0 },
8923   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
8924     0,
8925     Opcode_rdtlb1_encode_fns, 0, 0 },
8926   { "wdtlb", ICLASS_xt_iclass_wdtlb,
8927     0,
8928     Opcode_wdtlb_encode_fns, 0, 0 },
8929   { "iitlb", ICLASS_xt_iclass_iitlb,
8930     0,
8931     Opcode_iitlb_encode_fns, 0, 0 },
8932   { "pitlb", ICLASS_xt_iclass_ritlb,
8933     0,
8934     Opcode_pitlb_encode_fns, 0, 0 },
8935   { "ritlb0", ICLASS_xt_iclass_ritlb,
8936     0,
8937     Opcode_ritlb0_encode_fns, 0, 0 },
8938   { "ritlb1", ICLASS_xt_iclass_ritlb,
8939     0,
8940     Opcode_ritlb1_encode_fns, 0, 0 },
8941   { "witlb", ICLASS_xt_iclass_witlb,
8942     0,
8943     Opcode_witlb_encode_fns, 0, 0 },
8944   { "ldpte", ICLASS_xt_iclass_ldpte,
8945     0,
8946     Opcode_ldpte_encode_fns, 0, 0 },
8947   { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
8948     XTENSA_OPCODE_IS_BRANCH,
8949     Opcode_hwwitlba_encode_fns, 0, 0 },
8950   { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
8951     0,
8952     Opcode_hwwdtlba_encode_fns, 0, 0 },
8953   { "nsa", ICLASS_xt_iclass_nsa,
8954     0,
8955     Opcode_nsa_encode_fns, 0, 0 },
8956   { "nsau", ICLASS_xt_iclass_nsa,
8957     0,
8958     Opcode_nsau_encode_fns, 0, 0 }
8959 };
8960
8961 enum xtensa_opcode_id {
8962   OPCODE_EXCW,
8963   OPCODE_RFE,
8964   OPCODE_RFDE,
8965   OPCODE_SYSCALL,
8966   OPCODE_SIMCALL,
8967   OPCODE_CALL12,
8968   OPCODE_CALL8,
8969   OPCODE_CALL4,
8970   OPCODE_CALLX12,
8971   OPCODE_CALLX8,
8972   OPCODE_CALLX4,
8973   OPCODE_ENTRY,
8974   OPCODE_MOVSP,
8975   OPCODE_ROTW,
8976   OPCODE_RETW,
8977   OPCODE_RETW_N,
8978   OPCODE_RFWO,
8979   OPCODE_RFWU,
8980   OPCODE_L32E,
8981   OPCODE_S32E,
8982   OPCODE_RSR_WINDOWBASE,
8983   OPCODE_WSR_WINDOWBASE,
8984   OPCODE_XSR_WINDOWBASE,
8985   OPCODE_RSR_WINDOWSTART,
8986   OPCODE_WSR_WINDOWSTART,
8987   OPCODE_XSR_WINDOWSTART,
8988   OPCODE_ADD_N,
8989   OPCODE_ADDI_N,
8990   OPCODE_BEQZ_N,
8991   OPCODE_BNEZ_N,
8992   OPCODE_ILL_N,
8993   OPCODE_L32I_N,
8994   OPCODE_MOV_N,
8995   OPCODE_MOVI_N,
8996   OPCODE_NOP_N,
8997   OPCODE_RET_N,
8998   OPCODE_S32I_N,
8999   OPCODE_ADDI,
9000   OPCODE_ADDMI,
9001   OPCODE_ADD,
9002   OPCODE_SUB,
9003   OPCODE_ADDX2,
9004   OPCODE_ADDX4,
9005   OPCODE_ADDX8,
9006   OPCODE_SUBX2,
9007   OPCODE_SUBX4,
9008   OPCODE_SUBX8,
9009   OPCODE_AND,
9010   OPCODE_OR,
9011   OPCODE_XOR,
9012   OPCODE_BEQI,
9013   OPCODE_BNEI,
9014   OPCODE_BGEI,
9015   OPCODE_BLTI,
9016   OPCODE_BBCI,
9017   OPCODE_BBSI,
9018   OPCODE_BGEUI,
9019   OPCODE_BLTUI,
9020   OPCODE_BEQ,
9021   OPCODE_BNE,
9022   OPCODE_BGE,
9023   OPCODE_BLT,
9024   OPCODE_BGEU,
9025   OPCODE_BLTU,
9026   OPCODE_BANY,
9027   OPCODE_BNONE,
9028   OPCODE_BALL,
9029   OPCODE_BNALL,
9030   OPCODE_BBC,
9031   OPCODE_BBS,
9032   OPCODE_BEQZ,
9033   OPCODE_BNEZ,
9034   OPCODE_BGEZ,
9035   OPCODE_BLTZ,
9036   OPCODE_CALL0,
9037   OPCODE_CALLX0,
9038   OPCODE_EXTUI,
9039   OPCODE_ILL,
9040   OPCODE_J,
9041   OPCODE_JX,
9042   OPCODE_L16UI,
9043   OPCODE_L16SI,
9044   OPCODE_L32I,
9045   OPCODE_L32R,
9046   OPCODE_L8UI,
9047   OPCODE_LOOP,
9048   OPCODE_LOOPNEZ,
9049   OPCODE_LOOPGTZ,
9050   OPCODE_MOVI,
9051   OPCODE_MOVEQZ,
9052   OPCODE_MOVNEZ,
9053   OPCODE_MOVLTZ,
9054   OPCODE_MOVGEZ,
9055   OPCODE_NEG,
9056   OPCODE_ABS,
9057   OPCODE_NOP,
9058   OPCODE_RET,
9059   OPCODE_S16I,
9060   OPCODE_S32I,
9061   OPCODE_S8I,
9062   OPCODE_SSR,
9063   OPCODE_SSL,
9064   OPCODE_SSA8L,
9065   OPCODE_SSA8B,
9066   OPCODE_SSAI,
9067   OPCODE_SLL,
9068   OPCODE_SRC,
9069   OPCODE_SRL,
9070   OPCODE_SRA,
9071   OPCODE_SLLI,
9072   OPCODE_SRAI,
9073   OPCODE_SRLI,
9074   OPCODE_MEMW,
9075   OPCODE_EXTW,
9076   OPCODE_ISYNC,
9077   OPCODE_RSYNC,
9078   OPCODE_ESYNC,
9079   OPCODE_DSYNC,
9080   OPCODE_RSIL,
9081   OPCODE_RSR_LEND,
9082   OPCODE_WSR_LEND,
9083   OPCODE_XSR_LEND,
9084   OPCODE_RSR_LCOUNT,
9085   OPCODE_WSR_LCOUNT,
9086   OPCODE_XSR_LCOUNT,
9087   OPCODE_RSR_LBEG,
9088   OPCODE_WSR_LBEG,
9089   OPCODE_XSR_LBEG,
9090   OPCODE_RSR_SAR,
9091   OPCODE_WSR_SAR,
9092   OPCODE_XSR_SAR,
9093   OPCODE_RSR_LITBASE,
9094   OPCODE_WSR_LITBASE,
9095   OPCODE_XSR_LITBASE,
9096   OPCODE_RSR_176,
9097   OPCODE_RSR_208,
9098   OPCODE_RSR_PS,
9099   OPCODE_WSR_PS,
9100   OPCODE_XSR_PS,
9101   OPCODE_RSR_EPC1,
9102   OPCODE_WSR_EPC1,
9103   OPCODE_XSR_EPC1,
9104   OPCODE_RSR_EXCSAVE1,
9105   OPCODE_WSR_EXCSAVE1,
9106   OPCODE_XSR_EXCSAVE1,
9107   OPCODE_RSR_EPC2,
9108   OPCODE_WSR_EPC2,
9109   OPCODE_XSR_EPC2,
9110   OPCODE_RSR_EXCSAVE2,
9111   OPCODE_WSR_EXCSAVE2,
9112   OPCODE_XSR_EXCSAVE2,
9113   OPCODE_RSR_EPC3,
9114   OPCODE_WSR_EPC3,
9115   OPCODE_XSR_EPC3,
9116   OPCODE_RSR_EXCSAVE3,
9117   OPCODE_WSR_EXCSAVE3,
9118   OPCODE_XSR_EXCSAVE3,
9119   OPCODE_RSR_EPC4,
9120   OPCODE_WSR_EPC4,
9121   OPCODE_XSR_EPC4,
9122   OPCODE_RSR_EXCSAVE4,
9123   OPCODE_WSR_EXCSAVE4,
9124   OPCODE_XSR_EXCSAVE4,
9125   OPCODE_RSR_EPS2,
9126   OPCODE_WSR_EPS2,
9127   OPCODE_XSR_EPS2,
9128   OPCODE_RSR_EPS3,
9129   OPCODE_WSR_EPS3,
9130   OPCODE_XSR_EPS3,
9131   OPCODE_RSR_EPS4,
9132   OPCODE_WSR_EPS4,
9133   OPCODE_XSR_EPS4,
9134   OPCODE_RSR_EXCVADDR,
9135   OPCODE_WSR_EXCVADDR,
9136   OPCODE_XSR_EXCVADDR,
9137   OPCODE_RSR_DEPC,
9138   OPCODE_WSR_DEPC,
9139   OPCODE_XSR_DEPC,
9140   OPCODE_RSR_EXCCAUSE,
9141   OPCODE_WSR_EXCCAUSE,
9142   OPCODE_XSR_EXCCAUSE,
9143   OPCODE_RSR_MISC0,
9144   OPCODE_WSR_MISC0,
9145   OPCODE_XSR_MISC0,
9146   OPCODE_RSR_MISC1,
9147   OPCODE_WSR_MISC1,
9148   OPCODE_XSR_MISC1,
9149   OPCODE_RSR_PRID,
9150   OPCODE_RFI,
9151   OPCODE_WAITI,
9152   OPCODE_RSR_INTERRUPT,
9153   OPCODE_WSR_INTSET,
9154   OPCODE_WSR_INTCLEAR,
9155   OPCODE_RSR_INTENABLE,
9156   OPCODE_WSR_INTENABLE,
9157   OPCODE_XSR_INTENABLE,
9158   OPCODE_BREAK,
9159   OPCODE_BREAK_N,
9160   OPCODE_RSR_DBREAKA0,
9161   OPCODE_WSR_DBREAKA0,
9162   OPCODE_XSR_DBREAKA0,
9163   OPCODE_RSR_DBREAKC0,
9164   OPCODE_WSR_DBREAKC0,
9165   OPCODE_XSR_DBREAKC0,
9166   OPCODE_RSR_DBREAKA1,
9167   OPCODE_WSR_DBREAKA1,
9168   OPCODE_XSR_DBREAKA1,
9169   OPCODE_RSR_DBREAKC1,
9170   OPCODE_WSR_DBREAKC1,
9171   OPCODE_XSR_DBREAKC1,
9172   OPCODE_RSR_IBREAKA0,
9173   OPCODE_WSR_IBREAKA0,
9174   OPCODE_XSR_IBREAKA0,
9175   OPCODE_RSR_IBREAKA1,
9176   OPCODE_WSR_IBREAKA1,
9177   OPCODE_XSR_IBREAKA1,
9178   OPCODE_RSR_IBREAKENABLE,
9179   OPCODE_WSR_IBREAKENABLE,
9180   OPCODE_XSR_IBREAKENABLE,
9181   OPCODE_RSR_DEBUGCAUSE,
9182   OPCODE_WSR_DEBUGCAUSE,
9183   OPCODE_XSR_DEBUGCAUSE,
9184   OPCODE_RSR_ICOUNT,
9185   OPCODE_WSR_ICOUNT,
9186   OPCODE_XSR_ICOUNT,
9187   OPCODE_RSR_ICOUNTLEVEL,
9188   OPCODE_WSR_ICOUNTLEVEL,
9189   OPCODE_XSR_ICOUNTLEVEL,
9190   OPCODE_RSR_DDR,
9191   OPCODE_WSR_DDR,
9192   OPCODE_XSR_DDR,
9193   OPCODE_RFDO,
9194   OPCODE_RFDD,
9195   OPCODE_RSR_CCOUNT,
9196   OPCODE_WSR_CCOUNT,
9197   OPCODE_XSR_CCOUNT,
9198   OPCODE_RSR_CCOMPARE0,
9199   OPCODE_WSR_CCOMPARE0,
9200   OPCODE_XSR_CCOMPARE0,
9201   OPCODE_RSR_CCOMPARE1,
9202   OPCODE_WSR_CCOMPARE1,
9203   OPCODE_XSR_CCOMPARE1,
9204   OPCODE_RSR_CCOMPARE2,
9205   OPCODE_WSR_CCOMPARE2,
9206   OPCODE_XSR_CCOMPARE2,
9207   OPCODE_IPF,
9208   OPCODE_IHI,
9209   OPCODE_III,
9210   OPCODE_LICT,
9211   OPCODE_LICW,
9212   OPCODE_SICT,
9213   OPCODE_SICW,
9214   OPCODE_DHWB,
9215   OPCODE_DHWBI,
9216   OPCODE_DIWB,
9217   OPCODE_DIWBI,
9218   OPCODE_DHI,
9219   OPCODE_DII,
9220   OPCODE_DPFR,
9221   OPCODE_DPFW,
9222   OPCODE_DPFRO,
9223   OPCODE_DPFWO,
9224   OPCODE_SDCT,
9225   OPCODE_LDCT,
9226   OPCODE_WSR_PTEVADDR,
9227   OPCODE_RSR_PTEVADDR,
9228   OPCODE_XSR_PTEVADDR,
9229   OPCODE_RSR_RASID,
9230   OPCODE_WSR_RASID,
9231   OPCODE_XSR_RASID,
9232   OPCODE_RSR_ITLBCFG,
9233   OPCODE_WSR_ITLBCFG,
9234   OPCODE_XSR_ITLBCFG,
9235   OPCODE_RSR_DTLBCFG,
9236   OPCODE_WSR_DTLBCFG,
9237   OPCODE_XSR_DTLBCFG,
9238   OPCODE_IDTLB,
9239   OPCODE_PDTLB,
9240   OPCODE_RDTLB0,
9241   OPCODE_RDTLB1,
9242   OPCODE_WDTLB,
9243   OPCODE_IITLB,
9244   OPCODE_PITLB,
9245   OPCODE_RITLB0,
9246   OPCODE_RITLB1,
9247   OPCODE_WITLB,
9248   OPCODE_LDPTE,
9249   OPCODE_HWWITLBA,
9250   OPCODE_HWWDTLBA,
9251   OPCODE_NSA,
9252   OPCODE_NSAU
9253 };
9254
9255 \f
9256 /* Slot-specific opcode decode functions.  */
9257
9258 static int
9259 Slot_inst_decode (const xtensa_insnbuf insn)
9260 {
9261   switch (Field_op0_Slot_inst_get (insn))
9262     {
9263     case 0:
9264       switch (Field_op1_Slot_inst_get (insn))
9265         {
9266         case 0:
9267           switch (Field_op2_Slot_inst_get (insn))
9268             {
9269             case 0:
9270               switch (Field_r_Slot_inst_get (insn))
9271                 {
9272                 case 0:
9273                   switch (Field_m_Slot_inst_get (insn))
9274                     {
9275                     case 0:
9276                       if (Field_s_Slot_inst_get (insn) == 0 &&
9277                           Field_n_Slot_inst_get (insn) == 0)
9278                         return OPCODE_ILL;
9279                       break;
9280                     case 2:
9281                       switch (Field_n_Slot_inst_get (insn))
9282                         {
9283                         case 0:
9284                           return OPCODE_RET;
9285                         case 1:
9286                           return OPCODE_RETW;
9287                         case 2:
9288                           return OPCODE_JX;
9289                         }
9290                       break;
9291                     case 3:
9292                       switch (Field_n_Slot_inst_get (insn))
9293                         {
9294                         case 0:
9295                           return OPCODE_CALLX0;
9296                         case 1:
9297                           return OPCODE_CALLX4;
9298                         case 2:
9299                           return OPCODE_CALLX8;
9300                         case 3:
9301                           return OPCODE_CALLX12;
9302                         }
9303                       break;
9304                     }
9305                   break;
9306                 case 1:
9307                   return OPCODE_MOVSP;
9308                 case 2:
9309                   if (Field_s_Slot_inst_get (insn) == 0)
9310                     {
9311                       switch (Field_t_Slot_inst_get (insn))
9312                         {
9313                         case 0:
9314                           return OPCODE_ISYNC;
9315                         case 1:
9316                           return OPCODE_RSYNC;
9317                         case 2:
9318                           return OPCODE_ESYNC;
9319                         case 3:
9320                           return OPCODE_DSYNC;
9321                         case 8:
9322                           return OPCODE_EXCW;
9323                         case 12:
9324                           return OPCODE_MEMW;
9325                         case 13:
9326                           return OPCODE_EXTW;
9327                         case 15:
9328                           return OPCODE_NOP;
9329                         }
9330                     }
9331                   break;
9332                 case 3:
9333                   switch (Field_t_Slot_inst_get (insn))
9334                     {
9335                     case 0:
9336                       switch (Field_s_Slot_inst_get (insn))
9337                         {
9338                         case 0:
9339                           return OPCODE_RFE;
9340                         case 2:
9341                           return OPCODE_RFDE;
9342                         case 4:
9343                           return OPCODE_RFWO;
9344                         case 5:
9345                           return OPCODE_RFWU;
9346                         }
9347                       break;
9348                     case 1:
9349                       return OPCODE_RFI;
9350                     }
9351                   break;
9352                 case 4:
9353                   return OPCODE_BREAK;
9354                 case 5:
9355                   switch (Field_s_Slot_inst_get (insn))
9356                     {
9357                     case 0:
9358                       if (Field_t_Slot_inst_get (insn) == 0)
9359                         return OPCODE_SYSCALL;
9360                       break;
9361                     case 1:
9362                       if (Field_t_Slot_inst_get (insn) == 0)
9363                         return OPCODE_SIMCALL;
9364                       break;
9365                     }
9366                   break;
9367                 case 6:
9368                   return OPCODE_RSIL;
9369                 case 7:
9370                   if (Field_t_Slot_inst_get (insn) == 0)
9371                     return OPCODE_WAITI;
9372                   break;
9373                 }
9374               break;
9375             case 1:
9376               return OPCODE_AND;
9377             case 2:
9378               return OPCODE_OR;
9379             case 3:
9380               return OPCODE_XOR;
9381             case 4:
9382               switch (Field_r_Slot_inst_get (insn))
9383                 {
9384                 case 0:
9385                   if (Field_t_Slot_inst_get (insn) == 0)
9386                     return OPCODE_SSR;
9387                   break;
9388                 case 1:
9389                   if (Field_t_Slot_inst_get (insn) == 0)
9390                     return OPCODE_SSL;
9391                   break;
9392                 case 2:
9393                   if (Field_t_Slot_inst_get (insn) == 0)
9394                     return OPCODE_SSA8L;
9395                   break;
9396                 case 3:
9397                   if (Field_t_Slot_inst_get (insn) == 0)
9398                     return OPCODE_SSA8B;
9399                   break;
9400                 case 4:
9401                   if (Field_thi3_Slot_inst_get (insn) == 0)
9402                     return OPCODE_SSAI;
9403                   break;
9404                 case 8:
9405                   if (Field_s_Slot_inst_get (insn) == 0)
9406                     return OPCODE_ROTW;
9407                   break;
9408                 case 14:
9409                   return OPCODE_NSA;
9410                 case 15:
9411                   return OPCODE_NSAU;
9412                 }
9413               break;
9414             case 5:
9415               switch (Field_r_Slot_inst_get (insn))
9416                 {
9417                 case 1:
9418                   return OPCODE_HWWITLBA;
9419                 case 3:
9420                   return OPCODE_RITLB0;
9421                 case 4:
9422                   if (Field_t_Slot_inst_get (insn) == 0)
9423                     return OPCODE_IITLB;
9424                   break;
9425                 case 5:
9426                   return OPCODE_PITLB;
9427                 case 6:
9428                   return OPCODE_WITLB;
9429                 case 7:
9430                   return OPCODE_RITLB1;
9431                 case 9:
9432                   return OPCODE_HWWDTLBA;
9433                 case 11:
9434                   return OPCODE_RDTLB0;
9435                 case 12:
9436                   if (Field_t_Slot_inst_get (insn) == 0)
9437                     return OPCODE_IDTLB;
9438                   break;
9439                 case 13:
9440                   return OPCODE_PDTLB;
9441                 case 14:
9442                   return OPCODE_WDTLB;
9443                 case 15:
9444                   return OPCODE_RDTLB1;
9445                 }
9446               break;
9447             case 6:
9448               switch (Field_s_Slot_inst_get (insn))
9449                 {
9450                 case 0:
9451                   return OPCODE_NEG;
9452                 case 1:
9453                   return OPCODE_ABS;
9454                 }
9455               break;
9456             case 8:
9457               return OPCODE_ADD;
9458             case 9:
9459               return OPCODE_ADDX2;
9460             case 10:
9461               return OPCODE_ADDX4;
9462             case 11:
9463               return OPCODE_ADDX8;
9464             case 12:
9465               return OPCODE_SUB;
9466             case 13:
9467               return OPCODE_SUBX2;
9468             case 14:
9469               return OPCODE_SUBX4;
9470             case 15:
9471               return OPCODE_SUBX8;
9472             }
9473           break;
9474         case 1:
9475           switch (Field_op2_Slot_inst_get (insn))
9476             {
9477             case 0:
9478             case 1:
9479               return OPCODE_SLLI;
9480             case 2:
9481             case 3:
9482               return OPCODE_SRAI;
9483             case 4:
9484               return OPCODE_SRLI;
9485             case 6:
9486               switch (Field_sr_Slot_inst_get (insn))
9487                 {
9488                 case 0:
9489                   return OPCODE_XSR_LBEG;
9490                 case 1:
9491                   return OPCODE_XSR_LEND;
9492                 case 2:
9493                   return OPCODE_XSR_LCOUNT;
9494                 case 3:
9495                   return OPCODE_XSR_SAR;
9496                 case 5:
9497                   return OPCODE_XSR_LITBASE;
9498                 case 72:
9499                   return OPCODE_XSR_WINDOWBASE;
9500                 case 73:
9501                   return OPCODE_XSR_WINDOWSTART;
9502                 case 83:
9503                   return OPCODE_XSR_PTEVADDR;
9504                 case 90:
9505                   return OPCODE_XSR_RASID;
9506                 case 91:
9507                   return OPCODE_XSR_ITLBCFG;
9508                 case 92:
9509                   return OPCODE_XSR_DTLBCFG;
9510                 case 96:
9511                   return OPCODE_XSR_IBREAKENABLE;
9512                 case 104:
9513                   return OPCODE_XSR_DDR;
9514                 case 128:
9515                   return OPCODE_XSR_IBREAKA0;
9516                 case 129:
9517                   return OPCODE_XSR_IBREAKA1;
9518                 case 144:
9519                   return OPCODE_XSR_DBREAKA0;
9520                 case 145:
9521                   return OPCODE_XSR_DBREAKA1;
9522                 case 160:
9523                   return OPCODE_XSR_DBREAKC0;
9524                 case 161:
9525                   return OPCODE_XSR_DBREAKC1;
9526                 case 177:
9527                   return OPCODE_XSR_EPC1;
9528                 case 178:
9529                   return OPCODE_XSR_EPC2;
9530                 case 179:
9531                   return OPCODE_XSR_EPC3;
9532                 case 180:
9533                   return OPCODE_XSR_EPC4;
9534                 case 192:
9535                   return OPCODE_XSR_DEPC;
9536                 case 194:
9537                   return OPCODE_XSR_EPS2;
9538                 case 195:
9539                   return OPCODE_XSR_EPS3;
9540                 case 196:
9541                   return OPCODE_XSR_EPS4;
9542                 case 209:
9543                   return OPCODE_XSR_EXCSAVE1;
9544                 case 210:
9545                   return OPCODE_XSR_EXCSAVE2;
9546                 case 211:
9547                   return OPCODE_XSR_EXCSAVE3;
9548                 case 212:
9549                   return OPCODE_XSR_EXCSAVE4;
9550                 case 228:
9551                   return OPCODE_XSR_INTENABLE;
9552                 case 230:
9553                   return OPCODE_XSR_PS;
9554                 case 232:
9555                   return OPCODE_XSR_EXCCAUSE;
9556                 case 233:
9557                   return OPCODE_XSR_DEBUGCAUSE;
9558                 case 234:
9559                   return OPCODE_XSR_CCOUNT;
9560                 case 236:
9561                   return OPCODE_XSR_ICOUNT;
9562                 case 237:
9563                   return OPCODE_XSR_ICOUNTLEVEL;
9564                 case 238:
9565                   return OPCODE_XSR_EXCVADDR;
9566                 case 240:
9567                   return OPCODE_XSR_CCOMPARE0;
9568                 case 241:
9569                   return OPCODE_XSR_CCOMPARE1;
9570                 case 242:
9571                   return OPCODE_XSR_CCOMPARE2;
9572                 case 244:
9573                   return OPCODE_XSR_MISC0;
9574                 case 245:
9575                   return OPCODE_XSR_MISC1;
9576                 }
9577               break;
9578             case 8:
9579               return OPCODE_SRC;
9580             case 9:
9581               if (Field_s_Slot_inst_get (insn) == 0)
9582                 return OPCODE_SRL;
9583               break;
9584             case 10:
9585               if (Field_t_Slot_inst_get (insn) == 0)
9586                 return OPCODE_SLL;
9587               break;
9588             case 11:
9589               if (Field_s_Slot_inst_get (insn) == 0)
9590                 return OPCODE_SRA;
9591               break;
9592             case 15:
9593               switch (Field_r_Slot_inst_get (insn))
9594                 {
9595                 case 0:
9596                   return OPCODE_LICT;
9597                 case 1:
9598                   return OPCODE_SICT;
9599                 case 2:
9600                   return OPCODE_LICW;
9601                 case 3:
9602                   return OPCODE_SICW;
9603                 case 8:
9604                   return OPCODE_LDCT;
9605                 case 9:
9606                   return OPCODE_SDCT;
9607                 case 14:
9608                   if (Field_t_Slot_inst_get (insn) == 0)
9609                     return OPCODE_RFDO;
9610                   if (Field_t_Slot_inst_get (insn) == 1)
9611                     return OPCODE_RFDD;
9612                   break;
9613                 case 15:
9614                   return OPCODE_LDPTE;
9615                 }
9616               break;
9617             }
9618           break;
9619         case 3:
9620           switch (Field_op2_Slot_inst_get (insn))
9621             {
9622             case 0:
9623               switch (Field_sr_Slot_inst_get (insn))
9624                 {
9625                 case 0:
9626                   return OPCODE_RSR_LBEG;
9627                 case 1:
9628                   return OPCODE_RSR_LEND;
9629                 case 2:
9630                   return OPCODE_RSR_LCOUNT;
9631                 case 3:
9632                   return OPCODE_RSR_SAR;
9633                 case 5:
9634                   return OPCODE_RSR_LITBASE;
9635                 case 72:
9636                   return OPCODE_RSR_WINDOWBASE;
9637                 case 73:
9638                   return OPCODE_RSR_WINDOWSTART;
9639                 case 83:
9640                   return OPCODE_RSR_PTEVADDR;
9641                 case 90:
9642                   return OPCODE_RSR_RASID;
9643                 case 91:
9644                   return OPCODE_RSR_ITLBCFG;
9645                 case 92:
9646                   return OPCODE_RSR_DTLBCFG;
9647                 case 96:
9648                   return OPCODE_RSR_IBREAKENABLE;
9649                 case 104:
9650                   return OPCODE_RSR_DDR;
9651                 case 128:
9652                   return OPCODE_RSR_IBREAKA0;
9653                 case 129:
9654                   return OPCODE_RSR_IBREAKA1;
9655                 case 144:
9656                   return OPCODE_RSR_DBREAKA0;
9657                 case 145:
9658                   return OPCODE_RSR_DBREAKA1;
9659                 case 160:
9660                   return OPCODE_RSR_DBREAKC0;
9661                 case 161:
9662                   return OPCODE_RSR_DBREAKC1;
9663                 case 176:
9664                   return OPCODE_RSR_176;
9665                 case 177:
9666                   return OPCODE_RSR_EPC1;
9667                 case 178:
9668                   return OPCODE_RSR_EPC2;
9669                 case 179:
9670                   return OPCODE_RSR_EPC3;
9671                 case 180:
9672                   return OPCODE_RSR_EPC4;
9673                 case 192:
9674                   return OPCODE_RSR_DEPC;
9675                 case 194:
9676                   return OPCODE_RSR_EPS2;
9677                 case 195:
9678                   return OPCODE_RSR_EPS3;
9679                 case 196:
9680                   return OPCODE_RSR_EPS4;
9681                 case 208:
9682                   return OPCODE_RSR_208;
9683                 case 209:
9684                   return OPCODE_RSR_EXCSAVE1;
9685                 case 210:
9686                   return OPCODE_RSR_EXCSAVE2;
9687                 case 211:
9688                   return OPCODE_RSR_EXCSAVE3;
9689                 case 212:
9690                   return OPCODE_RSR_EXCSAVE4;
9691                 case 226:
9692                   return OPCODE_RSR_INTERRUPT;
9693                 case 228:
9694                   return OPCODE_RSR_INTENABLE;
9695                 case 230:
9696                   return OPCODE_RSR_PS;
9697                 case 232:
9698                   return OPCODE_RSR_EXCCAUSE;
9699                 case 233:
9700                   return OPCODE_RSR_DEBUGCAUSE;
9701                 case 234:
9702                   return OPCODE_RSR_CCOUNT;
9703                 case 235:
9704                   return OPCODE_RSR_PRID;
9705                 case 236:
9706                   return OPCODE_RSR_ICOUNT;
9707                 case 237:
9708                   return OPCODE_RSR_ICOUNTLEVEL;
9709                 case 238:
9710                   return OPCODE_RSR_EXCVADDR;
9711                 case 240:
9712                   return OPCODE_RSR_CCOMPARE0;
9713                 case 241:
9714                   return OPCODE_RSR_CCOMPARE1;
9715                 case 242:
9716                   return OPCODE_RSR_CCOMPARE2;
9717                 case 244:
9718                   return OPCODE_RSR_MISC0;
9719                 case 245:
9720                   return OPCODE_RSR_MISC1;
9721                 }
9722               break;
9723             case 1:
9724               switch (Field_sr_Slot_inst_get (insn))
9725                 {
9726                 case 0:
9727                   return OPCODE_WSR_LBEG;
9728                 case 1:
9729                   return OPCODE_WSR_LEND;
9730                 case 2:
9731                   return OPCODE_WSR_LCOUNT;
9732                 case 3:
9733                   return OPCODE_WSR_SAR;
9734                 case 5:
9735                   return OPCODE_WSR_LITBASE;
9736                 case 72:
9737                   return OPCODE_WSR_WINDOWBASE;
9738                 case 73:
9739                   return OPCODE_WSR_WINDOWSTART;
9740                 case 83:
9741                   return OPCODE_WSR_PTEVADDR;
9742                 case 90:
9743                   return OPCODE_WSR_RASID;
9744                 case 91:
9745                   return OPCODE_WSR_ITLBCFG;
9746                 case 92:
9747                   return OPCODE_WSR_DTLBCFG;
9748                 case 96:
9749                   return OPCODE_WSR_IBREAKENABLE;
9750                 case 104:
9751                   return OPCODE_WSR_DDR;
9752                 case 128:
9753                   return OPCODE_WSR_IBREAKA0;
9754                 case 129:
9755                   return OPCODE_WSR_IBREAKA1;
9756                 case 144:
9757                   return OPCODE_WSR_DBREAKA0;
9758                 case 145:
9759                   return OPCODE_WSR_DBREAKA1;
9760                 case 160:
9761                   return OPCODE_WSR_DBREAKC0;
9762                 case 161:
9763                   return OPCODE_WSR_DBREAKC1;
9764                 case 177:
9765                   return OPCODE_WSR_EPC1;
9766                 case 178:
9767                   return OPCODE_WSR_EPC2;
9768                 case 179:
9769                   return OPCODE_WSR_EPC3;
9770                 case 180:
9771                   return OPCODE_WSR_EPC4;
9772                 case 192:
9773                   return OPCODE_WSR_DEPC;
9774                 case 194:
9775                   return OPCODE_WSR_EPS2;
9776                 case 195:
9777                   return OPCODE_WSR_EPS3;
9778                 case 196:
9779                   return OPCODE_WSR_EPS4;
9780                 case 209:
9781                   return OPCODE_WSR_EXCSAVE1;
9782                 case 210:
9783                   return OPCODE_WSR_EXCSAVE2;
9784                 case 211:
9785                   return OPCODE_WSR_EXCSAVE3;
9786                 case 212:
9787                   return OPCODE_WSR_EXCSAVE4;
9788                 case 226:
9789                   return OPCODE_WSR_INTSET;
9790                 case 227:
9791                   return OPCODE_WSR_INTCLEAR;
9792                 case 228:
9793                   return OPCODE_WSR_INTENABLE;
9794                 case 230:
9795                   return OPCODE_WSR_PS;
9796                 case 232:
9797                   return OPCODE_WSR_EXCCAUSE;
9798                 case 233:
9799                   return OPCODE_WSR_DEBUGCAUSE;
9800                 case 234:
9801                   return OPCODE_WSR_CCOUNT;
9802                 case 236:
9803                   return OPCODE_WSR_ICOUNT;
9804                 case 237:
9805                   return OPCODE_WSR_ICOUNTLEVEL;
9806                 case 238:
9807                   return OPCODE_WSR_EXCVADDR;
9808                 case 240:
9809                   return OPCODE_WSR_CCOMPARE0;
9810                 case 241:
9811                   return OPCODE_WSR_CCOMPARE1;
9812                 case 242:
9813                   return OPCODE_WSR_CCOMPARE2;
9814                 case 244:
9815                   return OPCODE_WSR_MISC0;
9816                 case 245:
9817                   return OPCODE_WSR_MISC1;
9818                 }
9819               break;
9820             case 8:
9821               return OPCODE_MOVEQZ;
9822             case 9:
9823               return OPCODE_MOVNEZ;
9824             case 10:
9825               return OPCODE_MOVLTZ;
9826             case 11:
9827               return OPCODE_MOVGEZ;
9828             }
9829           break;
9830         case 4:
9831         case 5:
9832           return OPCODE_EXTUI;
9833         case 9:
9834           switch (Field_op2_Slot_inst_get (insn))
9835             {
9836             case 0:
9837               return OPCODE_L32E;
9838             case 4:
9839               return OPCODE_S32E;
9840             }
9841           break;
9842         }
9843       break;
9844     case 1:
9845       return OPCODE_L32R;
9846     case 2:
9847       switch (Field_r_Slot_inst_get (insn))
9848         {
9849         case 0:
9850           return OPCODE_L8UI;
9851         case 1:
9852           return OPCODE_L16UI;
9853         case 2:
9854           return OPCODE_L32I;
9855         case 4:
9856           return OPCODE_S8I;
9857         case 5:
9858           return OPCODE_S16I;
9859         case 6:
9860           return OPCODE_S32I;
9861         case 7:
9862           switch (Field_t_Slot_inst_get (insn))
9863             {
9864             case 0:
9865               return OPCODE_DPFR;
9866             case 1:
9867               return OPCODE_DPFW;
9868             case 2:
9869               return OPCODE_DPFRO;
9870             case 3:
9871               return OPCODE_DPFWO;
9872             case 4:
9873               return OPCODE_DHWB;
9874             case 5:
9875               return OPCODE_DHWBI;
9876             case 6:
9877               return OPCODE_DHI;
9878             case 7:
9879               return OPCODE_DII;
9880             case 8:
9881               switch (Field_op1_Slot_inst_get (insn))
9882                 {
9883                 case 4:
9884                   return OPCODE_DIWB;
9885                 case 5:
9886                   return OPCODE_DIWBI;
9887                 }
9888               break;
9889             case 12:
9890               return OPCODE_IPF;
9891             case 14:
9892               return OPCODE_IHI;
9893             case 15:
9894               return OPCODE_III;
9895             }
9896           break;
9897         case 9:
9898           return OPCODE_L16SI;
9899         case 10:
9900           return OPCODE_MOVI;
9901         case 12:
9902           return OPCODE_ADDI;
9903         case 13:
9904           return OPCODE_ADDMI;
9905         }
9906       break;
9907     case 5:
9908       switch (Field_n_Slot_inst_get (insn))
9909         {
9910         case 0:
9911           return OPCODE_CALL0;
9912         case 1:
9913           return OPCODE_CALL4;
9914         case 2:
9915           return OPCODE_CALL8;
9916         case 3:
9917           return OPCODE_CALL12;
9918         }
9919       break;
9920     case 6:
9921       switch (Field_n_Slot_inst_get (insn))
9922         {
9923         case 0:
9924           return OPCODE_J;
9925         case 1:
9926           switch (Field_m_Slot_inst_get (insn))
9927             {
9928             case 0:
9929               return OPCODE_BEQZ;
9930             case 1:
9931               return OPCODE_BNEZ;
9932             case 2:
9933               return OPCODE_BLTZ;
9934             case 3:
9935               return OPCODE_BGEZ;
9936             }
9937           break;
9938         case 2:
9939           switch (Field_m_Slot_inst_get (insn))
9940             {
9941             case 0:
9942               return OPCODE_BEQI;
9943             case 1:
9944               return OPCODE_BNEI;
9945             case 2:
9946               return OPCODE_BLTI;
9947             case 3:
9948               return OPCODE_BGEI;
9949             }
9950           break;
9951         case 3:
9952           switch (Field_m_Slot_inst_get (insn))
9953             {
9954             case 0:
9955               return OPCODE_ENTRY;
9956             case 1:
9957               switch (Field_r_Slot_inst_get (insn))
9958                 {
9959                 case 8:
9960                   return OPCODE_LOOP;
9961                 case 9:
9962                   return OPCODE_LOOPNEZ;
9963                 case 10:
9964                   return OPCODE_LOOPGTZ;
9965                 }
9966               break;
9967             case 2:
9968               return OPCODE_BLTUI;
9969             case 3:
9970               return OPCODE_BGEUI;
9971             }
9972           break;
9973         }
9974       break;
9975     case 7:
9976       switch (Field_r_Slot_inst_get (insn))
9977         {
9978         case 0:
9979           return OPCODE_BNONE;
9980         case 1:
9981           return OPCODE_BEQ;
9982         case 2:
9983           return OPCODE_BLT;
9984         case 3:
9985           return OPCODE_BLTU;
9986         case 4:
9987           return OPCODE_BALL;
9988         case 5:
9989           return OPCODE_BBC;
9990         case 6:
9991         case 7:
9992           return OPCODE_BBCI;
9993         case 8:
9994           return OPCODE_BANY;
9995         case 9:
9996           return OPCODE_BNE;
9997         case 10:
9998           return OPCODE_BGE;
9999         case 11:
10000           return OPCODE_BGEU;
10001         case 12:
10002           return OPCODE_BNALL;
10003         case 13:
10004           return OPCODE_BBS;
10005         case 14:
10006         case 15:
10007           return OPCODE_BBSI;
10008         }
10009       break;
10010     }
10011   return 0;
10012 }
10013
10014 static int
10015 Slot_inst16b_decode (const xtensa_insnbuf insn)
10016 {
10017   switch (Field_op0_Slot_inst16b_get (insn))
10018     {
10019     case 12:
10020       switch (Field_i_Slot_inst16b_get (insn))
10021         {
10022         case 0:
10023           return OPCODE_MOVI_N;
10024         case 1:
10025           switch (Field_z_Slot_inst16b_get (insn))
10026             {
10027             case 0:
10028               return OPCODE_BEQZ_N;
10029             case 1:
10030               return OPCODE_BNEZ_N;
10031             }
10032           break;
10033         }
10034       break;
10035     case 13:
10036       switch (Field_r_Slot_inst16b_get (insn))
10037         {
10038         case 0:
10039           return OPCODE_MOV_N;
10040         case 15:
10041           switch (Field_t_Slot_inst16b_get (insn))
10042             {
10043             case 0:
10044               return OPCODE_RET_N;
10045             case 1:
10046               return OPCODE_RETW_N;
10047             case 2:
10048               return OPCODE_BREAK_N;
10049             case 3:
10050               if (Field_s_Slot_inst16b_get (insn) == 0)
10051                 return OPCODE_NOP_N;
10052               break;
10053             case 6:
10054               if (Field_s_Slot_inst16b_get (insn) == 0)
10055                 return OPCODE_ILL_N;
10056               break;
10057             }
10058           break;
10059         }
10060       break;
10061     }
10062   return 0;
10063 }
10064
10065 static int
10066 Slot_inst16a_decode (const xtensa_insnbuf insn)
10067 {
10068   switch (Field_op0_Slot_inst16a_get (insn))
10069     {
10070     case 8:
10071       return OPCODE_L32I_N;
10072     case 9:
10073       return OPCODE_S32I_N;
10074     case 10:
10075       return OPCODE_ADD_N;
10076     case 11:
10077       return OPCODE_ADDI_N;
10078     }
10079   return 0;
10080 }
10081
10082 \f
10083 /* Instruction slots.  */
10084
10085 static void
10086 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
10087                             xtensa_insnbuf slotbuf)
10088 {
10089   slotbuf[0] = (insn[0] & 0xffffff);
10090 }
10091
10092 static void
10093 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
10094                             const xtensa_insnbuf slotbuf)
10095 {
10096   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
10097 }
10098
10099 static void
10100 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
10101                                 xtensa_insnbuf slotbuf)
10102 {
10103   slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
10104 }
10105
10106 static void
10107 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
10108                                 const xtensa_insnbuf slotbuf)
10109 {
10110   insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
10111 }
10112
10113 static void
10114 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
10115                                 xtensa_insnbuf slotbuf)
10116 {
10117   slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
10118 }
10119
10120 static void
10121 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
10122                                 const xtensa_insnbuf slotbuf)
10123 {
10124   insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
10125 }
10126
10127 static xtensa_get_field_fn
10128 Slot_inst_get_field_fns[] = {
10129   Field_t_Slot_inst_get,
10130   Field_bbi4_Slot_inst_get,
10131   Field_bbi_Slot_inst_get,
10132   Field_imm12_Slot_inst_get,
10133   Field_imm8_Slot_inst_get,
10134   Field_s_Slot_inst_get,
10135   Field_imm12b_Slot_inst_get,
10136   Field_imm16_Slot_inst_get,
10137   Field_m_Slot_inst_get,
10138   Field_n_Slot_inst_get,
10139   Field_offset_Slot_inst_get,
10140   Field_op0_Slot_inst_get,
10141   Field_op1_Slot_inst_get,
10142   Field_op2_Slot_inst_get,
10143   Field_r_Slot_inst_get,
10144   Field_sa4_Slot_inst_get,
10145   Field_sae4_Slot_inst_get,
10146   Field_sae_Slot_inst_get,
10147   Field_sal_Slot_inst_get,
10148   Field_sargt_Slot_inst_get,
10149   Field_sas4_Slot_inst_get,
10150   Field_sas_Slot_inst_get,
10151   Field_sr_Slot_inst_get,
10152   Field_st_Slot_inst_get,
10153   Field_thi3_Slot_inst_get,
10154   Field_imm4_Slot_inst_get,
10155   Field_mn_Slot_inst_get,
10156   0,
10157   0,
10158   0,
10159   0,
10160   0,
10161   0,
10162   0,
10163   0,
10164   Implicit_Field_ar0_get,
10165   Implicit_Field_ar4_get,
10166   Implicit_Field_ar8_get,
10167   Implicit_Field_ar12_get
10168 };
10169
10170 static xtensa_set_field_fn
10171 Slot_inst_set_field_fns[] = {
10172   Field_t_Slot_inst_set,
10173   Field_bbi4_Slot_inst_set,
10174   Field_bbi_Slot_inst_set,
10175   Field_imm12_Slot_inst_set,
10176   Field_imm8_Slot_inst_set,
10177   Field_s_Slot_inst_set,
10178   Field_imm12b_Slot_inst_set,
10179   Field_imm16_Slot_inst_set,
10180   Field_m_Slot_inst_set,
10181   Field_n_Slot_inst_set,
10182   Field_offset_Slot_inst_set,
10183   Field_op0_Slot_inst_set,
10184   Field_op1_Slot_inst_set,
10185   Field_op2_Slot_inst_set,
10186   Field_r_Slot_inst_set,
10187   Field_sa4_Slot_inst_set,
10188   Field_sae4_Slot_inst_set,
10189   Field_sae_Slot_inst_set,
10190   Field_sal_Slot_inst_set,
10191   Field_sargt_Slot_inst_set,
10192   Field_sas4_Slot_inst_set,
10193   Field_sas_Slot_inst_set,
10194   Field_sr_Slot_inst_set,
10195   Field_st_Slot_inst_set,
10196   Field_thi3_Slot_inst_set,
10197   Field_imm4_Slot_inst_set,
10198   Field_mn_Slot_inst_set,
10199   0,
10200   0,
10201   0,
10202   0,
10203   0,
10204   0,
10205   0,
10206   0,
10207   Implicit_Field_set,
10208   Implicit_Field_set,
10209   Implicit_Field_set,
10210   Implicit_Field_set
10211 };
10212
10213 static xtensa_get_field_fn
10214 Slot_inst16a_get_field_fns[] = {
10215   Field_t_Slot_inst16a_get,
10216   0,
10217   0,
10218   0,
10219   0,
10220   Field_s_Slot_inst16a_get,
10221   0,
10222   0,
10223   0,
10224   0,
10225   0,
10226   Field_op0_Slot_inst16a_get,
10227   0,
10228   0,
10229   Field_r_Slot_inst16a_get,
10230   0,
10231   0,
10232   0,
10233   0,
10234   0,
10235   0,
10236   0,
10237   Field_sr_Slot_inst16a_get,
10238   Field_st_Slot_inst16a_get,
10239   0,
10240   Field_imm4_Slot_inst16a_get,
10241   0,
10242   Field_i_Slot_inst16a_get,
10243   Field_imm6lo_Slot_inst16a_get,
10244   Field_imm6hi_Slot_inst16a_get,
10245   Field_imm7lo_Slot_inst16a_get,
10246   Field_imm7hi_Slot_inst16a_get,
10247   Field_z_Slot_inst16a_get,
10248   Field_imm6_Slot_inst16a_get,
10249   Field_imm7_Slot_inst16a_get,
10250   Implicit_Field_ar0_get,
10251   Implicit_Field_ar4_get,
10252   Implicit_Field_ar8_get,
10253   Implicit_Field_ar12_get
10254 };
10255
10256 static xtensa_set_field_fn
10257 Slot_inst16a_set_field_fns[] = {
10258   Field_t_Slot_inst16a_set,
10259   0,
10260   0,
10261   0,
10262   0,
10263   Field_s_Slot_inst16a_set,
10264   0,
10265   0,
10266   0,
10267   0,
10268   0,
10269   Field_op0_Slot_inst16a_set,
10270   0,
10271   0,
10272   Field_r_Slot_inst16a_set,
10273   0,
10274   0,
10275   0,
10276   0,
10277   0,
10278   0,
10279   0,
10280   Field_sr_Slot_inst16a_set,
10281   Field_st_Slot_inst16a_set,
10282   0,
10283   Field_imm4_Slot_inst16a_set,
10284   0,
10285   Field_i_Slot_inst16a_set,
10286   Field_imm6lo_Slot_inst16a_set,
10287   Field_imm6hi_Slot_inst16a_set,
10288   Field_imm7lo_Slot_inst16a_set,
10289   Field_imm7hi_Slot_inst16a_set,
10290   Field_z_Slot_inst16a_set,
10291   Field_imm6_Slot_inst16a_set,
10292   Field_imm7_Slot_inst16a_set,
10293   Implicit_Field_set,
10294   Implicit_Field_set,
10295   Implicit_Field_set,
10296   Implicit_Field_set
10297 };
10298
10299 static xtensa_get_field_fn
10300 Slot_inst16b_get_field_fns[] = {
10301   Field_t_Slot_inst16b_get,
10302   0,
10303   0,
10304   0,
10305   0,
10306   Field_s_Slot_inst16b_get,
10307   0,
10308   0,
10309   0,
10310   0,
10311   0,
10312   Field_op0_Slot_inst16b_get,
10313   0,
10314   0,
10315   Field_r_Slot_inst16b_get,
10316   0,
10317   0,
10318   0,
10319   0,
10320   0,
10321   0,
10322   0,
10323   Field_sr_Slot_inst16b_get,
10324   Field_st_Slot_inst16b_get,
10325   0,
10326   Field_imm4_Slot_inst16b_get,
10327   0,
10328   Field_i_Slot_inst16b_get,
10329   Field_imm6lo_Slot_inst16b_get,
10330   Field_imm6hi_Slot_inst16b_get,
10331   Field_imm7lo_Slot_inst16b_get,
10332   Field_imm7hi_Slot_inst16b_get,
10333   Field_z_Slot_inst16b_get,
10334   Field_imm6_Slot_inst16b_get,
10335   Field_imm7_Slot_inst16b_get,
10336   Implicit_Field_ar0_get,
10337   Implicit_Field_ar4_get,
10338   Implicit_Field_ar8_get,
10339   Implicit_Field_ar12_get
10340 };
10341
10342 static xtensa_set_field_fn
10343 Slot_inst16b_set_field_fns[] = {
10344   Field_t_Slot_inst16b_set,
10345   0,
10346   0,
10347   0,
10348   0,
10349   Field_s_Slot_inst16b_set,
10350   0,
10351   0,
10352   0,
10353   0,
10354   0,
10355   Field_op0_Slot_inst16b_set,
10356   0,
10357   0,
10358   Field_r_Slot_inst16b_set,
10359   0,
10360   0,
10361   0,
10362   0,
10363   0,
10364   0,
10365   0,
10366   Field_sr_Slot_inst16b_set,
10367   Field_st_Slot_inst16b_set,
10368   0,
10369   Field_imm4_Slot_inst16b_set,
10370   0,
10371   Field_i_Slot_inst16b_set,
10372   Field_imm6lo_Slot_inst16b_set,
10373   Field_imm6hi_Slot_inst16b_set,
10374   Field_imm7lo_Slot_inst16b_set,
10375   Field_imm7hi_Slot_inst16b_set,
10376   Field_z_Slot_inst16b_set,
10377   Field_imm6_Slot_inst16b_set,
10378   Field_imm7_Slot_inst16b_set,
10379   Implicit_Field_set,
10380   Implicit_Field_set,
10381   Implicit_Field_set,
10382   Implicit_Field_set
10383 };
10384
10385 static xtensa_slot_internal slots[] = {
10386   { "Inst", "x24", 0,
10387     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
10388     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
10389     Slot_inst_decode, "nop" },
10390   { "Inst16a", "x16a", 0,
10391     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
10392     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
10393     Slot_inst16a_decode, "" },
10394   { "Inst16b", "x16b", 0,
10395     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
10396     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
10397     Slot_inst16b_decode, "nop.n" }
10398 };
10399
10400 \f
10401 /* Instruction formats.  */
10402
10403 static void
10404 Format_x24_encode (xtensa_insnbuf insn)
10405 {
10406   insn[0] = 0;
10407 }
10408
10409 static void
10410 Format_x16a_encode (xtensa_insnbuf insn)
10411 {
10412   insn[0] = 0x800000;
10413 }
10414
10415 static void
10416 Format_x16b_encode (xtensa_insnbuf insn)
10417 {
10418   insn[0] = 0xc00000;
10419 }
10420
10421 static int Format_x24_slots[] = { 0 };
10422
10423 static int Format_x16a_slots[] = { 1 };
10424
10425 static int Format_x16b_slots[] = { 2 };
10426
10427 static xtensa_format_internal formats[] = {
10428   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
10429   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
10430   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
10431 };
10432
10433
10434 static int
10435 format_decoder (const xtensa_insnbuf insn)
10436 {
10437   if ((insn[0] & 0x800000) == 0)
10438     return 0; /* x24 */
10439   if ((insn[0] & 0xc00000) == 0x800000)
10440     return 1; /* x16a */
10441   if ((insn[0] & 0xe00000) == 0xc00000)
10442     return 2; /* x16b */
10443   return -1;
10444 }
10445
10446 static int length_table[16] = {
10447   3,
10448   3,
10449   3,
10450   3,
10451   3,
10452   3,
10453   3,
10454   3,
10455   2,
10456   2,
10457   2,
10458   2,
10459   2,
10460   2,
10461   -1,
10462   -1
10463 };
10464
10465 static int
10466 length_decoder (const unsigned char *insn)
10467 {
10468   int op0 = (insn[0] >> 4) & 0xf;
10469   return length_table[op0];
10470 }
10471
10472 \f
10473 /* Top-level ISA structure.  */
10474
10475 xtensa_isa_internal xtensa_modules = {
10476   1 /* big-endian */,
10477   3 /* insn_size */, 0,
10478   3, formats, format_decoder, length_decoder,
10479   3, slots,
10480   39 /* num_fields */,
10481   70, operands,
10482   235, iclasses,
10483   291, opcodes, 0,
10484   1, regfiles,
10485   NUM_STATES, states, 0,
10486   NUM_SYSREGS, sysregs, 0,
10487   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
10488   0, interfaces, 0,
10489   0, funcUnits, 0
10490 };