bfd/xtensa-modules.c

   1 /* Xtensa configuration-specific ISA information.
   2    Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
   3
   4    This file is part of BFD, the Binary File Descriptor library.
   5
   6    This program is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU General Public License as
   8    published by the Free Software Foundation; either version 3 of the
   9    License, or (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "ansidecl.h"
  22 #include <xtensa-isa.h>
  23 #include "xtensa-isa-internal.h"
  24
  25 \f
  26 /* Sysregs.  */
  27
  28 static xtensa_sysreg_internal sysregs[] = {
  29   { "LBEG", 0, 0 },
  30   { "LEND", 1, 0 },
  31   { "LCOUNT", 2, 0 },
  32   { "PTEVADDR", 83, 0 },
  33   { "MMID", 89, 0 },
  34   { "DDR", 104, 0 },
  35   { "176", 176, 0 },
  36   { "208", 208, 0 },
  37   { "INTERRUPT", 226, 0 },
  38   { "INTCLEAR", 227, 0 },
  39   { "CCOUNT", 234, 0 },
  40   { "PRID", 235, 0 },
  41   { "ICOUNT", 236, 0 },
  42   { "CCOMPARE0", 240, 0 },
  43   { "CCOMPARE1", 241, 0 },
  44   { "CCOMPARE2", 242, 0 },
  45   { "VECBASE", 231, 0 },
  46   { "EPC1", 177, 0 },
  47   { "EPC2", 178, 0 },
  48   { "EPC3", 179, 0 },
  49   { "EPC4", 180, 0 },
  50   { "EPC5", 181, 0 },
  51   { "EPC6", 182, 0 },
  52   { "EPC7", 183, 0 },
  53   { "EXCSAVE1", 209, 0 },
  54   { "EXCSAVE2", 210, 0 },
  55   { "EXCSAVE3", 211, 0 },
  56   { "EXCSAVE4", 212, 0 },
  57   { "EXCSAVE5", 213, 0 },
  58   { "EXCSAVE6", 214, 0 },
  59   { "EXCSAVE7", 215, 0 },
  60   { "EPS2", 194, 0 },
  61   { "EPS3", 195, 0 },
  62   { "EPS4", 196, 0 },
  63   { "EPS5", 197, 0 },
  64   { "EPS6", 198, 0 },
  65   { "EPS7", 199, 0 },
  66   { "EXCCAUSE", 232, 0 },
  67   { "DEPC", 192, 0 },
  68   { "EXCVADDR", 238, 0 },
  69   { "WINDOWBASE", 72, 0 },
  70   { "WINDOWSTART", 73, 0 },
  71   { "SAR", 3, 0 },
  72   { "LITBASE", 5, 0 },
  73   { "PS", 230, 0 },
  74   { "MISC0", 244, 0 },
  75   { "MISC1", 245, 0 },
  76   { "INTENABLE", 228, 0 },
  77   { "DBREAKA0", 144, 0 },
  78   { "DBREAKC0", 160, 0 },
  79   { "DBREAKA1", 145, 0 },
  80   { "DBREAKC1", 161, 0 },
  81   { "IBREAKA0", 128, 0 },
  82   { "IBREAKA1", 129, 0 },
  83   { "IBREAKENABLE", 96, 0 },
  84   { "ICOUNTLEVEL", 237, 0 },
  85   { "DEBUGCAUSE", 233, 0 },
  86   { "RASID", 90, 0 },
  87   { "ITLBCFG", 91, 0 },
  88   { "DTLBCFG", 92, 0 },
  89   { "CPENABLE", 224, 0 },
  90   { "SCOMPARE1", 12, 0 },
  91   { "THREADPTR", 231, 1 }
  92 };
  93
  94 #define NUM_SYSREGS 63
  95 #define MAX_SPECIAL_REG 245
  96 #define MAX_USER_REG 231
  97
  98 \f
  99 /* Processor states.  */
 100
 101 static xtensa_state_internal states[] = {
 102   { "LCOUNT", 32, 0 },
 103   { "PC", 32, 0 },
 104   { "ICOUNT", 32, 0 },
 105   { "DDR", 32, 0 },
 106   { "INTERRUPT", 22, 0 },
 107   { "CCOUNT", 32, 0 },
 108   { "XTSYNC", 1, 0 },
 109   { "VECBASE", 22, 0 },
 110   { "EPC1", 32, 0 },
 111   { "EPC2", 32, 0 },
 112   { "EPC3", 32, 0 },
 113   { "EPC4", 32, 0 },
 114   { "EPC5", 32, 0 },
 115   { "EPC6", 32, 0 },
 116   { "EPC7", 32, 0 },
 117   { "EXCSAVE1", 32, 0 },
 118   { "EXCSAVE2", 32, 0 },
 119   { "EXCSAVE3", 32, 0 },
 120   { "EXCSAVE4", 32, 0 },
 121   { "EXCSAVE5", 32, 0 },
 122   { "EXCSAVE6", 32, 0 },
 123   { "EXCSAVE7", 32, 0 },
 124   { "EPS2", 15, 0 },
 125   { "EPS3", 15, 0 },
 126   { "EPS4", 15, 0 },
 127   { "EPS5", 15, 0 },
 128   { "EPS6", 15, 0 },
 129   { "EPS7", 15, 0 },
 130   { "EXCCAUSE", 6, 0 },
 131   { "PSINTLEVEL", 4, 0 },
 132   { "PSUM", 1, 0 },
 133   { "PSWOE", 1, 0 },
 134   { "PSRING", 2, 0 },
 135   { "PSEXCM", 1, 0 },
 136   { "DEPC", 32, 0 },
 137   { "EXCVADDR", 32, 0 },
 138   { "WindowBase", 3, 0 },
 139   { "WindowStart", 8, 0 },
 140   { "PSCALLINC", 2, 0 },
 141   { "PSOWB", 4, 0 },
 142   { "LBEG", 32, 0 },
 143   { "LEND", 32, 0 },
 144   { "SAR", 6, 0 },
 145   { "THREADPTR", 32, 0 },
 146   { "LITBADDR", 20, 0 },
 147   { "LITBEN", 1, 0 },
 148   { "MISC0", 32, 0 },
 149   { "MISC1", 32, 0 },
 150   { "InOCDMode", 1, 0 },
 151   { "INTENABLE", 22, 0 },
 152   { "DBREAKA0", 32, 0 },
 153   { "DBREAKC0", 8, 0 },
 154   { "DBREAKA1", 32, 0 },
 155   { "DBREAKC1", 8, 0 },
 156   { "IBREAKA0", 32, 0 },
 157   { "IBREAKA1", 32, 0 },
 158   { "IBREAKENABLE", 2, 0 },
 159   { "ICOUNTLEVEL", 4, 0 },
 160   { "DEBUGCAUSE", 6, 0 },
 161   { "DBNUM", 4, 0 },
 162   { "CCOMPARE0", 32, 0 },
 163   { "CCOMPARE1", 32, 0 },
 164   { "CCOMPARE2", 32, 0 },
 165   { "ASID3", 8, 0 },
 166   { "ASID2", 8, 0 },
 167   { "ASID1", 8, 0 },
 168   { "INSTPGSZID4", 2, 0 },
 169   { "DATAPGSZID4", 2, 0 },
 170   { "PTBASE", 10, 0 },
 171   { "CPENABLE", 8, 0 },
 172   { "SCOMPARE1", 32, 0 }
 173 };
 174
 175 #define NUM_STATES 71
 176
 177 enum xtensa_state_id {
 178   STATE_LCOUNT,
 179   STATE_PC,
 180   STATE_ICOUNT,
 181   STATE_DDR,
 182   STATE_INTERRUPT,
 183   STATE_CCOUNT,
 184   STATE_XTSYNC,
 185   STATE_VECBASE,
 186   STATE_EPC1,
 187   STATE_EPC2,
 188   STATE_EPC3,
 189   STATE_EPC4,
 190   STATE_EPC5,
 191   STATE_EPC6,
 192   STATE_EPC7,
 193   STATE_EXCSAVE1,
 194   STATE_EXCSAVE2,
 195   STATE_EXCSAVE3,
 196   STATE_EXCSAVE4,
 197   STATE_EXCSAVE5,
 198   STATE_EXCSAVE6,
 199   STATE_EXCSAVE7,
 200   STATE_EPS2,
 201   STATE_EPS3,
 202   STATE_EPS4,
 203   STATE_EPS5,
 204   STATE_EPS6,
 205   STATE_EPS7,
 206   STATE_EXCCAUSE,
 207   STATE_PSINTLEVEL,
 208   STATE_PSUM,
 209   STATE_PSWOE,
 210   STATE_PSRING,
 211   STATE_PSEXCM,
 212   STATE_DEPC,
 213   STATE_EXCVADDR,
 214   STATE_WindowBase,
 215   STATE_WindowStart,
 216   STATE_PSCALLINC,
 217   STATE_PSOWB,
 218   STATE_LBEG,
 219   STATE_LEND,
 220   STATE_SAR,
 221   STATE_THREADPTR,
 222   STATE_LITBADDR,
 223   STATE_LITBEN,
 224   STATE_MISC0,
 225   STATE_MISC1,
 226   STATE_InOCDMode,
 227   STATE_INTENABLE,
 228   STATE_DBREAKA0,
 229   STATE_DBREAKC0,
 230   STATE_DBREAKA1,
 231   STATE_DBREAKC1,
 232   STATE_IBREAKA0,
 233   STATE_IBREAKA1,
 234   STATE_IBREAKENABLE,
 235   STATE_ICOUNTLEVEL,
 236   STATE_DEBUGCAUSE,
 237   STATE_DBNUM,
 238   STATE_CCOMPARE0,
 239   STATE_CCOMPARE1,
 240   STATE_CCOMPARE2,
 241   STATE_ASID3,
 242   STATE_ASID2,
 243   STATE_ASID1,
 244   STATE_INSTPGSZID4,
 245   STATE_DATAPGSZID4,
 246   STATE_PTBASE,
 247   STATE_CPENABLE,
 248   STATE_SCOMPARE1
 249 };
 250
 251 \f
 252 /* Field definitions.  */
 253
 254 static unsigned
 255 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 256 {
 257   unsigned tie_t = 0;
 258   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 259   return tie_t;
 260 }
 261
 262 static void
 263 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 264 {
 265   uint32 tie_t;
 266   tie_t = (val << 28) >> 28;
 267   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 268 }
 269
 270 static unsigned
 271 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 272 {
 273   unsigned tie_t = 0;
 274   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 275   return tie_t;
 276 }
 277
 278 static void
 279 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 280 {
 281   uint32 tie_t;
 282   tie_t = (val << 28) >> 28;
 283   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 284 }
 285
 286 static unsigned
 287 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 288 {
 289   unsigned tie_t = 0;
 290   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 291   return tie_t;
 292 }
 293
 294 static void
 295 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 296 {
 297   uint32 tie_t;
 298   tie_t = (val << 28) >> 28;
 299   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 300 }
 301
 302 static unsigned
 303 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 304 {
 305   unsigned tie_t = 0;
 306   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 307   return tie_t;
 308 }
 309
 310 static void
 311 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 312 {
 313   uint32 tie_t;
 314   tie_t = (val << 31) >> 31;
 315   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 316 }
 317
 318 static unsigned
 319 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 320 {
 321   unsigned tie_t = 0;
 322   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
 323   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 324   return tie_t;
 325 }
 326
 327 static void
 328 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 329 {
 330   uint32 tie_t;
 331   tie_t = (val << 28) >> 28;
 332   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 333   tie_t = (val << 27) >> 31;
 334   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
 335 }
 336
 337 static unsigned
 338 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 339 {
 340   unsigned tie_t = 0;
 341   tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
 342   return tie_t;
 343 }
 344
 345 static void
 346 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 347 {
 348   uint32 tie_t;
 349   tie_t = (val << 20) >> 20;
 350   insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
 351 }
 352
 353 static unsigned
 354 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 355 {
 356   unsigned tie_t = 0;
 357   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 358   return tie_t;
 359 }
 360
 361 static void
 362 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 363 {
 364   uint32 tie_t;
 365   tie_t = (val << 24) >> 24;
 366   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 367 }
 368
 369 static unsigned
 370 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 371 {
 372   unsigned tie_t = 0;
 373   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 374   return tie_t;
 375 }
 376
 377 static void
 378 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 379 {
 380   uint32 tie_t;
 381   tie_t = (val << 28) >> 28;
 382   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 383 }
 384
 385 static unsigned
 386 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 387 {
 388   unsigned tie_t = 0;
 389   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 390   return tie_t;
 391 }
 392
 393 static void
 394 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 395 {
 396   uint32 tie_t;
 397   tie_t = (val << 28) >> 28;
 398   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 399 }
 400
 401 static unsigned
 402 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 403 {
 404   unsigned tie_t = 0;
 405   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 406   return tie_t;
 407 }
 408
 409 static void
 410 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 411 {
 412   uint32 tie_t;
 413   tie_t = (val << 28) >> 28;
 414   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 415 }
 416
 417 static unsigned
 418 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 419 {
 420   unsigned tie_t = 0;
 421   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 422   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
 423   return tie_t;
 424 }
 425
 426 static void
 427 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 428 {
 429   uint32 tie_t;
 430   tie_t = (val << 24) >> 24;
 431   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
 432   tie_t = (val << 20) >> 28;
 433   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 434 }
 435
 436 static unsigned
 437 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 438 {
 439   unsigned tie_t = 0;
 440   tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
 441   return tie_t;
 442 }
 443
 444 static void
 445 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 446 {
 447   uint32 tie_t;
 448   tie_t = (val << 16) >> 16;
 449   insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
 450 }
 451
 452 static unsigned
 453 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 454 {
 455   unsigned tie_t = 0;
 456   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 457   return tie_t;
 458 }
 459
 460 static void
 461 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 462 {
 463   uint32 tie_t;
 464   tie_t = (val << 30) >> 30;
 465   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 466 }
 467
 468 static unsigned
 469 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 470 {
 471   unsigned tie_t = 0;
 472   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 473   return tie_t;
 474 }
 475
 476 static void
 477 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 478 {
 479   uint32 tie_t;
 480   tie_t = (val << 30) >> 30;
 481   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 482 }
 483
 484 static unsigned
 485 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 486 {
 487   unsigned tie_t = 0;
 488   tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
 489   return tie_t;
 490 }
 491
 492 static void
 493 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 494 {
 495   uint32 tie_t;
 496   tie_t = (val << 14) >> 14;
 497   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
 498 }
 499
 500 static unsigned
 501 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 502 {
 503   unsigned tie_t = 0;
 504   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 505   return tie_t;
 506 }
 507
 508 static void
 509 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 510 {
 511   uint32 tie_t;
 512   tie_t = (val << 28) >> 28;
 513   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 514 }
 515
 516 static unsigned
 517 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 518 {
 519   unsigned tie_t = 0;
 520   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 521   return tie_t;
 522 }
 523
 524 static void
 525 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 526 {
 527   uint32 tie_t;
 528   tie_t = (val << 28) >> 28;
 529   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 530 }
 531
 532 static unsigned
 533 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 534 {
 535   unsigned tie_t = 0;
 536   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 537   return tie_t;
 538 }
 539
 540 static void
 541 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 542 {
 543   uint32 tie_t;
 544   tie_t = (val << 28) >> 28;
 545   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 546 }
 547
 548 static unsigned
 549 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 550 {
 551   unsigned tie_t = 0;
 552   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 553   return tie_t;
 554 }
 555
 556 static void
 557 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 558 {
 559   uint32 tie_t;
 560   tie_t = (val << 28) >> 28;
 561   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 562 }
 563
 564 static unsigned
 565 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 566 {
 567   unsigned tie_t = 0;
 568   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 569   return tie_t;
 570 }
 571
 572 static void
 573 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 574 {
 575   uint32 tie_t;
 576   tie_t = (val << 28) >> 28;
 577   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 578 }
 579
 580 static unsigned
 581 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 582 {
 583   unsigned tie_t = 0;
 584   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 585   return tie_t;
 586 }
 587
 588 static void
 589 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 590 {
 591   uint32 tie_t;
 592   tie_t = (val << 28) >> 28;
 593   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 594 }
 595
 596 static unsigned
 597 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 598 {
 599   unsigned tie_t = 0;
 600   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 601   return tie_t;
 602 }
 603
 604 static void
 605 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 606 {
 607   uint32 tie_t;
 608   tie_t = (val << 28) >> 28;
 609   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 610 }
 611
 612 static unsigned
 613 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 614 {
 615   unsigned tie_t = 0;
 616   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 617   return tie_t;
 618 }
 619
 620 static void
 621 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 622 {
 623   uint32 tie_t;
 624   tie_t = (val << 28) >> 28;
 625   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 626 }
 627
 628 static unsigned
 629 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 630 {
 631   unsigned tie_t = 0;
 632   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 633   return tie_t;
 634 }
 635
 636 static void
 637 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 638 {
 639   uint32 tie_t;
 640   tie_t = (val << 31) >> 31;
 641   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 642 }
 643
 644 static unsigned
 645 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 646 {
 647   unsigned tie_t = 0;
 648   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 649   return tie_t;
 650 }
 651
 652 static void
 653 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 654 {
 655   uint32 tie_t;
 656   tie_t = (val << 31) >> 31;
 657   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 658 }
 659
 660 static unsigned
 661 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
 662 {
 663   unsigned tie_t = 0;
 664   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 665   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 666   return tie_t;
 667 }
 668
 669 static void
 670 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 671 {
 672   uint32 tie_t;
 673   tie_t = (val << 28) >> 28;
 674   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 675   tie_t = (val << 27) >> 31;
 676   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 677 }
 678
 679 static unsigned
 680 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
 681 {
 682   unsigned tie_t = 0;
 683   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 684   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 685   return tie_t;
 686 }
 687
 688 static void
 689 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 690 {
 691   uint32 tie_t;
 692   tie_t = (val << 28) >> 28;
 693   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 694   tie_t = (val << 27) >> 31;
 695   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 696 }
 697
 698 static unsigned
 699 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
 700 {
 701   unsigned tie_t = 0;
 702   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
 703   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 704   return tie_t;
 705 }
 706
 707 static void
 708 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 709 {
 710   uint32 tie_t;
 711   tie_t = (val << 28) >> 28;
 712   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 713   tie_t = (val << 27) >> 31;
 714   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
 715 }
 716
 717 static unsigned
 718 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
 719 {
 720   unsigned tie_t = 0;
 721   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 722   return tie_t;
 723 }
 724
 725 static void
 726 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 727 {
 728   uint32 tie_t;
 729   tie_t = (val << 31) >> 31;
 730   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 731 }
 732
 733 static unsigned
 734 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
 735 {
 736   unsigned tie_t = 0;
 737   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 738   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 739   return tie_t;
 740 }
 741
 742 static void
 743 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 744 {
 745   uint32 tie_t;
 746   tie_t = (val << 28) >> 28;
 747   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 748   tie_t = (val << 27) >> 31;
 749   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 750 }
 751
 752 static unsigned
 753 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 754 {
 755   unsigned tie_t = 0;
 756   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 757   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 758   return tie_t;
 759 }
 760
 761 static void
 762 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 763 {
 764   uint32 tie_t;
 765   tie_t = (val << 28) >> 28;
 766   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 767   tie_t = (val << 24) >> 28;
 768   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 769 }
 770
 771 static unsigned
 772 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
 773 {
 774   unsigned tie_t = 0;
 775   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 776   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 777   return tie_t;
 778 }
 779
 780 static void
 781 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 782 {
 783   uint32 tie_t;
 784   tie_t = (val << 28) >> 28;
 785   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 786   tie_t = (val << 24) >> 28;
 787   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 788 }
 789
 790 static unsigned
 791 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
 792 {
 793   unsigned tie_t = 0;
 794   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 795   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 796   return tie_t;
 797 }
 798
 799 static void
 800 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 801 {
 802   uint32 tie_t;
 803   tie_t = (val << 28) >> 28;
 804   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 805   tie_t = (val << 24) >> 28;
 806   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 807 }
 808
 809 static unsigned
 810 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 811 {
 812   unsigned tie_t = 0;
 813   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 814   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 815   return tie_t;
 816 }
 817
 818 static void
 819 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 820 {
 821   uint32 tie_t;
 822   tie_t = (val << 28) >> 28;
 823   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 824   tie_t = (val << 24) >> 28;
 825   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 826 }
 827
 828 static unsigned
 829 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
 830 {
 831   unsigned tie_t = 0;
 832   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 833   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 834   return tie_t;
 835 }
 836
 837 static void
 838 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 839 {
 840   uint32 tie_t;
 841   tie_t = (val << 28) >> 28;
 842   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 843   tie_t = (val << 24) >> 28;
 844   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 845 }
 846
 847 static unsigned
 848 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
 849 {
 850   unsigned tie_t = 0;
 851   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 852   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 853   return tie_t;
 854 }
 855
 856 static void
 857 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 858 {
 859   uint32 tie_t;
 860   tie_t = (val << 28) >> 28;
 861   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 862   tie_t = (val << 24) >> 28;
 863   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 864 }
 865
 866 static unsigned
 867 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 868 {
 869   unsigned tie_t = 0;
 870   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
 871   return tie_t;
 872 }
 873
 874 static void
 875 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 876 {
 877   uint32 tie_t;
 878   tie_t = (val << 29) >> 29;
 879   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
 880 }
 881
 882 static unsigned
 883 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
 884 {
 885   unsigned tie_t = 0;
 886   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 887   return tie_t;
 888 }
 889
 890 static void
 891 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 892 {
 893   uint32 tie_t;
 894   tie_t = (val << 28) >> 28;
 895   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 896 }
 897
 898 static unsigned
 899 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
 900 {
 901   unsigned tie_t = 0;
 902   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 903   return tie_t;
 904 }
 905
 906 static void
 907 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 908 {
 909   uint32 tie_t;
 910   tie_t = (val << 28) >> 28;
 911   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 912 }
 913
 914 static unsigned
 915 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
 916 {
 917   unsigned tie_t = 0;
 918   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 919   return tie_t;
 920 }
 921
 922 static void
 923 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 924 {
 925   uint32 tie_t;
 926   tie_t = (val << 28) >> 28;
 927   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 928 }
 929
 930 static unsigned
 931 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
 932 {
 933   unsigned tie_t = 0;
 934   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
 935   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
 936   return tie_t;
 937 }
 938
 939 static void
 940 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 941 {
 942   uint32 tie_t;
 943   tie_t = (val << 30) >> 30;
 944   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
 945   tie_t = (val << 28) >> 30;
 946   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
 947 }
 948
 949 static unsigned
 950 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
 951 {
 952   unsigned tie_t = 0;
 953   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 954   return tie_t;
 955 }
 956
 957 static void
 958 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 959 {
 960   uint32 tie_t;
 961   tie_t = (val << 31) >> 31;
 962   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 963 }
 964
 965 static unsigned
 966 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 967 {
 968   unsigned tie_t = 0;
 969   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
 970   return tie_t;
 971 }
 972
 973 static void
 974 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 975 {
 976   uint32 tie_t;
 977   tie_t = (val << 31) >> 31;
 978   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
 979 }
 980
 981 static unsigned
 982 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
 983 {
 984   unsigned tie_t = 0;
 985   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 986   return tie_t;
 987 }
 988
 989 static void
 990 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 991 {
 992   uint32 tie_t;
 993   tie_t = (val << 28) >> 28;
 994   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 995 }
 996
 997 static unsigned
 998 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
 999 {
1000   unsigned tie_t = 0;
1001   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1002   return tie_t;
1003 }
1004
1005 static void
1006 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1007 {
1008   uint32 tie_t;
1009   tie_t = (val << 28) >> 28;
1010   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1011 }
1012
1013 static unsigned
1014 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1015 {
1016   unsigned tie_t = 0;
1017   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1018   return tie_t;
1019 }
1020
1021 static void
1022 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1023 {
1024   uint32 tie_t;
1025   tie_t = (val << 30) >> 30;
1026   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1027 }
1028
1029 static unsigned
1030 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1031 {
1032   unsigned tie_t = 0;
1033   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1034   return tie_t;
1035 }
1036
1037 static void
1038 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1039 {
1040   uint32 tie_t;
1041   tie_t = (val << 30) >> 30;
1042   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1043 }
1044
1045 static unsigned
1046 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1047 {
1048   unsigned tie_t = 0;
1049   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1050   return tie_t;
1051 }
1052
1053 static void
1054 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1055 {
1056   uint32 tie_t;
1057   tie_t = (val << 28) >> 28;
1058   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1059 }
1060
1061 static unsigned
1062 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1063 {
1064   unsigned tie_t = 0;
1065   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1066   return tie_t;
1067 }
1068
1069 static void
1070 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1071 {
1072   uint32 tie_t;
1073   tie_t = (val << 28) >> 28;
1074   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1075 }
1076
1077 static unsigned
1078 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1079 {
1080   unsigned tie_t = 0;
1081   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1082   return tie_t;
1083 }
1084
1085 static void
1086 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1087 {
1088   uint32 tie_t;
1089   tie_t = (val << 29) >> 29;
1090   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1091 }
1092
1093 static unsigned
1094 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1095 {
1096   unsigned tie_t = 0;
1097   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1098   return tie_t;
1099 }
1100
1101 static void
1102 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1103 {
1104   uint32 tie_t;
1105   tie_t = (val << 29) >> 29;
1106   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1107 }
1108
1109 static unsigned
1110 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1111 {
1112   unsigned tie_t = 0;
1113   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1114   return tie_t;
1115 }
1116
1117 static void
1118 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1119 {
1120   uint32 tie_t;
1121   tie_t = (val << 31) >> 31;
1122   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1123 }
1124
1125 static unsigned
1126 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1127 {
1128   unsigned tie_t = 0;
1129   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1130   return tie_t;
1131 }
1132
1133 static void
1134 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1135 {
1136   uint32 tie_t;
1137   tie_t = (val << 31) >> 31;
1138   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1139 }
1140
1141 static unsigned
1142 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1143 {
1144   unsigned tie_t = 0;
1145   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1146   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1147   return tie_t;
1148 }
1149
1150 static void
1151 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1152 {
1153   uint32 tie_t;
1154   tie_t = (val << 28) >> 28;
1155   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1156   tie_t = (val << 26) >> 30;
1157   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1158 }
1159
1160 static unsigned
1161 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1162 {
1163   unsigned tie_t = 0;
1164   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1165   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1166   return tie_t;
1167 }
1168
1169 static void
1170 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1171 {
1172   uint32 tie_t;
1173   tie_t = (val << 28) >> 28;
1174   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1175   tie_t = (val << 26) >> 30;
1176   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1177 }
1178
1179 static unsigned
1180 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1181 {
1182   unsigned tie_t = 0;
1183   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1184   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1185   return tie_t;
1186 }
1187
1188 static void
1189 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1190 {
1191   uint32 tie_t;
1192   tie_t = (val << 28) >> 28;
1193   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1194   tie_t = (val << 25) >> 29;
1195   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1196 }
1197
1198 static unsigned
1199 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1200 {
1201   unsigned tie_t = 0;
1202   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1203   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1204   return tie_t;
1205 }
1206
1207 static void
1208 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1209 {
1210   uint32 tie_t;
1211   tie_t = (val << 28) >> 28;
1212   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1213   tie_t = (val << 25) >> 29;
1214   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1215 }
1216
1217 static unsigned
1218 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1219 {
1220   unsigned tie_t = 0;
1221   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1222   return tie_t;
1223 }
1224
1225 static void
1226 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1227 {
1228   uint32 tie_t;
1229   tie_t = (val << 17) >> 17;
1230   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1231 }
1232
1233 static unsigned
1234 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1235 {
1236   unsigned tie_t = 0;
1237   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1238   return tie_t;
1239 }
1240
1241 static void
1242 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1243 {
1244   uint32 tie_t;
1245   tie_t = (val << 14) >> 14;
1246   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1247 }
1248
1249 static void
1250 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1251                     uint32 val ATTRIBUTE_UNUSED)
1252 {
1253   /* Do nothing.  */
1254 }
1255
1256 static unsigned
1257 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1258 {
1259   return 0;
1260 }
1261
1262 static unsigned
1263 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1264 {
1265   return 4;
1266 }
1267
1268 static unsigned
1269 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1270 {
1271   return 8;
1272 }
1273
1274 static unsigned
1275 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1276 {
1277   return 12;
1278 }
1279
1280 \f
1281 /* Functional units.  */
1282
1283 static xtensa_funcUnit_internal funcUnits[] = {
1284
1285 };
1286
1287 \f
1288 /* Register files.  */
1289
1290 static xtensa_regfile_internal regfiles[] = {
1291   { "AR", "a", 0, 32, 32 }
1292 };
1293
1294 \f
1295 /* Interfaces.  */
1296
1297 static xtensa_interface_internal interfaces[] = {
1298
1299 };
1300
1301 \f
1302 /* Constant tables.  */
1303
1304 /* constant table ai4c */
1305 static const unsigned CONST_TBL_ai4c_0[] = {
1306   0xffffffff,
1307   0x1,
1308   0x2,
1309   0x3,
1310   0x4,
1311   0x5,
1312   0x6,
1313   0x7,
1314   0x8,
1315   0x9,
1316   0xa,
1317   0xb,
1318   0xc,
1319   0xd,
1320   0xe,
1321   0xf,
1322   0
1323 };
1324
1325 /* constant table b4c */
1326 static const unsigned CONST_TBL_b4c_0[] = {
1327   0xffffffff,
1328   0x1,
1329   0x2,
1330   0x3,
1331   0x4,
1332   0x5,
1333   0x6,
1334   0x7,
1335   0x8,
1336   0xa,
1337   0xc,
1338   0x10,
1339   0x20,
1340   0x40,
1341   0x80,
1342   0x100,
1343   0
1344 };
1345
1346 /* constant table b4cu */
1347 static const unsigned CONST_TBL_b4cu_0[] = {
1348   0x8000,
1349   0x10000,
1350   0x2,
1351   0x3,
1352   0x4,
1353   0x5,
1354   0x6,
1355   0x7,
1356   0x8,
1357   0xa,
1358   0xc,
1359   0x10,
1360   0x20,
1361   0x40,
1362   0x80,
1363   0x100,
1364   0
1365 };
1366
1367 \f
1368 /* Instruction operands.  */
1369
1370 static int
1371 Operand_soffsetx4_decode (uint32 *valp)
1372 {
1373   unsigned soffsetx4_0, offset_0;
1374   offset_0 = *valp & 0x3ffff;
1375   soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1376   *valp = soffsetx4_0;
1377   return 0;
1378 }
1379
1380 static int
1381 Operand_soffsetx4_encode (uint32 *valp)
1382 {
1383   unsigned offset_0, soffsetx4_0;
1384   soffsetx4_0 = *valp;
1385   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1386   *valp = offset_0;
1387   return 0;
1388 }
1389
1390 static int
1391 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1392 {
1393   *valp -= (pc & ~0x3);
1394   return 0;
1395 }
1396
1397 static int
1398 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1399 {
1400   *valp += (pc & ~0x3);
1401   return 0;
1402 }
1403
1404 static int
1405 Operand_uimm12x8_decode (uint32 *valp)
1406 {
1407   unsigned uimm12x8_0, imm12_0;
1408   imm12_0 = *valp & 0xfff;
1409   uimm12x8_0 = imm12_0 << 3;
1410   *valp = uimm12x8_0;
1411   return 0;
1412 }
1413
1414 static int
1415 Operand_uimm12x8_encode (uint32 *valp)
1416 {
1417   unsigned imm12_0, uimm12x8_0;
1418   uimm12x8_0 = *valp;
1419   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1420   *valp = imm12_0;
1421   return 0;
1422 }
1423
1424 static int
1425 Operand_simm4_decode (uint32 *valp)
1426 {
1427   unsigned simm4_0, mn_0;
1428   mn_0 = *valp & 0xf;
1429   simm4_0 = ((int) mn_0 << 28) >> 28;
1430   *valp = simm4_0;
1431   return 0;
1432 }
1433
1434 static int
1435 Operand_simm4_encode (uint32 *valp)
1436 {
1437   unsigned mn_0, simm4_0;
1438   simm4_0 = *valp;
1439   mn_0 = (simm4_0 & 0xf);
1440   *valp = mn_0;
1441   return 0;
1442 }
1443
1444 static int
1445 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1446 {
1447   return 0;
1448 }
1449
1450 static int
1451 Operand_arr_encode (uint32 *valp)
1452 {
1453   int error;
1454   error = (*valp & ~0xf) != 0;
1455   return error;
1456 }
1457
1458 static int
1459 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1460 {
1461   return 0;
1462 }
1463
1464 static int
1465 Operand_ars_encode (uint32 *valp)
1466 {
1467   int error;
1468   error = (*valp & ~0xf) != 0;
1469   return error;
1470 }
1471
1472 static int
1473 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1474 {
1475   return 0;
1476 }
1477
1478 static int
1479 Operand_art_encode (uint32 *valp)
1480 {
1481   int error;
1482   error = (*valp & ~0xf) != 0;
1483   return error;
1484 }
1485
1486 static int
1487 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1488 {
1489   return 0;
1490 }
1491
1492 static int
1493 Operand_ar0_encode (uint32 *valp)
1494 {
1495   int error;
1496   error = (*valp & ~0x1f) != 0;
1497   return error;
1498 }
1499
1500 static int
1501 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1502 {
1503   return 0;
1504 }
1505
1506 static int
1507 Operand_ar4_encode (uint32 *valp)
1508 {
1509   int error;
1510   error = (*valp & ~0x1f) != 0;
1511   return error;
1512 }
1513
1514 static int
1515 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
1516 {
1517   return 0;
1518 }
1519
1520 static int
1521 Operand_ar8_encode (uint32 *valp)
1522 {
1523   int error;
1524   error = (*valp & ~0x1f) != 0;
1525   return error;
1526 }
1527
1528 static int
1529 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
1530 {
1531   return 0;
1532 }
1533
1534 static int
1535 Operand_ar12_encode (uint32 *valp)
1536 {
1537   int error;
1538   error = (*valp & ~0x1f) != 0;
1539   return error;
1540 }
1541
1542 static int
1543 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1544 {
1545   return 0;
1546 }
1547
1548 static int
1549 Operand_ars_entry_encode (uint32 *valp)
1550 {
1551   int error;
1552   error = (*valp & ~0x1f) != 0;
1553   return error;
1554 }
1555
1556 static int
1557 Operand_immrx4_decode (uint32 *valp)
1558 {
1559   unsigned immrx4_0, r_0;
1560   r_0 = *valp & 0xf;
1561   immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1562   *valp = immrx4_0;
1563   return 0;
1564 }
1565
1566 static int
1567 Operand_immrx4_encode (uint32 *valp)
1568 {
1569   unsigned r_0, immrx4_0;
1570   immrx4_0 = *valp;
1571   r_0 = ((immrx4_0 >> 2) & 0xf);
1572   *valp = r_0;
1573   return 0;
1574 }
1575
1576 static int
1577 Operand_lsi4x4_decode (uint32 *valp)
1578 {
1579   unsigned lsi4x4_0, r_0;
1580   r_0 = *valp & 0xf;
1581   lsi4x4_0 = r_0 << 2;
1582   *valp = lsi4x4_0;
1583   return 0;
1584 }
1585
1586 static int
1587 Operand_lsi4x4_encode (uint32 *valp)
1588 {
1589   unsigned r_0, lsi4x4_0;
1590   lsi4x4_0 = *valp;
1591   r_0 = ((lsi4x4_0 >> 2) & 0xf);
1592   *valp = r_0;
1593   return 0;
1594 }
1595
1596 static int
1597 Operand_simm7_decode (uint32 *valp)
1598 {
1599   unsigned simm7_0, imm7_0;
1600   imm7_0 = *valp & 0x7f;
1601   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1602   *valp = simm7_0;
1603   return 0;
1604 }
1605
1606 static int
1607 Operand_simm7_encode (uint32 *valp)
1608 {
1609   unsigned imm7_0, simm7_0;
1610   simm7_0 = *valp;
1611   imm7_0 = (simm7_0 & 0x7f);
1612   *valp = imm7_0;
1613   return 0;
1614 }
1615
1616 static int
1617 Operand_uimm6_decode (uint32 *valp)
1618 {
1619   unsigned uimm6_0, imm6_0;
1620   imm6_0 = *valp & 0x3f;
1621   uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1622   *valp = uimm6_0;
1623   return 0;
1624 }
1625
1626 static int
1627 Operand_uimm6_encode (uint32 *valp)
1628 {
1629   unsigned imm6_0, uimm6_0;
1630   uimm6_0 = *valp;
1631   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1632   *valp = imm6_0;
1633   return 0;
1634 }
1635
1636 static int
1637 Operand_uimm6_ator (uint32 *valp, uint32 pc)
1638 {
1639   *valp -= pc;
1640   return 0;
1641 }
1642
1643 static int
1644 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1645 {
1646   *valp += pc;
1647   return 0;
1648 }
1649
1650 static int
1651 Operand_ai4const_decode (uint32 *valp)
1652 {
1653   unsigned ai4const_0, t_0;
1654   t_0 = *valp & 0xf;
1655   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1656   *valp = ai4const_0;
1657   return 0;
1658 }
1659
1660 static int
1661 Operand_ai4const_encode (uint32 *valp)
1662 {
1663   unsigned t_0, ai4const_0;
1664   ai4const_0 = *valp;
1665   switch (ai4const_0)
1666     {
1667     case 0xffffffff: t_0 = 0; break;
1668     case 0x1: t_0 = 0x1; break;
1669     case 0x2: t_0 = 0x2; break;
1670     case 0x3: t_0 = 0x3; break;
1671     case 0x4: t_0 = 0x4; break;
1672     case 0x5: t_0 = 0x5; break;
1673     case 0x6: t_0 = 0x6; break;
1674     case 0x7: t_0 = 0x7; break;
1675     case 0x8: t_0 = 0x8; break;
1676     case 0x9: t_0 = 0x9; break;
1677     case 0xa: t_0 = 0xa; break;
1678     case 0xb: t_0 = 0xb; break;
1679     case 0xc: t_0 = 0xc; break;
1680     case 0xd: t_0 = 0xd; break;
1681     case 0xe: t_0 = 0xe; break;
1682     default: t_0 = 0xf; break;
1683     }
1684   *valp = t_0;
1685   return 0;
1686 }
1687
1688 static int
1689 Operand_b4const_decode (uint32 *valp)
1690 {
1691   unsigned b4const_0, r_0;
1692   r_0 = *valp & 0xf;
1693   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1694   *valp = b4const_0;
1695   return 0;
1696 }
1697
1698 static int
1699 Operand_b4const_encode (uint32 *valp)
1700 {
1701   unsigned r_0, b4const_0;
1702   b4const_0 = *valp;
1703   switch (b4const_0)
1704     {
1705     case 0xffffffff: r_0 = 0; break;
1706     case 0x1: r_0 = 0x1; break;
1707     case 0x2: r_0 = 0x2; break;
1708     case 0x3: r_0 = 0x3; break;
1709     case 0x4: r_0 = 0x4; break;
1710     case 0x5: r_0 = 0x5; break;
1711     case 0x6: r_0 = 0x6; break;
1712     case 0x7: r_0 = 0x7; break;
1713     case 0x8: r_0 = 0x8; break;
1714     case 0xa: r_0 = 0x9; break;
1715     case 0xc: r_0 = 0xa; break;
1716     case 0x10: r_0 = 0xb; break;
1717     case 0x20: r_0 = 0xc; break;
1718     case 0x40: r_0 = 0xd; break;
1719     case 0x80: r_0 = 0xe; break;
1720     default: r_0 = 0xf; break;
1721     }
1722   *valp = r_0;
1723   return 0;
1724 }
1725
1726 static int
1727 Operand_b4constu_decode (uint32 *valp)
1728 {
1729   unsigned b4constu_0, r_0;
1730   r_0 = *valp & 0xf;
1731   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1732   *valp = b4constu_0;
1733   return 0;
1734 }
1735
1736 static int
1737 Operand_b4constu_encode (uint32 *valp)
1738 {
1739   unsigned r_0, b4constu_0;
1740   b4constu_0 = *valp;
1741   switch (b4constu_0)
1742     {
1743     case 0x8000: r_0 = 0; break;
1744     case 0x10000: r_0 = 0x1; break;
1745     case 0x2: r_0 = 0x2; break;
1746     case 0x3: r_0 = 0x3; break;
1747     case 0x4: r_0 = 0x4; break;
1748     case 0x5: r_0 = 0x5; break;
1749     case 0x6: r_0 = 0x6; break;
1750     case 0x7: r_0 = 0x7; break;
1751     case 0x8: r_0 = 0x8; break;
1752     case 0xa: r_0 = 0x9; break;
1753     case 0xc: r_0 = 0xa; break;
1754     case 0x10: r_0 = 0xb; break;
1755     case 0x20: r_0 = 0xc; break;
1756     case 0x40: r_0 = 0xd; break;
1757     case 0x80: r_0 = 0xe; break;
1758     default: r_0 = 0xf; break;
1759     }
1760   *valp = r_0;
1761   return 0;
1762 }
1763
1764 static int
1765 Operand_uimm8_decode (uint32 *valp)
1766 {
1767   unsigned uimm8_0, imm8_0;
1768   imm8_0 = *valp & 0xff;
1769   uimm8_0 = imm8_0;
1770   *valp = uimm8_0;
1771   return 0;
1772 }
1773
1774 static int
1775 Operand_uimm8_encode (uint32 *valp)
1776 {
1777   unsigned imm8_0, uimm8_0;
1778   uimm8_0 = *valp;
1779   imm8_0 = (uimm8_0 & 0xff);
1780   *valp = imm8_0;
1781   return 0;
1782 }
1783
1784 static int
1785 Operand_uimm8x2_decode (uint32 *valp)
1786 {
1787   unsigned uimm8x2_0, imm8_0;
1788   imm8_0 = *valp & 0xff;
1789   uimm8x2_0 = imm8_0 << 1;
1790   *valp = uimm8x2_0;
1791   return 0;
1792 }
1793
1794 static int
1795 Operand_uimm8x2_encode (uint32 *valp)
1796 {
1797   unsigned imm8_0, uimm8x2_0;
1798   uimm8x2_0 = *valp;
1799   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1800   *valp = imm8_0;
1801   return 0;
1802 }
1803
1804 static int
1805 Operand_uimm8x4_decode (uint32 *valp)
1806 {
1807   unsigned uimm8x4_0, imm8_0;
1808   imm8_0 = *valp & 0xff;
1809   uimm8x4_0 = imm8_0 << 2;
1810   *valp = uimm8x4_0;
1811   return 0;
1812 }
1813
1814 static int
1815 Operand_uimm8x4_encode (uint32 *valp)
1816 {
1817   unsigned imm8_0, uimm8x4_0;
1818   uimm8x4_0 = *valp;
1819   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1820   *valp = imm8_0;
1821   return 0;
1822 }
1823
1824 static int
1825 Operand_uimm4x16_decode (uint32 *valp)
1826 {
1827   unsigned uimm4x16_0, op2_0;
1828   op2_0 = *valp & 0xf;
1829   uimm4x16_0 = op2_0 << 4;
1830   *valp = uimm4x16_0;
1831   return 0;
1832 }
1833
1834 static int
1835 Operand_uimm4x16_encode (uint32 *valp)
1836 {
1837   unsigned op2_0, uimm4x16_0;
1838   uimm4x16_0 = *valp;
1839   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1840   *valp = op2_0;
1841   return 0;
1842 }
1843
1844 static int
1845 Operand_simm8_decode (uint32 *valp)
1846 {
1847   unsigned simm8_0, imm8_0;
1848   imm8_0 = *valp & 0xff;
1849   simm8_0 = ((int) imm8_0 << 24) >> 24;
1850   *valp = simm8_0;
1851   return 0;
1852 }
1853
1854 static int
1855 Operand_simm8_encode (uint32 *valp)
1856 {
1857   unsigned imm8_0, simm8_0;
1858   simm8_0 = *valp;
1859   imm8_0 = (simm8_0 & 0xff);
1860   *valp = imm8_0;
1861   return 0;
1862 }
1863
1864 static int
1865 Operand_simm8x256_decode (uint32 *valp)
1866 {
1867   unsigned simm8x256_0, imm8_0;
1868   imm8_0 = *valp & 0xff;
1869   simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1870   *valp = simm8x256_0;
1871   return 0;
1872 }
1873
1874 static int
1875 Operand_simm8x256_encode (uint32 *valp)
1876 {
1877   unsigned imm8_0, simm8x256_0;
1878   simm8x256_0 = *valp;
1879   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1880   *valp = imm8_0;
1881   return 0;
1882 }
1883
1884 static int
1885 Operand_simm12b_decode (uint32 *valp)
1886 {
1887   unsigned simm12b_0, imm12b_0;
1888   imm12b_0 = *valp & 0xfff;
1889   simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1890   *valp = simm12b_0;
1891   return 0;
1892 }
1893
1894 static int
1895 Operand_simm12b_encode (uint32 *valp)
1896 {
1897   unsigned imm12b_0, simm12b_0;
1898   simm12b_0 = *valp;
1899   imm12b_0 = (simm12b_0 & 0xfff);
1900   *valp = imm12b_0;
1901   return 0;
1902 }
1903
1904 static int
1905 Operand_msalp32_decode (uint32 *valp)
1906 {
1907   unsigned msalp32_0, sal_0;
1908   sal_0 = *valp & 0x1f;
1909   msalp32_0 = 0x20 - sal_0;
1910   *valp = msalp32_0;
1911   return 0;
1912 }
1913
1914 static int
1915 Operand_msalp32_encode (uint32 *valp)
1916 {
1917   unsigned sal_0, msalp32_0;
1918   msalp32_0 = *valp;
1919   sal_0 = (0x20 - msalp32_0) & 0x1f;
1920   *valp = sal_0;
1921   return 0;
1922 }
1923
1924 static int
1925 Operand_op2p1_decode (uint32 *valp)
1926 {
1927   unsigned op2p1_0, op2_0;
1928   op2_0 = *valp & 0xf;
1929   op2p1_0 = op2_0 + 0x1;
1930   *valp = op2p1_0;
1931   return 0;
1932 }
1933
1934 static int
1935 Operand_op2p1_encode (uint32 *valp)
1936 {
1937   unsigned op2_0, op2p1_0;
1938   op2p1_0 = *valp;
1939   op2_0 = (op2p1_0 - 0x1) & 0xf;
1940   *valp = op2_0;
1941   return 0;
1942 }
1943
1944 static int
1945 Operand_label8_decode (uint32 *valp)
1946 {
1947   unsigned label8_0, imm8_0;
1948   imm8_0 = *valp & 0xff;
1949   label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1950   *valp = label8_0;
1951   return 0;
1952 }
1953
1954 static int
1955 Operand_label8_encode (uint32 *valp)
1956 {
1957   unsigned imm8_0, label8_0;
1958   label8_0 = *valp;
1959   imm8_0 = (label8_0 - 0x4) & 0xff;
1960   *valp = imm8_0;
1961   return 0;
1962 }
1963
1964 static int
1965 Operand_label8_ator (uint32 *valp, uint32 pc)
1966 {
1967   *valp -= pc;
1968   return 0;
1969 }
1970
1971 static int
1972 Operand_label8_rtoa (uint32 *valp, uint32 pc)
1973 {
1974   *valp += pc;
1975   return 0;
1976 }
1977
1978 static int
1979 Operand_ulabel8_decode (uint32 *valp)
1980 {
1981   unsigned ulabel8_0, imm8_0;
1982   imm8_0 = *valp & 0xff;
1983   ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
1984   *valp = ulabel8_0;
1985   return 0;
1986 }
1987
1988 static int
1989 Operand_ulabel8_encode (uint32 *valp)
1990 {
1991   unsigned imm8_0, ulabel8_0;
1992   ulabel8_0 = *valp;
1993   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
1994   *valp = imm8_0;
1995   return 0;
1996 }
1997
1998 static int
1999 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2000 {
2001   *valp -= pc;
2002   return 0;
2003 }
2004
2005 static int
2006 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2007 {
2008   *valp += pc;
2009   return 0;
2010 }
2011
2012 static int
2013 Operand_label12_decode (uint32 *valp)
2014 {
2015   unsigned label12_0, imm12_0;
2016   imm12_0 = *valp & 0xfff;
2017   label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2018   *valp = label12_0;
2019   return 0;
2020 }
2021
2022 static int
2023 Operand_label12_encode (uint32 *valp)
2024 {
2025   unsigned imm12_0, label12_0;
2026   label12_0 = *valp;
2027   imm12_0 = (label12_0 - 0x4) & 0xfff;
2028   *valp = imm12_0;
2029   return 0;
2030 }
2031
2032 static int
2033 Operand_label12_ator (uint32 *valp, uint32 pc)
2034 {
2035   *valp -= pc;
2036   return 0;
2037 }
2038
2039 static int
2040 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2041 {
2042   *valp += pc;
2043   return 0;
2044 }
2045
2046 static int
2047 Operand_soffset_decode (uint32 *valp)
2048 {
2049   unsigned soffset_0, offset_0;
2050   offset_0 = *valp & 0x3ffff;
2051   soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2052   *valp = soffset_0;
2053   return 0;
2054 }
2055
2056 static int
2057 Operand_soffset_encode (uint32 *valp)
2058 {
2059   unsigned offset_0, soffset_0;
2060   soffset_0 = *valp;
2061   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2062   *valp = offset_0;
2063   return 0;
2064 }
2065
2066 static int
2067 Operand_soffset_ator (uint32 *valp, uint32 pc)
2068 {
2069   *valp -= pc;
2070   return 0;
2071 }
2072
2073 static int
2074 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2075 {
2076   *valp += pc;
2077   return 0;
2078 }
2079
2080 static int
2081 Operand_uimm16x4_decode (uint32 *valp)
2082 {
2083   unsigned uimm16x4_0, imm16_0;
2084   imm16_0 = *valp & 0xffff;
2085   uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2086   *valp = uimm16x4_0;
2087   return 0;
2088 }
2089
2090 static int
2091 Operand_uimm16x4_encode (uint32 *valp)
2092 {
2093   unsigned imm16_0, uimm16x4_0;
2094   uimm16x4_0 = *valp;
2095   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2096   *valp = imm16_0;
2097   return 0;
2098 }
2099
2100 static int
2101 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2102 {
2103   *valp -= ((pc + 3) & ~0x3);
2104   return 0;
2105 }
2106
2107 static int
2108 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2109 {
2110   *valp += ((pc + 3) & ~0x3);
2111   return 0;
2112 }
2113
2114 static int
2115 Operand_immt_decode (uint32 *valp)
2116 {
2117   unsigned immt_0, t_0;
2118   t_0 = *valp & 0xf;
2119   immt_0 = t_0;
2120   *valp = immt_0;
2121   return 0;
2122 }
2123
2124 static int
2125 Operand_immt_encode (uint32 *valp)
2126 {
2127   unsigned t_0, immt_0;
2128   immt_0 = *valp;
2129   t_0 = immt_0 & 0xf;
2130   *valp = t_0;
2131   return 0;
2132 }
2133
2134 static int
2135 Operand_imms_decode (uint32 *valp)
2136 {
2137   unsigned imms_0, s_0;
2138   s_0 = *valp & 0xf;
2139   imms_0 = s_0;
2140   *valp = imms_0;
2141   return 0;
2142 }
2143
2144 static int
2145 Operand_imms_encode (uint32 *valp)
2146 {
2147   unsigned s_0, imms_0;
2148   imms_0 = *valp;
2149   s_0 = imms_0 & 0xf;
2150   *valp = s_0;
2151   return 0;
2152 }
2153
2154 static int
2155 Operand_tp7_decode (uint32 *valp)
2156 {
2157   unsigned tp7_0, t_0;
2158   t_0 = *valp & 0xf;
2159   tp7_0 = t_0 + 0x7;
2160   *valp = tp7_0;
2161   return 0;
2162 }
2163
2164 static int
2165 Operand_tp7_encode (uint32 *valp)
2166 {
2167   unsigned t_0, tp7_0;
2168   tp7_0 = *valp;
2169   t_0 = (tp7_0 - 0x7) & 0xf;
2170   *valp = t_0;
2171   return 0;
2172 }
2173
2174 static int
2175 Operand_xt_wbr15_label_decode (uint32 *valp)
2176 {
2177   unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
2178   xt_wbr15_imm_0 = *valp & 0x7fff;
2179   xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2180   *valp = xt_wbr15_label_0;
2181   return 0;
2182 }
2183
2184 static int
2185 Operand_xt_wbr15_label_encode (uint32 *valp)
2186 {
2187   unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
2188   xt_wbr15_label_0 = *valp;
2189   xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2190   *valp = xt_wbr15_imm_0;
2191   return 0;
2192 }
2193
2194 static int
2195 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2196 {
2197   *valp -= pc;
2198   return 0;
2199 }
2200
2201 static int
2202 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2203 {
2204   *valp += pc;
2205   return 0;
2206 }
2207
2208 static int
2209 Operand_xt_wbr18_label_decode (uint32 *valp)
2210 {
2211   unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
2212   xt_wbr18_imm_0 = *valp & 0x3ffff;
2213   xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2214   *valp = xt_wbr18_label_0;
2215   return 0;
2216 }
2217
2218 static int
2219 Operand_xt_wbr18_label_encode (uint32 *valp)
2220 {
2221   unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
2222   xt_wbr18_label_0 = *valp;
2223   xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2224   *valp = xt_wbr18_imm_0;
2225   return 0;
2226 }
2227
2228 static int
2229 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2230 {
2231   *valp -= pc;
2232   return 0;
2233 }
2234
2235 static int
2236 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2237 {
2238   *valp += pc;
2239   return 0;
2240 }
2241
2242 static xtensa_operand_internal operands[] = {
2243   { "soffsetx4", 10, -1, 0,
2244     XTENSA_OPERAND_IS_PCRELATIVE,
2245     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2246     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2247   { "uimm12x8", 3, -1, 0,
2248     0,
2249     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2250     0, 0 },
2251   { "simm4", 26, -1, 0,
2252     0,
2253     Operand_simm4_encode, Operand_simm4_decode,
2254     0, 0 },
2255   { "arr", 14, 0, 1,
2256     XTENSA_OPERAND_IS_REGISTER,
2257     Operand_arr_encode, Operand_arr_decode,
2258     0, 0 },
2259   { "ars", 5, 0, 1,
2260     XTENSA_OPERAND_IS_REGISTER,
2261     Operand_ars_encode, Operand_ars_decode,
2262     0, 0 },
2263   { "*ars_invisible", 5, 0, 1,
2264     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2265     Operand_ars_encode, Operand_ars_decode,
2266     0, 0 },
2267   { "art", 0, 0, 1,
2268     XTENSA_OPERAND_IS_REGISTER,
2269     Operand_art_encode, Operand_art_decode,
2270     0, 0 },
2271   { "ar0", 37, 0, 1,
2272     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2273     Operand_ar0_encode, Operand_ar0_decode,
2274     0, 0 },
2275   { "ar4", 38, 0, 1,
2276     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2277     Operand_ar4_encode, Operand_ar4_decode,
2278     0, 0 },
2279   { "ar8", 39, 0, 1,
2280     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2281     Operand_ar8_encode, Operand_ar8_decode,
2282     0, 0 },
2283   { "ar12", 40, 0, 1,
2284     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2285     Operand_ar12_encode, Operand_ar12_decode,
2286     0, 0 },
2287   { "ars_entry", 5, 0, 1,
2288     XTENSA_OPERAND_IS_REGISTER,
2289     Operand_ars_entry_encode, Operand_ars_entry_decode,
2290     0, 0 },
2291   { "immrx4", 14, -1, 0,
2292     0,
2293     Operand_immrx4_encode, Operand_immrx4_decode,
2294     0, 0 },
2295   { "lsi4x4", 14, -1, 0,
2296     0,
2297     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2298     0, 0 },
2299   { "simm7", 34, -1, 0,
2300     0,
2301     Operand_simm7_encode, Operand_simm7_decode,
2302     0, 0 },
2303   { "uimm6", 33, -1, 0,
2304     XTENSA_OPERAND_IS_PCRELATIVE,
2305     Operand_uimm6_encode, Operand_uimm6_decode,
2306     Operand_uimm6_ator, Operand_uimm6_rtoa },
2307   { "ai4const", 0, -1, 0,
2308     0,
2309     Operand_ai4const_encode, Operand_ai4const_decode,
2310     0, 0 },
2311   { "b4const", 14, -1, 0,
2312     0,
2313     Operand_b4const_encode, Operand_b4const_decode,
2314     0, 0 },
2315   { "b4constu", 14, -1, 0,
2316     0,
2317     Operand_b4constu_encode, Operand_b4constu_decode,
2318     0, 0 },
2319   { "uimm8", 4, -1, 0,
2320     0,
2321     Operand_uimm8_encode, Operand_uimm8_decode,
2322     0, 0 },
2323   { "uimm8x2", 4, -1, 0,
2324     0,
2325     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2326     0, 0 },
2327   { "uimm8x4", 4, -1, 0,
2328     0,
2329     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2330     0, 0 },
2331   { "uimm4x16", 13, -1, 0,
2332     0,
2333     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2334     0, 0 },
2335   { "simm8", 4, -1, 0,
2336     0,
2337     Operand_simm8_encode, Operand_simm8_decode,
2338     0, 0 },
2339   { "simm8x256", 4, -1, 0,
2340     0,
2341     Operand_simm8x256_encode, Operand_simm8x256_decode,
2342     0, 0 },
2343   { "simm12b", 6, -1, 0,
2344     0,
2345     Operand_simm12b_encode, Operand_simm12b_decode,
2346     0, 0 },
2347   { "msalp32", 18, -1, 0,
2348     0,
2349     Operand_msalp32_encode, Operand_msalp32_decode,
2350     0, 0 },
2351   { "op2p1", 13, -1, 0,
2352     0,
2353     Operand_op2p1_encode, Operand_op2p1_decode,
2354     0, 0 },
2355   { "label8", 4, -1, 0,
2356     XTENSA_OPERAND_IS_PCRELATIVE,
2357     Operand_label8_encode, Operand_label8_decode,
2358     Operand_label8_ator, Operand_label8_rtoa },
2359   { "ulabel8", 4, -1, 0,
2360     XTENSA_OPERAND_IS_PCRELATIVE,
2361     Operand_ulabel8_encode, Operand_ulabel8_decode,
2362     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2363   { "label12", 3, -1, 0,
2364     XTENSA_OPERAND_IS_PCRELATIVE,
2365     Operand_label12_encode, Operand_label12_decode,
2366     Operand_label12_ator, Operand_label12_rtoa },
2367   { "soffset", 10, -1, 0,
2368     XTENSA_OPERAND_IS_PCRELATIVE,
2369     Operand_soffset_encode, Operand_soffset_decode,
2370     Operand_soffset_ator, Operand_soffset_rtoa },
2371   { "uimm16x4", 7, -1, 0,
2372     XTENSA_OPERAND_IS_PCRELATIVE,
2373     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2374     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2375   { "immt", 0, -1, 0,
2376     0,
2377     Operand_immt_encode, Operand_immt_decode,
2378     0, 0 },
2379   { "imms", 5, -1, 0,
2380     0,
2381     Operand_imms_encode, Operand_imms_decode,
2382     0, 0 },
2383   { "tp7", 0, -1, 0,
2384     0,
2385     Operand_tp7_encode, Operand_tp7_decode,
2386     0, 0 },
2387   { "xt_wbr15_label", 35, -1, 0,
2388     XTENSA_OPERAND_IS_PCRELATIVE,
2389     Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2390     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2391   { "xt_wbr18_label", 36, -1, 0,
2392     XTENSA_OPERAND_IS_PCRELATIVE,
2393     Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2394     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2395   { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2396   { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2397   { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2398   { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2399   { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2400   { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2401   { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2402   { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2403   { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2404   { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2405   { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2406   { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2407   { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2408   { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2409   { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2410   { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2411   { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2412   { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2413   { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2414   { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2415   { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2416   { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2417   { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2418   { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2419   { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2420   { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2421   { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2422   { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2423   { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2424   { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2425   { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2426   { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2427   { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2428   { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2429   { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
2430   { "xt_wbr15_imm", 35, -1, 0, 0, 0, 0, 0, 0 },
2431   { "xt_wbr18_imm", 36, -1, 0, 0, 0, 0, 0, 0 }
2432 };
2433
2434 \f
2435 /* Iclass table.  */
2436
2437 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2438   { { STATE_PSRING }, 'i' },
2439   { { STATE_PSEXCM }, 'm' },
2440   { { STATE_EPC1 }, 'i' }
2441 };
2442
2443 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2444   { { STATE_PSEXCM }, 'i' },
2445   { { STATE_PSRING }, 'i' },
2446   { { STATE_DEPC }, 'i' }
2447 };
2448
2449 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
2450   { { 0 /* soffsetx4 */ }, 'i' },
2451   { { 10 /* ar12 */ }, 'o' }
2452 };
2453
2454 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2455   { { STATE_PSCALLINC }, 'o' }
2456 };
2457
2458 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
2459   { { 0 /* soffsetx4 */ }, 'i' },
2460   { { 9 /* ar8 */ }, 'o' }
2461 };
2462
2463 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2464   { { STATE_PSCALLINC }, 'o' }
2465 };
2466
2467 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
2468   { { 0 /* soffsetx4 */ }, 'i' },
2469   { { 8 /* ar4 */ }, 'o' }
2470 };
2471
2472 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2473   { { STATE_PSCALLINC }, 'o' }
2474 };
2475
2476 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
2477   { { 4 /* ars */ }, 'i' },
2478   { { 10 /* ar12 */ }, 'o' }
2479 };
2480
2481 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2482   { { STATE_PSCALLINC }, 'o' }
2483 };
2484
2485 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
2486   { { 4 /* ars */ }, 'i' },
2487   { { 9 /* ar8 */ }, 'o' }
2488 };
2489
2490 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2491   { { STATE_PSCALLINC }, 'o' }
2492 };
2493
2494 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
2495   { { 4 /* ars */ }, 'i' },
2496   { { 8 /* ar4 */ }, 'o' }
2497 };
2498
2499 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2500   { { STATE_PSCALLINC }, 'o' }
2501 };
2502
2503 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
2504   { { 11 /* ars_entry */ }, 's' },
2505   { { 4 /* ars */ }, 'i' },
2506   { { 1 /* uimm12x8 */ }, 'i' }
2507 };
2508
2509 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2510   { { STATE_PSCALLINC }, 'i' },
2511   { { STATE_PSEXCM }, 'i' },
2512   { { STATE_PSWOE }, 'i' },
2513   { { STATE_WindowBase }, 'm' },
2514   { { STATE_WindowStart }, 'm' }
2515 };
2516
2517 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
2518   { { 6 /* art */ }, 'o' },
2519   { { 4 /* ars */ }, 'i' }
2520 };
2521
2522 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2523   { { STATE_WindowBase }, 'i' },
2524   { { STATE_WindowStart }, 'i' }
2525 };
2526
2527 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
2528   { { 2 /* simm4 */ }, 'i' }
2529 };
2530
2531 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
2532   { { STATE_PSEXCM }, 'i' },
2533   { { STATE_PSRING }, 'i' },
2534   { { STATE_WindowBase }, 'm' }
2535 };
2536
2537 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
2538   { { 5 /* *ars_invisible */ }, 'i' }
2539 };
2540
2541 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2542   { { STATE_WindowBase }, 'm' },
2543   { { STATE_WindowStart }, 'm' },
2544   { { STATE_PSEXCM }, 'i' },
2545   { { STATE_PSWOE }, 'i' }
2546 };
2547
2548 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2549   { { STATE_EPC1 }, 'i' },
2550   { { STATE_PSEXCM }, 'm' },
2551   { { STATE_PSRING }, 'i' },
2552   { { STATE_WindowBase }, 'm' },
2553   { { STATE_WindowStart }, 'm' },
2554   { { STATE_PSOWB }, 'i' }
2555 };
2556
2557 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
2558   { { 6 /* art */ }, 'o' },
2559   { { 4 /* ars */ }, 'i' },
2560   { { 12 /* immrx4 */ }, 'i' }
2561 };
2562
2563 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2564   { { STATE_PSEXCM }, 'i' },
2565   { { STATE_PSRING }, 'i' }
2566 };
2567
2568 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
2569   { { 6 /* art */ }, 'i' },
2570   { { 4 /* ars */ }, 'i' },
2571   { { 12 /* immrx4 */ }, 'i' }
2572 };
2573
2574 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2575   { { STATE_PSEXCM }, 'i' },
2576   { { STATE_PSRING }, 'i' }
2577 };
2578
2579 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
2580   { { 6 /* art */ }, 'o' }
2581 };
2582
2583 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
2584   { { STATE_PSEXCM }, 'i' },
2585   { { STATE_PSRING }, 'i' },
2586   { { STATE_WindowBase }, 'i' }
2587 };
2588
2589 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
2590   { { 6 /* art */ }, 'i' }
2591 };
2592
2593 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
2594   { { STATE_PSEXCM }, 'i' },
2595   { { STATE_PSRING }, 'i' },
2596   { { STATE_WindowBase }, 'o' }
2597 };
2598
2599 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
2600   { { 6 /* art */ }, 'm' }
2601 };
2602
2603 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
2604   { { STATE_PSEXCM }, 'i' },
2605   { { STATE_PSRING }, 'i' },
2606   { { STATE_WindowBase }, 'm' }
2607 };
2608
2609 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
2610   { { 6 /* art */ }, 'o' }
2611 };
2612
2613 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
2614   { { STATE_PSEXCM }, 'i' },
2615   { { STATE_PSRING }, 'i' },
2616   { { STATE_WindowStart }, 'i' }
2617 };
2618
2619 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
2620   { { 6 /* art */ }, 'i' }
2621 };
2622
2623 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
2624   { { STATE_PSEXCM }, 'i' },
2625   { { STATE_PSRING }, 'i' },
2626   { { STATE_WindowStart }, 'o' }
2627 };
2628
2629 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
2630   { { 6 /* art */ }, 'm' }
2631 };
2632
2633 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
2634   { { STATE_PSEXCM }, 'i' },
2635   { { STATE_PSRING }, 'i' },
2636   { { STATE_WindowStart }, 'm' }
2637 };
2638
2639 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2640   { { 3 /* arr */ }, 'o' },
2641   { { 4 /* ars */ }, 'i' },
2642   { { 6 /* art */ }, 'i' }
2643 };
2644
2645 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2646   { { 3 /* arr */ }, 'o' },
2647   { { 4 /* ars */ }, 'i' },
2648   { { 16 /* ai4const */ }, 'i' }
2649 };
2650
2651 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2652   { { 4 /* ars */ }, 'i' },
2653   { { 15 /* uimm6 */ }, 'i' }
2654 };
2655
2656 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2657   { { 6 /* art */ }, 'o' },
2658   { { 4 /* ars */ }, 'i' },
2659   { { 13 /* lsi4x4 */ }, 'i' }
2660 };
2661
2662 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2663   { { 6 /* art */ }, 'o' },
2664   { { 4 /* ars */ }, 'i' }
2665 };
2666
2667 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2668   { { 4 /* ars */ }, 'o' },
2669   { { 14 /* simm7 */ }, 'i' }
2670 };
2671
2672 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2673   { { 5 /* *ars_invisible */ }, 'i' }
2674 };
2675
2676 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2677   { { 6 /* art */ }, 'i' },
2678   { { 4 /* ars */ }, 'i' },
2679   { { 13 /* lsi4x4 */ }, 'i' }
2680 };
2681
2682 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
2683   { { 3 /* arr */ }, 'o' }
2684 };
2685
2686 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
2687   { { STATE_THREADPTR }, 'i' }
2688 };
2689
2690 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
2691   { { 6 /* art */ }, 'i' }
2692 };
2693
2694 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
2695   { { STATE_THREADPTR }, 'o' }
2696 };
2697
2698 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2699   { { 6 /* art */ }, 'o' },
2700   { { 4 /* ars */ }, 'i' },
2701   { { 23 /* simm8 */ }, 'i' }
2702 };
2703
2704 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2705   { { 6 /* art */ }, 'o' },
2706   { { 4 /* ars */ }, 'i' },
2707   { { 24 /* simm8x256 */ }, 'i' }
2708 };
2709
2710 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2711   { { 3 /* arr */ }, 'o' },
2712   { { 4 /* ars */ }, 'i' },
2713   { { 6 /* art */ }, 'i' }
2714 };
2715
2716 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2717   { { 3 /* arr */ }, 'o' },
2718   { { 4 /* ars */ }, 'i' },
2719   { { 6 /* art */ }, 'i' }
2720 };
2721
2722 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2723   { { 4 /* ars */ }, 'i' },
2724   { { 17 /* b4const */ }, 'i' },
2725   { { 28 /* label8 */ }, 'i' }
2726 };
2727
2728 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2729   { { 4 /* ars */ }, 'i' },
2730   { { 40 /* bbi */ }, 'i' },
2731   { { 28 /* label8 */ }, 'i' }
2732 };
2733
2734 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2735   { { 4 /* ars */ }, 'i' },
2736   { { 18 /* b4constu */ }, 'i' },
2737   { { 28 /* label8 */ }, 'i' }
2738 };
2739
2740 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2741   { { 4 /* ars */ }, 'i' },
2742   { { 6 /* art */ }, 'i' },
2743   { { 28 /* label8 */ }, 'i' }
2744 };
2745
2746 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2747   { { 4 /* ars */ }, 'i' },
2748   { { 30 /* label12 */ }, 'i' }
2749 };
2750
2751 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2752   { { 0 /* soffsetx4 */ }, 'i' },
2753   { { 7 /* ar0 */ }, 'o' }
2754 };
2755
2756 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2757   { { 4 /* ars */ }, 'i' },
2758   { { 7 /* ar0 */ }, 'o' }
2759 };
2760
2761 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2762   { { 3 /* arr */ }, 'o' },
2763   { { 6 /* art */ }, 'i' },
2764   { { 55 /* sae */ }, 'i' },
2765   { { 27 /* op2p1 */ }, 'i' }
2766 };
2767
2768 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
2769   { { 31 /* soffset */ }, 'i' }
2770 };
2771
2772 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
2773   { { 4 /* ars */ }, 'i' }
2774 };
2775
2776 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
2777   { { 6 /* art */ }, 'o' },
2778   { { 4 /* ars */ }, 'i' },
2779   { { 20 /* uimm8x2 */ }, 'i' }
2780 };
2781
2782 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
2783   { { 6 /* art */ }, 'o' },
2784   { { 4 /* ars */ }, 'i' },
2785   { { 20 /* uimm8x2 */ }, 'i' }
2786 };
2787
2788 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
2789   { { 6 /* art */ }, 'o' },
2790   { { 4 /* ars */ }, 'i' },
2791   { { 21 /* uimm8x4 */ }, 'i' }
2792 };
2793
2794 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
2795   { { 6 /* art */ }, 'o' },
2796   { { 32 /* uimm16x4 */ }, 'i' }
2797 };
2798
2799 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2800   { { STATE_LITBADDR }, 'i' },
2801   { { STATE_LITBEN }, 'i' }
2802 };
2803
2804 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
2805   { { 6 /* art */ }, 'o' },
2806   { { 4 /* ars */ }, 'i' },
2807   { { 19 /* uimm8 */ }, 'i' }
2808 };
2809
2810 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
2811   { { 4 /* ars */ }, 'i' },
2812   { { 29 /* ulabel8 */ }, 'i' }
2813 };
2814
2815 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
2816   { { STATE_LBEG }, 'o' },
2817   { { STATE_LEND }, 'o' },
2818   { { STATE_LCOUNT }, 'o' }
2819 };
2820
2821 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
2822   { { 4 /* ars */ }, 'i' },
2823   { { 29 /* ulabel8 */ }, 'i' }
2824 };
2825
2826 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
2827   { { STATE_LBEG }, 'o' },
2828   { { STATE_LEND }, 'o' },
2829   { { STATE_LCOUNT }, 'o' }
2830 };
2831
2832 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
2833   { { 6 /* art */ }, 'o' },
2834   { { 25 /* simm12b */ }, 'i' }
2835 };
2836
2837 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
2838   { { 3 /* arr */ }, 'm' },
2839   { { 4 /* ars */ }, 'i' },
2840   { { 6 /* art */ }, 'i' }
2841 };
2842
2843 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
2844   { { 3 /* arr */ }, 'o' },
2845   { { 6 /* art */ }, 'i' }
2846 };
2847
2848 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
2849   { { 5 /* *ars_invisible */ }, 'i' }
2850 };
2851
2852 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
2853   { { 6 /* art */ }, 'i' },
2854   { { 4 /* ars */ }, 'i' },
2855   { { 20 /* uimm8x2 */ }, 'i' }
2856 };
2857
2858 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
2859   { { 6 /* art */ }, 'i' },
2860   { { 4 /* ars */ }, 'i' },
2861   { { 21 /* uimm8x4 */ }, 'i' }
2862 };
2863
2864 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
2865   { { 6 /* art */ }, 'i' },
2866   { { 4 /* ars */ }, 'i' },
2867   { { 19 /* uimm8 */ }, 'i' }
2868 };
2869
2870 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
2871   { { 4 /* ars */ }, 'i' }
2872 };
2873
2874 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
2875   { { STATE_SAR }, 'o' }
2876 };
2877
2878 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
2879   { { 59 /* sas */ }, 'i' }
2880 };
2881
2882 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
2883   { { STATE_SAR }, 'o' }
2884 };
2885
2886 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
2887   { { 3 /* arr */ }, 'o' },
2888   { { 4 /* ars */ }, 'i' }
2889 };
2890
2891 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
2892   { { STATE_SAR }, 'i' }
2893 };
2894
2895 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
2896   { { 3 /* arr */ }, 'o' },
2897   { { 4 /* ars */ }, 'i' },
2898   { { 6 /* art */ }, 'i' }
2899 };
2900
2901 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
2902   { { STATE_SAR }, 'i' }
2903 };
2904
2905 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
2906   { { 3 /* arr */ }, 'o' },
2907   { { 6 /* art */ }, 'i' }
2908 };
2909
2910 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
2911   { { STATE_SAR }, 'i' }
2912 };
2913
2914 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
2915   { { 3 /* arr */ }, 'o' },
2916   { { 4 /* ars */ }, 'i' },
2917   { { 26 /* msalp32 */ }, 'i' }
2918 };
2919
2920 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
2921   { { 3 /* arr */ }, 'o' },
2922   { { 6 /* art */ }, 'i' },
2923   { { 57 /* sargt */ }, 'i' }
2924 };
2925
2926 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
2927   { { 3 /* arr */ }, 'o' },
2928   { { 6 /* art */ }, 'i' },
2929   { { 43 /* s */ }, 'i' }
2930 };
2931
2932 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
2933   { { STATE_XTSYNC }, 'i' }
2934 };
2935
2936 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
2937   { { 6 /* art */ }, 'o' },
2938   { { 43 /* s */ }, 'i' }
2939 };
2940
2941 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
2942   { { STATE_PSWOE }, 'i' },
2943   { { STATE_PSCALLINC }, 'i' },
2944   { { STATE_PSOWB }, 'i' },
2945   { { STATE_PSRING }, 'i' },
2946   { { STATE_PSUM }, 'i' },
2947   { { STATE_PSEXCM }, 'i' },
2948   { { STATE_PSINTLEVEL }, 'm' }
2949 };
2950
2951 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
2952   { { 6 /* art */ }, 'o' }
2953 };
2954
2955 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
2956   { { STATE_LEND }, 'i' }
2957 };
2958
2959 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
2960   { { 6 /* art */ }, 'i' }
2961 };
2962
2963 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
2964   { { STATE_LEND }, 'o' }
2965 };
2966
2967 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
2968   { { 6 /* art */ }, 'm' }
2969 };
2970
2971 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
2972   { { STATE_LEND }, 'm' }
2973 };
2974
2975 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
2976   { { 6 /* art */ }, 'o' }
2977 };
2978
2979 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
2980   { { STATE_LCOUNT }, 'i' }
2981 };
2982
2983 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
2984   { { 6 /* art */ }, 'i' }
2985 };
2986
2987 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
2988   { { STATE_XTSYNC }, 'o' },
2989   { { STATE_LCOUNT }, 'o' }
2990 };
2991
2992 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
2993   { { 6 /* art */ }, 'm' }
2994 };
2995
2996 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
2997   { { STATE_XTSYNC }, 'o' },
2998   { { STATE_LCOUNT }, 'm' }
2999 };
3000
3001 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3002   { { 6 /* art */ }, 'o' }
3003 };
3004
3005 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3006   { { STATE_LBEG }, 'i' }
3007 };
3008
3009 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3010   { { 6 /* art */ }, 'i' }
3011 };
3012
3013 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3014   { { STATE_LBEG }, 'o' }
3015 };
3016
3017 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3018   { { 6 /* art */ }, 'm' }
3019 };
3020
3021 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3022   { { STATE_LBEG }, 'm' }
3023 };
3024
3025 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3026   { { 6 /* art */ }, 'o' }
3027 };
3028
3029 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3030   { { STATE_SAR }, 'i' }
3031 };
3032
3033 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3034   { { 6 /* art */ }, 'i' }
3035 };
3036
3037 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3038   { { STATE_SAR }, 'o' },
3039   { { STATE_XTSYNC }, 'o' }
3040 };
3041
3042 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3043   { { 6 /* art */ }, 'm' }
3044 };
3045
3046 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3047   { { STATE_SAR }, 'm' }
3048 };
3049
3050 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3051   { { 6 /* art */ }, 'o' }
3052 };
3053
3054 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
3055   { { STATE_LITBADDR }, 'i' },
3056   { { STATE_LITBEN }, 'i' }
3057 };
3058
3059 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3060   { { 6 /* art */ }, 'i' }
3061 };
3062
3063 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
3064   { { STATE_LITBADDR }, 'o' },
3065   { { STATE_LITBEN }, 'o' }
3066 };
3067
3068 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3069   { { 6 /* art */ }, 'm' }
3070 };
3071
3072 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3073   { { STATE_LITBADDR }, 'm' },
3074   { { STATE_LITBEN }, 'm' }
3075 };
3076
3077 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
3078   { { 6 /* art */ }, 'o' }
3079 };
3080
3081 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3082   { { STATE_PSEXCM }, 'i' },
3083   { { STATE_PSRING }, 'i' }
3084 };
3085
3086 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
3087   { { 6 /* art */ }, 'i' }
3088 };
3089
3090 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
3091   { { STATE_PSEXCM }, 'i' },
3092   { { STATE_PSRING }, 'i' }
3093 };
3094
3095 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
3096   { { 6 /* art */ }, 'o' }
3097 };
3098
3099 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3100   { { STATE_PSEXCM }, 'i' },
3101   { { STATE_PSRING }, 'i' }
3102 };
3103
3104 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3105   { { 6 /* art */ }, 'o' }
3106 };
3107
3108 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3109   { { STATE_PSWOE }, 'i' },
3110   { { STATE_PSCALLINC }, 'i' },
3111   { { STATE_PSOWB }, 'i' },
3112   { { STATE_PSRING }, 'i' },
3113   { { STATE_PSUM }, 'i' },
3114   { { STATE_PSEXCM }, 'i' },
3115   { { STATE_PSINTLEVEL }, 'i' }
3116 };
3117
3118 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3119   { { 6 /* art */ }, 'i' }
3120 };
3121
3122 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3123   { { STATE_PSWOE }, 'o' },
3124   { { STATE_PSCALLINC }, 'o' },
3125   { { STATE_PSOWB }, 'o' },
3126   { { STATE_PSRING }, 'm' },
3127   { { STATE_PSUM }, 'o' },
3128   { { STATE_PSEXCM }, 'm' },
3129   { { STATE_PSINTLEVEL }, 'o' }
3130 };
3131
3132 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3133   { { 6 /* art */ }, 'm' }
3134 };
3135
3136 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3137   { { STATE_PSWOE }, 'm' },
3138   { { STATE_PSCALLINC }, 'm' },
3139   { { STATE_PSOWB }, 'm' },
3140   { { STATE_PSRING }, 'm' },
3141   { { STATE_PSUM }, 'm' },
3142   { { STATE_PSEXCM }, 'm' },
3143   { { STATE_PSINTLEVEL }, 'm' }
3144 };
3145
3146 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3147   { { 6 /* art */ }, 'o' }
3148 };
3149
3150 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3151   { { STATE_PSEXCM }, 'i' },
3152   { { STATE_PSRING }, 'i' },
3153   { { STATE_EPC1 }, 'i' }
3154 };
3155
3156 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3157   { { 6 /* art */ }, 'i' }
3158 };
3159
3160 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3161   { { STATE_PSEXCM }, 'i' },
3162   { { STATE_PSRING }, 'i' },
3163   { { STATE_EPC1 }, 'o' }
3164 };
3165
3166 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3167   { { 6 /* art */ }, 'm' }
3168 };
3169
3170 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3171   { { STATE_PSEXCM }, 'i' },
3172   { { STATE_PSRING }, 'i' },
3173   { { STATE_EPC1 }, 'm' }
3174 };
3175
3176 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3177   { { 6 /* art */ }, 'o' }
3178 };
3179
3180 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3181   { { STATE_PSEXCM }, 'i' },
3182   { { STATE_PSRING }, 'i' },
3183   { { STATE_EXCSAVE1 }, 'i' }
3184 };
3185
3186 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3187   { { 6 /* art */ }, 'i' }
3188 };
3189
3190 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3191   { { STATE_PSEXCM }, 'i' },
3192   { { STATE_PSRING }, 'i' },
3193   { { STATE_EXCSAVE1 }, 'o' }
3194 };
3195
3196 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3197   { { 6 /* art */ }, 'm' }
3198 };
3199
3200 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3201   { { STATE_PSEXCM }, 'i' },
3202   { { STATE_PSRING }, 'i' },
3203   { { STATE_EXCSAVE1 }, 'm' }
3204 };
3205
3206 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3207   { { 6 /* art */ }, 'o' }
3208 };
3209
3210 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3211   { { STATE_PSEXCM }, 'i' },
3212   { { STATE_PSRING }, 'i' },
3213   { { STATE_EPC2 }, 'i' }
3214 };
3215
3216 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3217   { { 6 /* art */ }, 'i' }
3218 };
3219
3220 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3221   { { STATE_PSEXCM }, 'i' },
3222   { { STATE_PSRING }, 'i' },
3223   { { STATE_EPC2 }, 'o' }
3224 };
3225
3226 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3227   { { 6 /* art */ }, 'm' }
3228 };
3229
3230 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3231   { { STATE_PSEXCM }, 'i' },
3232   { { STATE_PSRING }, 'i' },
3233   { { STATE_EPC2 }, 'm' }
3234 };
3235
3236 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3237   { { 6 /* art */ }, 'o' }
3238 };
3239
3240 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3241   { { STATE_PSEXCM }, 'i' },
3242   { { STATE_PSRING }, 'i' },
3243   { { STATE_EXCSAVE2 }, 'i' }
3244 };
3245
3246 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3247   { { 6 /* art */ }, 'i' }
3248 };
3249
3250 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3251   { { STATE_PSEXCM }, 'i' },
3252   { { STATE_PSRING }, 'i' },
3253   { { STATE_EXCSAVE2 }, 'o' }
3254 };
3255
3256 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3257   { { 6 /* art */ }, 'm' }
3258 };
3259
3260 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3261   { { STATE_PSEXCM }, 'i' },
3262   { { STATE_PSRING }, 'i' },
3263   { { STATE_EXCSAVE2 }, 'm' }
3264 };
3265
3266 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3267   { { 6 /* art */ }, 'o' }
3268 };
3269
3270 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3271   { { STATE_PSEXCM }, 'i' },
3272   { { STATE_PSRING }, 'i' },
3273   { { STATE_EPC3 }, 'i' }
3274 };
3275
3276 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3277   { { 6 /* art */ }, 'i' }
3278 };
3279
3280 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3281   { { STATE_PSEXCM }, 'i' },
3282   { { STATE_PSRING }, 'i' },
3283   { { STATE_EPC3 }, 'o' }
3284 };
3285
3286 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3287   { { 6 /* art */ }, 'm' }
3288 };
3289
3290 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3291   { { STATE_PSEXCM }, 'i' },
3292   { { STATE_PSRING }, 'i' },
3293   { { STATE_EPC3 }, 'm' }
3294 };
3295
3296 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3297   { { 6 /* art */ }, 'o' }
3298 };
3299
3300 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3301   { { STATE_PSEXCM }, 'i' },
3302   { { STATE_PSRING }, 'i' },
3303   { { STATE_EXCSAVE3 }, 'i' }
3304 };
3305
3306 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3307   { { 6 /* art */ }, 'i' }
3308 };
3309
3310 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3311   { { STATE_PSEXCM }, 'i' },
3312   { { STATE_PSRING }, 'i' },
3313   { { STATE_EXCSAVE3 }, 'o' }
3314 };
3315
3316 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3317   { { 6 /* art */ }, 'm' }
3318 };
3319
3320 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3321   { { STATE_PSEXCM }, 'i' },
3322   { { STATE_PSRING }, 'i' },
3323   { { STATE_EXCSAVE3 }, 'm' }
3324 };
3325
3326 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3327   { { 6 /* art */ }, 'o' }
3328 };
3329
3330 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3331   { { STATE_PSEXCM }, 'i' },
3332   { { STATE_PSRING }, 'i' },
3333   { { STATE_EPC4 }, 'i' }
3334 };
3335
3336 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3337   { { 6 /* art */ }, 'i' }
3338 };
3339
3340 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3341   { { STATE_PSEXCM }, 'i' },
3342   { { STATE_PSRING }, 'i' },
3343   { { STATE_EPC4 }, 'o' }
3344 };
3345
3346 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3347   { { 6 /* art */ }, 'm' }
3348 };
3349
3350 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3351   { { STATE_PSEXCM }, 'i' },
3352   { { STATE_PSRING }, 'i' },
3353   { { STATE_EPC4 }, 'm' }
3354 };
3355
3356 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3357   { { 6 /* art */ }, 'o' }
3358 };
3359
3360 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3361   { { STATE_PSEXCM }, 'i' },
3362   { { STATE_PSRING }, 'i' },
3363   { { STATE_EXCSAVE4 }, 'i' }
3364 };
3365
3366 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3367   { { 6 /* art */ }, 'i' }
3368 };
3369
3370 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3371   { { STATE_PSEXCM }, 'i' },
3372   { { STATE_PSRING }, 'i' },
3373   { { STATE_EXCSAVE4 }, 'o' }
3374 };
3375
3376 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3377   { { 6 /* art */ }, 'm' }
3378 };
3379
3380 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3381   { { STATE_PSEXCM }, 'i' },
3382   { { STATE_PSRING }, 'i' },
3383   { { STATE_EXCSAVE4 }, 'm' }
3384 };
3385
3386 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3387   { { 6 /* art */ }, 'o' }
3388 };
3389
3390 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3391   { { STATE_PSEXCM }, 'i' },
3392   { { STATE_PSRING }, 'i' },
3393   { { STATE_EPC5 }, 'i' }
3394 };
3395
3396 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3397   { { 6 /* art */ }, 'i' }
3398 };
3399
3400 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3401   { { STATE_PSEXCM }, 'i' },
3402   { { STATE_PSRING }, 'i' },
3403   { { STATE_EPC5 }, 'o' }
3404 };
3405
3406 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3407   { { 6 /* art */ }, 'm' }
3408 };
3409
3410 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3411   { { STATE_PSEXCM }, 'i' },
3412   { { STATE_PSRING }, 'i' },
3413   { { STATE_EPC5 }, 'm' }
3414 };
3415
3416 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3417   { { 6 /* art */ }, 'o' }
3418 };
3419
3420 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3421   { { STATE_PSEXCM }, 'i' },
3422   { { STATE_PSRING }, 'i' },
3423   { { STATE_EXCSAVE5 }, 'i' }
3424 };
3425
3426 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
3427   { { 6 /* art */ }, 'i' }
3428 };
3429
3430 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
3431   { { STATE_PSEXCM }, 'i' },
3432   { { STATE_PSRING }, 'i' },
3433   { { STATE_EXCSAVE5 }, 'o' }
3434 };
3435
3436 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
3437   { { 6 /* art */ }, 'm' }
3438 };
3439
3440 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
3441   { { STATE_PSEXCM }, 'i' },
3442   { { STATE_PSRING }, 'i' },
3443   { { STATE_EXCSAVE5 }, 'm' }
3444 };
3445
3446 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
3447   { { 6 /* art */ }, 'o' }
3448 };
3449
3450 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
3451   { { STATE_PSEXCM }, 'i' },
3452   { { STATE_PSRING }, 'i' },
3453   { { STATE_EPC6 }, 'i' }
3454 };
3455
3456 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
3457   { { 6 /* art */ }, 'i' }
3458 };
3459
3460 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
3461   { { STATE_PSEXCM }, 'i' },
3462   { { STATE_PSRING }, 'i' },
3463   { { STATE_EPC6 }, 'o' }
3464 };
3465
3466 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
3467   { { 6 /* art */ }, 'm' }
3468 };
3469
3470 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
3471   { { STATE_PSEXCM }, 'i' },
3472   { { STATE_PSRING }, 'i' },
3473   { { STATE_EPC6 }, 'm' }
3474 };
3475
3476 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
3477   { { 6 /* art */ }, 'o' }
3478 };
3479
3480 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
3481   { { STATE_PSEXCM }, 'i' },
3482   { { STATE_PSRING }, 'i' },
3483   { { STATE_EXCSAVE6 }, 'i' }
3484 };
3485
3486 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
3487   { { 6 /* art */ }, 'i' }
3488 };
3489
3490 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
3491   { { STATE_PSEXCM }, 'i' },
3492   { { STATE_PSRING }, 'i' },
3493   { { STATE_EXCSAVE6 }, 'o' }
3494 };
3495
3496 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
3497   { { 6 /* art */ }, 'm' }
3498 };
3499
3500 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
3501   { { STATE_PSEXCM }, 'i' },
3502   { { STATE_PSRING }, 'i' },
3503   { { STATE_EXCSAVE6 }, 'm' }
3504 };
3505
3506 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
3507   { { 6 /* art */ }, 'o' }
3508 };
3509
3510 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
3511   { { STATE_PSEXCM }, 'i' },
3512   { { STATE_PSRING }, 'i' },
3513   { { STATE_EPC7 }, 'i' }
3514 };
3515
3516 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
3517   { { 6 /* art */ }, 'i' }
3518 };
3519
3520 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
3521   { { STATE_PSEXCM }, 'i' },
3522   { { STATE_PSRING }, 'i' },
3523   { { STATE_EPC7 }, 'o' }
3524 };
3525
3526 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
3527   { { 6 /* art */ }, 'm' }
3528 };
3529
3530 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
3531   { { STATE_PSEXCM }, 'i' },
3532   { { STATE_PSRING }, 'i' },
3533   { { STATE_EPC7 }, 'm' }
3534 };
3535
3536 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
3537   { { 6 /* art */ }, 'o' }
3538 };
3539
3540 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
3541   { { STATE_PSEXCM }, 'i' },
3542   { { STATE_PSRING }, 'i' },
3543   { { STATE_EXCSAVE7 }, 'i' }
3544 };
3545
3546 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
3547   { { 6 /* art */ }, 'i' }
3548 };
3549
3550 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
3551   { { STATE_PSEXCM }, 'i' },
3552   { { STATE_PSRING }, 'i' },
3553   { { STATE_EXCSAVE7 }, 'o' }
3554 };
3555
3556 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
3557   { { 6 /* art */ }, 'm' }
3558 };
3559
3560 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
3561   { { STATE_PSEXCM }, 'i' },
3562   { { STATE_PSRING }, 'i' },
3563   { { STATE_EXCSAVE7 }, 'm' }
3564 };
3565
3566 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
3567   { { 6 /* art */ }, 'o' }
3568 };
3569
3570 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
3571   { { STATE_PSEXCM }, 'i' },
3572   { { STATE_PSRING }, 'i' },
3573   { { STATE_EPS2 }, 'i' }
3574 };
3575
3576 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
3577   { { 6 /* art */ }, 'i' }
3578 };
3579
3580 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
3581   { { STATE_PSEXCM }, 'i' },
3582   { { STATE_PSRING }, 'i' },
3583   { { STATE_EPS2 }, 'o' }
3584 };
3585
3586 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
3587   { { 6 /* art */ }, 'm' }
3588 };
3589
3590 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
3591   { { STATE_PSEXCM }, 'i' },
3592   { { STATE_PSRING }, 'i' },
3593   { { STATE_EPS2 }, 'm' }
3594 };
3595
3596 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
3597   { { 6 /* art */ }, 'o' }
3598 };
3599
3600 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
3601   { { STATE_PSEXCM }, 'i' },
3602   { { STATE_PSRING }, 'i' },
3603   { { STATE_EPS3 }, 'i' }
3604 };
3605
3606 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
3607   { { 6 /* art */ }, 'i' }
3608 };
3609
3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
3611   { { STATE_PSEXCM }, 'i' },
3612   { { STATE_PSRING }, 'i' },
3613   { { STATE_EPS3 }, 'o' }
3614 };
3615
3616 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
3617   { { 6 /* art */ }, 'm' }
3618 };
3619
3620 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
3621   { { STATE_PSEXCM }, 'i' },
3622   { { STATE_PSRING }, 'i' },
3623   { { STATE_EPS3 }, 'm' }
3624 };
3625
3626 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
3627   { { 6 /* art */ }, 'o' }
3628 };
3629
3630 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
3631   { { STATE_PSEXCM }, 'i' },
3632   { { STATE_PSRING }, 'i' },
3633   { { STATE_EPS4 }, 'i' }
3634 };
3635
3636 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
3637   { { 6 /* art */ }, 'i' }
3638 };
3639
3640 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3641   { { STATE_PSEXCM }, 'i' },
3642   { { STATE_PSRING }, 'i' },
3643   { { STATE_EPS4 }, 'o' }
3644 };
3645
3646 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
3647   { { 6 /* art */ }, 'm' }
3648 };
3649
3650 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3651   { { STATE_PSEXCM }, 'i' },
3652   { { STATE_PSRING }, 'i' },
3653   { { STATE_EPS4 }, 'm' }
3654 };
3655
3656 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
3657   { { 6 /* art */ }, 'o' }
3658 };
3659
3660 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
3661   { { STATE_PSEXCM }, 'i' },
3662   { { STATE_PSRING }, 'i' },
3663   { { STATE_EPS5 }, 'i' }
3664 };
3665
3666 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
3667   { { 6 /* art */ }, 'i' }
3668 };
3669
3670 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
3671   { { STATE_PSEXCM }, 'i' },
3672   { { STATE_PSRING }, 'i' },
3673   { { STATE_EPS5 }, 'o' }
3674 };
3675
3676 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
3677   { { 6 /* art */ }, 'm' }
3678 };
3679
3680 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
3681   { { STATE_PSEXCM }, 'i' },
3682   { { STATE_PSRING }, 'i' },
3683   { { STATE_EPS5 }, 'm' }
3684 };
3685
3686 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
3687   { { 6 /* art */ }, 'o' }
3688 };
3689
3690 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
3691   { { STATE_PSEXCM }, 'i' },
3692   { { STATE_PSRING }, 'i' },
3693   { { STATE_EPS6 }, 'i' }
3694 };
3695
3696 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
3697   { { 6 /* art */ }, 'i' }
3698 };
3699
3700 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
3701   { { STATE_PSEXCM }, 'i' },
3702   { { STATE_PSRING }, 'i' },
3703   { { STATE_EPS6 }, 'o' }
3704 };
3705
3706 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
3707   { { 6 /* art */ }, 'm' }
3708 };
3709
3710 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
3711   { { STATE_PSEXCM }, 'i' },
3712   { { STATE_PSRING }, 'i' },
3713   { { STATE_EPS6 }, 'm' }
3714 };
3715
3716 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
3717   { { 6 /* art */ }, 'o' }
3718 };
3719
3720 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
3721   { { STATE_PSEXCM }, 'i' },
3722   { { STATE_PSRING }, 'i' },
3723   { { STATE_EPS7 }, 'i' }
3724 };
3725
3726 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
3727   { { 6 /* art */ }, 'i' }
3728 };
3729
3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
3731   { { STATE_PSEXCM }, 'i' },
3732   { { STATE_PSRING }, 'i' },
3733   { { STATE_EPS7 }, 'o' }
3734 };
3735
3736 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
3737   { { 6 /* art */ }, 'm' }
3738 };
3739
3740 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
3741   { { STATE_PSEXCM }, 'i' },
3742   { { STATE_PSRING }, 'i' },
3743   { { STATE_EPS7 }, 'm' }
3744 };
3745
3746 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
3747   { { 6 /* art */ }, 'o' }
3748 };
3749
3750 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3751   { { STATE_PSEXCM }, 'i' },
3752   { { STATE_PSRING }, 'i' },
3753   { { STATE_EXCVADDR }, 'i' }
3754 };
3755
3756 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
3757   { { 6 /* art */ }, 'i' }
3758 };
3759
3760 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3761   { { STATE_PSEXCM }, 'i' },
3762   { { STATE_PSRING }, 'i' },
3763   { { STATE_EXCVADDR }, 'o' }
3764 };
3765
3766 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
3767   { { 6 /* art */ }, 'm' }
3768 };
3769
3770 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3771   { { STATE_PSEXCM }, 'i' },
3772   { { STATE_PSRING }, 'i' },
3773   { { STATE_EXCVADDR }, 'm' }
3774 };
3775
3776 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
3777   { { 6 /* art */ }, 'o' }
3778 };
3779
3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3781   { { STATE_PSEXCM }, 'i' },
3782   { { STATE_PSRING }, 'i' },
3783   { { STATE_DEPC }, 'i' }
3784 };
3785
3786 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
3787   { { 6 /* art */ }, 'i' }
3788 };
3789
3790 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3791   { { STATE_PSEXCM }, 'i' },
3792   { { STATE_PSRING }, 'i' },
3793   { { STATE_DEPC }, 'o' }
3794 };
3795
3796 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
3797   { { 6 /* art */ }, 'm' }
3798 };
3799
3800 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3801   { { STATE_PSEXCM }, 'i' },
3802   { { STATE_PSRING }, 'i' },
3803   { { STATE_DEPC }, 'm' }
3804 };
3805
3806 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
3807   { { 6 /* art */ }, 'o' }
3808 };
3809
3810 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3811   { { STATE_PSEXCM }, 'i' },
3812   { { STATE_PSRING }, 'i' },
3813   { { STATE_EXCCAUSE }, 'i' },
3814   { { STATE_XTSYNC }, 'i' }
3815 };
3816
3817 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
3818   { { 6 /* art */ }, 'i' }
3819 };
3820
3821 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3822   { { STATE_PSEXCM }, 'i' },
3823   { { STATE_PSRING }, 'i' },
3824   { { STATE_EXCCAUSE }, 'o' }
3825 };
3826
3827 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
3828   { { 6 /* art */ }, 'm' }
3829 };
3830
3831 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3832   { { STATE_PSEXCM }, 'i' },
3833   { { STATE_PSRING }, 'i' },
3834   { { STATE_EXCCAUSE }, 'm' }
3835 };
3836
3837 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
3838   { { 6 /* art */ }, 'o' }
3839 };
3840
3841 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3842   { { STATE_PSEXCM }, 'i' },
3843   { { STATE_PSRING }, 'i' },
3844   { { STATE_MISC0 }, 'i' }
3845 };
3846
3847 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
3848   { { 6 /* art */ }, 'i' }
3849 };
3850
3851 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3852   { { STATE_PSEXCM }, 'i' },
3853   { { STATE_PSRING }, 'i' },
3854   { { STATE_MISC0 }, 'o' }
3855 };
3856
3857 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
3858   { { 6 /* art */ }, 'm' }
3859 };
3860
3861 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3862   { { STATE_PSEXCM }, 'i' },
3863   { { STATE_PSRING }, 'i' },
3864   { { STATE_MISC0 }, 'm' }
3865 };
3866
3867 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
3868   { { 6 /* art */ }, 'o' }
3869 };
3870
3871 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3872   { { STATE_PSEXCM }, 'i' },
3873   { { STATE_PSRING }, 'i' },
3874   { { STATE_MISC1 }, 'i' }
3875 };
3876
3877 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
3878   { { 6 /* art */ }, 'i' }
3879 };
3880
3881 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
3882   { { STATE_PSEXCM }, 'i' },
3883   { { STATE_PSRING }, 'i' },
3884   { { STATE_MISC1 }, 'o' }
3885 };
3886
3887 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
3888   { { 6 /* art */ }, 'm' }
3889 };
3890
3891 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
3892   { { STATE_PSEXCM }, 'i' },
3893   { { STATE_PSRING }, 'i' },
3894   { { STATE_MISC1 }, 'm' }
3895 };
3896
3897 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
3898   { { 6 /* art */ }, 'o' }
3899 };
3900
3901 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
3902   { { STATE_PSEXCM }, 'i' },
3903   { { STATE_PSRING }, 'i' }
3904 };
3905
3906 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
3907   { { 6 /* art */ }, 'o' }
3908 };
3909
3910 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
3911   { { STATE_PSEXCM }, 'i' },
3912   { { STATE_PSRING }, 'i' },
3913   { { STATE_VECBASE }, 'i' }
3914 };
3915
3916 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
3917   { { 6 /* art */ }, 'i' }
3918 };
3919
3920 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
3921   { { STATE_PSEXCM }, 'i' },
3922   { { STATE_PSRING }, 'i' },
3923   { { STATE_VECBASE }, 'o' }
3924 };
3925
3926 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
3927   { { 6 /* art */ }, 'm' }
3928 };
3929
3930 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
3931   { { STATE_PSEXCM }, 'i' },
3932   { { STATE_PSRING }, 'i' },
3933   { { STATE_VECBASE }, 'm' }
3934 };
3935
3936 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
3937   { { 3 /* arr */ }, 'o' },
3938   { { 4 /* ars */ }, 'i' },
3939   { { 6 /* art */ }, 'i' }
3940 };
3941
3942 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
3943   { { 43 /* s */ }, 'i' }
3944 };
3945
3946 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
3947   { { STATE_PSWOE }, 'o' },
3948   { { STATE_PSCALLINC }, 'o' },
3949   { { STATE_PSOWB }, 'o' },
3950   { { STATE_PSRING }, 'm' },
3951   { { STATE_PSUM }, 'o' },
3952   { { STATE_PSEXCM }, 'm' },
3953   { { STATE_PSINTLEVEL }, 'o' },
3954   { { STATE_EPC1 }, 'i' },
3955   { { STATE_EPC2 }, 'i' },
3956   { { STATE_EPC3 }, 'i' },
3957   { { STATE_EPC4 }, 'i' },
3958   { { STATE_EPC5 }, 'i' },
3959   { { STATE_EPC6 }, 'i' },
3960   { { STATE_EPC7 }, 'i' },
3961   { { STATE_EPS2 }, 'i' },
3962   { { STATE_EPS3 }, 'i' },
3963   { { STATE_EPS4 }, 'i' },
3964   { { STATE_EPS5 }, 'i' },
3965   { { STATE_EPS6 }, 'i' },
3966   { { STATE_EPS7 }, 'i' },
3967   { { STATE_InOCDMode }, 'm' }
3968 };
3969
3970 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
3971   { { 43 /* s */ }, 'i' }
3972 };
3973
3974 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
3975   { { STATE_PSEXCM }, 'i' },
3976   { { STATE_PSRING }, 'i' },
3977   { { STATE_PSINTLEVEL }, 'o' }
3978 };
3979
3980 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
3981   { { 6 /* art */ }, 'o' }
3982 };
3983
3984 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
3985   { { STATE_PSEXCM }, 'i' },
3986   { { STATE_PSRING }, 'i' },
3987   { { STATE_INTERRUPT }, 'i' }
3988 };
3989
3990 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
3991   { { 6 /* art */ }, 'i' }
3992 };
3993
3994 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
3995   { { STATE_PSEXCM }, 'i' },
3996   { { STATE_PSRING }, 'i' },
3997   { { STATE_XTSYNC }, 'o' },
3998   { { STATE_INTERRUPT }, 'm' }
3999 };
4000
4001 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4002   { { 6 /* art */ }, 'i' }
4003 };
4004
4005 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4006   { { STATE_PSEXCM }, 'i' },
4007   { { STATE_PSRING }, 'i' },
4008   { { STATE_XTSYNC }, 'o' },
4009   { { STATE_INTERRUPT }, 'm' }
4010 };
4011
4012 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4013   { { 6 /* art */ }, 'o' }
4014 };
4015
4016 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4017   { { STATE_PSEXCM }, 'i' },
4018   { { STATE_PSRING }, 'i' },
4019   { { STATE_INTENABLE }, 'i' }
4020 };
4021
4022 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4023   { { 6 /* art */ }, 'i' }
4024 };
4025
4026 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4027   { { STATE_PSEXCM }, 'i' },
4028   { { STATE_PSRING }, 'i' },
4029   { { STATE_INTENABLE }, 'o' }
4030 };
4031
4032 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4033   { { 6 /* art */ }, 'm' }
4034 };
4035
4036 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4037   { { STATE_PSEXCM }, 'i' },
4038   { { STATE_PSRING }, 'i' },
4039   { { STATE_INTENABLE }, 'm' }
4040 };
4041
4042 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4043   { { 34 /* imms */ }, 'i' },
4044   { { 33 /* immt */ }, 'i' }
4045 };
4046
4047 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4048   { { STATE_PSEXCM }, 'i' },
4049   { { STATE_PSINTLEVEL }, 'i' }
4050 };
4051
4052 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4053   { { 34 /* imms */ }, 'i' }
4054 };
4055
4056 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4057   { { STATE_PSEXCM }, 'i' },
4058   { { STATE_PSINTLEVEL }, 'i' }
4059 };
4060
4061 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4062   { { 6 /* art */ }, 'o' }
4063 };
4064
4065 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4066   { { STATE_PSEXCM }, 'i' },
4067   { { STATE_PSRING }, 'i' },
4068   { { STATE_DBREAKA0 }, 'i' }
4069 };
4070
4071 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4072   { { 6 /* art */ }, 'i' }
4073 };
4074
4075 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4076   { { STATE_PSEXCM }, 'i' },
4077   { { STATE_PSRING }, 'i' },
4078   { { STATE_DBREAKA0 }, 'o' },
4079   { { STATE_XTSYNC }, 'o' }
4080 };
4081
4082 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4083   { { 6 /* art */ }, 'm' }
4084 };
4085
4086 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4087   { { STATE_PSEXCM }, 'i' },
4088   { { STATE_PSRING }, 'i' },
4089   { { STATE_DBREAKA0 }, 'm' },
4090   { { STATE_XTSYNC }, 'o' }
4091 };
4092
4093 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4094   { { 6 /* art */ }, 'o' }
4095 };
4096
4097 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4098   { { STATE_PSEXCM }, 'i' },
4099   { { STATE_PSRING }, 'i' },
4100   { { STATE_DBREAKC0 }, 'i' }
4101 };
4102
4103 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4104   { { 6 /* art */ }, 'i' }
4105 };
4106
4107 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4108   { { STATE_PSEXCM }, 'i' },
4109   { { STATE_PSRING }, 'i' },
4110   { { STATE_DBREAKC0 }, 'o' },
4111   { { STATE_XTSYNC }, 'o' }
4112 };
4113
4114 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4115   { { 6 /* art */ }, 'm' }
4116 };
4117
4118 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4119   { { STATE_PSEXCM }, 'i' },
4120   { { STATE_PSRING }, 'i' },
4121   { { STATE_DBREAKC0 }, 'm' },
4122   { { STATE_XTSYNC }, 'o' }
4123 };
4124
4125 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4126   { { 6 /* art */ }, 'o' }
4127 };
4128
4129 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4130   { { STATE_PSEXCM }, 'i' },
4131   { { STATE_PSRING }, 'i' },
4132   { { STATE_DBREAKA1 }, 'i' }
4133 };
4134
4135 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4136   { { 6 /* art */ }, 'i' }
4137 };
4138
4139 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4140   { { STATE_PSEXCM }, 'i' },
4141   { { STATE_PSRING }, 'i' },
4142   { { STATE_DBREAKA1 }, 'o' },
4143   { { STATE_XTSYNC }, 'o' }
4144 };
4145
4146 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4147   { { 6 /* art */ }, 'm' }
4148 };
4149
4150 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4151   { { STATE_PSEXCM }, 'i' },
4152   { { STATE_PSRING }, 'i' },
4153   { { STATE_DBREAKA1 }, 'm' },
4154   { { STATE_XTSYNC }, 'o' }
4155 };
4156
4157 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4158   { { 6 /* art */ }, 'o' }
4159 };
4160
4161 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4162   { { STATE_PSEXCM }, 'i' },
4163   { { STATE_PSRING }, 'i' },
4164   { { STATE_DBREAKC1 }, 'i' }
4165 };
4166
4167 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4168   { { 6 /* art */ }, 'i' }
4169 };
4170
4171 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4172   { { STATE_PSEXCM }, 'i' },
4173   { { STATE_PSRING }, 'i' },
4174   { { STATE_DBREAKC1 }, 'o' },
4175   { { STATE_XTSYNC }, 'o' }
4176 };
4177
4178 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4179   { { 6 /* art */ }, 'm' }
4180 };
4181
4182 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4183   { { STATE_PSEXCM }, 'i' },
4184   { { STATE_PSRING }, 'i' },
4185   { { STATE_DBREAKC1 }, 'm' },
4186   { { STATE_XTSYNC }, 'o' }
4187 };
4188
4189 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4190   { { 6 /* art */ }, 'o' }
4191 };
4192
4193 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4194   { { STATE_PSEXCM }, 'i' },
4195   { { STATE_PSRING }, 'i' },
4196   { { STATE_IBREAKA0 }, 'i' }
4197 };
4198
4199 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4200   { { 6 /* art */ }, 'i' }
4201 };
4202
4203 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4204   { { STATE_PSEXCM }, 'i' },
4205   { { STATE_PSRING }, 'i' },
4206   { { STATE_IBREAKA0 }, 'o' }
4207 };
4208
4209 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4210   { { 6 /* art */ }, 'm' }
4211 };
4212
4213 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4214   { { STATE_PSEXCM }, 'i' },
4215   { { STATE_PSRING }, 'i' },
4216   { { STATE_IBREAKA0 }, 'm' }
4217 };
4218
4219 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4220   { { 6 /* art */ }, 'o' }
4221 };
4222
4223 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4224   { { STATE_PSEXCM }, 'i' },
4225   { { STATE_PSRING }, 'i' },
4226   { { STATE_IBREAKA1 }, 'i' }
4227 };
4228
4229 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4230   { { 6 /* art */ }, 'i' }
4231 };
4232
4233 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4234   { { STATE_PSEXCM }, 'i' },
4235   { { STATE_PSRING }, 'i' },
4236   { { STATE_IBREAKA1 }, 'o' }
4237 };
4238
4239 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4240   { { 6 /* art */ }, 'm' }
4241 };
4242
4243 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4244   { { STATE_PSEXCM }, 'i' },
4245   { { STATE_PSRING }, 'i' },
4246   { { STATE_IBREAKA1 }, 'm' }
4247 };
4248
4249 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4250   { { 6 /* art */ }, 'o' }
4251 };
4252
4253 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4254   { { STATE_PSEXCM }, 'i' },
4255   { { STATE_PSRING }, 'i' },
4256   { { STATE_IBREAKENABLE }, 'i' }
4257 };
4258
4259 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4260   { { 6 /* art */ }, 'i' }
4261 };
4262
4263 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4264   { { STATE_PSEXCM }, 'i' },
4265   { { STATE_PSRING }, 'i' },
4266   { { STATE_IBREAKENABLE }, 'o' }
4267 };
4268
4269 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4270   { { 6 /* art */ }, 'm' }
4271 };
4272
4273 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4274   { { STATE_PSEXCM }, 'i' },
4275   { { STATE_PSRING }, 'i' },
4276   { { STATE_IBREAKENABLE }, 'm' }
4277 };
4278
4279 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4280   { { 6 /* art */ }, 'o' }
4281 };
4282
4283 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4284   { { STATE_PSEXCM }, 'i' },
4285   { { STATE_PSRING }, 'i' },
4286   { { STATE_DEBUGCAUSE }, 'i' },
4287   { { STATE_DBNUM }, 'i' }
4288 };
4289
4290 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4291   { { 6 /* art */ }, 'i' }
4292 };
4293
4294 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4295   { { STATE_PSEXCM }, 'i' },
4296   { { STATE_PSRING }, 'i' },
4297   { { STATE_DEBUGCAUSE }, 'o' },
4298   { { STATE_DBNUM }, 'o' }
4299 };
4300
4301 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4302   { { 6 /* art */ }, 'm' }
4303 };
4304
4305 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4306   { { STATE_PSEXCM }, 'i' },
4307   { { STATE_PSRING }, 'i' },
4308   { { STATE_DEBUGCAUSE }, 'm' },
4309   { { STATE_DBNUM }, 'm' }
4310 };
4311
4312 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4313   { { 6 /* art */ }, 'o' }
4314 };
4315
4316 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4317   { { STATE_PSEXCM }, 'i' },
4318   { { STATE_PSRING }, 'i' },
4319   { { STATE_ICOUNT }, 'i' }
4320 };
4321
4322 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4323   { { 6 /* art */ }, 'i' }
4324 };
4325
4326 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4327   { { STATE_PSEXCM }, 'i' },
4328   { { STATE_PSRING }, 'i' },
4329   { { STATE_XTSYNC }, 'o' },
4330   { { STATE_ICOUNT }, 'o' }
4331 };
4332
4333 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4334   { { 6 /* art */ }, 'm' }
4335 };
4336
4337 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4338   { { STATE_PSEXCM }, 'i' },
4339   { { STATE_PSRING }, 'i' },
4340   { { STATE_XTSYNC }, 'o' },
4341   { { STATE_ICOUNT }, 'm' }
4342 };
4343
4344 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4345   { { 6 /* art */ }, 'o' }
4346 };
4347
4348 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4349   { { STATE_PSEXCM }, 'i' },
4350   { { STATE_PSRING }, 'i' },
4351   { { STATE_ICOUNTLEVEL }, 'i' }
4352 };
4353
4354 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4355   { { 6 /* art */ }, 'i' }
4356 };
4357
4358 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4359   { { STATE_PSEXCM }, 'i' },
4360   { { STATE_PSRING }, 'i' },
4361   { { STATE_ICOUNTLEVEL }, 'o' }
4362 };
4363
4364 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4365   { { 6 /* art */ }, 'm' }
4366 };
4367
4368 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4369   { { STATE_PSEXCM }, 'i' },
4370   { { STATE_PSRING }, 'i' },
4371   { { STATE_ICOUNTLEVEL }, 'm' }
4372 };
4373
4374 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4375   { { 6 /* art */ }, 'o' }
4376 };
4377
4378 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4379   { { STATE_PSEXCM }, 'i' },
4380   { { STATE_PSRING }, 'i' },
4381   { { STATE_DDR }, 'i' }
4382 };
4383
4384 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4385   { { 6 /* art */ }, 'i' }
4386 };
4387
4388 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4389   { { STATE_PSEXCM }, 'i' },
4390   { { STATE_PSRING }, 'i' },
4391   { { STATE_XTSYNC }, 'o' },
4392   { { STATE_DDR }, 'o' }
4393 };
4394
4395 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4396   { { 6 /* art */ }, 'm' }
4397 };
4398
4399 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
4400   { { STATE_PSEXCM }, 'i' },
4401   { { STATE_PSRING }, 'i' },
4402   { { STATE_XTSYNC }, 'o' },
4403   { { STATE_DDR }, 'm' }
4404 };
4405
4406 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
4407   { { 34 /* imms */ }, 'i' }
4408 };
4409
4410 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
4411   { { STATE_InOCDMode }, 'm' },
4412   { { STATE_EPC6 }, 'i' },
4413   { { STATE_PSWOE }, 'o' },
4414   { { STATE_PSCALLINC }, 'o' },
4415   { { STATE_PSOWB }, 'o' },
4416   { { STATE_PSRING }, 'o' },
4417   { { STATE_PSUM }, 'o' },
4418   { { STATE_PSEXCM }, 'o' },
4419   { { STATE_PSINTLEVEL }, 'o' },
4420   { { STATE_EPS6 }, 'i' }
4421 };
4422
4423 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
4424   { { STATE_InOCDMode }, 'm' }
4425 };
4426
4427 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
4428   { { 6 /* art */ }, 'i' }
4429 };
4430
4431 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
4432   { { STATE_PSEXCM }, 'i' },
4433   { { STATE_PSRING }, 'i' },
4434   { { STATE_XTSYNC }, 'o' }
4435 };
4436
4437 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
4438   { { 6 /* art */ }, 'o' }
4439 };
4440
4441 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
4442   { { STATE_PSEXCM }, 'i' },
4443   { { STATE_PSRING }, 'i' },
4444   { { STATE_CCOUNT }, 'i' }
4445 };
4446
4447 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
4448   { { 6 /* art */ }, 'i' }
4449 };
4450
4451 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
4452   { { STATE_PSEXCM }, 'i' },
4453   { { STATE_PSRING }, 'i' },
4454   { { STATE_XTSYNC }, 'o' },
4455   { { STATE_CCOUNT }, 'o' }
4456 };
4457
4458 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
4459   { { 6 /* art */ }, 'm' }
4460 };
4461
4462 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
4463   { { STATE_PSEXCM }, 'i' },
4464   { { STATE_PSRING }, 'i' },
4465   { { STATE_XTSYNC }, 'o' },
4466   { { STATE_CCOUNT }, 'm' }
4467 };
4468
4469 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
4470   { { 6 /* art */ }, 'o' }
4471 };
4472
4473 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
4474   { { STATE_PSEXCM }, 'i' },
4475   { { STATE_PSRING }, 'i' },
4476   { { STATE_CCOMPARE0 }, 'i' }
4477 };
4478
4479 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
4480   { { 6 /* art */ }, 'i' }
4481 };
4482
4483 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
4484   { { STATE_PSEXCM }, 'i' },
4485   { { STATE_PSRING }, 'i' },
4486   { { STATE_CCOMPARE0 }, 'o' },
4487   { { STATE_INTERRUPT }, 'm' }
4488 };
4489
4490 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
4491   { { 6 /* art */ }, 'm' }
4492 };
4493
4494 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
4495   { { STATE_PSEXCM }, 'i' },
4496   { { STATE_PSRING }, 'i' },
4497   { { STATE_CCOMPARE0 }, 'm' },
4498   { { STATE_INTERRUPT }, 'm' }
4499 };
4500
4501 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
4502   { { 6 /* art */ }, 'o' }
4503 };
4504
4505 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
4506   { { STATE_PSEXCM }, 'i' },
4507   { { STATE_PSRING }, 'i' },
4508   { { STATE_CCOMPARE1 }, 'i' }
4509 };
4510
4511 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
4512   { { 6 /* art */ }, 'i' }
4513 };
4514
4515 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
4516   { { STATE_PSEXCM }, 'i' },
4517   { { STATE_PSRING }, 'i' },
4518   { { STATE_CCOMPARE1 }, 'o' },
4519   { { STATE_INTERRUPT }, 'm' }
4520 };
4521
4522 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
4523   { { 6 /* art */ }, 'm' }
4524 };
4525
4526 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
4527   { { STATE_PSEXCM }, 'i' },
4528   { { STATE_PSRING }, 'i' },
4529   { { STATE_CCOMPARE1 }, 'm' },
4530   { { STATE_INTERRUPT }, 'm' }
4531 };
4532
4533 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
4534   { { 6 /* art */ }, 'o' }
4535 };
4536
4537 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
4538   { { STATE_PSEXCM }, 'i' },
4539   { { STATE_PSRING }, 'i' },
4540   { { STATE_CCOMPARE2 }, 'i' }
4541 };
4542
4543 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
4544   { { 6 /* art */ }, 'i' }
4545 };
4546
4547 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
4548   { { STATE_PSEXCM }, 'i' },
4549   { { STATE_PSRING }, 'i' },
4550   { { STATE_CCOMPARE2 }, 'o' },
4551   { { STATE_INTERRUPT }, 'm' }
4552 };
4553
4554 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
4555   { { 6 /* art */ }, 'm' }
4556 };
4557
4558 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
4559   { { STATE_PSEXCM }, 'i' },
4560   { { STATE_PSRING }, 'i' },
4561   { { STATE_CCOMPARE2 }, 'm' },
4562   { { STATE_INTERRUPT }, 'm' }
4563 };
4564
4565 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
4566   { { 4 /* ars */ }, 'i' },
4567   { { 21 /* uimm8x4 */ }, 'i' }
4568 };
4569
4570 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
4571   { { 4 /* ars */ }, 'i' },
4572   { { 22 /* uimm4x16 */ }, 'i' }
4573 };
4574
4575 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
4576   { { STATE_PSEXCM }, 'i' },
4577   { { STATE_PSRING }, 'i' }
4578 };
4579
4580 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
4581   { { 4 /* ars */ }, 'i' },
4582   { { 21 /* uimm8x4 */ }, 'i' }
4583 };
4584
4585 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
4586   { { STATE_PSEXCM }, 'i' },
4587   { { STATE_PSRING }, 'i' }
4588 };
4589
4590 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
4591   { { 6 /* art */ }, 'o' },
4592   { { 4 /* ars */ }, 'i' }
4593 };
4594
4595 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
4596   { { STATE_PSEXCM }, 'i' },
4597   { { STATE_PSRING }, 'i' }
4598 };
4599
4600 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
4601   { { 6 /* art */ }, 'i' },
4602   { { 4 /* ars */ }, 'i' }
4603 };
4604
4605 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
4606   { { STATE_PSEXCM }, 'i' },
4607   { { STATE_PSRING }, 'i' }
4608 };
4609
4610 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
4611   { { 4 /* ars */ }, 'i' },
4612   { { 21 /* uimm8x4 */ }, 'i' }
4613 };
4614
4615 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
4616   { { 4 /* ars */ }, 'i' },
4617   { { 22 /* uimm4x16 */ }, 'i' }
4618 };
4619
4620 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
4621   { { STATE_PSEXCM }, 'i' },
4622   { { STATE_PSRING }, 'i' }
4623 };
4624
4625 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
4626   { { 4 /* ars */ }, 'i' },
4627   { { 21 /* uimm8x4 */ }, 'i' }
4628 };
4629
4630 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
4631   { { STATE_PSEXCM }, 'i' },
4632   { { STATE_PSRING }, 'i' }
4633 };
4634
4635 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
4636   { { 4 /* ars */ }, 'i' },
4637   { { 21 /* uimm8x4 */ }, 'i' }
4638 };
4639
4640 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
4641   { { 4 /* ars */ }, 'i' },
4642   { { 22 /* uimm4x16 */ }, 'i' }
4643 };
4644
4645 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
4646   { { STATE_PSEXCM }, 'i' },
4647   { { STATE_PSRING }, 'i' }
4648 };
4649
4650 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
4651   { { 6 /* art */ }, 'i' },
4652   { { 4 /* ars */ }, 'i' }
4653 };
4654
4655 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
4656   { { STATE_PSEXCM }, 'i' },
4657   { { STATE_PSRING }, 'i' }
4658 };
4659
4660 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
4661   { { 6 /* art */ }, 'o' },
4662   { { 4 /* ars */ }, 'i' }
4663 };
4664
4665 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
4666   { { STATE_PSEXCM }, 'i' },
4667   { { STATE_PSRING }, 'i' }
4668 };
4669
4670 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
4671   { { 6 /* art */ }, 'i' }
4672 };
4673
4674 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
4675   { { STATE_PSEXCM }, 'i' },
4676   { { STATE_PSRING }, 'i' },
4677   { { STATE_PTBASE }, 'o' },
4678   { { STATE_XTSYNC }, 'o' }
4679 };
4680
4681 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
4682   { { 6 /* art */ }, 'o' }
4683 };
4684
4685 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
4686   { { STATE_PSEXCM }, 'i' },
4687   { { STATE_PSRING }, 'i' },
4688   { { STATE_PTBASE }, 'i' },
4689   { { STATE_EXCVADDR }, 'i' }
4690 };
4691
4692 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
4693   { { 6 /* art */ }, 'm' }
4694 };
4695
4696 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
4697   { { STATE_PSEXCM }, 'i' },
4698   { { STATE_PSRING }, 'i' },
4699   { { STATE_PTBASE }, 'm' },
4700   { { STATE_EXCVADDR }, 'i' },
4701   { { STATE_XTSYNC }, 'o' }
4702 };
4703
4704 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
4705   { { 6 /* art */ }, 'o' }
4706 };
4707
4708 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
4709   { { STATE_PSEXCM }, 'i' },
4710   { { STATE_PSRING }, 'i' },
4711   { { STATE_ASID3 }, 'i' },
4712   { { STATE_ASID2 }, 'i' },
4713   { { STATE_ASID1 }, 'i' }
4714 };
4715
4716 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
4717   { { 6 /* art */ }, 'i' }
4718 };
4719
4720 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
4721   { { STATE_XTSYNC }, 'o' },
4722   { { STATE_PSEXCM }, 'i' },
4723   { { STATE_PSRING }, 'i' },
4724   { { STATE_ASID3 }, 'o' },
4725   { { STATE_ASID2 }, 'o' },
4726   { { STATE_ASID1 }, 'o' }
4727 };
4728
4729 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
4730   { { 6 /* art */ }, 'm' }
4731 };
4732
4733 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
4734   { { STATE_XTSYNC }, 'o' },
4735   { { STATE_PSEXCM }, 'i' },
4736   { { STATE_PSRING }, 'i' },
4737   { { STATE_ASID3 }, 'm' },
4738   { { STATE_ASID2 }, 'm' },
4739   { { STATE_ASID1 }, 'm' }
4740 };
4741
4742 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
4743   { { 6 /* art */ }, 'o' }
4744 };
4745
4746 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
4747   { { STATE_PSEXCM }, 'i' },
4748   { { STATE_PSRING }, 'i' },
4749   { { STATE_INSTPGSZID4 }, 'i' }
4750 };
4751
4752 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
4753   { { 6 /* art */ }, 'i' }
4754 };
4755
4756 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
4757   { { STATE_XTSYNC }, 'o' },
4758   { { STATE_PSEXCM }, 'i' },
4759   { { STATE_PSRING }, 'i' },
4760   { { STATE_INSTPGSZID4 }, 'o' }
4761 };
4762
4763 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
4764   { { 6 /* art */ }, 'm' }
4765 };
4766
4767 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
4768   { { STATE_XTSYNC }, 'o' },
4769   { { STATE_PSEXCM }, 'i' },
4770   { { STATE_PSRING }, 'i' },
4771   { { STATE_INSTPGSZID4 }, 'm' }
4772 };
4773
4774 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
4775   { { 6 /* art */ }, 'o' }
4776 };
4777
4778 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
4779   { { STATE_PSEXCM }, 'i' },
4780   { { STATE_PSRING }, 'i' },
4781   { { STATE_DATAPGSZID4 }, 'i' }
4782 };
4783
4784 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
4785   { { 6 /* art */ }, 'i' }
4786 };
4787
4788 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
4789   { { STATE_XTSYNC }, 'o' },
4790   { { STATE_PSEXCM }, 'i' },
4791   { { STATE_PSRING }, 'i' },
4792   { { STATE_DATAPGSZID4 }, 'o' }
4793 };
4794
4795 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
4796   { { 6 /* art */ }, 'm' }
4797 };
4798
4799 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
4800   { { STATE_XTSYNC }, 'o' },
4801   { { STATE_PSEXCM }, 'i' },
4802   { { STATE_PSRING }, 'i' },
4803   { { STATE_DATAPGSZID4 }, 'm' }
4804 };
4805
4806 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
4807   { { 4 /* ars */ }, 'i' }
4808 };
4809
4810 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4811   { { STATE_PSEXCM }, 'i' },
4812   { { STATE_PSRING }, 'i' },
4813   { { STATE_XTSYNC }, 'o' }
4814 };
4815
4816 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
4817   { { 6 /* art */ }, 'o' },
4818   { { 4 /* ars */ }, 'i' }
4819 };
4820
4821 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
4822   { { STATE_PSEXCM }, 'i' },
4823   { { STATE_PSRING }, 'i' }
4824 };
4825
4826 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
4827   { { 6 /* art */ }, 'i' },
4828   { { 4 /* ars */ }, 'i' }
4829 };
4830
4831 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4832   { { STATE_PSEXCM }, 'i' },
4833   { { STATE_PSRING }, 'i' },
4834   { { STATE_XTSYNC }, 'o' }
4835 };
4836
4837 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
4838   { { 4 /* ars */ }, 'i' }
4839 };
4840
4841 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
4842   { { STATE_PSEXCM }, 'i' },
4843   { { STATE_PSRING }, 'i' }
4844 };
4845
4846 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
4847   { { 6 /* art */ }, 'o' },
4848   { { 4 /* ars */ }, 'i' }
4849 };
4850
4851 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
4852   { { STATE_PSEXCM }, 'i' },
4853   { { STATE_PSRING }, 'i' }
4854 };
4855
4856 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
4857   { { 6 /* art */ }, 'i' },
4858   { { 4 /* ars */ }, 'i' }
4859 };
4860
4861 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
4862   { { STATE_PSEXCM }, 'i' },
4863   { { STATE_PSRING }, 'i' }
4864 };
4865
4866 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
4867   { { STATE_PTBASE }, 'i' },
4868   { { STATE_EXCVADDR }, 'i' }
4869 };
4870
4871 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
4872   { { STATE_EXCVADDR }, 'i' }
4873 };
4874
4875 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
4876   { { STATE_EXCVADDR }, 'i' }
4877 };
4878
4879 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
4880   { { 6 /* art */ }, 'o' }
4881 };
4882
4883 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
4884   { { STATE_PSEXCM }, 'i' },
4885   { { STATE_PSRING }, 'i' },
4886   { { STATE_CPENABLE }, 'i' }
4887 };
4888
4889 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
4890   { { 6 /* art */ }, 'i' }
4891 };
4892
4893 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
4894   { { STATE_PSEXCM }, 'i' },
4895   { { STATE_PSRING }, 'i' },
4896   { { STATE_CPENABLE }, 'o' }
4897 };
4898
4899 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
4900   { { 6 /* art */ }, 'm' }
4901 };
4902
4903 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
4904   { { STATE_PSEXCM }, 'i' },
4905   { { STATE_PSRING }, 'i' },
4906   { { STATE_CPENABLE }, 'm' }
4907 };
4908
4909 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
4910   { { 3 /* arr */ }, 'o' },
4911   { { 4 /* ars */ }, 'i' },
4912   { { 35 /* tp7 */ }, 'i' }
4913 };
4914
4915 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
4916   { { 3 /* arr */ }, 'o' },
4917   { { 4 /* ars */ }, 'i' },
4918   { { 6 /* art */ }, 'i' }
4919 };
4920
4921 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
4922   { { 6 /* art */ }, 'o' },
4923   { { 4 /* ars */ }, 'i' }
4924 };
4925
4926 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
4927   { { 3 /* arr */ }, 'o' },
4928   { { 4 /* ars */ }, 'i' },
4929   { { 35 /* tp7 */ }, 'i' }
4930 };
4931
4932 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
4933   { { 6 /* art */ }, 'o' },
4934   { { 4 /* ars */ }, 'i' },
4935   { { 21 /* uimm8x4 */ }, 'i' }
4936 };
4937
4938 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
4939   { { 6 /* art */ }, 'i' },
4940   { { 4 /* ars */ }, 'i' },
4941   { { 21 /* uimm8x4 */ }, 'i' }
4942 };
4943
4944 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
4945   { { 6 /* art */ }, 'm' },
4946   { { 4 /* ars */ }, 'i' },
4947   { { 21 /* uimm8x4 */ }, 'i' }
4948 };
4949
4950 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
4951   { { STATE_SCOMPARE1 }, 'i' },
4952   { { STATE_SCOMPARE1 }, 'i' }
4953 };
4954
4955 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
4956   { { 6 /* art */ }, 'o' }
4957 };
4958
4959 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
4960   { { STATE_SCOMPARE1 }, 'i' }
4961 };
4962
4963 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
4964   { { 6 /* art */ }, 'i' }
4965 };
4966
4967 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
4968   { { STATE_SCOMPARE1 }, 'o' }
4969 };
4970
4971 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
4972   { { 6 /* art */ }, 'm' }
4973 };
4974
4975 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
4976   { { STATE_SCOMPARE1 }, 'm' }
4977 };
4978
4979 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
4980   { { 3 /* arr */ }, 'o' },
4981   { { 4 /* ars */ }, 'i' },
4982   { { 6 /* art */ }, 'i' }
4983 };
4984
4985 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4986   { { 3 /* arr */ }, 'o' },
4987   { { 4 /* ars */ }, 'i' },
4988   { { 6 /* art */ }, 'i' }
4989 };
4990
4991 static xtensa_iclass_internal iclasses[] = {
4992   { 0, 0 /* xt_iclass_excw */,
4993     0, 0, 0, 0 },
4994   { 0, 0 /* xt_iclass_rfe */,
4995     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4996   { 0, 0 /* xt_iclass_rfde */,
4997     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4998   { 0, 0 /* xt_iclass_syscall */,
4999     0, 0, 0, 0 },
5000   { 0, 0 /* xt_iclass_simcall */,
5001     0, 0, 0, 0 },
5002   { 2, Iclass_xt_iclass_call12_args,
5003     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5004   { 2, Iclass_xt_iclass_call8_args,
5005     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5006   { 2, Iclass_xt_iclass_call4_args,
5007     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5008   { 2, Iclass_xt_iclass_callx12_args,
5009     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5010   { 2, Iclass_xt_iclass_callx8_args,
5011     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5012   { 2, Iclass_xt_iclass_callx4_args,
5013     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5014   { 3, Iclass_xt_iclass_entry_args,
5015     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5016   { 2, Iclass_xt_iclass_movsp_args,
5017     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5018   { 1, Iclass_xt_iclass_rotw_args,
5019     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5020   { 1, Iclass_xt_iclass_retw_args,
5021     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5022   { 0, 0 /* xt_iclass_rfwou */,
5023     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5024   { 3, Iclass_xt_iclass_l32e_args,
5025     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
5026   { 3, Iclass_xt_iclass_s32e_args,
5027     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
5028   { 1, Iclass_xt_iclass_rsr_windowbase_args,
5029     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5030   { 1, Iclass_xt_iclass_wsr_windowbase_args,
5031     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5032   { 1, Iclass_xt_iclass_xsr_windowbase_args,
5033     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5034   { 1, Iclass_xt_iclass_rsr_windowstart_args,
5035     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5036   { 1, Iclass_xt_iclass_wsr_windowstart_args,
5037     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5038   { 1, Iclass_xt_iclass_xsr_windowstart_args,
5039     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5040   { 3, Iclass_xt_iclass_add_n_args,
5041     0, 0, 0, 0 },
5042   { 3, Iclass_xt_iclass_addi_n_args,
5043     0, 0, 0, 0 },
5044   { 2, Iclass_xt_iclass_bz6_args,
5045     0, 0, 0, 0 },
5046   { 0, 0 /* xt_iclass_ill_n */,
5047     0, 0, 0, 0 },
5048   { 3, Iclass_xt_iclass_loadi4_args,
5049     0, 0, 0, 0 },
5050   { 2, Iclass_xt_iclass_mov_n_args,
5051     0, 0, 0, 0 },
5052   { 2, Iclass_xt_iclass_movi_n_args,
5053     0, 0, 0, 0 },
5054   { 0, 0 /* xt_iclass_nopn */,
5055     0, 0, 0, 0 },
5056   { 1, Iclass_xt_iclass_retn_args,
5057     0, 0, 0, 0 },
5058   { 3, Iclass_xt_iclass_storei4_args,
5059     0, 0, 0, 0 },
5060   { 1, Iclass_rur_threadptr_args,
5061     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
5062   { 1, Iclass_wur_threadptr_args,
5063     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
5064   { 3, Iclass_xt_iclass_addi_args,
5065     0, 0, 0, 0 },
5066   { 3, Iclass_xt_iclass_addmi_args,
5067     0, 0, 0, 0 },
5068   { 3, Iclass_xt_iclass_addsub_args,
5069     0, 0, 0, 0 },
5070   { 3, Iclass_xt_iclass_bit_args,
5071     0, 0, 0, 0 },
5072   { 3, Iclass_xt_iclass_bsi8_args,
5073     0, 0, 0, 0 },
5074   { 3, Iclass_xt_iclass_bsi8b_args,
5075     0, 0, 0, 0 },
5076   { 3, Iclass_xt_iclass_bsi8u_args,
5077     0, 0, 0, 0 },
5078   { 3, Iclass_xt_iclass_bst8_args,
5079     0, 0, 0, 0 },
5080   { 2, Iclass_xt_iclass_bsz12_args,
5081     0, 0, 0, 0 },
5082   { 2, Iclass_xt_iclass_call0_args,
5083     0, 0, 0, 0 },
5084   { 2, Iclass_xt_iclass_callx0_args,
5085     0, 0, 0, 0 },
5086   { 4, Iclass_xt_iclass_exti_args,
5087     0, 0, 0, 0 },
5088   { 0, 0 /* xt_iclass_ill */,
5089     0, 0, 0, 0 },
5090   { 1, Iclass_xt_iclass_jump_args,
5091     0, 0, 0, 0 },
5092   { 1, Iclass_xt_iclass_jumpx_args,
5093     0, 0, 0, 0 },
5094   { 3, Iclass_xt_iclass_l16ui_args,
5095     0, 0, 0, 0 },
5096   { 3, Iclass_xt_iclass_l16si_args,
5097     0, 0, 0, 0 },
5098   { 3, Iclass_xt_iclass_l32i_args,
5099     0, 0, 0, 0 },
5100   { 2, Iclass_xt_iclass_l32r_args,
5101     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
5102   { 3, Iclass_xt_iclass_l8i_args,
5103     0, 0, 0, 0 },
5104   { 2, Iclass_xt_iclass_loop_args,
5105     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5106   { 2, Iclass_xt_iclass_loopz_args,
5107     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5108   { 2, Iclass_xt_iclass_movi_args,
5109     0, 0, 0, 0 },
5110   { 3, Iclass_xt_iclass_movz_args,
5111     0, 0, 0, 0 },
5112   { 2, Iclass_xt_iclass_neg_args,
5113     0, 0, 0, 0 },
5114   { 0, 0 /* xt_iclass_nop */,
5115     0, 0, 0, 0 },
5116   { 1, Iclass_xt_iclass_return_args,
5117     0, 0, 0, 0 },
5118   { 3, Iclass_xt_iclass_s16i_args,
5119     0, 0, 0, 0 },
5120   { 3, Iclass_xt_iclass_s32i_args,
5121     0, 0, 0, 0 },
5122   { 3, Iclass_xt_iclass_s8i_args,
5123     0, 0, 0, 0 },
5124   { 1, Iclass_xt_iclass_sar_args,
5125     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5126   { 1, Iclass_xt_iclass_sari_args,
5127     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5128   { 2, Iclass_xt_iclass_shifts_args,
5129     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5130   { 3, Iclass_xt_iclass_shiftst_args,
5131     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5132   { 2, Iclass_xt_iclass_shiftt_args,
5133     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5134   { 3, Iclass_xt_iclass_slli_args,
5135     0, 0, 0, 0 },
5136   { 3, Iclass_xt_iclass_srai_args,
5137     0, 0, 0, 0 },
5138   { 3, Iclass_xt_iclass_srli_args,
5139     0, 0, 0, 0 },
5140   { 0, 0 /* xt_iclass_memw */,
5141     0, 0, 0, 0 },
5142   { 0, 0 /* xt_iclass_extw */,
5143     0, 0, 0, 0 },
5144   { 0, 0 /* xt_iclass_isync */,
5145     0, 0, 0, 0 },
5146   { 0, 0 /* xt_iclass_sync */,
5147     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5148   { 2, Iclass_xt_iclass_rsil_args,
5149     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5150   { 1, Iclass_xt_iclass_rsr_lend_args,
5151     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5152   { 1, Iclass_xt_iclass_wsr_lend_args,
5153     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5154   { 1, Iclass_xt_iclass_xsr_lend_args,
5155     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5156   { 1, Iclass_xt_iclass_rsr_lcount_args,
5157     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5158   { 1, Iclass_xt_iclass_wsr_lcount_args,
5159     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5160   { 1, Iclass_xt_iclass_xsr_lcount_args,
5161     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5162   { 1, Iclass_xt_iclass_rsr_lbeg_args,
5163     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5164   { 1, Iclass_xt_iclass_wsr_lbeg_args,
5165     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5166   { 1, Iclass_xt_iclass_xsr_lbeg_args,
5167     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5168   { 1, Iclass_xt_iclass_rsr_sar_args,
5169     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5170   { 1, Iclass_xt_iclass_wsr_sar_args,
5171     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5172   { 1, Iclass_xt_iclass_xsr_sar_args,
5173     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5174   { 1, Iclass_xt_iclass_rsr_litbase_args,
5175     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
5176   { 1, Iclass_xt_iclass_wsr_litbase_args,
5177     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
5178   { 1, Iclass_xt_iclass_xsr_litbase_args,
5179     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
5180   { 1, Iclass_xt_iclass_rsr_176_args,
5181     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
5182   { 1, Iclass_xt_iclass_wsr_176_args,
5183     2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
5184   { 1, Iclass_xt_iclass_rsr_208_args,
5185     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
5186   { 1, Iclass_xt_iclass_rsr_ps_args,
5187     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5188   { 1, Iclass_xt_iclass_wsr_ps_args,
5189     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5190   { 1, Iclass_xt_iclass_xsr_ps_args,
5191     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5192   { 1, Iclass_xt_iclass_rsr_epc1_args,
5193     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5194   { 1, Iclass_xt_iclass_wsr_epc1_args,
5195     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5196   { 1, Iclass_xt_iclass_xsr_epc1_args,
5197     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5198   { 1, Iclass_xt_iclass_rsr_excsave1_args,
5199     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5200   { 1, Iclass_xt_iclass_wsr_excsave1_args,
5201     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5202   { 1, Iclass_xt_iclass_xsr_excsave1_args,
5203     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5204   { 1, Iclass_xt_iclass_rsr_epc2_args,
5205     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5206   { 1, Iclass_xt_iclass_wsr_epc2_args,
5207     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5208   { 1, Iclass_xt_iclass_xsr_epc2_args,
5209     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5210   { 1, Iclass_xt_iclass_rsr_excsave2_args,
5211     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5212   { 1, Iclass_xt_iclass_wsr_excsave2_args,
5213     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5214   { 1, Iclass_xt_iclass_xsr_excsave2_args,
5215     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5216   { 1, Iclass_xt_iclass_rsr_epc3_args,
5217     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5218   { 1, Iclass_xt_iclass_wsr_epc3_args,
5219     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5220   { 1, Iclass_xt_iclass_xsr_epc3_args,
5221     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5222   { 1, Iclass_xt_iclass_rsr_excsave3_args,
5223     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5224   { 1, Iclass_xt_iclass_wsr_excsave3_args,
5225     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5226   { 1, Iclass_xt_iclass_xsr_excsave3_args,
5227     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5228   { 1, Iclass_xt_iclass_rsr_epc4_args,
5229     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5230   { 1, Iclass_xt_iclass_wsr_epc4_args,
5231     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5232   { 1, Iclass_xt_iclass_xsr_epc4_args,
5233     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5234   { 1, Iclass_xt_iclass_rsr_excsave4_args,
5235     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5236   { 1, Iclass_xt_iclass_wsr_excsave4_args,
5237     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5238   { 1, Iclass_xt_iclass_xsr_excsave4_args,
5239     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5240   { 1, Iclass_xt_iclass_rsr_epc5_args,
5241     3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5242   { 1, Iclass_xt_iclass_wsr_epc5_args,
5243     3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5244   { 1, Iclass_xt_iclass_xsr_epc5_args,
5245     3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5246   { 1, Iclass_xt_iclass_rsr_excsave5_args,
5247     3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5248   { 1, Iclass_xt_iclass_wsr_excsave5_args,
5249     3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5250   { 1, Iclass_xt_iclass_xsr_excsave5_args,
5251     3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5252   { 1, Iclass_xt_iclass_rsr_epc6_args,
5253     3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5254   { 1, Iclass_xt_iclass_wsr_epc6_args,
5255     3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5256   { 1, Iclass_xt_iclass_xsr_epc6_args,
5257     3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5258   { 1, Iclass_xt_iclass_rsr_excsave6_args,
5259     3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5260   { 1, Iclass_xt_iclass_wsr_excsave6_args,
5261     3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5262   { 1, Iclass_xt_iclass_xsr_excsave6_args,
5263     3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5264   { 1, Iclass_xt_iclass_rsr_epc7_args,
5265     3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5266   { 1, Iclass_xt_iclass_wsr_epc7_args,
5267     3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5268   { 1, Iclass_xt_iclass_xsr_epc7_args,
5269     3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5270   { 1, Iclass_xt_iclass_rsr_excsave7_args,
5271     3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5272   { 1, Iclass_xt_iclass_wsr_excsave7_args,
5273     3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5274   { 1, Iclass_xt_iclass_xsr_excsave7_args,
5275     3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5276   { 1, Iclass_xt_iclass_rsr_eps2_args,
5277     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5278   { 1, Iclass_xt_iclass_wsr_eps2_args,
5279     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5280   { 1, Iclass_xt_iclass_xsr_eps2_args,
5281     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5282   { 1, Iclass_xt_iclass_rsr_eps3_args,
5283     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5284   { 1, Iclass_xt_iclass_wsr_eps3_args,
5285     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5286   { 1, Iclass_xt_iclass_xsr_eps3_args,
5287     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5288   { 1, Iclass_xt_iclass_rsr_eps4_args,
5289     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5290   { 1, Iclass_xt_iclass_wsr_eps4_args,
5291     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5292   { 1, Iclass_xt_iclass_xsr_eps4_args,
5293     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5294   { 1, Iclass_xt_iclass_rsr_eps5_args,
5295     3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5296   { 1, Iclass_xt_iclass_wsr_eps5_args,
5297     3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5298   { 1, Iclass_xt_iclass_xsr_eps5_args,
5299     3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5300   { 1, Iclass_xt_iclass_rsr_eps6_args,
5301     3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5302   { 1, Iclass_xt_iclass_wsr_eps6_args,
5303     3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5304   { 1, Iclass_xt_iclass_xsr_eps6_args,
5305     3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5306   { 1, Iclass_xt_iclass_rsr_eps7_args,
5307     3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5308   { 1, Iclass_xt_iclass_wsr_eps7_args,
5309     3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5310   { 1, Iclass_xt_iclass_xsr_eps7_args,
5311     3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5312   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
5313     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5314   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
5315     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5316   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
5317     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5318   { 1, Iclass_xt_iclass_rsr_depc_args,
5319     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5320   { 1, Iclass_xt_iclass_wsr_depc_args,
5321     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5322   { 1, Iclass_xt_iclass_xsr_depc_args,
5323     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5324   { 1, Iclass_xt_iclass_rsr_exccause_args,
5325     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5326   { 1, Iclass_xt_iclass_wsr_exccause_args,
5327     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5328   { 1, Iclass_xt_iclass_xsr_exccause_args,
5329     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5330   { 1, Iclass_xt_iclass_rsr_misc0_args,
5331     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5332   { 1, Iclass_xt_iclass_wsr_misc0_args,
5333     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5334   { 1, Iclass_xt_iclass_xsr_misc0_args,
5335     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5336   { 1, Iclass_xt_iclass_rsr_misc1_args,
5337     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5338   { 1, Iclass_xt_iclass_wsr_misc1_args,
5339     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5340   { 1, Iclass_xt_iclass_xsr_misc1_args,
5341     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5342   { 1, Iclass_xt_iclass_rsr_prid_args,
5343     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
5344   { 1, Iclass_xt_iclass_rsr_vecbase_args,
5345     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5346   { 1, Iclass_xt_iclass_wsr_vecbase_args,
5347     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5348   { 1, Iclass_xt_iclass_xsr_vecbase_args,
5349     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
5350   { 3, Iclass_xt_iclass_mul16_args,
5351     0, 0, 0, 0 },
5352   { 1, Iclass_xt_iclass_rfi_args,
5353     21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
5354   { 1, Iclass_xt_iclass_wait_args,
5355     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
5356   { 1, Iclass_xt_iclass_rsr_interrupt_args,
5357     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5358   { 1, Iclass_xt_iclass_wsr_intset_args,
5359     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5360   { 1, Iclass_xt_iclass_wsr_intclear_args,
5361     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5362   { 1, Iclass_xt_iclass_rsr_intenable_args,
5363     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5364   { 1, Iclass_xt_iclass_wsr_intenable_args,
5365     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5366   { 1, Iclass_xt_iclass_xsr_intenable_args,
5367     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5368   { 2, Iclass_xt_iclass_break_args,
5369     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5370   { 1, Iclass_xt_iclass_break_n_args,
5371     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5372   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
5373     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5374   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
5375     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5376   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
5377     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5378   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
5379     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5380   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
5381     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5382   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
5383     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5384   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
5385     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5386   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
5387     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5388   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
5389     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5390   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
5391     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5392   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
5393     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5394   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
5395     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5396   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
5397     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5398   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
5399     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5400   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
5401     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5402   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
5403     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5404   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
5405     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5406   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
5407     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5408   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
5409     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5410   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
5411     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5412   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
5413     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5414   { 1, Iclass_xt_iclass_rsr_debugcause_args,
5415     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5416   { 1, Iclass_xt_iclass_wsr_debugcause_args,
5417     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5418   { 1, Iclass_xt_iclass_xsr_debugcause_args,
5419     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5420   { 1, Iclass_xt_iclass_rsr_icount_args,
5421     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5422   { 1, Iclass_xt_iclass_wsr_icount_args,
5423     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5424   { 1, Iclass_xt_iclass_xsr_icount_args,
5425     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5426   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
5427     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5428   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
5429     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5430   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
5431     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5432   { 1, Iclass_xt_iclass_rsr_ddr_args,
5433     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5434   { 1, Iclass_xt_iclass_wsr_ddr_args,
5435     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5436   { 1, Iclass_xt_iclass_xsr_ddr_args,
5437     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5438   { 1, Iclass_xt_iclass_rfdo_args,
5439     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5440   { 0, 0 /* xt_iclass_rfdd */,
5441     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5442   { 1, Iclass_xt_iclass_wsr_mmid_args,
5443     3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5444   { 1, Iclass_xt_iclass_rsr_ccount_args,
5445     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5446   { 1, Iclass_xt_iclass_wsr_ccount_args,
5447     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5448   { 1, Iclass_xt_iclass_xsr_ccount_args,
5449     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5450   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
5451     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5452   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
5453     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5454   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
5455     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5456   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
5457     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5458   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
5459     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5460   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
5461     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5462   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
5463     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5464   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
5465     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5466   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
5467     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5468   { 2, Iclass_xt_iclass_icache_args,
5469     0, 0, 0, 0 },
5470   { 2, Iclass_xt_iclass_icache_lock_args,
5471     2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
5472   { 2, Iclass_xt_iclass_icache_inv_args,
5473     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
5474   { 2, Iclass_xt_iclass_licx_args,
5475     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
5476   { 2, Iclass_xt_iclass_sicx_args,
5477     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
5478   { 2, Iclass_xt_iclass_dcache_args,
5479     0, 0, 0, 0 },
5480   { 2, Iclass_xt_iclass_dcache_ind_args,
5481     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
5482   { 2, Iclass_xt_iclass_dcache_inv_args,
5483     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
5484   { 2, Iclass_xt_iclass_dpf_args,
5485     0, 0, 0, 0 },
5486   { 2, Iclass_xt_iclass_dcache_lock_args,
5487     2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
5488   { 2, Iclass_xt_iclass_sdct_args,
5489     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
5490   { 2, Iclass_xt_iclass_ldct_args,
5491     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
5492   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
5493     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
5494   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
5495     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
5496   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
5497     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
5498   { 1, Iclass_xt_iclass_rsr_rasid_args,
5499     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
5500   { 1, Iclass_xt_iclass_wsr_rasid_args,
5501     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
5502   { 1, Iclass_xt_iclass_xsr_rasid_args,
5503     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
5504   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
5505     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
5506   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
5507     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
5508   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
5509     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
5510   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
5511     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
5512   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
5513     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
5514   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
5515     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
5516   { 1, Iclass_xt_iclass_idtlb_args,
5517     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
5518   { 2, Iclass_xt_iclass_rdtlb_args,
5519     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
5520   { 2, Iclass_xt_iclass_wdtlb_args,
5521     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
5522   { 1, Iclass_xt_iclass_iitlb_args,
5523     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
5524   { 2, Iclass_xt_iclass_ritlb_args,
5525     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
5526   { 2, Iclass_xt_iclass_witlb_args,
5527     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
5528   { 0, 0 /* xt_iclass_ldpte */,
5529     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
5530   { 0, 0 /* xt_iclass_hwwitlba */,
5531     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
5532   { 0, 0 /* xt_iclass_hwwdtlba */,
5533     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
5534   { 1, Iclass_xt_iclass_rsr_cpenable_args,
5535     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
5536   { 1, Iclass_xt_iclass_wsr_cpenable_args,
5537     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
5538   { 1, Iclass_xt_iclass_xsr_cpenable_args,
5539     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
5540   { 3, Iclass_xt_iclass_clamp_args,
5541     0, 0, 0, 0 },
5542   { 3, Iclass_xt_iclass_minmax_args,
5543     0, 0, 0, 0 },
5544   { 2, Iclass_xt_iclass_nsa_args,
5545     0, 0, 0, 0 },
5546   { 3, Iclass_xt_iclass_sx_args,
5547     0, 0, 0, 0 },
5548   { 3, Iclass_xt_iclass_l32ai_args,
5549     0, 0, 0, 0 },
5550   { 3, Iclass_xt_iclass_s32ri_args,
5551     0, 0, 0, 0 },
5552   { 3, Iclass_xt_iclass_s32c1i_args,
5553     2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
5554   { 1, Iclass_xt_iclass_rsr_scompare1_args,
5555     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
5556   { 1, Iclass_xt_iclass_wsr_scompare1_args,
5557     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
5558   { 1, Iclass_xt_iclass_xsr_scompare1_args,
5559     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
5560   { 3, Iclass_xt_iclass_div_args,
5561     0, 0, 0, 0 },
5562   { 3, Iclass_xt_mul32_args,
5563     0, 0, 0, 0 }
5564 };
5565
5566 \f
5567 /*  Opcode encodings.  */
5568
5569 static void
5570 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5571 {
5572   slotbuf[0] = 0x80200;
5573 }
5574
5575 static void
5576 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
5577 {
5578   slotbuf[0] = 0x300;
5579 }
5580
5581 static void
5582 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
5583 {
5584   slotbuf[0] = 0x2300;
5585 }
5586
5587 static void
5588 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5589 {
5590   slotbuf[0] = 0x500;
5591 }
5592
5593 static void
5594 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5595 {
5596   slotbuf[0] = 0x1500;
5597 }
5598
5599 static void
5600 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
5601 {
5602   slotbuf[0] = 0x5c0000;
5603 }
5604
5605 static void
5606 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5607 {
5608   slotbuf[0] = 0x580000;
5609 }
5610
5611 static void
5612 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5613 {
5614   slotbuf[0] = 0x540000;
5615 }
5616
5617 static void
5618 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
5619 {
5620   slotbuf[0] = 0xf0000;
5621 }
5622
5623 static void
5624 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5625 {
5626   slotbuf[0] = 0xb0000;
5627 }
5628
5629 static void
5630 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5631 {
5632   slotbuf[0] = 0x70000;
5633 }
5634
5635 static void
5636 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
5637 {
5638   slotbuf[0] = 0x6c0000;
5639 }
5640
5641 static void
5642 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
5643 {
5644   slotbuf[0] = 0x100;
5645 }
5646
5647 static void
5648 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5649 {
5650   slotbuf[0] = 0x804;
5651 }
5652
5653 static void
5654 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5655 {
5656   slotbuf[0] = 0x60000;
5657 }
5658
5659 static void
5660 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5661 {
5662   slotbuf[0] = 0xd10f;
5663 }
5664
5665 static void
5666 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
5667 {
5668   slotbuf[0] = 0x4300;
5669 }
5670
5671 static void
5672 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5673 {
5674   slotbuf[0] = 0x5300;
5675 }
5676
5677 static void
5678 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
5679 {
5680   slotbuf[0] = 0x90;
5681 }
5682
5683 static void
5684 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
5685 {
5686   slotbuf[0] = 0x94;
5687 }
5688
5689 static void
5690 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5691 {
5692   slotbuf[0] = 0x4830;
5693 }
5694
5695 static void
5696 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5697 {
5698   slotbuf[0] = 0x4831;
5699 }
5700
5701 static void
5702 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
5703 {
5704   slotbuf[0] = 0x4816;
5705 }
5706
5707 static void
5708 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5709 {
5710   slotbuf[0] = 0x4930;
5711 }
5712
5713 static void
5714 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5715 {
5716   slotbuf[0] = 0x4931;
5717 }
5718
5719 static void
5720 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
5721 {
5722   slotbuf[0] = 0x4916;
5723 }
5724
5725 static void
5726 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5727 {
5728   slotbuf[0] = 0xa000;
5729 }
5730
5731 static void
5732 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5733 {
5734   slotbuf[0] = 0xb000;
5735 }
5736
5737 static void
5738 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5739 {
5740   slotbuf[0] = 0xc800;
5741 }
5742
5743 static void
5744 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5745 {
5746   slotbuf[0] = 0xcc00;
5747 }
5748
5749 static void
5750 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5751 {
5752   slotbuf[0] = 0xd60f;
5753 }
5754
5755 static void
5756 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5757 {
5758   slotbuf[0] = 0x8000;
5759 }
5760
5761 static void
5762 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5763 {
5764   slotbuf[0] = 0xd000;
5765 }
5766
5767 static void
5768 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5769 {
5770   slotbuf[0] = 0xc000;
5771 }
5772
5773 static void
5774 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5775 {
5776   slotbuf[0] = 0xd30f;
5777 }
5778
5779 static void
5780 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
5781 {
5782   slotbuf[0] = 0xd00f;
5783 }
5784
5785 static void
5786 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
5787 {
5788   slotbuf[0] = 0x9000;
5789 }
5790
5791 static void
5792 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5793 {
5794   slotbuf[0] = 0x7e03e;
5795 }
5796
5797 static void
5798 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
5799 {
5800   slotbuf[0] = 0xe73f;
5801 }
5802
5803 static void
5804 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5805 {
5806   slotbuf[0] = 0x200c00;
5807 }
5808
5809 static void
5810 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5811 {
5812   slotbuf[0] = 0x200d00;
5813 }
5814
5815 static void
5816 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
5817 {
5818   slotbuf[0] = 0x8;
5819 }
5820
5821 static void
5822 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
5823 {
5824   slotbuf[0] = 0xc;
5825 }
5826
5827 static void
5828 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5829 {
5830   slotbuf[0] = 0x9;
5831 }
5832
5833 static void
5834 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5835 {
5836   slotbuf[0] = 0xa;
5837 }
5838
5839 static void
5840 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5841 {
5842   slotbuf[0] = 0xb;
5843 }
5844
5845 static void
5846 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
5847 {
5848   slotbuf[0] = 0xd;
5849 }
5850
5851 static void
5852 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
5853 {
5854   slotbuf[0] = 0xe;
5855 }
5856
5857 static void
5858 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
5859 {
5860   slotbuf[0] = 0xf;
5861 }
5862
5863 static void
5864 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
5865 {
5866   slotbuf[0] = 0x1;
5867 }
5868
5869 static void
5870 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
5871 {
5872   slotbuf[0] = 0x2;
5873 }
5874
5875 static void
5876 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
5877 {
5878   slotbuf[0] = 0x3;
5879 }
5880
5881 static void
5882 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5883 {
5884   slotbuf[0] = 0x680000;
5885 }
5886
5887 static void
5888 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5889 {
5890   slotbuf[0] = 0x690000;
5891 }
5892
5893 static void
5894 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
5895 {
5896   slotbuf[0] = 0x6b0000;
5897 }
5898
5899 static void
5900 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
5901 {
5902   slotbuf[0] = 0x6a0000;
5903 }
5904
5905 static void
5906 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
5907 {
5908   slotbuf[0] = 0x700600;
5909 }
5910
5911 static void
5912 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
5913 {
5914   slotbuf[0] = 0x700e00;
5915 }
5916
5917 static void
5918 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5919 {
5920   slotbuf[0] = 0x6f0000;
5921 }
5922
5923 static void
5924 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
5925 {
5926   slotbuf[0] = 0x6e0000;
5927 }
5928
5929 static void
5930 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
5931 {
5932   slotbuf[0] = 0x700100;
5933 }
5934
5935 static void
5936 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
5937 {
5938   slotbuf[0] = 0x700900;
5939 }
5940
5941 static void
5942 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
5943 {
5944   slotbuf[0] = 0x700a00;
5945 }
5946
5947 static void
5948 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
5949 {
5950   slotbuf[0] = 0x700200;
5951 }
5952
5953 static void
5954 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5955 {
5956   slotbuf[0] = 0x700b00;
5957 }
5958
5959 static void
5960 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
5961 {
5962   slotbuf[0] = 0x700300;
5963 }
5964
5965 static void
5966 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
5967 {
5968   slotbuf[0] = 0x700800;
5969 }
5970
5971 static void
5972 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
5973 {
5974   slotbuf[0] = 0x700000;
5975 }
5976
5977 static void
5978 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
5979 {
5980   slotbuf[0] = 0x700400;
5981 }
5982
5983 static void
5984 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
5985 {
5986   slotbuf[0] = 0x700c00;
5987 }
5988
5989 static void
5990 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
5991 {
5992   slotbuf[0] = 0x700500;
5993 }
5994
5995 static void
5996 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
5997 {
5998   slotbuf[0] = 0x700d00;
5999 }
6000
6001 static void
6002 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6003 {
6004   slotbuf[0] = 0x640000;
6005 }
6006
6007 static void
6008 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6009 {
6010   slotbuf[0] = 0x650000;
6011 }
6012
6013 static void
6014 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6015 {
6016   slotbuf[0] = 0x670000;
6017 }
6018
6019 static void
6020 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6021 {
6022   slotbuf[0] = 0x660000;
6023 }
6024
6025 static void
6026 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6027 {
6028   slotbuf[0] = 0x500000;
6029 }
6030
6031 static void
6032 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6033 {
6034   slotbuf[0] = 0x30000;
6035 }
6036
6037 static void
6038 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6039 {
6040   slotbuf[0] = 0x40;
6041 }
6042
6043 static void
6044 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
6045 {
6046   slotbuf[0] = 0;
6047 }
6048
6049 static void
6050 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
6051 {
6052   slotbuf[0] = 0x600000;
6053 }
6054
6055 static void
6056 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
6057 {
6058   slotbuf[0] = 0xa0000;
6059 }
6060
6061 static void
6062 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6063 {
6064   slotbuf[0] = 0x200100;
6065 }
6066
6067 static void
6068 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
6069 {
6070   slotbuf[0] = 0x200900;
6071 }
6072
6073 static void
6074 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6075 {
6076   slotbuf[0] = 0x200200;
6077 }
6078
6079 static void
6080 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
6081 {
6082   slotbuf[0] = 0x100000;
6083 }
6084
6085 static void
6086 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6087 {
6088   slotbuf[0] = 0x200000;
6089 }
6090
6091 static void
6092 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6093 {
6094   slotbuf[0] = 0x6d0800;
6095 }
6096
6097 static void
6098 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6099 {
6100   slotbuf[0] = 0x6d0900;
6101 }
6102
6103 static void
6104 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6105 {
6106   slotbuf[0] = 0x6d0a00;
6107 }
6108
6109 static void
6110 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6111 {
6112   slotbuf[0] = 0x200a00;
6113 }
6114
6115 static void
6116 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6117 {
6118   slotbuf[0] = 0x38;
6119 }
6120
6121 static void
6122 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6123 {
6124   slotbuf[0] = 0x39;
6125 }
6126
6127 static void
6128 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6129 {
6130   slotbuf[0] = 0x3a;
6131 }
6132
6133 static void
6134 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6135 {
6136   slotbuf[0] = 0x3b;
6137 }
6138
6139 static void
6140 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6141 {
6142   slotbuf[0] = 0x6;
6143 }
6144
6145 static void
6146 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6147 {
6148   slotbuf[0] = 0x1006;
6149 }
6150
6151 static void
6152 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6153 {
6154   slotbuf[0] = 0xf0200;
6155 }
6156
6157 static void
6158 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
6159 {
6160   slotbuf[0] = 0x20000;
6161 }
6162
6163 static void
6164 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6165 {
6166   slotbuf[0] = 0x200500;
6167 }
6168
6169 static void
6170 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6171 {
6172   slotbuf[0] = 0x200600;
6173 }
6174
6175 static void
6176 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6177 {
6178   slotbuf[0] = 0x200400;
6179 }
6180
6181 static void
6182 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6183 {
6184   slotbuf[0] = 0x4;
6185 }
6186
6187 static void
6188 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6189 {
6190   slotbuf[0] = 0x104;
6191 }
6192
6193 static void
6194 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
6195 {
6196   slotbuf[0] = 0x204;
6197 }
6198
6199 static void
6200 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
6201 {
6202   slotbuf[0] = 0x304;
6203 }
6204
6205 static void
6206 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6207 {
6208   slotbuf[0] = 0x404;
6209 }
6210
6211 static void
6212 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
6213 {
6214   slotbuf[0] = 0x1a;
6215 }
6216
6217 static void
6218 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
6219 {
6220   slotbuf[0] = 0x18;
6221 }
6222
6223 static void
6224 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6225 {
6226   slotbuf[0] = 0x19;
6227 }
6228
6229 static void
6230 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
6231 {
6232   slotbuf[0] = 0x1b;
6233 }
6234
6235 static void
6236 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6237 {
6238   slotbuf[0] = 0x10;
6239 }
6240
6241 static void
6242 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6243 {
6244   slotbuf[0] = 0x12;
6245 }
6246
6247 static void
6248 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6249 {
6250   slotbuf[0] = 0x14;
6251 }
6252
6253 static void
6254 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6255 {
6256   slotbuf[0] = 0xc0200;
6257 }
6258
6259 static void
6260 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6261 {
6262   slotbuf[0] = 0xd0200;
6263 }
6264
6265 static void
6266 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6267 {
6268   slotbuf[0] = 0x200;
6269 }
6270
6271 static void
6272 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6273 {
6274   slotbuf[0] = 0x10200;
6275 }
6276
6277 static void
6278 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6279 {
6280   slotbuf[0] = 0x20200;
6281 }
6282
6283 static void
6284 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6285 {
6286   slotbuf[0] = 0x30200;
6287 }
6288
6289 static void
6290 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
6291 {
6292   slotbuf[0] = 0x600;
6293 }
6294
6295 static void
6296 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6297 {
6298   slotbuf[0] = 0x130;
6299 }
6300
6301 static void
6302 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6303 {
6304   slotbuf[0] = 0x131;
6305 }
6306
6307 static void
6308 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6309 {
6310   slotbuf[0] = 0x116;
6311 }
6312
6313 static void
6314 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6315 {
6316   slotbuf[0] = 0x230;
6317 }
6318
6319 static void
6320 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6321 {
6322   slotbuf[0] = 0x231;
6323 }
6324
6325 static void
6326 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6327 {
6328   slotbuf[0] = 0x216;
6329 }
6330
6331 static void
6332 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6333 {
6334   slotbuf[0] = 0x30;
6335 }
6336
6337 static void
6338 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6339 {
6340   slotbuf[0] = 0x31;
6341 }
6342
6343 static void
6344 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6345 {
6346   slotbuf[0] = 0x16;
6347 }
6348
6349 static void
6350 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6351 {
6352   slotbuf[0] = 0x330;
6353 }
6354
6355 static void
6356 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6357 {
6358   slotbuf[0] = 0x331;
6359 }
6360
6361 static void
6362 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6363 {
6364   slotbuf[0] = 0x316;
6365 }
6366
6367 static void
6368 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6369 {
6370   slotbuf[0] = 0x530;
6371 }
6372
6373 static void
6374 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6375 {
6376   slotbuf[0] = 0x531;
6377 }
6378
6379 static void
6380 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6381 {
6382   slotbuf[0] = 0x516;
6383 }
6384
6385 static void
6386 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
6387 {
6388   slotbuf[0] = 0xb030;
6389 }
6390
6391 static void
6392 Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
6393 {
6394   slotbuf[0] = 0xb031;
6395 }
6396
6397 static void
6398 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
6399 {
6400   slotbuf[0] = 0xd030;
6401 }
6402
6403 static void
6404 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6405 {
6406   slotbuf[0] = 0xe630;
6407 }
6408
6409 static void
6410 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6411 {
6412   slotbuf[0] = 0xe631;
6413 }
6414
6415 static void
6416 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6417 {
6418   slotbuf[0] = 0xe616;
6419 }
6420
6421 static void
6422 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6423 {
6424   slotbuf[0] = 0xb130;
6425 }
6426
6427 static void
6428 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6429 {
6430   slotbuf[0] = 0xb131;
6431 }
6432
6433 static void
6434 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6435 {
6436   slotbuf[0] = 0xb116;
6437 }
6438
6439 static void
6440 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6441 {
6442   slotbuf[0] = 0xd130;
6443 }
6444
6445 static void
6446 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6447 {
6448   slotbuf[0] = 0xd131;
6449 }
6450
6451 static void
6452 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6453 {
6454   slotbuf[0] = 0xd116;
6455 }
6456
6457 static void
6458 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6459 {
6460   slotbuf[0] = 0xb230;
6461 }
6462
6463 static void
6464 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6465 {
6466   slotbuf[0] = 0xb231;
6467 }
6468
6469 static void
6470 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6471 {
6472   slotbuf[0] = 0xb216;
6473 }
6474
6475 static void
6476 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6477 {
6478   slotbuf[0] = 0xd230;
6479 }
6480
6481 static void
6482 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6483 {
6484   slotbuf[0] = 0xd231;
6485 }
6486
6487 static void
6488 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6489 {
6490   slotbuf[0] = 0xd216;
6491 }
6492
6493 static void
6494 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6495 {
6496   slotbuf[0] = 0xb330;
6497 }
6498
6499 static void
6500 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6501 {
6502   slotbuf[0] = 0xb331;
6503 }
6504
6505 static void
6506 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6507 {
6508   slotbuf[0] = 0xb316;
6509 }
6510
6511 static void
6512 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6513 {
6514   slotbuf[0] = 0xd330;
6515 }
6516
6517 static void
6518 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6519 {
6520   slotbuf[0] = 0xd331;
6521 }
6522
6523 static void
6524 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6525 {
6526   slotbuf[0] = 0xd316;
6527 }
6528
6529 static void
6530 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6531 {
6532   slotbuf[0] = 0xb430;
6533 }
6534
6535 static void
6536 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6537 {
6538   slotbuf[0] = 0xb431;
6539 }
6540
6541 static void
6542 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6543 {
6544   slotbuf[0] = 0xb416;
6545 }
6546
6547 static void
6548 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6549 {
6550   slotbuf[0] = 0xd430;
6551 }
6552
6553 static void
6554 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6555 {
6556   slotbuf[0] = 0xd431;
6557 }
6558
6559 static void
6560 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6561 {
6562   slotbuf[0] = 0xd416;
6563 }
6564
6565 static void
6566 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6567 {
6568   slotbuf[0] = 0xb530;
6569 }
6570
6571 static void
6572 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6573 {
6574   slotbuf[0] = 0xb531;
6575 }
6576
6577 static void
6578 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6579 {
6580   slotbuf[0] = 0xb516;
6581 }
6582
6583 static void
6584 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6585 {
6586   slotbuf[0] = 0xd530;
6587 }
6588
6589 static void
6590 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6591 {
6592   slotbuf[0] = 0xd531;
6593 }
6594
6595 static void
6596 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6597 {
6598   slotbuf[0] = 0xd516;
6599 }
6600
6601 static void
6602 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6603 {
6604   slotbuf[0] = 0xb630;
6605 }
6606
6607 static void
6608 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6609 {
6610   slotbuf[0] = 0xb631;
6611 }
6612
6613 static void
6614 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6615 {
6616   slotbuf[0] = 0xb616;
6617 }
6618
6619 static void
6620 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6621 {
6622   slotbuf[0] = 0xd630;
6623 }
6624
6625 static void
6626 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6627 {
6628   slotbuf[0] = 0xd631;
6629 }
6630
6631 static void
6632 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6633 {
6634   slotbuf[0] = 0xd616;
6635 }
6636
6637 static void
6638 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6639 {
6640   slotbuf[0] = 0xb730;
6641 }
6642
6643 static void
6644 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6645 {
6646   slotbuf[0] = 0xb731;
6647 }
6648
6649 static void
6650 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6651 {
6652   slotbuf[0] = 0xb716;
6653 }
6654
6655 static void
6656 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6657 {
6658   slotbuf[0] = 0xd730;
6659 }
6660
6661 static void
6662 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6663 {
6664   slotbuf[0] = 0xd731;
6665 }
6666
6667 static void
6668 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6669 {
6670   slotbuf[0] = 0xd716;
6671 }
6672
6673 static void
6674 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6675 {
6676   slotbuf[0] = 0xc230;
6677 }
6678
6679 static void
6680 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6681 {
6682   slotbuf[0] = 0xc231;
6683 }
6684
6685 static void
6686 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6687 {
6688   slotbuf[0] = 0xc216;
6689 }
6690
6691 static void
6692 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6693 {
6694   slotbuf[0] = 0xc330;
6695 }
6696
6697 static void
6698 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6699 {
6700   slotbuf[0] = 0xc331;
6701 }
6702
6703 static void
6704 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6705 {
6706   slotbuf[0] = 0xc316;
6707 }
6708
6709 static void
6710 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6711 {
6712   slotbuf[0] = 0xc430;
6713 }
6714
6715 static void
6716 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6717 {
6718   slotbuf[0] = 0xc431;
6719 }
6720
6721 static void
6722 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6723 {
6724   slotbuf[0] = 0xc416;
6725 }
6726
6727 static void
6728 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6729 {
6730   slotbuf[0] = 0xc530;
6731 }
6732
6733 static void
6734 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6735 {
6736   slotbuf[0] = 0xc531;
6737 }
6738
6739 static void
6740 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
6741 {
6742   slotbuf[0] = 0xc516;
6743 }
6744
6745 static void
6746 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6747 {
6748   slotbuf[0] = 0xc630;
6749 }
6750
6751 static void
6752 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6753 {
6754   slotbuf[0] = 0xc631;
6755 }
6756
6757 static void
6758 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
6759 {
6760   slotbuf[0] = 0xc616;
6761 }
6762
6763 static void
6764 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6765 {
6766   slotbuf[0] = 0xc730;
6767 }
6768
6769 static void
6770 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6771 {
6772   slotbuf[0] = 0xc731;
6773 }
6774
6775 static void
6776 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
6777 {
6778   slotbuf[0] = 0xc716;
6779 }
6780
6781 static void
6782 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6783 {
6784   slotbuf[0] = 0xee30;
6785 }
6786
6787 static void
6788 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6789 {
6790   slotbuf[0] = 0xee31;
6791 }
6792
6793 static void
6794 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6795 {
6796   slotbuf[0] = 0xee16;
6797 }
6798
6799 static void
6800 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6801 {
6802   slotbuf[0] = 0xc030;
6803 }
6804
6805 static void
6806 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6807 {
6808   slotbuf[0] = 0xc031;
6809 }
6810
6811 static void
6812 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6813 {
6814   slotbuf[0] = 0xc016;
6815 }
6816
6817 static void
6818 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6819 {
6820   slotbuf[0] = 0xe830;
6821 }
6822
6823 static void
6824 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6825 {
6826   slotbuf[0] = 0xe831;
6827 }
6828
6829 static void
6830 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
6831 {
6832   slotbuf[0] = 0xe816;
6833 }
6834
6835 static void
6836 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6837 {
6838   slotbuf[0] = 0xf430;
6839 }
6840
6841 static void
6842 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6843 {
6844   slotbuf[0] = 0xf431;
6845 }
6846
6847 static void
6848 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6849 {
6850   slotbuf[0] = 0xf416;
6851 }
6852
6853 static void
6854 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6855 {
6856   slotbuf[0] = 0xf530;
6857 }
6858
6859 static void
6860 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6861 {
6862   slotbuf[0] = 0xf531;
6863 }
6864
6865 static void
6866 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6867 {
6868   slotbuf[0] = 0xf516;
6869 }
6870
6871 static void
6872 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
6873 {
6874   slotbuf[0] = 0xeb30;
6875 }
6876
6877 static void
6878 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6879 {
6880   slotbuf[0] = 0xe730;
6881 }
6882
6883 static void
6884 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6885 {
6886   slotbuf[0] = 0xe731;
6887 }
6888
6889 static void
6890 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6891 {
6892   slotbuf[0] = 0xe716;
6893 }
6894
6895 static void
6896 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
6897 {
6898   slotbuf[0] = 0x1c;
6899 }
6900
6901 static void
6902 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
6903 {
6904   slotbuf[0] = 0x1d;
6905 }
6906
6907 static void
6908 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6909 {
6910   slotbuf[0] = 0x10300;
6911 }
6912
6913 static void
6914 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6915 {
6916   slotbuf[0] = 0x700;
6917 }
6918
6919 static void
6920 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6921 {
6922   slotbuf[0] = 0xe230;
6923 }
6924
6925 static void
6926 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
6927 {
6928   slotbuf[0] = 0xe231;
6929 }
6930
6931 static void
6932 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
6933 {
6934   slotbuf[0] = 0xe331;
6935 }
6936
6937 static void
6938 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6939 {
6940   slotbuf[0] = 0xe430;
6941 }
6942
6943 static void
6944 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6945 {
6946   slotbuf[0] = 0xe431;
6947 }
6948
6949 static void
6950 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
6951 {
6952   slotbuf[0] = 0xe416;
6953 }
6954
6955 static void
6956 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
6957 {
6958   slotbuf[0] = 0x400;
6959 }
6960
6961 static void
6962 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6963 {
6964   slotbuf[0] = 0xd20f;
6965 }
6966
6967 static void
6968 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6969 {
6970   slotbuf[0] = 0x9030;
6971 }
6972
6973 static void
6974 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6975 {
6976   slotbuf[0] = 0x9031;
6977 }
6978
6979 static void
6980 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6981 {
6982   slotbuf[0] = 0x9016;
6983 }
6984
6985 static void
6986 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6987 {
6988   slotbuf[0] = 0xa030;
6989 }
6990
6991 static void
6992 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6993 {
6994   slotbuf[0] = 0xa031;
6995 }
6996
6997 static void
6998 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6999 {
7000   slotbuf[0] = 0xa016;
7001 }
7002
7003 static void
7004 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7005 {
7006   slotbuf[0] = 0x9130;
7007 }
7008
7009 static void
7010 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7011 {
7012   slotbuf[0] = 0x9131;
7013 }
7014
7015 static void
7016 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7017 {
7018   slotbuf[0] = 0x9116;
7019 }
7020
7021 static void
7022 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7023 {
7024   slotbuf[0] = 0xa130;
7025 }
7026
7027 static void
7028 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7029 {
7030   slotbuf[0] = 0xa131;
7031 }
7032
7033 static void
7034 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7035 {
7036   slotbuf[0] = 0xa116;
7037 }
7038
7039 static void
7040 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7041 {
7042   slotbuf[0] = 0x8030;
7043 }
7044
7045 static void
7046 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7047 {
7048   slotbuf[0] = 0x8031;
7049 }
7050
7051 static void
7052 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7053 {
7054   slotbuf[0] = 0x8016;
7055 }
7056
7057 static void
7058 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7059 {
7060   slotbuf[0] = 0x8130;
7061 }
7062
7063 static void
7064 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7065 {
7066   slotbuf[0] = 0x8131;
7067 }
7068
7069 static void
7070 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7071 {
7072   slotbuf[0] = 0x8116;
7073 }
7074
7075 static void
7076 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7077 {
7078   slotbuf[0] = 0x6030;
7079 }
7080
7081 static void
7082 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7083 {
7084   slotbuf[0] = 0x6031;
7085 }
7086
7087 static void
7088 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7089 {
7090   slotbuf[0] = 0x6016;
7091 }
7092
7093 static void
7094 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7095 {
7096   slotbuf[0] = 0xe930;
7097 }
7098
7099 static void
7100 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7101 {
7102   slotbuf[0] = 0xe931;
7103 }
7104
7105 static void
7106 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7107 {
7108   slotbuf[0] = 0xe916;
7109 }
7110
7111 static void
7112 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7113 {
7114   slotbuf[0] = 0xec30;
7115 }
7116
7117 static void
7118 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7119 {
7120   slotbuf[0] = 0xec31;
7121 }
7122
7123 static void
7124 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7125 {
7126   slotbuf[0] = 0xec16;
7127 }
7128
7129 static void
7130 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
7131 {
7132   slotbuf[0] = 0xed30;
7133 }
7134
7135 static void
7136 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
7137 {
7138   slotbuf[0] = 0xed31;
7139 }
7140
7141 static void
7142 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
7143 {
7144   slotbuf[0] = 0xed16;
7145 }
7146
7147 static void
7148 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7149 {
7150   slotbuf[0] = 0x6830;
7151 }
7152
7153 static void
7154 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7155 {
7156   slotbuf[0] = 0x6831;
7157 }
7158
7159 static void
7160 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7161 {
7162   slotbuf[0] = 0x6816;
7163 }
7164
7165 static void
7166 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
7167 {
7168   slotbuf[0] = 0xe1f;
7169 }
7170
7171 static void
7172 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
7173 {
7174   slotbuf[0] = 0x10e1f;
7175 }
7176
7177 static void
7178 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7179 {
7180   slotbuf[0] = 0x5931;
7181 }
7182
7183 static void
7184 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7185 {
7186   slotbuf[0] = 0xea30;
7187 }
7188
7189 static void
7190 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7191 {
7192   slotbuf[0] = 0xea31;
7193 }
7194
7195 static void
7196 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7197 {
7198   slotbuf[0] = 0xea16;
7199 }
7200
7201 static void
7202 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7203 {
7204   slotbuf[0] = 0xf030;
7205 }
7206
7207 static void
7208 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7209 {
7210   slotbuf[0] = 0xf031;
7211 }
7212
7213 static void
7214 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7215 {
7216   slotbuf[0] = 0xf016;
7217 }
7218
7219 static void
7220 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7221 {
7222   slotbuf[0] = 0xf130;
7223 }
7224
7225 static void
7226 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7227 {
7228   slotbuf[0] = 0xf131;
7229 }
7230
7231 static void
7232 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7233 {
7234   slotbuf[0] = 0xf116;
7235 }
7236
7237 static void
7238 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7239 {
7240   slotbuf[0] = 0xf230;
7241 }
7242
7243 static void
7244 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7245 {
7246   slotbuf[0] = 0xf231;
7247 }
7248
7249 static void
7250 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7251 {
7252   slotbuf[0] = 0xf216;
7253 }
7254
7255 static void
7256 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
7257 {
7258   slotbuf[0] = 0x2c0700;
7259 }
7260
7261 static void
7262 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
7263 {
7264   slotbuf[0] = 0x2e0700;
7265 }
7266
7267 static void
7268 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7269 {
7270   slotbuf[0] = 0x2d0700;
7271 }
7272
7273 static void
7274 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7275 {
7276   slotbuf[0] = 0x2d0720;
7277 }
7278
7279 static void
7280 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7281 {
7282   slotbuf[0] = 0x2d0730;
7283 }
7284
7285 static void
7286 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
7287 {
7288   slotbuf[0] = 0x2f0700;
7289 }
7290
7291 static void
7292 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
7293 {
7294   slotbuf[0] = 0x1f;
7295 }
7296
7297 static void
7298 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7299 {
7300   slotbuf[0] = 0x21f;
7301 }
7302
7303 static void
7304 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
7305 {
7306   slotbuf[0] = 0x11f;
7307 }
7308
7309 static void
7310 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7311 {
7312   slotbuf[0] = 0x31f;
7313 }
7314
7315 static void
7316 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7317 {
7318   slotbuf[0] = 0x240700;
7319 }
7320
7321 static void
7322 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
7323 {
7324   slotbuf[0] = 0x250700;
7325 }
7326
7327 static void
7328 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7329 {
7330   slotbuf[0] = 0x280740;
7331 }
7332
7333 static void
7334 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
7335 {
7336   slotbuf[0] = 0x280750;
7337 }
7338
7339 static void
7340 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
7341 {
7342   slotbuf[0] = 0x260700;
7343 }
7344
7345 static void
7346 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
7347 {
7348   slotbuf[0] = 0x270700;
7349 }
7350
7351 static void
7352 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7353 {
7354   slotbuf[0] = 0x200700;
7355 }
7356
7357 static void
7358 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7359 {
7360   slotbuf[0] = 0x210700;
7361 }
7362
7363 static void
7364 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
7365 {
7366   slotbuf[0] = 0x220700;
7367 }
7368
7369 static void
7370 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
7371 {
7372   slotbuf[0] = 0x230700;
7373 }
7374
7375 static void
7376 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7377 {
7378   slotbuf[0] = 0x280700;
7379 }
7380
7381 static void
7382 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7383 {
7384   slotbuf[0] = 0x280720;
7385 }
7386
7387 static void
7388 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7389 {
7390   slotbuf[0] = 0x280730;
7391 }
7392
7393 static void
7394 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
7395 {
7396   slotbuf[0] = 0x91f;
7397 }
7398
7399 static void
7400 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
7401 {
7402   slotbuf[0] = 0x81f;
7403 }
7404
7405 static void
7406 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7407 {
7408   slotbuf[0] = 0x5331;
7409 }
7410
7411 static void
7412 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7413 {
7414   slotbuf[0] = 0x5330;
7415 }
7416
7417 static void
7418 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7419 {
7420   slotbuf[0] = 0x5316;
7421 }
7422
7423 static void
7424 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7425 {
7426   slotbuf[0] = 0x5a30;
7427 }
7428
7429 static void
7430 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7431 {
7432   slotbuf[0] = 0x5a31;
7433 }
7434
7435 static void
7436 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7437 {
7438   slotbuf[0] = 0x5a16;
7439 }
7440
7441 static void
7442 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7443 {
7444   slotbuf[0] = 0x5b30;
7445 }
7446
7447 static void
7448 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7449 {
7450   slotbuf[0] = 0x5b31;
7451 }
7452
7453 static void
7454 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7455 {
7456   slotbuf[0] = 0x5b16;
7457 }
7458
7459 static void
7460 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7461 {
7462   slotbuf[0] = 0x5c30;
7463 }
7464
7465 static void
7466 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7467 {
7468   slotbuf[0] = 0x5c31;
7469 }
7470
7471 static void
7472 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7473 {
7474   slotbuf[0] = 0x5c16;
7475 }
7476
7477 static void
7478 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7479 {
7480   slotbuf[0] = 0xc05;
7481 }
7482
7483 static void
7484 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7485 {
7486   slotbuf[0] = 0xd05;
7487 }
7488
7489 static void
7490 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7491 {
7492   slotbuf[0] = 0xb05;
7493 }
7494
7495 static void
7496 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7497 {
7498   slotbuf[0] = 0xf05;
7499 }
7500
7501 static void
7502 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7503 {
7504   slotbuf[0] = 0xe05;
7505 }
7506
7507 static void
7508 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7509 {
7510   slotbuf[0] = 0x405;
7511 }
7512
7513 static void
7514 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7515 {
7516   slotbuf[0] = 0x505;
7517 }
7518
7519 static void
7520 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7521 {
7522   slotbuf[0] = 0x305;
7523 }
7524
7525 static void
7526 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7527 {
7528   slotbuf[0] = 0x705;
7529 }
7530
7531 static void
7532 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7533 {
7534   slotbuf[0] = 0x605;
7535 }
7536
7537 static void
7538 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
7539 {
7540   slotbuf[0] = 0xf1f;
7541 }
7542
7543 static void
7544 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
7545 {
7546   slotbuf[0] = 0x105;
7547 }
7548
7549 static void
7550 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
7551 {
7552   slotbuf[0] = 0x905;
7553 }
7554
7555 static void
7556 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7557 {
7558   slotbuf[0] = 0xe030;
7559 }
7560
7561 static void
7562 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7563 {
7564   slotbuf[0] = 0xe031;
7565 }
7566
7567 static void
7568 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7569 {
7570   slotbuf[0] = 0xe016;
7571 }
7572
7573 static void
7574 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7575 {
7576   slotbuf[0] = 0x33;
7577 }
7578
7579 static void
7580 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
7581 {
7582   slotbuf[0] = 0x34;
7583 }
7584
7585 static void
7586 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
7587 {
7588   slotbuf[0] = 0x35;
7589 }
7590
7591 static void
7592 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7593 {
7594   slotbuf[0] = 0x36;
7595 }
7596
7597 static void
7598 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7599 {
7600   slotbuf[0] = 0x37;
7601 }
7602
7603 static void
7604 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
7605 {
7606   slotbuf[0] = 0xe04;
7607 }
7608
7609 static void
7610 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
7611 {
7612   slotbuf[0] = 0xf04;
7613 }
7614
7615 static void
7616 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
7617 {
7618   slotbuf[0] = 0x32;
7619 }
7620
7621 static void
7622 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
7623 {
7624   slotbuf[0] = 0x200b00;
7625 }
7626
7627 static void
7628 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
7629 {
7630   slotbuf[0] = 0x200f00;
7631 }
7632
7633 static void
7634 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
7635 {
7636   slotbuf[0] = 0x200e00;
7637 }
7638
7639 static void
7640 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7641 {
7642   slotbuf[0] = 0xc30;
7643 }
7644
7645 static void
7646 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7647 {
7648   slotbuf[0] = 0xc31;
7649 }
7650
7651 static void
7652 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7653 {
7654   slotbuf[0] = 0xc16;
7655 }
7656
7657 static void
7658 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
7659 {
7660   slotbuf[0] = 0x2c;
7661 }
7662
7663 static void
7664 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
7665 {
7666   slotbuf[0] = 0x2d;
7667 }
7668
7669 static void
7670 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7671 {
7672   slotbuf[0] = 0x2e;
7673 }
7674
7675 static void
7676 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
7677 {
7678   slotbuf[0] = 0x2f;
7679 }
7680
7681 static void
7682 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
7683 {
7684   slotbuf[0] = 0x28;
7685 }
7686
7687 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
7688   Opcode_excw_Slot_inst_encode, 0, 0
7689 };
7690
7691 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
7692   Opcode_rfe_Slot_inst_encode, 0, 0
7693 };
7694
7695 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
7696   Opcode_rfde_Slot_inst_encode, 0, 0
7697 };
7698
7699 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
7700   Opcode_syscall_Slot_inst_encode, 0, 0
7701 };
7702
7703 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
7704   Opcode_simcall_Slot_inst_encode, 0, 0
7705 };
7706
7707 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
7708   Opcode_call12_Slot_inst_encode, 0, 0
7709 };
7710
7711 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
7712   Opcode_call8_Slot_inst_encode, 0, 0
7713 };
7714
7715 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
7716   Opcode_call4_Slot_inst_encode, 0, 0
7717 };
7718
7719 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
7720   Opcode_callx12_Slot_inst_encode, 0, 0
7721 };
7722
7723 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
7724   Opcode_callx8_Slot_inst_encode, 0, 0
7725 };
7726
7727 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
7728   Opcode_callx4_Slot_inst_encode, 0, 0
7729 };
7730
7731 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
7732   Opcode_entry_Slot_inst_encode, 0, 0
7733 };
7734
7735 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
7736   Opcode_movsp_Slot_inst_encode, 0, 0
7737 };
7738
7739 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
7740   Opcode_rotw_Slot_inst_encode, 0, 0
7741 };
7742
7743 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
7744   Opcode_retw_Slot_inst_encode, 0, 0
7745 };
7746
7747 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
7748   0, 0, Opcode_retw_n_Slot_inst16b_encode
7749 };
7750
7751 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
7752   Opcode_rfwo_Slot_inst_encode, 0, 0
7753 };
7754
7755 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
7756   Opcode_rfwu_Slot_inst_encode, 0, 0
7757 };
7758
7759 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
7760   Opcode_l32e_Slot_inst_encode, 0, 0
7761 };
7762
7763 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
7764   Opcode_s32e_Slot_inst_encode, 0, 0
7765 };
7766
7767 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
7768   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
7769 };
7770
7771 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
7772   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
7773 };
7774
7775 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
7776   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
7777 };
7778
7779 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
7780   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
7781 };
7782
7783 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
7784   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
7785 };
7786
7787 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
7788   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
7789 };
7790
7791 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
7792   0, Opcode_add_n_Slot_inst16a_encode, 0
7793 };
7794
7795 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
7796   0, Opcode_addi_n_Slot_inst16a_encode, 0
7797 };
7798
7799 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
7800   0, 0, Opcode_beqz_n_Slot_inst16b_encode
7801 };
7802
7803 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
7804   0, 0, Opcode_bnez_n_Slot_inst16b_encode
7805 };
7806
7807 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
7808   0, 0, Opcode_ill_n_Slot_inst16b_encode
7809 };
7810
7811 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
7812   0, Opcode_l32i_n_Slot_inst16a_encode, 0
7813 };
7814
7815 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
7816   0, 0, Opcode_mov_n_Slot_inst16b_encode
7817 };
7818
7819 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
7820   0, 0, Opcode_movi_n_Slot_inst16b_encode
7821 };
7822
7823 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
7824   0, 0, Opcode_nop_n_Slot_inst16b_encode
7825 };
7826
7827 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
7828   0, 0, Opcode_ret_n_Slot_inst16b_encode
7829 };
7830
7831 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
7832   0, Opcode_s32i_n_Slot_inst16a_encode, 0
7833 };
7834
7835 xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
7836   Opcode_rur_threadptr_Slot_inst_encode, 0, 0
7837 };
7838
7839 xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
7840   Opcode_wur_threadptr_Slot_inst_encode, 0, 0
7841 };
7842
7843 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
7844   Opcode_addi_Slot_inst_encode, 0, 0
7845 };
7846
7847 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
7848   Opcode_addmi_Slot_inst_encode, 0, 0
7849 };
7850
7851 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
7852   Opcode_add_Slot_inst_encode, 0, 0
7853 };
7854
7855 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
7856   Opcode_sub_Slot_inst_encode, 0, 0
7857 };
7858
7859 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
7860   Opcode_addx2_Slot_inst_encode, 0, 0
7861 };
7862
7863 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
7864   Opcode_addx4_Slot_inst_encode, 0, 0
7865 };
7866
7867 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
7868   Opcode_addx8_Slot_inst_encode, 0, 0
7869 };
7870
7871 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
7872   Opcode_subx2_Slot_inst_encode, 0, 0
7873 };
7874
7875 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
7876   Opcode_subx4_Slot_inst_encode, 0, 0
7877 };
7878
7879 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
7880   Opcode_subx8_Slot_inst_encode, 0, 0
7881 };
7882
7883 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
7884   Opcode_and_Slot_inst_encode, 0, 0
7885 };
7886
7887 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
7888   Opcode_or_Slot_inst_encode, 0, 0
7889 };
7890
7891 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
7892   Opcode_xor_Slot_inst_encode, 0, 0
7893 };
7894
7895 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
7896   Opcode_beqi_Slot_inst_encode, 0, 0
7897 };
7898
7899 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
7900   Opcode_bnei_Slot_inst_encode, 0, 0
7901 };
7902
7903 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
7904   Opcode_bgei_Slot_inst_encode, 0, 0
7905 };
7906
7907 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
7908   Opcode_blti_Slot_inst_encode, 0, 0
7909 };
7910
7911 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
7912   Opcode_bbci_Slot_inst_encode, 0, 0
7913 };
7914
7915 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
7916   Opcode_bbsi_Slot_inst_encode, 0, 0
7917 };
7918
7919 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
7920   Opcode_bgeui_Slot_inst_encode, 0, 0
7921 };
7922
7923 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
7924   Opcode_bltui_Slot_inst_encode, 0, 0
7925 };
7926
7927 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
7928   Opcode_beq_Slot_inst_encode, 0, 0
7929 };
7930
7931 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
7932   Opcode_bne_Slot_inst_encode, 0, 0
7933 };
7934
7935 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
7936   Opcode_bge_Slot_inst_encode, 0, 0
7937 };
7938
7939 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
7940   Opcode_blt_Slot_inst_encode, 0, 0
7941 };
7942
7943 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
7944   Opcode_bgeu_Slot_inst_encode, 0, 0
7945 };
7946
7947 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
7948   Opcode_bltu_Slot_inst_encode, 0, 0
7949 };
7950
7951 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
7952   Opcode_bany_Slot_inst_encode, 0, 0
7953 };
7954
7955 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
7956   Opcode_bnone_Slot_inst_encode, 0, 0
7957 };
7958
7959 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
7960   Opcode_ball_Slot_inst_encode, 0, 0
7961 };
7962
7963 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
7964   Opcode_bnall_Slot_inst_encode, 0, 0
7965 };
7966
7967 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
7968   Opcode_bbc_Slot_inst_encode, 0, 0
7969 };
7970
7971 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
7972   Opcode_bbs_Slot_inst_encode, 0, 0
7973 };
7974
7975 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
7976   Opcode_beqz_Slot_inst_encode, 0, 0
7977 };
7978
7979 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
7980   Opcode_bnez_Slot_inst_encode, 0, 0
7981 };
7982
7983 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
7984   Opcode_bgez_Slot_inst_encode, 0, 0
7985 };
7986
7987 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
7988   Opcode_bltz_Slot_inst_encode, 0, 0
7989 };
7990
7991 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
7992   Opcode_call0_Slot_inst_encode, 0, 0
7993 };
7994
7995 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
7996   Opcode_callx0_Slot_inst_encode, 0, 0
7997 };
7998
7999 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
8000   Opcode_extui_Slot_inst_encode, 0, 0
8001 };
8002
8003 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
8004   Opcode_ill_Slot_inst_encode, 0, 0
8005 };
8006
8007 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
8008   Opcode_j_Slot_inst_encode, 0, 0
8009 };
8010
8011 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
8012   Opcode_jx_Slot_inst_encode, 0, 0
8013 };
8014
8015 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
8016   Opcode_l16ui_Slot_inst_encode, 0, 0
8017 };
8018
8019 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
8020   Opcode_l16si_Slot_inst_encode, 0, 0
8021 };
8022
8023 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
8024   Opcode_l32i_Slot_inst_encode, 0, 0
8025 };
8026
8027 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
8028   Opcode_l32r_Slot_inst_encode, 0, 0
8029 };
8030
8031 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
8032   Opcode_l8ui_Slot_inst_encode, 0, 0
8033 };
8034
8035 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
8036   Opcode_loop_Slot_inst_encode, 0, 0
8037 };
8038
8039 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
8040   Opcode_loopnez_Slot_inst_encode, 0, 0
8041 };
8042
8043 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
8044   Opcode_loopgtz_Slot_inst_encode, 0, 0
8045 };
8046
8047 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
8048   Opcode_movi_Slot_inst_encode, 0, 0
8049 };
8050
8051 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
8052   Opcode_moveqz_Slot_inst_encode, 0, 0
8053 };
8054
8055 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
8056   Opcode_movnez_Slot_inst_encode, 0, 0
8057 };
8058
8059 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
8060   Opcode_movltz_Slot_inst_encode, 0, 0
8061 };
8062
8063 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
8064   Opcode_movgez_Slot_inst_encode, 0, 0
8065 };
8066
8067 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
8068   Opcode_neg_Slot_inst_encode, 0, 0
8069 };
8070
8071 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
8072   Opcode_abs_Slot_inst_encode, 0, 0
8073 };
8074
8075 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
8076   Opcode_nop_Slot_inst_encode, 0, 0
8077 };
8078
8079 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
8080   Opcode_ret_Slot_inst_encode, 0, 0
8081 };
8082
8083 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
8084   Opcode_s16i_Slot_inst_encode, 0, 0
8085 };
8086
8087 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
8088   Opcode_s32i_Slot_inst_encode, 0, 0
8089 };
8090
8091 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
8092   Opcode_s8i_Slot_inst_encode, 0, 0
8093 };
8094
8095 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
8096   Opcode_ssr_Slot_inst_encode, 0, 0
8097 };
8098
8099 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
8100   Opcode_ssl_Slot_inst_encode, 0, 0
8101 };
8102
8103 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
8104   Opcode_ssa8l_Slot_inst_encode, 0, 0
8105 };
8106
8107 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
8108   Opcode_ssa8b_Slot_inst_encode, 0, 0
8109 };
8110
8111 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
8112   Opcode_ssai_Slot_inst_encode, 0, 0
8113 };
8114
8115 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
8116   Opcode_sll_Slot_inst_encode, 0, 0
8117 };
8118
8119 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
8120   Opcode_src_Slot_inst_encode, 0, 0
8121 };
8122
8123 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
8124   Opcode_srl_Slot_inst_encode, 0, 0
8125 };
8126
8127 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
8128   Opcode_sra_Slot_inst_encode, 0, 0
8129 };
8130
8131 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
8132   Opcode_slli_Slot_inst_encode, 0, 0
8133 };
8134
8135 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
8136   Opcode_srai_Slot_inst_encode, 0, 0
8137 };
8138
8139 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
8140   Opcode_srli_Slot_inst_encode, 0, 0
8141 };
8142
8143 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
8144   Opcode_memw_Slot_inst_encode, 0, 0
8145 };
8146
8147 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
8148   Opcode_extw_Slot_inst_encode, 0, 0
8149 };
8150
8151 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
8152   Opcode_isync_Slot_inst_encode, 0, 0
8153 };
8154
8155 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
8156   Opcode_rsync_Slot_inst_encode, 0, 0
8157 };
8158
8159 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
8160   Opcode_esync_Slot_inst_encode, 0, 0
8161 };
8162
8163 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
8164   Opcode_dsync_Slot_inst_encode, 0, 0
8165 };
8166
8167 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
8168   Opcode_rsil_Slot_inst_encode, 0, 0
8169 };
8170
8171 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
8172   Opcode_rsr_lend_Slot_inst_encode, 0, 0
8173 };
8174
8175 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
8176   Opcode_wsr_lend_Slot_inst_encode, 0, 0
8177 };
8178
8179 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
8180   Opcode_xsr_lend_Slot_inst_encode, 0, 0
8181 };
8182
8183 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
8184   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
8185 };
8186
8187 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
8188   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
8189 };
8190
8191 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
8192   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
8193 };
8194
8195 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
8196   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
8197 };
8198
8199 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
8200   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
8201 };
8202
8203 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
8204   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
8205 };
8206
8207 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
8208   Opcode_rsr_sar_Slot_inst_encode, 0, 0
8209 };
8210
8211 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
8212   Opcode_wsr_sar_Slot_inst_encode, 0, 0
8213 };
8214
8215 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
8216   Opcode_xsr_sar_Slot_inst_encode, 0, 0
8217 };
8218
8219 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
8220   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
8221 };
8222
8223 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
8224   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
8225 };
8226
8227 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
8228   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
8229 };
8230
8231 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
8232   Opcode_rsr_176_Slot_inst_encode, 0, 0
8233 };
8234
8235 xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
8236   Opcode_wsr_176_Slot_inst_encode, 0, 0
8237 };
8238
8239 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
8240   Opcode_rsr_208_Slot_inst_encode, 0, 0
8241 };
8242
8243 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
8244   Opcode_rsr_ps_Slot_inst_encode, 0, 0
8245 };
8246
8247 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
8248   Opcode_wsr_ps_Slot_inst_encode, 0, 0
8249 };
8250
8251 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
8252   Opcode_xsr_ps_Slot_inst_encode, 0, 0
8253 };
8254
8255 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
8256   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
8257 };
8258
8259 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
8260   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
8261 };
8262
8263 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
8264   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
8265 };
8266
8267 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
8268   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
8269 };
8270
8271 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
8272   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
8273 };
8274
8275 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
8276   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
8277 };
8278
8279 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
8280   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
8281 };
8282
8283 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
8284   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
8285 };
8286
8287 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
8288   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
8289 };
8290
8291 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
8292   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
8293 };
8294
8295 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
8296   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
8297 };
8298
8299 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
8300   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
8301 };
8302
8303 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
8304   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
8305 };
8306
8307 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
8308   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
8309 };
8310
8311 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
8312   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
8313 };
8314
8315 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
8316   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
8317 };
8318
8319 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
8320   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
8321 };
8322
8323 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
8324   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
8325 };
8326
8327 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
8328   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
8329 };
8330
8331 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
8332   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
8333 };
8334
8335 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
8336   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
8337 };
8338
8339 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
8340   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
8341 };
8342
8343 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
8344   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
8345 };
8346
8347 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
8348   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
8349 };
8350
8351 xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
8352   Opcode_rsr_epc5_Slot_inst_encode, 0, 0
8353 };
8354
8355 xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
8356   Opcode_wsr_epc5_Slot_inst_encode, 0, 0
8357 };
8358
8359 xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
8360   Opcode_xsr_epc5_Slot_inst_encode, 0, 0
8361 };
8362
8363 xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
8364   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
8365 };
8366
8367 xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
8368   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
8369 };
8370
8371 xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
8372   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
8373 };
8374
8375 xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
8376   Opcode_rsr_epc6_Slot_inst_encode, 0, 0
8377 };
8378
8379 xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
8380   Opcode_wsr_epc6_Slot_inst_encode, 0, 0
8381 };
8382
8383 xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
8384   Opcode_xsr_epc6_Slot_inst_encode, 0, 0
8385 };
8386
8387 xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
8388   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
8389 };
8390
8391 xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
8392   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
8393 };
8394
8395 xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
8396   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
8397 };
8398
8399 xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
8400   Opcode_rsr_epc7_Slot_inst_encode, 0, 0
8401 };
8402
8403 xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
8404   Opcode_wsr_epc7_Slot_inst_encode, 0, 0
8405 };
8406
8407 xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
8408   Opcode_xsr_epc7_Slot_inst_encode, 0, 0
8409 };
8410
8411 xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
8412   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
8413 };
8414
8415 xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
8416   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
8417 };
8418
8419 xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
8420   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
8421 };
8422
8423 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
8424   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
8425 };
8426
8427 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
8428   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
8429 };
8430
8431 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
8432   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
8433 };
8434
8435 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
8436   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
8437 };
8438
8439 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
8440   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
8441 };
8442
8443 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
8444   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
8445 };
8446
8447 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
8448   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
8449 };
8450
8451 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
8452   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
8453 };
8454
8455 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
8456   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
8457 };
8458
8459 xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
8460   Opcode_rsr_eps5_Slot_inst_encode, 0, 0
8461 };
8462
8463 xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
8464   Opcode_wsr_eps5_Slot_inst_encode, 0, 0
8465 };
8466
8467 xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
8468   Opcode_xsr_eps5_Slot_inst_encode, 0, 0
8469 };
8470
8471 xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
8472   Opcode_rsr_eps6_Slot_inst_encode, 0, 0
8473 };
8474
8475 xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
8476   Opcode_wsr_eps6_Slot_inst_encode, 0, 0
8477 };
8478
8479 xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
8480   Opcode_xsr_eps6_Slot_inst_encode, 0, 0
8481 };
8482
8483 xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
8484   Opcode_rsr_eps7_Slot_inst_encode, 0, 0
8485 };
8486
8487 xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
8488   Opcode_wsr_eps7_Slot_inst_encode, 0, 0
8489 };
8490
8491 xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
8492   Opcode_xsr_eps7_Slot_inst_encode, 0, 0
8493 };
8494
8495 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
8496   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
8497 };
8498
8499 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
8500   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
8501 };
8502
8503 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
8504   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
8505 };
8506
8507 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
8508   Opcode_rsr_depc_Slot_inst_encode, 0, 0
8509 };
8510
8511 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
8512   Opcode_wsr_depc_Slot_inst_encode, 0, 0
8513 };
8514
8515 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
8516   Opcode_xsr_depc_Slot_inst_encode, 0, 0
8517 };
8518
8519 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
8520   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
8521 };
8522
8523 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
8524   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
8525 };
8526
8527 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
8528   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
8529 };
8530
8531 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
8532   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
8533 };
8534
8535 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
8536   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
8537 };
8538
8539 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
8540   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
8541 };
8542
8543 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
8544   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
8545 };
8546
8547 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
8548   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
8549 };
8550
8551 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
8552   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
8553 };
8554
8555 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
8556   Opcode_rsr_prid_Slot_inst_encode, 0, 0
8557 };
8558
8559 xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
8560   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
8561 };
8562
8563 xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
8564   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
8565 };
8566
8567 xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
8568   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
8569 };
8570
8571 xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
8572   Opcode_mul16u_Slot_inst_encode, 0, 0
8573 };
8574
8575 xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
8576   Opcode_mul16s_Slot_inst_encode, 0, 0
8577 };
8578
8579 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
8580   Opcode_rfi_Slot_inst_encode, 0, 0
8581 };
8582
8583 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
8584   Opcode_waiti_Slot_inst_encode, 0, 0
8585 };
8586
8587 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
8588   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
8589 };
8590
8591 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
8592   Opcode_wsr_intset_Slot_inst_encode, 0, 0
8593 };
8594
8595 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
8596   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
8597 };
8598
8599 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
8600   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
8601 };
8602
8603 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
8604   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
8605 };
8606
8607 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
8608   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
8609 };
8610
8611 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
8612   Opcode_break_Slot_inst_encode, 0, 0
8613 };
8614
8615 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
8616   0, 0, Opcode_break_n_Slot_inst16b_encode
8617 };
8618
8619 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
8620   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
8621 };
8622
8623 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
8624   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
8625 };
8626
8627 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
8628   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
8629 };
8630
8631 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
8632   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
8633 };
8634
8635 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
8636   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
8637 };
8638
8639 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
8640   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
8641 };
8642
8643 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
8644   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
8645 };
8646
8647 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
8648   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
8649 };
8650
8651 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
8652   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
8653 };
8654
8655 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
8656   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
8657 };
8658
8659 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
8660   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
8661 };
8662
8663 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
8664   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
8665 };
8666
8667 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
8668   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
8669 };
8670
8671 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
8672   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
8673 };
8674
8675 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
8676   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
8677 };
8678
8679 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
8680   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
8681 };
8682
8683 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
8684   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
8685 };
8686
8687 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
8688   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
8689 };
8690
8691 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
8692   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
8693 };
8694
8695 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
8696   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
8697 };
8698
8699 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
8700   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
8701 };
8702
8703 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
8704   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
8705 };
8706
8707 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
8708   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
8709 };
8710
8711 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
8712   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
8713 };
8714
8715 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
8716   Opcode_rsr_icount_Slot_inst_encode, 0, 0
8717 };
8718
8719 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
8720   Opcode_wsr_icount_Slot_inst_encode, 0, 0
8721 };
8722
8723 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
8724   Opcode_xsr_icount_Slot_inst_encode, 0, 0
8725 };
8726
8727 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
8728   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
8729 };
8730
8731 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
8732   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
8733 };
8734
8735 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
8736   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
8737 };
8738
8739 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
8740   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
8741 };
8742
8743 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
8744   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
8745 };
8746
8747 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
8748   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
8749 };
8750
8751 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
8752   Opcode_rfdo_Slot_inst_encode, 0, 0
8753 };
8754
8755 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
8756   Opcode_rfdd_Slot_inst_encode, 0, 0
8757 };
8758
8759 xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
8760   Opcode_wsr_mmid_Slot_inst_encode, 0, 0
8761 };
8762
8763 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
8764   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
8765 };
8766
8767 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
8768   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
8769 };
8770
8771 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
8772   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
8773 };
8774
8775 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
8776   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
8777 };
8778
8779 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
8780   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
8781 };
8782
8783 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
8784   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
8785 };
8786
8787 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
8788   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
8789 };
8790
8791 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
8792   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
8793 };
8794
8795 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
8796   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
8797 };
8798
8799 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
8800   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
8801 };
8802
8803 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
8804   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
8805 };
8806
8807 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
8808   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
8809 };
8810
8811 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
8812   Opcode_ipf_Slot_inst_encode, 0, 0
8813 };
8814
8815 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
8816   Opcode_ihi_Slot_inst_encode, 0, 0
8817 };
8818
8819 xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
8820   Opcode_ipfl_Slot_inst_encode, 0, 0
8821 };
8822
8823 xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
8824   Opcode_ihu_Slot_inst_encode, 0, 0
8825 };
8826
8827 xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
8828   Opcode_iiu_Slot_inst_encode, 0, 0
8829 };
8830
8831 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
8832   Opcode_iii_Slot_inst_encode, 0, 0
8833 };
8834
8835 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
8836   Opcode_lict_Slot_inst_encode, 0, 0
8837 };
8838
8839 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
8840   Opcode_licw_Slot_inst_encode, 0, 0
8841 };
8842
8843 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
8844   Opcode_sict_Slot_inst_encode, 0, 0
8845 };
8846
8847 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
8848   Opcode_sicw_Slot_inst_encode, 0, 0
8849 };
8850
8851 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
8852   Opcode_dhwb_Slot_inst_encode, 0, 0
8853 };
8854
8855 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
8856   Opcode_dhwbi_Slot_inst_encode, 0, 0
8857 };
8858
8859 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
8860   Opcode_diwb_Slot_inst_encode, 0, 0
8861 };
8862
8863 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
8864   Opcode_diwbi_Slot_inst_encode, 0, 0
8865 };
8866
8867 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
8868   Opcode_dhi_Slot_inst_encode, 0, 0
8869 };
8870
8871 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
8872   Opcode_dii_Slot_inst_encode, 0, 0
8873 };
8874
8875 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
8876   Opcode_dpfr_Slot_inst_encode, 0, 0
8877 };
8878
8879 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
8880   Opcode_dpfw_Slot_inst_encode, 0, 0
8881 };
8882
8883 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
8884   Opcode_dpfro_Slot_inst_encode, 0, 0
8885 };
8886
8887 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
8888   Opcode_dpfwo_Slot_inst_encode, 0, 0
8889 };
8890
8891 xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
8892   Opcode_dpfl_Slot_inst_encode, 0, 0
8893 };
8894
8895 xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
8896   Opcode_dhu_Slot_inst_encode, 0, 0
8897 };
8898
8899 xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
8900   Opcode_diu_Slot_inst_encode, 0, 0
8901 };
8902
8903 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
8904   Opcode_sdct_Slot_inst_encode, 0, 0
8905 };
8906
8907 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
8908   Opcode_ldct_Slot_inst_encode, 0, 0
8909 };
8910
8911 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
8912   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
8913 };
8914
8915 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
8916   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
8917 };
8918
8919 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
8920   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
8921 };
8922
8923 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
8924   Opcode_rsr_rasid_Slot_inst_encode, 0, 0
8925 };
8926
8927 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
8928   Opcode_wsr_rasid_Slot_inst_encode, 0, 0
8929 };
8930
8931 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
8932   Opcode_xsr_rasid_Slot_inst_encode, 0, 0
8933 };
8934
8935 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
8936   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
8937 };
8938
8939 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
8940   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
8941 };
8942
8943 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
8944   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
8945 };
8946
8947 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
8948   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
8949 };
8950
8951 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
8952   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
8953 };
8954
8955 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
8956   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
8957 };
8958
8959 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
8960   Opcode_idtlb_Slot_inst_encode, 0, 0
8961 };
8962
8963 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
8964   Opcode_pdtlb_Slot_inst_encode, 0, 0
8965 };
8966
8967 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
8968   Opcode_rdtlb0_Slot_inst_encode, 0, 0
8969 };
8970
8971 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
8972   Opcode_rdtlb1_Slot_inst_encode, 0, 0
8973 };
8974
8975 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
8976   Opcode_wdtlb_Slot_inst_encode, 0, 0
8977 };
8978
8979 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
8980   Opcode_iitlb_Slot_inst_encode, 0, 0
8981 };
8982
8983 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
8984   Opcode_pitlb_Slot_inst_encode, 0, 0
8985 };
8986
8987 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
8988   Opcode_ritlb0_Slot_inst_encode, 0, 0
8989 };
8990
8991 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
8992   Opcode_ritlb1_Slot_inst_encode, 0, 0
8993 };
8994
8995 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
8996   Opcode_witlb_Slot_inst_encode, 0, 0
8997 };
8998
8999 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
9000   Opcode_ldpte_Slot_inst_encode, 0, 0
9001 };
9002
9003 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
9004   Opcode_hwwitlba_Slot_inst_encode, 0, 0
9005 };
9006
9007 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
9008   Opcode_hwwdtlba_Slot_inst_encode, 0, 0
9009 };
9010
9011 xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
9012   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
9013 };
9014
9015 xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
9016   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
9017 };
9018
9019 xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
9020   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
9021 };
9022
9023 xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
9024   Opcode_clamps_Slot_inst_encode, 0, 0
9025 };
9026
9027 xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
9028   Opcode_min_Slot_inst_encode, 0, 0
9029 };
9030
9031 xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
9032   Opcode_max_Slot_inst_encode, 0, 0
9033 };
9034
9035 xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
9036   Opcode_minu_Slot_inst_encode, 0, 0
9037 };
9038
9039 xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
9040   Opcode_maxu_Slot_inst_encode, 0, 0
9041 };
9042
9043 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
9044   Opcode_nsa_Slot_inst_encode, 0, 0
9045 };
9046
9047 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
9048   Opcode_nsau_Slot_inst_encode, 0, 0
9049 };
9050
9051 xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
9052   Opcode_sext_Slot_inst_encode, 0, 0
9053 };
9054
9055 xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
9056   Opcode_l32ai_Slot_inst_encode, 0, 0
9057 };
9058
9059 xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
9060   Opcode_s32ri_Slot_inst_encode, 0, 0
9061 };
9062
9063 xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
9064   Opcode_s32c1i_Slot_inst_encode, 0, 0
9065 };
9066
9067 xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
9068   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
9069 };
9070
9071 xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
9072   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
9073 };
9074
9075 xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
9076   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
9077 };
9078
9079 xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
9080   Opcode_quou_Slot_inst_encode, 0, 0
9081 };
9082
9083 xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
9084   Opcode_quos_Slot_inst_encode, 0, 0
9085 };
9086
9087 xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
9088   Opcode_remu_Slot_inst_encode, 0, 0
9089 };
9090
9091 xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
9092   Opcode_rems_Slot_inst_encode, 0, 0
9093 };
9094
9095 xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
9096   Opcode_mull_Slot_inst_encode, 0, 0
9097 };
9098
9099 \f
9100 /* Opcode table.  */
9101
9102 static xtensa_opcode_internal opcodes[] = {
9103   { "excw", 0 /* xt_iclass_excw */,
9104     0,
9105     Opcode_excw_encode_fns, 0, 0 },
9106   { "rfe", 1 /* xt_iclass_rfe */,
9107     XTENSA_OPCODE_IS_JUMP,
9108     Opcode_rfe_encode_fns, 0, 0 },
9109   { "rfde", 2 /* xt_iclass_rfde */,
9110     XTENSA_OPCODE_IS_JUMP,
9111     Opcode_rfde_encode_fns, 0, 0 },
9112   { "syscall", 3 /* xt_iclass_syscall */,
9113     0,
9114     Opcode_syscall_encode_fns, 0, 0 },
9115   { "simcall", 4 /* xt_iclass_simcall */,
9116     0,
9117     Opcode_simcall_encode_fns, 0, 0 },
9118   { "call12", 5 /* xt_iclass_call12 */,
9119     XTENSA_OPCODE_IS_CALL,
9120     Opcode_call12_encode_fns, 0, 0 },
9121   { "call8", 6 /* xt_iclass_call8 */,
9122     XTENSA_OPCODE_IS_CALL,
9123     Opcode_call8_encode_fns, 0, 0 },
9124   { "call4", 7 /* xt_iclass_call4 */,
9125     XTENSA_OPCODE_IS_CALL,
9126     Opcode_call4_encode_fns, 0, 0 },
9127   { "callx12", 8 /* xt_iclass_callx12 */,
9128     XTENSA_OPCODE_IS_CALL,
9129     Opcode_callx12_encode_fns, 0, 0 },
9130   { "callx8", 9 /* xt_iclass_callx8 */,
9131     XTENSA_OPCODE_IS_CALL,
9132     Opcode_callx8_encode_fns, 0, 0 },
9133   { "callx4", 10 /* xt_iclass_callx4 */,
9134     XTENSA_OPCODE_IS_CALL,
9135     Opcode_callx4_encode_fns, 0, 0 },
9136   { "entry", 11 /* xt_iclass_entry */,
9137     0,
9138     Opcode_entry_encode_fns, 0, 0 },
9139   { "movsp", 12 /* xt_iclass_movsp */,
9140     0,
9141     Opcode_movsp_encode_fns, 0, 0 },
9142   { "rotw", 13 /* xt_iclass_rotw */,
9143     0,
9144     Opcode_rotw_encode_fns, 0, 0 },
9145   { "retw", 14 /* xt_iclass_retw */,
9146     XTENSA_OPCODE_IS_JUMP,
9147     Opcode_retw_encode_fns, 0, 0 },
9148   { "retw.n", 14 /* xt_iclass_retw */,
9149     XTENSA_OPCODE_IS_JUMP,
9150     Opcode_retw_n_encode_fns, 0, 0 },
9151   { "rfwo", 15 /* xt_iclass_rfwou */,
9152     XTENSA_OPCODE_IS_JUMP,
9153     Opcode_rfwo_encode_fns, 0, 0 },
9154   { "rfwu", 15 /* xt_iclass_rfwou */,
9155     XTENSA_OPCODE_IS_JUMP,
9156     Opcode_rfwu_encode_fns, 0, 0 },
9157   { "l32e", 16 /* xt_iclass_l32e */,
9158     0,
9159     Opcode_l32e_encode_fns, 0, 0 },
9160   { "s32e", 17 /* xt_iclass_s32e */,
9161     0,
9162     Opcode_s32e_encode_fns, 0, 0 },
9163   { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
9164     0,
9165     Opcode_rsr_windowbase_encode_fns, 0, 0 },
9166   { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
9167     0,
9168     Opcode_wsr_windowbase_encode_fns, 0, 0 },
9169   { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
9170     0,
9171     Opcode_xsr_windowbase_encode_fns, 0, 0 },
9172   { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
9173     0,
9174     Opcode_rsr_windowstart_encode_fns, 0, 0 },
9175   { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
9176     0,
9177     Opcode_wsr_windowstart_encode_fns, 0, 0 },
9178   { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
9179     0,
9180     Opcode_xsr_windowstart_encode_fns, 0, 0 },
9181   { "add.n", 24 /* xt_iclass_add.n */,
9182     0,
9183     Opcode_add_n_encode_fns, 0, 0 },
9184   { "addi.n", 25 /* xt_iclass_addi.n */,
9185     0,
9186     Opcode_addi_n_encode_fns, 0, 0 },
9187   { "beqz.n", 26 /* xt_iclass_bz6 */,
9188     XTENSA_OPCODE_IS_BRANCH,
9189     Opcode_beqz_n_encode_fns, 0, 0 },
9190   { "bnez.n", 26 /* xt_iclass_bz6 */,
9191     XTENSA_OPCODE_IS_BRANCH,
9192     Opcode_bnez_n_encode_fns, 0, 0 },
9193   { "ill.n", 27 /* xt_iclass_ill.n */,
9194     0,
9195     Opcode_ill_n_encode_fns, 0, 0 },
9196   { "l32i.n", 28 /* xt_iclass_loadi4 */,
9197     0,
9198     Opcode_l32i_n_encode_fns, 0, 0 },
9199   { "mov.n", 29 /* xt_iclass_mov.n */,
9200     0,
9201     Opcode_mov_n_encode_fns, 0, 0 },
9202   { "movi.n", 30 /* xt_iclass_movi.n */,
9203     0,
9204     Opcode_movi_n_encode_fns, 0, 0 },
9205   { "nop.n", 31 /* xt_iclass_nopn */,
9206     0,
9207     Opcode_nop_n_encode_fns, 0, 0 },
9208   { "ret.n", 32 /* xt_iclass_retn */,
9209     XTENSA_OPCODE_IS_JUMP,
9210     Opcode_ret_n_encode_fns, 0, 0 },
9211   { "s32i.n", 33 /* xt_iclass_storei4 */,
9212     0,
9213     Opcode_s32i_n_encode_fns, 0, 0 },
9214   { "rur.threadptr", 34 /* rur_threadptr */,
9215     0,
9216     Opcode_rur_threadptr_encode_fns, 0, 0 },
9217   { "wur.threadptr", 35 /* wur_threadptr */,
9218     0,
9219     Opcode_wur_threadptr_encode_fns, 0, 0 },
9220   { "addi", 36 /* xt_iclass_addi */,
9221     0,
9222     Opcode_addi_encode_fns, 0, 0 },
9223   { "addmi", 37 /* xt_iclass_addmi */,
9224     0,
9225     Opcode_addmi_encode_fns, 0, 0 },
9226   { "add", 38 /* xt_iclass_addsub */,
9227     0,
9228     Opcode_add_encode_fns, 0, 0 },
9229   { "sub", 38 /* xt_iclass_addsub */,
9230     0,
9231     Opcode_sub_encode_fns, 0, 0 },
9232   { "addx2", 38 /* xt_iclass_addsub */,
9233     0,
9234     Opcode_addx2_encode_fns, 0, 0 },
9235   { "addx4", 38 /* xt_iclass_addsub */,
9236     0,
9237     Opcode_addx4_encode_fns, 0, 0 },
9238   { "addx8", 38 /* xt_iclass_addsub */,
9239     0,
9240     Opcode_addx8_encode_fns, 0, 0 },
9241   { "subx2", 38 /* xt_iclass_addsub */,
9242     0,
9243     Opcode_subx2_encode_fns, 0, 0 },
9244   { "subx4", 38 /* xt_iclass_addsub */,
9245     0,
9246     Opcode_subx4_encode_fns, 0, 0 },
9247   { "subx8", 38 /* xt_iclass_addsub */,
9248     0,
9249     Opcode_subx8_encode_fns, 0, 0 },
9250   { "and", 39 /* xt_iclass_bit */,
9251     0,
9252     Opcode_and_encode_fns, 0, 0 },
9253   { "or", 39 /* xt_iclass_bit */,
9254     0,
9255     Opcode_or_encode_fns, 0, 0 },
9256   { "xor", 39 /* xt_iclass_bit */,
9257     0,
9258     Opcode_xor_encode_fns, 0, 0 },
9259   { "beqi", 40 /* xt_iclass_bsi8 */,
9260     XTENSA_OPCODE_IS_BRANCH,
9261     Opcode_beqi_encode_fns, 0, 0 },
9262   { "bnei", 40 /* xt_iclass_bsi8 */,
9263     XTENSA_OPCODE_IS_BRANCH,
9264     Opcode_bnei_encode_fns, 0, 0 },
9265   { "bgei", 40 /* xt_iclass_bsi8 */,
9266     XTENSA_OPCODE_IS_BRANCH,
9267     Opcode_bgei_encode_fns, 0, 0 },
9268   { "blti", 40 /* xt_iclass_bsi8 */,
9269     XTENSA_OPCODE_IS_BRANCH,
9270     Opcode_blti_encode_fns, 0, 0 },
9271   { "bbci", 41 /* xt_iclass_bsi8b */,
9272     XTENSA_OPCODE_IS_BRANCH,
9273     Opcode_bbci_encode_fns, 0, 0 },
9274   { "bbsi", 41 /* xt_iclass_bsi8b */,
9275     XTENSA_OPCODE_IS_BRANCH,
9276     Opcode_bbsi_encode_fns, 0, 0 },
9277   { "bgeui", 42 /* xt_iclass_bsi8u */,
9278     XTENSA_OPCODE_IS_BRANCH,
9279     Opcode_bgeui_encode_fns, 0, 0 },
9280   { "bltui", 42 /* xt_iclass_bsi8u */,
9281     XTENSA_OPCODE_IS_BRANCH,
9282     Opcode_bltui_encode_fns, 0, 0 },
9283   { "beq", 43 /* xt_iclass_bst8 */,
9284     XTENSA_OPCODE_IS_BRANCH,
9285     Opcode_beq_encode_fns, 0, 0 },
9286   { "bne", 43 /* xt_iclass_bst8 */,
9287     XTENSA_OPCODE_IS_BRANCH,
9288     Opcode_bne_encode_fns, 0, 0 },
9289   { "bge", 43 /* xt_iclass_bst8 */,
9290     XTENSA_OPCODE_IS_BRANCH,
9291     Opcode_bge_encode_fns, 0, 0 },
9292   { "blt", 43 /* xt_iclass_bst8 */,
9293     XTENSA_OPCODE_IS_BRANCH,
9294     Opcode_blt_encode_fns, 0, 0 },
9295   { "bgeu", 43 /* xt_iclass_bst8 */,
9296     XTENSA_OPCODE_IS_BRANCH,
9297     Opcode_bgeu_encode_fns, 0, 0 },
9298   { "bltu", 43 /* xt_iclass_bst8 */,
9299     XTENSA_OPCODE_IS_BRANCH,
9300     Opcode_bltu_encode_fns, 0, 0 },
9301   { "bany", 43 /* xt_iclass_bst8 */,
9302     XTENSA_OPCODE_IS_BRANCH,
9303     Opcode_bany_encode_fns, 0, 0 },
9304   { "bnone", 43 /* xt_iclass_bst8 */,
9305     XTENSA_OPCODE_IS_BRANCH,
9306     Opcode_bnone_encode_fns, 0, 0 },
9307   { "ball", 43 /* xt_iclass_bst8 */,
9308     XTENSA_OPCODE_IS_BRANCH,
9309     Opcode_ball_encode_fns, 0, 0 },
9310   { "bnall", 43 /* xt_iclass_bst8 */,
9311     XTENSA_OPCODE_IS_BRANCH,
9312     Opcode_bnall_encode_fns, 0, 0 },
9313   { "bbc", 43 /* xt_iclass_bst8 */,
9314     XTENSA_OPCODE_IS_BRANCH,
9315     Opcode_bbc_encode_fns, 0, 0 },
9316   { "bbs", 43 /* xt_iclass_bst8 */,
9317     XTENSA_OPCODE_IS_BRANCH,
9318     Opcode_bbs_encode_fns, 0, 0 },
9319   { "beqz", 44 /* xt_iclass_bsz12 */,
9320     XTENSA_OPCODE_IS_BRANCH,
9321     Opcode_beqz_encode_fns, 0, 0 },
9322   { "bnez", 44 /* xt_iclass_bsz12 */,
9323     XTENSA_OPCODE_IS_BRANCH,
9324     Opcode_bnez_encode_fns, 0, 0 },
9325   { "bgez", 44 /* xt_iclass_bsz12 */,
9326     XTENSA_OPCODE_IS_BRANCH,
9327     Opcode_bgez_encode_fns, 0, 0 },
9328   { "bltz", 44 /* xt_iclass_bsz12 */,
9329     XTENSA_OPCODE_IS_BRANCH,
9330     Opcode_bltz_encode_fns, 0, 0 },
9331   { "call0", 45 /* xt_iclass_call0 */,
9332     XTENSA_OPCODE_IS_CALL,
9333     Opcode_call0_encode_fns, 0, 0 },
9334   { "callx0", 46 /* xt_iclass_callx0 */,
9335     XTENSA_OPCODE_IS_CALL,
9336     Opcode_callx0_encode_fns, 0, 0 },
9337   { "extui", 47 /* xt_iclass_exti */,
9338     0,
9339     Opcode_extui_encode_fns, 0, 0 },
9340   { "ill", 48 /* xt_iclass_ill */,
9341     0,
9342     Opcode_ill_encode_fns, 0, 0 },
9343   { "j", 49 /* xt_iclass_jump */,
9344     XTENSA_OPCODE_IS_JUMP,
9345     Opcode_j_encode_fns, 0, 0 },
9346   { "jx", 50 /* xt_iclass_jumpx */,
9347     XTENSA_OPCODE_IS_JUMP,
9348     Opcode_jx_encode_fns, 0, 0 },
9349   { "l16ui", 51 /* xt_iclass_l16ui */,
9350     0,
9351     Opcode_l16ui_encode_fns, 0, 0 },
9352   { "l16si", 52 /* xt_iclass_l16si */,
9353     0,
9354     Opcode_l16si_encode_fns, 0, 0 },
9355   { "l32i", 53 /* xt_iclass_l32i */,
9356     0,
9357     Opcode_l32i_encode_fns, 0, 0 },
9358   { "l32r", 54 /* xt_iclass_l32r */,
9359     0,
9360     Opcode_l32r_encode_fns, 0, 0 },
9361   { "l8ui", 55 /* xt_iclass_l8i */,
9362     0,
9363     Opcode_l8ui_encode_fns, 0, 0 },
9364   { "loop", 56 /* xt_iclass_loop */,
9365     XTENSA_OPCODE_IS_LOOP,
9366     Opcode_loop_encode_fns, 0, 0 },
9367   { "loopnez", 57 /* xt_iclass_loopz */,
9368     XTENSA_OPCODE_IS_LOOP,
9369     Opcode_loopnez_encode_fns, 0, 0 },
9370   { "loopgtz", 57 /* xt_iclass_loopz */,
9371     XTENSA_OPCODE_IS_LOOP,
9372     Opcode_loopgtz_encode_fns, 0, 0 },
9373   { "movi", 58 /* xt_iclass_movi */,
9374     0,
9375     Opcode_movi_encode_fns, 0, 0 },
9376   { "moveqz", 59 /* xt_iclass_movz */,
9377     0,
9378     Opcode_moveqz_encode_fns, 0, 0 },
9379   { "movnez", 59 /* xt_iclass_movz */,
9380     0,
9381     Opcode_movnez_encode_fns, 0, 0 },
9382   { "movltz", 59 /* xt_iclass_movz */,
9383     0,
9384     Opcode_movltz_encode_fns, 0, 0 },
9385   { "movgez", 59 /* xt_iclass_movz */,
9386     0,
9387     Opcode_movgez_encode_fns, 0, 0 },
9388   { "neg", 60 /* xt_iclass_neg */,
9389     0,
9390     Opcode_neg_encode_fns, 0, 0 },
9391   { "abs", 60 /* xt_iclass_neg */,
9392     0,
9393     Opcode_abs_encode_fns, 0, 0 },
9394   { "nop", 61 /* xt_iclass_nop */,
9395     0,
9396     Opcode_nop_encode_fns, 0, 0 },
9397   { "ret", 62 /* xt_iclass_return */,
9398     XTENSA_OPCODE_IS_JUMP,
9399     Opcode_ret_encode_fns, 0, 0 },
9400   { "s16i", 63 /* xt_iclass_s16i */,
9401     0,
9402     Opcode_s16i_encode_fns, 0, 0 },
9403   { "s32i", 64 /* xt_iclass_s32i */,
9404     0,
9405     Opcode_s32i_encode_fns, 0, 0 },
9406   { "s8i", 65 /* xt_iclass_s8i */,
9407     0,
9408     Opcode_s8i_encode_fns, 0, 0 },
9409   { "ssr", 66 /* xt_iclass_sar */,
9410     0,
9411     Opcode_ssr_encode_fns, 0, 0 },
9412   { "ssl", 66 /* xt_iclass_sar */,
9413     0,
9414     Opcode_ssl_encode_fns, 0, 0 },
9415   { "ssa8l", 66 /* xt_iclass_sar */,
9416     0,
9417     Opcode_ssa8l_encode_fns, 0, 0 },
9418   { "ssa8b", 66 /* xt_iclass_sar */,
9419     0,
9420     Opcode_ssa8b_encode_fns, 0, 0 },
9421   { "ssai", 67 /* xt_iclass_sari */,
9422     0,
9423     Opcode_ssai_encode_fns, 0, 0 },
9424   { "sll", 68 /* xt_iclass_shifts */,
9425     0,
9426     Opcode_sll_encode_fns, 0, 0 },
9427   { "src", 69 /* xt_iclass_shiftst */,
9428     0,
9429     Opcode_src_encode_fns, 0, 0 },
9430   { "srl", 70 /* xt_iclass_shiftt */,
9431     0,
9432     Opcode_srl_encode_fns, 0, 0 },
9433   { "sra", 70 /* xt_iclass_shiftt */,
9434     0,
9435     Opcode_sra_encode_fns, 0, 0 },
9436   { "slli", 71 /* xt_iclass_slli */,
9437     0,
9438     Opcode_slli_encode_fns, 0, 0 },
9439   { "srai", 72 /* xt_iclass_srai */,
9440     0,
9441     Opcode_srai_encode_fns, 0, 0 },
9442   { "srli", 73 /* xt_iclass_srli */,
9443     0,
9444     Opcode_srli_encode_fns, 0, 0 },
9445   { "memw", 74 /* xt_iclass_memw */,
9446     0,
9447     Opcode_memw_encode_fns, 0, 0 },
9448   { "extw", 75 /* xt_iclass_extw */,
9449     0,
9450     Opcode_extw_encode_fns, 0, 0 },
9451   { "isync", 76 /* xt_iclass_isync */,
9452     0,
9453     Opcode_isync_encode_fns, 0, 0 },
9454   { "rsync", 77 /* xt_iclass_sync */,
9455     0,
9456     Opcode_rsync_encode_fns, 0, 0 },
9457   { "esync", 77 /* xt_iclass_sync */,
9458     0,
9459     Opcode_esync_encode_fns, 0, 0 },
9460   { "dsync", 77 /* xt_iclass_sync */,
9461     0,
9462     Opcode_dsync_encode_fns, 0, 0 },
9463   { "rsil", 78 /* xt_iclass_rsil */,
9464     0,
9465     Opcode_rsil_encode_fns, 0, 0 },
9466   { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
9467     0,
9468     Opcode_rsr_lend_encode_fns, 0, 0 },
9469   { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
9470     0,
9471     Opcode_wsr_lend_encode_fns, 0, 0 },
9472   { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
9473     0,
9474     Opcode_xsr_lend_encode_fns, 0, 0 },
9475   { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
9476     0,
9477     Opcode_rsr_lcount_encode_fns, 0, 0 },
9478   { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
9479     0,
9480     Opcode_wsr_lcount_encode_fns, 0, 0 },
9481   { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
9482     0,
9483     Opcode_xsr_lcount_encode_fns, 0, 0 },
9484   { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
9485     0,
9486     Opcode_rsr_lbeg_encode_fns, 0, 0 },
9487   { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
9488     0,
9489     Opcode_wsr_lbeg_encode_fns, 0, 0 },
9490   { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
9491     0,
9492     Opcode_xsr_lbeg_encode_fns, 0, 0 },
9493   { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
9494     0,
9495     Opcode_rsr_sar_encode_fns, 0, 0 },
9496   { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
9497     0,
9498     Opcode_wsr_sar_encode_fns, 0, 0 },
9499   { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
9500     0,
9501     Opcode_xsr_sar_encode_fns, 0, 0 },
9502   { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
9503     0,
9504     Opcode_rsr_litbase_encode_fns, 0, 0 },
9505   { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
9506     0,
9507     Opcode_wsr_litbase_encode_fns, 0, 0 },
9508   { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
9509     0,
9510     Opcode_xsr_litbase_encode_fns, 0, 0 },
9511   { "rsr.176", 94 /* xt_iclass_rsr.176 */,
9512     0,
9513     Opcode_rsr_176_encode_fns, 0, 0 },
9514   { "wsr.176", 95 /* xt_iclass_wsr.176 */,
9515     0,
9516     Opcode_wsr_176_encode_fns, 0, 0 },
9517   { "rsr.208", 96 /* xt_iclass_rsr.208 */,
9518     0,
9519     Opcode_rsr_208_encode_fns, 0, 0 },
9520   { "rsr.ps", 97 /* xt_iclass_rsr.ps */,
9521     0,
9522     Opcode_rsr_ps_encode_fns, 0, 0 },
9523   { "wsr.ps", 98 /* xt_iclass_wsr.ps */,
9524     0,
9525     Opcode_wsr_ps_encode_fns, 0, 0 },
9526   { "xsr.ps", 99 /* xt_iclass_xsr.ps */,
9527     0,
9528     Opcode_xsr_ps_encode_fns, 0, 0 },
9529   { "rsr.epc1", 100 /* xt_iclass_rsr.epc1 */,
9530     0,
9531     Opcode_rsr_epc1_encode_fns, 0, 0 },
9532   { "wsr.epc1", 101 /* xt_iclass_wsr.epc1 */,
9533     0,
9534     Opcode_wsr_epc1_encode_fns, 0, 0 },
9535   { "xsr.epc1", 102 /* xt_iclass_xsr.epc1 */,
9536     0,
9537     Opcode_xsr_epc1_encode_fns, 0, 0 },
9538   { "rsr.excsave1", 103 /* xt_iclass_rsr.excsave1 */,
9539     0,
9540     Opcode_rsr_excsave1_encode_fns, 0, 0 },
9541   { "wsr.excsave1", 104 /* xt_iclass_wsr.excsave1 */,
9542     0,
9543     Opcode_wsr_excsave1_encode_fns, 0, 0 },
9544   { "xsr.excsave1", 105 /* xt_iclass_xsr.excsave1 */,
9545     0,
9546     Opcode_xsr_excsave1_encode_fns, 0, 0 },
9547   { "rsr.epc2", 106 /* xt_iclass_rsr.epc2 */,
9548     0,
9549     Opcode_rsr_epc2_encode_fns, 0, 0 },
9550   { "wsr.epc2", 107 /* xt_iclass_wsr.epc2 */,
9551     0,
9552     Opcode_wsr_epc2_encode_fns, 0, 0 },
9553   { "xsr.epc2", 108 /* xt_iclass_xsr.epc2 */,
9554     0,
9555     Opcode_xsr_epc2_encode_fns, 0, 0 },
9556   { "rsr.excsave2", 109 /* xt_iclass_rsr.excsave2 */,
9557     0,
9558     Opcode_rsr_excsave2_encode_fns, 0, 0 },
9559   { "wsr.excsave2", 110 /* xt_iclass_wsr.excsave2 */,
9560     0,
9561     Opcode_wsr_excsave2_encode_fns, 0, 0 },
9562   { "xsr.excsave2", 111 /* xt_iclass_xsr.excsave2 */,
9563     0,
9564     Opcode_xsr_excsave2_encode_fns, 0, 0 },
9565   { "rsr.epc3", 112 /* xt_iclass_rsr.epc3 */,
9566     0,
9567     Opcode_rsr_epc3_encode_fns, 0, 0 },
9568   { "wsr.epc3", 113 /* xt_iclass_wsr.epc3 */,
9569     0,
9570     Opcode_wsr_epc3_encode_fns, 0, 0 },
9571   { "xsr.epc3", 114 /* xt_iclass_xsr.epc3 */,
9572     0,
9573     Opcode_xsr_epc3_encode_fns, 0, 0 },
9574   { "rsr.excsave3", 115 /* xt_iclass_rsr.excsave3 */,
9575     0,
9576     Opcode_rsr_excsave3_encode_fns, 0, 0 },
9577   { "wsr.excsave3", 116 /* xt_iclass_wsr.excsave3 */,
9578     0,
9579     Opcode_wsr_excsave3_encode_fns, 0, 0 },
9580   { "xsr.excsave3", 117 /* xt_iclass_xsr.excsave3 */,
9581     0,
9582     Opcode_xsr_excsave3_encode_fns, 0, 0 },
9583   { "rsr.epc4", 118 /* xt_iclass_rsr.epc4 */,
9584     0,
9585     Opcode_rsr_epc4_encode_fns, 0, 0 },
9586   { "wsr.epc4", 119 /* xt_iclass_wsr.epc4 */,
9587     0,
9588     Opcode_wsr_epc4_encode_fns, 0, 0 },
9589   { "xsr.epc4", 120 /* xt_iclass_xsr.epc4 */,
9590     0,
9591     Opcode_xsr_epc4_encode_fns, 0, 0 },
9592   { "rsr.excsave4", 121 /* xt_iclass_rsr.excsave4 */,
9593     0,
9594     Opcode_rsr_excsave4_encode_fns, 0, 0 },
9595   { "wsr.excsave4", 122 /* xt_iclass_wsr.excsave4 */,
9596     0,
9597     Opcode_wsr_excsave4_encode_fns, 0, 0 },
9598   { "xsr.excsave4", 123 /* xt_iclass_xsr.excsave4 */,
9599     0,
9600     Opcode_xsr_excsave4_encode_fns, 0, 0 },
9601   { "rsr.epc5", 124 /* xt_iclass_rsr.epc5 */,
9602     0,
9603     Opcode_rsr_epc5_encode_fns, 0, 0 },
9604   { "wsr.epc5", 125 /* xt_iclass_wsr.epc5 */,
9605     0,
9606     Opcode_wsr_epc5_encode_fns, 0, 0 },
9607   { "xsr.epc5", 126 /* xt_iclass_xsr.epc5 */,
9608     0,
9609     Opcode_xsr_epc5_encode_fns, 0, 0 },
9610   { "rsr.excsave5", 127 /* xt_iclass_rsr.excsave5 */,
9611     0,
9612     Opcode_rsr_excsave5_encode_fns, 0, 0 },
9613   { "wsr.excsave5", 128 /* xt_iclass_wsr.excsave5 */,
9614     0,
9615     Opcode_wsr_excsave5_encode_fns, 0, 0 },
9616   { "xsr.excsave5", 129 /* xt_iclass_xsr.excsave5 */,
9617     0,
9618     Opcode_xsr_excsave5_encode_fns, 0, 0 },
9619   { "rsr.epc6", 130 /* xt_iclass_rsr.epc6 */,
9620     0,
9621     Opcode_rsr_epc6_encode_fns, 0, 0 },
9622   { "wsr.epc6", 131 /* xt_iclass_wsr.epc6 */,
9623     0,
9624     Opcode_wsr_epc6_encode_fns, 0, 0 },
9625   { "xsr.epc6", 132 /* xt_iclass_xsr.epc6 */,
9626     0,
9627     Opcode_xsr_epc6_encode_fns, 0, 0 },
9628   { "rsr.excsave6", 133 /* xt_iclass_rsr.excsave6 */,
9629     0,
9630     Opcode_rsr_excsave6_encode_fns, 0, 0 },
9631   { "wsr.excsave6", 134 /* xt_iclass_wsr.excsave6 */,
9632     0,
9633     Opcode_wsr_excsave6_encode_fns, 0, 0 },
9634   { "xsr.excsave6", 135 /* xt_iclass_xsr.excsave6 */,
9635     0,
9636     Opcode_xsr_excsave6_encode_fns, 0, 0 },
9637   { "rsr.epc7", 136 /* xt_iclass_rsr.epc7 */,
9638     0,
9639     Opcode_rsr_epc7_encode_fns, 0, 0 },
9640   { "wsr.epc7", 137 /* xt_iclass_wsr.epc7 */,
9641     0,
9642     Opcode_wsr_epc7_encode_fns, 0, 0 },
9643   { "xsr.epc7", 138 /* xt_iclass_xsr.epc7 */,
9644     0,
9645     Opcode_xsr_epc7_encode_fns, 0, 0 },
9646   { "rsr.excsave7", 139 /* xt_iclass_rsr.excsave7 */,
9647     0,
9648     Opcode_rsr_excsave7_encode_fns, 0, 0 },
9649   { "wsr.excsave7", 140 /* xt_iclass_wsr.excsave7 */,
9650     0,
9651     Opcode_wsr_excsave7_encode_fns, 0, 0 },
9652   { "xsr.excsave7", 141 /* xt_iclass_xsr.excsave7 */,
9653     0,
9654     Opcode_xsr_excsave7_encode_fns, 0, 0 },
9655   { "rsr.eps2", 142 /* xt_iclass_rsr.eps2 */,
9656     0,
9657     Opcode_rsr_eps2_encode_fns, 0, 0 },
9658   { "wsr.eps2", 143 /* xt_iclass_wsr.eps2 */,
9659     0,
9660     Opcode_wsr_eps2_encode_fns, 0, 0 },
9661   { "xsr.eps2", 144 /* xt_iclass_xsr.eps2 */,
9662     0,
9663     Opcode_xsr_eps2_encode_fns, 0, 0 },
9664   { "rsr.eps3", 145 /* xt_iclass_rsr.eps3 */,
9665     0,
9666     Opcode_rsr_eps3_encode_fns, 0, 0 },
9667   { "wsr.eps3", 146 /* xt_iclass_wsr.eps3 */,
9668     0,
9669     Opcode_wsr_eps3_encode_fns, 0, 0 },
9670   { "xsr.eps3", 147 /* xt_iclass_xsr.eps3 */,
9671     0,
9672     Opcode_xsr_eps3_encode_fns, 0, 0 },
9673   { "rsr.eps4", 148 /* xt_iclass_rsr.eps4 */,
9674     0,
9675     Opcode_rsr_eps4_encode_fns, 0, 0 },
9676   { "wsr.eps4", 149 /* xt_iclass_wsr.eps4 */,
9677     0,
9678     Opcode_wsr_eps4_encode_fns, 0, 0 },
9679   { "xsr.eps4", 150 /* xt_iclass_xsr.eps4 */,
9680     0,
9681     Opcode_xsr_eps4_encode_fns, 0, 0 },
9682   { "rsr.eps5", 151 /* xt_iclass_rsr.eps5 */,
9683     0,
9684     Opcode_rsr_eps5_encode_fns, 0, 0 },
9685   { "wsr.eps5", 152 /* xt_iclass_wsr.eps5 */,
9686     0,
9687     Opcode_wsr_eps5_encode_fns, 0, 0 },
9688   { "xsr.eps5", 153 /* xt_iclass_xsr.eps5 */,
9689     0,
9690     Opcode_xsr_eps5_encode_fns, 0, 0 },
9691   { "rsr.eps6", 154 /* xt_iclass_rsr.eps6 */,
9692     0,
9693     Opcode_rsr_eps6_encode_fns, 0, 0 },
9694   { "wsr.eps6", 155 /* xt_iclass_wsr.eps6 */,
9695     0,
9696     Opcode_wsr_eps6_encode_fns, 0, 0 },
9697   { "xsr.eps6", 156 /* xt_iclass_xsr.eps6 */,
9698     0,
9699     Opcode_xsr_eps6_encode_fns, 0, 0 },
9700   { "rsr.eps7", 157 /* xt_iclass_rsr.eps7 */,
9701     0,
9702     Opcode_rsr_eps7_encode_fns, 0, 0 },
9703   { "wsr.eps7", 158 /* xt_iclass_wsr.eps7 */,
9704     0,
9705     Opcode_wsr_eps7_encode_fns, 0, 0 },
9706   { "xsr.eps7", 159 /* xt_iclass_xsr.eps7 */,
9707     0,
9708     Opcode_xsr_eps7_encode_fns, 0, 0 },
9709   { "rsr.excvaddr", 160 /* xt_iclass_rsr.excvaddr */,
9710     0,
9711     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
9712   { "wsr.excvaddr", 161 /* xt_iclass_wsr.excvaddr */,
9713     0,
9714     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
9715   { "xsr.excvaddr", 162 /* xt_iclass_xsr.excvaddr */,
9716     0,
9717     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
9718   { "rsr.depc", 163 /* xt_iclass_rsr.depc */,
9719     0,
9720     Opcode_rsr_depc_encode_fns, 0, 0 },
9721   { "wsr.depc", 164 /* xt_iclass_wsr.depc */,
9722     0,
9723     Opcode_wsr_depc_encode_fns, 0, 0 },
9724   { "xsr.depc", 165 /* xt_iclass_xsr.depc */,
9725     0,
9726     Opcode_xsr_depc_encode_fns, 0, 0 },
9727   { "rsr.exccause", 166 /* xt_iclass_rsr.exccause */,
9728     0,
9729     Opcode_rsr_exccause_encode_fns, 0, 0 },
9730   { "wsr.exccause", 167 /* xt_iclass_wsr.exccause */,
9731     0,
9732     Opcode_wsr_exccause_encode_fns, 0, 0 },
9733   { "xsr.exccause", 168 /* xt_iclass_xsr.exccause */,
9734     0,
9735     Opcode_xsr_exccause_encode_fns, 0, 0 },
9736   { "rsr.misc0", 169 /* xt_iclass_rsr.misc0 */,
9737     0,
9738     Opcode_rsr_misc0_encode_fns, 0, 0 },
9739   { "wsr.misc0", 170 /* xt_iclass_wsr.misc0 */,
9740     0,
9741     Opcode_wsr_misc0_encode_fns, 0, 0 },
9742   { "xsr.misc0", 171 /* xt_iclass_xsr.misc0 */,
9743     0,
9744     Opcode_xsr_misc0_encode_fns, 0, 0 },
9745   { "rsr.misc1", 172 /* xt_iclass_rsr.misc1 */,
9746     0,
9747     Opcode_rsr_misc1_encode_fns, 0, 0 },
9748   { "wsr.misc1", 173 /* xt_iclass_wsr.misc1 */,
9749     0,
9750     Opcode_wsr_misc1_encode_fns, 0, 0 },
9751   { "xsr.misc1", 174 /* xt_iclass_xsr.misc1 */,
9752     0,
9753     Opcode_xsr_misc1_encode_fns, 0, 0 },
9754   { "rsr.prid", 175 /* xt_iclass_rsr.prid */,
9755     0,
9756     Opcode_rsr_prid_encode_fns, 0, 0 },
9757   { "rsr.vecbase", 176 /* xt_iclass_rsr.vecbase */,
9758     0,
9759     Opcode_rsr_vecbase_encode_fns, 0, 0 },
9760   { "wsr.vecbase", 177 /* xt_iclass_wsr.vecbase */,
9761     0,
9762     Opcode_wsr_vecbase_encode_fns, 0, 0 },
9763   { "xsr.vecbase", 178 /* xt_iclass_xsr.vecbase */,
9764     0,
9765     Opcode_xsr_vecbase_encode_fns, 0, 0 },
9766   { "mul16u", 179 /* xt_iclass_mul16 */,
9767     0,
9768     Opcode_mul16u_encode_fns, 0, 0 },
9769   { "mul16s", 179 /* xt_iclass_mul16 */,
9770     0,
9771     Opcode_mul16s_encode_fns, 0, 0 },
9772   { "rfi", 180 /* xt_iclass_rfi */,
9773     XTENSA_OPCODE_IS_JUMP,
9774     Opcode_rfi_encode_fns, 0, 0 },
9775   { "waiti", 181 /* xt_iclass_wait */,
9776     0,
9777     Opcode_waiti_encode_fns, 0, 0 },
9778   { "rsr.interrupt", 182 /* xt_iclass_rsr.interrupt */,
9779     0,
9780     Opcode_rsr_interrupt_encode_fns, 0, 0 },
9781   { "wsr.intset", 183 /* xt_iclass_wsr.intset */,
9782     0,
9783     Opcode_wsr_intset_encode_fns, 0, 0 },
9784   { "wsr.intclear", 184 /* xt_iclass_wsr.intclear */,
9785     0,
9786     Opcode_wsr_intclear_encode_fns, 0, 0 },
9787   { "rsr.intenable", 185 /* xt_iclass_rsr.intenable */,
9788     0,
9789     Opcode_rsr_intenable_encode_fns, 0, 0 },
9790   { "wsr.intenable", 186 /* xt_iclass_wsr.intenable */,
9791     0,
9792     Opcode_wsr_intenable_encode_fns, 0, 0 },
9793   { "xsr.intenable", 187 /* xt_iclass_xsr.intenable */,
9794     0,
9795     Opcode_xsr_intenable_encode_fns, 0, 0 },
9796   { "break", 188 /* xt_iclass_break */,
9797     0,
9798     Opcode_break_encode_fns, 0, 0 },
9799   { "break.n", 189 /* xt_iclass_break.n */,
9800     0,
9801     Opcode_break_n_encode_fns, 0, 0 },
9802   { "rsr.dbreaka0", 190 /* xt_iclass_rsr.dbreaka0 */,
9803     0,
9804     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
9805   { "wsr.dbreaka0", 191 /* xt_iclass_wsr.dbreaka0 */,
9806     0,
9807     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
9808   { "xsr.dbreaka0", 192 /* xt_iclass_xsr.dbreaka0 */,
9809     0,
9810     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
9811   { "rsr.dbreakc0", 193 /* xt_iclass_rsr.dbreakc0 */,
9812     0,
9813     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
9814   { "wsr.dbreakc0", 194 /* xt_iclass_wsr.dbreakc0 */,
9815     0,
9816     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
9817   { "xsr.dbreakc0", 195 /* xt_iclass_xsr.dbreakc0 */,
9818     0,
9819     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
9820   { "rsr.dbreaka1", 196 /* xt_iclass_rsr.dbreaka1 */,
9821     0,
9822     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
9823   { "wsr.dbreaka1", 197 /* xt_iclass_wsr.dbreaka1 */,
9824     0,
9825     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
9826   { "xsr.dbreaka1", 198 /* xt_iclass_xsr.dbreaka1 */,
9827     0,
9828     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
9829   { "rsr.dbreakc1", 199 /* xt_iclass_rsr.dbreakc1 */,
9830     0,
9831     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
9832   { "wsr.dbreakc1", 200 /* xt_iclass_wsr.dbreakc1 */,
9833     0,
9834     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
9835   { "xsr.dbreakc1", 201 /* xt_iclass_xsr.dbreakc1 */,
9836     0,
9837     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
9838   { "rsr.ibreaka0", 202 /* xt_iclass_rsr.ibreaka0 */,
9839     0,
9840     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
9841   { "wsr.ibreaka0", 203 /* xt_iclass_wsr.ibreaka0 */,
9842     0,
9843     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
9844   { "xsr.ibreaka0", 204 /* xt_iclass_xsr.ibreaka0 */,
9845     0,
9846     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
9847   { "rsr.ibreaka1", 205 /* xt_iclass_rsr.ibreaka1 */,
9848     0,
9849     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
9850   { "wsr.ibreaka1", 206 /* xt_iclass_wsr.ibreaka1 */,
9851     0,
9852     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
9853   { "xsr.ibreaka1", 207 /* xt_iclass_xsr.ibreaka1 */,
9854     0,
9855     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
9856   { "rsr.ibreakenable", 208 /* xt_iclass_rsr.ibreakenable */,
9857     0,
9858     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
9859   { "wsr.ibreakenable", 209 /* xt_iclass_wsr.ibreakenable */,
9860     0,
9861     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
9862   { "xsr.ibreakenable", 210 /* xt_iclass_xsr.ibreakenable */,
9863     0,
9864     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
9865   { "rsr.debugcause", 211 /* xt_iclass_rsr.debugcause */,
9866     0,
9867     Opcode_rsr_debugcause_encode_fns, 0, 0 },
9868   { "wsr.debugcause", 212 /* xt_iclass_wsr.debugcause */,
9869     0,
9870     Opcode_wsr_debugcause_encode_fns, 0, 0 },
9871   { "xsr.debugcause", 213 /* xt_iclass_xsr.debugcause */,
9872     0,
9873     Opcode_xsr_debugcause_encode_fns, 0, 0 },
9874   { "rsr.icount", 214 /* xt_iclass_rsr.icount */,
9875     0,
9876     Opcode_rsr_icount_encode_fns, 0, 0 },
9877   { "wsr.icount", 215 /* xt_iclass_wsr.icount */,
9878     0,
9879     Opcode_wsr_icount_encode_fns, 0, 0 },
9880   { "xsr.icount", 216 /* xt_iclass_xsr.icount */,
9881     0,
9882     Opcode_xsr_icount_encode_fns, 0, 0 },
9883   { "rsr.icountlevel", 217 /* xt_iclass_rsr.icountlevel */,
9884     0,
9885     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
9886   { "wsr.icountlevel", 218 /* xt_iclass_wsr.icountlevel */,
9887     0,
9888     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
9889   { "xsr.icountlevel", 219 /* xt_iclass_xsr.icountlevel */,
9890     0,
9891     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
9892   { "rsr.ddr", 220 /* xt_iclass_rsr.ddr */,
9893     0,
9894     Opcode_rsr_ddr_encode_fns, 0, 0 },
9895   { "wsr.ddr", 221 /* xt_iclass_wsr.ddr */,
9896     0,
9897     Opcode_wsr_ddr_encode_fns, 0, 0 },
9898   { "xsr.ddr", 222 /* xt_iclass_xsr.ddr */,
9899     0,
9900     Opcode_xsr_ddr_encode_fns, 0, 0 },
9901   { "rfdo", 223 /* xt_iclass_rfdo */,
9902     XTENSA_OPCODE_IS_JUMP,
9903     Opcode_rfdo_encode_fns, 0, 0 },
9904   { "rfdd", 224 /* xt_iclass_rfdd */,
9905     XTENSA_OPCODE_IS_JUMP,
9906     Opcode_rfdd_encode_fns, 0, 0 },
9907   { "wsr.mmid", 225 /* xt_iclass_wsr.mmid */,
9908     0,
9909     Opcode_wsr_mmid_encode_fns, 0, 0 },
9910   { "rsr.ccount", 226 /* xt_iclass_rsr.ccount */,
9911     0,
9912     Opcode_rsr_ccount_encode_fns, 0, 0 },
9913   { "wsr.ccount", 227 /* xt_iclass_wsr.ccount */,
9914     0,
9915     Opcode_wsr_ccount_encode_fns, 0, 0 },
9916   { "xsr.ccount", 228 /* xt_iclass_xsr.ccount */,
9917     0,
9918     Opcode_xsr_ccount_encode_fns, 0, 0 },
9919   { "rsr.ccompare0", 229 /* xt_iclass_rsr.ccompare0 */,
9920     0,
9921     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
9922   { "wsr.ccompare0", 230 /* xt_iclass_wsr.ccompare0 */,
9923     0,
9924     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
9925   { "xsr.ccompare0", 231 /* xt_iclass_xsr.ccompare0 */,
9926     0,
9927     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
9928   { "rsr.ccompare1", 232 /* xt_iclass_rsr.ccompare1 */,
9929     0,
9930     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
9931   { "wsr.ccompare1", 233 /* xt_iclass_wsr.ccompare1 */,
9932     0,
9933     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
9934   { "xsr.ccompare1", 234 /* xt_iclass_xsr.ccompare1 */,
9935     0,
9936     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
9937   { "rsr.ccompare2", 235 /* xt_iclass_rsr.ccompare2 */,
9938     0,
9939     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
9940   { "wsr.ccompare2", 236 /* xt_iclass_wsr.ccompare2 */,
9941     0,
9942     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
9943   { "xsr.ccompare2", 237 /* xt_iclass_xsr.ccompare2 */,
9944     0,
9945     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
9946   { "ipf", 238 /* xt_iclass_icache */,
9947     0,
9948     Opcode_ipf_encode_fns, 0, 0 },
9949   { "ihi", 238 /* xt_iclass_icache */,
9950     0,
9951     Opcode_ihi_encode_fns, 0, 0 },
9952   { "ipfl", 239 /* xt_iclass_icache_lock */,
9953     0,
9954     Opcode_ipfl_encode_fns, 0, 0 },
9955   { "ihu", 239 /* xt_iclass_icache_lock */,
9956     0,
9957     Opcode_ihu_encode_fns, 0, 0 },
9958   { "iiu", 239 /* xt_iclass_icache_lock */,
9959     0,
9960     Opcode_iiu_encode_fns, 0, 0 },
9961   { "iii", 240 /* xt_iclass_icache_inv */,
9962     0,
9963     Opcode_iii_encode_fns, 0, 0 },
9964   { "lict", 241 /* xt_iclass_licx */,
9965     0,
9966     Opcode_lict_encode_fns, 0, 0 },
9967   { "licw", 241 /* xt_iclass_licx */,
9968     0,
9969     Opcode_licw_encode_fns, 0, 0 },
9970   { "sict", 242 /* xt_iclass_sicx */,
9971     0,
9972     Opcode_sict_encode_fns, 0, 0 },
9973   { "sicw", 242 /* xt_iclass_sicx */,
9974     0,
9975     Opcode_sicw_encode_fns, 0, 0 },
9976   { "dhwb", 243 /* xt_iclass_dcache */,
9977     0,
9978     Opcode_dhwb_encode_fns, 0, 0 },
9979   { "dhwbi", 243 /* xt_iclass_dcache */,
9980     0,
9981     Opcode_dhwbi_encode_fns, 0, 0 },
9982   { "diwb", 244 /* xt_iclass_dcache_ind */,
9983     0,
9984     Opcode_diwb_encode_fns, 0, 0 },
9985   { "diwbi", 244 /* xt_iclass_dcache_ind */,
9986     0,
9987     Opcode_diwbi_encode_fns, 0, 0 },
9988   { "dhi", 245 /* xt_iclass_dcache_inv */,
9989     0,
9990     Opcode_dhi_encode_fns, 0, 0 },
9991   { "dii", 245 /* xt_iclass_dcache_inv */,
9992     0,
9993     Opcode_dii_encode_fns, 0, 0 },
9994   { "dpfr", 246 /* xt_iclass_dpf */,
9995     0,
9996     Opcode_dpfr_encode_fns, 0, 0 },
9997   { "dpfw", 246 /* xt_iclass_dpf */,
9998     0,
9999     Opcode_dpfw_encode_fns, 0, 0 },
10000   { "dpfro", 246 /* xt_iclass_dpf */,
10001     0,
10002     Opcode_dpfro_encode_fns, 0, 0 },
10003   { "dpfwo", 246 /* xt_iclass_dpf */,
10004     0,
10005     Opcode_dpfwo_encode_fns, 0, 0 },
10006   { "dpfl", 247 /* xt_iclass_dcache_lock */,
10007     0,
10008     Opcode_dpfl_encode_fns, 0, 0 },
10009   { "dhu", 247 /* xt_iclass_dcache_lock */,
10010     0,
10011     Opcode_dhu_encode_fns, 0, 0 },
10012   { "diu", 247 /* xt_iclass_dcache_lock */,
10013     0,
10014     Opcode_diu_encode_fns, 0, 0 },
10015   { "sdct", 248 /* xt_iclass_sdct */,
10016     0,
10017     Opcode_sdct_encode_fns, 0, 0 },
10018   { "ldct", 249 /* xt_iclass_ldct */,
10019     0,
10020     Opcode_ldct_encode_fns, 0, 0 },
10021   { "wsr.ptevaddr", 250 /* xt_iclass_wsr.ptevaddr */,
10022     0,
10023     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
10024   { "rsr.ptevaddr", 251 /* xt_iclass_rsr.ptevaddr */,
10025     0,
10026     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
10027   { "xsr.ptevaddr", 252 /* xt_iclass_xsr.ptevaddr */,
10028     0,
10029     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
10030   { "rsr.rasid", 253 /* xt_iclass_rsr.rasid */,
10031     0,
10032     Opcode_rsr_rasid_encode_fns, 0, 0 },
10033   { "wsr.rasid", 254 /* xt_iclass_wsr.rasid */,
10034     0,
10035     Opcode_wsr_rasid_encode_fns, 0, 0 },
10036   { "xsr.rasid", 255 /* xt_iclass_xsr.rasid */,
10037     0,
10038     Opcode_xsr_rasid_encode_fns, 0, 0 },
10039   { "rsr.itlbcfg", 256 /* xt_iclass_rsr.itlbcfg */,
10040     0,
10041     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
10042   { "wsr.itlbcfg", 257 /* xt_iclass_wsr.itlbcfg */,
10043     0,
10044     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
10045   { "xsr.itlbcfg", 258 /* xt_iclass_xsr.itlbcfg */,
10046     0,
10047     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
10048   { "rsr.dtlbcfg", 259 /* xt_iclass_rsr.dtlbcfg */,
10049     0,
10050     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
10051   { "wsr.dtlbcfg", 260 /* xt_iclass_wsr.dtlbcfg */,
10052     0,
10053     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
10054   { "xsr.dtlbcfg", 261 /* xt_iclass_xsr.dtlbcfg */,
10055     0,
10056     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
10057   { "idtlb", 262 /* xt_iclass_idtlb */,
10058     0,
10059     Opcode_idtlb_encode_fns, 0, 0 },
10060   { "pdtlb", 263 /* xt_iclass_rdtlb */,
10061     0,
10062     Opcode_pdtlb_encode_fns, 0, 0 },
10063   { "rdtlb0", 263 /* xt_iclass_rdtlb */,
10064     0,
10065     Opcode_rdtlb0_encode_fns, 0, 0 },
10066   { "rdtlb1", 263 /* xt_iclass_rdtlb */,
10067     0,
10068     Opcode_rdtlb1_encode_fns, 0, 0 },
10069   { "wdtlb", 264 /* xt_iclass_wdtlb */,
10070     0,
10071     Opcode_wdtlb_encode_fns, 0, 0 },
10072   { "iitlb", 265 /* xt_iclass_iitlb */,
10073     0,
10074     Opcode_iitlb_encode_fns, 0, 0 },
10075   { "pitlb", 266 /* xt_iclass_ritlb */,
10076     0,
10077     Opcode_pitlb_encode_fns, 0, 0 },
10078   { "ritlb0", 266 /* xt_iclass_ritlb */,
10079     0,
10080     Opcode_ritlb0_encode_fns, 0, 0 },
10081   { "ritlb1", 266 /* xt_iclass_ritlb */,
10082     0,
10083     Opcode_ritlb1_encode_fns, 0, 0 },
10084   { "witlb", 267 /* xt_iclass_witlb */,
10085     0,
10086     Opcode_witlb_encode_fns, 0, 0 },
10087   { "ldpte", 268 /* xt_iclass_ldpte */,
10088     0,
10089     Opcode_ldpte_encode_fns, 0, 0 },
10090   { "hwwitlba", 269 /* xt_iclass_hwwitlba */,
10091     XTENSA_OPCODE_IS_BRANCH,
10092     Opcode_hwwitlba_encode_fns, 0, 0 },
10093   { "hwwdtlba", 270 /* xt_iclass_hwwdtlba */,
10094     0,
10095     Opcode_hwwdtlba_encode_fns, 0, 0 },
10096   { "rsr.cpenable", 271 /* xt_iclass_rsr.cpenable */,
10097     0,
10098     Opcode_rsr_cpenable_encode_fns, 0, 0 },
10099   { "wsr.cpenable", 272 /* xt_iclass_wsr.cpenable */,
10100     0,
10101     Opcode_wsr_cpenable_encode_fns, 0, 0 },
10102   { "xsr.cpenable", 273 /* xt_iclass_xsr.cpenable */,
10103     0,
10104     Opcode_xsr_cpenable_encode_fns, 0, 0 },
10105   { "clamps", 274 /* xt_iclass_clamp */,
10106     0,
10107     Opcode_clamps_encode_fns, 0, 0 },
10108   { "min", 275 /* xt_iclass_minmax */,
10109     0,
10110     Opcode_min_encode_fns, 0, 0 },
10111   { "max", 275 /* xt_iclass_minmax */,
10112     0,
10113     Opcode_max_encode_fns, 0, 0 },
10114   { "minu", 275 /* xt_iclass_minmax */,
10115     0,
10116     Opcode_minu_encode_fns, 0, 0 },
10117   { "maxu", 275 /* xt_iclass_minmax */,
10118     0,
10119     Opcode_maxu_encode_fns, 0, 0 },
10120   { "nsa", 276 /* xt_iclass_nsa */,
10121     0,
10122     Opcode_nsa_encode_fns, 0, 0 },
10123   { "nsau", 276 /* xt_iclass_nsa */,
10124     0,
10125     Opcode_nsau_encode_fns, 0, 0 },
10126   { "sext", 277 /* xt_iclass_sx */,
10127     0,
10128     Opcode_sext_encode_fns, 0, 0 },
10129   { "l32ai", 278 /* xt_iclass_l32ai */,
10130     0,
10131     Opcode_l32ai_encode_fns, 0, 0 },
10132   { "s32ri", 279 /* xt_iclass_s32ri */,
10133     0,
10134     Opcode_s32ri_encode_fns, 0, 0 },
10135   { "s32c1i", 280 /* xt_iclass_s32c1i */,
10136     0,
10137     Opcode_s32c1i_encode_fns, 0, 0 },
10138   { "rsr.scompare1", 281 /* xt_iclass_rsr.scompare1 */,
10139     0,
10140     Opcode_rsr_scompare1_encode_fns, 0, 0 },
10141   { "wsr.scompare1", 282 /* xt_iclass_wsr.scompare1 */,
10142     0,
10143     Opcode_wsr_scompare1_encode_fns, 0, 0 },
10144   { "xsr.scompare1", 283 /* xt_iclass_xsr.scompare1 */,
10145     0,
10146     Opcode_xsr_scompare1_encode_fns, 0, 0 },
10147   { "quou", 284 /* xt_iclass_div */,
10148     0,
10149     Opcode_quou_encode_fns, 0, 0 },
10150   { "quos", 284 /* xt_iclass_div */,
10151     0,
10152     Opcode_quos_encode_fns, 0, 0 },
10153   { "remu", 284 /* xt_iclass_div */,
10154     0,
10155     Opcode_remu_encode_fns, 0, 0 },
10156   { "rems", 284 /* xt_iclass_div */,
10157     0,
10158     Opcode_rems_encode_fns, 0, 0 },
10159   { "mull", 285 /* xt_mul32 */,
10160     0,
10161     Opcode_mull_encode_fns, 0, 0 }
10162 };
10163
10164 \f
10165 /* Slot-specific opcode decode functions.  */
10166
10167 static int
10168 Slot_inst_decode (const xtensa_insnbuf insn)
10169 {
10170   switch (Field_op0_Slot_inst_get (insn))
10171     {
10172     case 0:
10173       switch (Field_op1_Slot_inst_get (insn))
10174         {
10175         case 0:
10176           switch (Field_op2_Slot_inst_get (insn))
10177             {
10178             case 0:
10179               switch (Field_r_Slot_inst_get (insn))
10180                 {
10181                 case 0:
10182                   switch (Field_m_Slot_inst_get (insn))
10183                     {
10184                     case 0:
10185                       if (Field_s_Slot_inst_get (insn) == 0 &&
10186                           Field_n_Slot_inst_get (insn) == 0)
10187                         return 79; /* ill */
10188                       break;
10189                     case 2:
10190                       switch (Field_n_Slot_inst_get (insn))
10191                         {
10192                         case 0:
10193                           return 98; /* ret */
10194                         case 1:
10195                           return 14; /* retw */
10196                         case 2:
10197                           return 81; /* jx */
10198                         }
10199                       break;
10200                     case 3:
10201                       switch (Field_n_Slot_inst_get (insn))
10202                         {
10203                         case 0:
10204                           return 77; /* callx0 */
10205                         case 1:
10206                           return 10; /* callx4 */
10207                         case 2:
10208                           return 9; /* callx8 */
10209                         case 3:
10210                           return 8; /* callx12 */
10211                         }
10212                       break;
10213                     }
10214                   break;
10215                 case 1:
10216                   return 12; /* movsp */
10217                 case 2:
10218                   if (Field_s_Slot_inst_get (insn) == 0)
10219                     {
10220                       switch (Field_t_Slot_inst_get (insn))
10221                         {
10222                         case 0:
10223                           return 116; /* isync */
10224                         case 1:
10225                           return 117; /* rsync */
10226                         case 2:
10227                           return 118; /* esync */
10228                         case 3:
10229                           return 119; /* dsync */
10230                         case 8:
10231                           return 0; /* excw */
10232                         case 12:
10233                           return 114; /* memw */
10234                         case 13:
10235                           return 115; /* extw */
10236                         case 15:
10237                           return 97; /* nop */
10238                         }
10239                     }
10240                   break;
10241                 case 3:
10242                   switch (Field_t_Slot_inst_get (insn))
10243                     {
10244                     case 0:
10245                       switch (Field_s_Slot_inst_get (insn))
10246                         {
10247                         case 0:
10248                           return 1; /* rfe */
10249                         case 2:
10250                           return 2; /* rfde */
10251                         case 4:
10252                           return 16; /* rfwo */
10253                         case 5:
10254                           return 17; /* rfwu */
10255                         }
10256                       break;
10257                     case 1:
10258                       return 223; /* rfi */
10259                     }
10260                   break;
10261                 case 4:
10262                   return 231; /* break */
10263                 case 5:
10264                   switch (Field_s_Slot_inst_get (insn))
10265                     {
10266                     case 0:
10267                       if (Field_t_Slot_inst_get (insn) == 0)
10268                         return 3; /* syscall */
10269                       break;
10270                     case 1:
10271                       if (Field_t_Slot_inst_get (insn) == 0)
10272                         return 4; /* simcall */
10273                       break;
10274                     }
10275                   break;
10276                 case 6:
10277                   return 120; /* rsil */
10278                 case 7:
10279                   if (Field_t_Slot_inst_get (insn) == 0)
10280                     return 224; /* waiti */
10281                   break;
10282                 }
10283               break;
10284             case 1:
10285               return 49; /* and */
10286             case 2:
10287               return 50; /* or */
10288             case 3:
10289               return 51; /* xor */
10290             case 4:
10291               switch (Field_r_Slot_inst_get (insn))
10292                 {
10293                 case 0:
10294                   if (Field_t_Slot_inst_get (insn) == 0)
10295                     return 102; /* ssr */
10296                   break;
10297                 case 1:
10298                   if (Field_t_Slot_inst_get (insn) == 0)
10299                     return 103; /* ssl */
10300                   break;
10301                 case 2:
10302                   if (Field_t_Slot_inst_get (insn) == 0)
10303                     return 104; /* ssa8l */
10304                   break;
10305                 case 3:
10306                   if (Field_t_Slot_inst_get (insn) == 0)
10307                     return 105; /* ssa8b */
10308                   break;
10309                 case 4:
10310                   if (Field_thi3_Slot_inst_get (insn) == 0)
10311                     return 106; /* ssai */
10312                   break;
10313                 case 8:
10314                   if (Field_s_Slot_inst_get (insn) == 0)
10315                     return 13; /* rotw */
10316                   break;
10317                 case 14:
10318                   return 339; /* nsa */
10319                 case 15:
10320                   return 340; /* nsau */
10321                 }
10322               break;
10323             case 5:
10324               switch (Field_r_Slot_inst_get (insn))
10325                 {
10326                 case 1:
10327                   return 329; /* hwwitlba */
10328                 case 3:
10329                   return 325; /* ritlb0 */
10330                 case 4:
10331                   if (Field_t_Slot_inst_get (insn) == 0)
10332                     return 323; /* iitlb */
10333                   break;
10334                 case 5:
10335                   return 324; /* pitlb */
10336                 case 6:
10337                   return 327; /* witlb */
10338                 case 7:
10339                   return 326; /* ritlb1 */
10340                 case 9:
10341                   return 330; /* hwwdtlba */
10342                 case 11:
10343                   return 320; /* rdtlb0 */
10344                 case 12:
10345                   if (Field_t_Slot_inst_get (insn) == 0)
10346                     return 318; /* idtlb */
10347                   break;
10348                 case 13:
10349                   return 319; /* pdtlb */
10350                 case 14:
10351                   return 322; /* wdtlb */
10352                 case 15:
10353                   return 321; /* rdtlb1 */
10354                 }
10355               break;
10356             case 6:
10357               switch (Field_s_Slot_inst_get (insn))
10358                 {
10359                 case 0:
10360                   return 95; /* neg */
10361                 case 1:
10362                   return 96; /* abs */
10363                 }
10364               break;
10365             case 8:
10366               return 41; /* add */
10367             case 9:
10368               return 43; /* addx2 */
10369             case 10:
10370               return 44; /* addx4 */
10371             case 11:
10372               return 45; /* addx8 */
10373             case 12:
10374               return 42; /* sub */
10375             case 13:
10376               return 46; /* subx2 */
10377             case 14:
10378               return 47; /* subx4 */
10379             case 15:
10380               return 48; /* subx8 */
10381             }
10382           break;
10383         case 1:
10384           switch (Field_op2_Slot_inst_get (insn))
10385             {
10386             case 0:
10387             case 1:
10388               return 111; /* slli */
10389             case 2:
10390             case 3:
10391               return 112; /* srai */
10392             case 4:
10393               return 113; /* srli */
10394             case 6:
10395               switch (Field_sr_Slot_inst_get (insn))
10396                 {
10397                 case 0:
10398                   return 129; /* xsr.lbeg */
10399                 case 1:
10400                   return 123; /* xsr.lend */
10401                 case 2:
10402                   return 126; /* xsr.lcount */
10403                 case 3:
10404                   return 132; /* xsr.sar */
10405                 case 5:
10406                   return 135; /* xsr.litbase */
10407                 case 12:
10408                   return 347; /* xsr.scompare1 */
10409                 case 72:
10410                   return 22; /* xsr.windowbase */
10411                 case 73:
10412                   return 25; /* xsr.windowstart */
10413                 case 83:
10414                   return 308; /* xsr.ptevaddr */
10415                 case 90:
10416                   return 311; /* xsr.rasid */
10417                 case 91:
10418                   return 314; /* xsr.itlbcfg */
10419                 case 92:
10420                   return 317; /* xsr.dtlbcfg */
10421                 case 96:
10422                   return 253; /* xsr.ibreakenable */
10423                 case 104:
10424                   return 265; /* xsr.ddr */
10425                 case 128:
10426                   return 247; /* xsr.ibreaka0 */
10427                 case 129:
10428                   return 250; /* xsr.ibreaka1 */
10429                 case 144:
10430                   return 235; /* xsr.dbreaka0 */
10431                 case 145:
10432                   return 241; /* xsr.dbreaka1 */
10433                 case 160:
10434                   return 238; /* xsr.dbreakc0 */
10435                 case 161:
10436                   return 244; /* xsr.dbreakc1 */
10437                 case 177:
10438                   return 144; /* xsr.epc1 */
10439                 case 178:
10440                   return 150; /* xsr.epc2 */
10441                 case 179:
10442                   return 156; /* xsr.epc3 */
10443                 case 180:
10444                   return 162; /* xsr.epc4 */
10445                 case 181:
10446                   return 168; /* xsr.epc5 */
10447                 case 182:
10448                   return 174; /* xsr.epc6 */
10449                 case 183:
10450                   return 180; /* xsr.epc7 */
10451                 case 192:
10452                   return 207; /* xsr.depc */
10453                 case 194:
10454                   return 186; /* xsr.eps2 */
10455                 case 195:
10456                   return 189; /* xsr.eps3 */
10457                 case 196:
10458                   return 192; /* xsr.eps4 */
10459                 case 197:
10460                   return 195; /* xsr.eps5 */
10461                 case 198:
10462                   return 198; /* xsr.eps6 */
10463                 case 199:
10464                   return 201; /* xsr.eps7 */
10465                 case 209:
10466                   return 147; /* xsr.excsave1 */
10467                 case 210:
10468                   return 153; /* xsr.excsave2 */
10469                 case 211:
10470                   return 159; /* xsr.excsave3 */
10471                 case 212:
10472                   return 165; /* xsr.excsave4 */
10473                 case 213:
10474                   return 171; /* xsr.excsave5 */
10475                 case 214:
10476                   return 177; /* xsr.excsave6 */
10477                 case 215:
10478                   return 183; /* xsr.excsave7 */
10479                 case 224:
10480                   return 333; /* xsr.cpenable */
10481                 case 228:
10482                   return 230; /* xsr.intenable */
10483                 case 230:
10484                   return 141; /* xsr.ps */
10485                 case 231:
10486                   return 220; /* xsr.vecbase */
10487                 case 232:
10488                   return 210; /* xsr.exccause */
10489                 case 233:
10490                   return 256; /* xsr.debugcause */
10491                 case 234:
10492                   return 271; /* xsr.ccount */
10493                 case 236:
10494                   return 259; /* xsr.icount */
10495                 case 237:
10496                   return 262; /* xsr.icountlevel */
10497                 case 238:
10498                   return 204; /* xsr.excvaddr */
10499                 case 240:
10500                   return 274; /* xsr.ccompare0 */
10501                 case 241:
10502                   return 277; /* xsr.ccompare1 */
10503                 case 242:
10504                   return 280; /* xsr.ccompare2 */
10505                 case 244:
10506                   return 213; /* xsr.misc0 */
10507                 case 245:
10508                   return 216; /* xsr.misc1 */
10509                 }
10510               break;
10511             case 8:
10512               return 108; /* src */
10513             case 9:
10514               if (Field_s_Slot_inst_get (insn) == 0)
10515                 return 109; /* srl */
10516               break;
10517             case 10:
10518               if (Field_t_Slot_inst_get (insn) == 0)
10519                 return 107; /* sll */
10520               break;
10521             case 11:
10522               if (Field_s_Slot_inst_get (insn) == 0)
10523                 return 110; /* sra */
10524               break;
10525             case 12:
10526               return 221; /* mul16u */
10527             case 13:
10528               return 222; /* mul16s */
10529             case 15:
10530               switch (Field_r_Slot_inst_get (insn))
10531                 {
10532                 case 0:
10533                   return 287; /* lict */
10534                 case 1:
10535                   return 289; /* sict */
10536                 case 2:
10537                   return 288; /* licw */
10538                 case 3:
10539                   return 290; /* sicw */
10540                 case 8:
10541                   return 305; /* ldct */
10542                 case 9:
10543                   return 304; /* sdct */
10544                 case 14:
10545                   if (Field_t_Slot_inst_get (insn) == 0)
10546                     return 266; /* rfdo */
10547                   if (Field_t_Slot_inst_get (insn) == 1)
10548                     return 267; /* rfdd */
10549                   break;
10550                 case 15:
10551                   return 328; /* ldpte */
10552                 }
10553               break;
10554             }
10555           break;
10556         case 2:
10557           switch (Field_op2_Slot_inst_get (insn))
10558             {
10559             case 8:
10560               return 352; /* mull */
10561             case 12:
10562               return 348; /* quou */
10563             case 13:
10564               return 349; /* quos */
10565             case 14:
10566               return 350; /* remu */
10567             case 15:
10568               return 351; /* rems */
10569             }
10570           break;
10571         case 3:
10572           switch (Field_op2_Slot_inst_get (insn))
10573             {
10574             case 0:
10575               switch (Field_sr_Slot_inst_get (insn))
10576                 {
10577                 case 0:
10578                   return 127; /* rsr.lbeg */
10579                 case 1:
10580                   return 121; /* rsr.lend */
10581                 case 2:
10582                   return 124; /* rsr.lcount */
10583                 case 3:
10584                   return 130; /* rsr.sar */
10585                 case 5:
10586                   return 133; /* rsr.litbase */
10587                 case 12:
10588                   return 345; /* rsr.scompare1 */
10589                 case 72:
10590                   return 20; /* rsr.windowbase */
10591                 case 73:
10592                   return 23; /* rsr.windowstart */
10593                 case 83:
10594                   return 307; /* rsr.ptevaddr */
10595                 case 90:
10596                   return 309; /* rsr.rasid */
10597                 case 91:
10598                   return 312; /* rsr.itlbcfg */
10599                 case 92:
10600                   return 315; /* rsr.dtlbcfg */
10601                 case 96:
10602                   return 251; /* rsr.ibreakenable */
10603                 case 104:
10604                   return 263; /* rsr.ddr */
10605                 case 128:
10606                   return 245; /* rsr.ibreaka0 */
10607                 case 129:
10608                   return 248; /* rsr.ibreaka1 */
10609                 case 144:
10610                   return 233; /* rsr.dbreaka0 */
10611                 case 145:
10612                   return 239; /* rsr.dbreaka1 */
10613                 case 160:
10614                   return 236; /* rsr.dbreakc0 */
10615                 case 161:
10616                   return 242; /* rsr.dbreakc1 */
10617                 case 176:
10618                   return 136; /* rsr.176 */
10619                 case 177:
10620                   return 142; /* rsr.epc1 */
10621                 case 178:
10622                   return 148; /* rsr.epc2 */
10623                 case 179:
10624                   return 154; /* rsr.epc3 */
10625                 case 180:
10626                   return 160; /* rsr.epc4 */
10627                 case 181:
10628                   return 166; /* rsr.epc5 */
10629                 case 182:
10630                   return 172; /* rsr.epc6 */
10631                 case 183:
10632                   return 178; /* rsr.epc7 */
10633                 case 192:
10634                   return 205; /* rsr.depc */
10635                 case 194:
10636                   return 184; /* rsr.eps2 */
10637                 case 195:
10638                   return 187; /* rsr.eps3 */
10639                 case 196:
10640                   return 190; /* rsr.eps4 */
10641                 case 197:
10642                   return 193; /* rsr.eps5 */
10643                 case 198:
10644                   return 196; /* rsr.eps6 */
10645                 case 199:
10646                   return 199; /* rsr.eps7 */
10647                 case 208:
10648                   return 138; /* rsr.208 */
10649                 case 209:
10650                   return 145; /* rsr.excsave1 */
10651                 case 210:
10652                   return 151; /* rsr.excsave2 */
10653                 case 211:
10654                   return 157; /* rsr.excsave3 */
10655                 case 212:
10656                   return 163; /* rsr.excsave4 */
10657                 case 213:
10658                   return 169; /* rsr.excsave5 */
10659                 case 214:
10660                   return 175; /* rsr.excsave6 */
10661                 case 215:
10662                   return 181; /* rsr.excsave7 */
10663                 case 224:
10664                   return 331; /* rsr.cpenable */
10665                 case 226:
10666                   return 225; /* rsr.interrupt */
10667                 case 228:
10668                   return 228; /* rsr.intenable */
10669                 case 230:
10670                   return 139; /* rsr.ps */
10671                 case 231:
10672                   return 218; /* rsr.vecbase */
10673                 case 232:
10674                   return 208; /* rsr.exccause */
10675                 case 233:
10676                   return 254; /* rsr.debugcause */
10677                 case 234:
10678                   return 269; /* rsr.ccount */
10679                 case 235:
10680                   return 217; /* rsr.prid */
10681                 case 236:
10682                   return 257; /* rsr.icount */
10683                 case 237:
10684                   return 260; /* rsr.icountlevel */
10685                 case 238:
10686                   return 202; /* rsr.excvaddr */
10687                 case 240:
10688                   return 272; /* rsr.ccompare0 */
10689                 case 241:
10690                   return 275; /* rsr.ccompare1 */
10691                 case 242:
10692                   return 278; /* rsr.ccompare2 */
10693                 case 244:
10694                   return 211; /* rsr.misc0 */
10695                 case 245:
10696                   return 214; /* rsr.misc1 */
10697                 }
10698               break;
10699             case 1:
10700               switch (Field_sr_Slot_inst_get (insn))
10701                 {
10702                 case 0:
10703                   return 128; /* wsr.lbeg */
10704                 case 1:
10705                   return 122; /* wsr.lend */
10706                 case 2:
10707                   return 125; /* wsr.lcount */
10708                 case 3:
10709                   return 131; /* wsr.sar */
10710                 case 5:
10711                   return 134; /* wsr.litbase */
10712                 case 12:
10713                   return 346; /* wsr.scompare1 */
10714                 case 72:
10715                   return 21; /* wsr.windowbase */
10716                 case 73:
10717                   return 24; /* wsr.windowstart */
10718                 case 83:
10719                   return 306; /* wsr.ptevaddr */
10720                 case 89:
10721                   return 268; /* wsr.mmid */
10722                 case 90:
10723                   return 310; /* wsr.rasid */
10724                 case 91:
10725                   return 313; /* wsr.itlbcfg */
10726                 case 92:
10727                   return 316; /* wsr.dtlbcfg */
10728                 case 96:
10729                   return 252; /* wsr.ibreakenable */
10730                 case 104:
10731                   return 264; /* wsr.ddr */
10732                 case 128:
10733                   return 246; /* wsr.ibreaka0 */
10734                 case 129:
10735                   return 249; /* wsr.ibreaka1 */
10736                 case 144:
10737                   return 234; /* wsr.dbreaka0 */
10738                 case 145:
10739                   return 240; /* wsr.dbreaka1 */
10740                 case 160:
10741                   return 237; /* wsr.dbreakc0 */
10742                 case 161:
10743                   return 243; /* wsr.dbreakc1 */
10744                 case 176:
10745                   return 137; /* wsr.176 */
10746                 case 177:
10747                   return 143; /* wsr.epc1 */
10748                 case 178:
10749                   return 149; /* wsr.epc2 */
10750                 case 179:
10751                   return 155; /* wsr.epc3 */
10752                 case 180:
10753                   return 161; /* wsr.epc4 */
10754                 case 181:
10755                   return 167; /* wsr.epc5 */
10756                 case 182:
10757                   return 173; /* wsr.epc6 */
10758                 case 183:
10759                   return 179; /* wsr.epc7 */
10760                 case 192:
10761                   return 206; /* wsr.depc */
10762                 case 194:
10763                   return 185; /* wsr.eps2 */
10764                 case 195:
10765                   return 188; /* wsr.eps3 */
10766                 case 196:
10767                   return 191; /* wsr.eps4 */
10768                 case 197:
10769                   return 194; /* wsr.eps5 */
10770                 case 198:
10771                   return 197; /* wsr.eps6 */
10772                 case 199:
10773                   return 200; /* wsr.eps7 */
10774                 case 209:
10775                   return 146; /* wsr.excsave1 */
10776                 case 210:
10777                   return 152; /* wsr.excsave2 */
10778                 case 211:
10779                   return 158; /* wsr.excsave3 */
10780                 case 212:
10781                   return 164; /* wsr.excsave4 */
10782                 case 213:
10783                   return 170; /* wsr.excsave5 */
10784                 case 214:
10785                   return 176; /* wsr.excsave6 */
10786                 case 215:
10787                   return 182; /* wsr.excsave7 */
10788                 case 224:
10789                   return 332; /* wsr.cpenable */
10790                 case 226:
10791                   return 226; /* wsr.intset */
10792                 case 227:
10793                   return 227; /* wsr.intclear */
10794                 case 228:
10795                   return 229; /* wsr.intenable */
10796                 case 230:
10797                   return 140; /* wsr.ps */
10798                 case 231:
10799                   return 219; /* wsr.vecbase */
10800                 case 232:
10801                   return 209; /* wsr.exccause */
10802                 case 233:
10803                   return 255; /* wsr.debugcause */
10804                 case 234:
10805                   return 270; /* wsr.ccount */
10806                 case 236:
10807                   return 258; /* wsr.icount */
10808                 case 237:
10809                   return 261; /* wsr.icountlevel */
10810                 case 238:
10811                   return 203; /* wsr.excvaddr */
10812                 case 240:
10813                   return 273; /* wsr.ccompare0 */
10814                 case 241:
10815                   return 276; /* wsr.ccompare1 */
10816                 case 242:
10817                   return 279; /* wsr.ccompare2 */
10818                 case 244:
10819                   return 212; /* wsr.misc0 */
10820                 case 245:
10821                   return 215; /* wsr.misc1 */
10822                 }
10823               break;
10824             case 2:
10825               return 341; /* sext */
10826             case 3:
10827               return 334; /* clamps */
10828             case 4:
10829               return 335; /* min */
10830             case 5:
10831               return 336; /* max */
10832             case 6:
10833               return 337; /* minu */
10834             case 7:
10835               return 338; /* maxu */
10836             case 8:
10837               return 91; /* moveqz */
10838             case 9:
10839               return 92; /* movnez */
10840             case 10:
10841               return 93; /* movltz */
10842             case 11:
10843               return 94; /* movgez */
10844             case 14:
10845               if (Field_st_Slot_inst_get (insn) == 231)
10846                 return 37; /* rur.threadptr */
10847               break;
10848             case 15:
10849               if (Field_sr_Slot_inst_get (insn) == 231)
10850                 return 38; /* wur.threadptr */
10851               break;
10852             }
10853           break;
10854         case 4:
10855         case 5:
10856           return 78; /* extui */
10857         case 9:
10858           switch (Field_op2_Slot_inst_get (insn))
10859             {
10860             case 0:
10861               return 18; /* l32e */
10862             case 4:
10863               return 19; /* s32e */
10864             }
10865           break;
10866         }
10867       break;
10868     case 1:
10869       return 85; /* l32r */
10870     case 2:
10871       switch (Field_r_Slot_inst_get (insn))
10872         {
10873         case 0:
10874           return 86; /* l8ui */
10875         case 1:
10876           return 82; /* l16ui */
10877         case 2:
10878           return 84; /* l32i */
10879         case 4:
10880           return 101; /* s8i */
10881         case 5:
10882           return 99; /* s16i */
10883         case 6:
10884           return 100; /* s32i */
10885         case 7:
10886           switch (Field_t_Slot_inst_get (insn))
10887             {
10888             case 0:
10889               return 297; /* dpfr */
10890             case 1:
10891               return 298; /* dpfw */
10892             case 2:
10893               return 299; /* dpfro */
10894             case 3:
10895               return 300; /* dpfwo */
10896             case 4:
10897               return 291; /* dhwb */
10898             case 5:
10899               return 292; /* dhwbi */
10900             case 6:
10901               return 295; /* dhi */
10902             case 7:
10903               return 296; /* dii */
10904             case 8:
10905               switch (Field_op1_Slot_inst_get (insn))
10906                 {
10907                 case 0:
10908                   return 301; /* dpfl */
10909                 case 2:
10910                   return 302; /* dhu */
10911                 case 3:
10912                   return 303; /* diu */
10913                 case 4:
10914                   return 293; /* diwb */
10915                 case 5:
10916                   return 294; /* diwbi */
10917                 }
10918               break;
10919             case 12:
10920               return 281; /* ipf */
10921             case 13:
10922               switch (Field_op1_Slot_inst_get (insn))
10923                 {
10924                 case 0:
10925                   return 283; /* ipfl */
10926                 case 2:
10927                   return 284; /* ihu */
10928                 case 3:
10929                   return 285; /* iiu */
10930                 }
10931               break;
10932             case 14:
10933               return 282; /* ihi */
10934             case 15:
10935               return 286; /* iii */
10936             }
10937           break;
10938         case 9:
10939           return 83; /* l16si */
10940         case 10:
10941           return 90; /* movi */
10942         case 11:
10943           return 342; /* l32ai */
10944         case 12:
10945           return 39; /* addi */
10946         case 13:
10947           return 40; /* addmi */
10948         case 14:
10949           return 344; /* s32c1i */
10950         case 15:
10951           return 343; /* s32ri */
10952         }
10953       break;
10954     case 5:
10955       switch (Field_n_Slot_inst_get (insn))
10956         {
10957         case 0:
10958           return 76; /* call0 */
10959         case 1:
10960           return 7; /* call4 */
10961         case 2:
10962           return 6; /* call8 */
10963         case 3:
10964           return 5; /* call12 */
10965         }
10966       break;
10967     case 6:
10968       switch (Field_n_Slot_inst_get (insn))
10969         {
10970         case 0:
10971           return 80; /* j */
10972         case 1:
10973           switch (Field_m_Slot_inst_get (insn))
10974             {
10975             case 0:
10976               return 72; /* beqz */
10977             case 1:
10978               return 73; /* bnez */
10979             case 2:
10980               return 75; /* bltz */
10981             case 3:
10982               return 74; /* bgez */
10983             }
10984           break;
10985         case 2:
10986           switch (Field_m_Slot_inst_get (insn))
10987             {
10988             case 0:
10989               return 52; /* beqi */
10990             case 1:
10991               return 53; /* bnei */
10992             case 2:
10993               return 55; /* blti */
10994             case 3:
10995               return 54; /* bgei */
10996             }
10997           break;
10998         case 3:
10999           switch (Field_m_Slot_inst_get (insn))
11000             {
11001             case 0:
11002               return 11; /* entry */
11003             case 1:
11004               switch (Field_r_Slot_inst_get (insn))
11005                 {
11006                 case 8:
11007                   return 87; /* loop */
11008                 case 9:
11009                   return 88; /* loopnez */
11010                 case 10:
11011                   return 89; /* loopgtz */
11012                 }
11013               break;
11014             case 2:
11015               return 59; /* bltui */
11016             case 3:
11017               return 58; /* bgeui */
11018             }
11019           break;
11020         }
11021       break;
11022     case 7:
11023       switch (Field_r_Slot_inst_get (insn))
11024         {
11025         case 0:
11026           return 67; /* bnone */
11027         case 1:
11028           return 60; /* beq */
11029         case 2:
11030           return 63; /* blt */
11031         case 3:
11032           return 65; /* bltu */
11033         case 4:
11034           return 68; /* ball */
11035         case 5:
11036           return 70; /* bbc */
11037         case 6:
11038         case 7:
11039           return 56; /* bbci */
11040         case 8:
11041           return 66; /* bany */
11042         case 9:
11043           return 61; /* bne */
11044         case 10:
11045           return 62; /* bge */
11046         case 11:
11047           return 64; /* bgeu */
11048         case 12:
11049           return 69; /* bnall */
11050         case 13:
11051           return 71; /* bbs */
11052         case 14:
11053         case 15:
11054           return 57; /* bbsi */
11055         }
11056       break;
11057     }
11058   return 0;
11059 }
11060
11061 static int
11062 Slot_inst16b_decode (const xtensa_insnbuf insn)
11063 {
11064   switch (Field_op0_Slot_inst16b_get (insn))
11065     {
11066     case 12:
11067       switch (Field_i_Slot_inst16b_get (insn))
11068         {
11069         case 0:
11070           return 33; /* movi.n */
11071         case 1:
11072           switch (Field_z_Slot_inst16b_get (insn))
11073             {
11074             case 0:
11075               return 28; /* beqz.n */
11076             case 1:
11077               return 29; /* bnez.n */
11078             }
11079           break;
11080         }
11081       break;
11082     case 13:
11083       switch (Field_r_Slot_inst16b_get (insn))
11084         {
11085         case 0:
11086           return 32; /* mov.n */
11087         case 15:
11088           switch (Field_t_Slot_inst16b_get (insn))
11089             {
11090             case 0:
11091               return 35; /* ret.n */
11092             case 1:
11093               return 15; /* retw.n */
11094             case 2:
11095               return 232; /* break.n */
11096             case 3:
11097               if (Field_s_Slot_inst16b_get (insn) == 0)
11098                 return 34; /* nop.n */
11099               break;
11100             case 6:
11101               if (Field_s_Slot_inst16b_get (insn) == 0)
11102                 return 30; /* ill.n */
11103               break;
11104             }
11105           break;
11106         }
11107       break;
11108     }
11109   return 0;
11110 }
11111
11112 static int
11113 Slot_inst16a_decode (const xtensa_insnbuf insn)
11114 {
11115   switch (Field_op0_Slot_inst16a_get (insn))
11116     {
11117     case 8:
11118       return 31; /* l32i.n */
11119     case 9:
11120       return 36; /* s32i.n */
11121     case 10:
11122       return 26; /* add.n */
11123     case 11:
11124       return 27; /* addi.n */
11125     }
11126   return 0;
11127 }
11128
11129 \f
11130 /* Instruction slots.  */
11131
11132 static void
11133 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
11134                             xtensa_insnbuf slotbuf)
11135 {
11136   slotbuf[0] = (insn[0] & 0xffffff);
11137 }
11138
11139 static void
11140 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
11141                             const xtensa_insnbuf slotbuf)
11142 {
11143   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
11144 }
11145
11146 static void
11147 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
11148                                 xtensa_insnbuf slotbuf)
11149 {
11150   slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
11151 }
11152
11153 static void
11154 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
11155                                 const xtensa_insnbuf slotbuf)
11156 {
11157   insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
11158 }
11159
11160 static void
11161 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
11162                                 xtensa_insnbuf slotbuf)
11163 {
11164   slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
11165 }
11166
11167 static void
11168 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
11169                                 const xtensa_insnbuf slotbuf)
11170 {
11171   insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
11172 }
11173
11174 static xtensa_get_field_fn
11175 Slot_inst_get_field_fns[] = {
11176   Field_t_Slot_inst_get,
11177   Field_bbi4_Slot_inst_get,
11178   Field_bbi_Slot_inst_get,
11179   Field_imm12_Slot_inst_get,
11180   Field_imm8_Slot_inst_get,
11181   Field_s_Slot_inst_get,
11182   Field_imm12b_Slot_inst_get,
11183   Field_imm16_Slot_inst_get,
11184   Field_m_Slot_inst_get,
11185   Field_n_Slot_inst_get,
11186   Field_offset_Slot_inst_get,
11187   Field_op0_Slot_inst_get,
11188   Field_op1_Slot_inst_get,
11189   Field_op2_Slot_inst_get,
11190   Field_r_Slot_inst_get,
11191   Field_sa4_Slot_inst_get,
11192   Field_sae4_Slot_inst_get,
11193   Field_sae_Slot_inst_get,
11194   Field_sal_Slot_inst_get,
11195   Field_sargt_Slot_inst_get,
11196   Field_sas4_Slot_inst_get,
11197   Field_sas_Slot_inst_get,
11198   Field_sr_Slot_inst_get,
11199   Field_st_Slot_inst_get,
11200   Field_thi3_Slot_inst_get,
11201   Field_imm4_Slot_inst_get,
11202   Field_mn_Slot_inst_get,
11203   0,
11204   0,
11205   0,
11206   0,
11207   0,
11208   0,
11209   0,
11210   0,
11211   Field_xt_wbr15_imm_Slot_inst_get,
11212   Field_xt_wbr18_imm_Slot_inst_get,
11213   Implicit_Field_ar0_get,
11214   Implicit_Field_ar4_get,
11215   Implicit_Field_ar8_get,
11216   Implicit_Field_ar12_get
11217 };
11218
11219 static xtensa_set_field_fn
11220 Slot_inst_set_field_fns[] = {
11221   Field_t_Slot_inst_set,
11222   Field_bbi4_Slot_inst_set,
11223   Field_bbi_Slot_inst_set,
11224   Field_imm12_Slot_inst_set,
11225   Field_imm8_Slot_inst_set,
11226   Field_s_Slot_inst_set,
11227   Field_imm12b_Slot_inst_set,
11228   Field_imm16_Slot_inst_set,
11229   Field_m_Slot_inst_set,
11230   Field_n_Slot_inst_set,
11231   Field_offset_Slot_inst_set,
11232   Field_op0_Slot_inst_set,
11233   Field_op1_Slot_inst_set,
11234   Field_op2_Slot_inst_set,
11235   Field_r_Slot_inst_set,
11236   Field_sa4_Slot_inst_set,
11237   Field_sae4_Slot_inst_set,
11238   Field_sae_Slot_inst_set,
11239   Field_sal_Slot_inst_set,
11240   Field_sargt_Slot_inst_set,
11241   Field_sas4_Slot_inst_set,
11242   Field_sas_Slot_inst_set,
11243   Field_sr_Slot_inst_set,
11244   Field_st_Slot_inst_set,
11245   Field_thi3_Slot_inst_set,
11246   Field_imm4_Slot_inst_set,
11247   Field_mn_Slot_inst_set,
11248   0,
11249   0,
11250   0,
11251   0,
11252   0,
11253   0,
11254   0,
11255   0,
11256   Field_xt_wbr15_imm_Slot_inst_set,
11257   Field_xt_wbr18_imm_Slot_inst_set,
11258   Implicit_Field_set,
11259   Implicit_Field_set,
11260   Implicit_Field_set,
11261   Implicit_Field_set
11262 };
11263
11264 static xtensa_get_field_fn
11265 Slot_inst16a_get_field_fns[] = {
11266   Field_t_Slot_inst16a_get,
11267   0,
11268   0,
11269   0,
11270   0,
11271   Field_s_Slot_inst16a_get,
11272   0,
11273   0,
11274   0,
11275   0,
11276   0,
11277   Field_op0_Slot_inst16a_get,
11278   0,
11279   0,
11280   Field_r_Slot_inst16a_get,
11281   0,
11282   0,
11283   0,
11284   0,
11285   0,
11286   0,
11287   0,
11288   Field_sr_Slot_inst16a_get,
11289   Field_st_Slot_inst16a_get,
11290   0,
11291   Field_imm4_Slot_inst16a_get,
11292   0,
11293   Field_i_Slot_inst16a_get,
11294   Field_imm6lo_Slot_inst16a_get,
11295   Field_imm6hi_Slot_inst16a_get,
11296   Field_imm7lo_Slot_inst16a_get,
11297   Field_imm7hi_Slot_inst16a_get,
11298   Field_z_Slot_inst16a_get,
11299   Field_imm6_Slot_inst16a_get,
11300   Field_imm7_Slot_inst16a_get,
11301   0,
11302   0,
11303   Implicit_Field_ar0_get,
11304   Implicit_Field_ar4_get,
11305   Implicit_Field_ar8_get,
11306   Implicit_Field_ar12_get
11307 };
11308
11309 static xtensa_set_field_fn
11310 Slot_inst16a_set_field_fns[] = {
11311   Field_t_Slot_inst16a_set,
11312   0,
11313   0,
11314   0,
11315   0,
11316   Field_s_Slot_inst16a_set,
11317   0,
11318   0,
11319   0,
11320   0,
11321   0,
11322   Field_op0_Slot_inst16a_set,
11323   0,
11324   0,
11325   Field_r_Slot_inst16a_set,
11326   0,
11327   0,
11328   0,
11329   0,
11330   0,
11331   0,
11332   0,
11333   Field_sr_Slot_inst16a_set,
11334   Field_st_Slot_inst16a_set,
11335   0,
11336   Field_imm4_Slot_inst16a_set,
11337   0,
11338   Field_i_Slot_inst16a_set,
11339   Field_imm6lo_Slot_inst16a_set,
11340   Field_imm6hi_Slot_inst16a_set,
11341   Field_imm7lo_Slot_inst16a_set,
11342   Field_imm7hi_Slot_inst16a_set,
11343   Field_z_Slot_inst16a_set,
11344   Field_imm6_Slot_inst16a_set,
11345   Field_imm7_Slot_inst16a_set,
11346   0,
11347   0,
11348   Implicit_Field_set,
11349   Implicit_Field_set,
11350   Implicit_Field_set,
11351   Implicit_Field_set
11352 };
11353
11354 static xtensa_get_field_fn
11355 Slot_inst16b_get_field_fns[] = {
11356   Field_t_Slot_inst16b_get,
11357   0,
11358   0,
11359   0,
11360   0,
11361   Field_s_Slot_inst16b_get,
11362   0,
11363   0,
11364   0,
11365   0,
11366   0,
11367   Field_op0_Slot_inst16b_get,
11368   0,
11369   0,
11370   Field_r_Slot_inst16b_get,
11371   0,
11372   0,
11373   0,
11374   0,
11375   0,
11376   0,
11377   0,
11378   Field_sr_Slot_inst16b_get,
11379   Field_st_Slot_inst16b_get,
11380   0,
11381   Field_imm4_Slot_inst16b_get,
11382   0,
11383   Field_i_Slot_inst16b_get,
11384   Field_imm6lo_Slot_inst16b_get,
11385   Field_imm6hi_Slot_inst16b_get,
11386   Field_imm7lo_Slot_inst16b_get,
11387   Field_imm7hi_Slot_inst16b_get,
11388   Field_z_Slot_inst16b_get,
11389   Field_imm6_Slot_inst16b_get,
11390   Field_imm7_Slot_inst16b_get,
11391   0,
11392   0,
11393   Implicit_Field_ar0_get,
11394   Implicit_Field_ar4_get,
11395   Implicit_Field_ar8_get,
11396   Implicit_Field_ar12_get
11397 };
11398
11399 static xtensa_set_field_fn
11400 Slot_inst16b_set_field_fns[] = {
11401   Field_t_Slot_inst16b_set,
11402   0,
11403   0,
11404   0,
11405   0,
11406   Field_s_Slot_inst16b_set,
11407   0,
11408   0,
11409   0,
11410   0,
11411   0,
11412   Field_op0_Slot_inst16b_set,
11413   0,
11414   0,
11415   Field_r_Slot_inst16b_set,
11416   0,
11417   0,
11418   0,
11419   0,
11420   0,
11421   0,
11422   0,
11423   Field_sr_Slot_inst16b_set,
11424   Field_st_Slot_inst16b_set,
11425   0,
11426   Field_imm4_Slot_inst16b_set,
11427   0,
11428   Field_i_Slot_inst16b_set,
11429   Field_imm6lo_Slot_inst16b_set,
11430   Field_imm6hi_Slot_inst16b_set,
11431   Field_imm7lo_Slot_inst16b_set,
11432   Field_imm7hi_Slot_inst16b_set,
11433   Field_z_Slot_inst16b_set,
11434   Field_imm6_Slot_inst16b_set,
11435   Field_imm7_Slot_inst16b_set,
11436   0,
11437   0,
11438   Implicit_Field_set,
11439   Implicit_Field_set,
11440   Implicit_Field_set,
11441   Implicit_Field_set
11442 };
11443
11444 static xtensa_slot_internal slots[] = {
11445   { "Inst", "x24", 0,
11446     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
11447     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
11448     Slot_inst_decode, "nop" },
11449   { "Inst16a", "x16a", 0,
11450     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
11451     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
11452     Slot_inst16a_decode, "" },
11453   { "Inst16b", "x16b", 0,
11454     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
11455     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
11456     Slot_inst16b_decode, "nop.n" }
11457 };
11458
11459 \f
11460 /* Instruction formats.  */
11461
11462 static void
11463 Format_x24_encode (xtensa_insnbuf insn)
11464 {
11465   insn[0] = 0;
11466 }
11467
11468 static void
11469 Format_x16a_encode (xtensa_insnbuf insn)
11470 {
11471   insn[0] = 0x800000;
11472 }
11473
11474 static void
11475 Format_x16b_encode (xtensa_insnbuf insn)
11476 {
11477   insn[0] = 0xc00000;
11478 }
11479
11480 static int Format_x24_slots[] = { 0 };
11481
11482 static int Format_x16a_slots[] = { 1 };
11483
11484 static int Format_x16b_slots[] = { 2 };
11485
11486 static xtensa_format_internal formats[] = {
11487   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
11488   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
11489   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
11490 };
11491
11492
11493 static int
11494 format_decoder (const xtensa_insnbuf insn)
11495 {
11496   if ((insn[0] & 0x800000) == 0)
11497     return 0; /* x24 */
11498   if ((insn[0] & 0xc00000) == 0x800000)
11499     return 1; /* x16a */
11500   if ((insn[0] & 0xe00000) == 0xc00000)
11501     return 2; /* x16b */
11502   return -1;
11503 }
11504
11505 static int length_table[16] = {
11506   3,
11507   3,
11508   3,
11509   3,
11510   3,
11511   3,
11512   3,
11513   3,
11514   2,
11515   2,
11516   2,
11517   2,
11518   2,
11519   2,
11520   -1,
11521   -1
11522 };
11523
11524 static int
11525 length_decoder (const unsigned char *insn)
11526 {
11527   int op0 = (insn[0] >> 4) & 0xf;
11528   return length_table[op0];
11529 }
11530
11531 \f
11532 /* Top-level ISA structure.  */
11533
11534 xtensa_isa_internal xtensa_modules = {
11535   1 /* big-endian */,
11536   3 /* insn_size */, 0,
11537   3, formats, format_decoder, length_decoder,
11538   3, slots,
11539   41 /* num_fields */,
11540   75, operands,
11541   286, iclasses,
11542   353, opcodes, 0,
11543   1, regfiles,
11544   NUM_STATES, states, 0,
11545   NUM_SYSREGS, sysregs, 0,
11546   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
11547   0, interfaces, 0,
11548   0, funcUnits, 0
11549 };