1 /* Instruction printing code for the AMD 29000
2 Copyright (C) 1990 Free Software Foundation, Inc.
3 Contributed by Cygnus Support. Written by Jim Kingdon.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 1, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 # include "opcode/a29k.h"
31 # include "opcode/a29k.h"
32 # define am29k_opcodes a29k_opcodes
33 # define am29k_opcode a29k_opcode
34 # define NUM_OPCODES num_opcodes
35 # define fprintf_filtered fprintf
39 /* Print a symbolic representation of a general-purpose
40 register number NUM on STREAM.
41 NUM is a number as found in the instruction, not as found in
42 debugging symbols; it must be in the range 0-255. */
44 print_general (num
, stream
)
49 fprintf_filtered (stream
, "gr%d", num
);
51 fprintf_filtered (stream
, "lr%d", num
- 128);
54 /* Like print_general but a special-purpose register.
56 The mnemonics used by the AMD assembler are not quite the same
57 as the ones in the User's Manual. We use the ones that the
60 print_special (num
, stream
)
64 /* Register names of registers 0-SPEC0_NUM-1. */
65 static char *spec0_names
[] = {
66 "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
67 "pc0", "pc1", "pc2", "mmu", "lru"
69 #define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
71 /* Register names of registers 128-128+SPEC128_NUM-1. */
72 static char *spec128_names
[] = {
73 "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
75 #define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
77 /* Register names of registers 160-160+SPEC160_NUM-1. */
78 static char *spec160_names
[] = {
79 "fpe", "inte", "fps", "sr163", "exop"
81 #define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
84 fprintf_filtered (stream
, spec0_names
[num
]);
85 else if (num
>= 128 && num
< 128 + SPEC128_NUM
)
86 fprintf_filtered (stream
, spec128_names
[num
-128]);
87 else if (num
>= 160 && num
< 160 + SPEC160_NUM
)
88 fprintf_filtered (stream
, spec160_names
[num
-160]);
90 fprintf_filtered (stream
, "sr%d", num
);
93 /* Is an instruction with OPCODE a delayed branch? */
95 is_delayed_branch (opcode
)
98 return (opcode
== 0xa8 || opcode
== 0xa9 || opcode
== 0xa0 || opcode
== 0xa1
99 || opcode
== 0xa4 || opcode
== 0xa5
100 || opcode
== 0xb4 || opcode
== 0xb5
101 || opcode
== 0xc4 || opcode
== 0xc0
102 || opcode
== 0xac || opcode
== 0xad
106 /* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}.
107 Note that the amd can be set up as either
108 big or little-endian (the tm file says which) and we can't assume
109 the host machine is the same. */
111 find_bytes (insn
, insn0
, insn8
, insn16
, insn24
)
113 unsigned char *insn0
;
114 unsigned char *insn8
;
115 unsigned char *insn16
;
116 unsigned char *insn24
;
118 #if TARGET_BYTE_ORDER == BIG_ENDIAN
123 #else /* Little-endian. */
128 #endif /* Little-endian. */
131 /* Print one instruction from MEMADDR on STREAM.
132 Return the size of the instruction (always 4 on am29k). */
134 print_insn (memaddr
, stream
)
139 print_insn_a29k (memaddr
, buffer
, stream
)
145 /* The raw instruction. */
148 /* The four bytes of the instruction. */
149 unsigned char insn24
, insn16
, insn8
, insn0
;
151 CONST
struct am29k_opcode
*opcode
;
154 read_memory (memaddr
, &insn
[0], 4);
156 insn
[0] = ((char*)buffer
)[0];
157 insn
[1] = ((char*)buffer
)[1];
158 insn
[2] = ((char*)buffer
)[2];
159 insn
[3] = ((char*)buffer
)[3];
162 find_bytes (insn
, &insn0
, &insn8
, &insn16
, &insn24
);
164 value
= (insn24
<< 24) + (insn16
<< 16) + (insn8
<< 8) + insn0
;
165 /* Handle the nop (aseq 0x40,gr1,gr1) specially */
166 if ((insn24
==0x70) && (insn16
==0x40) && (insn8
==0x01) && (insn0
==0x01)) {
167 fprintf_filtered (stream
,"nop");
172 /* The opcode is always in insn24. */
173 for (opcode
= &am29k_opcodes
[0];
174 opcode
< &am29k_opcodes
[NUM_OPCODES
];
178 if (insn24
== opcode
->opcode
)
180 if (insn24
== (opcode
->opcode
>> 24))
185 fprintf_filtered (stream
, "%s ", opcode
->name
);
186 for (s
= opcode
->args
; *s
!= '\0'; ++s
)
191 print_general (insn8
, stream
);
195 print_general (insn0
, stream
);
199 print_general (insn16
, stream
);
203 fprintf_filtered (stream
, "%d", insn0
);
207 fprintf_filtered (stream
, "%d", (insn16
<< 8) + insn0
);
211 fprintf_filtered (stream
, "0x%x",
212 (insn16
<< 24) + (insn0
<< 16));
216 fprintf_filtered (stream
, "%d",
217 ((insn16
<< 8) + insn0
) | 0xffff0000);
221 /* This output looks just like absolute addressing, but
222 maybe that's OK (it's what the GDB 68k and EBMON
223 29k disassemblers do). */
224 /* All the shifting is to sign-extend it. p*/
227 (((int)((insn16
<< 10) + (insn0
<< 2)) << 14) >> 14),
232 print_address ((insn16
<< 10) + (insn0
<< 2), stream
);
236 fprintf_filtered (stream
, "%d", insn16
>> 7);
240 fprintf_filtered (stream
, "0x%x", insn16
& 0x7f);
244 fprintf_filtered (stream
, "%x", insn16
);
248 print_special (insn8
, stream
);
252 fprintf_filtered (stream
, "%d", insn0
>> 7);
256 fprintf_filtered (stream
, "%d", (insn0
>> 4) & 7);
260 fprintf_filtered (stream
, "%d", (insn0
>> 2) & 3);
264 fprintf_filtered (stream
, "%d", insn0
& 3);
268 fprintf_filtered (stream
, "%d", (value
>> 18) & 0xf);
272 fprintf_filtered (stream
, "%d", (value
>> 16) & 3);
276 fprintf_filtered (stream
, "%c", *s
);
280 /* Now we look for a const,consth pair of instructions,
281 in which case we try to print the symbolic address. */
282 if (insn24
== 2) /* consth */
286 unsigned char prev_insn0
, prev_insn8
, prev_insn16
, prev_insn24
;
289 errcode
= target_read_memory (memaddr
- 4,
293 prev_insn
[0] = ((char*)buffer
)[0-4];
294 prev_insn
[1] = ((char*)buffer
)[1-4];
295 prev_insn
[2] = ((char*)buffer
)[2-4];
296 prev_insn
[3] = ((char*)buffer
)[3-4];
301 /* If it is a delayed branch, we need to look at the
302 instruction before the delayed brach to handle
309 find_bytes (prev_insn
, &prev_insn0
, &prev_insn8
,
310 &prev_insn16
, &prev_insn24
);
311 if (is_delayed_branch (prev_insn24
))
314 errcode
= target_read_memory
315 (memaddr
- 8, &prev_insn
[0], 4);
317 prev_insn
[0] = ((char*)buffer
)[0-8];
318 prev_insn
[1] = ((char*)buffer
)[1-8];
319 prev_insn
[2] = ((char*)buffer
)[2-8];
320 prev_insn
[3] = ((char*)buffer
)[3-8];
323 find_bytes (prev_insn
, &prev_insn0
, &prev_insn8
,
324 &prev_insn16
, &prev_insn24
);
328 /* If there was a problem reading memory, then assume
329 the previous instruction was not const. */
332 /* Is it const to the same register? */
334 && prev_insn8
== insn8
)
336 fprintf_filtered (stream
, "\t; ");
337 print_address (((insn16
<< 24) + (insn0
<< 16)
338 + (prev_insn16
<< 8) + (prev_insn0
)),
347 fprintf_filtered (stream
, ".word %8x",
348 (insn24
<< 24) + (insn16
<< 16) + (insn8
<< 8) + insn0
);
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