1 /* Stolen from GDB on 27 mar 92 by steve chamberlain */
2 /* Print i386 instructions for GDB, the GNU debugger.
3 Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
22 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
27 * The main tables describing the instructions is essentially a copy
28 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
29 * Programmers Manual. Usually, there is a capital letter, followed
30 * by a small letter. The capital letter tell the addressing mode,
31 * and the small letter tells about the operand size. Refer to
32 * the Intel manual for details.
42 /* For the GDB interface at the bottom of the file... */
46 #define Eb OP_E, b_mode
47 #define indirEb OP_indirE, b_mode
48 #define Gb OP_G, b_mode
49 #define Ev OP_E, v_mode
50 #define indirEv OP_indirE, v_mode
51 #define Ew OP_E, w_mode
52 #define Ma OP_E, v_mode
54 #define Mp OP_E, 0 /* ? */
55 #define Gv OP_G, v_mode
56 #define Gw OP_G, w_mode
57 #define Rw OP_rm, w_mode
58 #define Rd OP_rm, d_mode
59 #define Ib OP_I, b_mode
60 #define sIb OP_sI, b_mode /* sign extened byte */
61 #define Iv OP_I, v_mode
62 #define Iw OP_I, w_mode
63 #define Jb OP_J, b_mode
64 #define Jv OP_J, v_mode
66 #define Cd OP_C, d_mode
67 #define Dd OP_D, d_mode
68 #define Td OP_T, d_mode
70 #define eAX OP_REG, eAX_reg
71 #define eBX OP_REG, eBX_reg
72 #define eCX OP_REG, eCX_reg
73 #define eDX OP_REG, eDX_reg
74 #define eSP OP_REG, eSP_reg
75 #define eBP OP_REG, eBP_reg
76 #define eSI OP_REG, eSI_reg
77 #define eDI OP_REG, eDI_reg
78 #define AL OP_REG, al_reg
79 #define CL OP_REG, cl_reg
80 #define DL OP_REG, dl_reg
81 #define BL OP_REG, bl_reg
82 #define AH OP_REG, ah_reg
83 #define CH OP_REG, ch_reg
84 #define DH OP_REG, dh_reg
85 #define BH OP_REG, bh_reg
86 #define AX OP_REG, ax_reg
87 #define DX OP_REG, dx_reg
88 #define indirDX OP_REG, indir_dx_reg
90 #define Sw OP_SEG, w_mode
91 #define Ap OP_DIR, lptr
92 #define Av OP_DIR, v_mode
93 #define Ob OP_OFF, b_mode
94 #define Ov OP_OFF, v_mode
95 #define Xb OP_DSSI, b_mode
96 #define Xv OP_DSSI, v_mode
97 #define Yb OP_ESDI, b_mode
98 #define Yv OP_ESDI, v_mode
100 #define es OP_REG, es_reg
101 #define ss OP_REG, ss_reg
102 #define cs OP_REG, cs_reg
103 #define ds OP_REG, ds_reg
104 #define fs OP_REG, fs_reg
105 #define gs OP_REG, gs_reg
107 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
108 int OP_J(), OP_SEG();
109 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
110 int OP_D(), OP_T(), OP_rm();
153 #define indir_dx_reg 150
155 #define GRP1b NULL, NULL, 0
156 #define GRP1S NULL, NULL, 1
157 #define GRP1Ss NULL, NULL, 2
158 #define GRP2b NULL, NULL, 3
159 #define GRP2S NULL, NULL, 4
160 #define GRP2b_one NULL, NULL, 5
161 #define GRP2S_one NULL, NULL, 6
162 #define GRP2b_cl NULL, NULL, 7
163 #define GRP2S_cl NULL, NULL, 8
164 #define GRP3b NULL, NULL, 9
165 #define GRP3S NULL, NULL, 10
166 #define GRP4 NULL, NULL, 11
167 #define GRP5 NULL, NULL, 12
168 #define GRP6 NULL, NULL, 13
169 #define GRP7 NULL, NULL, 14
170 #define GRP8 NULL, NULL, 15
173 #define FLOAT NULL, NULL, FLOATCODE
185 struct dis386 dis386
[] = {
203 { "(bad)" }, /* 0x0f extended opcode escape */
229 { "(bad)" }, /* SEG ES prefix */
238 { "(bad)" }, /* SEG CS prefix */
247 { "(bad)" }, /* SEG SS prefix */
256 { "(bad)" }, /* SEG DS prefix */
297 { "boundS", Gv
, Ma
},
299 { "(bad)" }, /* seg fs */
300 { "(bad)" }, /* seg gs */
301 { "(bad)" }, /* op size prefix */
302 { "(bad)" }, /* adr size prefix */
304 { "pushS", Iv
}, /* 386 book wrong */
305 { "imulS", Gv
, Ev
, Iv
},
306 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
307 { "imulS", Gv
, Ev
, Ib
},
308 { "insb", Yb
, indirDX
},
309 { "insS", Yv
, indirDX
},
310 { "outsb", indirDX
, Xb
},
311 { "outsS", indirDX
, Xv
},
350 { "xchgS", eCX
, eAX
},
351 { "xchgS", eDX
, eAX
},
352 { "xchgS", eBX
, eAX
},
353 { "xchgS", eSP
, eAX
},
354 { "xchgS", eBP
, eAX
},
355 { "xchgS", eSI
, eAX
},
356 { "xchgS", eDI
, eAX
},
361 { "(bad)" }, /* fwait */
377 { "testS", eAX
, Iv
},
379 { "stosS", Yv
, eAX
},
381 { "lodsS", eAX
, Xv
},
383 { "scasS", eAX
, Xv
},
452 { "inb", AL
, indirDX
},
453 { "inS", eAX
, indirDX
},
454 { "outb", indirDX
, AL
},
455 { "outS", indirDX
, eAX
},
457 { "(bad)" }, /* lock prefix */
459 { "(bad)" }, /* repne */
460 { "(bad)" }, /* repz */
476 struct dis386 dis386_twobyte
[] = {
487 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
488 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
490 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
491 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
493 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
494 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
496 /* these are all backward in appendix A of the intel book */
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
507 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
510 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
513 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
516 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
519 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
522 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
525 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
528 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
530 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
531 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
533 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
534 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
536 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
537 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
579 { "shldS", Ev
, Gv
, Ib
},
580 { "shldS", Ev
, Gv
, CL
},
588 { "shrdS", Ev
, Gv
, Ib
},
589 { "shrdS", Ev
, Gv
, CL
},
595 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
597 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
598 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
599 { "movzbS", Gv
, Eb
},
600 { "movzwS", Gv
, Ew
},
608 { "movsbS", Gv
, Eb
},
609 { "movswS", Gv
, Ew
},
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
612 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
615 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
618 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
621 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
624 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
626 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
627 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
629 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
630 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
632 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
633 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
636 static char obuf
[100];
638 static char scratchbuf
[100];
639 static unsigned char *start_codep
;
640 static unsigned char *codep
;
644 static void oappend ();
646 static char *names32
[]={
647 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
649 static char *names16
[] = {
650 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
652 static char *names8
[] = {
653 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
655 static char *names_seg
[] = {
656 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
659 struct dis386 grps
[][8] = {
777 { "imulS", eAX
, Ev
},
779 { "idivS", eAX
, Ev
},
797 { "lcall", indirEv
},
838 #define PREFIX_REPZ 1
839 #define PREFIX_REPNZ 2
840 #define PREFIX_LOCK 4
842 #define PREFIX_SS 0x10
843 #define PREFIX_DS 0x20
844 #define PREFIX_ES 0x40
845 #define PREFIX_FS 0x80
846 #define PREFIX_GS 0x100
847 #define PREFIX_DATA 0x200
848 #define PREFIX_ADR 0x400
849 #define PREFIX_FWAIT 0x800
861 prefixes
|= PREFIX_REPZ
;
864 prefixes
|= PREFIX_REPNZ
;
867 prefixes
|= PREFIX_LOCK
;
870 prefixes
|= PREFIX_CS
;
873 prefixes
|= PREFIX_SS
;
876 prefixes
|= PREFIX_DS
;
879 prefixes
|= PREFIX_ES
;
882 prefixes
|= PREFIX_FS
;
885 prefixes
|= PREFIX_GS
;
888 prefixes
|= PREFIX_DATA
;
891 prefixes
|= PREFIX_ADR
;
894 prefixes
|= PREFIX_FWAIT
;
906 static char op1out
[100], op2out
[100], op3out
[100];
907 static int op_address
[3], op_ad
, op_index
[3];
912 * disassemble the first instruction in 'inbuf'. You have to make
913 * sure all of the bytes of the instruction are filled in.
914 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
915 * (see topic "Redundant prefixes" in the "Differences from 8086"
916 * section of the "Virtual 8086 Mode" chapter.)
917 * 'pc' should be the address of this instruction, it will
918 * be used to print the target address if this is a relative jump or call
919 * 'outbuf' gets filled in with the disassembled instruction. it should
920 * be long enough to hold the longest disassembled instruction.
921 * 100 bytes is certainly enough, unless symbol printing is added later
922 * The function returns the length of this instruction in bytes.
924 i386dis (pc
, inbuf
, stream
)
926 unsigned char *inbuf
;
932 int enter_instruction
;
933 char *first
, *second
, *third
;
941 op_index
[0] = op_index
[1] = op_index
[2] = -1;
950 enter_instruction
= 1;
952 enter_instruction
= 0;
956 if (prefixes
& PREFIX_REPZ
)
958 if (prefixes
& PREFIX_REPNZ
)
960 if (prefixes
& PREFIX_LOCK
)
963 if ((prefixes
& PREFIX_FWAIT
)
964 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
966 /* fwait not followed by floating point instruction */
967 fputs ("fwait", stream
);
971 /* these would be initialized to 0 if disassembling for 8086 or 286 */
975 if (prefixes
& PREFIX_DATA
)
978 if (prefixes
& PREFIX_ADR
)
985 dp
= &dis386_twobyte
[*++codep
];
987 dp
= &dis386
[*codep
];
989 mod
= (*codep
>> 6) & 3;
990 reg
= (*codep
>> 3) & 7;
993 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
999 if (dp
->name
== NULL
)
1000 dp
= &grps
[dp
->bytemode1
][reg
];
1007 (*dp
->op1
)(dp
->bytemode1
);
1012 (*dp
->op2
)(dp
->bytemode2
);
1017 (*dp
->op3
)(dp
->bytemode3
);
1020 obufp
= obuf
+ strlen (obuf
);
1021 for (i
= strlen (obuf
); i
< 6; i
++)
1024 fputs (obuf
, stream
);
1026 /* enter instruction is printed with operands in the
1027 * same order as the intel book; everything else
1028 * is printed in reverse order
1030 if (enter_instruction
)
1035 op_ad
= op_index
[0];
1036 op_index
[0] = op_index
[2];
1037 op_index
[2] = op_ad
;
1048 if (op_index
[0] != -1)
1049 print_address (op_address
[op_index
[0]], stream
);
1051 fputs (first
, stream
);
1057 fputs (",", stream
);
1058 if (op_index
[1] != -1)
1059 print_address (op_address
[op_index
[1]], stream
);
1061 fputs (second
, stream
);
1067 fputs (",", stream
);
1068 if (op_index
[2] != -1)
1069 print_address (op_address
[op_index
[2]], stream
);
1071 fputs (third
, stream
);
1073 return (codep
- inbuf
);
1076 char *float_mem
[] = {
1152 #define STi OP_STi, 0
1153 int OP_ST(), OP_STi();
1155 #define FGRPd9_2 NULL, NULL, 0
1156 #define FGRPd9_4 NULL, NULL, 1
1157 #define FGRPd9_5 NULL, NULL, 2
1158 #define FGRPd9_6 NULL, NULL, 3
1159 #define FGRPd9_7 NULL, NULL, 4
1160 #define FGRPda_5 NULL, NULL, 5
1161 #define FGRPdb_4 NULL, NULL, 6
1162 #define FGRPde_3 NULL, NULL, 7
1163 #define FGRPdf_4 NULL, NULL, 8
1165 struct dis386 float_reg
[][8] = {
1168 { "fadd", ST
, STi
},
1169 { "fmul", ST
, STi
},
1172 { "fsub", ST
, STi
},
1173 { "fsubr", ST
, STi
},
1174 { "fdiv", ST
, STi
},
1175 { "fdivr", ST
, STi
},
1212 { "fadd", STi
, ST
},
1213 { "fmul", STi
, ST
},
1216 { "fsub", STi
, ST
},
1217 { "fsubr", STi
, ST
},
1218 { "fdiv", STi
, ST
},
1219 { "fdivr", STi
, ST
},
1234 { "faddp", STi
, ST
},
1235 { "fmulp", STi
, ST
},
1238 { "fsubp", STi
, ST
},
1239 { "fsubrp", STi
, ST
},
1240 { "fdivp", STi
, ST
},
1241 { "fdivrp", STi
, ST
},
1257 char *fgrps
[][8] = {
1260 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1265 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1270 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1275 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1280 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1285 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1290 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1291 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1296 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1301 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1309 unsigned char floatop
;
1311 floatop
= codep
[-1];
1315 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1322 dp
= &float_reg
[floatop
- 0xd8][reg
];
1323 if (dp
->name
== NULL
)
1325 putop (fgrps
[dp
->bytemode1
][rm
]);
1326 /* instruction fnstsw is only one with strange arg */
1327 if (floatop
== 0xdf && *codep
== 0xe0)
1328 strcpy (op1out
, "%eax");
1335 (*dp
->op1
)(dp
->bytemode1
);
1338 (*dp
->op2
)(dp
->bytemode2
);
1351 sprintf (scratchbuf
, "%%st(%d)", rm
);
1352 oappend (scratchbuf
);
1356 /* capital letters in template are macros */
1362 for (p
= template; *p
; p
++)
1369 case 'C': /* For jcxz/jecxz */
1374 if ((prefixes
& PREFIX_FWAIT
) == 0)
1378 /* operand size flag */
1394 obufp
+= strlen (s
);
1400 if (prefixes
& PREFIX_CS
)
1402 if (prefixes
& PREFIX_DS
)
1404 if (prefixes
& PREFIX_SS
)
1406 if (prefixes
& PREFIX_ES
)
1408 if (prefixes
& PREFIX_FS
)
1410 if (prefixes
& PREFIX_GS
)
1414 OP_indirE (bytemode
)
1430 /* skip mod/rm byte */
1442 oappend (names8
[rm
]);
1445 oappend (names16
[rm
]);
1449 oappend (names32
[rm
]);
1451 oappend (names16
[rm
]);
1454 oappend ("<bad dis table>");
1465 scale
= (*codep
>> 6) & 3;
1466 index
= (*codep
>> 3) & 7;
1477 /* implies havesib and havebase */
1493 disp
= *(char *)codep
++;
1510 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1512 sprintf (scratchbuf
, "0x%x", disp
);
1513 oappend (scratchbuf
);
1516 if (havebase
|| havesib
)
1520 oappend (names32
[base
]);
1525 sprintf (scratchbuf
, ",%s", names32
[index
]);
1526 oappend (scratchbuf
);
1528 sprintf (scratchbuf
, ",%d", 1 << scale
);
1529 oappend (scratchbuf
);
1540 oappend (names8
[reg
]);
1543 oappend (names16
[reg
]);
1546 oappend (names32
[reg
]);
1550 oappend (names32
[reg
]);
1552 oappend (names16
[reg
]);
1555 oappend ("<internal disassembler error>");
1564 x
= *codep
++ & 0xff;
1565 x
|= (*codep
++ & 0xff) << 8;
1566 x
|= (*codep
++ & 0xff) << 16;
1567 x
|= (*codep
++ & 0xff) << 24;
1575 x
= *codep
++ & 0xff;
1576 x
|= (*codep
++ & 0xff) << 8;
1583 op_index
[op_ad
] = op_ad
;
1584 op_address
[op_ad
] = op
;
1593 case indir_dx_reg
: s
= "(%dx)"; break;
1594 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1595 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1596 s
= names16
[code
- ax_reg
];
1598 case es_reg
: case ss_reg
: case cs_reg
:
1599 case ds_reg
: case fs_reg
: case gs_reg
:
1600 s
= names_seg
[code
- es_reg
];
1602 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1603 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1604 s
= names8
[code
- al_reg
];
1606 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1607 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1609 s
= names32
[code
- eAX_reg
];
1611 s
= names16
[code
- eAX_reg
];
1614 s
= "<internal disassembler error>";
1627 op
= *codep
++ & 0xff;
1639 oappend ("<internal disassembler error>");
1642 sprintf (scratchbuf
, "$0x%x", op
);
1643 oappend (scratchbuf
);
1653 op
= *(char *)codep
++;
1659 op
= (short)get16();
1662 op
= (short)get16 ();
1665 oappend ("<internal disassembler error>");
1668 sprintf (scratchbuf
, "$0x%x", op
);
1669 oappend (scratchbuf
);
1680 disp
= *(char *)codep
++;
1687 disp
= (short)get16 ();
1688 /* for some reason, a data16 prefix on a jump instruction
1689 means that the pc is masked to 16 bits after the
1690 displacement is added! */
1695 oappend ("<internal disassembler error>");
1698 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1700 sprintf (scratchbuf
, "0x%x", disp
);
1701 oappend (scratchbuf
);
1707 static char *sreg
[] = {
1708 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1711 oappend (sreg
[reg
]);
1731 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1732 oappend (scratchbuf
);
1738 offset
= (short)get16 ();
1740 offset
= start_pc
+ codep
- start_codep
+ offset
;
1742 sprintf (scratchbuf
, "0x%x", offset
);
1743 oappend (scratchbuf
);
1746 oappend ("<internal disassembler error>");
1761 sprintf (scratchbuf
, "0x%x", off
);
1762 oappend (scratchbuf
);
1769 oappend (aflag
? "%edi" : "%di");
1777 oappend (aflag
? "%esi" : "%si");
1790 codep
++; /* skip mod/rm */
1791 sprintf (scratchbuf
, "%%cr%d", reg
);
1792 oappend (scratchbuf
);
1798 codep
++; /* skip mod/rm */
1799 sprintf (scratchbuf
, "%%db%d", reg
);
1800 oappend (scratchbuf
);
1806 codep
++; /* skip mod/rm */
1807 sprintf (scratchbuf
, "%%tr%d", reg
);
1808 oappend (scratchbuf
);
1816 oappend (names32
[rm
]);
1819 oappend (names16
[rm
]);
1826 print_insn (memaddr
, stream
)
1830 unsigned char buffer
[MAXLEN
];
1832 read_memory (memaddr
, buffer
, MAXLEN
);
1834 return (i386dis ((int)memaddr
, buffer
, stream
));
1840 print_insn_i386(memaddr
, buffer
, stream
)
1847 return (i386dis ((int)memaddr
, buffer
, stream
));
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