1 /* Disassemble i80960 instructions.
2 Copyright (C) 1990, 1991 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Diddler.
6 BFD is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 BFD is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with BFD; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 static char *reg_names
[] = {
25 /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
26 /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
27 /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
28 /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
29 /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
33 static FILE *stream
; /* Output goes here */
34 static void print_addr();
42 static void invalid();
44 static void put_abs();
47 /* Print the i960 instruction at address 'memaddr' in debugged memory,
48 * on stream 's'. Returns length of the instruction, in bytes.
51 print_insn_i960( memaddr
, buffer
, s
)
56 unsigned int word1
, word2
;
59 word1
=buffer
[0] |( buffer
[1]<< 8) | (buffer
[2] << 16) | ( buffer
[3] <<24);
60 word2
=buffer
[4] |( buffer
[5]<< 8) | (buffer
[6] << 16) | ( buffer
[7] <<24);
61 return pinsn( memaddr
, word1
, word2
);
66 /*****************************************************************************
67 * All code below this point should be identical with that of
68 * the disassembler in gdmp960.
69 *****************************************************************************/
77 pinsn( memaddr
, word1
, word2
)
78 unsigned long memaddr
;
79 unsigned long word1
, word2
;
84 put_abs( word1
, word2
);
86 /* Divide instruction set into classes based on high 4 bits of opcode*/
87 switch ( (word1
>> 28) & 0xf ){
90 ctrl( memaddr
, word1
, word2
);
94 cobr( memaddr
, word1
, word2
);
106 instr_len
= mem( memaddr
, word1
, word2
, 0 );
109 /* invalid instruction, print as data word */
116 /****************************************/
118 /****************************************/
120 ctrl( memaddr
, word1
, word2
)
121 unsigned long memaddr
;
122 unsigned long word1
, word2
;
125 static struct tabent ctrl_tab
[] = {
135 "call", 1, /* 0x09 */
150 "faultno", 0, /* 0x18 */
151 "faultg", 0, /* 0x19 */
152 "faulte", 0, /* 0x1a */
153 "faultge", 0, /* 0x1b */
154 "faultl", 0, /* 0x1c */
155 "faultne", 0, /* 0x1d */
156 "faultle", 0, /* 0x1e */
157 "faulto", 0, /* 0x1f */
160 i
= (word1
>> 24) & 0xff;
161 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
166 fputs( ctrl_tab
[i
].name
, stream
);
167 if ( word1
& 2 ){ /* Predicts branch not taken */
168 fputs( ".f", stream
);
171 if ( ctrl_tab
[i
].numops
== 1 ){
172 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
174 if ( word1
& 0x00800000 ){ /* Sign bit is set */
175 word1
|= (-1 & ~0xffffff); /* Sign extend */
177 putc( '\t', stream
);
178 print_addr( word1
+ memaddr
);
182 /****************************************/
184 /****************************************/
186 cobr( memaddr
, word1
, word2
)
187 unsigned long memaddr
;
188 unsigned long word1
, word2
;
194 static struct tabent cobr_tab
[] = {
195 "testno", 1, /* 0x20 */
196 "testg", 1, /* 0x21 */
197 "teste", 1, /* 0x22 */
198 "testge", 1, /* 0x23 */
199 "testl", 1, /* 0x24 */
200 "testne", 1, /* 0x25 */
201 "testle", 1, /* 0x26 */
202 "testo", 1, /* 0x27 */
212 "cmpobg", 3, /* 0x31 */
213 "cmpobe", 3, /* 0x32 */
214 "cmpobge", 3, /* 0x33 */
215 "cmpobl", 3, /* 0x34 */
216 "cmpobne", 3, /* 0x35 */
217 "cmpoble", 3, /* 0x36 */
219 "cmpibno", 3, /* 0x38 */
220 "cmpibg", 3, /* 0x39 */
221 "cmpibe", 3, /* 0x3a */
222 "cmpibge", 3, /* 0x3b */
223 "cmpibl", 3, /* 0x3c */
224 "cmpibne", 3, /* 0x3d */
225 "cmpible", 3, /* 0x3e */
226 "cmpibo", 3, /* 0x3f */
229 i
= ((word1
>> 24) & 0xff) - 0x20;
230 if ( cobr_tab
[i
].name
== NULL
){
235 fputs( cobr_tab
[i
].name
, stream
);
236 if ( word1
& 2 ){ /* Predicts branch not taken */
237 fputs( ".f", stream
);
239 putc( '\t', stream
);
241 src1
= (word1
>> 19) & 0x1f;
242 src2
= (word1
>> 14) & 0x1f;
244 if ( word1
& 0x02000 ){ /* M1 is 1 */
245 fprintf( stream
, "%d", src1
);
246 } else { /* M1 is 0 */
247 fputs( reg_names
[src1
], stream
);
250 if ( cobr_tab
[i
].numops
> 1 ){
251 if ( word1
& 1 ){ /* S2 is 1 */
252 fprintf( stream
, ",sf%d,", src2
);
253 } else { /* S1 is 0 */
254 fprintf( stream
, ",%s,", reg_names
[src2
] );
257 /* Extract displacement and convert to address
260 if ( word1
& 0x00001000 ){ /* Negative displacement */
261 word1
|= (-1 & ~0x1fff); /* Sign extend */
263 print_addr( memaddr
+ word1
);
267 /****************************************/
269 /****************************************/
270 static int /* returns instruction length: 4 or 8 */
271 mem( memaddr
, word1
, word2
, noprint
)
272 unsigned long memaddr
;
273 unsigned long word1
, word2
;
274 int noprint
; /* If TRUE, return instruction length, but
275 * don't output any text.
282 char *reg1
, *reg2
, *reg3
;
284 /* This lookup table is too sparse to make it worth typing in, but not
285 * so large as to make a sparse array necessary. We allocate the
286 * table at runtime, initialize all entries to empty, and copy the
287 * real ones in from an initialization table.
289 * NOTE: In this table, the meaning of 'numops' is:
291 * 2: 2 operands, load instruction
292 * -2: 2 operands, store instruction
294 static struct tabent
*mem_tab
= NULL
;
295 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
298 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
300 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
324 if ( mem_tab
== NULL
){
325 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
326 memset( (void *) mem_tab
, 0, MEM_SIZ
);
327 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
328 j
= mem_init
[i
].opcode
- MEM_MIN
;
329 mem_tab
[j
].name
= mem_init
[i
].name
;
330 mem_tab
[j
].numops
= mem_init
[i
].numops
;
334 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
335 mode
= (word1
>> 10) & 0xf;
337 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
338 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
348 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
353 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
355 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
356 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
357 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
358 offset
= word1
& 0xfff; /* MEMA only */
360 switch ( mem_tab
[i
].numops
){
362 case 2: /* LOAD INSTRUCTION */
363 if ( mode
& 4 ){ /* MEMB FORMAT */
364 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
365 fprintf( stream
, ",%s", reg1
);
366 } else { /* MEMA FORMAT */
367 fprintf( stream
, "0x%x", (unsigned) offset
);
369 fprintf( stream
, "(%s)", reg2
);
371 fprintf( stream
, ",%s", reg1
);
375 case -2: /* STORE INSTRUCTION */
376 if ( mode
& 4 ){ /* MEMB FORMAT */
377 fprintf( stream
, "%s,", reg1
);
378 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
379 } else { /* MEMA FORMAT */
380 fprintf( stream
, "%s,0x%x", reg1
, (unsigned) offset
);
382 fprintf( stream
, "(%s)", reg2
);
387 case 1: /* BX/CALLX INSTRUCTION */
388 if ( mode
& 4 ){ /* MEMB FORMAT */
389 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
390 } else { /* MEMA FORMAT */
391 fprintf( stream
, "0x%x", (unsigned) offset
);
393 fprintf( stream
, "(%s)", reg2
);
402 /****************************************/
404 /****************************************/
417 /* This lookup table is too sparse to make it worth typing in, but not
418 * so large as to make a sparse array necessary. We allocate the
419 * table at runtime, initialize all entries to empty, and copy the
420 * real ones in from an initialization table.
422 * NOTE: In this table, the meaning of 'numops' is:
423 * 1: single operand, which is NOT a destination.
424 * -1: single operand, which IS a destination.
425 * 2: 2 operands, the 2nd of which is NOT a destination.
426 * -2: 2 operands, the 2nd of which IS a destination.
429 * If an opcode mnemonic begins with "F", it is a floating-point
430 * opcode (the "F" is not printed).
433 static struct tabent
*reg_tab
= NULL
;
434 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
435 #define REG_MIN 0x580
450 0x58f, "alterbit", 3,
469 0x5ac, "scanbyte", 2,
486 0x613, "inspacc", -2,
492 0x640, "spanbit", -2,
493 0x641, "scanbit", -2,
498 0x646, "condrec", -2,
503 0x656, "receive", -2,
507 0x663, "sendserv", 1,
508 0x664, "resumprcs", 1,
509 0x665, "schedprcs", 1,
510 0x666, "saveprcs", 0,
511 0x668, "condwait", 1,
516 0x66d, "flushreg", 0,
522 0x675, "Fcvtilr", -2,
523 0x676, "Fscalerl", 3,
533 0x68a, "Flogbnr", -2,
534 0x68b, "Froundr", -2,
540 0x691, "Flogeprl", 3,
545 0x698, "Fsqrtrl", -2,
547 0x69a, "Flogbnrl", -2,
548 0x69b, "Froundrl", -2,
552 0x69f, "Fclassrl", 1,
554 0x6c1, "Fcvtril", -2,
555 0x6c2, "Fcvtzri", -2,
556 0x6c3, "Fcvtzril", -2,
561 0x6e3, "Fcpyrsre", 3,
577 #define REG_MAX 0x79f
578 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
582 if ( reg_tab
== NULL
){
583 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
584 memset( (void *) reg_tab
, 0, REG_SIZ
);
585 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
586 j
= reg_init
[i
].opcode
- REG_MIN
;
587 reg_tab
[j
].name
= reg_init
[i
].name
;
588 reg_tab
[j
].numops
= reg_init
[i
].numops
;
592 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
593 i
= opcode
- REG_MIN
;
595 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
600 mnemp
= reg_tab
[i
].name
;
601 if ( *mnemp
== 'F' ){
608 fputs( mnemp
, stream
);
610 s1
= (word1
>> 5) & 1;
611 s2
= (word1
>> 6) & 1;
612 m1
= (word1
>> 11) & 1;
613 m2
= (word1
>> 12) & 1;
614 m3
= (word1
>> 13) & 1;
616 src2
= (word1
>> 14) & 0x1f;
617 dst
= (word1
>> 19) & 0x1f;
619 if ( reg_tab
[i
].numops
!= 0 ){
620 putc( '\t', stream
);
622 switch ( reg_tab
[i
].numops
){
624 regop( m1
, s1
, src
, fp
);
627 dstop( m3
, dst
, fp
);
630 regop( m1
, s1
, src
, fp
);
632 regop( m2
, s2
, src2
, fp
);
635 regop( m1
, s1
, src
, fp
);
637 dstop( m3
, dst
, fp
);
640 regop( m1
, s1
, src
, fp
);
642 regop( m2
, s2
, src2
, fp
);
644 dstop( m3
, dst
, fp
);
652 * Print out effective address for memb instructions.
655 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
656 unsigned long memaddr
;
663 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
665 scale
= (word1
>> 7) & 0x07;
666 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
670 scale
= scale_tab
[scale
];
674 fprintf( stream
, "(%s)", reg2
);
676 case 5: /* displ+8(ip) */
677 print_addr( word2
+8+memaddr
);
679 case 7: /* (reg)[index*scale] */
681 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
683 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
686 case 12: /* displacement */
689 case 13: /* displ(reg) */
691 fprintf( stream
, "(%s)", reg2
);
693 case 14: /* displ[index*scale] */
696 fprintf( stream
, "[%s]", reg3
);
698 fprintf( stream
, "[%s*%d]", reg3
, scale
);
701 case 15: /* displ(reg)[index*scale] */
704 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
706 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
716 /************************************************/
717 /* Register Instruction Operand */
718 /************************************************/
720 regop( mode
, spec
, reg
, fp
)
721 int mode
, spec
, reg
, fp
;
723 if ( fp
){ /* FLOATING POINT INSTRUCTION */
724 if ( mode
== 1 ){ /* FP operand */
726 case 0: fputs( "fp0", stream
); break;
727 case 1: fputs( "fp1", stream
); break;
728 case 2: fputs( "fp2", stream
); break;
729 case 3: fputs( "fp3", stream
); break;
730 case 16: fputs( "0f0.0", stream
); break;
731 case 22: fputs( "0f1.0", stream
); break;
732 default: putc( '?', stream
); break;
734 } else { /* Non-FP register */
735 fputs( reg_names
[reg
], stream
);
737 } else { /* NOT FLOATING POINT */
738 if ( mode
== 1 ){ /* Literal */
739 fprintf( stream
, "%d", reg
);
740 } else { /* Register */
742 fputs( reg_names
[reg
], stream
);
744 fprintf( stream
, "sf%d", reg
);
750 /************************************************/
751 /* Register Instruction Destination Operand */
752 /************************************************/
754 dstop( mode
, reg
, fp
)
757 /* 'dst' operand can't be a literal. On non-FP instructions, register
758 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
759 * sf registers are not allowed so m3 acts normally.
762 regop( mode
, 0, reg
, fp
);
764 regop( 0, mode
, reg
, fp
);
773 fprintf( stream
, ".word\t0x%08x", (unsigned) word1
);
780 fprintf( stream
, "0x%x", (unsigned) a
);
784 put_abs( word1
, word2
)
785 unsigned long word1
, word2
;
792 switch ( (word1
>> 28) & 0xf ){
798 /* MEM format instruction */
799 len
= mem( 0, word1
, word2
, 1 );
807 fprintf( stream
, "%08x %08x\t", word1
, word2
);
809 fprintf( stream
, "%08x \t", word1
);
This page took 0.047975 seconds and 4 git commands to generate.