1 ; OpenRISC 1000 architecture. -*- Scheme -*-
2 ; Copyright 2000-2019 Free Software Foundation, Inc.
3 ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
4 ; Modified by Julius Baxter, juliusbaxter@gmail.com
5 ; Modified by Peter Gavin, pgavin@gmail.com
6 ; Modified by Andrey Bacherov, avbacherov@opencores.org
8 ; This program is free software; you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation; either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program; if not, see <http://www.gnu.org/licenses/>
21 (include "simplify.inc")
23 ; The OpenRISC family is a set of RISC microprocessor architectures with an
24 ; emphasis on scalability and is targetted at embedded use.
25 ; The CPU RTL development is a collaborative open source effort.
26 ; http://opencores.org/or1k
31 (comment "OpenRISC 1000")
32 (default-alignment aligned)
34 (machs or32 or32nd or64 or64nd)
38 ; Instruction set parameters.
42 ; Base insturction length. The insns are always 32 bits wide.
43 (base-insn-bitsize 32)
46 (define-pmacro OR32-MACHS or32,or32nd)
47 (define-pmacro OR64-MACHS or64,or64nd)
48 (define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
49 (define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
50 (define-pmacro ORFPX64-MACHS or64,or64nd)
51 (define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
57 (comment "does not have delay slots")
60 (if (keep-mach? (or32 or32nd))
64 (comment "OpenRISC 1000 32-bit CPU family")
73 (comment "Generic OpenRISC 1000 32-bit CPU")
80 (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
85 ; OpenRISC 1200 - 32-bit or1k CPU implementation
87 (name or1200) (comment "OpenRISC 1200 model")
90 (unit u-exec "Execution Unit" () 1 1 () () () ())
93 ; OpenRISC 1200 - 32-bit or1k CPU implementation
95 (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
98 (unit u-exec "Execution Unit" () 1 1 () () () ())
103 (if (keep-mach? (or64 or64nd))
107 (comment "OpenRISC 1000 64-bit CPU family")
111 (file-transform "64")
116 (comment "Generic OpenRISC 1000 64-bit CPU")
123 (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
125 (bfd-name "or1k64nd")
130 (include "or1kcommon.cpu")
131 (include "or1korbis.cpu")
132 (include "or1korfpx.cpu")