2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/delay.h>
26 ACPI_MODULE_NAME("acpi_lpss");
28 #ifdef CONFIG_X86_INTEL_LPSS
30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
32 #define LPSS_CLK_SIZE 0x04
33 #define LPSS_LTR_SIZE 0x18
35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
37 #define LPSS_RESETS 0x04
38 #define LPSS_RESETS_RESET_FUNC BIT(0)
39 #define LPSS_RESETS_RESET_APB BIT(1)
40 #define LPSS_GENERAL 0x08
41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
43 #define LPSS_SW_LTR 0x10
44 #define LPSS_AUTO_LTR 0x14
45 #define LPSS_LTR_SNOOP_REQ BIT(15)
46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47 #define LPSS_LTR_SNOOP_LAT_1US 0x800
48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51 #define LPSS_LTR_MAX_VAL 0x3FF
52 #define LPSS_TX_INT 0x20
53 #define LPSS_TX_INT_MASK BIT(1)
55 #define LPSS_PRV_REG_COUNT 9
58 #define LPSS_CLK BIT(0)
59 #define LPSS_CLK_GATE BIT(1)
60 #define LPSS_CLK_DIVIDER BIT(2)
61 #define LPSS_LTR BIT(3)
62 #define LPSS_SAVE_CTX BIT(4)
64 struct lpss_private_data
;
66 struct lpss_device_desc
{
68 unsigned int prv_offset
;
69 size_t prv_size_override
;
70 void (*setup
)(struct lpss_private_data
*pdata
);
73 static struct lpss_device_desc lpss_dma_desc
= {
77 struct lpss_private_data
{
78 void __iomem
*mmio_base
;
79 resource_size_t mmio_size
;
80 unsigned int fixed_clk_rate
;
82 const struct lpss_device_desc
*dev_desc
;
83 u32 prv_reg_ctx
[LPSS_PRV_REG_COUNT
];
86 /* UART Component Parameter Register */
87 #define LPSS_UART_CPR 0xF4
88 #define LPSS_UART_CPR_AFCE BIT(4)
90 static void lpss_uart_setup(struct lpss_private_data
*pdata
)
95 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_TX_INT
;
96 val
= readl(pdata
->mmio_base
+ offset
);
97 writel(val
| LPSS_TX_INT_MASK
, pdata
->mmio_base
+ offset
);
99 val
= readl(pdata
->mmio_base
+ LPSS_UART_CPR
);
100 if (!(val
& LPSS_UART_CPR_AFCE
)) {
101 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_GENERAL
;
102 val
= readl(pdata
->mmio_base
+ offset
);
103 val
|= LPSS_GENERAL_UART_RTS_OVRD
;
104 writel(val
, pdata
->mmio_base
+ offset
);
108 static void lpss_deassert_reset(struct lpss_private_data
*pdata
)
113 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_RESETS
;
114 val
= readl(pdata
->mmio_base
+ offset
);
115 val
|= LPSS_RESETS_RESET_APB
| LPSS_RESETS_RESET_FUNC
;
116 writel(val
, pdata
->mmio_base
+ offset
);
119 #define LPSS_I2C_ENABLE 0x6c
121 static void byt_i2c_setup(struct lpss_private_data
*pdata
)
123 lpss_deassert_reset(pdata
);
125 if (readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
))
126 pdata
->fixed_clk_rate
= 133000000;
128 writel(0, pdata
->mmio_base
+ LPSS_I2C_ENABLE
);
131 static struct lpss_device_desc lpt_dev_desc
= {
132 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
136 static struct lpss_device_desc lpt_i2c_dev_desc
= {
137 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_LTR
,
141 static struct lpss_device_desc lpt_uart_dev_desc
= {
142 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
144 .setup
= lpss_uart_setup
,
147 static struct lpss_device_desc lpt_sdio_dev_desc
= {
149 .prv_offset
= 0x1000,
150 .prv_size_override
= 0x1018,
153 static struct lpss_device_desc byt_pwm_dev_desc
= {
154 .flags
= LPSS_SAVE_CTX
,
157 static struct lpss_device_desc byt_uart_dev_desc
= {
158 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
160 .setup
= lpss_uart_setup
,
163 static struct lpss_device_desc byt_spi_dev_desc
= {
164 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
168 static struct lpss_device_desc byt_sdio_dev_desc
= {
172 static struct lpss_device_desc byt_i2c_dev_desc
= {
173 .flags
= LPSS_CLK
| LPSS_SAVE_CTX
,
175 .setup
= byt_i2c_setup
,
178 static struct lpss_device_desc bsw_spi_dev_desc
= {
179 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
181 .setup
= lpss_deassert_reset
,
186 #define LPSS_ADDR(desc) (0UL)
188 #endif /* CONFIG_X86_INTEL_LPSS */
190 static const struct acpi_device_id acpi_lpss_device_ids
[] = {
191 /* Generic LPSS devices */
192 { "INTL9C60", LPSS_ADDR(lpss_dma_desc
) },
194 /* Lynxpoint LPSS devices */
195 { "INT33C0", LPSS_ADDR(lpt_dev_desc
) },
196 { "INT33C1", LPSS_ADDR(lpt_dev_desc
) },
197 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc
) },
198 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc
) },
199 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc
) },
200 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc
) },
201 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc
) },
204 /* BayTrail LPSS devices */
205 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc
) },
206 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc
) },
207 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc
) },
208 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc
) },
209 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc
) },
213 /* Braswell LPSS devices */
214 { "80862288", LPSS_ADDR(byt_pwm_dev_desc
) },
215 { "8086228A", LPSS_ADDR(byt_uart_dev_desc
) },
216 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc
) },
217 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc
) },
219 { "INT3430", LPSS_ADDR(lpt_dev_desc
) },
220 { "INT3431", LPSS_ADDR(lpt_dev_desc
) },
221 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc
) },
222 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc
) },
223 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc
) },
224 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc
) },
225 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc
) },
228 /* Wildcat Point LPSS devices */
229 { "INT3438", LPSS_ADDR(lpt_dev_desc
) },
234 #ifdef CONFIG_X86_INTEL_LPSS
236 static int is_memory(struct acpi_resource
*res
, void *not_used
)
239 return !acpi_dev_resource_memory(res
, &r
);
242 /* LPSS main clock device. */
243 static struct platform_device
*lpss_clk_dev
;
245 static inline void lpt_register_clock_device(void)
247 lpss_clk_dev
= platform_device_register_simple("clk-lpt", -1, NULL
, 0);
250 static int register_device_clock(struct acpi_device
*adev
,
251 struct lpss_private_data
*pdata
)
253 const struct lpss_device_desc
*dev_desc
= pdata
->dev_desc
;
254 const char *devname
= dev_name(&adev
->dev
);
255 struct clk
*clk
= ERR_PTR(-ENODEV
);
256 struct lpss_clk_data
*clk_data
;
257 const char *parent
, *clk_name
;
258 void __iomem
*prv_base
;
261 lpt_register_clock_device();
263 clk_data
= platform_get_drvdata(lpss_clk_dev
);
268 if (!pdata
->mmio_base
269 || pdata
->mmio_size
< dev_desc
->prv_offset
+ LPSS_CLK_SIZE
)
272 parent
= clk_data
->name
;
273 prv_base
= pdata
->mmio_base
+ dev_desc
->prv_offset
;
275 if (pdata
->fixed_clk_rate
) {
276 clk
= clk_register_fixed_rate(NULL
, devname
, parent
, 0,
277 pdata
->fixed_clk_rate
);
281 if (dev_desc
->flags
& LPSS_CLK_GATE
) {
282 clk
= clk_register_gate(NULL
, devname
, parent
, 0,
283 prv_base
, 0, 0, NULL
);
287 if (dev_desc
->flags
& LPSS_CLK_DIVIDER
) {
288 /* Prevent division by zero */
289 if (!readl(prv_base
))
290 writel(LPSS_CLK_DIVIDER_DEF_MASK
, prv_base
);
292 clk_name
= kasprintf(GFP_KERNEL
, "%s-div", devname
);
295 clk
= clk_register_fractional_divider(NULL
, clk_name
, parent
,
297 1, 15, 16, 15, 0, NULL
);
300 clk_name
= kasprintf(GFP_KERNEL
, "%s-update", devname
);
305 clk
= clk_register_gate(NULL
, clk_name
, parent
,
306 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
,
307 prv_base
, 31, 0, NULL
);
316 clk_register_clkdev(clk
, NULL
, devname
);
320 static int acpi_lpss_create_device(struct acpi_device
*adev
,
321 const struct acpi_device_id
*id
)
323 struct lpss_device_desc
*dev_desc
;
324 struct lpss_private_data
*pdata
;
325 struct resource_entry
*rentry
;
326 struct list_head resource_list
;
327 struct platform_device
*pdev
;
330 dev_desc
= (struct lpss_device_desc
*)id
->driver_data
;
332 pdev
= acpi_create_platform_device(adev
);
333 return IS_ERR_OR_NULL(pdev
) ? PTR_ERR(pdev
) : 1;
335 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
339 INIT_LIST_HEAD(&resource_list
);
340 ret
= acpi_dev_get_resources(adev
, &resource_list
, is_memory
, NULL
);
344 list_for_each_entry(rentry
, &resource_list
, node
)
345 if (resource_type(rentry
->res
) == IORESOURCE_MEM
) {
346 if (dev_desc
->prv_size_override
)
347 pdata
->mmio_size
= dev_desc
->prv_size_override
;
349 pdata
->mmio_size
= resource_size(rentry
->res
);
350 pdata
->mmio_base
= ioremap(rentry
->res
->start
,
352 if (!pdata
->mmio_base
)
357 acpi_dev_free_resource_list(&resource_list
);
359 pdata
->dev_desc
= dev_desc
;
362 dev_desc
->setup(pdata
);
364 if (dev_desc
->flags
& LPSS_CLK
) {
365 ret
= register_device_clock(adev
, pdata
);
367 /* Skip the device, but continue the namespace scan. */
374 * This works around a known issue in ACPI tables where LPSS devices
375 * have _PS0 and _PS3 without _PSC (and no power resources), so
376 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
378 ret
= acpi_device_fix_up_power(adev
);
380 /* Skip the device, but continue the namespace scan. */
385 adev
->driver_data
= pdata
;
386 pdev
= acpi_create_platform_device(adev
);
387 if (!IS_ERR_OR_NULL(pdev
)) {
392 adev
->driver_data
= NULL
;
399 static u32
__lpss_reg_read(struct lpss_private_data
*pdata
, unsigned int reg
)
401 return readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
404 static void __lpss_reg_write(u32 val
, struct lpss_private_data
*pdata
,
407 writel(val
, pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
410 static int lpss_reg_read(struct device
*dev
, unsigned int reg
, u32
*val
)
412 struct acpi_device
*adev
;
413 struct lpss_private_data
*pdata
;
417 ret
= acpi_bus_get_device(ACPI_HANDLE(dev
), &adev
);
421 spin_lock_irqsave(&dev
->power
.lock
, flags
);
422 if (pm_runtime_suspended(dev
)) {
426 pdata
= acpi_driver_data(adev
);
427 if (WARN_ON(!pdata
|| !pdata
->mmio_base
)) {
431 *val
= __lpss_reg_read(pdata
, reg
);
434 spin_unlock_irqrestore(&dev
->power
.lock
, flags
);
438 static ssize_t
lpss_ltr_show(struct device
*dev
, struct device_attribute
*attr
,
445 reg
= strcmp(attr
->attr
.name
, "auto_ltr") ? LPSS_SW_LTR
: LPSS_AUTO_LTR
;
446 ret
= lpss_reg_read(dev
, reg
, <r_value
);
450 return snprintf(buf
, PAGE_SIZE
, "%08x\n", ltr_value
);
453 static ssize_t
lpss_ltr_mode_show(struct device
*dev
,
454 struct device_attribute
*attr
, char *buf
)
460 ret
= lpss_reg_read(dev
, LPSS_GENERAL
, <r_mode
);
464 outstr
= (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) ? "sw" : "auto";
465 return sprintf(buf
, "%s\n", outstr
);
468 static DEVICE_ATTR(auto_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
469 static DEVICE_ATTR(sw_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
470 static DEVICE_ATTR(ltr_mode
, S_IRUSR
, lpss_ltr_mode_show
, NULL
);
472 static struct attribute
*lpss_attrs
[] = {
473 &dev_attr_auto_ltr
.attr
,
474 &dev_attr_sw_ltr
.attr
,
475 &dev_attr_ltr_mode
.attr
,
479 static struct attribute_group lpss_attr_group
= {
484 static void acpi_lpss_set_ltr(struct device
*dev
, s32 val
)
486 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
487 u32 ltr_mode
, ltr_val
;
489 ltr_mode
= __lpss_reg_read(pdata
, LPSS_GENERAL
);
491 if (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) {
492 ltr_mode
&= ~LPSS_GENERAL_LTR_MODE_SW
;
493 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
497 ltr_val
= __lpss_reg_read(pdata
, LPSS_SW_LTR
) & ~LPSS_LTR_SNOOP_MASK
;
498 if (val
>= LPSS_LTR_SNOOP_LAT_CUTOFF
) {
499 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
;
500 val
= LPSS_LTR_MAX_VAL
;
501 } else if (val
> LPSS_LTR_MAX_VAL
) {
502 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
| LPSS_LTR_SNOOP_REQ
;
503 val
>>= LPSS_LTR_SNOOP_LAT_SHIFT
;
505 ltr_val
|= LPSS_LTR_SNOOP_LAT_1US
| LPSS_LTR_SNOOP_REQ
;
508 __lpss_reg_write(ltr_val
, pdata
, LPSS_SW_LTR
);
509 if (!(ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
)) {
510 ltr_mode
|= LPSS_GENERAL_LTR_MODE_SW
;
511 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
517 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
519 * @pdata: pointer to the private data of the LPSS device
521 * Most LPSS devices have private registers which may loose their context when
522 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
525 static void acpi_lpss_save_ctx(struct device
*dev
,
526 struct lpss_private_data
*pdata
)
530 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
531 unsigned long offset
= i
* sizeof(u32
);
533 pdata
->prv_reg_ctx
[i
] = __lpss_reg_read(pdata
, offset
);
534 dev_dbg(dev
, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
535 pdata
->prv_reg_ctx
[i
], offset
);
540 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
542 * @pdata: pointer to the private data of the LPSS device
544 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
546 static void acpi_lpss_restore_ctx(struct device
*dev
,
547 struct lpss_private_data
*pdata
)
552 * The following delay is needed or the subsequent write operations may
553 * fail. The LPSS devices are actually PCI devices and the PCI spec
554 * expects 10ms delay before the device can be accessed after D3 to D0
559 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
560 unsigned long offset
= i
* sizeof(u32
);
562 __lpss_reg_write(pdata
->prv_reg_ctx
[i
], pdata
, offset
);
563 dev_dbg(dev
, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
564 pdata
->prv_reg_ctx
[i
], offset
);
568 #ifdef CONFIG_PM_SLEEP
569 static int acpi_lpss_suspend_late(struct device
*dev
)
571 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
574 ret
= pm_generic_suspend_late(dev
);
578 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
579 acpi_lpss_save_ctx(dev
, pdata
);
581 return acpi_dev_suspend_late(dev
);
584 static int acpi_lpss_resume_early(struct device
*dev
)
586 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
589 ret
= acpi_dev_resume_early(dev
);
593 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
594 acpi_lpss_restore_ctx(dev
, pdata
);
596 return pm_generic_resume_early(dev
);
598 #endif /* CONFIG_PM_SLEEP */
600 static int acpi_lpss_runtime_suspend(struct device
*dev
)
602 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
605 ret
= pm_generic_runtime_suspend(dev
);
609 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
610 acpi_lpss_save_ctx(dev
, pdata
);
612 return acpi_dev_runtime_suspend(dev
);
615 static int acpi_lpss_runtime_resume(struct device
*dev
)
617 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
620 ret
= acpi_dev_runtime_resume(dev
);
624 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
625 acpi_lpss_restore_ctx(dev
, pdata
);
627 return pm_generic_runtime_resume(dev
);
629 #endif /* CONFIG_PM */
631 static struct dev_pm_domain acpi_lpss_pm_domain
= {
634 #ifdef CONFIG_PM_SLEEP
635 .prepare
= acpi_subsys_prepare
,
636 .complete
= acpi_subsys_complete
,
637 .suspend
= acpi_subsys_suspend
,
638 .suspend_late
= acpi_lpss_suspend_late
,
639 .resume_early
= acpi_lpss_resume_early
,
640 .freeze
= acpi_subsys_freeze
,
641 .poweroff
= acpi_subsys_suspend
,
642 .poweroff_late
= acpi_lpss_suspend_late
,
643 .restore_early
= acpi_lpss_resume_early
,
645 .runtime_suspend
= acpi_lpss_runtime_suspend
,
646 .runtime_resume
= acpi_lpss_runtime_resume
,
651 static int acpi_lpss_platform_notify(struct notifier_block
*nb
,
652 unsigned long action
, void *data
)
654 struct platform_device
*pdev
= to_platform_device(data
);
655 struct lpss_private_data
*pdata
;
656 struct acpi_device
*adev
;
657 const struct acpi_device_id
*id
;
659 id
= acpi_match_device(acpi_lpss_device_ids
, &pdev
->dev
);
660 if (!id
|| !id
->driver_data
)
663 if (acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
666 pdata
= acpi_driver_data(adev
);
670 if (pdata
->mmio_base
&&
671 pdata
->mmio_size
< pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
) {
672 dev_err(&pdev
->dev
, "MMIO size insufficient to access LTR\n");
677 case BUS_NOTIFY_ADD_DEVICE
:
678 pdev
->dev
.pm_domain
= &acpi_lpss_pm_domain
;
679 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
680 return sysfs_create_group(&pdev
->dev
.kobj
,
683 case BUS_NOTIFY_DEL_DEVICE
:
684 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
685 sysfs_remove_group(&pdev
->dev
.kobj
, &lpss_attr_group
);
686 pdev
->dev
.pm_domain
= NULL
;
695 static struct notifier_block acpi_lpss_nb
= {
696 .notifier_call
= acpi_lpss_platform_notify
,
699 static void acpi_lpss_bind(struct device
*dev
)
701 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
703 if (!pdata
|| !pdata
->mmio_base
|| !(pdata
->dev_desc
->flags
& LPSS_LTR
))
706 if (pdata
->mmio_size
>= pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
)
707 dev
->power
.set_latency_tolerance
= acpi_lpss_set_ltr
;
709 dev_err(dev
, "MMIO size insufficient to access LTR\n");
712 static void acpi_lpss_unbind(struct device
*dev
)
714 dev
->power
.set_latency_tolerance
= NULL
;
717 static struct acpi_scan_handler lpss_handler
= {
718 .ids
= acpi_lpss_device_ids
,
719 .attach
= acpi_lpss_create_device
,
720 .bind
= acpi_lpss_bind
,
721 .unbind
= acpi_lpss_unbind
,
724 void __init
acpi_lpss_init(void)
726 if (!lpt_clk_init()) {
727 bus_register_notifier(&platform_bus_type
, &acpi_lpss_nb
);
728 acpi_scan_add_handler(&lpss_handler
);
734 static struct acpi_scan_handler lpss_handler
= {
735 .ids
= acpi_lpss_device_ids
,
738 void __init
acpi_lpss_init(void)
740 acpi_scan_add_handler(&lpss_handler
);
743 #endif /* CONFIG_X86_INTEL_LPSS */